include/asm-arm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/config.h>
   7
   8 #define CPU_ARCH_UNKNOWN        0
   9 #define CPU_ARCH_ARMv3          1
  10 #define CPU_ARCH_ARMv4          2
  11 #define CPU_ARCH_ARMv4T         3
  12 #define CPU_ARCH_ARMv5          4
  13 #define CPU_ARCH_ARMv5T         5
  14 #define CPU_ARCH_ARMv5TE        6
  15 #define CPU_ARCH_ARMv5TEJ       7
  16 #define CPU_ARCH_ARMv6          8
  17
  18 /*
  19  * CR1 bits (CP#15 CR1)
  20  */
  21 #define CR_M    (1 << 0)        /* MMU enable                           */
  22 #define CR_A    (1 << 1)        /* Alignment abort enable               */
  23 #define CR_C    (1 << 2)        /* Dcache enable                        */
  24 #define CR_W    (1 << 3)        /* Write buffer enable                  */
  25 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
  26 #define CR_D    (1 << 5)        /* 32-bit data address range            */
  27 #define CR_L    (1 << 6)        /* Implementation defined               */
  28 #define CR_B    (1 << 7)        /* Big endian                           */
  29 #define CR_S    (1 << 8)        /* System MMU protection                */
  30 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
  31 #define CR_F    (1 << 10)       /* Implementation defined               */
  32 #define CR_Z    (1 << 11)       /* Implementation defined               */
  33 #define CR_I    (1 << 12)       /* Icache enable                        */
  34 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  35 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  36 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  37 #define CR_DT   (1 << 16)
  38 #define CR_IT   (1 << 18)
  39 #define CR_ST   (1 << 19)
  40 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  41 #define CR_U    (1 << 22)       /* Unaligned access operation           */
  42 #define CR_XP   (1 << 23)       /* Extended page tables                 */
  43 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  44
  45 #define CPUID_ID        0
  46 #define CPUID_CACHETYPE 1
  47 #define CPUID_TCM       2
  48 #define CPUID_TLBTYPE   3
  49
  50 #define read_cpuid(reg)                                                 \
  51         ({                                                              \
  52                 unsigned int __val;                                     \
  53                 asm("mrc%? p15, 0, %0, c0, c0, " __stringify(reg)       \
  54                     : "=r" (__val));                                    \
  55                 __val;                                                  \
  56         })
  57
  58 /*
  59  * This is used to ensure the compiler did actually allocate the register we
  60  * asked it for some inline assembly sequences.  Apparently we can't trust
  61  * the compiler from one version to another so a bit of paranoia won't hurt.
  62  * This string is meant to be concatenated with the inline asm string and
  63  * will cause compilation to stop on mismatch.
  64  */
  65 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  66
  67 #ifndef __ASSEMBLY__
  68
  69 #include <linux/kernel.h>
  70
  71 struct thread_info;
  72
  73 /* information about the system we're running on */
  74 extern unsigned int system_rev;
  75 extern unsigned int system_serial_low;
  76 extern unsigned int system_serial_high;
  77 extern unsigned int mem_fclk_21285;
  78
  79 struct pt_regs;
  80
  81 void die(const char *msg, struct pt_regs *regs, int err)
  82                 __attribute__((noreturn));
  83
  84 void die_if_kernel(const char *str, struct pt_regs *regs, int err);
  85
  86 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  87                                        struct pt_regs *),
  88                      int sig, const char *name);
  89
  90 #include <asm/proc-fns.h>
  91
  92 #define xchg(ptr,x) \
  93         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  94
  95 #define tas(ptr) (xchg((ptr),1))
  96
  97 extern asmlinkage void __backtrace(void);
  98
  99 extern int cpu_architecture(void);
 100
 101 #define set_cr(x)                                       \
 102         __asm__ __volatile__(                           \
 103         "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
 104         : : "r" (x) : "cc")
 105
 106 #define get_cr()                                        \
 107         ({                                              \
 108         unsigned int __val;                             \
 109         __asm__ __volatile__(                           \
 110         "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
 111         : "=r" (__val) : : "cc");                       \
 112         __val;                                          \
 113         })
 114
 115 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 116 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 117
 118 #define UDBG_UNDEFINED  (1 << 0)
 119 #define UDBG_SYSCALL    (1 << 1)
 120 #define UDBG_BADABORT   (1 << 2)
 121 #define UDBG_SEGV       (1 << 3)
 122 #define UDBG_BUS        (1 << 4)
 123
 124 extern unsigned int user_debug;
 125
 126 #if __LINUX_ARM_ARCH__ >= 4
 127 #define vectors_base()  ((cr_alignment & CR_V) ? 0xffff0000 : 0)
 128 #else
 129 #define vectors_base()  (0)
 130 #endif
 131
 132 #define mb() __asm__ __volatile__ ("" : : : "memory")
 133 #define rmb() mb()
 134 #define wmb() mb()
 135 #define read_barrier_depends() do { } while(0)
 136 #define set_mb(var, value)  do { var = value; mb(); } while (0)
 137 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 138 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 139
 140 #ifdef CONFIG_SMP
 141 /*
 142  * Define our own context switch locking.  This allows us to enable
 143  * interrupts over the context switch, otherwise we end up with high
 144  * interrupt latency.  The real problem area is switch_mm() which may
 145  * do a full cache flush.
 146  */
 147 #define prepare_arch_switch(rq,next)                                    \
 148 do {                                                                    \
 149         spin_lock(&(next)->switch_lock);                                \
 150         spin_unlock_irq(&(rq)->lock);                                   \
 151 } while (0)
 152
 153 #define finish_arch_switch(rq,prev)                                     \
 154         spin_unlock(&(prev)->switch_lock)
 155
 156 #define task_running(rq,p)                                              \
 157         ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
 158 #else
 159 /*
 160  * Our UP-case is more simple, but we assume knowledge of how
 161  * spin_unlock_irq() and friends are implemented.  This avoids
 162  * us needlessly decrementing and incrementing the preempt count.
 163  */
 164 #define prepare_arch_switch(rq,next)    local_irq_enable()
 165 #define finish_arch_switch(rq,prev)     spin_unlock(&(rq)->lock)
 166 #define task_running(rq,p)              ((rq)->curr == (p))
 167 #endif
 168
 169 /*
 170  * switch_to(prev, next) should switch from task `prev' to `next'
 171  * `prev' will never be the same as `next'.  schedule() itself
 172  * contains the memory barrier to tell GCC not to cache `current'.
 173  */
 174 struct thread_info;
 175 struct task_struct;
 176 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 177
 178 #define switch_to(prev,next,last)                                       \
 179 do {                                                                    \
 180         last = __switch_to(prev,prev->thread_info,next->thread_info);   \
 181 } while (0)
 182
 183 /*
 184  * CPU interrupt mask handling.
 185  */
 186 #if __LINUX_ARM_ARCH__ >= 6
 187
 188 #define local_irq_save(x)                                       \
 189         ({                                                      \
 190         __asm__ __volatile__(                                   \
 191         "mrs    %0, cpsr                @ local_irq_save\n"     \
 192         "cpsid  i"                                              \
 193         : "=r" (x) : : "memory", "cc");                         \
 194         })
 195
 196 #define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
 197 #define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
 198 #define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
 199 #define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
 200
 201 #else
 202
 203 /*
 204  * Save the current interrupt enable state & disable IRQs
 205  */
 206 #define local_irq_save(x)                                       \
 207         ({                                                      \
 208                 unsigned long temp;                             \
 209                 (void) (&temp == &x);                           \
 210         __asm__ __volatile__(                                   \
 211         "mrs    %0, cpsr                @ local_irq_save\n"     \
 212 "       orr     %1, %0, #128\n"                                 \
 213 "       msr     cpsr_c, %1"                                     \
 214         : "=r" (x), "=r" (temp)                                 \
 215         :                                                       \
 216         : "memory", "cc");                                      \
 217         })
 218
 219 /*
 220  * Enable IRQs
 221  */
 222 #define local_irq_enable()                                      \
 223         ({                                                      \
 224                 unsigned long temp;                             \
 225         __asm__ __volatile__(                                   \
 226         "mrs    %0, cpsr                @ local_irq_enable\n"   \
 227 "       bic     %0, %0, #128\n"                                 \
 228 "       msr     cpsr_c, %0"                                     \
 229         : "=r" (temp)                                           \
 230         :                                                       \
 231         : "memory", "cc");                                      \
 232         })
 233
 234 /*
 235  * Disable IRQs
 236  */
 237 #define local_irq_disable()                                     \
 238         ({                                                      \
 239                 unsigned long temp;                             \
 240         __asm__ __volatile__(                                   \
 241         "mrs    %0, cpsr                @ local_irq_disable\n"  \
 242 "       orr     %0, %0, #128\n"                                 \
 243 "       msr     cpsr_c, %0"                                     \
 244         : "=r" (temp)                                           \
 245         :                                                       \
 246         : "memory", "cc");                                      \
 247         })
 248
 249 /*
 250  * Enable FIQs
 251  */
 252 #define __stf()                                                 \
 253         ({                                                      \
 254                 unsigned long temp;                             \
 255         __asm__ __volatile__(                                   \
 256         "mrs    %0, cpsr                @ stf\n"                \
 257 "       bic     %0, %0, #64\n"                                  \
 258 "       msr     cpsr_c, %0"                                     \
 259         : "=r" (temp)                                           \
 260         :                                                       \
 261         : "memory", "cc");                                      \
 262         })
 263
 264 /*
 265  * Disable FIQs
 266  */
 267 #define __clf()                                                 \
 268         ({                                                      \
 269                 unsigned long temp;                             \
 270         __asm__ __volatile__(                                   \
 271         "mrs    %0, cpsr                @ clf\n"                \
 272 "       orr     %0, %0, #64\n"                                  \
 273 "       msr     cpsr_c, %0"                                     \
 274         : "=r" (temp)                                           \
 275         :                                                       \
 276         : "memory", "cc");                                      \
 277         })
 278
 279 #endif
 280
 281 /*
 282  * Save the current interrupt enable state.
 283  */
 284 #define local_save_flags(x)                                     \
 285         ({                                                      \
 286         __asm__ __volatile__(                                   \
 287         "mrs    %0, cpsr                @ local_save_flags"     \
 288         : "=r" (x) : : "memory", "cc");                         \
 289         })
 290
 291 /*
 292  * restore saved IRQ & FIQ state
 293  */
 294 #define local_irq_restore(x)                                    \
 295         __asm__ __volatile__(                                   \
 296         "msr    cpsr_c, %0              @ local_irq_restore\n"  \
 297         :                                                       \
 298         : "r" (x)                                               \
 299         : "memory", "cc")
 300
 301 #ifdef CONFIG_SMP
 302 #error SMP not supported
 303
 304 #define smp_mb()                mb()
 305 #define smp_rmb()               rmb()
 306 #define smp_wmb()               wmb()
 307 #define smp_read_barrier_depends()              read_barrier_depends()
 308
 309 #else
 310
 311 #define smp_mb()                barrier()
 312 #define smp_rmb()               barrier()
 313 #define smp_wmb()               barrier()
 314 #define smp_read_barrier_depends()              do { } while(0)
 315
 316 #define clf()                   __clf()
 317 #define stf()                   __stf()
 318
 319 #define irqs_disabled()                 \
 320 ({                                      \
 321         unsigned long flags;            \
 322         local_save_flags(flags);        \
 323         flags & PSR_I_BIT;              \
 324 })
 325
 326 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 327 /*
 328  * On the StrongARM, "swp" is terminally broken since it bypasses the
 329  * cache totally.  This means that the cache becomes inconsistent, and,
 330  * since we use normal loads/stores as well, this is really bad.
 331  * Typically, this causes oopsen in filp_close, but could have other,
 332  * more disasterous effects.  There are two work-arounds:
 333  *  1. Disable interrupts and emulate the atomic swap
 334  *  2. Clean the cache, perform atomic swap, flush the cache
 335  *
 336  * We choose (1) since its the "easiest" to achieve here and is not
 337  * dependent on the processor type.
 338  */
 339 #define swp_is_buggy
 340 #endif
 341
 342 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 343 {
 344         extern void __bad_xchg(volatile void *, int);
 345         unsigned long ret;
 346 #ifdef swp_is_buggy
 347         unsigned long flags;
 348 #endif
 349
 350         switch (size) {
 351 #ifdef swp_is_buggy
 352                 case 1:
 353                         local_irq_save(flags);
 354                         ret = *(volatile unsigned char *)ptr;
 355                         *(volatile unsigned char *)ptr = x;
 356                         local_irq_restore(flags);
 357                         break;
 358
 359                 case 4:
 360                         local_irq_save(flags);
 361                         ret = *(volatile unsigned long *)ptr;
 362                         *(volatile unsigned long *)ptr = x;
 363                         local_irq_restore(flags);
 364                         break;
 365 #else
 366                 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
 367                                         : "=&r" (ret)
 368                                         : "r" (x), "r" (ptr)
 369                                         : "memory", "cc");
 370                         break;
 371                 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
 372                                         : "=&r" (ret)
 373                                         : "r" (x), "r" (ptr)
 374                                         : "memory", "cc");
 375                         break;
 376 #endif
 377                 default: __bad_xchg(ptr, size), ret = 0;
 378         }
 379
 380         return ret;
 381 }
 382
 383 #endif /* CONFIG_SMP */
 384
 385 #endif /* __ASSEMBLY__ */
 386
 387 #endif /* __KERNEL__ */
 388
 389 #endif