include/asm-i386/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define         APIC_LVR        0x30
  15 #define                 APIC_LVR_MASK           0xFF00FF
  16 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  17 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  18 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  19 #define                 APIC_XAPIC(x)           ((x) >= 0x14)
  20 #define         APIC_TASKPRI    0x80
  21 #define                 APIC_TPRI_MASK          0xFF
  22 #define         APIC_ARBPRI     0x90
  23 #define                 APIC_ARBPRI_MASK        0xFF
  24 #define         APIC_PROCPRI    0xA0
  25 #define         APIC_EOI        0xB0
  26 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  27 #define         APIC_RRR        0xC0
  28 #define         APIC_LDR        0xD0
  29 #define                 APIC_LDR_MASK           (0xFF<<24)
  30 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  31 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  32 #define                 APIC_ALL_CPUS           0xFF
  33 #define         APIC_DFR        0xE0
  34 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  35 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  36 #define         APIC_SPIV       0xF0
  37 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  38 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  39 #define         APIC_ISR        0x100
  40 #define         APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
  41 #define         APIC_TMR        0x180
  42 #define         APIC_IRR        0x200
  43 #define         APIC_ESR        0x280
  44 #define                 APIC_ESR_SEND_CS        0x00001
  45 #define                 APIC_ESR_RECV_CS        0x00002
  46 #define                 APIC_ESR_SEND_ACC       0x00004
  47 #define                 APIC_ESR_RECV_ACC       0x00008
  48 #define                 APIC_ESR_SENDILL        0x00020
  49 #define                 APIC_ESR_RECVILL        0x00040
  50 #define                 APIC_ESR_ILLREGA        0x00080
  51 #define         APIC_ICR        0x300
  52 #define                 APIC_DEST_SELF          0x40000
  53 #define                 APIC_DEST_ALLINC        0x80000
  54 #define                 APIC_DEST_ALLBUT        0xC0000
  55 #define                 APIC_ICR_RR_MASK        0x30000
  56 #define                 APIC_ICR_RR_INVALID     0x00000
  57 #define                 APIC_ICR_RR_INPROG      0x10000
  58 #define                 APIC_ICR_RR_VALID       0x20000
  59 #define                 APIC_INT_LEVELTRIG      0x08000
  60 #define                 APIC_INT_ASSERT         0x04000
  61 #define                 APIC_ICR_BUSY           0x01000
  62 #define                 APIC_DEST_LOGICAL       0x00800
  63 #define                 APIC_DM_FIXED           0x00000
  64 #define                 APIC_DM_LOWEST          0x00100
  65 #define                 APIC_DM_SMI             0x00200
  66 #define                 APIC_DM_REMRD           0x00300
  67 #define                 APIC_DM_NMI             0x00400
  68 #define                 APIC_DM_INIT            0x00500
  69 #define                 APIC_DM_STARTUP         0x00600
  70 #define                 APIC_DM_EXTINT          0x00700
  71 #define                 APIC_VECTOR_MASK        0x000FF
  72 #define         APIC_ICR2       0x310
  73 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  74 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  75 #define         APIC_LVTT       0x320
  76 #define         APIC_LVTTHMR    0x330
  77 #define         APIC_LVTPC      0x340
  78 #define         APIC_LVT0       0x350
  79 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  80 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  81 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  82 #define                 APIC_TIMER_BASE_CLKIN           0x0
  83 #define                 APIC_TIMER_BASE_TMBASE          0x1
  84 #define                 APIC_TIMER_BASE_DIV             0x2
  85 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  86 #define                 APIC_LVT_MASKED                 (1<<16)
  87 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  88 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  89 #define                 APIC_INPUT_POLARITY             (1<<13)
  90 #define                 APIC_SEND_PENDING               (1<<12)
  91 #define                 APIC_MODE_MASK                  0x700
  92 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  93 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  94 #define                         APIC_MODE_FIXED         0x0
  95 #define                         APIC_MODE_NMI           0x4
  96 #define                         APIC_MODE_EXTINT        0x7
  97 #define         APIC_LVT1       0x360
  98 #define         APIC_LVTERR     0x370
  99 #define         APIC_TMICT      0x380
 100 #define         APIC_TMCCT      0x390
 101 #define         APIC_TDCR       0x3E0
 102 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 103 #define                 APIC_TDR_DIV_1          0xB
 104 #define                 APIC_TDR_DIV_2          0x0
 105 #define                 APIC_TDR_DIV_4          0x1
 106 #define                 APIC_TDR_DIV_8          0x2
 107 #define                 APIC_TDR_DIV_16         0x3
 108 #define                 APIC_TDR_DIV_32         0x8
 109 #define                 APIC_TDR_DIV_64         0x9
 110 #define                 APIC_TDR_DIV_128        0xA
 111
 112 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 113
 114 #define MAX_IO_APICS 64
 115
 116 /*
 117  * the local APIC register structure, memory mapped. Not terribly well
 118  * tested, but we might eventually use this one in the future - the
 119  * problem why we cannot use it right now is the P5 APIC, it has an
 120  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 121  */
 122 #define u32 unsigned int
 123
 124 #define lapic ((volatile struct local_apic *)APIC_BASE)
 125
 126 struct local_apic {
 127
 128 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 129
 130 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 131
 132 /*020*/ struct { /* APIC ID Register */
 133                 u32   __reserved_1      : 24,
 134                         phys_apic_id    :  4,
 135                         __reserved_2    :  4;
 136                 u32 __reserved[3];
 137         } id;
 138
 139 /*030*/ const
 140         struct { /* APIC Version Register */
 141                 u32   version           :  8,
 142                         __reserved_1    :  8,
 143                         max_lvt         :  8,
 144                         __reserved_2    :  8;
 145                 u32 __reserved[3];
 146         } version;
 147
 148 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 149
 150 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 151
 152 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 153
 154 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 155
 156 /*080*/ struct { /* Task Priority Register */
 157                 u32   priority  :  8,
 158                         __reserved_1    : 24;
 159                 u32 __reserved_2[3];
 160         } tpr;
 161
 162 /*090*/ const
 163         struct { /* Arbitration Priority Register */
 164                 u32   priority  :  8,
 165                         __reserved_1    : 24;
 166                 u32 __reserved_2[3];
 167         } apr;
 168
 169 /*0A0*/ const
 170         struct { /* Processor Priority Register */
 171                 u32   priority  :  8,
 172                         __reserved_1    : 24;
 173                 u32 __reserved_2[3];
 174         } ppr;
 175
 176 /*0B0*/ struct { /* End Of Interrupt Register */
 177                 u32   eoi;
 178                 u32 __reserved[3];
 179         } eoi;
 180
 181 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 182
 183 /*0D0*/ struct { /* Logical Destination Register */
 184                 u32   __reserved_1      : 24,
 185                         logical_dest    :  8;
 186                 u32 __reserved_2[3];
 187         } ldr;
 188
 189 /*0E0*/ struct { /* Destination Format Register */
 190                 u32   __reserved_1      : 28,
 191                         model           :  4;
 192                 u32 __reserved_2[3];
 193         } dfr;
 194
 195 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 196                 u32     spurious_vector :  8,
 197                         apic_enabled    :  1,
 198                         focus_cpu       :  1,
 199                         __reserved_2    : 22;
 200                 u32 __reserved_3[3];
 201         } svr;
 202
 203 /*100*/ struct { /* In Service Register */
 204 /*170*/         u32 bitfield;
 205                 u32 __reserved[3];
 206         } isr [8];
 207
 208 /*180*/ struct { /* Trigger Mode Register */
 209 /*1F0*/         u32 bitfield;
 210                 u32 __reserved[3];
 211         } tmr [8];
 212
 213 /*200*/ struct { /* Interrupt Request Register */
 214 /*270*/         u32 bitfield;
 215                 u32 __reserved[3];
 216         } irr [8];
 217
 218 /*280*/ union { /* Error Status Register */
 219                 struct {
 220                         u32   send_cs_error                     :  1,
 221                                 receive_cs_error                :  1,
 222                                 send_accept_error               :  1,
 223                                 receive_accept_error            :  1,
 224                                 __reserved_1                    :  1,
 225                                 send_illegal_vector             :  1,
 226                                 receive_illegal_vector          :  1,
 227                                 illegal_register_address        :  1,
 228                                 __reserved_2                    : 24;
 229                         u32 __reserved_3[3];
 230                 } error_bits;
 231                 struct {
 232                         u32 errors;
 233                         u32 __reserved_3[3];
 234                 } all_errors;
 235         } esr;
 236
 237 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 238
 239 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 240
 241 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 242
 243 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 244
 245 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 246
 247 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 248
 249 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 250
 251 /*300*/ struct { /* Interrupt Command Register 1 */
 252                 u32   vector                    :  8,
 253                         delivery_mode           :  3,
 254                         destination_mode        :  1,
 255                         delivery_status         :  1,
 256                         __reserved_1            :  1,
 257                         level                   :  1,
 258                         trigger                 :  1,
 259                         __reserved_2            :  2,
 260                         shorthand               :  2,
 261                         __reserved_3            :  12;
 262                 u32 __reserved_4[3];
 263         } icr1;
 264
 265 /*310*/ struct { /* Interrupt Command Register 2 */
 266                 union {
 267                         u32   __reserved_1      : 24,
 268                                 phys_dest       :  4,
 269                                 __reserved_2    :  4;
 270                         u32   __reserved_3      : 24,
 271                                 logical_dest    :  8;
 272                 } dest;
 273                 u32 __reserved_4[3];
 274         } icr2;
 275
 276 /*320*/ struct { /* LVT - Timer */
 277                 u32   vector            :  8,
 278                         __reserved_1    :  4,
 279                         delivery_status :  1,
 280                         __reserved_2    :  3,
 281                         mask            :  1,
 282                         timer_mode      :  1,
 283                         __reserved_3    : 14;
 284                 u32 __reserved_4[3];
 285         } lvt_timer;
 286
 287 /*330*/ struct { /* LVT - Thermal Sensor */
 288                 u32  vector             :  8,
 289                         delivery_mode   :  3,
 290                         __reserved_1    :  1,
 291                         delivery_status :  1,
 292                         __reserved_2    :  3,
 293                         mask            :  1,
 294                         __reserved_3    : 15;
 295                 u32 __reserved_4[3];
 296         } lvt_thermal;
 297
 298 /*340*/ struct { /* LVT - Performance Counter */
 299                 u32   vector            :  8,
 300                         delivery_mode   :  3,
 301                         __reserved_1    :  1,
 302                         delivery_status :  1,
 303                         __reserved_2    :  3,
 304                         mask            :  1,
 305                         __reserved_3    : 15;
 306                 u32 __reserved_4[3];
 307         } lvt_pc;
 308
 309 /*350*/ struct { /* LVT - LINT0 */
 310                 u32   vector            :  8,
 311                         delivery_mode   :  3,
 312                         __reserved_1    :  1,
 313                         delivery_status :  1,
 314                         polarity        :  1,
 315                         remote_irr      :  1,
 316                         trigger         :  1,
 317                         mask            :  1,
 318                         __reserved_2    : 15;
 319                 u32 __reserved_3[3];
 320         } lvt_lint0;
 321
 322 /*360*/ struct { /* LVT - LINT1 */
 323                 u32   vector            :  8,
 324                         delivery_mode   :  3,
 325                         __reserved_1    :  1,
 326                         delivery_status :  1,
 327                         polarity        :  1,
 328                         remote_irr      :  1,
 329                         trigger         :  1,
 330                         mask            :  1,
 331                         __reserved_2    : 15;
 332                 u32 __reserved_3[3];
 333         } lvt_lint1;
 334
 335 /*370*/ struct { /* LVT - Error */
 336                 u32   vector            :  8,
 337                         __reserved_1    :  4,
 338                         delivery_status :  1,
 339                         __reserved_2    :  3,
 340                         mask            :  1,
 341                         __reserved_3    : 15;
 342                 u32 __reserved_4[3];
 343         } lvt_error;
 344
 345 /*380*/ struct { /* Timer Initial Count Register */
 346                 u32   initial_count;
 347                 u32 __reserved_2[3];
 348         } timer_icr;
 349
 350 /*390*/ const
 351         struct { /* Timer Current Count Register */
 352                 u32   curr_count;
 353                 u32 __reserved_2[3];
 354         } timer_ccr;
 355
 356 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 357
 358 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 359
 360 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 361
 362 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 363
 364 /*3E0*/ struct { /* Timer Divide Configuration Register */
 365                 u32   divisor           :  4,
 366                         __reserved_1    : 28;
 367                 u32 __reserved_2[3];
 368         } timer_dcr;
 369
 370 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 371
 372 } __attribute__ ((packed));
 373
 374 #undef u32
 375
 376 #endif