include/asm-i386/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define         APIC_LVR        0x30
  15 #define                 APIC_LVR_MASK           0xFF00FF
  16 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  17 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  18 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  19 #define         APIC_TASKPRI    0x80
  20 #define                 APIC_TPRI_MASK          0xFF
  21 #define         APIC_ARBPRI     0x90
  22 #define                 APIC_ARBPRI_MASK        0xFF
  23 #define         APIC_PROCPRI    0xA0
  24 #define         APIC_EOI        0xB0
  25 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  26 #define         APIC_RRR        0xC0
  27 #define         APIC_LDR        0xD0
  28 #define                 APIC_LDR_MASK           (0xFF<<24)
  29 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  30 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  31 #define                 APIC_ALL_CPUS           0xFF
  32 #define         APIC_DFR        0xE0
  33 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  34 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  35 #define         APIC_SPIV       0xF0
  36 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  37 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  38 #define         APIC_ISR        0x100
  39 #define         APIC_TMR        0x180
  40 #define         APIC_IRR        0x200
  41 #define         APIC_ESR        0x280
  42 #define                 APIC_ESR_SEND_CS        0x00001
  43 #define                 APIC_ESR_RECV_CS        0x00002
  44 #define                 APIC_ESR_SEND_ACC       0x00004
  45 #define                 APIC_ESR_RECV_ACC       0x00008
  46 #define                 APIC_ESR_SENDILL        0x00020
  47 #define                 APIC_ESR_RECVILL        0x00040
  48 #define                 APIC_ESR_ILLREGA        0x00080
  49 #define         APIC_ICR        0x300
  50 #define                 APIC_DEST_SELF          0x40000
  51 #define                 APIC_DEST_ALLINC        0x80000
  52 #define                 APIC_DEST_ALLBUT        0xC0000
  53 #define                 APIC_ICR_RR_MASK        0x30000
  54 #define                 APIC_ICR_RR_INVALID     0x00000
  55 #define                 APIC_ICR_RR_INPROG      0x10000
  56 #define                 APIC_ICR_RR_VALID       0x20000
  57 #define                 APIC_INT_LEVELTRIG      0x08000
  58 #define                 APIC_INT_ASSERT         0x04000
  59 #define                 APIC_ICR_BUSY           0x01000
  60 #define                 APIC_DEST_LOGICAL       0x00800
  61 #define                 APIC_DM_FIXED           0x00000
  62 #define                 APIC_DM_LOWEST          0x00100
  63 #define                 APIC_DM_SMI             0x00200
  64 #define                 APIC_DM_REMRD           0x00300
  65 #define                 APIC_DM_NMI             0x00400
  66 #define                 APIC_DM_INIT            0x00500
  67 #define                 APIC_DM_STARTUP         0x00600
  68 #define                 APIC_DM_EXTINT          0x00700
  69 #define                 APIC_VECTOR_MASK        0x000FF
  70 #define         APIC_ICR2       0x310
  71 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  72 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  73 #define         APIC_LVTT       0x320
  74 #define         APIC_LVTTHMR    0x330
  75 #define         APIC_LVTPC      0x340
  76 #define         APIC_LVT0       0x350
  77 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  78 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  79 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  80 #define                 APIC_TIMER_BASE_CLKIN           0x0
  81 #define                 APIC_TIMER_BASE_TMBASE          0x1
  82 #define                 APIC_TIMER_BASE_DIV             0x2
  83 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  84 #define                 APIC_LVT_MASKED                 (1<<16)
  85 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  86 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  87 #define                 APIC_INPUT_POLARITY             (1<<13)
  88 #define                 APIC_SEND_PENDING               (1<<12)
  89 #define                 APIC_MODE_MASK                  0x700
  90 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  91 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  92 #define                         APIC_MODE_FIXED         0x0
  93 #define                         APIC_MODE_NMI           0x4
  94 #define                         APIC_MODE_EXINT         0x7
  95 #define         APIC_LVT1       0x360
  96 #define         APIC_LVTERR     0x370
  97 #define         APIC_TMICT      0x380
  98 #define         APIC_TMCCT      0x390
  99 #define         APIC_TDCR       0x3E0
 100 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 101 #define                 APIC_TDR_DIV_1          0xB
 102 #define                 APIC_TDR_DIV_2          0x0
 103 #define                 APIC_TDR_DIV_4          0x1
 104 #define                 APIC_TDR_DIV_8          0x2
 105 #define                 APIC_TDR_DIV_16         0x3
 106 #define                 APIC_TDR_DIV_32         0x8
 107 #define                 APIC_TDR_DIV_64         0x9
 108 #define                 APIC_TDR_DIV_128        0xA
 109
 110 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 111
 112 #ifdef CONFIG_NUMA
 113  #define MAX_IO_APICS 32
 114 #else
 115  #define MAX_IO_APICS 8
 116 #endif
 117
 118 /*
 119  * the local APIC register structure, memory mapped. Not terribly well
 120  * tested, but we might eventually use this one in the future - the
 121  * problem why we cannot use it right now is the P5 APIC, it has an
 122  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 123  */
 124 #define u32 unsigned int
 125
 126 #define lapic ((volatile struct local_apic *)APIC_BASE)
 127
 128 struct local_apic {
 129
 130 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 131
 132 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 133
 134 /*020*/ struct { /* APIC ID Register */
 135                 u32   __reserved_1      : 24,
 136                         phys_apic_id    :  4,
 137                         __reserved_2    :  4;
 138                 u32 __reserved[3];
 139         } id;
 140
 141 /*030*/ const
 142         struct { /* APIC Version Register */
 143                 u32   version           :  8,
 144                         __reserved_1    :  8,
 145                         max_lvt         :  8,
 146                         __reserved_2    :  8;
 147                 u32 __reserved[3];
 148         } version;
 149
 150 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 151
 152 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 153
 154 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 155
 156 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 157
 158 /*080*/ struct { /* Task Priority Register */
 159                 u32   priority  :  8,
 160                         __reserved_1    : 24;
 161                 u32 __reserved_2[3];
 162         } tpr;
 163
 164 /*090*/ const
 165         struct { /* Arbitration Priority Register */
 166                 u32   priority  :  8,
 167                         __reserved_1    : 24;
 168                 u32 __reserved_2[3];
 169         } apr;
 170
 171 /*0A0*/ const
 172         struct { /* Processor Priority Register */
 173                 u32   priority  :  8,
 174                         __reserved_1    : 24;
 175                 u32 __reserved_2[3];
 176         } ppr;
 177
 178 /*0B0*/ struct { /* End Of Interrupt Register */
 179                 u32   eoi;
 180                 u32 __reserved[3];
 181         } eoi;
 182
 183 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 184
 185 /*0D0*/ struct { /* Logical Destination Register */
 186                 u32   __reserved_1      : 24,
 187                         logical_dest    :  8;
 188                 u32 __reserved_2[3];
 189         } ldr;
 190
 191 /*0E0*/ struct { /* Destination Format Register */
 192                 u32   __reserved_1      : 28,
 193                         model           :  4;
 194                 u32 __reserved_2[3];
 195         } dfr;
 196
 197 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 198                 u32     spurious_vector :  8,
 199                         apic_enabled    :  1,
 200                         focus_cpu       :  1,
 201                         __reserved_2    : 22;
 202                 u32 __reserved_3[3];
 203         } svr;
 204
 205 /*100*/ struct { /* In Service Register */
 206 /*170*/         u32 bitfield;
 207                 u32 __reserved[3];
 208         } isr [8];
 209
 210 /*180*/ struct { /* Trigger Mode Register */
 211 /*1F0*/         u32 bitfield;
 212                 u32 __reserved[3];
 213         } tmr [8];
 214
 215 /*200*/ struct { /* Interrupt Request Register */
 216 /*270*/         u32 bitfield;
 217                 u32 __reserved[3];
 218         } irr [8];
 219
 220 /*280*/ union { /* Error Status Register */
 221                 struct {
 222                         u32   send_cs_error                     :  1,
 223                                 receive_cs_error                :  1,
 224                                 send_accept_error               :  1,
 225                                 receive_accept_error            :  1,
 226                                 __reserved_1                    :  1,
 227                                 send_illegal_vector             :  1,
 228                                 receive_illegal_vector          :  1,
 229                                 illegal_register_address        :  1,
 230                                 __reserved_2                    : 24;
 231                         u32 __reserved_3[3];
 232                 } error_bits;
 233                 struct {
 234                         u32 errors;
 235                         u32 __reserved_3[3];
 236                 } all_errors;
 237         } esr;
 238
 239 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 240
 241 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 242
 243 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 244
 245 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 246
 247 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 248
 249 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 250
 251 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 252
 253 /*300*/ struct { /* Interrupt Command Register 1 */
 254                 u32   vector                    :  8,
 255                         delivery_mode           :  3,
 256                         destination_mode        :  1,
 257                         delivery_status         :  1,
 258                         __reserved_1            :  1,
 259                         level                   :  1,
 260                         trigger                 :  1,
 261                         __reserved_2            :  2,
 262                         shorthand               :  2,
 263                         __reserved_3            :  12;
 264                 u32 __reserved_4[3];
 265         } icr1;
 266
 267 /*310*/ struct { /* Interrupt Command Register 2 */
 268                 union {
 269                         u32   __reserved_1      : 24,
 270                                 phys_dest       :  4,
 271                                 __reserved_2    :  4;
 272                         u32   __reserved_3      : 24,
 273                                 logical_dest    :  8;
 274                 } dest;
 275                 u32 __reserved_4[3];
 276         } icr2;
 277
 278 /*320*/ struct { /* LVT - Timer */
 279                 u32   vector            :  8,
 280                         __reserved_1    :  4,
 281                         delivery_status :  1,
 282                         __reserved_2    :  3,
 283                         mask            :  1,
 284                         timer_mode      :  1,
 285                         __reserved_3    : 14;
 286                 u32 __reserved_4[3];
 287         } lvt_timer;
 288
 289 /*330*/ struct { /* LVT - Thermal Sensor */
 290                 u32  vector             :  8,
 291                         delivery_mode   :  3,
 292                         __reserved_1    :  1,
 293                         delivery_status :  1,
 294                         __reserved_2    :  3,
 295                         mask            :  1,
 296                         __reserved_3    : 15;
 297                 u32 __reserved_4[3];
 298         } lvt_thermal;
 299
 300 /*340*/ struct { /* LVT - Performance Counter */
 301                 u32   vector            :  8,
 302                         delivery_mode   :  3,
 303                         __reserved_1    :  1,
 304                         delivery_status :  1,
 305                         __reserved_2    :  3,
 306                         mask            :  1,
 307                         __reserved_3    : 15;
 308                 u32 __reserved_4[3];
 309         } lvt_pc;
 310
 311 /*350*/ struct { /* LVT - LINT0 */
 312                 u32   vector            :  8,
 313                         delivery_mode   :  3,
 314                         __reserved_1    :  1,
 315                         delivery_status :  1,
 316                         polarity        :  1,
 317                         remote_irr      :  1,
 318                         trigger         :  1,
 319                         mask            :  1,
 320                         __reserved_2    : 15;
 321                 u32 __reserved_3[3];
 322         } lvt_lint0;
 323
 324 /*360*/ struct { /* LVT - LINT1 */
 325                 u32   vector            :  8,
 326                         delivery_mode   :  3,
 327                         __reserved_1    :  1,
 328                         delivery_status :  1,
 329                         polarity        :  1,
 330                         remote_irr      :  1,
 331                         trigger         :  1,
 332                         mask            :  1,
 333                         __reserved_2    : 15;
 334                 u32 __reserved_3[3];
 335         } lvt_lint1;
 336
 337 /*370*/ struct { /* LVT - Error */
 338                 u32   vector            :  8,
 339                         __reserved_1    :  4,
 340                         delivery_status :  1,
 341                         __reserved_2    :  3,
 342                         mask            :  1,
 343                         __reserved_3    : 15;
 344                 u32 __reserved_4[3];
 345         } lvt_error;
 346
 347 /*380*/ struct { /* Timer Initial Count Register */
 348                 u32   initial_count;
 349                 u32 __reserved_2[3];
 350         } timer_icr;
 351
 352 /*390*/ const
 353         struct { /* Timer Current Count Register */
 354                 u32   curr_count;
 355                 u32 __reserved_2[3];
 356         } timer_ccr;
 357
 358 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 359
 360 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 361
 362 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 363
 364 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 365
 366 /*3E0*/ struct { /* Timer Divide Configuration Register */
 367                 u32   divisor           :  4,
 368                         __reserved_1    : 28;
 369                 u32 __reserved_2[3];
 370         } timer_dcr;
 371
 372 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 373
 374 } __attribute__ ((packed));
 375
 376 #undef u32
 377
 378 #endif