1 #ifndef __ASM_MACH_APIC_H
2 #define __ASM_MACH_APIC_H
5 #define SEQUENTIAL_APICID
6 #ifdef SEQUENTIAL_APICID
7 #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
8 ((phys_apic<<2) & (~0xf)) )
10 #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
11 ((phys_apic) & (~0xf)) )
14 #define NO_BALANCE_IRQ (1)
15 #define esr_disable (1)
17 #define NO_IOAPIC_CHECK (0)
19 static inline int apic_id_registered(void)
24 #define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
25 static inline cpumask_t target_cpus(void)
27 return cpu_online_map;
29 #define TARGET_CPUS (target_cpus())
31 #define INT_DELIVERY_MODE dest_LowestPrio
32 #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
34 #define APIC_BROADCAST_ID (0xff)
35 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
40 /* we don't use the phys_cpu_present_map to indicate apicid presence */
41 static inline unsigned long check_apicid_present(int bit)
46 #define apicid_cluster(apicid) (apicid & 0xF0)
48 static inline unsigned long calculate_ldr(unsigned long old)
51 id = xapic_phys_to_log_apicid(hard_smp_processor_id());
52 return ((old & ~APIC_LDR_MASK) | SET_APIC_LOGICAL_ID(id));
56 * Set up the logical destination ID.
58 * Intel recommends to set DFR, LDR and TPR before enabling
59 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
60 * document number 292116). So here it goes...
62 static inline void init_apic_ldr(void)
66 apic_write_around(APIC_DFR, APIC_DFR_VALUE);
67 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
68 val = calculate_ldr(val);
69 apic_write_around(APIC_LDR, val);
72 static inline void clustered_apic_check(void)
74 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
75 "Cluster", nr_ioapics);
78 static inline int multi_timer_check(int apic, int irq)
83 static inline int apicid_to_node(int logical_apicid)
88 extern u8 bios_cpu_apicid[];
90 static inline int cpu_present_to_apicid(int mps_cpu)
92 if (mps_cpu < NR_CPUS)
93 return (int)bios_cpu_apicid[mps_cpu];
98 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
100 return physid_mask_of_physid(phys_apicid);
103 extern u8 cpu_2_logical_apicid[];
104 /* Mapping from cpu number to logical apicid */
105 static inline int cpu_to_logical_apicid(int cpu)
109 return (int)cpu_2_logical_apicid[cpu];
112 static inline int mpc_apic_id(struct mpc_config_processor *m,
113 struct mpc_config_translation *translation_record)
115 printk("Processor #%d %ld:%ld APIC version %d\n",
117 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
118 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
120 return m->mpc_apicid;
123 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
125 /* For clustered we don't have a good way to do this yet - hack */
126 return physids_promote(0xFUL);
129 #define WAKE_SECONDARY_VIA_INIT
131 static inline void setup_portio_remap(void)
135 static inline void enable_apic_mode(void)
139 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
144 static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
151 num_bits_set = cpus_weight_const(cpumask);
152 /* Return id to all */
153 if (num_bits_set == NR_CPUS)
156 * The cpus in the mask must all be on the apic cluster. If are not
157 * on the same apicid cluster return default value of TARGET_CPUS.
159 cpu = first_cpu_const(cpumask);
160 apicid = cpu_to_logical_apicid(cpu);
161 while (cpus_found < num_bits_set) {
162 if (cpu_isset_const(cpu, cpumask)) {
163 int new_apicid = cpu_to_logical_apicid(cpu);
164 if (apicid_cluster(apicid) !=
165 apicid_cluster(new_apicid)){
166 printk ("%s: Not a valid mask!\n",__FUNCTION__);
169 apicid = apicid | new_apicid;
177 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
179 return cpuid_apic >> index_msb;
182 #endif /* __ASM_MACH_APIC_H */