1 #ifndef __ASM_MACH_APIC_H
2 #define __ASM_MACH_APIC_H
5 #define SEQUENTIAL_APICID
6 #ifdef SEQUENTIAL_APICID
7 #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
8 ((phys_apic<<2) & (~0xf)) )
10 #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\
11 ((phys_apic) & (~0xf)) )
14 #define NO_BALANCE_IRQ (1)
15 #define esr_disable (1)
17 #define NO_IOAPIC_CHECK (0)
19 static inline int apic_id_registered(void)
24 #define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
25 /* Round robin the irqs amoung the online cpus */
26 static inline cpumask_t target_cpus(void)
28 static unsigned long cpu = NR_CPUS;
31 cpu = first_cpu_const(cpu_online_map);
33 cpu = next_cpu_const(cpu, cpu_online_map);
34 } while (cpu >= NR_CPUS);
35 return mk_cpumask_const(cpumask_of_cpu(cpu));
37 #define TARGET_CPUS (target_cpus())
39 #define INT_DELIVERY_MODE dest_Fixed
40 #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
42 #define APIC_BROADCAST_ID (0xff)
43 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
48 /* we don't use the phys_cpu_present_map to indicate apicid presence */
49 static inline unsigned long check_apicid_present(int bit)
54 #define apicid_cluster(apicid) (apicid & 0xF0)
56 static inline unsigned long calculate_ldr(unsigned long old)
59 id = xapic_phys_to_log_apicid(hard_smp_processor_id());
60 return ((old & ~APIC_LDR_MASK) | SET_APIC_LOGICAL_ID(id));
64 * Set up the logical destination ID.
66 * Intel recommends to set DFR, LDR and TPR before enabling
67 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
68 * document number 292116). So here it goes...
70 static inline void init_apic_ldr(void)
74 apic_write_around(APIC_DFR, APIC_DFR_VALUE);
75 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
76 val = calculate_ldr(val);
77 apic_write_around(APIC_LDR, val);
80 static inline void clustered_apic_check(void)
82 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
83 "Cluster", nr_ioapics);
86 static inline int multi_timer_check(int apic, int irq)
91 static inline int apicid_to_node(int logical_apicid)
96 extern u8 bios_cpu_apicid[];
98 static inline int cpu_present_to_apicid(int mps_cpu)
100 if (mps_cpu < NR_CPUS)
101 return (int)bios_cpu_apicid[mps_cpu];
106 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
108 return physid_mask_of_physid(phys_apicid);
111 extern u8 cpu_2_logical_apicid[];
112 /* Mapping from cpu number to logical apicid */
113 static inline int cpu_to_logical_apicid(int cpu)
117 return (int)cpu_2_logical_apicid[cpu];
120 static inline int mpc_apic_id(struct mpc_config_processor *m,
121 struct mpc_config_translation *translation_record)
123 printk("Processor #%d %ld:%ld APIC version %d\n",
125 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
126 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
128 return m->mpc_apicid;
131 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
133 /* For clustered we don't have a good way to do this yet - hack */
134 return physids_promote(0xFUL);
137 #define WAKE_SECONDARY_VIA_INIT
139 static inline void setup_portio_remap(void)
143 static inline void enable_apic_mode(void)
147 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
152 /* As we are using single CPU as destination, pick only one CPU here */
153 static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
158 cpu = first_cpu_const(cpumask);
159 apicid = cpu_to_logical_apicid(cpu);
163 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
165 return cpuid_apic >> index_msb;
168 #endif /* __ASM_MACH_APIC_H */