1 #ifndef _I386_PGTABLE_3LEVEL_H
2 #define _I386_PGTABLE_3LEVEL_H
5 * Intel Physical Address Extension (PAE) Mode - three-level page
6 * tables on PPro+ CPUs.
8 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
11 #define pte_ERROR(e) \
12 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
13 #define pmd_ERROR(e) \
14 printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
15 #define pgd_ERROR(e) \
16 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
18 #define pud_none(pud) 0
19 #define pud_bad(pud) 0
20 #define pud_present(pud) 1
23 * Is the pte executable?
25 static inline int pte_x(pte_t pte)
27 return !(pte_val(pte) & _PAGE_NX);
31 * All present user-pages with !NX bit are user-executable:
33 static inline int pte_exec(pte_t pte)
35 return pte_user(pte) && pte_x(pte);
38 * All present pages with !NX bit are kernel-executable:
40 static inline int pte_exec_kernel(pte_t pte)
45 #ifndef CONFIG_PARAVIRT
46 /* Rules for using set_pte: the pte being assigned *must* be
47 * either not present or in a state where the hardware will
48 * not attempt to update the pte. In places where this is
49 * not possible, use pte_get_and_clear to obtain the old pte
50 * value and then use set_pte to update it. -ben
52 #define __HAVE_ARCH_SET_PTE_ATOMIC
55 /* use writable pagetables */
56 static inline void set_pte(pte_t *ptep, pte_t pte)
58 ptep->pte_high = pte.pte_high;
60 ptep->pte_low = pte.pte_low;
62 # define set_pte_atomic(pteptr,pteval) \
63 set_64bit((unsigned long long *)(pteptr),pte_val_ma(pteval))
66 * Since this is only called on user PTEs, and the page fault handler
67 * must handle the already racy situation of simultaneous page faults,
68 * we are justified in merely clearing the PTE present bit, followed
69 * by a set. The ordering here is important.
71 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
75 ptep->pte_high = pte.pte_high;
77 ptep->pte_low = pte.pte_low;
80 /* no writable pagetables */
81 # define set_pte(pteptr,pteval) \
82 xen_l1_entry_update((pteptr), (pteval))
83 # define set_pte_atomic(pteptr,pteval) set_pte(pteptr,pteval)
84 # define set_pte_pressent(mm,addr,ptep,pte) set_pte_at(mm,addr,ptep,pteval)
87 #define set_pte_at(_mm,addr,ptep,pteval) do { \
88 if (((_mm) != current->mm && (_mm) != &init_mm) || \
89 HYPERVISOR_update_va_mapping((addr), (pteval), 0)) \
90 set_pte((ptep), (pteval)); \
93 #define set_pmd(pmdptr,pmdval) \
94 xen_l2_entry_update((pmdptr), (pmdval))
95 #define set_pud(pudptr,pudval) \
96 xen_l3_entry_update((pudptr), (pudval))
99 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
100 * entry, so clear the bottom half first and enforce ordering with a compiler
103 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
110 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
112 static inline pte_t raw_ptep_get_and_clear(pte_t *ptep)
116 /* xchg acts as a barrier before the setting of the high bits */
117 res.pte_low = xchg(&ptep->pte_low, 0);
118 res.pte_high = ptep->pte_high;
126 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
127 * the TLB via cr3 if the top-level pgd is changed...
128 * We do not let the generic code free and clear pgd entries due to
131 static inline void pud_clear (pud_t * pud) { }
133 #define pud_page(pud) \
134 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
136 #define pud_page_vaddr(pud) \
137 ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
140 /* Find an entry in the second-level page table.. */
141 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
144 #define __HAVE_ARCH_PTE_SAME
145 static inline int pte_same(pte_t a, pte_t b)
147 return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
150 #define pte_page(x) pfn_to_page(pte_pfn(x))
152 static inline int pte_none(pte_t pte)
154 return !pte.pte_low && !pte.pte_high;
157 #define pte_mfn(_pte) (((_pte).pte_low >> PAGE_SHIFT) |\
158 (((_pte).pte_high & 0xfff) << (32-PAGE_SHIFT)))
159 #define pte_pfn(_pte) mfn_to_local_pfn(pte_mfn(_pte))
161 extern unsigned long long __supported_pte_mask;
163 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
165 return pfn_pte_ma(pfn_to_mfn(page_nr), pgprot);
168 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
170 BUG(); panic("needs review");
171 return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
172 pgprot_val(pgprot)) & __supported_pte_mask);
176 * Bits 0, 6 and 7 are taken in the low part of the pte,
177 * put the 32 bits of offset into the high part.
179 #define pte_to_pgoff(pte) ((pte).pte_high)
180 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
181 #define PTE_FILE_MAX_BITS 32
183 /* Encode and de-code a swap entry */
184 #define __swp_type(x) (((x).val) & 0x1f)
185 #define __swp_offset(x) ((x).val >> 5)
186 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
187 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
188 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
190 #define __pmd_free_tlb(tlb, x) do { } while (0)
192 #define vmalloc_sync_all() ((void)0)
194 #endif /* _I386_PGTABLE_3LEVEL_H */