1 #ifndef _I386_PGTABLE_3LEVEL_H
2 #define _I386_PGTABLE_3LEVEL_H
4 #include <asm-generic/pgtable-nopud.h>
7 * Intel Physical Address Extension (PAE) Mode - three-level page
8 * tables on PPro+ CPUs.
10 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
13 #define pte_ERROR(e) \
14 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15 #define pmd_ERROR(e) \
16 printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
17 #define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
20 #define pud_none(pud) 0
21 #define pud_bad(pud) 0
22 #define pud_present(pud) 1
25 * Is the pte executable?
27 static inline int pte_x(pte_t pte)
29 return !(pte_val(pte) & _PAGE_NX);
33 * All present user-pages with !NX bit are user-executable:
35 static inline int pte_exec(pte_t pte)
37 return pte_user(pte) && pte_x(pte);
40 * All present pages with !NX bit are kernel-executable:
42 static inline int pte_exec_kernel(pte_t pte)
47 /* Rules for using set_pte: the pte being assigned *must* be
48 * either not present or in a state where the hardware will
49 * not attempt to update the pte. In places where this is
50 * not possible, use pte_get_and_clear to obtain the old pte
51 * value and then use set_pte to update it. -ben
53 #define __HAVE_ARCH_SET_PTE_ATOMIC
56 /* use writable pagetables */
57 static inline void set_pte(pte_t *ptep, pte_t pte)
59 ptep->pte_high = pte.pte_high;
61 ptep->pte_low = pte.pte_low;
63 # define set_pte_atomic(pteptr,pteval) \
64 set_64bit((unsigned long long *)(pteptr),pte_val_ma(pteval))
66 /* no writable pagetables */
67 # define set_pte(pteptr,pteval) \
68 xen_l1_entry_update((pteptr), (pteval))
69 # define set_pte_atomic(pteptr,pteval) set_pte(pteptr,pteval)
72 #define set_pte_at(_mm,addr,ptep,pteval) do { \
73 if (((_mm) != current->mm && (_mm) != &init_mm) || \
74 HYPERVISOR_update_va_mapping((addr), (pteval), 0)) \
75 set_pte((ptep), (pteval)); \
78 #define set_pte_at_sync(_mm,addr,ptep,pteval) do { \
79 if (((_mm) != current->mm && (_mm) != &init_mm) || \
80 HYPERVISOR_update_va_mapping((addr), (pteval), UVMF_INVLPG)) { \
81 set_pte((ptep), (pteval)); \
86 #define set_pmd(pmdptr,pmdval) \
87 xen_l2_entry_update((pmdptr), (pmdval))
88 #define set_pud(pudptr,pudval) \
89 xen_l3_entry_update((pudptr), (pudval))
92 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
93 * the TLB via cr3 if the top-level pgd is changed...
94 * We do not let the generic code free and clear pgd entries due to
97 static inline void pud_clear (pud_t * pud) { }
99 #define pud_page(pud) \
100 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
102 #define pud_page_kernel(pud) \
103 ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
106 /* Find an entry in the second-level page table.. */
107 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
111 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
112 * entry, so clear the bottom half first and enforce ordering with a compiler
115 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
122 #define pmd_clear(xp)do { set_pmd(xp, __pmd(0)); } while (0)
124 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
128 /* xchg acts as a barrier before the setting of the high bits */
129 res.pte_low = xchg(&ptep->pte_low, 0);
130 res.pte_high = ptep->pte_high;
136 static inline int pte_same(pte_t a, pte_t b)
138 return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
141 #define pte_page(x) pfn_to_page(pte_pfn(x))
143 static inline int pte_none(pte_t pte)
145 return !pte.pte_low && !pte.pte_high;
148 #define pte_mfn(_pte) (((_pte).pte_low >> PAGE_SHIFT) |\
149 (((_pte).pte_high & 0xfff) << (32-PAGE_SHIFT)))
150 #define pte_pfn(_pte) mfn_to_local_pfn(pte_mfn(_pte))
152 extern unsigned long long __supported_pte_mask;
154 static inline pte_t pfn_pte_ma(unsigned long page_nr, pgprot_t pgprot)
158 pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
159 (pgprot_val(pgprot) >> 32);
160 pte.pte_high &= (__supported_pte_mask >> 32);
161 pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
162 __supported_pte_mask;
166 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
168 return pfn_pte_ma(pfn_to_mfn(page_nr), pgprot);
171 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
173 BUG(); panic("needs review");
174 return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
175 pgprot_val(pgprot)) & __supported_pte_mask);
179 * Bits 0, 6 and 7 are taken in the low part of the pte,
180 * put the 32 bits of offset into the high part.
182 #define pte_to_pgoff(pte) ((pte).pte_high)
183 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
184 #define PTE_FILE_MAX_BITS 32
186 /* Encode and de-code a swap entry */
187 #define __swp_type(x) (((x).val) & 0x1f)
188 #define __swp_offset(x) ((x).val >> 5)
189 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
190 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
191 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
193 #define __pmd_free_tlb(tlb, x) do { } while (0)
195 #define vmalloc_sync_all() ((void)0)
197 #endif /* _I386_PGTABLE_3LEVEL_H */