2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
23 #include <linux/init.h>
24 #include <xen/interface/physdev.h>
26 /* flag for disabling the tsc */
27 extern int tsc_disable;
33 #define desc_empty(desc) \
34 (!((desc)->a | (desc)->b))
36 #define desc_equal(desc1, desc2) \
37 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
39 * Default implementation of macro that returns current
40 * instruction pointer ("program counter").
42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
45 * CPU type and hardware bug flags. Kept separately for each CPU.
46 * Members of this structure are referenced in head.S, so think twice
47 * before touching them. [mj]
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
55 char wp_works_ok; /* It doesn't on 386's */
56 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
59 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
60 unsigned long x86_capability[NCAPINTS];
61 char x86_vendor_id[16];
62 char x86_model_id[64];
63 int x86_cache_size; /* in KB - valid for CPUS which support this
65 int x86_cache_alignment; /* In bytes */
71 unsigned long loops_per_jiffy;
73 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
75 unsigned char x86_max_cores; /* cpuid returned max cores value */
77 unsigned short x86_clflush_size;
79 unsigned char booted_cores; /* number of cores as seen by OS */
80 __u8 phys_proc_id; /* Physical processor id. */
81 __u8 cpu_core_id; /* Core id */
83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
85 #define X86_VENDOR_INTEL 0
86 #define X86_VENDOR_CYRIX 1
87 #define X86_VENDOR_AMD 2
88 #define X86_VENDOR_UMC 3
89 #define X86_VENDOR_NEXGEN 4
90 #define X86_VENDOR_CENTAUR 5
91 #define X86_VENDOR_RISE 6
92 #define X86_VENDOR_TRANSMETA 7
93 #define X86_VENDOR_NSC 8
94 #define X86_VENDOR_NUM 9
95 #define X86_VENDOR_UNKNOWN 0xff
98 * capabilities of CPUs
101 extern struct cpuinfo_x86 boot_cpu_data;
102 extern struct cpuinfo_x86 new_cpu_data;
103 #ifndef CONFIG_X86_NO_TSS
104 extern struct tss_struct doublefault_tss;
105 DECLARE_PER_CPU(struct tss_struct, init_tss);
109 extern struct cpuinfo_x86 cpu_data[];
110 #define current_cpu_data cpu_data[smp_processor_id()]
112 #define cpu_data (&boot_cpu_data)
113 #define current_cpu_data boot_cpu_data
116 extern int cpu_llc_id[NR_CPUS];
117 extern char ignore_fpu_irq;
119 void __init cpu_detect(struct cpuinfo_x86 *c);
121 extern void identify_cpu(struct cpuinfo_x86 *);
122 extern void print_cpu_info(struct cpuinfo_x86 *);
123 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
124 extern unsigned short num_cache_leaves;
127 extern void detect_ht(struct cpuinfo_x86 *c);
129 static inline void detect_ht(struct cpuinfo_x86 *c) {}
135 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
136 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
137 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
138 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
139 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
140 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
141 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
142 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
143 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
144 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
145 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
146 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
147 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
148 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
149 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
150 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
151 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
153 static inline fastcall void native_cpuid(unsigned int *eax, unsigned int *ebx,
154 unsigned int *ecx, unsigned int *edx)
156 /* ecx is often an input as well as an output. */
162 : "0" (*eax), "2" (*ecx));
165 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
168 * Intel CPU features in CR4
170 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
171 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
172 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
173 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
174 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
175 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
176 #define X86_CR4_MCE 0x0040 /* Machine check enable */
177 #define X86_CR4_PGE 0x0080 /* enable global pages */
178 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
179 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
180 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
183 * Save the cr4 feature set we're using (ie
184 * Pentium 4MB enable and PPro Global page
185 * enable), so that any CPU's that boot up
186 * after us can get the correct flags.
188 extern unsigned long mmu_cr4_features;
190 static inline void set_in_cr4 (unsigned long mask)
193 mmu_cr4_features |= mask;
199 static inline void clear_in_cr4 (unsigned long mask)
202 mmu_cr4_features &= ~mask;
209 * NSC/Cyrix CPU configuration register indexes
212 #define CX86_PCR0 0x20
213 #define CX86_GCR 0xb8
214 #define CX86_CCR0 0xc0
215 #define CX86_CCR1 0xc1
216 #define CX86_CCR2 0xc2
217 #define CX86_CCR3 0xc3
218 #define CX86_CCR4 0xe8
219 #define CX86_CCR5 0xe9
220 #define CX86_CCR6 0xea
221 #define CX86_CCR7 0xeb
222 #define CX86_PCR1 0xf0
223 #define CX86_DIR0 0xfe
224 #define CX86_DIR1 0xff
225 #define CX86_ARR_BASE 0xc4
226 #define CX86_RCR_BASE 0xdc
229 * NSC/Cyrix CPU indexed register access macros
232 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
234 #define setCx86(reg, data) do { \
236 outb((data), 0x23); \
239 /* Stop speculative execution */
240 static inline void sync_core(void)
243 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
246 static inline void __monitor(const void *eax, unsigned long ecx,
249 /* "monitor %eax,%ecx,%edx;" */
251 ".byte 0x0f,0x01,0xc8;"
252 : :"a" (eax), "c" (ecx), "d"(edx));
255 static inline void __mwait(unsigned long eax, unsigned long ecx)
257 /* "mwait %eax,%ecx;" */
259 ".byte 0x0f,0x01,0xc9;"
260 : :"a" (eax), "c" (ecx));
263 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
265 /* from system description table in BIOS. Mostly for MCA use, but
266 others may find it useful. */
267 extern unsigned int machine_id;
268 extern unsigned int machine_submodel_id;
269 extern unsigned int BIOS_revision;
270 extern unsigned int mca_pentium_flag;
272 /* Boot loader type from the setup header */
273 extern int bootloader_type;
276 * User space process size: 3GB (default).
278 #define TASK_SIZE (PAGE_OFFSET)
280 /* This decides where the kernel will search for a free chunk of vm
281 * space during mmap's.
283 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
285 #define __HAVE_ARCH_ALIGN_STACK
286 extern unsigned long arch_align_stack(unsigned long sp);
288 #define HAVE_ARCH_PICK_MMAP_LAYOUT
293 #define IO_BITMAP_BITS 65536
294 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
295 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
296 #ifndef CONFIG_X86_NO_TSS
297 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
299 #define INVALID_IO_BITMAP_OFFSET 0x8000
300 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
302 struct i387_fsave_struct {
310 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
311 long status; /* software status information */
314 struct i387_fxsave_struct {
325 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
326 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
328 } __attribute__ ((aligned (16)));
330 struct i387_soft_struct {
338 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
339 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
341 unsigned long entry_eip;
345 struct i387_fsave_struct fsave;
346 struct i387_fxsave_struct fxsave;
347 struct i387_soft_struct soft;
354 struct thread_struct;
356 #ifndef CONFIG_X86_NO_TSS
358 unsigned short back_link,__blh;
360 unsigned short ss0,__ss0h;
362 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
364 unsigned short ss2,__ss2h;
367 unsigned long eflags;
368 unsigned long eax,ecx,edx,ebx;
373 unsigned short es, __esh;
374 unsigned short cs, __csh;
375 unsigned short ss, __ssh;
376 unsigned short ds, __dsh;
377 unsigned short fs, __fsh;
378 unsigned short gs, __gsh;
379 unsigned short ldt, __ldth;
380 unsigned short trace, io_bitmap_base;
382 * The extra 1 is there because the CPU will access an
383 * additional byte beyond the end of the IO permission
384 * bitmap. The extra byte must be all 1 bits, and must
385 * be within the limit.
387 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
389 * Cache the current maximum and the last task that used the bitmap:
391 unsigned long io_bitmap_max;
392 struct thread_struct *io_bitmap_owner;
394 * pads the TSS to be cacheline-aligned (size is 0x100)
396 unsigned long __cacheline_filler[35];
398 * .. and then another 0x100 bytes for emergency kernel stack
400 unsigned long stack[64];
401 } __attribute__((packed));
404 #define ARCH_MIN_TASKALIGN 16
406 struct thread_struct {
407 /* cached TLS descriptors. */
408 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
410 unsigned long sysenter_cs;
415 /* Hardware debugging registers */
416 unsigned long debugreg[8]; /* %%db0-7 debug registers */
418 unsigned long cr2, trap_no, error_code;
419 /* floating point info */
420 union i387_union i387;
421 /* virtual 86 mode info */
422 struct vm86_struct __user * vm86_info;
423 unsigned long screen_bitmap;
424 unsigned long v86flags, v86mask, saved_esp0;
425 unsigned int saved_fs, saved_gs;
427 unsigned long *io_bitmap_ptr;
429 /* max allowed port in the bitmap, in bytes: */
430 unsigned long io_bitmap_max;
433 #define INIT_THREAD { \
435 .sysenter_cs = __KERNEL_CS, \
436 .io_bitmap_ptr = NULL, \
437 .gs = __KERNEL_PDA, \
440 #ifndef CONFIG_X86_NO_TSS
442 * Note that the .io_bitmap member must be extra-big. This is because
443 * the CPU will access an additional byte beyond the end of the IO
444 * permission bitmap. The extra byte must be all 1 bits, and must
445 * be within the limit.
448 .esp0 = sizeof(init_stack) + (long)&init_stack, \
449 .ss0 = __KERNEL_DS, \
450 .ss1 = __KERNEL_CS, \
451 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
452 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
456 #define start_thread(regs, new_eip, new_esp) do { \
457 __asm__("movl %0,%%fs": :"r" (0)); \
460 regs->xds = __USER_DS; \
461 regs->xes = __USER_DS; \
462 regs->xss = __USER_DS; \
463 regs->xcs = __USER_CS; \
464 regs->eip = new_eip; \
465 regs->esp = new_esp; \
467 load_user_cs_desc(smp_processor_id(), current->mm); \
471 /* Forward declaration, a strange C thing */
475 /* Free all resources held by a thread. */
476 extern void release_thread(struct task_struct *);
478 /* Prepare to copy thread state - unlazy all lazy status */
479 extern void prepare_to_copy(struct task_struct *tsk);
482 * create a kernel thread without removing it from tasklists
484 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
486 extern unsigned long thread_saved_pc(struct task_struct *tsk);
487 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
489 unsigned long get_wchan(struct task_struct *p);
491 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
492 #define KSTK_TOP(info) \
494 unsigned long *__ptr = (unsigned long *)(info); \
495 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
499 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
500 * This is necessary to guarantee that the entire "struct pt_regs"
501 * is accessable even if the CPU haven't stored the SS/ESP registers
502 * on the stack (interrupt gate does not save these registers
503 * when switching to the same priv ring).
504 * Therefore beware: accessing the xss/esp fields of the
505 * "struct pt_regs" is possible, but they may contain the
506 * completely wrong values.
508 #define task_pt_regs(task) \
510 struct pt_regs *__regs__; \
511 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
515 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
516 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
519 struct microcode_header {
527 unsigned int datasize;
528 unsigned int totalsize;
529 unsigned int reserved[3];
533 struct microcode_header hdr;
534 unsigned int bits[0];
537 typedef struct microcode microcode_t;
538 typedef struct microcode_header microcode_header_t;
540 /* microcode format is extended from prescott processors */
541 struct extended_signature {
547 struct extended_sigtable {
550 unsigned int reserved[3];
551 struct extended_signature sigs[0];
554 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
555 static inline void rep_nop(void)
557 __asm__ __volatile__("rep;nop": : :"memory");
560 #define cpu_relax() rep_nop()
562 #ifdef CONFIG_PARAVIRT
563 #include <asm/paravirt.h>
565 #define paravirt_enabled() 0
566 #define __cpuid native_cpuid
568 #ifndef CONFIG_X86_NO_TSS
569 static inline void __load_esp0(struct tss_struct *tss, struct thread_struct *thread)
571 tss->esp0 = thread->esp0;
572 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
573 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
574 tss->ss1 = thread->sysenter_cs;
575 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
578 #define load_esp0(tss, thread) \
579 __load_esp0(tss, thread)
581 #define load_esp0(tss, thread) \
582 HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->esp0)
587 * These special macros can be used to get or set a debugging register
589 #define get_debugreg(var, register) \
590 (var) = HYPERVISOR_get_debugreg((register))
591 #define set_debugreg(value, register) \
592 HYPERVISOR_set_debugreg((register), (value))
594 #define set_iopl_mask native_set_iopl_mask
595 #endif /* CONFIG_PARAVIRT */
598 * Set IOPL bits in EFLAGS from given mask
600 static fastcall inline void native_set_iopl_mask(unsigned mask)
602 struct physdev_set_iopl set_iopl;
604 /* Force the change at ring 0. */
605 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
606 HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
610 * Generic CPUID function
611 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
612 * resulting in stale register contents being returned.
614 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
618 __cpuid(eax, ebx, ecx, edx);
621 /* Some CPUID calls want 'count' to be placed in ecx */
622 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
627 __cpuid(eax, ebx, ecx, edx);
631 * CPUID functions returning a single datum
633 static inline unsigned int cpuid_eax(unsigned int op)
635 unsigned int eax, ebx, ecx, edx;
637 cpuid(op, &eax, &ebx, &ecx, &edx);
640 static inline unsigned int cpuid_ebx(unsigned int op)
642 unsigned int eax, ebx, ecx, edx;
644 cpuid(op, &eax, &ebx, &ecx, &edx);
647 static inline unsigned int cpuid_ecx(unsigned int op)
649 unsigned int eax, ebx, ecx, edx;
651 cpuid(op, &eax, &ebx, &ecx, &edx);
654 static inline unsigned int cpuid_edx(unsigned int op)
656 unsigned int eax, ebx, ecx, edx;
658 cpuid(op, &eax, &ebx, &ecx, &edx);
662 /* generic versions from gas */
663 #define GENERIC_NOP1 ".byte 0x90\n"
664 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
665 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
666 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
667 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
668 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
669 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
670 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
673 #define K8_NOP1 GENERIC_NOP1
674 #define K8_NOP2 ".byte 0x66,0x90\n"
675 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
676 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
677 #define K8_NOP5 K8_NOP3 K8_NOP2
678 #define K8_NOP6 K8_NOP3 K8_NOP3
679 #define K8_NOP7 K8_NOP4 K8_NOP3
680 #define K8_NOP8 K8_NOP4 K8_NOP4
683 /* uses eax dependencies (arbitary choice) */
684 #define K7_NOP1 GENERIC_NOP1
685 #define K7_NOP2 ".byte 0x8b,0xc0\n"
686 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
687 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
688 #define K7_NOP5 K7_NOP4 ASM_NOP1
689 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
690 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
691 #define K7_NOP8 K7_NOP7 ASM_NOP1
694 #define ASM_NOP1 K8_NOP1
695 #define ASM_NOP2 K8_NOP2
696 #define ASM_NOP3 K8_NOP3
697 #define ASM_NOP4 K8_NOP4
698 #define ASM_NOP5 K8_NOP5
699 #define ASM_NOP6 K8_NOP6
700 #define ASM_NOP7 K8_NOP7
701 #define ASM_NOP8 K8_NOP8
702 #elif defined(CONFIG_MK7)
703 #define ASM_NOP1 K7_NOP1
704 #define ASM_NOP2 K7_NOP2
705 #define ASM_NOP3 K7_NOP3
706 #define ASM_NOP4 K7_NOP4
707 #define ASM_NOP5 K7_NOP5
708 #define ASM_NOP6 K7_NOP6
709 #define ASM_NOP7 K7_NOP7
710 #define ASM_NOP8 K7_NOP8
712 #define ASM_NOP1 GENERIC_NOP1
713 #define ASM_NOP2 GENERIC_NOP2
714 #define ASM_NOP3 GENERIC_NOP3
715 #define ASM_NOP4 GENERIC_NOP4
716 #define ASM_NOP5 GENERIC_NOP5
717 #define ASM_NOP6 GENERIC_NOP6
718 #define ASM_NOP7 GENERIC_NOP7
719 #define ASM_NOP8 GENERIC_NOP8
722 #define ASM_NOP_MAX 8
724 /* Prefetch instructions for Pentium III and AMD Athlon */
725 /* It's not worth to care about 3dnow! prefetches for the K6
726 because they are microcoded there and very slow.
727 However we don't do prefetches for pre XP Athlons currently
728 That should be fixed. */
729 #define ARCH_HAS_PREFETCH
730 static inline void prefetch(const void *x)
732 alternative_input(ASM_NOP4,
738 #define ARCH_HAS_PREFETCH
739 #define ARCH_HAS_PREFETCHW
740 #define ARCH_HAS_SPINLOCK_PREFETCH
742 /* 3dnow! prefetch to get an exclusive cache line. Useful for
743 spinlocks to avoid one state transition in the cache coherency protocol. */
744 static inline void prefetchw(const void *x)
746 alternative_input(ASM_NOP4,
751 #define spin_lock_prefetch(x) prefetchw(x)
753 extern void select_idle_routine(const struct cpuinfo_x86 *c);
755 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
757 extern unsigned long boot_option_idle_override;
758 extern void enable_sep_cpu(void);
759 extern int sysenter_setup(void);
761 extern int init_gdt(int cpu, struct task_struct *idle);
762 extern void cpu_set_gdt(int);
763 extern void secondary_cpu_init(void);
765 #endif /* __ASM_I386_PROCESSOR_H */