include/asm-i386/mach-xen/asm/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <linux/bitops.h> /* for LOCK_PREFIX */
   8 #include <asm/synch_bitops.h>
   9 #include <asm/hypervisor.h>
  10
  11 #ifdef __KERNEL__
  12
  13 #ifdef CONFIG_SMP
  14 #define __vcpu_id smp_processor_id()
  15 #else
  16 #define __vcpu_id 0
  17 #endif
  18
  19 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
  20 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
  21
  22 /*
  23  * Saving eflags is important. It switches not only IOPL between tasks,
  24  * it also protects other tasks from NT leaking through sysenter etc.
  25  */
  26 #define switch_to(prev,next,last) do {                                  \
  27         unsigned long esi,edi;                                          \
  28         asm volatile("pushfl\n\t"               /* Save flags */        \
  29                      "pushl %%ebp\n\t"                                  \
  30                      "movl %%esp,%0\n\t"        /* save ESP */          \
  31                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  32                      "movl $1f,%1\n\t"          /* save EIP */          \
  33                      "pushl %6\n\t"             /* restore EIP */       \
  34                      "jmp __switch_to\n"                                \
  35                      "1:\t"                                             \
  36                      "popl %%ebp\n\t"                                   \
  37                      "popfl"                                            \
  38                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
  39                       "=a" (last),"=S" (esi),"=D" (edi)                 \
  40                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
  41                       "2" (prev), "d" (next));                          \
  42 } while (0)
  43
  44 #define _set_base(addr,base) do { unsigned long __pr; \
  45 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  46         "rorl $16,%%edx\n\t" \
  47         "movb %%dl,%2\n\t" \
  48         "movb %%dh,%3" \
  49         :"=&d" (__pr) \
  50         :"m" (*((addr)+2)), \
  51          "m" (*((addr)+4)), \
  52          "m" (*((addr)+7)), \
  53          "0" (base) \
  54         ); } while(0)
  55
  56 #define _set_limit(addr,limit) do { unsigned long __lr; \
  57 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  58         "rorl $16,%%edx\n\t" \
  59         "movb %2,%%dh\n\t" \
  60         "andb $0xf0,%%dh\n\t" \
  61         "orb %%dh,%%dl\n\t" \
  62         "movb %%dl,%2" \
  63         :"=&d" (__lr) \
  64         :"m" (*(addr)), \
  65          "m" (*((addr)+6)), \
  66          "0" (limit) \
  67         ); } while(0)
  68
  69 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
  70 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
  71
  72 /*
  73  * Load a segment. Fall back on loading the zero
  74  * segment if something goes wrong..
  75  */
  76 #define loadsegment(seg,value)                  \
  77         asm volatile("\n"                       \
  78                 "1:\t"                          \
  79                 "mov %0,%%" #seg "\n"           \
  80                 "2:\n"                          \
  81                 ".section .fixup,\"ax\"\n"      \
  82                 "3:\t"                          \
  83                 "pushl $0\n\t"                  \
  84                 "popl %%" #seg "\n\t"           \
  85                 "jmp 2b\n"                      \
  86                 ".previous\n"                   \
  87                 ".section __ex_table,\"a\"\n\t" \
  88                 ".align 4\n\t"                  \
  89                 ".long 1b,3b\n"                 \
  90                 ".previous"                     \
  91                 : :"rm" (value))
  92
  93 /*
  94  * Save a segment register away
  95  */
  96 #define savesegment(seg, value) \
  97         asm volatile("mov %%" #seg ",%0":"=rm" (value))
  98
  99 #ifdef CONFIG_PARAVIRT
 100 #include <asm/paravirt.h>
 101 #else
 102 #define read_cr0() ({ \
 103         unsigned int __dummy; \
 104         __asm__ __volatile__( \
 105                 "movl %%cr0,%0\n\t" \
 106                 :"=r" (__dummy)); \
 107         __dummy; \
 108 })
 109 #define write_cr0(x) \
 110         __asm__ __volatile__("movl %0,%%cr0": :"r" (x))
 111
 112 #define read_cr2() \
 113         (HYPERVISOR_shared_info->vcpu_info[smp_processor_id()].arch.cr2)
 114 #define write_cr2(x) \
 115         __asm__ __volatile__("movl %0,%%cr2": :"r" (x))
 116
 117 #define read_cr3() ({ \
 118         unsigned int __dummy; \
 119         __asm__ ( \
 120                 "movl %%cr3,%0\n\t" \
 121                 :"=r" (__dummy)); \
 122         __dummy = xen_cr3_to_pfn(__dummy); \
 123         mfn_to_pfn(__dummy) << PAGE_SHIFT; \
 124 })
 125 #define write_cr3(x) ({                                         \
 126         unsigned int __dummy = pfn_to_mfn((x) >> PAGE_SHIFT);   \
 127         __dummy = xen_pfn_to_cr3(__dummy);                      \
 128         __asm__ __volatile__("movl %0,%%cr3": :"r" (__dummy));  \
 129 })
 130
 131 #define read_cr4() ({ \
 132         unsigned int __dummy; \
 133         __asm__( \
 134                 "movl %%cr4,%0\n\t" \
 135                 :"=r" (__dummy)); \
 136         __dummy; \
 137 })
 138 #define read_cr4_safe() ({                            \
 139         unsigned int __dummy;                         \
 140         /* This could fault if %cr4 does not exist */ \
 141         __asm__("1: movl %%cr4, %0              \n"   \
 142                 "2:                             \n"   \
 143                 ".section __ex_table,\"a\"      \n"   \
 144                 ".long 1b,2b                    \n"   \
 145                 ".previous                      \n"   \
 146                 : "=r" (__dummy): "0" (0));           \
 147         __dummy;                                      \
 148 })
 149 #define write_cr4(x) \
 150         __asm__ __volatile__("movl %0,%%cr4": :"r" (x))
 151
 152 #define wbinvd() \
 153         __asm__ __volatile__ ("wbinvd": : :"memory")
 154
 155 /* Clear the 'TS' bit */
 156 #define clts() (HYPERVISOR_fpu_taskswitch(0))
 157 #endif/* CONFIG_PARAVIRT */
 158
 159 /* Set the 'TS' bit */
 160 #define stts() (HYPERVISOR_fpu_taskswitch(1))
 161
 162 #endif  /* __KERNEL__ */
 163
 164 static inline unsigned long get_limit(unsigned long segment)
 165 {
 166         unsigned long __limit;
 167         __asm__("lsll %1,%0"
 168                 :"=r" (__limit):"r" (segment));
 169         return __limit+1;
 170 }
 171
 172 #define nop() __asm__ __volatile__ ("nop")
 173
 174 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 175
 176 #define tas(ptr) (xchg((ptr),1))
 177
 178 struct __xchg_dummy { unsigned long a[100]; };
 179 #define __xg(x) ((struct __xchg_dummy *)(x))
 180
 181
 182 #ifdef CONFIG_X86_CMPXCHG64
 183
 184 /*
 185  * The semantics of XCHGCMP8B are a bit strange, this is why
 186  * there is a loop and the loading of %%eax and %%edx has to
 187  * be inside. This inlines well in most cases, the cached
 188  * cost is around ~38 cycles. (in the future we might want
 189  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
 190  * might have an implicit FPU-save as a cost, so it's not
 191  * clear which path to go.)
 192  *
 193  * cmpxchg8b must be used with the lock prefix here to allow
 194  * the instruction to be executed atomically, see page 3-102
 195  * of the instruction set reference 24319102.pdf. We need
 196  * the reader side to see the coherent 64bit value.
 197  */
 198 static inline void __set_64bit (unsigned long long * ptr,
 199                 unsigned int low, unsigned int high)
 200 {
 201         __asm__ __volatile__ (
 202                 "\n1:\t"
 203                 "movl (%0), %%eax\n\t"
 204                 "movl 4(%0), %%edx\n\t"
 205                 "lock cmpxchg8b (%0)\n\t"
 206                 "jnz 1b"
 207                 : /* no outputs */
 208                 :       "D"(ptr),
 209                         "b"(low),
 210                         "c"(high)
 211                 :       "ax","dx","memory");
 212 }
 213
 214 static inline void __set_64bit_constant (unsigned long long *ptr,
 215                                                  unsigned long long value)
 216 {
 217         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
 218 }
 219 #define ll_low(x)       *(((unsigned int*)&(x))+0)
 220 #define ll_high(x)      *(((unsigned int*)&(x))+1)
 221
 222 static inline void __set_64bit_var (unsigned long long *ptr,
 223                          unsigned long long value)
 224 {
 225         __set_64bit(ptr,ll_low(value), ll_high(value));
 226 }
 227
 228 #define set_64bit(ptr,value) \
 229 (__builtin_constant_p(value) ? \
 230  __set_64bit_constant(ptr, value) : \
 231  __set_64bit_var(ptr, value) )
 232
 233 #define _set_64bit(ptr,value) \
 234 (__builtin_constant_p(value) ? \
 235  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 236  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 237
 238 #endif
 239
 240 /*
 241  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 242  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 243  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 244  */
 245 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 246 {
 247         switch (size) {
 248                 case 1:
 249                         __asm__ __volatile__("xchgb %b0,%1"
 250                                 :"=q" (x)
 251                                 :"m" (*__xg(ptr)), "0" (x)
 252                                 :"memory");
 253                         break;
 254                 case 2:
 255                         __asm__ __volatile__("xchgw %w0,%1"
 256                                 :"=r" (x)
 257                                 :"m" (*__xg(ptr)), "0" (x)
 258                                 :"memory");
 259                         break;
 260                 case 4:
 261                         __asm__ __volatile__("xchgl %0,%1"
 262                                 :"=r" (x)
 263                                 :"m" (*__xg(ptr)), "0" (x)
 264                                 :"memory");
 265                         break;
 266         }
 267         return x;
 268 }
 269
 270 /*
 271  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 272  * store NEW in MEM.  Return the initial value in MEM.  Success is
 273  * indicated by comparing RETURN with OLD.
 274  */
 275
 276 #ifdef CONFIG_X86_CMPXCHG
 277 #define __HAVE_ARCH_CMPXCHG 1
 278 #define cmpxchg(ptr,o,n)\
 279         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 280                                         (unsigned long)(n),sizeof(*(ptr))))
 281 #define sync_cmpxchg(ptr,o,n)\
 282         ((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
 283                                         (unsigned long)(n),sizeof(*(ptr))))
 284 #endif
 285
 286 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 287                                       unsigned long new, int size)
 288 {
 289         unsigned long prev;
 290         switch (size) {
 291         case 1:
 292                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 293                                      : "=a"(prev)
 294                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 295                                      : "memory");
 296                 return prev;
 297         case 2:
 298                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 299                                      : "=a"(prev)
 300                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 301                                      : "memory");
 302                 return prev;
 303         case 4:
 304                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
 305                                      : "=a"(prev)
 306                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 307                                      : "memory");
 308                 return prev;
 309         }
 310         return old;
 311 }
 312
 313 /*
 314  * Always use locked operations when touching memory shared with a
 315  * hypervisor, since the system may be SMP even if the guest kernel
 316  * isn't.
 317  */
 318 static inline unsigned long __sync_cmpxchg(volatile void *ptr,
 319                                             unsigned long old,
 320                                             unsigned long new, int size)
 321 {
 322         unsigned long prev;
 323         switch (size) {
 324         case 1:
 325                 __asm__ __volatile__("lock; cmpxchgb %b1,%2"
 326                                      : "=a"(prev)
 327                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 328                                      : "memory");
 329                 return prev;
 330         case 2:
 331                 __asm__ __volatile__("lock; cmpxchgw %w1,%2"
 332                                      : "=a"(prev)
 333                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 334                                      : "memory");
 335                 return prev;
 336         case 4:
 337                 __asm__ __volatile__("lock; cmpxchgl %1,%2"
 338                                      : "=a"(prev)
 339                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 340                                      : "memory");
 341                 return prev;
 342         }
 343         return old;
 344 }
 345
 346 #ifndef CONFIG_X86_CMPXCHG
 347 /*
 348  * Building a kernel capable running on 80386. It may be necessary to
 349  * simulate the cmpxchg on the 80386 CPU. For that purpose we define
 350  * a function for each of the sizes we support.
 351  */
 352
 353 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
 354 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
 355 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
 356
 357 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
 358                                       unsigned long new, int size)
 359 {
 360         switch (size) {
 361         case 1:
 362                 return cmpxchg_386_u8(ptr, old, new);
 363         case 2:
 364                 return cmpxchg_386_u16(ptr, old, new);
 365         case 4:
 366                 return cmpxchg_386_u32(ptr, old, new);
 367         }
 368         return old;
 369 }
 370
 371 #define cmpxchg(ptr,o,n)                                                \
 372 ({                                                                      \
 373         __typeof__(*(ptr)) __ret;                                       \
 374         if (likely(boot_cpu_data.x86 > 3))                              \
 375                 __ret = __cmpxchg((ptr), (unsigned long)(o),            \
 376                                         (unsigned long)(n), sizeof(*(ptr))); \
 377         else                                                            \
 378                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
 379                                         (unsigned long)(n), sizeof(*(ptr))); \
 380         __ret;                                                          \
 381 })
 382 #endif
 383
 384 #ifdef CONFIG_X86_CMPXCHG64
 385
 386 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
 387                                       unsigned long long new)
 388 {
 389         unsigned long long prev;
 390         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
 391                              : "=A"(prev)
 392                              : "b"((unsigned long)new),
 393                                "c"((unsigned long)(new >> 32)),
 394                                "m"(*__xg(ptr)),
 395                                "0"(old)
 396                              : "memory");
 397         return prev;
 398 }
 399
 400 #define cmpxchg64(ptr,o,n)\
 401         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
 402                                         (unsigned long long)(n)))
 403
 404 #endif
 405
 406 /*
 407  * Force strict CPU ordering.
 408  * And yes, this is required on UP too when we're talking
 409  * to devices.
 410  *
 411  * For now, "wmb()" doesn't actually do anything, as all
 412  * Intel CPU's follow what Intel calls a *Processor Order*,
 413  * in which all writes are seen in the program order even
 414  * outside the CPU.
 415  *
 416  * I expect future Intel CPU's to have a weaker ordering,
 417  * but I'd also expect them to finally get their act together
 418  * and add some real memory barriers if so.
 419  *
 420  * Some non intel clones support out of order store. wmb() ceases to be a
 421  * nop for these.
 422  */
 423
 424
 425 /*
 426  * Actually only lfence would be needed for mb() because all stores done
 427  * by the kernel should be already ordered. But keep a full barrier for now.
 428  */
 429
 430 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 431 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 432
 433 /**
 434  * read_barrier_depends - Flush all pending reads that subsequents reads
 435  * depend on.
 436  *
 437  * No data-dependent reads from memory-like regions are ever reordered
 438  * over this barrier.  All reads preceding this primitive are guaranteed
 439  * to access memory (but not necessarily other CPUs' caches) before any
 440  * reads following this primitive that depend on the data return by
 441  * any of the preceding reads.  This primitive is much lighter weight than
 442  * rmb() on most CPUs, and is never heavier weight than is
 443  * rmb().
 444  *
 445  * These ordering constraints are respected by both the local CPU
 446  * and the compiler.
 447  *
 448  * Ordering is not guaranteed by anything other than these primitives,
 449  * not even by data dependencies.  See the documentation for
 450  * memory_barrier() for examples and URLs to more information.
 451  *
 452  * For example, the following code would force ordering (the initial
 453  * value of "a" is zero, "b" is one, and "p" is "&a"):
 454  *
 455  * <programlisting>
 456  *      CPU 0                           CPU 1
 457  *
 458  *      b = 2;
 459  *      memory_barrier();
 460  *      p = &b;                         q = p;
 461  *                                      read_barrier_depends();
 462  *                                      d = *q;
 463  * </programlisting>
 464  *
 465  * because the read of "*q" depends on the read of "p" and these
 466  * two reads are separated by a read_barrier_depends().  However,
 467  * the following code, with the same initial values for "a" and "b":
 468  *
 469  * <programlisting>
 470  *      CPU 0                           CPU 1
 471  *
 472  *      a = 2;
 473  *      memory_barrier();
 474  *      b = 3;                          y = b;
 475  *                                      read_barrier_depends();
 476  *                                      x = a;
 477  * </programlisting>
 478  *
 479  * does not enforce ordering, since there is no data dependency between
 480  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 481  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 482  * in cases like this where there are no data dependencies.
 483  **/
 484
 485 #define read_barrier_depends()  do { } while(0)
 486
 487 #ifdef CONFIG_X86_OOSTORE
 488 /* Actually there are no OOO store capable CPUs for now that do SSE,
 489    but make it already an possibility. */
 490 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 491 #else
 492 #define wmb()   __asm__ __volatile__ ("": : :"memory")
 493 #endif
 494
 495 #ifdef CONFIG_SMP
 496 #define smp_mb()        mb()
 497 #define smp_rmb()       rmb()
 498 #define smp_wmb()       wmb()
 499 #define smp_read_barrier_depends()      read_barrier_depends()
 500 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 501 #else
 502 #define smp_mb()        barrier()
 503 #define smp_rmb()       barrier()
 504 #define smp_wmb()       barrier()
 505 #define smp_read_barrier_depends()      do { } while(0)
 506 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 507 #endif
 508
 509 #include <linux/irqflags.h>
 510
 511 /*
 512  * disable hlt during certain critical i/o operations
 513  */
 514 #define HAVE_DISABLE_HLT
 515 void disable_hlt(void);
 516 void enable_hlt(void);
 517
 518 extern int es7000_plat;
 519 void cpu_idle_wait(void);
 520
 521 /*
 522  * On SMP systems, when the scheduler does migration-cost autodetection,
 523  * it needs a way to flush as much of the CPU's caches as possible:
 524  */
 525 static inline void sched_cacheflush(void)
 526 {
 527         wbinvd();
 528 }
 529
 530 extern unsigned long arch_align_stack(unsigned long sp);
 531 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 532
 533 void default_idle(void);
 534
 535 #endif