include/asm-i386/mach-xen/asm/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <linux/bitops.h> /* for LOCK_PREFIX */
   8 #include <asm/synch_bitops.h>
   9 #include <asm/hypervisor.h>
  10
  11 #ifdef __KERNEL__
  12
  13 #ifdef CONFIG_SMP
  14 #define __vcpu_id smp_processor_id()
  15 #else
  16 #define __vcpu_id 0
  17 #endif
  18
  19 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
  20 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
  21
  22 /*
  23  * Saving eflags is important. It switches not only IOPL between tasks,
  24  * it also protects other tasks from NT leaking through sysenter etc.
  25  */
  26 #define switch_to(prev,next,last) do {                                  \
  27         unsigned long esi,edi;                                          \
  28         asm volatile("pushfl\n\t"               /* Save flags */        \
  29                      "pushl %%ebp\n\t"                                  \
  30                      "movl %%esp,%0\n\t"        /* save ESP */          \
  31                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  32                      "movl $1f,%1\n\t"          /* save EIP */          \
  33                      "pushl %6\n\t"             /* restore EIP */       \
  34                      "jmp __switch_to\n"                                \
  35                      "1:\t"                                             \
  36                      "popl %%ebp\n\t"                                   \
  37                      "popfl"                                            \
  38                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
  39                       "=a" (last),"=S" (esi),"=D" (edi)                 \
  40                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
  41                       "2" (prev), "d" (next));                          \
  42 } while (0)
  43
  44 #define _set_base(addr,base) do { unsigned long __pr; \
  45 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  46         "rorl $16,%%edx\n\t" \
  47         "movb %%dl,%2\n\t" \
  48         "movb %%dh,%3" \
  49         :"=&d" (__pr) \
  50         :"m" (*((addr)+2)), \
  51          "m" (*((addr)+4)), \
  52          "m" (*((addr)+7)), \
  53          "0" (base) \
  54         ); } while(0)
  55
  56 #define _set_limit(addr,limit) do { unsigned long __lr; \
  57 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  58         "rorl $16,%%edx\n\t" \
  59         "movb %2,%%dh\n\t" \
  60         "andb $0xf0,%%dh\n\t" \
  61         "orb %%dh,%%dl\n\t" \
  62         "movb %%dl,%2" \
  63         :"=&d" (__lr) \
  64         :"m" (*(addr)), \
  65          "m" (*((addr)+6)), \
  66          "0" (limit) \
  67         ); } while(0)
  68
  69 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
  70 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
  71
  72 /*
  73  * Load a segment. Fall back on loading the zero
  74  * segment if something goes wrong..
  75  */
  76 #define loadsegment(seg,value)                  \
  77         asm volatile("\n"                       \
  78                 "1:\t"                          \
  79                 "mov %0,%%" #seg "\n"           \
  80                 "2:\n"                          \
  81                 ".section .fixup,\"ax\"\n"      \
  82                 "3:\t"                          \
  83                 "pushl $0\n\t"                  \
  84                 "popl %%" #seg "\n\t"           \
  85                 "jmp 2b\n"                      \
  86                 ".previous\n"                   \
  87                 ".section __ex_table,\"a\"\n\t" \
  88                 ".align 4\n\t"                  \
  89                 ".long 1b,3b\n"                 \
  90                 ".previous"                     \
  91                 : :"rm" (value))
  92
  93 /*
  94  * Save a segment register away
  95  */
  96 #define savesegment(seg, value) \
  97         asm volatile("mov %%" #seg ",%0":"=rm" (value))
  98
  99 #define read_cr0() ({ \
 100         unsigned int __dummy; \
 101         __asm__ __volatile__( \
 102                 "movl %%cr0,%0\n\t" \
 103                 :"=r" (__dummy)); \
 104         __dummy; \
 105 })
 106 #define write_cr0(x) \
 107         __asm__ __volatile__("movl %0,%%cr0": :"r" (x))
 108
 109 #define read_cr2() \
 110         (HYPERVISOR_shared_info->vcpu_info[smp_processor_id()].arch.cr2)
 111 #define write_cr2(x) \
 112         __asm__ __volatile__("movl %0,%%cr2": :"r" (x))
 113
 114 #define read_cr3() ({ \
 115         unsigned int __dummy; \
 116         __asm__ ( \
 117                 "movl %%cr3,%0\n\t" \
 118                 :"=r" (__dummy)); \
 119         __dummy = xen_cr3_to_pfn(__dummy); \
 120         mfn_to_pfn(__dummy) << PAGE_SHIFT; \
 121 })
 122 #define write_cr3(x) ({                                         \
 123         unsigned int __dummy = pfn_to_mfn((x) >> PAGE_SHIFT);   \
 124         __dummy = xen_pfn_to_cr3(__dummy);                      \
 125         __asm__ __volatile__("movl %0,%%cr3": :"r" (__dummy));  \
 126 })
 127
 128 #define read_cr4() ({ \
 129         unsigned int __dummy; \
 130         __asm__( \
 131                 "movl %%cr4,%0\n\t" \
 132                 :"=r" (__dummy)); \
 133         __dummy; \
 134 })
 135 #define read_cr4_safe() ({                            \
 136         unsigned int __dummy;                         \
 137         /* This could fault if %cr4 does not exist */ \
 138         __asm__("1: movl %%cr4, %0              \n"   \
 139                 "2:                             \n"   \
 140                 ".section __ex_table,\"a\"      \n"   \
 141                 ".long 1b,2b                    \n"   \
 142                 ".previous                      \n"   \
 143                 : "=r" (__dummy): "0" (0));           \
 144         __dummy;                                      \
 145 })
 146
 147 #define write_cr4(x) \
 148         __asm__ __volatile__("movl %0,%%cr4": :"r" (x))
 149 /*
 150  * Clear and set 'TS' bit respectively
 151  */
 152 #define clts() (HYPERVISOR_fpu_taskswitch(0))
 153 #define stts() (HYPERVISOR_fpu_taskswitch(1))
 154
 155 #endif  /* __KERNEL__ */
 156
 157 #define wbinvd() \
 158         __asm__ __volatile__ ("wbinvd": : :"memory")
 159
 160 static inline unsigned long get_limit(unsigned long segment)
 161 {
 162         unsigned long __limit;
 163         __asm__("lsll %1,%0"
 164                 :"=r" (__limit):"r" (segment));
 165         return __limit+1;
 166 }
 167
 168 #define nop() __asm__ __volatile__ ("nop")
 169
 170 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 171
 172 #define tas(ptr) (xchg((ptr),1))
 173
 174 struct __xchg_dummy { unsigned long a[100]; };
 175 #define __xg(x) ((struct __xchg_dummy *)(x))
 176
 177
 178 #ifdef CONFIG_X86_CMPXCHG64
 179
 180 /*
 181  * The semantics of XCHGCMP8B are a bit strange, this is why
 182  * there is a loop and the loading of %%eax and %%edx has to
 183  * be inside. This inlines well in most cases, the cached
 184  * cost is around ~38 cycles. (in the future we might want
 185  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
 186  * might have an implicit FPU-save as a cost, so it's not
 187  * clear which path to go.)
 188  *
 189  * cmpxchg8b must be used with the lock prefix here to allow
 190  * the instruction to be executed atomically, see page 3-102
 191  * of the instruction set reference 24319102.pdf. We need
 192  * the reader side to see the coherent 64bit value.
 193  */
 194 static inline void __set_64bit (unsigned long long * ptr,
 195                 unsigned int low, unsigned int high)
 196 {
 197         __asm__ __volatile__ (
 198                 "\n1:\t"
 199                 "movl (%0), %%eax\n\t"
 200                 "movl 4(%0), %%edx\n\t"
 201                 "lock cmpxchg8b (%0)\n\t"
 202                 "jnz 1b"
 203                 : /* no outputs */
 204                 :       "D"(ptr),
 205                         "b"(low),
 206                         "c"(high)
 207                 :       "ax","dx","memory");
 208 }
 209
 210 static inline void __set_64bit_constant (unsigned long long *ptr,
 211                                                  unsigned long long value)
 212 {
 213         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
 214 }
 215 #define ll_low(x)       *(((unsigned int*)&(x))+0)
 216 #define ll_high(x)      *(((unsigned int*)&(x))+1)
 217
 218 static inline void __set_64bit_var (unsigned long long *ptr,
 219                          unsigned long long value)
 220 {
 221         __set_64bit(ptr,ll_low(value), ll_high(value));
 222 }
 223
 224 #define set_64bit(ptr,value) \
 225 (__builtin_constant_p(value) ? \
 226  __set_64bit_constant(ptr, value) : \
 227  __set_64bit_var(ptr, value) )
 228
 229 #define _set_64bit(ptr,value) \
 230 (__builtin_constant_p(value) ? \
 231  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 232  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 233
 234 #endif
 235
 236 /*
 237  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 238  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 239  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 240  */
 241 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 242 {
 243         switch (size) {
 244                 case 1:
 245                         __asm__ __volatile__("xchgb %b0,%1"
 246                                 :"=q" (x)
 247                                 :"m" (*__xg(ptr)), "0" (x)
 248                                 :"memory");
 249                         break;
 250                 case 2:
 251                         __asm__ __volatile__("xchgw %w0,%1"
 252                                 :"=r" (x)
 253                                 :"m" (*__xg(ptr)), "0" (x)
 254                                 :"memory");
 255                         break;
 256                 case 4:
 257                         __asm__ __volatile__("xchgl %0,%1"
 258                                 :"=r" (x)
 259                                 :"m" (*__xg(ptr)), "0" (x)
 260                                 :"memory");
 261                         break;
 262         }
 263         return x;
 264 }
 265
 266 /*
 267  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 268  * store NEW in MEM.  Return the initial value in MEM.  Success is
 269  * indicated by comparing RETURN with OLD.
 270  */
 271
 272 #ifdef CONFIG_X86_CMPXCHG
 273 #define __HAVE_ARCH_CMPXCHG 1
 274 #define cmpxchg(ptr,o,n)\
 275         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 276                                         (unsigned long)(n),sizeof(*(ptr))))
 277 #endif
 278
 279 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 280                                       unsigned long new, int size)
 281 {
 282         unsigned long prev;
 283         switch (size) {
 284         case 1:
 285                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 286                                      : "=a"(prev)
 287                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 288                                      : "memory");
 289                 return prev;
 290         case 2:
 291                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 292                                      : "=a"(prev)
 293                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 294                                      : "memory");
 295                 return prev;
 296         case 4:
 297                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
 298                                      : "=a"(prev)
 299                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 300                                      : "memory");
 301                 return prev;
 302         }
 303         return old;
 304 }
 305
 306 #ifndef CONFIG_X86_CMPXCHG
 307 /*
 308  * Building a kernel capable running on 80386. It may be necessary to
 309  * simulate the cmpxchg on the 80386 CPU. For that purpose we define
 310  * a function for each of the sizes we support.
 311  */
 312
 313 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
 314 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
 315 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
 316
 317 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
 318                                       unsigned long new, int size)
 319 {
 320         switch (size) {
 321         case 1:
 322                 return cmpxchg_386_u8(ptr, old, new);
 323         case 2:
 324                 return cmpxchg_386_u16(ptr, old, new);
 325         case 4:
 326                 return cmpxchg_386_u32(ptr, old, new);
 327         }
 328         return old;
 329 }
 330
 331 #define cmpxchg(ptr,o,n)                                                \
 332 ({                                                                      \
 333         __typeof__(*(ptr)) __ret;                                       \
 334         if (likely(boot_cpu_data.x86 > 3))                              \
 335                 __ret = __cmpxchg((ptr), (unsigned long)(o),            \
 336                                         (unsigned long)(n), sizeof(*(ptr))); \
 337         else                                                            \
 338                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
 339                                         (unsigned long)(n), sizeof(*(ptr))); \
 340         __ret;                                                          \
 341 })
 342 #endif
 343
 344 #ifdef CONFIG_X86_CMPXCHG64
 345
 346 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
 347                                       unsigned long long new)
 348 {
 349         unsigned long long prev;
 350         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
 351                              : "=A"(prev)
 352                              : "b"((unsigned long)new),
 353                                "c"((unsigned long)(new >> 32)),
 354                                "m"(*__xg(ptr)),
 355                                "0"(old)
 356                              : "memory");
 357         return prev;
 358 }
 359
 360 #define cmpxchg64(ptr,o,n)\
 361         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
 362                                         (unsigned long long)(n)))
 363
 364 #endif
 365
 366 /*
 367  * Force strict CPU ordering.
 368  * And yes, this is required on UP too when we're talking
 369  * to devices.
 370  *
 371  * For now, "wmb()" doesn't actually do anything, as all
 372  * Intel CPU's follow what Intel calls a *Processor Order*,
 373  * in which all writes are seen in the program order even
 374  * outside the CPU.
 375  *
 376  * I expect future Intel CPU's to have a weaker ordering,
 377  * but I'd also expect them to finally get their act together
 378  * and add some real memory barriers if so.
 379  *
 380  * Some non intel clones support out of order store. wmb() ceases to be a
 381  * nop for these.
 382  */
 383
 384
 385 /*
 386  * Actually only lfence would be needed for mb() because all stores done
 387  * by the kernel should be already ordered. But keep a full barrier for now.
 388  */
 389
 390 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 391 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 392
 393 /**
 394  * read_barrier_depends - Flush all pending reads that subsequents reads
 395  * depend on.
 396  *
 397  * No data-dependent reads from memory-like regions are ever reordered
 398  * over this barrier.  All reads preceding this primitive are guaranteed
 399  * to access memory (but not necessarily other CPUs' caches) before any
 400  * reads following this primitive that depend on the data return by
 401  * any of the preceding reads.  This primitive is much lighter weight than
 402  * rmb() on most CPUs, and is never heavier weight than is
 403  * rmb().
 404  *
 405  * These ordering constraints are respected by both the local CPU
 406  * and the compiler.
 407  *
 408  * Ordering is not guaranteed by anything other than these primitives,
 409  * not even by data dependencies.  See the documentation for
 410  * memory_barrier() for examples and URLs to more information.
 411  *
 412  * For example, the following code would force ordering (the initial
 413  * value of "a" is zero, "b" is one, and "p" is "&a"):
 414  *
 415  * <programlisting>
 416  *      CPU 0                           CPU 1
 417  *
 418  *      b = 2;
 419  *      memory_barrier();
 420  *      p = &b;                         q = p;
 421  *                                      read_barrier_depends();
 422  *                                      d = *q;
 423  * </programlisting>
 424  *
 425  * because the read of "*q" depends on the read of "p" and these
 426  * two reads are separated by a read_barrier_depends().  However,
 427  * the following code, with the same initial values for "a" and "b":
 428  *
 429  * <programlisting>
 430  *      CPU 0                           CPU 1
 431  *
 432  *      a = 2;
 433  *      memory_barrier();
 434  *      b = 3;                          y = b;
 435  *                                      read_barrier_depends();
 436  *                                      x = a;
 437  * </programlisting>
 438  *
 439  * does not enforce ordering, since there is no data dependency between
 440  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 441  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 442  * in cases like this where there are no data dependencies.
 443  **/
 444
 445 #define read_barrier_depends()  do { } while(0)
 446
 447 #ifdef CONFIG_X86_OOSTORE
 448 /* Actually there are no OOO store capable CPUs for now that do SSE,
 449    but make it already an possibility. */
 450 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 451 #else
 452 #define wmb()   __asm__ __volatile__ ("": : :"memory")
 453 #endif
 454
 455 #ifdef CONFIG_SMP
 456 #define smp_mb()        mb()
 457 #define smp_rmb()       rmb()
 458 #define smp_wmb()       wmb()
 459 #define smp_read_barrier_depends()      read_barrier_depends()
 460 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 461 #else
 462 #define smp_mb()        barrier()
 463 #define smp_rmb()       barrier()
 464 #define smp_wmb()       barrier()
 465 #define smp_read_barrier_depends()      do { } while(0)
 466 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 467 #endif
 468
 469 #include <linux/irqflags.h>
 470
 471 /*
 472  * disable hlt during certain critical i/o operations
 473  */
 474 #define HAVE_DISABLE_HLT
 475 void disable_hlt(void);
 476 void enable_hlt(void);
 477
 478 extern int es7000_plat;
 479 void cpu_idle_wait(void);
 480
 481 /*
 482  * On SMP systems, when the scheduler does migration-cost autodetection,
 483  * it needs a way to flush as much of the CPU's caches as possible:
 484  */
 485 static inline void sched_cacheflush(void)
 486 {
 487         wbinvd();
 488 }
 489
 490 extern unsigned long arch_align_stack(unsigned long sp);
 491 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 492
 493 void default_idle(void);
 494
 495 #endif