include/asm-i386/mach-xen/asm/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <linux/bitops.h> /* for LOCK_PREFIX */
   8 #include <asm/synch_bitops.h>
   9 #include <asm/hypervisor.h>
  10
  11 #ifdef __KERNEL__
  12
  13 #ifdef CONFIG_SMP
  14 #define __vcpu_id smp_processor_id()
  15 #else
  16 #define __vcpu_id 0
  17 #endif
  18
  19 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
  20 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
  21
  22 #define switch_to(prev,next,last) do {                                  \
  23         unsigned long esi,edi;                                          \
  24         asm volatile("pushfl\n\t"               /* Save flags */        \
  25                      "pushl %%ebp\n\t"                                  \
  26                      "movl %%esp,%0\n\t"        /* save ESP */          \
  27                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  28                      "movl $1f,%1\n\t"          /* save EIP */          \
  29                      "pushl %6\n\t"             /* restore EIP */       \
  30                      "jmp __switch_to\n"                                \
  31                      "1:\t"                                             \
  32                      "popl %%ebp\n\t"                                   \
  33                      "popfl"                                            \
  34                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
  35                       "=a" (last),"=S" (esi),"=D" (edi)                 \
  36                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
  37                       "2" (prev), "d" (next));                          \
  38 } while (0)
  39
  40 #define _set_base(addr,base) do { unsigned long __pr; \
  41 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  42         "rorl $16,%%edx\n\t" \
  43         "movb %%dl,%2\n\t" \
  44         "movb %%dh,%3" \
  45         :"=&d" (__pr) \
  46         :"m" (*((addr)+2)), \
  47          "m" (*((addr)+4)), \
  48          "m" (*((addr)+7)), \
  49          "0" (base) \
  50         ); } while(0)
  51
  52 #define _set_limit(addr,limit) do { unsigned long __lr; \
  53 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  54         "rorl $16,%%edx\n\t" \
  55         "movb %2,%%dh\n\t" \
  56         "andb $0xf0,%%dh\n\t" \
  57         "orb %%dh,%%dl\n\t" \
  58         "movb %%dl,%2" \
  59         :"=&d" (__lr) \
  60         :"m" (*(addr)), \
  61          "m" (*((addr)+6)), \
  62          "0" (limit) \
  63         ); } while(0)
  64
  65 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
  66 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
  67
  68 /*
  69  * Load a segment. Fall back on loading the zero
  70  * segment if something goes wrong..
  71  */
  72 #define loadsegment(seg,value)                  \
  73         asm volatile("\n"                       \
  74                 "1:\t"                          \
  75                 "mov %0,%%" #seg "\n"           \
  76                 "2:\n"                          \
  77                 ".section .fixup,\"ax\"\n"      \
  78                 "3:\t"                          \
  79                 "pushl $0\n\t"                  \
  80                 "popl %%" #seg "\n\t"           \
  81                 "jmp 2b\n"                      \
  82                 ".previous\n"                   \
  83                 ".section __ex_table,\"a\"\n\t" \
  84                 ".align 4\n\t"                  \
  85                 ".long 1b,3b\n"                 \
  86                 ".previous"                     \
  87                 : :"rm" (value))
  88
  89 /*
  90  * Save a segment register away
  91  */
  92 #define savesegment(seg, value) \
  93         asm volatile("mov %%" #seg ",%0":"=rm" (value))
  94
  95 #define read_cr0() ({ \
  96         unsigned int __dummy; \
  97         __asm__ __volatile__( \
  98                 "movl %%cr0,%0\n\t" \
  99                 :"=r" (__dummy)); \
 100         __dummy; \
 101 })
 102 #define write_cr0(x) \
 103         __asm__ __volatile__("movl %0,%%cr0": :"r" (x))
 104
 105 #define read_cr2() \
 106         (HYPERVISOR_shared_info->vcpu_info[smp_processor_id()].arch.cr2)
 107 #define write_cr2(x) \
 108         __asm__ __volatile__("movl %0,%%cr2": :"r" (x))
 109
 110 #define read_cr3() ({ \
 111         unsigned int __dummy; \
 112         __asm__ ( \
 113                 "movl %%cr3,%0\n\t" \
 114                 :"=r" (__dummy)); \
 115         __dummy = xen_cr3_to_pfn(__dummy); \
 116         mfn_to_pfn(__dummy) << PAGE_SHIFT; \
 117 })
 118 #define write_cr3(x) ({                                         \
 119         unsigned int __dummy = pfn_to_mfn((x) >> PAGE_SHIFT);   \
 120         __dummy = xen_pfn_to_cr3(__dummy);                      \
 121         __asm__ __volatile__("movl %0,%%cr3": :"r" (__dummy));  \
 122 })
 123
 124 #define read_cr4() ({ \
 125         unsigned int __dummy; \
 126         __asm__( \
 127                 "movl %%cr4,%0\n\t" \
 128                 :"=r" (__dummy)); \
 129         __dummy; \
 130 })
 131 #define read_cr4_safe() ({                            \
 132         unsigned int __dummy;                         \
 133         /* This could fault if %cr4 does not exist */ \
 134         __asm__("1: movl %%cr4, %0              \n"   \
 135                 "2:                             \n"   \
 136                 ".section __ex_table,\"a\"      \n"   \
 137                 ".long 1b,2b                    \n"   \
 138                 ".previous                      \n"   \
 139                 : "=r" (__dummy): "0" (0));           \
 140         __dummy;                                      \
 141 })
 142
 143 #define write_cr4(x) \
 144         __asm__ __volatile__("movl %0,%%cr4": :"r" (x))
 145 /*
 146  * Clear and set 'TS' bit respectively
 147  */
 148 #define clts() (HYPERVISOR_fpu_taskswitch(0))
 149 #define stts() (HYPERVISOR_fpu_taskswitch(1))
 150
 151 #endif  /* __KERNEL__ */
 152
 153 #define wbinvd() \
 154         __asm__ __volatile__ ("wbinvd": : :"memory")
 155
 156 static inline unsigned long get_limit(unsigned long segment)
 157 {
 158         unsigned long __limit;
 159         __asm__("lsll %1,%0"
 160                 :"=r" (__limit):"r" (segment));
 161         return __limit+1;
 162 }
 163
 164 #define nop() __asm__ __volatile__ ("nop")
 165
 166 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 167
 168 #define tas(ptr) (xchg((ptr),1))
 169
 170 struct __xchg_dummy { unsigned long a[100]; };
 171 #define __xg(x) ((struct __xchg_dummy *)(x))
 172
 173
 174 #ifdef CONFIG_X86_CMPXCHG64
 175
 176 /*
 177  * The semantics of XCHGCMP8B are a bit strange, this is why
 178  * there is a loop and the loading of %%eax and %%edx has to
 179  * be inside. This inlines well in most cases, the cached
 180  * cost is around ~38 cycles. (in the future we might want
 181  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
 182  * might have an implicit FPU-save as a cost, so it's not
 183  * clear which path to go.)
 184  *
 185  * cmpxchg8b must be used with the lock prefix here to allow
 186  * the instruction to be executed atomically, see page 3-102
 187  * of the instruction set reference 24319102.pdf. We need
 188  * the reader side to see the coherent 64bit value.
 189  */
 190 static inline void __set_64bit (unsigned long long * ptr,
 191                 unsigned int low, unsigned int high)
 192 {
 193         __asm__ __volatile__ (
 194                 "\n1:\t"
 195                 "movl (%0), %%eax\n\t"
 196                 "movl 4(%0), %%edx\n\t"
 197                 "lock cmpxchg8b (%0)\n\t"
 198                 "jnz 1b"
 199                 : /* no outputs */
 200                 :       "D"(ptr),
 201                         "b"(low),
 202                         "c"(high)
 203                 :       "ax","dx","memory");
 204 }
 205
 206 static inline void __set_64bit_constant (unsigned long long *ptr,
 207                                                  unsigned long long value)
 208 {
 209         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
 210 }
 211 #define ll_low(x)       *(((unsigned int*)&(x))+0)
 212 #define ll_high(x)      *(((unsigned int*)&(x))+1)
 213
 214 static inline void __set_64bit_var (unsigned long long *ptr,
 215                          unsigned long long value)
 216 {
 217         __set_64bit(ptr,ll_low(value), ll_high(value));
 218 }
 219
 220 #define set_64bit(ptr,value) \
 221 (__builtin_constant_p(value) ? \
 222  __set_64bit_constant(ptr, value) : \
 223  __set_64bit_var(ptr, value) )
 224
 225 #define _set_64bit(ptr,value) \
 226 (__builtin_constant_p(value) ? \
 227  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 228  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 229
 230 #endif
 231
 232 /*
 233  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 234  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 235  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 236  */
 237 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 238 {
 239         switch (size) {
 240                 case 1:
 241                         __asm__ __volatile__("xchgb %b0,%1"
 242                                 :"=q" (x)
 243                                 :"m" (*__xg(ptr)), "0" (x)
 244                                 :"memory");
 245                         break;
 246                 case 2:
 247                         __asm__ __volatile__("xchgw %w0,%1"
 248                                 :"=r" (x)
 249                                 :"m" (*__xg(ptr)), "0" (x)
 250                                 :"memory");
 251                         break;
 252                 case 4:
 253                         __asm__ __volatile__("xchgl %0,%1"
 254                                 :"=r" (x)
 255                                 :"m" (*__xg(ptr)), "0" (x)
 256                                 :"memory");
 257                         break;
 258         }
 259         return x;
 260 }
 261
 262 /*
 263  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 264  * store NEW in MEM.  Return the initial value in MEM.  Success is
 265  * indicated by comparing RETURN with OLD.
 266  */
 267
 268 #ifdef CONFIG_X86_CMPXCHG
 269 #define __HAVE_ARCH_CMPXCHG 1
 270 #define cmpxchg(ptr,o,n)\
 271         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 272                                         (unsigned long)(n),sizeof(*(ptr))))
 273 #endif
 274
 275 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 276                                       unsigned long new, int size)
 277 {
 278         unsigned long prev;
 279         switch (size) {
 280         case 1:
 281                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 282                                      : "=a"(prev)
 283                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 284                                      : "memory");
 285                 return prev;
 286         case 2:
 287                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 288                                      : "=a"(prev)
 289                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 290                                      : "memory");
 291                 return prev;
 292         case 4:
 293                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
 294                                      : "=a"(prev)
 295                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 296                                      : "memory");
 297                 return prev;
 298         }
 299         return old;
 300 }
 301
 302 #ifndef CONFIG_X86_CMPXCHG
 303 /*
 304  * Building a kernel capable running on 80386. It may be necessary to
 305  * simulate the cmpxchg on the 80386 CPU. For that purpose we define
 306  * a function for each of the sizes we support.
 307  */
 308
 309 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
 310 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
 311 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
 312
 313 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
 314                                       unsigned long new, int size)
 315 {
 316         switch (size) {
 317         case 1:
 318                 return cmpxchg_386_u8(ptr, old, new);
 319         case 2:
 320                 return cmpxchg_386_u16(ptr, old, new);
 321         case 4:
 322                 return cmpxchg_386_u32(ptr, old, new);
 323         }
 324         return old;
 325 }
 326
 327 #define cmpxchg(ptr,o,n)                                                \
 328 ({                                                                      \
 329         __typeof__(*(ptr)) __ret;                                       \
 330         if (likely(boot_cpu_data.x86 > 3))                              \
 331                 __ret = __cmpxchg((ptr), (unsigned long)(o),            \
 332                                         (unsigned long)(n), sizeof(*(ptr))); \
 333         else                                                            \
 334                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
 335                                         (unsigned long)(n), sizeof(*(ptr))); \
 336         __ret;                                                          \
 337 })
 338 #endif
 339
 340 #ifdef CONFIG_X86_CMPXCHG64
 341
 342 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
 343                                       unsigned long long new)
 344 {
 345         unsigned long long prev;
 346         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
 347                              : "=A"(prev)
 348                              : "b"((unsigned long)new),
 349                                "c"((unsigned long)(new >> 32)),
 350                                "m"(*__xg(ptr)),
 351                                "0"(old)
 352                              : "memory");
 353         return prev;
 354 }
 355
 356 #define cmpxchg64(ptr,o,n)\
 357         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
 358                                         (unsigned long long)(n)))
 359
 360 #endif
 361
 362 /*
 363  * Force strict CPU ordering.
 364  * And yes, this is required on UP too when we're talking
 365  * to devices.
 366  *
 367  * For now, "wmb()" doesn't actually do anything, as all
 368  * Intel CPU's follow what Intel calls a *Processor Order*,
 369  * in which all writes are seen in the program order even
 370  * outside the CPU.
 371  *
 372  * I expect future Intel CPU's to have a weaker ordering,
 373  * but I'd also expect them to finally get their act together
 374  * and add some real memory barriers if so.
 375  *
 376  * Some non intel clones support out of order store. wmb() ceases to be a
 377  * nop for these.
 378  */
 379
 380
 381 /*
 382  * Actually only lfence would be needed for mb() because all stores done
 383  * by the kernel should be already ordered. But keep a full barrier for now.
 384  */
 385
 386 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 387 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 388
 389 /**
 390  * read_barrier_depends - Flush all pending reads that subsequents reads
 391  * depend on.
 392  *
 393  * No data-dependent reads from memory-like regions are ever reordered
 394  * over this barrier.  All reads preceding this primitive are guaranteed
 395  * to access memory (but not necessarily other CPUs' caches) before any
 396  * reads following this primitive that depend on the data return by
 397  * any of the preceding reads.  This primitive is much lighter weight than
 398  * rmb() on most CPUs, and is never heavier weight than is
 399  * rmb().
 400  *
 401  * These ordering constraints are respected by both the local CPU
 402  * and the compiler.
 403  *
 404  * Ordering is not guaranteed by anything other than these primitives,
 405  * not even by data dependencies.  See the documentation for
 406  * memory_barrier() for examples and URLs to more information.
 407  *
 408  * For example, the following code would force ordering (the initial
 409  * value of "a" is zero, "b" is one, and "p" is "&a"):
 410  *
 411  * <programlisting>
 412  *      CPU 0                           CPU 1
 413  *
 414  *      b = 2;
 415  *      memory_barrier();
 416  *      p = &b;                         q = p;
 417  *                                      read_barrier_depends();
 418  *                                      d = *q;
 419  * </programlisting>
 420  *
 421  * because the read of "*q" depends on the read of "p" and these
 422  * two reads are separated by a read_barrier_depends().  However,
 423  * the following code, with the same initial values for "a" and "b":
 424  *
 425  * <programlisting>
 426  *      CPU 0                           CPU 1
 427  *
 428  *      a = 2;
 429  *      memory_barrier();
 430  *      b = 3;                          y = b;
 431  *                                      read_barrier_depends();
 432  *                                      x = a;
 433  * </programlisting>
 434  *
 435  * does not enforce ordering, since there is no data dependency between
 436  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 437  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 438  * in cases like this where there are no data dependencies.
 439  **/
 440
 441 #define read_barrier_depends()  do { } while(0)
 442
 443 #ifdef CONFIG_X86_OOSTORE
 444 /* Actually there are no OOO store capable CPUs for now that do SSE,
 445    but make it already an possibility. */
 446 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 447 #else
 448 #define wmb()   __asm__ __volatile__ ("": : :"memory")
 449 #endif
 450
 451 #ifdef CONFIG_SMP
 452 #define smp_mb()        mb()
 453 #define smp_rmb()       rmb()
 454 #define smp_wmb()       wmb()
 455 #define smp_read_barrier_depends()      read_barrier_depends()
 456 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 457 #else
 458 #define smp_mb()        barrier()
 459 #define smp_rmb()       barrier()
 460 #define smp_wmb()       barrier()
 461 #define smp_read_barrier_depends()      do { } while(0)
 462 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 463 #endif
 464
 465 #include <linux/irqflags.h>
 466
 467 /*
 468  * disable hlt during certain critical i/o operations
 469  */
 470 #define HAVE_DISABLE_HLT
 471 void disable_hlt(void);
 472 void enable_hlt(void);
 473
 474 extern int es7000_plat;
 475 void cpu_idle_wait(void);
 476
 477 /*
 478  * On SMP systems, when the scheduler does migration-cost autodetection,
 479  * it needs a way to flush as much of the CPU's caches as possible:
 480  */
 481 static inline void sched_cacheflush(void)
 482 {
 483         wbinvd();
 484 }
 485
 486 extern unsigned long arch_align_stack(unsigned long sp);
 487 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 488
 489 void default_idle(void);
 490
 491 #endif