1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
4 #include <linux/config.h>
7 * The Linux memory management assumes a three-level page table setup. On
8 * the i386, we use that, but "fold" the mid level into the top-level page
9 * table, so that we physically have the same two-level page table as the
12 * This file contains the functions and defines necessary to modify and use
13 * the i386 page table tree.
16 #include <asm/processor.h>
17 #include <asm/fixmap.h>
18 #include <linux/threads.h>
19 #include <linux/slab.h>
21 #ifndef _I386_BITOPS_H
22 #include <asm/bitops.h>
25 extern pgd_t swapper_pg_dir[1024];
26 extern kmem_cache_t *pgd_cache, *pmd_cache, *kpmd_cache;
27 extern spinlock_t pgd_lock;
28 extern struct page *pgd_list;
29 void pmd_ctor(void *, kmem_cache_t *, unsigned long);
30 void kpmd_ctor(void *, kmem_cache_t *, unsigned long);
31 void pgd_ctor(void *, kmem_cache_t *, unsigned long);
32 void pgd_dtor(void *, kmem_cache_t *, unsigned long);
33 void pgtable_cache_init(void);
34 extern void paging_init(void);
35 void setup_identity_mappings(pgd_t *pgd_base, unsigned long start, unsigned long end);
38 * ZERO_PAGE is a global shared page that is always zero: used
39 * for zero-mapped memory areas etc..
41 extern unsigned long empty_zero_page[1024];
42 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
44 #endif /* !__ASSEMBLY__ */
47 * The Linux x86 paging architecture is 'compile-time dual-mode', it
48 * implements both the traditional 2-level x86 page tables and the
49 * newer 3-level PAE-mode page tables.
53 extern void set_system_gate(unsigned int n, void *addr);
54 extern void init_entry_mappings(void);
55 extern void entry_trampoline_setup(void);
58 # include <asm/pgtable-3level.h>
60 # include <asm/pgtable-2level.h>
64 #define PMD_SIZE (1UL << PMD_SHIFT)
65 #define PMD_MASK (~(PMD_SIZE-1))
66 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
67 #define PGDIR_MASK (~(PGDIR_SIZE-1))
69 #if defined(CONFIG_X86_PAE) && defined(CONFIG_X86_4G_VM_LAYOUT)
70 # define USER_PTRS_PER_PGD 4
72 # define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) + ((TASK_SIZE % PGDIR_SIZE) + PGDIR_SIZE-1)/PGDIR_SIZE)
75 #define FIRST_USER_PGD_NR 0
77 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
78 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
80 #define TWOLEVEL_PGDIR_SHIFT 22
81 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
82 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
86 /* Just any arbitrary offset to the start of the vmalloc VM area: the
87 * current 8MB value just means that there will be a 8MB "hole" after the
88 * physical memory until the kernel virtual memory starts. That means that
89 * any out-of-bounds memory accesses will hopefully be caught.
90 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
91 * area for the same reason. ;)
93 #define VMALLOC_OFFSET (8*1024*1024)
94 #define VMALLOC_START (((unsigned long) high_memory + 2*VMALLOC_OFFSET-1) & \
97 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
99 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
103 * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
104 * of the Pentium details, but assuming intel did the straightforward
105 * thing, this bit set in the page directory entry just means that
106 * the page directory entry points directly to a 4MB-aligned block of
109 #define _PAGE_BIT_PRESENT 0
110 #define _PAGE_BIT_RW 1
111 #define _PAGE_BIT_USER 2
112 #define _PAGE_BIT_PWT 3
113 #define _PAGE_BIT_PCD 4
114 #define _PAGE_BIT_ACCESSED 5
115 #define _PAGE_BIT_DIRTY 6
116 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
117 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
118 #define _PAGE_BIT_UNUSED1 9 /* available for programmer */
119 #define _PAGE_BIT_UNUSED2 10
120 #define _PAGE_BIT_UNUSED3 11
121 #define _PAGE_BIT_NX 63
123 #define _PAGE_PRESENT 0x001
124 #define _PAGE_RW 0x002
125 #define _PAGE_USER 0x004
126 #define _PAGE_PWT 0x008
127 #define _PAGE_PCD 0x010
128 #define _PAGE_ACCESSED 0x020
129 #define _PAGE_DIRTY 0x040
130 #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
131 #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
132 #define _PAGE_UNUSED1 0x200 /* available for programmer */
133 #define _PAGE_UNUSED2 0x400
134 #define _PAGE_UNUSED3 0x800
136 #define _PAGE_FILE 0x040 /* set:pagecache unset:swap */
137 #define _PAGE_PROTNONE 0x080 /* If not present */
138 #ifdef CONFIG_X86_PAE
139 #define _PAGE_NX (1ULL<<_PAGE_BIT_NX)
144 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
145 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
146 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
149 __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
150 #define PAGE_SHARED \
151 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
153 #define PAGE_SHARED_EXEC \
154 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
155 #define PAGE_COPY_NOEXEC \
156 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
157 #define PAGE_COPY_EXEC \
158 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
161 #define PAGE_READONLY \
162 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
163 #define PAGE_READONLY_EXEC \
164 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
166 #define _PAGE_KERNEL \
167 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
168 #define _PAGE_KERNEL_EXEC \
169 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
171 extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
172 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
173 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD)
174 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
175 #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
177 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
178 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
179 #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
180 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
181 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
182 #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
185 * The i386 can't do page protection for execute, and considers that
186 * the same are read. Also, write permissions imply read permissions.
187 * This is the closest we can get..
189 #define __P000 PAGE_NONE
190 #define __P001 PAGE_READONLY
191 #define __P010 PAGE_COPY
192 #define __P011 PAGE_COPY
193 #define __P100 PAGE_READONLY_EXEC
194 #define __P101 PAGE_READONLY_EXEC
195 #define __P110 PAGE_COPY_EXEC
196 #define __P111 PAGE_COPY_EXEC
198 #define __S000 PAGE_NONE
199 #define __S001 PAGE_READONLY
200 #define __S010 PAGE_SHARED
201 #define __S011 PAGE_SHARED
202 #define __S100 PAGE_READONLY_EXEC
203 #define __S101 PAGE_READONLY_EXEC
204 #define __S110 PAGE_SHARED_EXEC
205 #define __S111 PAGE_SHARED_EXEC
208 * Define this if things work differently on an i386 and an i486:
209 * it will (on an i486) warn about kernel memory accesses that are
210 * done without a 'verify_area(VERIFY_WRITE,..)'
212 #undef TEST_VERIFY_AREA
214 /* The boot page tables (all created as a single array) */
215 extern unsigned long pg0[];
217 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
218 #define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
220 #define pmd_none(x) (!pmd_val(x))
221 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
222 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
223 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
226 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
229 * The following only work if pte_present() is true.
230 * Undefined behaviour if not..
232 static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
233 static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
234 static inline int pte_exec(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
235 static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
236 static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
237 static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
240 * The following only works if pte_present() is not true.
242 static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
244 static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
245 static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
246 static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
247 static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
248 static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
249 static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
250 static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
251 static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
252 static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
253 static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
255 static inline int ptep_test_and_clear_dirty(pte_t *ptep)
257 if (!pte_dirty(*ptep))
259 return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low);
262 static inline int ptep_test_and_clear_young(pte_t *ptep)
264 if (!pte_young(*ptep))
266 return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low);
269 static inline void ptep_set_wrprotect(pte_t *ptep) { clear_bit(_PAGE_BIT_RW, &ptep->pte_low); }
270 static inline void ptep_mkdirty(pte_t *ptep) { set_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); }
273 * Macro to mark a page protection value as "uncacheable". On processors which do not support
274 * it, this is a no-op.
276 #define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \
277 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
280 * Conversion functions: convert a page and protection to a page entry,
281 * and a page entry and page directory to the page they refer to.
284 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
285 #define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
286 #define mk_pte_phys(physpage, pgprot) pfn_pte((physpage) >> PAGE_SHIFT, pgprot)
288 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
290 pte.pte_low &= _PAGE_CHG_MASK;
291 pte.pte_low |= pgprot_val(newprot);
292 #ifdef CONFIG_X86_PAE
294 * Chop off the NX bit (if present), and add the NX portion of
295 * the newprot (if present):
297 pte.pte_high &= -1 ^ (1 << (_PAGE_BIT_NX - 32));
298 pte.pte_high |= (pgprot_val(newprot) >> 32) & \
299 (__supported_pte_mask >> 32);
304 #define page_pte(page) page_pte_prot(page, __pgprot(0))
306 #define pmd_page_kernel(pmd) \
307 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
309 #ifndef CONFIG_DISCONTIGMEM
310 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
311 #endif /* !CONFIG_DISCONTIGMEM */
313 #define pmd_large(pmd) \
314 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
317 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
319 * this macro returns the index of the entry in the pgd page which would
320 * control the given virtual address
322 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
325 * pgd_offset() returns a (pgd_t *)
326 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
328 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
331 * a shortcut which implies the use of the kernel's pgd, instead
334 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
337 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
339 * this macro returns the index of the entry in the pmd page which would
340 * control the given virtual address
342 #define pmd_index(address) \
343 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
346 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
348 * this macro returns the index of the entry in the pte page which would
349 * control the given virtual address
351 #define pte_index(address) \
352 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
353 #define pte_offset_kernel(dir, address) \
354 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
356 #if defined(CONFIG_HIGHPTE)
357 #define pte_offset_map(dir, address) \
358 ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
359 #define pte_offset_map_nested(dir, address) \
360 ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
361 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
362 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
364 #define pte_offset_map(dir, address) \
365 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
366 #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
367 #define pte_unmap(pte) do { } while (0)
368 #define pte_unmap_nested(pte) do { } while (0)
372 * The i386 doesn't have any external MMU info: the kernel page
373 * tables contain all the necessary information.
375 * Also, we only update the dirty/accessed state if we set
376 * the dirty bit by hand in the kernel, since the hardware
377 * will do the accessed bit for us, and we don't want to
378 * race with other CPU's that might be updating the dirty
379 * bit at the same time.
381 #define update_mmu_cache(vma,address,pte) do { } while (0)
382 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
383 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
386 (__ptep)->pte_low = (__entry).pte_low; \
387 flush_tlb_page(__vma, __address); \
391 /* Encode and de-code a swap entry */
392 #define __swp_type(x) (((x).val >> 1) & 0x1f)
393 #define __swp_offset(x) ((x).val >> 8)
394 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
395 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
396 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
398 #endif /* !__ASSEMBLY__ */
400 #ifndef CONFIG_DISCONTIGMEM
401 #define kern_addr_valid(addr) (1)
402 #endif /* !CONFIG_DISCONTIGMEM */
404 #define io_remap_page_range remap_page_range
406 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
407 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
408 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
409 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
410 #define __HAVE_ARCH_PTEP_MKDIRTY
411 #define __HAVE_ARCH_PTE_SAME
412 #include <asm-generic/pgtable.h>
415 * The size of the low 1:1 mappings we use during bootup,
416 * SMP-boot and ACPI-sleep:
418 #define LOW_MAPPINGS_SIZE (16*1024*1024)
421 #endif /* _I386_PGTABLE_H */