2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
23 /* flag for disabling the tsc */
24 extern int tsc_disable;
30 #define desc_empty(desc) \
31 (!((desc)->a + (desc)->b))
33 #define desc_equal(desc1, desc2) \
34 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36 * Default implementation of macro that returns current
37 * instruction pointer ("program counter").
39 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
42 * CPU type and hardware bug flags. Kept separately for each CPU.
43 * Members of this structure are referenced in head.S, so think twice
44 * before touching them. [mj]
48 __u8 x86; /* CPU family */
49 __u8 x86_vendor; /* CPU vendor */
52 char wp_works_ok; /* It doesn't on 386's */
53 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
56 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
57 unsigned long x86_capability[NCAPINTS];
58 char x86_vendor_id[16];
59 char x86_model_id[64];
60 int x86_cache_size; /* in KB - valid for CPUS which support this
62 int x86_cache_alignment; /* In bytes */
66 unsigned long loops_per_jiffy;
67 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
69 #define X86_VENDOR_INTEL 0
70 #define X86_VENDOR_CYRIX 1
71 #define X86_VENDOR_AMD 2
72 #define X86_VENDOR_UMC 3
73 #define X86_VENDOR_NEXGEN 4
74 #define X86_VENDOR_CENTAUR 5
75 #define X86_VENDOR_RISE 6
76 #define X86_VENDOR_TRANSMETA 7
77 #define X86_VENDOR_NSC 8
78 #define X86_VENDOR_NUM 9
79 #define X86_VENDOR_UNKNOWN 0xff
82 * capabilities of CPUs
85 extern struct cpuinfo_x86 boot_cpu_data;
86 extern struct cpuinfo_x86 new_cpu_data;
87 extern struct tss_struct init_tss[NR_CPUS];
88 extern struct tss_struct doublefault_tss;
91 extern struct cpuinfo_x86 cpu_data[];
92 #define current_cpu_data cpu_data[smp_processor_id()]
94 #define cpu_data (&boot_cpu_data)
95 #define current_cpu_data boot_cpu_data
98 extern char ignore_fpu_irq;
100 extern void identify_cpu(struct cpuinfo_x86 *);
101 extern void print_cpu_info(struct cpuinfo_x86 *);
102 extern void dodgy_tsc(void);
107 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
108 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
109 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
110 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
111 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
112 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
113 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
114 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
115 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
116 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
117 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
118 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
119 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
120 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
121 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
122 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
123 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
126 * Generic CPUID function
128 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
139 * CPUID functions returning a single datum
141 static inline unsigned int cpuid_eax(unsigned int op)
151 static inline unsigned int cpuid_ebx(unsigned int op)
153 unsigned int eax, ebx;
156 : "=a" (eax), "=b" (ebx)
161 static inline unsigned int cpuid_ecx(unsigned int op)
163 unsigned int eax, ecx;
166 : "=a" (eax), "=c" (ecx)
171 static inline unsigned int cpuid_edx(unsigned int op)
173 unsigned int eax, edx;
176 : "=a" (eax), "=d" (edx)
182 #define load_cr3(pgdir) \
183 asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
187 * Intel CPU features in CR4
189 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
190 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
191 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
192 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
193 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
194 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
195 #define X86_CR4_MCE 0x0040 /* Machine check enable */
196 #define X86_CR4_PGE 0x0080 /* enable global pages */
197 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
198 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
199 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
202 * Save the cr4 feature set we're using (ie
203 * Pentium 4MB enable and PPro Global page
204 * enable), so that any CPU's that boot up
205 * after us can get the correct flags.
207 extern unsigned long mmu_cr4_features;
209 static inline void set_in_cr4 (unsigned long mask)
211 mmu_cr4_features |= mask;
212 __asm__("movl %%cr4,%%eax\n\t"
219 static inline void clear_in_cr4 (unsigned long mask)
221 mmu_cr4_features &= ~mask;
222 __asm__("movl %%cr4,%%eax\n\t"
230 * NSC/Cyrix CPU configuration register indexes
233 #define CX86_PCR0 0x20
234 #define CX86_GCR 0xb8
235 #define CX86_CCR0 0xc0
236 #define CX86_CCR1 0xc1
237 #define CX86_CCR2 0xc2
238 #define CX86_CCR3 0xc3
239 #define CX86_CCR4 0xe8
240 #define CX86_CCR5 0xe9
241 #define CX86_CCR6 0xea
242 #define CX86_CCR7 0xeb
243 #define CX86_PCR1 0xf0
244 #define CX86_DIR0 0xfe
245 #define CX86_DIR1 0xff
246 #define CX86_ARR_BASE 0xc4
247 #define CX86_RCR_BASE 0xdc
250 * NSC/Cyrix CPU indexed register access macros
253 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
255 #define setCx86(reg, data) do { \
257 outb((data), 0x23); \
261 * Bus types (default is ISA, but people can check others with these..)
265 static inline void __monitor(const void *eax, unsigned long ecx,
268 /* "monitor %eax,%ecx,%edx;" */
270 ".byte 0x0f,0x01,0xc8;"
271 : :"a" (eax), "c" (ecx), "d"(edx));
274 static inline void __mwait(unsigned long eax, unsigned long ecx)
276 /* "mwait %eax,%ecx;" */
278 ".byte 0x0f,0x01,0xc9;"
279 : :"a" (eax), "c" (ecx));
282 /* from system description table in BIOS. Mostly for MCA use, but
283 others may find it useful. */
284 extern unsigned int machine_id;
285 extern unsigned int machine_submodel_id;
286 extern unsigned int BIOS_revision;
287 extern unsigned int mca_pentium_flag;
290 * User space process size: 3GB (default).
292 #define TASK_SIZE (PAGE_OFFSET)
294 /* This decides where the kernel will search for a free chunk of vm
295 * space during mmap's.
297 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
302 #define IO_BITMAP_BITS 65536
303 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
304 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
305 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
306 #define INVALID_IO_BITMAP_OFFSET 0x8000
308 struct i387_fsave_struct {
316 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
317 long status; /* software status information */
320 struct i387_fxsave_struct {
331 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
332 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
334 } __attribute__ ((aligned (16)));
336 struct i387_soft_struct {
344 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
345 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
347 unsigned long entry_eip;
351 struct i387_fsave_struct fsave;
352 struct i387_fxsave_struct fxsave;
353 struct i387_soft_struct soft;
361 unsigned short back_link,__blh;
363 unsigned short ss0,__ss0h;
365 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
367 unsigned short ss2,__ss2h;
370 unsigned long eflags;
371 unsigned long eax,ecx,edx,ebx;
376 unsigned short es, __esh;
377 unsigned short cs, __csh;
378 unsigned short ss, __ssh;
379 unsigned short ds, __dsh;
380 unsigned short fs, __fsh;
381 unsigned short gs, __gsh;
382 unsigned short ldt, __ldth;
383 unsigned short trace, io_bitmap_base;
385 * The extra 1 is there because the CPU will access an
386 * additional byte beyond the end of the IO permission
387 * bitmap. The extra byte must be all 1 bits, and must
388 * be within the limit.
390 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
392 * pads the TSS to be cacheline-aligned (size is 0x100)
394 unsigned long __cacheline_filler[37];
396 * .. and then another 0x100 bytes for emergency kernel stack
398 unsigned long stack[64];
399 } __attribute__((packed));
401 #define ARCH_MIN_TASKALIGN 16
403 struct thread_struct {
404 /* cached TLS descriptors. */
405 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
407 unsigned long sysenter_cs;
412 /* Hardware debugging registers */
413 unsigned long debugreg[8]; /* %%db0-7 debug registers */
415 unsigned long cr2, trap_no, error_code;
416 /* floating point info */
417 union i387_union i387;
418 /* virtual 86 mode info */
419 struct vm86_struct __user * vm86_info;
420 unsigned long screen_bitmap;
421 unsigned long v86flags, v86mask, saved_esp0;
422 unsigned int saved_fs, saved_gs;
424 unsigned long *io_bitmap_ptr;
427 #define INIT_THREAD { \
429 .sysenter_cs = __KERNEL_CS, \
430 .io_bitmap_ptr = NULL, \
434 * Note that the .io_bitmap member must be extra-big. This is because
435 * the CPU will access an additional byte beyond the end of the IO
436 * permission bitmap. The extra byte must be all 1 bits, and must
437 * be within the limit.
440 .esp0 = sizeof(init_stack) + (long)&init_stack, \
441 .ss0 = __KERNEL_DS, \
442 .esp1 = sizeof(init_tss[0]) + (long)&init_tss[0], \
443 .ss1 = __KERNEL_CS, \
444 .ldt = GDT_ENTRY_LDT, \
445 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
446 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
449 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
451 tss->esp0 = thread->esp0;
452 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
453 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
454 tss->ss1 = thread->sysenter_cs;
455 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
459 #define start_thread(regs, new_eip, new_esp) do { \
460 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
462 regs->xds = __USER_DS; \
463 regs->xes = __USER_DS; \
464 regs->xss = __USER_DS; \
465 regs->xcs = __USER_CS; \
466 regs->eip = new_eip; \
467 regs->esp = new_esp; \
470 /* Forward declaration, a strange C thing */
474 /* Free all resources held by a thread. */
475 extern void release_thread(struct task_struct *);
477 /* Prepare to copy thread state - unlazy all lazy status */
478 extern void prepare_to_copy(struct task_struct *tsk);
481 * create a kernel thread without removing it from tasklists
483 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
485 extern unsigned long thread_saved_pc(struct task_struct *tsk);
486 void show_trace(struct task_struct *task, unsigned long *stack);
488 unsigned long get_wchan(struct task_struct *p);
490 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
491 #define KSTK_TOP(info) \
493 unsigned long *__ptr = (unsigned long *)(info); \
494 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
497 #define task_pt_regs(task) \
499 struct pt_regs *__regs__; \
500 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
504 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
505 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
508 struct microcode_header {
516 unsigned int datasize;
517 unsigned int totalsize;
518 unsigned int reserved[3];
522 struct microcode_header hdr;
523 unsigned int bits[0];
526 typedef struct microcode microcode_t;
527 typedef struct microcode_header microcode_header_t;
529 /* microcode format is extended from prescott processors */
530 struct extended_signature {
536 struct extended_sigtable {
539 unsigned int reserved[3];
540 struct extended_signature sigs[0];
542 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
543 #define MICROCODE_IOCFREE _IO('6',0)
545 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
546 static inline void rep_nop(void)
548 __asm__ __volatile__("rep;nop": : :"memory");
551 #define cpu_relax() rep_nop()
553 /* generic versions from gas */
554 #define GENERIC_NOP1 ".byte 0x90\n"
555 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
556 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
557 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
558 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
559 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
560 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
561 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
564 #define K8_NOP1 GENERIC_NOP1
565 #define K8_NOP2 ".byte 0x66,0x90\n"
566 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
567 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
568 #define K8_NOP5 K8_NOP3 K8_NOP2
569 #define K8_NOP6 K8_NOP3 K8_NOP3
570 #define K8_NOP7 K8_NOP4 K8_NOP3
571 #define K8_NOP8 K8_NOP4 K8_NOP4
574 /* uses eax dependencies (arbitary choice) */
575 #define K7_NOP1 GENERIC_NOP1
576 #define K7_NOP2 ".byte 0x8b,0xc0\n"
577 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
578 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
579 #define K7_NOP5 K7_NOP4 ASM_NOP1
580 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
581 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
582 #define K7_NOP8 K7_NOP7 ASM_NOP1
585 #define ASM_NOP1 K8_NOP1
586 #define ASM_NOP2 K8_NOP2
587 #define ASM_NOP3 K8_NOP3
588 #define ASM_NOP4 K8_NOP4
589 #define ASM_NOP5 K8_NOP5
590 #define ASM_NOP6 K8_NOP6
591 #define ASM_NOP7 K8_NOP7
592 #define ASM_NOP8 K8_NOP8
593 #elif defined(CONFIG_MK7)
594 #define ASM_NOP1 K7_NOP1
595 #define ASM_NOP2 K7_NOP2
596 #define ASM_NOP3 K7_NOP3
597 #define ASM_NOP4 K7_NOP4
598 #define ASM_NOP5 K7_NOP5
599 #define ASM_NOP6 K7_NOP6
600 #define ASM_NOP7 K7_NOP7
601 #define ASM_NOP8 K7_NOP8
603 #define ASM_NOP1 GENERIC_NOP1
604 #define ASM_NOP2 GENERIC_NOP2
605 #define ASM_NOP3 GENERIC_NOP3
606 #define ASM_NOP4 GENERIC_NOP4
607 #define ASM_NOP5 GENERIC_NOP5
608 #define ASM_NOP6 GENERIC_NOP6
609 #define ASM_NOP7 GENERIC_NOP7
610 #define ASM_NOP8 GENERIC_NOP8
613 #define ASM_NOP_MAX 8
615 /* Prefetch instructions for Pentium III and AMD Athlon */
616 /* It's not worth to care about 3dnow! prefetches for the K6
617 because they are microcoded there and very slow.
618 However we don't do prefetches for pre XP Athlons currently
619 That should be fixed. */
620 #define ARCH_HAS_PREFETCH
621 extern inline void prefetch(const void *x)
623 alternative_input(ASM_NOP4,
629 #define ARCH_HAS_PREFETCH
630 #define ARCH_HAS_PREFETCHW
631 #define ARCH_HAS_SPINLOCK_PREFETCH
633 /* 3dnow! prefetch to get an exclusive cache line. Useful for
634 spinlocks to avoid one state transition in the cache coherency protocol. */
635 extern inline void prefetchw(const void *x)
637 alternative_input(ASM_NOP4,
642 #define spin_lock_prefetch(x) prefetchw(x)
644 extern void select_idle_routine(const struct cpuinfo_x86 *c);
646 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
648 #ifdef CONFIG_SCHED_SMT
649 #define ARCH_HAS_SCHED_DOMAIN
650 #define ARCH_HAS_SCHED_WAKE_IDLE
653 #endif /* __ASM_I386_PROCESSOR_H */