include/asm-ia64/processor.h

   1 #ifndef _ASM_IA64_PROCESSOR_H
   2 #define _ASM_IA64_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 1998-2004 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *      Stephane Eranian <eranian@hpl.hp.com>
   8  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   9  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  10  *
  11  * 11/24/98     S.Eranian       added ia64_set_iva()
  12  * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
  13  * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
  14  */
  15
  16 #include <linux/config.h>
  17
  18 #include <asm/intrinsics.h>
  19 #include <asm/kregs.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/ustack.h>
  22
  23 /* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
  24 #define ARCH_HAS_SCHED_DOMAIN
  25
  26 #define IA64_NUM_DBG_REGS       8
  27 /*
  28  * Limits for PMC and PMD are set to less than maximum architected values
  29  * but should be sufficient for a while
  30  */
  31 #define IA64_NUM_PMC_REGS       32
  32 #define IA64_NUM_PMD_REGS       32
  33
  34 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
  35 #define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
  36
  37 /*
  38  * TASK_SIZE really is a mis-named.  It really is the maximum user
  39  * space address (plus one).  On IA-64, there are five regions of 2TB
  40  * each (assuming 8KB page size), for a total of 8TB of user virtual
  41  * address space.
  42  */
  43 #define TASK_SIZE               (current->thread.task_size)
  44
  45 /*
  46  * This decides where the kernel will search for a free chunk of vm
  47  * space during mmap's.
  48  */
  49 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
  50
  51 #define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
  52 #define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
  53 #define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
  54 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
  55 #define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
  56                                                         /* bit 5 is currently unused */
  57 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
  58 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
  59
  60 #define IA64_THREAD_UAC_SHIFT   3
  61 #define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
  62 #define IA64_THREAD_FPEMU_SHIFT 6
  63 #define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
  64
  65
  66 /*
  67  * This shift should be large enough to be able to represent 1000000000/itc_freq with good
  68  * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
  69  * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
  70  */
  71 #define IA64_NSEC_PER_CYC_SHIFT 30
  72
  73 #ifndef __ASSEMBLY__
  74
  75 #include <linux/cache.h>
  76 #include <linux/compiler.h>
  77 #include <linux/threads.h>
  78 #include <linux/types.h>
  79
  80 #include <asm/fpu.h>
  81 #include <asm/page.h>
  82 #include <asm/percpu.h>
  83 #include <asm/rse.h>
  84 #include <asm/unwind.h>
  85 #include <asm/atomic.h>
  86 #ifdef CONFIG_NUMA
  87 #include <asm/nodedata.h>
  88 #endif
  89
  90 /* like above but expressed as bitfields for more efficient access: */
  91 struct ia64_psr {
  92         __u64 reserved0 : 1;
  93         __u64 be : 1;
  94         __u64 up : 1;
  95         __u64 ac : 1;
  96         __u64 mfl : 1;
  97         __u64 mfh : 1;
  98         __u64 reserved1 : 7;
  99         __u64 ic : 1;
 100         __u64 i : 1;
 101         __u64 pk : 1;
 102         __u64 reserved2 : 1;
 103         __u64 dt : 1;
 104         __u64 dfl : 1;
 105         __u64 dfh : 1;
 106         __u64 sp : 1;
 107         __u64 pp : 1;
 108         __u64 di : 1;
 109         __u64 si : 1;
 110         __u64 db : 1;
 111         __u64 lp : 1;
 112         __u64 tb : 1;
 113         __u64 rt : 1;
 114         __u64 reserved3 : 4;
 115         __u64 cpl : 2;
 116         __u64 is : 1;
 117         __u64 mc : 1;
 118         __u64 it : 1;
 119         __u64 id : 1;
 120         __u64 da : 1;
 121         __u64 dd : 1;
 122         __u64 ss : 1;
 123         __u64 ri : 2;
 124         __u64 ed : 1;
 125         __u64 bn : 1;
 126         __u64 reserved4 : 19;
 127 };
 128
 129 /*
 130  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 131  * state comes earlier:
 132  */
 133 struct cpuinfo_ia64 {
 134         __u32 softirq_pending;
 135         __u64 itm_delta;        /* # of clock cycles between clock ticks */
 136         __u64 itm_next;         /* interval timer mask value to use for next clock tick */
 137         __u64 nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
 138         __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
 139         __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
 140         __u64 itc_freq;         /* frequency of ITC counter */
 141         __u64 proc_freq;        /* frequency of processor */
 142         __u64 cyc_per_usec;     /* itc_freq/1000000 */
 143         __u64 ptce_base;
 144         __u32 ptce_count[2];
 145         __u32 ptce_stride[2];
 146         struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
 147
 148 #ifdef CONFIG_SMP
 149         __u64 loops_per_jiffy;
 150         int cpu;
 151         __u32 socket_id;        /* physical processor socket id */
 152         __u16 core_id;          /* core id */
 153         __u16 thread_id;        /* thread id */
 154         __u16 num_log;          /* Total number of logical processors on
 155                                  * this socket that were successfully booted */
 156         __u8  cores_per_socket; /* Cores per processor socket */
 157         __u8  threads_per_core; /* Threads per core */
 158 #endif
 159
 160         /* CPUID-derived information: */
 161         __u64 ppn;
 162         __u64 features;
 163         __u8 number;
 164         __u8 revision;
 165         __u8 model;
 166         __u8 family;
 167         __u8 archrev;
 168         char vendor[16];
 169
 170 #ifdef CONFIG_NUMA
 171         struct ia64_node_data *node_data;
 172 #endif
 173 };
 174
 175 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
 176
 177 /*
 178  * The "local" data variable.  It refers to the per-CPU data of the currently executing
 179  * CPU, much like "current" points to the per-task data of the currently executing task.
 180  * Do not use the address of local_cpu_data, since it will be different from
 181  * cpu_data(smp_processor_id())!
 182  */
 183 #define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
 184 #define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
 185
 186 extern void identify_cpu (struct cpuinfo_ia64 *);
 187 extern void print_cpu_info (struct cpuinfo_ia64 *);
 188
 189 typedef struct {
 190         unsigned long seg;
 191 } mm_segment_t;
 192
 193 #define SET_UNALIGN_CTL(task,value)                                                             \
 194 ({                                                                                              \
 195         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
 196                                 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
 197         0;                                                                                      \
 198 })
 199 #define GET_UNALIGN_CTL(task,addr)                                                              \
 200 ({                                                                                              \
 201         put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
 202                  (int __user *) (addr));                                                        \
 203 })
 204
 205 #define SET_FPEMU_CTL(task,value)                                                               \
 206 ({                                                                                              \
 207         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
 208                           | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
 209         0;                                                                                      \
 210 })
 211 #define GET_FPEMU_CTL(task,addr)                                                                \
 212 ({                                                                                              \
 213         put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
 214                  (int __user *) (addr));                                                        \
 215 })
 216
 217 #ifdef CONFIG_IA32_SUPPORT
 218 struct desc_struct {
 219         unsigned int a, b;
 220 };
 221
 222 #define desc_empty(desc)                (!((desc)->a + (desc)->b))
 223 #define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
 224
 225 #define GDT_ENTRY_TLS_ENTRIES   3
 226 #define GDT_ENTRY_TLS_MIN       6
 227 #define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
 228
 229 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
 230
 231 struct partial_page_list;
 232 #endif
 233
 234 struct thread_struct {
 235         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
 236         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
 237         __u8 on_ustack;                 /* executing on user-stacks? */
 238         __u8 pad[3];
 239         __u64 ksp;                      /* kernel stack pointer */
 240         __u64 map_base;                 /* base address for get_unmapped_area() */
 241         __u64 task_size;                /* limit for task size */
 242         __u64 rbs_bot;                  /* the base address for the RBS */
 243         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
 244
 245 #ifdef CONFIG_IA32_SUPPORT
 246         __u64 eflag;                    /* IA32 EFLAGS reg */
 247         __u64 fsr;                      /* IA32 floating pt status reg */
 248         __u64 fcr;                      /* IA32 floating pt control reg */
 249         __u64 fir;                      /* IA32 fp except. instr. reg */
 250         __u64 fdr;                      /* IA32 fp except. data reg */
 251         __u64 old_k1;                   /* old value of ar.k1 */
 252         __u64 old_iob;                  /* old IOBase value */
 253         struct partial_page_list *ppl;  /* partial page list for 4K page size issue */
 254         /* cached TLS descriptors. */
 255         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 256
 257 # define INIT_THREAD_IA32       .eflag =        0,                      \
 258                                 .fsr =          0,                      \
 259                                 .fcr =          0x17800000037fULL,      \
 260                                 .fir =          0,                      \
 261                                 .fdr =          0,                      \
 262                                 .old_k1 =       0,                      \
 263                                 .old_iob =      0,                      \
 264                                 .ppl =          NULL,
 265 #else
 266 # define INIT_THREAD_IA32
 267 #endif /* CONFIG_IA32_SUPPORT */
 268 #ifdef CONFIG_PERFMON
 269         __u64 pmcs[IA64_NUM_PMC_REGS];
 270         __u64 pmds[IA64_NUM_PMD_REGS];
 271         void *pfm_context;                   /* pointer to detailed PMU context */
 272         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
 273 # define INIT_THREAD_PM         .pmcs =                 {0UL, },  \
 274                                 .pmds =                 {0UL, },  \
 275                                 .pfm_context =          NULL,     \
 276                                 .pfm_needs_checking =   0UL,
 277 #else
 278 # define INIT_THREAD_PM
 279 #endif
 280         __u64 dbr[IA64_NUM_DBG_REGS];
 281         __u64 ibr[IA64_NUM_DBG_REGS];
 282         struct ia64_fpreg fph[96];      /* saved/loaded on demand */
 283 };
 284
 285 #define INIT_THREAD {                                           \
 286         .flags =        0,                                      \
 287         .on_ustack =    0,                                      \
 288         .ksp =          0,                                      \
 289         .map_base =     DEFAULT_MAP_BASE,                       \
 290         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
 291         .task_size =    DEFAULT_TASK_SIZE,                      \
 292         .last_fph_cpu =  -1,                                    \
 293         INIT_THREAD_IA32                                        \
 294         INIT_THREAD_PM                                          \
 295         .dbr =          {0, },                                  \
 296         .ibr =          {0, },                                  \
 297         .fph =          {{{{0}}}, }                             \
 298 }
 299
 300 #define start_thread(regs,new_ip,new_sp) do {                                                   \
 301         set_fs(USER_DS);                                                                        \
 302         regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
 303                          & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
 304         regs->cr_iip = new_ip;                                                                  \
 305         regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
 306         regs->ar_rnat = 0;                                                                      \
 307         regs->ar_bspstore = current->thread.rbs_bot;                                            \
 308         regs->ar_fpsr = FPSR_DEFAULT;                                                           \
 309         regs->loadrs = 0;                                                                       \
 310         regs->r8 = current->mm->dumpable;       /* set "don't zap registers" flag */            \
 311         regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
 312         if (unlikely(!current->mm->dumpable)) {                                                 \
 313                 /*                                                                              \
 314                  * Zap scratch regs to avoid leaking bits between processes with different      \
 315                  * uid/privileges.                                                              \
 316                  */                                                                             \
 317                 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
 318                 regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
 319         }                                                                                       \
 320 } while (0)
 321
 322 /* Forward declarations, a strange C thing... */
 323 struct mm_struct;
 324 struct task_struct;
 325
 326 /*
 327  * Free all resources held by a thread. This is called after the
 328  * parent of DEAD_TASK has collected the exit status of the task via
 329  * wait().
 330  */
 331 #define release_thread(dead_task)
 332
 333 /* Prepare to copy thread state - unlazy all lazy status */
 334 #define prepare_to_copy(tsk)    do { } while (0)
 335
 336 /*
 337  * This is the mechanism for creating a new kernel thread.
 338  *
 339  * NOTE 1: Only a kernel-only process (ie the swapper or direct
 340  * descendants who haven't done an "execve()") should use this: it
 341  * will work within a system call from a "real" process, but the
 342  * process memory space will not be free'd until both the parent and
 343  * the child have exited.
 344  *
 345  * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
 346  * into trouble in init/main.c when the child thread returns to
 347  * do_basic_setup() and the timing is such that free_initmem() has
 348  * been called already.
 349  */
 350 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
 351
 352 /* Get wait channel for task P.  */
 353 extern unsigned long get_wchan (struct task_struct *p);
 354
 355 /* Return instruction pointer of blocked task TSK.  */
 356 #define KSTK_EIP(tsk)                                   \
 357   ({                                                    \
 358         struct pt_regs *_regs = ia64_task_regs(tsk);    \
 359         _regs->cr_iip + ia64_psr(_regs)->ri;            \
 360   })
 361
 362 /* Return stack pointer of blocked task TSK.  */
 363 #define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
 364
 365 extern void ia64_getreg_unknown_kr (void);
 366 extern void ia64_setreg_unknown_kr (void);
 367
 368 #define ia64_get_kr(regnum)                                     \
 369 ({                                                              \
 370         unsigned long r = 0;                                    \
 371                                                                 \
 372         switch (regnum) {                                       \
 373             case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
 374             case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
 375             case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
 376             case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
 377             case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
 378             case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
 379             case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
 380             case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
 381             default: ia64_getreg_unknown_kr(); break;           \
 382         }                                                       \
 383         r;                                                      \
 384 })
 385
 386 #define ia64_set_kr(regnum, r)                                  \
 387 ({                                                              \
 388         switch (regnum) {                                       \
 389             case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
 390             case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
 391             case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
 392             case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
 393             case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
 394             case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
 395             case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
 396             case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
 397             default: ia64_setreg_unknown_kr(); break;           \
 398         }                                                       \
 399 })
 400
 401 /*
 402  * The following three macros can't be inline functions because we don't have struct
 403  * task_struct at this point.
 404  */
 405
 406 /*
 407  * Return TRUE if task T owns the fph partition of the CPU we're running on.
 408  * Must be called from code that has preemption disabled.
 409  */
 410 #define ia64_is_local_fpu_owner(t)                                                              \
 411 ({                                                                                              \
 412         struct task_struct *__ia64_islfo_task = (t);                                            \
 413         (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
 414          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
 415 })
 416
 417 /*
 418  * Mark task T as owning the fph partition of the CPU we're running on.
 419  * Must be called from code that has preemption disabled.
 420  */
 421 #define ia64_set_local_fpu_owner(t) do {                                                \
 422         struct task_struct *__ia64_slfo_task = (t);                                     \
 423         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
 424         ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
 425 } while (0)
 426
 427 /* Mark the fph partition of task T as being invalid on all CPUs.  */
 428 #define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
 429
 430 extern void __ia64_init_fpu (void);
 431 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
 432 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 433 extern void ia64_save_debug_regs (unsigned long *save_area);
 434 extern void ia64_load_debug_regs (unsigned long *save_area);
 435
 436 #ifdef CONFIG_IA32_SUPPORT
 437 extern void ia32_save_state (struct task_struct *task);
 438 extern void ia32_load_state (struct task_struct *task);
 439 #endif
 440
 441 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 442 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 443
 444 /* load fp 0.0 into fph */
 445 static inline void
 446 ia64_init_fpu (void) {
 447         ia64_fph_enable();
 448         __ia64_init_fpu();
 449         ia64_fph_disable();
 450 }
 451
 452 /* save f32-f127 at FPH */
 453 static inline void
 454 ia64_save_fpu (struct ia64_fpreg *fph) {
 455         ia64_fph_enable();
 456         __ia64_save_fpu(fph);
 457         ia64_fph_disable();
 458 }
 459
 460 /* load f32-f127 from FPH */
 461 static inline void
 462 ia64_load_fpu (struct ia64_fpreg *fph) {
 463         ia64_fph_enable();
 464         __ia64_load_fpu(fph);
 465         ia64_fph_disable();
 466 }
 467
 468 static inline __u64
 469 ia64_clear_ic (void)
 470 {
 471         __u64 psr;
 472         psr = ia64_getreg(_IA64_REG_PSR);
 473         ia64_stop();
 474         ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
 475         ia64_srlz_i();
 476         return psr;
 477 }
 478
 479 /*
 480  * Restore the psr.
 481  */
 482 static inline void
 483 ia64_set_psr (__u64 psr)
 484 {
 485         ia64_stop();
 486         ia64_setreg(_IA64_REG_PSR_L, psr);
 487         ia64_srlz_d();
 488 }
 489
 490 /*
 491  * Insert a translation into an instruction and/or data translation
 492  * register.
 493  */
 494 static inline void
 495 ia64_itr (__u64 target_mask, __u64 tr_num,
 496           __u64 vmaddr, __u64 pte,
 497           __u64 log_page_size)
 498 {
 499         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 500         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 501         ia64_stop();
 502         if (target_mask & 0x1)
 503                 ia64_itri(tr_num, pte);
 504         if (target_mask & 0x2)
 505                 ia64_itrd(tr_num, pte);
 506 }
 507
 508 /*
 509  * Insert a translation into the instruction and/or data translation
 510  * cache.
 511  */
 512 static inline void
 513 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
 514           __u64 log_page_size)
 515 {
 516         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 517         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 518         ia64_stop();
 519         /* as per EAS2.6, itc must be the last instruction in an instruction group */
 520         if (target_mask & 0x1)
 521                 ia64_itci(pte);
 522         if (target_mask & 0x2)
 523                 ia64_itcd(pte);
 524 }
 525
 526 /*
 527  * Purge a range of addresses from instruction and/or data translation
 528  * register(s).
 529  */
 530 static inline void
 531 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
 532 {
 533         if (target_mask & 0x1)
 534                 ia64_ptri(vmaddr, (log_size << 2));
 535         if (target_mask & 0x2)
 536                 ia64_ptrd(vmaddr, (log_size << 2));
 537 }
 538
 539 /* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
 540 static inline void
 541 ia64_set_iva (void *ivt_addr)
 542 {
 543         ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
 544         ia64_srlz_i();
 545 }
 546
 547 /* Set the page table address and control bits.  */
 548 static inline void
 549 ia64_set_pta (__u64 pta)
 550 {
 551         /* Note: srlz.i implies srlz.d */
 552         ia64_setreg(_IA64_REG_CR_PTA, pta);
 553         ia64_srlz_i();
 554 }
 555
 556 static inline void
 557 ia64_eoi (void)
 558 {
 559         ia64_setreg(_IA64_REG_CR_EOI, 0);
 560         ia64_srlz_d();
 561 }
 562
 563 #define cpu_relax()     ia64_hint(ia64_hint_pause)
 564
 565 static inline void
 566 ia64_set_lrr0 (unsigned long val)
 567 {
 568         ia64_setreg(_IA64_REG_CR_LRR0, val);
 569         ia64_srlz_d();
 570 }
 571
 572 static inline void
 573 ia64_set_lrr1 (unsigned long val)
 574 {
 575         ia64_setreg(_IA64_REG_CR_LRR1, val);
 576         ia64_srlz_d();
 577 }
 578
 579
 580 /*
 581  * Given the address to which a spill occurred, return the unat bit
 582  * number that corresponds to this address.
 583  */
 584 static inline __u64
 585 ia64_unat_pos (void *spill_addr)
 586 {
 587         return ((__u64) spill_addr >> 3) & 0x3f;
 588 }
 589
 590 /*
 591  * Set the NaT bit of an integer register which was spilled at address
 592  * SPILL_ADDR.  UNAT is the mask to be updated.
 593  */
 594 static inline void
 595 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
 596 {
 597         __u64 bit = ia64_unat_pos(spill_addr);
 598         __u64 mask = 1UL << bit;
 599
 600         *unat = (*unat & ~mask) | (nat << bit);
 601 }
 602
 603 /*
 604  * Return saved PC of a blocked thread.
 605  * Note that the only way T can block is through a call to schedule() -> switch_to().
 606  */
 607 static inline unsigned long
 608 thread_saved_pc (struct task_struct *t)
 609 {
 610         struct unw_frame_info info;
 611         unsigned long ip;
 612
 613         unw_init_from_blocked_task(&info, t);
 614         if (unw_unwind(&info) < 0)
 615                 return 0;
 616         unw_get_ip(&info, &ip);
 617         return ip;
 618 }
 619
 620 /*
 621  * Get the current instruction/program counter value.
 622  */
 623 #define current_text_addr() \
 624         ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
 625
 626 static inline __u64
 627 ia64_get_ivr (void)
 628 {
 629         __u64 r;
 630         ia64_srlz_d();
 631         r = ia64_getreg(_IA64_REG_CR_IVR);
 632         ia64_srlz_d();
 633         return r;
 634 }
 635
 636 static inline void
 637 ia64_set_dbr (__u64 regnum, __u64 value)
 638 {
 639         __ia64_set_dbr(regnum, value);
 640 #ifdef CONFIG_ITANIUM
 641         ia64_srlz_d();
 642 #endif
 643 }
 644
 645 static inline __u64
 646 ia64_get_dbr (__u64 regnum)
 647 {
 648         __u64 retval;
 649
 650         retval = __ia64_get_dbr(regnum);
 651 #ifdef CONFIG_ITANIUM
 652         ia64_srlz_d();
 653 #endif
 654         return retval;
 655 }
 656
 657 static inline __u64
 658 ia64_rotr (__u64 w, __u64 n)
 659 {
 660         return (w >> n) | (w << (64 - n));
 661 }
 662
 663 #define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
 664
 665 /*
 666  * Take a mapped kernel address and return the equivalent address
 667  * in the region 7 identity mapped virtual area.
 668  */
 669 static inline void *
 670 ia64_imva (void *addr)
 671 {
 672         void *result;
 673         result = (void *) ia64_tpa(addr);
 674         return __va(result);
 675 }
 676
 677 #define ARCH_HAS_PREFETCH
 678 #define ARCH_HAS_PREFETCHW
 679 #define ARCH_HAS_SPINLOCK_PREFETCH
 680 #define PREFETCH_STRIDE                 L1_CACHE_BYTES
 681
 682 static inline void
 683 prefetch (const void *x)
 684 {
 685          ia64_lfetch(ia64_lfhint_none, x);
 686 }
 687
 688 static inline void
 689 prefetchw (const void *x)
 690 {
 691         ia64_lfetch_excl(ia64_lfhint_none, x);
 692 }
 693
 694 #define spin_lock_prefetch(x)   prefetchw(x)
 695
 696 extern unsigned long boot_option_idle_override;
 697
 698 #endif /* !__ASSEMBLY__ */
 699
 700 #endif /* _ASM_IA64_PROCESSOR_H */