include/asm-ia64/sn/pci/bridge.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_SN_PCI_BRIDGE_H
   9 #define _ASM_SN_PCI_BRIDGE_H
  10
  11
  12 /*
  13  * bridge.h - header file for bridge chip and bridge portion of xbridge chip
  14  *
  15  * Also including offsets for unique PIC registers.
  16  * The PIC asic is a follow-on to Xbridge and most of its registers are
  17  * identical to those of Xbridge.  PIC is different than Xbridge in that
  18  * it will accept 64 bit register access and that, in some cases, data
  19  * is kept in bits 63:32.   PIC registers that are identical to Xbridge
  20  * may be accessed identically to the Xbridge registers, allowing for lots
  21  * of code reuse.  Here are the access rules as described in the PIC
  22  * manual:
  23  *
  24  *      o Read a word on a DW boundary returns D31:00 of reg.
  25  *      o Read a DW on a DW boundary returns D63:00 of reg.
  26  *      o Write a word on a DW boundary loads D31:00 of reg.
  27  *      o Write a DW on a DW boundary loads D63:00 of reg.
  28  *      o No support for word boundary access that is not double word
  29  *           aligned.
  30  *
  31  * So we can reuse a lot of bridge_s for PIC.  In bridge_s are included
  32  * #define tags and unions for 64 bit access to PIC registers.
  33  * For a detailed PIC register layout see pic.h.
  34  */
  35
  36 #include <linux/config.h>
  37 #include <asm/sn/xtalk/xwidget.h>
  38 #include <asm/sn/pci/pic.h>
  39
  40 #define BRIDGE_REG_GET32(reg) \
  41                 __swab32( *(volatile uint32_t *) (((uint64_t)reg)^4) )
  42
  43 #define BRIDGE_REG_SET32(reg) \
  44                 *(volatile uint32_t *) (((uint64_t)reg)^4)
  45
  46 /* I/O page size */
  47
  48 #if PAGE_SIZE == 4096
  49 #define IOPFNSHIFT              12      /* 4K per mapped page */
  50 #else
  51 #define IOPFNSHIFT              14      /* 16K per mapped page */
  52 #endif                          /* PAGE_SIZE */
  53
  54 #define IOPGSIZE                (1 << IOPFNSHIFT)
  55 #define IOPG(x)                 ((x) >> IOPFNSHIFT)
  56 #define IOPGOFF(x)              ((x) & (IOPGSIZE-1))
  57
  58 /* Bridge RAM sizes */
  59
  60 #define BRIDGE_INTERNAL_ATES    128
  61 #define XBRIDGE_INTERNAL_ATES   1024
  62
  63 #define BRIDGE_ATE_RAM_SIZE     (BRIDGE_INTERNAL_ATES<<3)       /* 1kB ATE */
  64 #define XBRIDGE_ATE_RAM_SIZE    (XBRIDGE_INTERNAL_ATES<<3)      /* 8kB ATE */
  65
  66 #define PIC_WR_REQ_BUFSIZE      256
  67
  68 #define BRIDGE_CONFIG_BASE      0x20000         /* start of bridge's */
  69                                                 /* map to each device's */
  70                                                 /* config space */
  71 #define BRIDGE_CONFIG1_BASE     0x28000         /* type 1 device config space */
  72 #define BRIDGE_CONFIG_END       0x30000
  73 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000          /* each map == 4k */
  74
  75 #define BRIDGE_SSRAM_512K       0x00080000      /* 512kB */
  76 #define BRIDGE_SSRAM_128K       0x00020000      /* 128kB */
  77 #define BRIDGE_SSRAM_64K        0x00010000      /* 64kB */
  78 #define BRIDGE_SSRAM_0K         0x00000000      /* 0kB */
  79
  80 /* ========================================================================
  81  *    Bridge address map
  82  */
  83
  84 #ifndef __ASSEMBLY__
  85
  86 #ifdef __cplusplus
  87 extern "C" {
  88 #endif
  89
  90 /*
  91  * All accesses to bridge hardware registers must be done
  92  * using 32-bit loads and stores.
  93  */
  94 typedef uint32_t        bridgereg_t;
  95
  96 typedef uint64_t        bridge_ate_t;
  97
  98 /* pointers to bridge ATEs
  99  * are always "pointer to volatile"
 100  */
 101 typedef volatile bridge_ate_t  *bridge_ate_p;
 102
 103 /*
 104  * It is generally preferred that hardware registers on the bridge
 105  * are located from C code via this structure.
 106  *
 107  * Generated from Bridge spec dated 04oct95
 108  */
 109
 110
 111 /*
 112  * pic_widget_cfg_s is a local definition of widget_cfg_t but with
 113  * a union of 64bit & 32bit registers, since PIC has 64bit widget
 114  * registers but BRIDGE and XBRIDGE have 32bit.  PIC registers that
 115  * have valid bits (ie. not just reserved) in the upper 32bits are
 116  * defined as a union so we can access them as 64bit for PIC and
 117  * as 32bit for BRIDGE and XBRIDGE.
 118  */
 119 typedef volatile struct pic_widget_cfg_s {
 120     bridgereg_t             _b_wid_id;              /* 0x000004 */
 121     bridgereg_t             _pad_000000;
 122
 123     union {
 124         picreg_t            _p_wid_stat;            /* 0x000008 */
 125         struct {
 126             bridgereg_t     _b_wid_stat;            /* 0x00000C */
 127             bridgereg_t     _b_pad_000008;
 128         } _b;
 129     } u_wid_stat;
 130     #define __p_wid_stat_64 u_wid_stat._p_wid_stat
 131     #define __b_wid_stat u_wid_stat._b._b_wid_stat
 132
 133     bridgereg_t             _b_wid_err_upper;       /* 0x000014 */
 134     bridgereg_t             _pad_000010;
 135
 136     union {
 137         picreg_t            _p_wid_err_lower;       /* 0x000018 */
 138         struct {
 139             bridgereg_t     _b_wid_err_lower;       /* 0x00001C */
 140             bridgereg_t     _b_pad_000018;
 141         } _b;
 142     } u_wid_err_lower;
 143     #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower
 144     #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower
 145
 146     union {
 147         picreg_t            _p_wid_control;         /* 0x000020 */
 148         struct {
 149             bridgereg_t     _b_wid_control;         /* 0x000024 */
 150             bridgereg_t     _b_pad_000020;
 151         } _b;
 152     } u_wid_control;
 153     #define __p_wid_control_64 u_wid_control._p_wid_control
 154     #define __b_wid_control u_wid_control._b._b_wid_control
 155
 156     bridgereg_t             _b_wid_req_timeout;     /* 0x00002C */
 157     bridgereg_t             _pad_000028;
 158
 159     bridgereg_t             _b_wid_int_upper;       /* 0x000034 */
 160     bridgereg_t             _pad_000030;
 161
 162     union {
 163         picreg_t            _p_wid_int_lower;       /* 0x000038 */
 164         struct {
 165             bridgereg_t     _b_wid_int_lower;       /* 0x00003C */
 166             bridgereg_t     _b_pad_000038;
 167         } _b;
 168     } u_wid_int_lower;
 169     #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower
 170     #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower
 171
 172     bridgereg_t             _b_wid_err_cmdword;     /* 0x000044 */
 173     bridgereg_t             _pad_000040;
 174
 175     bridgereg_t             _b_wid_llp;             /* 0x00004C */
 176     bridgereg_t             _pad_000048;
 177
 178     bridgereg_t             _b_wid_tflush;          /* 0x000054 */
 179     bridgereg_t             _pad_000050;
 180 } pic_widget_cfg_t;
 181
 182 /*
 183  * BRIDGE, XBRIDGE, PIC register definitions.  NOTE: Prior to PIC, registers
 184  * were a 32bit quantity and double word aligned (and only accessible as a
 185  * 32bit word.  PIC registers are 64bits and accessible as words or double
 186  * words.  PIC registers that have valid bits (ie. not just reserved) in the
 187  * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit
 188  * bridgereg_t so we can access them both ways.
 189  *
 190  * It is generally preferred that hardware registers on the bridge are
 191  * located from C code via this structure.
 192  *
 193  * Generated from Bridge spec dated 04oct95
 194  */
 195
 196 typedef volatile struct bridge_s {
 197
 198     /* 0x000000-0x00FFFF -- Local Registers */
 199
 200     /* 0x000000-0x000057 -- Standard Widget Configuration */
 201     union {
 202         widget_cfg_t        xtalk_widget_def;       /* 0x000000 */
 203         pic_widget_cfg_t    local_widget_def;       /* 0x000000 */
 204     } u_wid;
 205
 206     /* 32bit widget register access via the widget_cfg_t */
 207     #define b_widget u_wid.xtalk_widget_def
 208
 209     /* 32bit widget register access via the pic_widget_cfg_t */
 210     #define b_wid_id u_wid.local_widget_def._b_wid_id
 211     #define b_wid_stat u_wid.local_widget_def.__b_wid_stat
 212     #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper
 213     #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower
 214     #define b_wid_control u_wid.local_widget_def.__b_wid_control
 215     #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout
 216     #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper
 217     #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower
 218     #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword
 219     #define b_wid_llp u_wid.local_widget_def._b_wid_llp
 220     #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush
 221
 222     /* 64bit widget register access via the pic_widget_cfg_t */
 223     #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64
 224     #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64
 225     #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64
 226     #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64
 227
 228     /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
 229     bridgereg_t             b_wid_aux_err;          /* 0x00005C */
 230     bridgereg_t             _pad_000058;
 231
 232     bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
 233     bridgereg_t             _pad_000060;
 234
 235     union {
 236         picreg_t            _p_wid_resp_lower;      /* 0x000068 */
 237         struct {
 238             bridgereg_t     _b_wid_resp_lower;      /* 0x00006C */
 239             bridgereg_t     _b_pad_000068;
 240         } _b;
 241     } u_wid_resp_lower;
 242     #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower
 243     #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower
 244
 245     bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
 246     bridgereg_t             _pad_000070;
 247
 248     union {
 249         picreg_t            _p_addr_lkerr;          /* 0x000078 */
 250         struct {
 251             bridgereg_t     _b_pad_00007C;
 252             bridgereg_t     _b_pad_000078;
 253         } _b;
 254     } u_addr_lkerr;
 255     #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr
 256
 257     /* 0x000080-0x00008F -- PMU */
 258     bridgereg_t             b_dir_map;              /* 0x000084 */
 259     bridgereg_t             _pad_000080;
 260
 261     bridgereg_t             _pad_00008C;
 262     bridgereg_t             _pad_000088;
 263
 264     /* 0x000090-0x00009F -- SSRAM */
 265     bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
 266     bridgereg_t             _pad_000090;
 267     #define b_ram_perr  b_ram_perr_or_map_fault     /* Bridge */
 268     #define b_map_fault b_ram_perr_or_map_fault     /* Xbridge & PIC */
 269
 270     bridgereg_t             _pad_00009C;
 271     bridgereg_t             _pad_000098;
 272
 273     /* 0x0000A0-0x0000AF -- Arbitration */
 274     bridgereg_t             b_arb;                  /* 0x0000A4 */
 275     bridgereg_t             _pad_0000A0;
 276
 277     bridgereg_t             _pad_0000AC;
 278     bridgereg_t             _pad_0000A8;
 279
 280     /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
 281     union {
 282         picreg_t            _p_ate_parity_err;      /* 0x0000B0 */
 283         struct {
 284             bridgereg_t     _b_nic;                 /* 0x0000B4 */
 285             bridgereg_t     _b_pad_0000B0;
 286         } _b;
 287     } u_ate_parity_err_or_nic;
 288     #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err
 289     #define b_nic u_ate_parity_err_or_nic._b._b_nic
 290
 291     bridgereg_t             _pad_0000BC;
 292     bridgereg_t             _pad_0000B8;
 293
 294     /* 0x0000C0-0x0000FF -- PCI/GIO */
 295     bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
 296     bridgereg_t             _pad_0000C0;
 297     #define b_pci_bus_timeout b_bus_timeout
 298
 299     bridgereg_t             b_pci_cfg;              /* 0x0000CC */
 300     bridgereg_t             _pad_0000C8;
 301
 302     bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
 303     bridgereg_t             _pad_0000D0;
 304     #define b_gio_err_upper b_pci_err_upper
 305
 306     union {
 307         picreg_t            _p_pci_err_lower;       /* 0x0000D8 */
 308         struct {
 309             bridgereg_t     _b_pci_err_lower;       /* 0x0000DC */
 310             bridgereg_t     _b_pad_0000D8;
 311         } _b;
 312     } u_pci_err_lower;
 313     #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower
 314     #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower
 315     #define b_gio_err_lower b_pci_err_lower
 316
 317     bridgereg_t             _pad_0000E0[8];
 318
 319     /* 0x000100-0x0001FF -- Interrupt */
 320     union {
 321         picreg_t            _p_int_status;          /* 0x000100 */
 322         struct {
 323             bridgereg_t     _b_int_status;          /* 0x000104 */
 324             bridgereg_t     _b_pad_000100;
 325         } _b;
 326     } u_int_status;
 327     #define p_int_status_64 u_int_status._p_int_status
 328     #define b_int_status u_int_status._b._b_int_status
 329
 330     union {
 331         picreg_t            _p_int_enable;          /* 0x000108 */
 332         struct {
 333             bridgereg_t     _b_int_enable;          /* 0x00010C */
 334             bridgereg_t     _b_pad_000108;
 335         } _b;
 336     } u_int_enable;
 337     #define p_int_enable_64 u_int_enable._p_int_enable
 338     #define b_int_enable u_int_enable._b._b_int_enable
 339
 340     union {
 341         picreg_t            _p_int_rst_stat;        /* 0x000110 */
 342         struct {
 343             bridgereg_t     _b_int_rst_stat;        /* 0x000114 */
 344             bridgereg_t     _b_pad_000110;
 345         } _b;
 346     } u_int_rst_stat;
 347     #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat
 348     #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat
 349
 350     bridgereg_t             b_int_mode;             /* 0x00011C */
 351     bridgereg_t             _pad_000118;
 352
 353     bridgereg_t             b_int_device;           /* 0x000124 */
 354     bridgereg_t             _pad_000120;
 355
 356     bridgereg_t             b_int_host_err;         /* 0x00012C */
 357     bridgereg_t             _pad_000128;
 358
 359     union {
 360         picreg_t            _p_int_addr[8];         /* 0x0001{30,,,68} */
 361         struct {
 362             bridgereg_t     addr;                   /* 0x0001{34,,,6C} */
 363             bridgereg_t     _b_pad;
 364         } _b[8];
 365     } u_int_addr;
 366     #define p_int_addr_64 u_int_addr._p_int_addr
 367     #define b_int_addr u_int_addr._b
 368
 369     union {
 370         picreg_t            _p_err_int_view;        /* 0x000170 */
 371         struct {
 372             bridgereg_t     _b_err_int_view;        /* 0x000174 */
 373             bridgereg_t     _b_pad_000170;
 374         } _b;
 375     } u_err_int_view;
 376     #define p_err_int_view_64 u_err_int_view._p_err_int_view
 377     #define b_err_int_view u_err_int_view._b._b_err_int_view
 378
 379     union {
 380         picreg_t            _p_mult_int;            /* 0x000178 */
 381         struct {
 382             bridgereg_t     _b_mult_int;            /* 0x00017C */
 383             bridgereg_t     _b_pad_000178;
 384         } _b;
 385     } u_mult_int;
 386     #define p_mult_int_64 u_mult_int._p_mult_int
 387     #define b_mult_int u_mult_int._b._b_mult_int
 388
 389     struct {
 390         bridgereg_t         intr;                   /* 0x0001{84,,,BC} */
 391         bridgereg_t         __pad;
 392     } b_force_always[8];
 393
 394     struct {
 395         bridgereg_t         intr;                   /* 0x0001{C4,,,FC} */
 396         bridgereg_t         __pad;
 397     } b_force_pin[8];
 398
 399     /* 0x000200-0x0003FF -- Device */
 400     struct {
 401         bridgereg_t         reg;                    /* 0x0002{04,,,3C} */
 402         bridgereg_t         __pad;
 403     } b_device[8];
 404
 405     struct {
 406         bridgereg_t         reg;                    /* 0x0002{44,,,7C} */
 407         bridgereg_t         __pad;
 408     } b_wr_req_buf[8];
 409
 410     struct {
 411         bridgereg_t         reg;                    /* 0x0002{84,,,8C} */
 412         bridgereg_t         __pad;
 413     } b_rrb_map[2];
 414     #define b_even_resp b_rrb_map[0].reg            /* 0x000284 */
 415     #define b_odd_resp  b_rrb_map[1].reg            /* 0x00028C */
 416
 417     bridgereg_t             b_resp_status;          /* 0x000294 */
 418     bridgereg_t             _pad_000290;
 419
 420     bridgereg_t             b_resp_clear;           /* 0x00029C */
 421     bridgereg_t             _pad_000298;
 422
 423     bridgereg_t             _pad_0002A0[24];
 424
 425     /* Xbridge/PIC only */
 426     union {
 427         struct {
 428             picreg_t        lower;                  /* 0x0003{08,,,F8} */
 429             picreg_t        upper;                  /* 0x0003{00,,,F0} */
 430         } _p[16];
 431         struct {
 432             bridgereg_t     upper;                  /* 0x0003{04,,,F4} */
 433             bridgereg_t     _b_pad1;
 434             bridgereg_t     lower;                  /* 0x0003{0C,,,FC} */
 435             bridgereg_t     _b_pad2;
 436         } _b[16];
 437     } u_buf_addr_match;
 438     #define p_buf_addr_match_64 u_buf_addr_match._p
 439     #define b_buf_addr_match u_buf_addr_match._b
 440
 441     /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
 442     struct {
 443         bridgereg_t         flush_w_touch;          /* 0x000{404,,,5C4} */
 444         bridgereg_t         __pad1;
 445         bridgereg_t         flush_wo_touch;         /* 0x000{40C,,,5CC} */
 446         bridgereg_t         __pad2;
 447         bridgereg_t         inflight;               /* 0x000{414,,,5D4} */
 448         bridgereg_t         __pad3;
 449         bridgereg_t         prefetch;               /* 0x000{41C,,,5DC} */
 450         bridgereg_t         __pad4;
 451         bridgereg_t         total_pci_retry;        /* 0x000{424,,,5E4} */
 452         bridgereg_t         __pad5;
 453         bridgereg_t         max_pci_retry;          /* 0x000{42C,,,5EC} */
 454         bridgereg_t         __pad6;
 455         bridgereg_t         max_latency;            /* 0x000{434,,,5F4} */
 456         bridgereg_t         __pad7;
 457         bridgereg_t         clear_all;              /* 0x000{43C,,,5FC} */
 458         bridgereg_t         __pad8;
 459     } b_buf_count[8];
 460
 461     /*
 462      * "PCI/X registers that are specific to PIC".   See pic.h.
 463      */
 464
 465     /* 0x000600-0x0009FF -- PCI/X registers */
 466     picreg_t                p_pcix_bus_err_addr_64;     /* 0x000600 */
 467     picreg_t                p_pcix_bus_err_attr_64;     /* 0x000608 */
 468     picreg_t                p_pcix_bus_err_data_64;     /* 0x000610 */
 469     picreg_t                p_pcix_pio_split_addr_64;   /* 0x000618 */
 470     picreg_t                p_pcix_pio_split_attr_64;   /* 0x000620 */
 471     picreg_t                p_pcix_dma_req_err_attr_64; /* 0x000628 */
 472     picreg_t                p_pcix_dma_req_err_addr_64; /* 0x000630 */
 473     picreg_t                p_pcix_timeout_64;          /* 0x000638 */
 474
 475     picreg_t                _pad_000600[120];
 476
 477     /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
 478     struct {
 479         picreg_t            p_buf_attr;             /* 0X000{A08,,,AF8} */
 480         picreg_t            p_buf_addr;             /* 0x000{A00,,,AF0} */
 481     } p_pcix_read_buf_64[16];
 482
 483     struct {
 484         picreg_t            p_buf_attr;             /* 0x000{B08,,,BE8} */
 485         picreg_t            p_buf_addr;             /* 0x000{B00,,,BE0} */
 486         picreg_t            __pad1;                 /* 0x000{B18,,,BF8} */
 487         picreg_t            p_buf_valid;            /* 0x000{B10,,,BF0} */
 488     } p_pcix_write_buf_64[8];
 489
 490     /*
 491      * end "PCI/X registers that are specific to PIC"
 492      */
 493
 494     char                    _pad_000c00[0x010000 - 0x000c00];
 495
 496     /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */
 497     /*
 498      * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128.
 499      * Make enough room for the Xbridge/PIC ATE's and depend on runtime
 500      * checks to limit access to bridge ATE's.
 501      *
 502      * In [X]bridge the internal ATE Ram is writen as double words only,
 503      * but due to internal design issues it is read back as single words.
 504      * i.e:
 505      *   b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd
 506      */
 507     union {
 508         bridge_ate_t        wr; /* write-only */    /* 0x01{0000,,,1FF8} */
 509         struct {
 510             bridgereg_t     rd; /* read-only */     /* 0x01{0004,,,1FFC} */
 511             bridgereg_t     _p_pad;
 512         } hi;
 513     } b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
 514     #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
 515
 516     /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */
 517     struct {
 518         bridgereg_t         rd; /* read-only */     /* 0x01{2004,,,3FFC} */
 519         bridgereg_t         _p_pad;
 520     } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
 521
 522     char                    _pad_014000[0x18000 - 0x014000];
 523
 524     /* 0x18000-0x197F8 -- PIC Write Request Ram */
 525                                 /* 0x18000 - 0x187F8 */
 526     picreg_t                p_wr_req_lower[PIC_WR_REQ_BUFSIZE];
 527                                 /* 0x18800 - 0x18FF8 */
 528     picreg_t                p_wr_req_upper[PIC_WR_REQ_BUFSIZE];
 529                                 /* 0x19000 - 0x197F8 */
 530     picreg_t                p_wr_req_parity[PIC_WR_REQ_BUFSIZE];
 531
 532     char                    _pad_019800[0x20000 - 0x019800];
 533
 534     /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
 535     union {                             /* make all access sizes available. */
 536         unsigned char               c[0x1000 / 1];          /* 0x02{0000,,,7FFF} */
 537         uint16_t            s[0x1000 / 2];          /* 0x02{0000,,,7FFF} */
 538         uint32_t            l[0x1000 / 4];          /* 0x02{0000,,,7FFF} */
 539         uint64_t            d[0x1000 / 8];          /* 0x02{0000,,,7FFF} */
 540         union {
 541             unsigned char           c[0x100 / 1];
 542             uint16_t        s[0x100 / 2];
 543             uint32_t        l[0x100 / 4];
 544             uint64_t        d[0x100 / 8];
 545         } f[8];
 546     } b_type0_cfg_dev[8];                           /* 0x02{0000,,,7FFF} */
 547
 548     /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
 549     union {                             /* make all access sizes available. */
 550         unsigned char               c[0x1000 / 1];
 551         uint16_t            s[0x1000 / 2];
 552         uint32_t            l[0x1000 / 4];
 553         uint64_t            d[0x1000 / 8];
 554         union {
 555             unsigned char         c[0x100 / 1];
 556             uint16_t        s[0x100 / 2];
 557             uint32_t        l[0x100 / 4];
 558             uint64_t        d[0x100 / 8];
 559         } f[8];
 560     } b_type1_cfg;                                  /* 0x028000-0x029000 */
 561
 562     char                    _pad_029000[0x007000];  /* 0x029000-0x030000 */
 563
 564     /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
 565     union {
 566         unsigned char               c[8 / 1];
 567         uint16_t            s[8 / 2];
 568         uint32_t            l[8 / 4];
 569         uint64_t            d[8 / 8];
 570     } b_pci_iack;                                   /* 0x030000-0x030007 */
 571
 572     unsigned char                   _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */
 573
 574     /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */
 575     bridge_ate_t            b_ext_ate_ram[0x10000];
 576
 577     /* 0x100000-0x1FFFFF -- Reserved */
 578     char                    _pad_100000[0x200000-0x100000];
 579
 580     /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */
 581     union {                             /* make all access sizes available. */
 582         unsigned char               c[0x100000 / 1];
 583         uint16_t            s[0x100000 / 2];
 584         uint32_t            l[0x100000 / 4];
 585         uint64_t            d[0x100000 / 8];
 586     } b_devio_raw[10];
 587
 588     /* b_devio macro is a bit strange; it reflects the
 589      * fact that the Bridge ASIC provides 2M for the
 590      * first two DevIO windows and 1M for the other six.
 591      */
 592     #define b_devio(n)  b_devio_raw[((n)<2)?(n*2):(n+2)]
 593
 594     /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */
 595     union {                             /* make all access sizes available. */
 596         unsigned char               c[0x400000 / 1];    /* read-only */
 597         uint16_t            s[0x400000 / 2];    /* read-write */
 598         uint32_t            l[0x400000 / 4];    /* read-only */
 599         uint64_t            d[0x400000 / 8];    /* read-only */
 600     } b_external_flash;
 601 } bridge_t;
 602
 603 #define berr_field      berr_un.berr_st
 604 #endif                          /* __ASSEMBLY__ */
 605
 606 /*
 607  * The values of these macros can and should be crosschecked
 608  * regularly against the offsets of the like-named fields
 609  * within the "bridge_t" structure above.
 610  */
 611
 612 /* Byte offset macros for Bridge internal registers */
 613
 614 #define BRIDGE_WID_ID           WIDGET_ID
 615 #define BRIDGE_WID_STAT         WIDGET_STATUS
 616 #define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
 617 #define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
 618 #define BRIDGE_WID_CONTROL      WIDGET_CONTROL
 619 #define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
 620 #define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
 621 #define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
 622 #define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
 623 #define BRIDGE_WID_LLP          WIDGET_LLP_CFG
 624 #define BRIDGE_WID_TFLUSH       WIDGET_TFLUSH
 625
 626 #define BRIDGE_WID_AUX_ERR      0x00005C        /* Aux Error Command Word */
 627 #define BRIDGE_WID_RESP_UPPER   0x000064        /* Response Buf Upper Addr */
 628 #define BRIDGE_WID_RESP_LOWER   0x00006C        /* Response Buf Lower Addr */
 629 #define BRIDGE_WID_TST_PIN_CTRL 0x000074        /* Test pin control */
 630
 631 #define BRIDGE_DIR_MAP          0x000084        /* Direct Map reg */
 632
 633 /* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */
 634 #define BRIDGE_RAM_PERR         0x000094        /* SSRAM Parity Error */
 635 #define BRIDGE_MAP_FAULT        0x000094        /* Map Fault */
 636
 637 #define BRIDGE_ARB              0x0000A4        /* Arbitration Priority reg */
 638
 639 #define BRIDGE_NIC              0x0000B4        /* Number In A Can */
 640
 641 #define BRIDGE_BUS_TIMEOUT      0x0000C4        /* Bus Timeout Register */
 642 #define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
 643 #define BRIDGE_PCI_CFG          0x0000CC        /* PCI Type 1 Config reg */
 644 #define BRIDGE_PCI_ERR_UPPER    0x0000D4        /* PCI error Upper Addr */
 645 #define BRIDGE_PCI_ERR_LOWER    0x0000DC        /* PCI error Lower Addr */
 646
 647 #define BRIDGE_INT_STATUS       0x000104        /* Interrupt Status */
 648 #define BRIDGE_INT_ENABLE       0x00010C        /* Interrupt Enables */
 649 #define BRIDGE_INT_RST_STAT     0x000114        /* Reset Intr Status */
 650 #define BRIDGE_INT_MODE         0x00011C        /* Interrupt Mode */
 651 #define BRIDGE_INT_DEVICE       0x000124        /* Interrupt Device */
 652 #define BRIDGE_INT_HOST_ERR     0x00012C        /* Host Error Field */
 653
 654 #define BRIDGE_INT_ADDR0        0x000134        /* Host Address Reg */
 655 #define BRIDGE_INT_ADDR_OFF     0x000008        /* Host Addr offset (1..7) */
 656 #define BRIDGE_INT_ADDR(x)      (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
 657
 658 #define BRIDGE_INT_VIEW         0x000174        /* Interrupt view */
 659 #define BRIDGE_MULTIPLE_INT     0x00017c        /* Multiple interrupt occurred */
 660
 661 #define BRIDGE_FORCE_ALWAYS0    0x000184        /* Force an interrupt (always)*/
 662 #define BRIDGE_FORCE_ALWAYS_OFF 0x000008        /* Force Always offset */
 663 #define BRIDGE_FORCE_ALWAYS(x)  (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF)
 664
 665 #define BRIDGE_FORCE_PIN0       0x0001c4        /* Force an interrupt */
 666 #define BRIDGE_FORCE_PIN_OFF    0x000008        /* Force Pin offset */
 667 #define BRIDGE_FORCE_PIN(x)  (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF)
 668
 669 #define BRIDGE_DEVICE0          0x000204        /* Device 0 */
 670 #define BRIDGE_DEVICE_OFF       0x000008        /* Device offset (1..7) */
 671 #define BRIDGE_DEVICE(x)        (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
 672
 673 #define BRIDGE_WR_REQ_BUF0      0x000244        /* Write Request Buffer 0 */
 674 #define BRIDGE_WR_REQ_BUF_OFF   0x000008        /* Buffer Offset (1..7) */
 675 #define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
 676
 677 #define BRIDGE_EVEN_RESP        0x000284        /* Even Device Response Buf */
 678 #define BRIDGE_ODD_RESP         0x00028C        /* Odd Device Response Buf */
 679
 680 #define BRIDGE_RESP_STATUS      0x000294        /* Read Response Status reg */
 681 #define BRIDGE_RESP_CLEAR       0x00029C        /* Read Response Clear reg */
 682
 683 #define BRIDGE_BUF_ADDR_UPPER0  0x000304
 684 #define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010      /* PCI Buffer Upper Offset */
 685 #define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF)
 686
 687 #define BRIDGE_BUF_ADDR_LOWER0  0x00030c
 688 #define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010      /* PCI Buffer Upper Offset */
 689 #define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF)
 690
 691 /*
 692  * Performance Monitor Registers.
 693  *
 694  * The Performance registers are those registers which are associated with
 695  * monitoring the performance of PCI generated reads to the host environ
 696  * ment. Because of the size of the register file only the even registers
 697  * were instrumented.
 698  */
 699
 700 #define BRIDGE_BUF_OFF 0x40
 701 #define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF))
 702
 703 /*
 704  * Buffer (x) Flush Count with Data Touch Register.
 705  *
 706  * This counter is incremented each time the corresponding response buffer
 707  * is flushed after at least a single data element in the buffer is used.
 708  * A word write to this address clears the count.
 709  */
 710
 711 #define BRIDGE_BUF_0_FLUSH_TOUCH  0x000404
 712 #define BRIDGE_BUF_2_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1)
 713 #define BRIDGE_BUF_4_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2)
 714 #define BRIDGE_BUF_6_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3)
 715 #define BRIDGE_BUF_8_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4)
 716 #define BRIDGE_BUF_10_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5)
 717 #define BRIDGE_BUF_12_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6)
 718 #define BRIDGE_BUF_14_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7)
 719
 720 /*
 721  * Buffer (x) Flush Count w/o Data Touch Register
 722  *
 723  * This counter is incremented each time the corresponding response buffer
 724  * is flushed without any data element in the buffer being used. A word
 725  * write to this address clears the count.
 726  */
 727
 728
 729 #define BRIDGE_BUF_0_FLUSH_NOTOUCH  0x00040c
 730 #define BRIDGE_BUF_2_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1)
 731 #define BRIDGE_BUF_4_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2)
 732 #define BRIDGE_BUF_6_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3)
 733 #define BRIDGE_BUF_8_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4)
 734 #define BRIDGE_BUF_10_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5)
 735 #define BRIDGE_BUF_12_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6)
 736 #define BRIDGE_BUF_14_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7)
 737
 738 /*
 739  * Buffer (x) Request in Flight Count Register
 740  *
 741  * This counter is incremented on each bus clock while the request is in
 742  * flight. A word write to this address clears the count.
 743  */
 744
 745 #define BRIDGE_BUF_0_INFLIGHT    0x000414
 746 #define BRIDGE_BUF_2_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1)
 747 #define BRIDGE_BUF_4_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2)
 748 #define BRIDGE_BUF_6_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3)
 749 #define BRIDGE_BUF_8_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4)
 750 #define BRIDGE_BUF_10_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5)
 751 #define BRIDGE_BUF_12_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6)
 752 #define BRIDGE_BUF_14_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7)
 753
 754 /*
 755  * Buffer (x) Prefetch Request Count Register
 756  *
 757  * This counter is incremented each time the request using this buffer was
 758  * generated from the prefetcher. A word write to this address clears the
 759  * count.
 760  */
 761
 762 #define BRIDGE_BUF_0_PREFETCH    0x00041C
 763 #define BRIDGE_BUF_2_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1)
 764 #define BRIDGE_BUF_4_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2)
 765 #define BRIDGE_BUF_6_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3)
 766 #define BRIDGE_BUF_8_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4)
 767 #define BRIDGE_BUF_10_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5)
 768 #define BRIDGE_BUF_12_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6)
 769 #define BRIDGE_BUF_14_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7)
 770
 771 /*
 772  * Buffer (x) Total PCI Retry Count Register
 773  *
 774  * This counter is incremented each time a PCI bus retry occurs and the ad
 775  * dress matches the tag for the selected buffer. The buffer must also has
 776  * this request in-flight. A word write to this address clears the count.
 777  */
 778
 779 #define BRIDGE_BUF_0_PCI_RETRY   0x000424
 780 #define BRIDGE_BUF_2_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1)
 781 #define BRIDGE_BUF_4_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2)
 782 #define BRIDGE_BUF_6_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3)
 783 #define BRIDGE_BUF_8_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4)
 784 #define BRIDGE_BUF_10_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5)
 785 #define BRIDGE_BUF_12_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6)
 786 #define BRIDGE_BUF_14_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7)
 787
 788 /*
 789  * Buffer (x) Max PCI Retry Count Register
 790  *
 791  * This counter is contains the maximum retry count for a single request
 792  * which was in-flight for this buffer. A word write to this address
 793  * clears the count.
 794  */
 795
 796 #define BRIDGE_BUF_0_MAX_PCI_RETRY       0x00042C
 797 #define BRIDGE_BUF_2_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1)
 798 #define BRIDGE_BUF_4_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2)
 799 #define BRIDGE_BUF_6_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3)
 800 #define BRIDGE_BUF_8_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4)
 801 #define BRIDGE_BUF_10_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5)
 802 #define BRIDGE_BUF_12_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6)
 803 #define BRIDGE_BUF_14_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7)
 804
 805 /*
 806  * Buffer (x) Max Latency Count Register
 807  *
 808  * This counter is contains the maximum count (in bus clocks) for a single
 809  * request which was in-flight for this buffer. A word write to this
 810  * address clears the count.
 811  */
 812
 813 #define BRIDGE_BUF_0_MAX_LATENCY         0x000434
 814 #define BRIDGE_BUF_2_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1)
 815 #define BRIDGE_BUF_4_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2)
 816 #define BRIDGE_BUF_6_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3)
 817 #define BRIDGE_BUF_8_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4)
 818 #define BRIDGE_BUF_10_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5)
 819 #define BRIDGE_BUF_12_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6)
 820 #define BRIDGE_BUF_14_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7)
 821
 822 /*
 823  * Buffer (x) Clear All Register
 824  *
 825  * Any access to this register clears all the count values for the (x)
 826  * registers.
 827  */
 828
 829 #define BRIDGE_BUF_0_CLEAR_ALL   0x00043C
 830 #define BRIDGE_BUF_2_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1)
 831 #define BRIDGE_BUF_4_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2)
 832 #define BRIDGE_BUF_6_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3)
 833 #define BRIDGE_BUF_8_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4)
 834 #define BRIDGE_BUF_10_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5)
 835 #define BRIDGE_BUF_12_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6)
 836 #define BRIDGE_BUF_14_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7)
 837
 838 /* end of Performance Monitor Registers */
 839
 840 /* Byte offset macros for Bridge I/O space.
 841  *
 842  * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx
 843  * macros (below) as they will handle [X]Bridge and PIC. For example,
 844  * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0
 845  */
 846
 847 #define BRIDGE_ATE_RAM          0x00010000      /* Internal Addr Xlat Ram */
 848
 849 #define BRIDGE_TYPE0_CFG_DEV0   0x00020000      /* Type 0 Cfg, Device 0 */
 850 #define BRIDGE_TYPE0_CFG_SLOT_OFF       0x00001000      /* Type 0 Cfg Slot Offset (1..7) */
 851 #define BRIDGE_TYPE0_CFG_FUNC_OFF       0x00000100      /* Type 0 Cfg Func Offset (1..7) */
 852 #define BRIDGE_TYPE0_CFG_DEV(s)         (BRIDGE_TYPE0_CFG_DEV0+\
 853                                          (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
 854 #define BRIDGE_TYPE0_CFG_DEVF(s,f)      (BRIDGE_TYPE0_CFG_DEV0+\
 855                                          (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
 856                                          (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
 857
 858 #define BRIDGE_TYPE1_CFG        0x00028000      /* Type 1 Cfg space */
 859
 860 #define BRIDGE_PCI_IACK         0x00030000      /* PCI Interrupt Ack */
 861 #define BRIDGE_EXT_SSRAM        0x00080000      /* Extern SSRAM (ATE) */
 862
 863 /* Byte offset macros for Bridge device IO spaces */
 864
 865 #define BRIDGE_DEV_CNT          8       /* Up to 8 devices per bridge */
 866 #define BRIDGE_DEVIO0           0x00200000      /* Device IO 0 Addr */
 867 #define BRIDGE_DEVIO1           0x00400000      /* Device IO 1 Addr */
 868 #define BRIDGE_DEVIO2           0x00600000      /* Device IO 2 Addr */
 869 #define BRIDGE_DEVIO_OFF        0x00100000      /* Device IO Offset (3..7) */
 870
 871 #define BRIDGE_DEVIO_2MB        0x00200000      /* Device IO Offset (0..1) */
 872 #define BRIDGE_DEVIO_1MB        0x00100000      /* Device IO Offset (2..7) */
 873
 874 #ifndef __ASSEMBLY__
 875
 876 #define BRIDGE_DEVIO(x)         ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
 877
 878 /*
 879  * The device space macros for PIC are more complicated because the PIC has
 880  * two PCI/X bridges under the same widget.  For PIC bus 0, the addresses are
 881  * basically the same as for the [X]Bridge.  For PIC bus 1, the addresses are
 882  * offset by 0x800000.   Here are two sets of macros.  They are
 883  * "PCIBRIDGE_xxx" that return the address based on the supplied bus number
 884  * and also equivalent "PCIBR_xxx" macros that may be used with a
 885  * pcibr_soft_s structure.   Both should work with all bridges.
 886  */
 887 #define PIC_BUS1_OFFSET 0x800000
 888
 889 #define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \
 890     ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \
 891                     BRIDGE_TYPE0_CFG_DEV0)
 892 #define PCIBRIDGE_TYPE1_CFG(busnum) \
 893     ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG)
 894 #define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \
 895         (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\
 896         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
 897 #define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \
 898         (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\
 899         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
 900         (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
 901 #define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \
 902         (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0)
 903 #define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \
 904         (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1)
 905 #define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \
 906         (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2)
 907 #define PCIBRIDGE_DEVIO(busnum, x) \
 908     ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \
 909         PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB)
 910
 911 #define PCIBR_BRIDGE_DEVIO0(ps)     PCIBRIDGE_DEVIO0((ps)->bs_busnum)
 912 #define PCIBR_BRIDGE_DEVIO1(ps)     PCIBRIDGE_DEVIO1((ps)->bs_busnum)
 913 #define PCIBR_BRIDGE_DEVIO2(ps)     PCIBRIDGE_DEVIO2((ps)->bs_busnum)
 914 #define PCIBR_BRIDGE_DEVIO(ps, s)   PCIBRIDGE_DEVIO((ps)->bs_busnum, s)
 915
 916 #define PCIBR_TYPE1_CFG(ps)         PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum)
 917 #define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0)
 918 #define PCIBR_TYPE0_CFG_DEV(ps, s) PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1)
 919 #define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f)
 920
 921 /* NOTE: 's' is the internal device number, not the external slot number */
 922 #define PCIBR_BUS_TYPE0_CFG_DEV(ps, s) \
 923                 PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1)
 924
 925 #endif                          /* LANGUAGE_C */
 926
 927 #define BRIDGE_EXTERNAL_FLASH   0x00C00000      /* External Flash PROMS */
 928
 929 /* ========================================================================
 930  *    Bridge register bit field definitions
 931  */
 932
 933 /* Widget part number of bridge */
 934 #define BRIDGE_WIDGET_PART_NUM          0xc002
 935 #define XBRIDGE_WIDGET_PART_NUM         0xd002
 936
 937 /* Manufacturer of bridge */
 938 #define BRIDGE_WIDGET_MFGR_NUM          0x036
 939 #define XBRIDGE_WIDGET_MFGR_NUM         0x024
 940
 941 /* Revision numbers for known [X]Bridge revisions */
 942 #define BRIDGE_REV_A                    0x1
 943 #define BRIDGE_REV_B                    0x2
 944 #define BRIDGE_REV_C                    0x3
 945 #define BRIDGE_REV_D                    0x4
 946 #define XBRIDGE_REV_A                   0x1
 947 #define XBRIDGE_REV_B                   0x2
 948
 949 /* macros to determine bridge type. 'wid' == widget identification */
 950 #define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \
 951                         XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
 952 #define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \
 953                         XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
 954 #define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid))
 955
 956 /* Part + Rev numbers allows distinction and acscending sequence */
 957 #define BRIDGE_PART_REV_A       (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A)
 958 #define BRIDGE_PART_REV_B       (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B)
 959 #define BRIDGE_PART_REV_C       (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C)
 960 #define BRIDGE_PART_REV_D       (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D)
 961 #define XBRIDGE_PART_REV_A      (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A)
 962 #define XBRIDGE_PART_REV_B      (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B)
 963
 964 /* Bridge widget status register bits definition */
 965 #define PIC_STAT_PCIX_SPEED             (0x3ull << 34)
 966 #define PIC_STAT_PCIX_ACTIVE            (0x1ull << 33)
 967 #define BRIDGE_STAT_LLP_REC_CNT         (0xFFu << 24)
 968 #define BRIDGE_STAT_LLP_TX_CNT          (0xFF << 16)
 969 #define BRIDGE_STAT_FLASH_SELECT        (0x1 << 6)
 970 #define BRIDGE_STAT_PCI_GIO_N           (0x1 << 5)
 971 #define BRIDGE_STAT_PENDING             (0x1F << 0)
 972
 973 /* Bridge widget control register bits definition */
 974 #define PIC_CTRL_NO_SNOOP               (0x1ull << 62)
 975 #define PIC_CTRL_RELAX_ORDER            (0x1ull << 61)
 976 #define PIC_CTRL_BUS_NUM(x)             ((unsigned long long)(x) << 48)
 977 #define PIC_CTRL_BUS_NUM_MASK           (PIC_CTRL_BUS_NUM(0xff))
 978 #define PIC_CTRL_DEV_NUM(x)             ((unsigned long long)(x) << 43)
 979 #define PIC_CTRL_DEV_NUM_MASK           (PIC_CTRL_DEV_NUM(0x1f))
 980 #define PIC_CTRL_FUN_NUM(x)             ((unsigned long long)(x) << 40)
 981 #define PIC_CTRL_FUN_NUM_MASK           (PIC_CTRL_FUN_NUM(0x7))
 982 #define PIC_CTRL_PAR_EN_REQ             (0x1ull << 29)
 983 #define PIC_CTRL_PAR_EN_RESP            (0x1ull << 30)
 984 #define PIC_CTRL_PAR_EN_ATE             (0x1ull << 31)
 985 #define BRIDGE_CTRL_FLASH_WR_EN         (0x1ul << 31)   /* bridge only */
 986 #define BRIDGE_CTRL_EN_CLK50            (0x1 << 30)
 987 #define BRIDGE_CTRL_EN_CLK40            (0x1 << 29)
 988 #define BRIDGE_CTRL_EN_CLK33            (0x1 << 28)
 989 #define BRIDGE_CTRL_RST(n)              ((n) << 24)
 990 #define BRIDGE_CTRL_RST_MASK            (BRIDGE_CTRL_RST(0xF))
 991 #define BRIDGE_CTRL_RST_PIN(x)          (BRIDGE_CTRL_RST(0x1 << (x)))
 992 #define BRIDGE_CTRL_IO_SWAP             (0x1 << 23)
 993 #define BRIDGE_CTRL_MEM_SWAP            (0x1 << 22)
 994 #define BRIDGE_CTRL_PAGE_SIZE           (0x1 << 21)
 995 #define BRIDGE_CTRL_SS_PAR_BAD          (0x1 << 20)
 996 #define BRIDGE_CTRL_SS_PAR_EN           (0x1 << 19)
 997 #define BRIDGE_CTRL_SSRAM_SIZE(n)       ((n) << 17)
 998 #define BRIDGE_CTRL_SSRAM_SIZE_MASK     (BRIDGE_CTRL_SSRAM_SIZE(0x3))
 999 #define BRIDGE_CTRL_SSRAM_512K          (BRIDGE_CTRL_SSRAM_SIZE(0x3))
1000 #define BRIDGE_CTRL_SSRAM_128K          (BRIDGE_CTRL_SSRAM_SIZE(0x2))
1001 #define BRIDGE_CTRL_SSRAM_64K           (BRIDGE_CTRL_SSRAM_SIZE(0x1))
1002 #define BRIDGE_CTRL_SSRAM_1K            (BRIDGE_CTRL_SSRAM_SIZE(0x0))
1003 #define BRIDGE_CTRL_F_BAD_PKT           (0x1 << 16)
1004 #define BRIDGE_CTRL_LLP_XBAR_CRD(n)     ((n) << 12)
1005 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
1006 #define BRIDGE_CTRL_CLR_RLLP_CNT        (0x1 << 11)
1007 #define BRIDGE_CTRL_CLR_TLLP_CNT        (0x1 << 10)
1008 #define BRIDGE_CTRL_SYS_END             (0x1 << 9)
1009 #define BRIDGE_CTRL_PCI_SPEED           (0x3 << 4)
1010
1011 #define BRIDGE_CTRL_BUS_SPEED(n)        ((n) << 4)
1012 #define BRIDGE_CTRL_BUS_SPEED_MASK      (BRIDGE_CTRL_BUS_SPEED(0x3))
1013 #define BRIDGE_CTRL_BUS_SPEED_33        0x00
1014 #define BRIDGE_CTRL_BUS_SPEED_66        0x10
1015 #define BRIDGE_CTRL_MAX_TRANS(n)        ((n) << 4)
1016 #define BRIDGE_CTRL_MAX_TRANS_MASK      (BRIDGE_CTRL_MAX_TRANS(0x1f))
1017 #define BRIDGE_CTRL_WIDGET_ID(n)        ((n) << 0)
1018 #define BRIDGE_CTRL_WIDGET_ID_MASK      (BRIDGE_CTRL_WIDGET_ID(0xf))
1019
1020 /* Bridge Response buffer Error Upper Register bit fields definition */
1021 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
1022 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
1023 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
1024 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
1025 #define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
1026
1027 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
1028                         (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
1029                                 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
1030
1031 #define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
1032                         (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
1033                                  BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
1034
1035 /* Bridge direct mapping register bits definition */
1036 #define BRIDGE_DIRMAP_W_ID_SHFT         20
1037 #define BRIDGE_DIRMAP_W_ID              (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
1038 #define BRIDGE_DIRMAP_RMF_64            (0x1 << 18)
1039 #define BRIDGE_DIRMAP_ADD512            (0x1 << 17)
1040 #define BRIDGE_DIRMAP_OFF               (0x1ffff << 0)
1041 #define BRIDGE_DIRMAP_OFF_ADDRSHFT      (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
1042
1043 /* Bridge Arbitration register bits definition */
1044 #define BRIDGE_ARB_REQ_WAIT_TICK(x)     ((x) << 16)
1045 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
1046 #define BRIDGE_ARB_REQ_WAIT_EN(x)       ((x) << 8)
1047 #define BRIDGE_ARB_REQ_WAIT_EN_MASK     BRIDGE_ARB_REQ_WAIT_EN(0xff)
1048 #define BRIDGE_ARB_FREEZE_GNT           (1 << 6)
1049 #define BRIDGE_ARB_HPRI_RING_B2         (1 << 5)
1050 #define BRIDGE_ARB_HPRI_RING_B1         (1 << 4)
1051 #define BRIDGE_ARB_HPRI_RING_B0         (1 << 3)
1052 #define BRIDGE_ARB_LPRI_RING_B2         (1 << 2)
1053 #define BRIDGE_ARB_LPRI_RING_B1         (1 << 1)
1054 #define BRIDGE_ARB_LPRI_RING_B0         (1 << 0)
1055
1056 /* Bridge Bus time-out register bits definition */
1057 #define BRIDGE_BUS_PCI_RETRY_HLD(x)     ((x) << 16)
1058 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
1059 #define BRIDGE_BUS_GIO_TIMEOUT          (1 << 12)
1060 #define BRIDGE_BUS_PCI_RETRY_CNT(x)     ((x) << 0)
1061 #define BRIDGE_BUS_PCI_RETRY_MASK       BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
1062
1063 /* Bridge interrupt status register bits definition */
1064 #define PIC_ISR_PCIX_SPLIT_MSG_PE       (0x1ull << 45)
1065 #define PIC_ISR_PCIX_SPLIT_EMSG         (0x1ull << 44)
1066 #define PIC_ISR_PCIX_SPLIT_TO           (0x1ull << 43)
1067 #define PIC_ISR_PCIX_UNEX_COMP          (0x1ull << 42)
1068 #define PIC_ISR_INT_RAM_PERR            (0x1ull << 41)
1069 #define PIC_ISR_PCIX_ARB_ERR            (0x1ull << 40)
1070 #define PIC_ISR_PCIX_REQ_TOUT           (0x1ull << 39)
1071 #define PIC_ISR_PCIX_TABORT             (0x1ull << 38)
1072 #define PIC_ISR_PCIX_PERR               (0x1ull << 37)
1073 #define PIC_ISR_PCIX_SERR               (0x1ull << 36)
1074 #define PIC_ISR_PCIX_MRETRY             (0x1ull << 35)
1075 #define PIC_ISR_PCIX_MTOUT              (0x1ull << 34)
1076 #define PIC_ISR_PCIX_DA_PARITY          (0x1ull << 33)
1077 #define PIC_ISR_PCIX_AD_PARITY          (0x1ull << 32)
1078 #define BRIDGE_ISR_MULTI_ERR            (0x1u << 31)    /* bridge only */
1079 #define BRIDGE_ISR_PMU_ESIZE_FAULT      (0x1 << 30)     /* bridge only */
1080 #define BRIDGE_ISR_PAGE_FAULT           (0x1 << 30)     /* xbridge only */
1081 #define BRIDGE_ISR_UNEXP_RESP           (0x1 << 29)
1082 #define BRIDGE_ISR_BAD_XRESP_PKT        (0x1 << 28)
1083 #define BRIDGE_ISR_BAD_XREQ_PKT         (0x1 << 27)
1084 #define BRIDGE_ISR_RESP_XTLK_ERR        (0x1 << 26)
1085 #define BRIDGE_ISR_REQ_XTLK_ERR         (0x1 << 25)
1086 #define BRIDGE_ISR_INVLD_ADDR           (0x1 << 24)
1087 #define BRIDGE_ISR_UNSUPPORTED_XOP      (0x1 << 23)
1088 #define BRIDGE_ISR_XREQ_FIFO_OFLOW      (0x1 << 22)
1089 #define BRIDGE_ISR_LLP_REC_SNERR        (0x1 << 21)
1090 #define BRIDGE_ISR_LLP_REC_CBERR        (0x1 << 20)
1091 #define BRIDGE_ISR_LLP_RCTY             (0x1 << 19)
1092 #define BRIDGE_ISR_LLP_TX_RETRY         (0x1 << 18)
1093 #define BRIDGE_ISR_LLP_TCTY             (0x1 << 17)
1094 #define BRIDGE_ISR_SSRAM_PERR           (0x1 << 16)
1095 #define BRIDGE_ISR_PCI_ABORT            (0x1 << 15)
1096 #define BRIDGE_ISR_PCI_PARITY           (0x1 << 14)
1097 #define BRIDGE_ISR_PCI_SERR             (0x1 << 13)
1098 #define BRIDGE_ISR_PCI_PERR             (0x1 << 12)
1099 #define BRIDGE_ISR_PCI_MST_TIMEOUT      (0x1 << 11)
1100 #define BRIDGE_ISR_GIO_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
1101 #define BRIDGE_ISR_PCI_RETRY_CNT        (0x1 << 10)
1102 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
1103 #define BRIDGE_ISR_GIO_B_ENBL_ERR       (0x1 << 8)
1104 #define BRIDGE_ISR_INT_MSK              (0xff << 0)
1105 #define BRIDGE_ISR_INT(x)               (0x1 << (x))
1106
1107 #define BRIDGE_ISR_LINK_ERROR           \
1108                 (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|     \
1109                  BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|           \
1110                  BRIDGE_ISR_LLP_TCTY)
1111
1112 #define BRIDGE_ISR_PCIBUS_PIOERR        \
1113                 (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT|       \
1114                  PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)
1115
1116 #define BRIDGE_ISR_PCIBUS_ERROR         \
1117                 (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|          \
1118                  BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|          \
1119                  BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR|               \
1120                  PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY|                 \
1121                  PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY|         \
1122                  PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP|          \
1123                  PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG|         \
1124                  PIC_ISR_PCIX_SPLIT_MSG_PE)
1125
1126 #define BRIDGE_ISR_XTALK_ERROR          \
1127                 (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
1128                  BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|      \
1129                  BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|      \
1130                  BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|      \
1131                  BRIDGE_ISR_UNEXP_RESP)
1132
1133 #define BRIDGE_ISR_ERRORS               \
1134                 (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|         \
1135                  BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
1136                  BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR)
1137
1138 /*
1139  * List of Errors which are fatal and kill the sytem
1140  */
1141 #define BRIDGE_ISR_ERROR_FATAL          \
1142                 ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
1143                  BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY|               \
1144                  PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY|                \
1145                  PIC_ISR_PCIX_DA_PARITY|                                  \
1146                  PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE )
1147
1148 #define BRIDGE_ISR_ERROR_DUMP           \
1149                 (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
1150                  BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
1151                  PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR)
1152
1153 /* Bridge interrupt enable register bits definition */
1154 #define PIC_IMR_PCIX_SPLIT_MSG_PE       PIC_ISR_PCIX_SPLIT_MSG_PE
1155 #define PIC_IMR_PCIX_SPLIT_EMSG         PIC_ISR_PCIX_SPLIT_EMSG
1156 #define PIC_IMR_PCIX_SPLIT_TO           PIC_ISR_PCIX_SPLIT_TO
1157 #define PIC_IMR_PCIX_UNEX_COMP          PIC_ISR_PCIX_UNEX_COMP
1158 #define PIC_IMR_INT_RAM_PERR            PIC_ISR_INT_RAM_PERR
1159 #define PIC_IMR_PCIX_ARB_ERR            PIC_ISR_PCIX_ARB_ERR
1160 #define PIC_IMR_PCIX_REQ_TOUR           PIC_ISR_PCIX_REQ_TOUT
1161 #define PIC_IMR_PCIX_TABORT             PIC_ISR_PCIX_TABORT
1162 #define PIC_IMR_PCIX_PERR               PIC_ISR_PCIX_PERR
1163 #define PIC_IMR_PCIX_SERR               PIC_ISR_PCIX_SERR
1164 #define PIC_IMR_PCIX_MRETRY             PIC_ISR_PCIX_MRETRY
1165 #define PIC_IMR_PCIX_MTOUT              PIC_ISR_PCIX_MTOUT
1166 #define PIC_IMR_PCIX_DA_PARITY          PIC_ISR_PCIX_DA_PARITY
1167 #define PIC_IMR_PCIX_AD_PARITY          PIC_ISR_PCIX_AD_PARITY
1168 #define BRIDGE_IMR_UNEXP_RESP           BRIDGE_ISR_UNEXP_RESP
1169 #define BRIDGE_IMR_PMU_ESIZE_FAULT      BRIDGE_ISR_PMU_ESIZE_FAULT
1170 #define BRIDGE_IMR_BAD_XRESP_PKT        BRIDGE_ISR_BAD_XRESP_PKT
1171 #define BRIDGE_IMR_BAD_XREQ_PKT         BRIDGE_ISR_BAD_XREQ_PKT
1172 #define BRIDGE_IMR_RESP_XTLK_ERR        BRIDGE_ISR_RESP_XTLK_ERR
1173 #define BRIDGE_IMR_REQ_XTLK_ERR         BRIDGE_ISR_REQ_XTLK_ERR
1174 #define BRIDGE_IMR_INVLD_ADDR           BRIDGE_ISR_INVLD_ADDR
1175 #define BRIDGE_IMR_UNSUPPORTED_XOP      BRIDGE_ISR_UNSUPPORTED_XOP
1176 #define BRIDGE_IMR_XREQ_FIFO_OFLOW      BRIDGE_ISR_XREQ_FIFO_OFLOW
1177 #define BRIDGE_IMR_LLP_REC_SNERR        BRIDGE_ISR_LLP_REC_SNERR
1178 #define BRIDGE_IMR_LLP_REC_CBERR        BRIDGE_ISR_LLP_REC_CBERR
1179 #define BRIDGE_IMR_LLP_RCTY             BRIDGE_ISR_LLP_RCTY
1180 #define BRIDGE_IMR_LLP_TX_RETRY         BRIDGE_ISR_LLP_TX_RETRY
1181 #define BRIDGE_IMR_LLP_TCTY             BRIDGE_ISR_LLP_TCTY
1182 #define BRIDGE_IMR_SSRAM_PERR           BRIDGE_ISR_SSRAM_PERR
1183 #define BRIDGE_IMR_PCI_ABORT            BRIDGE_ISR_PCI_ABORT
1184 #define BRIDGE_IMR_PCI_PARITY           BRIDGE_ISR_PCI_PARITY
1185 #define BRIDGE_IMR_PCI_SERR             BRIDGE_ISR_PCI_SERR
1186 #define BRIDGE_IMR_PCI_PERR             BRIDGE_ISR_PCI_PERR
1187 #define BRIDGE_IMR_PCI_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
1188 #define BRIDGE_IMR_GIO_MST_TIMEOUT      BRIDGE_ISR_GIO_MST_TIMEOUT
1189 #define BRIDGE_IMR_PCI_RETRY_CNT        BRIDGE_ISR_PCI_RETRY_CNT
1190 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
1191 #define BRIDGE_IMR_GIO_B_ENBL_ERR       BRIDGE_ISR_GIO_B_ENBL_ERR
1192 #define BRIDGE_IMR_INT_MSK              BRIDGE_ISR_INT_MSK
1193 #define BRIDGE_IMR_INT(x)               BRIDGE_ISR_INT(x)
1194
1195 /*
1196  * Bridge interrupt reset register bits definition.  Note, PIC can
1197  * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do
1198  * groups of them.
1199  */
1200 #define PIC_IRR_PCIX_SPLIT_MSG_PE       PIC_ISR_PCIX_SPLIT_MSG_PE
1201 #define PIC_IRR_PCIX_SPLIT_EMSG         PIC_ISR_PCIX_SPLIT_EMSG
1202 #define PIC_IRR_PCIX_SPLIT_TO           PIC_ISR_PCIX_SPLIT_TO
1203 #define PIC_IRR_PCIX_UNEX_COMP          PIC_ISR_PCIX_UNEX_COMP
1204 #define PIC_IRR_INT_RAM_PERR            PIC_ISR_INT_RAM_PERR
1205 #define PIC_IRR_PCIX_ARB_ERR            PIC_ISR_PCIX_ARB_ERR
1206 #define PIC_IRR_PCIX_REQ_TOUT           PIC_ISR_PCIX_REQ_TOUT
1207 #define PIC_IRR_PCIX_TABORT             PIC_ISR_PCIX_TABORT
1208 #define PIC_IRR_PCIX_PERR               PIC_ISR_PCIX_PERR
1209 #define PIC_IRR_PCIX_SERR               PIC_ISR_PCIX_SERR
1210 #define PIC_IRR_PCIX_MRETRY             PIC_ISR_PCIX_MRETRY
1211 #define PIC_IRR_PCIX_MTOUT              PIC_ISR_PCIX_MTOUT
1212 #define PIC_IRR_PCIX_DA_PARITY          PIC_ISR_PCIX_DA_PARITY
1213 #define PIC_IRR_PCIX_AD_PARITY          PIC_ISR_PCIX_AD_PARITY
1214 #define PIC_IRR_PAGE_FAULT              BRIDGE_ISR_PAGE_FAULT
1215 #define PIC_IRR_UNEXP_RESP              BRIDGE_ISR_UNEXP_RESP
1216 #define PIC_IRR_BAD_XRESP_PKT           BRIDGE_ISR_BAD_XRESP_PKT
1217 #define PIC_IRR_BAD_XREQ_PKT            BRIDGE_ISR_BAD_XREQ_PKT
1218 #define PIC_IRR_RESP_XTLK_ERR           BRIDGE_ISR_RESP_XTLK_ERR
1219 #define PIC_IRR_REQ_XTLK_ERR            BRIDGE_ISR_REQ_XTLK_ERR
1220 #define PIC_IRR_INVLD_ADDR              BRIDGE_ISR_INVLD_ADDR
1221 #define PIC_IRR_UNSUPPORTED_XOP         BRIDGE_ISR_UNSUPPORTED_XOP
1222 #define PIC_IRR_XREQ_FIFO_OFLOW         BRIDGE_ISR_XREQ_FIFO_OFLOW
1223 #define PIC_IRR_LLP_REC_SNERR           BRIDGE_ISR_LLP_REC_SNERR
1224 #define PIC_IRR_LLP_REC_CBERR           BRIDGE_ISR_LLP_REC_CBERR
1225 #define PIC_IRR_LLP_RCTY                BRIDGE_ISR_LLP_RCTY
1226 #define PIC_IRR_LLP_TX_RETRY            BRIDGE_ISR_LLP_TX_RETRY
1227 #define PIC_IRR_LLP_TCTY                BRIDGE_ISR_LLP_TCTY
1228 #define PIC_IRR_PCI_ABORT               BRIDGE_ISR_PCI_ABORT
1229 #define PIC_IRR_PCI_PARITY              BRIDGE_ISR_PCI_PARITY
1230 #define PIC_IRR_PCI_SERR                BRIDGE_ISR_PCI_SERR
1231 #define PIC_IRR_PCI_PERR                BRIDGE_ISR_PCI_PERR
1232 #define PIC_IRR_PCI_MST_TIMEOUT         BRIDGE_ISR_PCI_MST_TIMEOUT
1233 #define PIC_IRR_PCI_RETRY_CNT           BRIDGE_ISR_PCI_RETRY_CNT
1234 #define PIC_IRR_XREAD_REQ_TIMEOUT       BRIDGE_ISR_XREAD_REQ_TIMEOUT
1235 #define BRIDGE_IRR_MULTI_CLR            (0x1 << 6)
1236 #define BRIDGE_IRR_CRP_GRP_CLR          (0x1 << 5)
1237 #define BRIDGE_IRR_RESP_BUF_GRP_CLR     (0x1 << 4)
1238 #define BRIDGE_IRR_REQ_DSP_GRP_CLR      (0x1 << 3)
1239 #define BRIDGE_IRR_LLP_GRP_CLR          (0x1 << 2)
1240 #define BRIDGE_IRR_SSRAM_GRP_CLR        (0x1 << 1)
1241 #define BRIDGE_IRR_PCI_GRP_CLR          (0x1 << 0)
1242 #define BRIDGE_IRR_GIO_GRP_CLR          (0x1 << 0)
1243 #define BRIDGE_IRR_ALL_CLR              0x7f
1244
1245 #define BRIDGE_IRR_CRP_GRP              (BRIDGE_ISR_UNEXP_RESP | \
1246                                          BRIDGE_ISR_XREQ_FIFO_OFLOW)
1247 #define BRIDGE_IRR_RESP_BUF_GRP         (BRIDGE_ISR_BAD_XRESP_PKT | \
1248                                          BRIDGE_ISR_RESP_XTLK_ERR | \
1249                                          BRIDGE_ISR_XREAD_REQ_TIMEOUT)
1250 #define BRIDGE_IRR_REQ_DSP_GRP          (BRIDGE_ISR_UNSUPPORTED_XOP | \
1251                                          BRIDGE_ISR_BAD_XREQ_PKT | \
1252                                          BRIDGE_ISR_REQ_XTLK_ERR | \
1253                                          BRIDGE_ISR_INVLD_ADDR)
1254 #define BRIDGE_IRR_LLP_GRP              (BRIDGE_ISR_LLP_REC_SNERR | \
1255                                          BRIDGE_ISR_LLP_REC_CBERR | \
1256                                          BRIDGE_ISR_LLP_RCTY | \
1257                                          BRIDGE_ISR_LLP_TX_RETRY | \
1258                                          BRIDGE_ISR_LLP_TCTY)
1259 #define BRIDGE_IRR_SSRAM_GRP            (BRIDGE_ISR_SSRAM_PERR | \
1260                                          BRIDGE_ISR_PMU_ESIZE_FAULT)
1261 #define BRIDGE_IRR_PCI_GRP              (BRIDGE_ISR_PCI_ABORT | \
1262                                          BRIDGE_ISR_PCI_PARITY | \
1263                                          BRIDGE_ISR_PCI_SERR | \
1264                                          BRIDGE_ISR_PCI_PERR | \
1265                                          BRIDGE_ISR_PCI_MST_TIMEOUT | \
1266                                          BRIDGE_ISR_PCI_RETRY_CNT)
1267
1268 #define BRIDGE_IRR_GIO_GRP              (BRIDGE_ISR_GIO_B_ENBL_ERR | \
1269                                          BRIDGE_ISR_GIO_MST_TIMEOUT)
1270
1271 #define PIC_IRR_RAM_GRP                 PIC_ISR_INT_RAM_PERR
1272
1273 #define PIC_PCIX_GRP_CLR                (PIC_IRR_PCIX_AD_PARITY | \
1274                                          PIC_IRR_PCIX_DA_PARITY | \
1275                                          PIC_IRR_PCIX_MTOUT | \
1276                                          PIC_IRR_PCIX_MRETRY | \
1277                                          PIC_IRR_PCIX_SERR | \
1278                                          PIC_IRR_PCIX_PERR | \
1279                                          PIC_IRR_PCIX_TABORT | \
1280                                          PIC_ISR_PCIX_REQ_TOUT | \
1281                                          PIC_ISR_PCIX_UNEX_COMP | \
1282                                          PIC_ISR_PCIX_SPLIT_TO | \
1283                                          PIC_ISR_PCIX_SPLIT_EMSG | \
1284                                          PIC_ISR_PCIX_SPLIT_MSG_PE)
1285
1286 /* Bridge INT_DEV register bits definition */
1287 #define BRIDGE_INT_DEV_SHFT(n)          ((n)*3)
1288 #define BRIDGE_INT_DEV_MASK(n)          (0x7 << BRIDGE_INT_DEV_SHFT(n))
1289 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
1290
1291 /* Bridge interrupt(x) register bits definition */
1292 #define BRIDGE_INT_ADDR_HOST            0x0003FF00
1293 #define BRIDGE_INT_ADDR_FLD             0x000000FF
1294
1295 /* PIC interrupt(x) register bits definition */
1296 #define PIC_INT_ADDR_FLD                0x00FF000000000000
1297 #define PIC_INT_ADDR_HOST               0x0000FFFFFFFFFFFF
1298
1299 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
1300 #define BRIDGE_TMO_GIO_TIMEOUT_MASK     0x001000
1301 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
1302
1303 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
1304
1305 /* Bridge device(x) register bits definition */
1306 #define BRIDGE_DEV_ERR_LOCK_EN          (1ull << 28)
1307 #define BRIDGE_DEV_PAGE_CHK_DIS         (1ull << 27)
1308 #define BRIDGE_DEV_FORCE_PCI_PAR        (1ull << 26)
1309 #define BRIDGE_DEV_VIRTUAL_EN           (1ull << 25)
1310 #define BRIDGE_DEV_PMU_WRGA_EN          (1ull << 24)
1311 #define BRIDGE_DEV_DIR_WRGA_EN          (1ull << 23)
1312 #define BRIDGE_DEV_DEV_SIZE             (1ull << 22)
1313 #define BRIDGE_DEV_RT                   (1ull << 21)
1314 #define BRIDGE_DEV_SWAP_PMU             (1ull << 20)
1315 #define BRIDGE_DEV_SWAP_DIR             (1ull << 19)
1316 #define BRIDGE_DEV_PREF                 (1ull << 18)
1317 #define BRIDGE_DEV_PRECISE              (1ull << 17)
1318 #define BRIDGE_DEV_COH                  (1ull << 16)
1319 #define BRIDGE_DEV_BARRIER              (1ull << 15)
1320 #define BRIDGE_DEV_GBR                  (1ull << 14)
1321 #define BRIDGE_DEV_DEV_SWAP             (1ull << 13)
1322 #define BRIDGE_DEV_DEV_IO_MEM           (1ull << 12)
1323 #define BRIDGE_DEV_OFF_MASK             0x00000fff
1324 #define BRIDGE_DEV_OFF_ADDR_SHFT        20
1325
1326 #define XBRIDGE_DEV_PMU_BITS            BRIDGE_DEV_PMU_WRGA_EN
1327 #define BRIDGE_DEV_PMU_BITS             (BRIDGE_DEV_PMU_WRGA_EN         | \
1328                                          BRIDGE_DEV_SWAP_PMU)
1329 #define BRIDGE_DEV_D32_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
1330                                          BRIDGE_DEV_SWAP_DIR            | \
1331                                          BRIDGE_DEV_PREF                | \
1332                                          BRIDGE_DEV_PRECISE             | \
1333                                          BRIDGE_DEV_COH                 | \
1334                                          BRIDGE_DEV_BARRIER)
1335 #define XBRIDGE_DEV_D64_BITS            (BRIDGE_DEV_DIR_WRGA_EN         | \
1336                                          BRIDGE_DEV_COH                 | \
1337                                          BRIDGE_DEV_BARRIER)
1338 #define BRIDGE_DEV_D64_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
1339                                          BRIDGE_DEV_SWAP_DIR            | \
1340                                          BRIDGE_DEV_COH                 | \
1341                                          BRIDGE_DEV_BARRIER)
1342
1343 /* Bridge Error Upper register bit field definition */
1344 #define BRIDGE_ERRUPPR_DEVMASTER        (0x1 << 20)     /* Device was master */
1345 #define BRIDGE_ERRUPPR_PCIVDEV          (0x1 << 19)     /* Virtual Req value */
1346 #define BRIDGE_ERRUPPR_DEVNUM_SHFT      (16)
1347 #define BRIDGE_ERRUPPR_DEVNUM_MASK      (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
1348 #define BRIDGE_ERRUPPR_DEVICE(err)      (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
1349 #define BRIDGE_ERRUPPR_ADDRMASK         (0xFFFF)
1350
1351 /* Bridge interrupt mode register bits definition */
1352 #define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
1353
1354 /* this should be written to the xbow's link_control(x) register */
1355 #define BRIDGE_CREDIT   3
1356
1357 /* RRB assignment register */
1358 #define BRIDGE_RRB_EN   0x8     /* after shifting down */
1359 #define BRIDGE_RRB_DEV  0x7     /* after shifting down */
1360 #define BRIDGE_RRB_VDEV 0x4     /* after shifting down, 2 virtual channels */
1361 #define BRIDGE_RRB_PDEV 0x3     /* after shifting down, 8 devices */
1362
1363 #define PIC_RRB_EN      0x8     /* after shifting down */
1364 #define PIC_RRB_DEV     0x7     /* after shifting down */
1365 #define PIC_RRB_VDEV    0x6     /* after shifting down, 4 virtual channels */
1366 #define PIC_RRB_PDEV    0x1     /* after shifting down, 4 devices */
1367
1368 /* RRB status register */
1369 #define BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
1370 #define BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
1371
1372 /* RRB clear register */
1373 #define BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
1374
1375 /* Defines for the virtual channels so we don't hardcode 0-3 within code */
1376 #define VCHAN0  0       /* virtual channel 0 (ie. the "normal" channel) */
1377 #define VCHAN1  1       /* virtual channel 1 */
1378 #define VCHAN2  2       /* virtual channel 2 - PIC only */
1379 #define VCHAN3  3       /* virtual channel 3 - PIC only */
1380
1381 /* PIC: PCI-X Read Buffer Attribute Register (RBAR) */
1382 #define NUM_RBAR 16     /* number of RBAR registers */
1383
1384 /* xbox system controller declarations */
1385 #define XBOX_BRIDGE_WID         8
1386 #define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
1387 #define XBOX_RPS_EXISTS         1 << 6   /* RPS bit in status register */
1388 #define XBOX_RPS_FAIL           1 << 4   /* RPS status bit in register */
1389
1390 /* ========================================================================
1391  */
1392 /*
1393  * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
1394  * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
1395  */
1396 /* XTALK addresses that map into Bridge Bus addr space */
1397 #define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
1398 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
1399 #define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
1400 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
1401 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
1402 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
1403
1404 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
1405 #define BRIDGE_MIN_PIO_ADDR_MEM         0x00000000      /* 1G PCI memory space */
1406 #define BRIDGE_MAX_PIO_ADDR_MEM         0x3fffffff
1407 #define BRIDGE_MIN_PIO_ADDR_IO          0x00000000      /* 4G PCI IO space */
1408 #define BRIDGE_MAX_PIO_ADDR_IO          0xffffffff
1409
1410 /* XTALK addresses that map into PCI addresses */
1411 #define BRIDGE_PCI_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
1412 #define BRIDGE_PCI_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
1413 #define BRIDGE_PCI_MEM64_BASE           BRIDGE_PIO64_XTALK_ALIAS_BASE
1414 #define BRIDGE_PCI_MEM64_LIMIT          BRIDGE_PIO64_XTALK_ALIAS_LIMIT
1415 #define BRIDGE_PCI_IO_BASE              BRIDGE_PCIIO_XTALK_ALIAS_BASE
1416 #define BRIDGE_PCI_IO_LIMIT             BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
1417
1418 /*
1419  * Macros for Xtalk to Bridge bus (PCI) PIO
1420  * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II
1421  * Programmer's Reference" (Revision 0.8 as of this writing).
1422  *
1423  * These are PIC bridge specific.  A separate set of macros was defined
1424  * because PIC deviates from Bridge/Xbridge by not supporting a big-window
1425  * alias for PCI I/O space, and also redefines XTALK addresses
1426  * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second
1427  * bus.
1428  */
1429
1430 /* XTALK addresses that map into PIC Bridge Bus addr space */
1431 #define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE       0x000040000000L
1432 #define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT      0x00007FFFFFFFL
1433 #define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE       0x000080000000L
1434 #define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT      0x0000BFFFFFFFL
1435 #define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE       0x0000C0000000L
1436 #define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT      0x0000FFFFFFFFL
1437 #define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE       0x000100000000L
1438 #define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT      0x00013FFFFFFFL
1439
1440 /* XTALK addresses that map into PCI addresses */
1441 #define PICBRIDGE0_PCI_MEM32_BASE       PICBRIDGE0_PIO32_XTALK_ALIAS_BASE
1442 #define PICBRIDGE0_PCI_MEM32_LIMIT      PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT
1443 #define PICBRIDGE0_PCI_MEM64_BASE       PICBRIDGE0_PIO64_XTALK_ALIAS_BASE
1444 #define PICBRIDGE0_PCI_MEM64_LIMIT      PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT
1445 #define PICBRIDGE1_PCI_MEM32_BASE       PICBRIDGE1_PIO32_XTALK_ALIAS_BASE
1446 #define PICBRIDGE1_PCI_MEM32_LIMIT      PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT
1447 #define PICBRIDGE1_PCI_MEM64_BASE       PICBRIDGE1_PIO64_XTALK_ALIAS_BASE
1448 #define PICBRIDGE1_PCI_MEM64_LIMIT      PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT
1449
1450 /*
1451  * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
1452  */
1453 /* Bridge Bus DMA addresses */
1454 #define BRIDGE_LOCAL_BASE               0
1455 #define BRIDGE_DMA_MAPPED_BASE          0x40000000
1456 #define BRIDGE_DMA_MAPPED_SIZE          0x40000000      /* 1G Bytes */
1457 #define BRIDGE_DMA_DIRECT_BASE          0x80000000
1458 #define BRIDGE_DMA_DIRECT_SIZE          0x80000000      /* 2G Bytes */
1459
1460 #define PCI32_LOCAL_BASE                BRIDGE_LOCAL_BASE
1461
1462 /* PCI addresses of regions decoded by Bridge for DMA */
1463 #define PCI32_MAPPED_BASE               BRIDGE_DMA_MAPPED_BASE
1464 #define PCI32_DIRECT_BASE               BRIDGE_DMA_DIRECT_BASE
1465
1466 #ifndef __ASSEMBLY__
1467
1468 #define IS_PCI32_LOCAL(x)       ((uint64_t)(x) < PCI32_MAPPED_BASE)
1469 #define IS_PCI32_MAPPED(x)      ((uint64_t)(x) < PCI32_DIRECT_BASE && \
1470                                         (uint64_t)(x) >= PCI32_MAPPED_BASE)
1471 #define IS_PCI32_DIRECT(x)      ((uint64_t)(x) >= PCI32_MAPPED_BASE)
1472 #define IS_PCI64(x)             ((uint64_t)(x) >= PCI64_BASE)
1473 #endif                          /* __ASSEMBLY__ */
1474
1475 /*
1476  * The GIO address space.
1477  */
1478 /* Xtalk to GIO PIO */
1479 #define BRIDGE_GIO_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
1480 #define BRIDGE_GIO_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
1481
1482 #define GIO_LOCAL_BASE                  BRIDGE_LOCAL_BASE
1483
1484 /* GIO addresses of regions decoded by Bridge for DMA */
1485 #define GIO_MAPPED_BASE                 BRIDGE_DMA_MAPPED_BASE
1486 #define GIO_DIRECT_BASE                 BRIDGE_DMA_DIRECT_BASE
1487
1488 #ifndef __ASSEMBLY__
1489
1490 #define IS_GIO_LOCAL(x)         ((uint64_t)(x) < GIO_MAPPED_BASE)
1491 #define IS_GIO_MAPPED(x)        ((uint64_t)(x) < GIO_DIRECT_BASE && \
1492                                         (uint64_t)(x) >= GIO_MAPPED_BASE)
1493 #define IS_GIO_DIRECT(x)        ((uint64_t)(x) >= GIO_MAPPED_BASE)
1494 #endif                          /* __ASSEMBLY__ */
1495
1496 /* PCI to xtalk mapping */
1497
1498 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
1499  * which xtalk address is accessed
1500  */
1501 #define BRIDGE_DIRECT_32_SEG_SIZE       BRIDGE_DMA_DIRECT_SIZE
1502 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)          \
1503         ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +        \
1504                 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
1505
1506 /* 64-bit address attribute masks */
1507 #define PCI64_ATTR_TARG_MASK    0xf000000000000000
1508 #define PCI64_ATTR_TARG_SHFT    60
1509 #define PCI64_ATTR_PREF         (1ull << 59)
1510 #define PCI64_ATTR_PREC         (1ull << 58)
1511 #define PCI64_ATTR_VIRTUAL      (1ull << 57)
1512 #define PCI64_ATTR_BAR          (1ull << 56)
1513 #define PCI64_ATTR_SWAP         (1ull << 55)
1514 #define PCI64_ATTR_RMF_MASK     0x00ff000000000000
1515 #define PCI64_ATTR_RMF_SHFT     48
1516
1517 #ifndef __ASSEMBLY__
1518 /* Address translation entry for mapped pci32 accesses */
1519 typedef union ate_u {
1520     uint64_t                ent;
1521     struct xb_ate_s {                                   /* xbridge */
1522         uint64_t                :16;
1523         uint64_t                addr:36;
1524         uint64_t                targ:4;
1525         uint64_t                reserved:2;
1526         uint64_t                swap:1;
1527         uint64_t                barrier:1;
1528         uint64_t                prefetch:1;
1529         uint64_t                precise:1;
1530         uint64_t                coherent:1;
1531         uint64_t                valid:1;
1532     } xb_field;
1533     struct ate_s {                                      /* bridge */
1534         uint64_t                rmf:16;
1535         uint64_t                addr:36;
1536         uint64_t                targ:4;
1537         uint64_t                reserved:3;
1538         uint64_t                barrier:1;
1539         uint64_t                prefetch:1;
1540         uint64_t                precise:1;
1541         uint64_t                coherent:1;
1542         uint64_t                valid:1;
1543     } field;
1544 } ate_t;
1545 #endif                          /* __ASSEMBLY__ */
1546
1547 #define ATE_V           (1 << 0)
1548 #define ATE_CO          (1 << 1)
1549 #define ATE_PREC        (1 << 2)
1550 #define ATE_PREF        (1 << 3)
1551 #define ATE_BAR         (1 << 4)
1552 #define ATE_SWAP        (1 << 5)
1553
1554 #define ATE_PFNSHIFT            12
1555 #define ATE_TIDSHIFT            8
1556 #define ATE_RMFSHIFT            48
1557
1558 #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
1559                                 ((xid)<<ATE_TIDSHIFT) | \
1560                                 (attr)
1561
1562 /*
1563  * for xbridge, bit 29 of the pci address is the swap bit */
1564 #define ATE_SWAPSHIFT           29
1565 #define ATE_SWAP_ON(x)          ((x) |= (1 << ATE_SWAPSHIFT))
1566 #define ATE_SWAP_OFF(x)         ((x) &= ~(1 << ATE_SWAPSHIFT))
1567
1568 /* extern declarations */
1569
1570 #ifndef __ASSEMBLY__
1571
1572 /* ========================================================================
1573  */
1574
1575 #ifdef  MACROFIELD_LINE
1576 /*
1577  * This table forms a relation between the byte offset macros normally
1578  * used for ASM coding and the calculated byte offsets of the fields
1579  * in the C structure.
1580  *
1581  * See bridge_check.c and bridge_html.c for further details.
1582  */
1583 #ifndef MACROFIELD_LINE_BITFIELD
1584 #define MACROFIELD_LINE_BITFIELD(m)     /* ignored */
1585 #endif
1586
1587 struct macrofield_s     bridge_macrofield[] =
1588 {
1589
1590     MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id)
1591     MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM)
1592     MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM)
1593     MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM)
1594     MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat)
1595     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT)
1596     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT)
1597     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT)
1598     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N)
1599     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING)
1600     MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper)
1601     MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower)
1602     MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control)
1603     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN)
1604     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50)
1605     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40)
1606     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33)
1607     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK)
1608     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP)
1609     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP)
1610     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE)
1611     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD)
1612     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN)
1613     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK)
1614     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT)
1615     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK)
1616     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT)
1617     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT)
1618     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END)
1619     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK)
1620     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK)
1621     MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout)
1622     MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper)
1623     MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR)
1624     MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID)
1625     MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR)
1626     MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower)
1627     MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword)
1628     MACROFIELD_LINE_BITFIELD(WIDGET_DIDN)
1629     MACROFIELD_LINE_BITFIELD(WIDGET_SIDN)
1630     MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP)
1631     MACROFIELD_LINE_BITFIELD(WIDGET_TNUM)
1632     MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT)
1633     MACROFIELD_LINE_BITFIELD(WIDGET_DS)
1634     MACROFIELD_LINE_BITFIELD(WIDGET_GBR)
1635     MACROFIELD_LINE_BITFIELD(WIDGET_VBPM)
1636     MACROFIELD_LINE_BITFIELD(WIDGET_ERROR)
1637     MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER)
1638     MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp)
1639     MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY)
1640     MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT)
1641     MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST)
1642     MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush)
1643     MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err)
1644     MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper)
1645     MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower)
1646     MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl)
1647     MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map)
1648     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID)
1649     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64)
1650     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512)
1651     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF)
1652     MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr)
1653     MACROFIELD_LINE(BRIDGE_ARB, b_arb)
1654     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK)
1655     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK)
1656     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT)
1657     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2)
1658     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1)
1659     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0)
1660     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2)
1661     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1)
1662     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0)
1663     MACROFIELD_LINE(BRIDGE_NIC, b_nic)
1664     MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout)
1665     MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg)
1666     MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper)
1667     MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower)
1668     MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status)
1669     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR)
1670     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT)
1671     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP)
1672     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT)
1673     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT)
1674     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR)
1675     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR)
1676     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR)
1677     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP)
1678     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW)
1679     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR)
1680     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR)
1681     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY)
1682     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY)
1683     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY)
1684     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR)
1685     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT)
1686     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY)
1687     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR)
1688     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR)
1689     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT)
1690     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT)
1691     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT)
1692     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR)
1693     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK)
1694     MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable)
1695     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP)
1696     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT)
1697     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT)
1698     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT)
1699     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR)
1700     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR)
1701     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR)
1702     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP)
1703     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW)
1704     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR)
1705     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR)
1706     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY)
1707     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY)
1708     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY)
1709     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR)
1710     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT)
1711     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY)
1712     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR)
1713     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR)
1714     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT)
1715     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT)
1716     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT)
1717     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR)
1718     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK)
1719     MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat)
1720     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR)
1721     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR)
1722     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR)
1723     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR)
1724     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR)
1725     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR)
1726     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR)
1727     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR)
1728     MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode)
1729     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7))
1730     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6))
1731     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5))
1732     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4))
1733     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3))
1734     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2))
1735     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1))
1736     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0))
1737     MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device)
1738     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7))
1739     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6))
1740     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5))
1741     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4))
1742     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3))
1743     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2))
1744     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1))
1745     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0))
1746     MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err)
1747     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST)
1748     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD)
1749     MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr)
1750     MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr)
1751     MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr)
1752     MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr)
1753     MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr)
1754     MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr)
1755     MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr)
1756     MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr)
1757     MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr)
1758     MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg)
1759     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN)
1760     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS)
1761     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR)
1762     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN)
1763     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN)
1764     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN)
1765     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE)
1766     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT)
1767     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU)
1768     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR)
1769     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF)
1770     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE)
1771     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH)
1772     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER)
1773     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR)
1774     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP)
1775     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM)
1776     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK)
1777     MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg)
1778     MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg)
1779     MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg)
1780     MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg)
1781     MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg)
1782     MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg)
1783     MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg)
1784     MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg)
1785     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg)
1786     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg)
1787     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg)
1788     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg)
1789     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg)
1790     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg)
1791     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg)
1792     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg)
1793     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg)
1794     MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp)
1795     MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp)
1796     MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status)
1797     MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear)
1798     MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram)
1799     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0])
1800
1801     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0])
1802     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0])
1803     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1])
1804     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2])
1805     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3])
1806     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4])
1807     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5])
1808     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6])
1809     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7])
1810     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1])
1811     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0])
1812     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1])
1813     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2])
1814     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3])
1815     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4])
1816     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5])
1817     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6])
1818     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7])
1819     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2])
1820     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0])
1821     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1])
1822     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2])
1823     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3])
1824     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4])
1825     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5])
1826     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6])
1827     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7])
1828     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3])
1829     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0])
1830     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1])
1831     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2])
1832     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3])
1833     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4])
1834     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5])
1835     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6])
1836     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7])
1837     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4])
1838     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0])
1839     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1])
1840     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2])
1841     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3])
1842     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4])
1843     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5])
1844     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6])
1845     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7])
1846     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5])
1847     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0])
1848     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1])
1849     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2])
1850     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3])
1851     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4])
1852     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5])
1853     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6])
1854     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7])
1855     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6])
1856     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0])
1857     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1])
1858     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2])
1859     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3])
1860     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4])
1861     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5])
1862     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6])
1863     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7])
1864     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7])
1865     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0])
1866     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1])
1867     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2])
1868     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3])
1869     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4])
1870     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5])
1871     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6])
1872     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7])
1873
1874     MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg)
1875     MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack)
1876     MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram)
1877     MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0))
1878     MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0))
1879     MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1))
1880     MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2))
1881     MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3))
1882     MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4))
1883     MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5))
1884     MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6))
1885     MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7))
1886     MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash)
1887 };
1888 #endif
1889
1890 #ifdef __cplusplus
1891 };
1892 #endif
1893 #endif                          /* C or C++ */
1894
1895 #endif                          /* _ASM_SN_PCI_BRIDGE_H */