2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved.
8 #ifndef _ASM_IA64_SN_PCI_PCIBR_H
9 #define _ASM_IA64_SN_PCI_PCIBR_H
11 #if defined(__KERNEL__)
13 #include <linux/config.h>
14 #include <asm/sn/dmamap.h>
15 #include <asm/sn/driver.h>
16 #include <asm/sn/pio.h>
18 #include <asm/sn/pci/pciio.h>
19 #include <asm/sn/pci/bridge.h>
21 /* =====================================================================
22 * symbolic constants used by pcibr's xtalk bus provider
25 #define PCIBR_PIOMAP_BUSY 0x80000000
27 #define PCIBR_DMAMAP_BUSY 0x80000000
28 #define PCIBR_DMAMAP_SSRAM 0x40000000
30 #define PCIBR_INTR_BLOCKED 0x40000000
31 #define PCIBR_INTR_BUSY 0x80000000
35 /* =====================================================================
36 * opaque types used by pcibr's xtalk bus provider
39 typedef struct pcibr_piomap_s *pcibr_piomap_t;
40 typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
41 typedef struct pcibr_intr_s *pcibr_intr_t;
43 /* =====================================================================
44 * bus provider function table
46 * Normally, this table is only handed off explicitly
47 * during provider initialization, and the PCI generic
48 * layer will stash a pointer to it in the vertex; however,
49 * exporting it explicitly enables a performance hack in
50 * the generic PCI provider where if we know at compile
51 * time that the only possible PCI provider is a
52 * pcibr, we can go directly to this ops table.
55 extern pciio_provider_t pci_pic_provider;
57 /* =====================================================================
58 * secondary entry points: pcibr PCI bus provider
60 * These functions are normally exported explicitly by
61 * a direct call from the pcibr initialization routine
62 * into the generic crosstalk provider; they are included
63 * here to enable a more aggressive performance hack in
64 * the generic crosstalk layer, where if we know that the
65 * only possible crosstalk provider is pcibr, and we can
66 * guarantee that all entry points are properly named, and
67 * we can deal with the implicit casting properly, then
68 * we can turn many of the generic provider routines into
69 * plain brances, or even eliminate them (given sufficient
70 * smarts on the part of the compilation system).
73 extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev,
74 device_desc_t dev_desc,
78 size_t byte_count_max,
81 extern void pcibr_piomap_free(pcibr_piomap_t piomap);
83 extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap,
87 extern void pcibr_piomap_done(pcibr_piomap_t piomap);
89 extern int pcibr_piomap_probe(pcibr_piomap_t piomap,
94 extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev,
95 device_desc_t dev_desc,
101 extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev,
102 device_desc_t dev_desc,
106 extern void pcibr_piospace_free(vertex_hdl_t dev,
111 extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev,
112 device_desc_t dev_desc,
113 size_t byte_count_max,
116 extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap);
118 extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap,
122 extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap);
125 * pcibr_get_dmatrans_node() will return the compact node id to which
126 * all 32-bit Direct Mapping memory accesses will be directed.
127 * (This node id can be different for each PCI bus.)
130 extern cnodeid_t pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl);
132 extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev,
133 device_desc_t dev_desc,
138 extern void pcibr_dmamap_drain(pcibr_dmamap_t map);
140 extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl,
144 typedef unsigned pcibr_intr_ibit_f(pciio_info_t info,
145 pciio_intr_line_t lines);
147 extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *);
149 extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev,
150 device_desc_t dev_desc,
151 pciio_intr_line_t lines,
152 vertex_hdl_t owner_dev);
154 extern void pcibr_intr_free(pcibr_intr_t intr);
156 extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t);
158 extern void pcibr_intr_disconnect(pcibr_intr_t intr);
160 extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr);
162 extern void pcibr_provider_startup(vertex_hdl_t pcibr);
164 extern void pcibr_provider_shutdown(vertex_hdl_t pcibr);
166 extern int pcibr_reset(vertex_hdl_t dev);
168 extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev,
169 pciio_endian_t device_end,
170 pciio_endian_t desired_end);
172 extern uint64_t pcibr_config_get(vertex_hdl_t conn,
176 extern void pcibr_config_set(vertex_hdl_t conn,
181 extern pciio_slot_t pcibr_error_extract(vertex_hdl_t pcibr_vhdl,
182 pciio_space_t *spacep,
185 extern int pcibr_wrb_flush(vertex_hdl_t pconn_vhdl);
186 extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
192 extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd,
193 int dev_1_rrbs, int virt1,
194 int dev_2_rrbs, int virt2,
195 int dev_3_rrbs, int virt3,
196 int dev_4_rrbs, int virt4);
199 rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl,
202 typedef rrb_alloc_funct_f *rrb_alloc_funct_t;
204 void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl,
205 rrb_alloc_funct_f *func);
207 extern int pcibr_device_unregister(vertex_hdl_t);
208 extern void pcibr_driver_reg_callback(vertex_hdl_t, int, int, int);
209 extern void pcibr_driver_unreg_callback(vertex_hdl_t,
213 extern void * pcibr_bridge_ptr_get(vertex_hdl_t, int);
216 * Bridge-specific flags that can be set via pcibr_device_flags_set
217 * and cleared via pcibr_device_flags_clear. Other flags are
218 * more generic and are maniuplated through PCI-generic interfaces.
220 * Note that all PCI implementation-specific flags (Bridge flags, in
221 * this case) are in bits 15-31. The lower 15 bits are reserved
222 * for PCI-generic flags.
224 * Some of these flags have been "promoted" to the
225 * generic layer, so they can be used without having
226 * to "know" that the PCI bus is hosted by a Bridge.
228 * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when
229 * allocating ATE's. ATE count computation will assume that the
230 * address to be mapped will start on a page boundary.
232 #define PCIBR_NO_ATE_ROUNDUP 0x00008000
233 #define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */
234 #define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */
235 #define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */
236 #define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */
237 #define PCIBR_PRECISE 0x00100000
238 #define PCIBR_NOPRECISE 0x00200000
239 #define PCIBR_BARRIER 0x00400000
240 #define PCIBR_NOBARRIER 0x00800000
241 #define PCIBR_VCHAN0 0x01000000
242 #define PCIBR_VCHAN1 0x02000000
243 #define PCIBR_64BIT 0x04000000
244 #define PCIBR_NO64BIT 0x08000000
245 #define PCIBR_SWAP 0x10000000
246 #define PCIBR_NOSWAP 0x20000000
248 #define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */
249 #define PCIBR_ACTIVE 0x80000000 /* need a "done" */
251 /* Flags that have meaning to pcibr_device_flags_{set,clear} */
252 #define PCIBR_DEVICE_FLAGS ( \
253 PCIBR_WRITE_GATHER |\
254 PCIBR_NOWRITE_GATHER |\
263 /* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */
264 #define PCIBR_DMA_FLAGS ( \
275 typedef int pcibr_device_flags_t;
277 #define MINIMAL_ATES_REQUIRED(addr, size) \
278 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
280 #define MINIMAL_ATE_FLAG(addr, size) \
281 (MINIMAL_ATES_REQUIRED((u_long)addr, size) ? PCIBR_NO_ATE_ROUNDUP : 0)
284 * Set bits in the Bridge Device(x) register for this device.
285 * "flags" are defined above. NOTE: this includes turning
286 * things *OFF* as well as turning them *ON* ...
288 extern int pcibr_device_flags_set(vertex_hdl_t dev,
289 pcibr_device_flags_t flags);
292 * Allocate Read Response Buffers for use by the specified device.
293 * count_vchan0 is the total number of buffers desired for the
294 * "normal" channel. count_vchan1 is the total number of buffers
295 * desired for the "virtual" channel. Returns 0 on success, or
296 * <0 on failure, which occurs when we're unable to allocate any
297 * buffers to a channel that desires at least one buffer.
299 extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
304 * Get the starting PCIbus address out of the given DMA map.
305 * This function is supposed to be used by a close friend of PCI bridge
306 * since it relies on the fact that the starting address of the map is fixed at
307 * the allocation time in the current implementation of PCI bridge.
309 extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
310 extern void pcibr_hints_fix_rrbs(vertex_hdl_t);
311 extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t);
312 extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong);
313 extern void pcibr_hints_handsoff(vertex_hdl_t);
315 typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int);
316 extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *);
318 extern int pcibr_asic_rev(vertex_hdl_t);
320 #endif /* __ASSEMBLY__ */
321 #endif /* #if defined(__KERNEL__) */
323 * Some useful ioctls into the pcibr driver
326 #define _PCIBR(x) ((PCIBR << 8) | (x))
329 * Bit defintions for variable slot_status in struct
330 * pcibr_soft_slot_s. They are here so that the user
331 * hot-plug utility can interpret the slot's power
334 #ifdef CONFIG_HOTPLUG_PCI_SGI
335 #define PCI_SLOT_ENABLE_CMPLT 0x01
336 #define PCI_SLOT_ENABLE_INCMPLT 0x02
337 #define PCI_SLOT_DISABLE_CMPLT 0x04
338 #define PCI_SLOT_DISABLE_INCMPLT 0x08
339 #define PCI_SLOT_POWER_ON 0x10
340 #define PCI_SLOT_POWER_OFF 0x20
341 #define PCI_SLOT_IS_SYS_CRITICAL 0x40
342 #define PCI_SLOT_PCIBA_LOADED 0x80
344 #define PCI_SLOT_STATUS_MASK (PCI_SLOT_ENABLE_CMPLT | \
345 PCI_SLOT_ENABLE_INCMPLT | \
346 PCI_SLOT_DISABLE_CMPLT | \
347 PCI_SLOT_DISABLE_INCMPLT)
348 #define PCI_SLOT_POWER_MASK (PCI_SLOT_POWER_ON | PCI_SLOT_POWER_OFF)
351 * Bit defintions for variable slot_status in struct
352 * pcibr_soft_slot_s. They are here so that both
353 * the pcibr driver and the pciconfig command can
356 #define SLOT_STARTUP_CMPLT 0x01
357 #define SLOT_STARTUP_INCMPLT 0x02
358 #define SLOT_SHUTDOWN_CMPLT 0x04
359 #define SLOT_SHUTDOWN_INCMPLT 0x08
360 #define SLOT_POWER_UP 0x10
361 #define SLOT_POWER_DOWN 0x20
362 #define SLOT_IS_SYS_CRITICAL 0x40
364 #define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \
365 SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT)
366 #define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN)
369 * Bit definitions for variable resp_f_staus.
370 * They are here so that both the pcibr driver
371 * and the pciconfig command can reference them.
373 #define FUNC_IS_VALID 0x01
374 #define FUNC_IS_SYS_CRITICAL 0x02
377 * L1 slot power operations for PCI hot-plug
379 #define PCI_REQ_SLOT_POWER_ON 1
380 #define PCI_L1_QSIZE 128 /* our L1 message buffer size */
383 #define L1_QSIZE 128 /* our L1 message buffer size */
385 enum pcibr_slot_disable_action_e {
386 PCI_REQ_SLOT_ELIGIBLE,
391 struct pcibr_slot_up_resp_s {
393 char resp_l1_msg[L1_QSIZE + 1];
396 struct pcibr_slot_down_resp_s {
398 char resp_l1_msg[L1_QSIZE + 1];
401 struct pcibr_slot_info_resp_s {
402 short resp_bs_bridge_type;
403 short resp_bs_bridge_mode;
406 vertex_hdl_t resp_slot_conn;
407 char resp_slot_conn_name[MAXDEVNAME];
408 int resp_slot_status;
411 char resp_bss_devio_bssd_space[16];
412 iopaddr_t resp_bss_devio_bssd_base;
413 uint64_t resp_bss_device;
414 int resp_bss_pmu_uctr;
415 int resp_bss_d32_uctr;
416 int resp_bss_d64_uctr;
417 iopaddr_t resp_bss_d64_base;
418 unsigned resp_bss_d64_flags;
419 iopaddr_t resp_bss_d32_base;
420 unsigned resp_bss_d32_flags;
421 volatile unsigned *resp_bss_cmd_pointer;
422 unsigned resp_bss_cmd_shadow;
423 int resp_bs_rrb_valid;
424 int resp_bs_rrb_valid_v1;
425 int resp_bs_rrb_valid_v2;
426 int resp_bs_rrb_valid_v3;
428 uint64_t resp_b_resp;
429 uint64_t resp_b_int_device;
430 uint64_t resp_b_int_enable;
431 uint64_t resp_b_int_host;
432 struct pcibr_slot_func_info_resp_s {
434 char resp_f_slot_name[MAXDEVNAME];
438 char resp_f_master_name[MAXDEVNAME];
440 error_handler_f *resp_f_efunc;
441 error_handler_arg_t resp_f_einfo;
446 char resp_w_space[16];
447 iopaddr_t resp_w_base;
451 unsigned resp_f_rbase;
452 unsigned resp_f_rsize;
454 int resp_f_att_det_error;
459 struct pcibr_slot_req_s {
462 enum pcibr_slot_disable_action_e up;
463 struct pcibr_slot_down_resp_s *down;
464 struct pcibr_slot_info_resp_s *query;
470 struct pcibr_slot_enable_resp_s {
472 char resp_l1_msg[PCI_L1_QSIZE + 1];
475 struct pcibr_slot_disable_resp_s {
477 char resp_l1_msg[PCI_L1_QSIZE + 1];
480 struct pcibr_slot_enable_req_s {
481 pciio_slot_t req_device;
482 struct pcibr_slot_enable_resp_s req_resp;
485 struct pcibr_slot_disable_req_s {
486 pciio_slot_t req_device;
487 enum pcibr_slot_disable_action_e req_action;
488 struct pcibr_slot_disable_resp_s req_resp;
491 struct pcibr_slot_info_req_s {
492 pciio_slot_t req_device;
493 struct pcibr_slot_info_resp_s req_resp;
496 #endif /* CONFIG_HOTPLUG_PCI_SGI */
500 * PCI specific errors, interpreted by pciconfig command
504 #define PCI_SLOT_ALREADY_UP 2 /* slot already up */
505 #define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */
506 #define PCI_IS_SYS_CRITICAL 4 /* slot is system critical */
509 #define PCI_L1_ERR 7 /* L1 console command error */
510 #define PCI_NOT_A_BRIDGE 8 /* device is not a bridge */
511 #define PCI_SLOT_IN_SHOEHORN 9 /* slot is in a shorhorn */
512 #define PCI_NOT_A_SLOT 10 /* slot is invalid */
513 #define PCI_RESP_AREA_TOO_SMALL 11 /* slot is invalid */
515 #define PCI_NO_DRIVER 13 /* no driver for device */
517 #define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */
519 #define PCI_SLOT_RESET_ERR 17 /* slot reset error */
520 #define PCI_SLOT_INFO_INIT_ERR 18 /* slot info init error */
522 #define PCI_SLOT_ADDR_INIT_ERR 20 /* slot addr space init error */
523 #define PCI_SLOT_DEV_INIT_ERR 21 /* slot device init error */
525 #define PCI_SLOT_GUEST_INIT_ERR 23 /* slot guest info init error */
526 #define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */
527 #define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */
528 #define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */
530 #define PCI_MULTI_FUNC_ERR 28 /* multi-function card error */
531 #define PCI_SLOT_RBAR_ALLOC_ERR 29 /* slot PCI-X RBAR alloc error */
535 #endif /* _ASM_IA64_SN_PCI_PCIBR_H */