2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
8 #ifndef _ASM_IA64_SN_PCI_PCIIO_PRIVATE_H
9 #define _ASM_IA64_SN_PCI_PCIIO_PRIVATE_H
11 #include <asm/sn/pci/pciio.h>
12 #include <asm/sn/pci/pci_defs.h>
15 * pciio_private.h -- private definitions for pciio
16 * PCI drivers should NOT include this file.
20 * All PCI providers set up PIO using this information.
22 struct pciio_piomap_s {
23 unsigned int pp_flags; /* PCIIO_PIOMAP flags */
24 vertex_hdl_t pp_dev; /* associated pci card */
25 pciio_slot_t pp_slot; /* which slot the card is in */
26 pciio_space_t pp_space; /* which address space */
27 iopaddr_t pp_pciaddr; /* starting offset of mapping */
28 size_t pp_mapsz; /* size of this mapping */
29 caddr_t pp_kvaddr; /* kernel virtual address to use */
33 * All PCI providers set up DMA using this information.
35 struct pciio_dmamap_s {
36 unsigned int pd_flags; /* PCIIO_DMAMAP flags */
37 vertex_hdl_t pd_dev; /* associated pci card */
38 pciio_slot_t pd_slot; /* which slot the card is in */
42 * All PCI providers set up interrupts using this information.
46 unsigned int pi_flags; /* PCIIO_INTR flags */
47 vertex_hdl_t pi_dev; /* associated pci card */
48 device_desc_t pi_dev_desc; /* override device descriptor */
49 pciio_intr_line_t pi_lines; /* which interrupt line(s) */
50 intr_func_t pi_func; /* handler function (when connected) */
51 intr_arg_t pi_arg; /* handler parameter (when connected) */
52 cpuid_t pi_mustruncpu; /* Where we must run. */
53 int pi_irq; /* IRQ assigned */
54 int pi_cpu; /* cpu assigned */
57 /* PCIIO_INTR (pi_flags) flags */
58 #define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */
59 #define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */
62 * Generic PCI bus information
64 struct pciio_businfo_s {
65 int bi_multi_master;/* Bus provider supports multiple */
66 /* dma masters behind a single slot. */
67 /* Needed to work around a thrashing */
68 /* issue in SGI Bridge ASIC and */
69 /* its derivatives. */
70 pciio_asic_type_t bi_asic_type; /* PCI ASIC type */
71 pciio_bus_type_t bi_bus_type; /* PCI bus type */
72 pciio_bus_speed_t bi_bus_speed; /* PCI bus speed */
76 * Some PCI provider implementations keep track of PCI window Base Address
77 * Register (BAR) address range assignment via the rmalloc()/rmfree() arena
78 * management routines. These implementations use the following data
79 * structure for each allocation address space (e.g. memory, I/O, small
82 * The ``page size'' encodes the minimum allocation unit and must be a power
83 * of 2. The main use of this allocation ``page size'' is to control the
84 * number of free address ranges that the mapping allocation software will
85 * need to track. Smaller values will allow more efficient use of the address
86 * ranges but will result in much larger allocation map structures ... For
87 * instance, if we want to manage allocations for a 256MB address range,
88 * choosing a 1MB allocation page size will result in up to 1MB being wasted
89 * for allocation requests smaller than 1MB. The worst case allocation
90 * pattern for the allocation software to track would be a pattern of 1MB
91 * allocated, 1MB free. This results in the need to track up to 128 free
94 struct pciio_win_map_s {
95 struct map *wm_map; /* window address map */
96 int wm_page_size; /* allocation ``page size'' */
100 * Opaque structure used to keep track of window allocation information.
102 struct pciio_win_alloc_s {
103 struct resource *wa_resource; /* window map allocation resource */
104 unsigned long wa_base; /* allocation starting page number */
105 size_t wa_pages; /* number of pages in allocation */
109 * Each PCI Card has one of these.
112 struct pciio_info_s {
114 vertex_hdl_t c_vertex; /* back pointer to vertex */
115 vertex_hdl_t c_hostvertex;/* top most device in tree */
116 pciio_bus_t c_bus; /* which bus the card is in */
117 pciio_slot_t c_slot; /* which slot the card is in */
118 pciio_function_t c_func; /* which func (on multi-func cards) */
119 pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */
120 pciio_device_id_t c_device; /* PCI card "device" code */
121 vertex_hdl_t c_master; /* PCI bus provider */
122 arbitrary_info_t c_mfast; /* cached fastinfo from c_master */
123 pciio_provider_t *c_pops; /* cached provider from c_master */
124 error_handler_f *c_efunc; /* error handling function */
125 error_handler_arg_t c_einfo; /* first parameter for efunc */
127 struct pciio_win_info_s { /* state of BASE regs */
128 pciio_space_t w_space;
129 char w_code; /* low 4 bits of MEM BAR */
130 /* low 2 bits of IO BAR */
133 int w_devio_index; /* DevIO[] register used to
134 access this window */
135 struct pciio_win_alloc_s w_win_alloc; /* window allocation cookie */
136 } c_window[PCI_CFG_BASE_ADDRS + 1];
137 #define c_rwindow c_window[PCI_CFG_BASE_ADDRS] /* EXPANSION ROM window */
138 #define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */
139 #define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */
140 pciio_piospace_t c_piospace; /* additional I/O spaces allocated */
141 int c_type1; /* use type1 addressing */
144 extern char pciio_info_fingerprint[];
145 #endif /* _ASM_IA64_SN_PCI_PCIIO_PRIVATE_H */