include/asm-ia64/sn/shub_mmr.h

   1 /*
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
   8  */
   9
  10 #ifndef _ASM_IA64_SN_SHUB_MMR_H
  11 #define _ASM_IA64_SN_SHUB_MMR_H
  12
  13 /* ==================================================================== */
  14 /*                        Register "SH_IPI_INT"                         */
  15 /*               SHub Inter-Processor Interrupt Registers               */
  16 /* ==================================================================== */
  17 #define SH1_IPI_INT                               0x0000000110000380
  18 #define SH2_IPI_INT                               0x0000000010000380
  19
  20 /*   SH_IPI_INT_TYPE                                                    */
  21 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  22 #define SH_IPI_INT_TYPE_SHFT                     0
  23 #define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
  24
  25 /*   SH_IPI_INT_AGT                                                     */
  26 /*   Description:  Agent, must be 0 for SHub                            */
  27 #define SH_IPI_INT_AGT_SHFT                      3
  28 #define SH_IPI_INT_AGT_MASK                      0x0000000000000008
  29
  30 /*   SH_IPI_INT_PID                                                     */
  31 /*   Description:  Processor ID, same setting as on targeted McKinley  */
  32 #define SH_IPI_INT_PID_SHFT                      4
  33 #define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
  34
  35 /*   SH_IPI_INT_BASE                                                    */
  36 /*   Description:  Optional interrupt vector area, 2MB aligned          */
  37 #define SH_IPI_INT_BASE_SHFT                     21
  38 #define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
  39
  40 /*   SH_IPI_INT_IDX                                                     */
  41 /*   Description:  Targeted McKinley interrupt vector                   */
  42 #define SH_IPI_INT_IDX_SHFT                      52
  43 #define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
  44
  45 /*   SH_IPI_INT_SEND                                                    */
  46 /*   Description:  Send Interrupt Message to PI, This generates a puls  */
  47 #define SH_IPI_INT_SEND_SHFT                     63
  48 #define SH_IPI_INT_SEND_MASK                     0x8000000000000000
  49
  50 /* ==================================================================== */
  51 /*                     Register "SH_EVENT_OCCURRED"                     */
  52 /*                    SHub Interrupt Event Occurred                     */
  53 /* ==================================================================== */
  54 #define SH1_EVENT_OCCURRED                        0x0000000110010000
  55 #define SH1_EVENT_OCCURRED_ALIAS                  0x0000000110010008
  56 #define SH2_EVENT_OCCURRED                        0x0000000010010000
  57 #define SH2_EVENT_OCCURRED_ALIAS                  0x0000000010010008
  58
  59 /* ==================================================================== */
  60 /*                     Register "SH_PI_CAM_CONTROL"                     */
  61 /*                      CRB CAM MMR Access Control                      */
  62 /* ==================================================================== */
  63 #define SH1_PI_CAM_CONTROL                        0x0000000120050300
  64
  65 /* ==================================================================== */
  66 /*                        Register "SH_SHUB_ID"                         */
  67 /*                            SHub ID Number                            */
  68 /* ==================================================================== */
  69 #define SH1_SHUB_ID                               0x0000000110060580
  70 #define SH1_SHUB_ID_REVISION_SHFT                 28
  71 #define SH1_SHUB_ID_REVISION_MASK                 0x00000000f0000000
  72
  73 /* ==================================================================== */
  74 /*                          Register "SH_RTC"                           */
  75 /*                           Real-time Clock                            */
  76 /* ==================================================================== */
  77 #define SH1_RTC                                   0x00000001101c0000
  78 #define SH2_RTC                                   0x00000002101c0000
  79 #define SH_RTC_MASK                               0x007fffffffffffff
  80
  81 /* ==================================================================== */
  82 /*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
  83 /*                      PIO Write Status for CPU 0 & 1                  */
  84 /* ==================================================================== */
  85 #define SH1_PIO_WRITE_STATUS_0                    0x0000000120070200
  86 #define SH1_PIO_WRITE_STATUS_1                    0x0000000120070280
  87 #define SH2_PIO_WRITE_STATUS_0                    0x0000000020070200
  88 #define SH2_PIO_WRITE_STATUS_1                    0x0000000020070280
  89 #define SH2_PIO_WRITE_STATUS_2                    0x0000000020070300
  90 #define SH2_PIO_WRITE_STATUS_3                    0x0000000020070380
  91
  92 /*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
  93 /*   Description:  Deadlock response detected                           */
  94 #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
  95 #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002
  96
  97 /*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
  98 /*   Description:  Count of currently pending PIO writes                */
  99 #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
 100 #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
 101
 102 /* ==================================================================== */
 103 /*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
 104 /* ==================================================================== */
 105 #define SH1_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
 106 #define SH2_PIO_WRITE_STATUS_0_ALIAS              0x0000000020070208
 107
 108 /* ==================================================================== */
 109 /*                     Register "SH_EVENT_OCCURRED"                     */
 110 /*                    SHub Interrupt Event Occurred                     */
 111 /* ==================================================================== */
 112 /*   SH_EVENT_OCCURRED_UART_INT                                         */
 113 /*   Description:  Pending Junk Bus UART Interrupt                      */
 114 #define SH_EVENT_OCCURRED_UART_INT_SHFT          20
 115 #define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
 116
 117 /*   SH_EVENT_OCCURRED_IPI_INT                                          */
 118 /*   Description:  Pending IPI Interrupt                                */
 119 #define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
 120 #define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
 121
 122 /*   SH_EVENT_OCCURRED_II_INT0                                          */
 123 /*   Description:  Pending II 0 Interrupt                               */
 124 #define SH_EVENT_OCCURRED_II_INT0_SHFT           29
 125 #define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
 126
 127 /*   SH_EVENT_OCCURRED_II_INT1                                          */
 128 /*   Description:  Pending II 1 Interrupt                               */
 129 #define SH_EVENT_OCCURRED_II_INT1_SHFT           30
 130 #define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
 131
 132 /* ==================================================================== */
 133 /*                         LEDS                                         */
 134 /* ==================================================================== */
 135 #define SH1_REAL_JUNK_BUS_LED0                   0x7fed00000UL
 136 #define SH1_REAL_JUNK_BUS_LED1                   0x7fed10000UL
 137 #define SH1_REAL_JUNK_BUS_LED2                   0x7fed20000UL
 138 #define SH1_REAL_JUNK_BUS_LED3                   0x7fed30000UL
 139
 140 #define SH2_REAL_JUNK_BUS_LED0                   0xf0000000UL
 141 #define SH2_REAL_JUNK_BUS_LED1                   0xf0010000UL
 142 #define SH2_REAL_JUNK_BUS_LED2                   0xf0020000UL
 143 #define SH2_REAL_JUNK_BUS_LED3                   0xf0030000UL
 144
 145 /* ==================================================================== */
 146 /*                         Register "SH1_PTC_0"                         */
 147 /*       Puge Translation Cache Message Configuration Information       */
 148 /* ==================================================================== */
 149 #define SH1_PTC_0                                 0x00000001101a0000
 150
 151 /*   SH1_PTC_0_A                                                        */
 152 /*   Description:  Type                                                 */
 153 #define SH1_PTC_0_A_SHFT                          0
 154
 155 /*   SH1_PTC_0_PS                                                       */
 156 /*   Description:  Page Size                                            */
 157 #define SH1_PTC_0_PS_SHFT                         2
 158
 159 /*   SH1_PTC_0_RID                                                      */
 160 /*   Description:  Region ID                                            */
 161 #define SH1_PTC_0_RID_SHFT                        8
 162
 163 /*   SH1_PTC_0_START                                                    */
 164 /*   Description:  Start                                                */
 165 #define SH1_PTC_0_START_SHFT                      63
 166
 167 /* ==================================================================== */
 168 /*                         Register "SH1_PTC_1"                         */
 169 /*       Puge Translation Cache Message Configuration Information       */
 170 /* ==================================================================== */
 171 #define SH1_PTC_1                                 0x00000001101a0080
 172
 173 /*   SH1_PTC_1_START                                                    */
 174 /*   Description:  PTC_1 Start                                          */
 175 #define SH1_PTC_1_START_SHFT                      63
 176
 177
 178 /* ==================================================================== */
 179 /*                         Register "SH2_PTC"                           */
 180 /*       Puge Translation Cache Message Configuration Information       */
 181 /* ==================================================================== */
 182 #define SH2_PTC                                   0x0000000170000000
 183
 184 /*   SH2_PTC_A                                                          */
 185 /*   Description:  Type                                                 */
 186 #define SH2_PTC_A_SHFT                            0
 187
 188 /*   SH2_PTC_PS                                                         */
 189 /*   Description:  Page Size                                            */
 190 #define SH2_PTC_PS_SHFT                           2
 191
 192 /*   SH2_PTC_RID                                                      */
 193 /*   Description:  Region ID                                            */
 194 #define SH2_PTC_RID_SHFT                          4
 195
 196 /*   SH2_PTC_START                                                      */
 197 /*   Description:  Start                                                */
 198 #define SH2_PTC_START_SHFT                        63
 199
 200 /*   SH2_PTC_ADDR_RID                                                   */
 201 /*   Description:  Region ID                                            */
 202 #define SH2_PTC_ADDR_SHFT                         4
 203 #define SH2_PTC_ADDR_MASK                         0x1ffffffffffff000
 204
 205 /* ==================================================================== */
 206 /*                    Register "SH_RTC1_INT_CONFIG"                     */
 207 /*                SHub RTC 1 Interrupt Config Registers                 */
 208 /* ==================================================================== */
 209
 210 #define SH1_RTC1_INT_CONFIG                      0x0000000110001480
 211 #define SH2_RTC1_INT_CONFIG                      0x0000000010001480
 212 #define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 213 #define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
 214
 215 /*   SH_RTC1_INT_CONFIG_TYPE                                            */
 216 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 217 #define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
 218 #define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
 219
 220 /*   SH_RTC1_INT_CONFIG_AGT                                             */
 221 /*   Description:  Agent, must be 0 for SHub                            */
 222 #define SH_RTC1_INT_CONFIG_AGT_SHFT              3
 223 #define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
 224
 225 /*   SH_RTC1_INT_CONFIG_PID                                             */
 226 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 227 #define SH_RTC1_INT_CONFIG_PID_SHFT              4
 228 #define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
 229
 230 /*   SH_RTC1_INT_CONFIG_BASE                                            */
 231 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 232 #define SH_RTC1_INT_CONFIG_BASE_SHFT             21
 233 #define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 234
 235 /*   SH_RTC1_INT_CONFIG_IDX                                             */
 236 /*   Description:  Targeted McKinley interrupt vector                   */
 237 #define SH_RTC1_INT_CONFIG_IDX_SHFT              52
 238 #define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 239
 240 /* ==================================================================== */
 241 /*                    Register "SH_RTC1_INT_ENABLE"                     */
 242 /*                SHub RTC 1 Interrupt Enable Registers                 */
 243 /* ==================================================================== */
 244
 245 #define SH1_RTC1_INT_ENABLE                      0x0000000110001500
 246 #define SH2_RTC1_INT_ENABLE                      0x0000000010001500
 247 #define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
 248 #define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
 249
 250 /*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
 251 /*   Description:  Enable RTC 1 Interrupt                               */
 252 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
 253 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
 254
 255 /* ==================================================================== */
 256 /*                    Register "SH_RTC2_INT_CONFIG"                     */
 257 /*                SHub RTC 2 Interrupt Config Registers                 */
 258 /* ==================================================================== */
 259
 260 #define SH1_RTC2_INT_CONFIG                      0x0000000110001580
 261 #define SH2_RTC2_INT_CONFIG                      0x0000000010001580
 262 #define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 263 #define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
 264
 265 /*   SH_RTC2_INT_CONFIG_TYPE                                            */
 266 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 267 #define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
 268 #define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
 269
 270 /*   SH_RTC2_INT_CONFIG_AGT                                             */
 271 /*   Description:  Agent, must be 0 for SHub                            */
 272 #define SH_RTC2_INT_CONFIG_AGT_SHFT              3
 273 #define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
 274
 275 /*   SH_RTC2_INT_CONFIG_PID                                             */
 276 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 277 #define SH_RTC2_INT_CONFIG_PID_SHFT              4
 278 #define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
 279
 280 /*   SH_RTC2_INT_CONFIG_BASE                                            */
 281 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 282 #define SH_RTC2_INT_CONFIG_BASE_SHFT             21
 283 #define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 284
 285 /*   SH_RTC2_INT_CONFIG_IDX                                             */
 286 /*   Description:  Targeted McKinley interrupt vector                   */
 287 #define SH_RTC2_INT_CONFIG_IDX_SHFT              52
 288 #define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 289
 290 /* ==================================================================== */
 291 /*                    Register "SH_RTC2_INT_ENABLE"                     */
 292 /*                SHub RTC 2 Interrupt Enable Registers                 */
 293 /* ==================================================================== */
 294
 295 #define SH1_RTC2_INT_ENABLE                      0x0000000110001600
 296 #define SH2_RTC2_INT_ENABLE                      0x0000000010001600
 297 #define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
 298 #define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
 299
 300 /*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
 301 /*   Description:  Enable RTC 2 Interrupt                               */
 302 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
 303 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
 304
 305 /* ==================================================================== */
 306 /*                    Register "SH_RTC3_INT_CONFIG"                     */
 307 /*                SHub RTC 3 Interrupt Config Registers                 */
 308 /* ==================================================================== */
 309
 310 #define SH1_RTC3_INT_CONFIG                      0x0000000110001680
 311 #define SH2_RTC3_INT_CONFIG                      0x0000000010001680
 312 #define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 313 #define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
 314
 315 /*   SH_RTC3_INT_CONFIG_TYPE                                            */
 316 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 317 #define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
 318 #define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
 319
 320 /*   SH_RTC3_INT_CONFIG_AGT                                             */
 321 /*   Description:  Agent, must be 0 for SHub                            */
 322 #define SH_RTC3_INT_CONFIG_AGT_SHFT              3
 323 #define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
 324
 325 /*   SH_RTC3_INT_CONFIG_PID                                             */
 326 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 327 #define SH_RTC3_INT_CONFIG_PID_SHFT              4
 328 #define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
 329
 330 /*   SH_RTC3_INT_CONFIG_BASE                                            */
 331 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 332 #define SH_RTC3_INT_CONFIG_BASE_SHFT             21
 333 #define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 334
 335 /*   SH_RTC3_INT_CONFIG_IDX                                             */
 336 /*   Description:  Targeted McKinley interrupt vector                   */
 337 #define SH_RTC3_INT_CONFIG_IDX_SHFT              52
 338 #define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 339
 340 /* ==================================================================== */
 341 /*                    Register "SH_RTC3_INT_ENABLE"                     */
 342 /*                SHub RTC 3 Interrupt Enable Registers                 */
 343 /* ==================================================================== */
 344
 345 #define SH1_RTC3_INT_ENABLE                      0x0000000110001700
 346 #define SH2_RTC3_INT_ENABLE                      0x0000000010001700
 347 #define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
 348 #define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
 349
 350 /*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
 351 /*   Description:  Enable RTC 3 Interrupt                               */
 352 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
 353 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
 354
 355 /*   SH_EVENT_OCCURRED_RTC1_INT                                         */
 356 /*   Description:  Pending RTC 1 Interrupt                              */
 357 #define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
 358 #define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
 359
 360 /*   SH_EVENT_OCCURRED_RTC2_INT                                         */
 361 /*   Description:  Pending RTC 2 Interrupt                              */
 362 #define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
 363 #define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
 364
 365 /*   SH_EVENT_OCCURRED_RTC3_INT                                         */
 366 /*   Description:  Pending RTC 3 Interrupt                              */
 367 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
 368 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 369
 370 /* ==================================================================== */
 371 /*                        Register "SH_INT_CMPB"                        */
 372 /*                  RTC Compare Value for Processor B                   */
 373 /* ==================================================================== */
 374
 375 #define SH1_INT_CMPB                             0x00000001101b0080
 376 #define SH2_INT_CMPB                             0x00000000101b0080
 377 #define SH_INT_CMPB_MASK                         0x007fffffffffffff
 378 #define SH_INT_CMPB_INIT                         0x0000000000000000
 379
 380 /*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
 381 /*   Description:  Real Time Clock Compare                              */
 382 #define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
 383 #define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
 384
 385 /* ==================================================================== */
 386 /*                        Register "SH_INT_CMPC"                        */
 387 /*                  RTC Compare Value for Processor C                   */
 388 /* ==================================================================== */
 389
 390 #define SH1_INT_CMPC                             0x00000001101b0100
 391 #define SH2_INT_CMPC                             0x00000000101b0100
 392 #define SH_INT_CMPC_MASK                         0x007fffffffffffff
 393 #define SH_INT_CMPC_INIT                         0x0000000000000000
 394
 395 /*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
 396 /*   Description:  Real Time Clock Compare                              */
 397 #define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
 398 #define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
 399
 400 /* ==================================================================== */
 401 /*                        Register "SH_INT_CMPD"                        */
 402 /*                  RTC Compare Value for Processor D                   */
 403 /* ==================================================================== */
 404
 405 #define SH1_INT_CMPD                             0x00000001101b0180
 406 #define SH2_INT_CMPD                             0x00000000101b0180
 407 #define SH_INT_CMPD_MASK                         0x007fffffffffffff
 408 #define SH_INT_CMPD_INIT                         0x0000000000000000
 409
 410 /*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
 411 /*   Description:  Real Time Clock Compare                              */
 412 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 413 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 414
 415
 416 /* ==================================================================== */
 417 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */
 418 /* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
 419 /* It is acceptible to use (for example) SH_IPI_INT to reference the    */
 420 /* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
 421 /* on the type of the SHUB. Do not use these #defines in performance    */
 422 /* critical code  or loops - there is a small performance penalty.      */
 423 /* ==================================================================== */
 424 #define shubmmr(a,b)            (is_shub2() ? a##2_##b : a##1_##b)
 425
 426 #define SH_REAL_JUNK_BUS_LED0   shubmmr(SH, REAL_JUNK_BUS_LED0)
 427 #define SH_IPI_INT              shubmmr(SH, IPI_INT)
 428 #define SH_EVENT_OCCURRED       shubmmr(SH, EVENT_OCCURRED)
 429 #define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
 430 #define SH_RTC                  shubmmr(SH, RTC)
 431 #define SH_RTC1_INT_CONFIG      shubmmr(SH, RTC1_INT_CONFIG)
 432 #define SH_RTC1_INT_ENABLE      shubmmr(SH, RTC1_INT_ENABLE)
 433 #define SH_RTC2_INT_CONFIG      shubmmr(SH, RTC2_INT_CONFIG)
 434 #define SH_RTC2_INT_ENABLE      shubmmr(SH, RTC2_INT_ENABLE)
 435 #define SH_RTC3_INT_CONFIG      shubmmr(SH, RTC3_INT_CONFIG)
 436 #define SH_RTC3_INT_ENABLE      shubmmr(SH, RTC3_INT_ENABLE)
 437 #define SH_INT_CMPB             shubmmr(SH, INT_CMPB)
 438 #define SH_INT_CMPC             shubmmr(SH, INT_CMPC)
 439 #define SH_INT_CMPD             shubmmr(SH, INT_CMPD)
 440
 441 #endif /* _ASM_IA64_SN_SHUB_MMR_H */