include/asm-mips/hazards.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 2004 Ralf Baechle
   7  */
   8 #ifndef _ASM_HAZARDS_H
   9 #define _ASM_HAZARDS_H
  10
  11 #include <linux/config.h>
  12
  13 #ifdef __ASSEMBLY__
  14
  15 /*
  16  * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
  17  * use of the JTLB for instructions should not occur for 4 cpu cycles and use
  18  * for data translations should not occur for 3 cpu cycles.
  19  */
  20 #ifdef CONFIG_CPU_RM9000
  21 #define mtc0_tlbw_hazard                                                \
  22         .set    push;                                                   \
  23         .set    mips32;                                                 \
  24         ssnop; ssnop; ssnop; ssnop;                                     \
  25         .set    pop
  26
  27 #define tlbw_eret_hazard                                                \
  28         .set    push;                                                   \
  29         .set    mips32;                                                 \
  30         ssnop; ssnop; ssnop; ssnop;                                     \
  31         .set    pop
  32
  33 #else
  34
  35 /*
  36  * The taken branch will result in a two cycle penalty for the two killed
  37  * instructions on R4000 / R4400.  Other processors only have a single cycle
  38  * hazard so this is nice trick to have an optimal code for a range of
  39  * processors.
  40  */
  41 #define mtc0_tlbw_hazard                                                \
  42         b       . + 8
  43 #define tlbw_eret_hazard
  44 #endif
  45
  46 #else /* __ASSEMBLY__ */
  47
  48 /*
  49  * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
  50  * use of the JTLB for instructions should not occur for 4 cpu cycles and use
  51  * for data translations should not occur for 3 cpu cycles.
  52  */
  53 #ifdef CONFIG_CPU_RM9000
  54
  55 #define mtc0_tlbw_hazard()                                              \
  56         __asm__ __volatile__(                                           \
  57                 ".set\tmips32\n\t"                                      \
  58                 "ssnop; ssnop; ssnop; ssnop\n\t"                        \
  59                 ".set\tmips0")
  60
  61 #define tlbw_use_hazard()                                               \
  62         __asm__ __volatile__(                                           \
  63                 ".set\tmips32\n\t"                                      \
  64                 "ssnop; ssnop; ssnop; ssnop\n\t"                        \
  65                 ".set\tmips0")
  66 #else
  67
  68 /*
  69  * Overkill warning ...
  70  */
  71 #define mtc0_tlbw_hazard()                                              \
  72         __asm__ __volatile__(                                           \
  73                 ".set noreorder\n\t"                                    \
  74                 "nop; nop; nop; nop; nop; nop;\n\t"                     \
  75                 ".set reorder\n\t")
  76
  77 #define tlbw_use_hazard()                                               \
  78         __asm__ __volatile__(                                           \
  79                 ".set noreorder\n\t"                                    \
  80                 "nop; nop; nop; nop; nop; nop;\n\t"                     \
  81                 ".set reorder\n\t")
  82
  83 #endif
  84
  85 #endif /* __ASSEMBLY__ */
  86
  87 #endif /* _ASM_HAZARDS_H */