include/asm-mips/hazards.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 2004 Ralf Baechle
   7  */
   8 #ifndef _ASM_HAZARDS_H
   9 #define _ASM_HAZARDS_H
  10
  11 #include <linux/config.h>
  12
  13 #ifdef __ASSEMBLY__
  14
  15         .macro  _ssnop
  16         sll     $0, $2, 1
  17         .endm
  18
  19 /*
  20  * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
  21  * use of the JTLB for instructions should not occur for 4 cpu cycles and use
  22  * for data translations should not occur for 3 cpu cycles.
  23  */
  24 #ifdef CONFIG_CPU_RM9000
  25
  26 #define mtc0_tlbw_hazard                                                \
  27         .set    push;                                                   \
  28         .set    mips32;                                                 \
  29         _ssnop; _ssnop; _ssnop; _ssnop;                                 \
  30         .set    pop
  31
  32 #define tlbw_eret_hazard                                                \
  33         .set    push;                                                   \
  34         .set    mips32;                                                 \
  35         _ssnop; _ssnop; _ssnop; _ssnop;                                 \
  36         .set    pop
  37
  38 #else
  39
  40 /*
  41  * The taken branch will result in a two cycle penalty for the two killed
  42  * instructions on R4000 / R4400.  Other processors only have a single cycle
  43  * hazard so this is nice trick to have an optimal code for a range of
  44  * processors.
  45  */
  46 #define mtc0_tlbw_hazard                                                \
  47         b       . + 8
  48 #define tlbw_eret_hazard
  49 #endif
  50
  51 /*
  52  * mtc0->mfc0 hazard
  53  * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
  54  * It is a MIPS32R2 processor so ehb will clear the hazard.
  55  */
  56
  57 #ifdef CONFIG_CPU_MIPSR2
  58 /*
  59  * Use a macro for ehb unless explicit support for MIPSR2 is enabled
  60  */
  61         .macro  ehb
  62         sll     $0, $0, 3
  63         .endm
  64
  65 #define irq_enable_hazard                                               \
  66         ehb             # irq_enable_hazard
  67
  68 #define irq_disable_hazard                                              \
  69         ehb             # irq_disable_hazard
  70
  71 #else
  72
  73 #define irq_enable_hazard
  74 #define irq_disable_hazard
  75
  76 #endif
  77
  78 #else /* __ASSEMBLY__ */
  79
  80 /*
  81  * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
  82  * use of the JTLB for instructions should not occur for 4 cpu cycles and use
  83  * for data translations should not occur for 3 cpu cycles.
  84  */
  85 #ifdef CONFIG_CPU_RM9000
  86
  87 #define mtc0_tlbw_hazard()                                              \
  88         __asm__ __volatile__(                                           \
  89                 ".set\tmips32\n\t"                                      \
  90                 "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
  91                 ".set\tmips0")
  92
  93 #define tlbw_use_hazard()                                               \
  94         __asm__ __volatile__(                                           \
  95                 ".set\tmips32\n\t"                                      \
  96                 "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
  97                 ".set\tmips0")
  98 #else
  99
 100 /*
 101  * Overkill warning ...
 102  */
 103 #define mtc0_tlbw_hazard()                                              \
 104         __asm__ __volatile__(                                           \
 105                 ".set noreorder\n\t"                                    \
 106                 "nop; nop; nop; nop; nop; nop;\n\t"                     \
 107                 ".set reorder\n\t")
 108
 109 #define tlbw_use_hazard()                                               \
 110         __asm__ __volatile__(                                           \
 111                 ".set noreorder\n\t"                                    \
 112                 "nop; nop; nop; nop; nop; nop;\n\t"                     \
 113                 ".set reorder\n\t")
 114
 115 #endif
 116
 117 /*
 118  * mtc0->mfc0 hazard
 119  * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
 120  * It is a MIPS32R2 processor so ehb will clear the hazard.
 121  */
 122
 123 #ifdef CONFIG_CPU_MIPSR2
 124 /*
 125  * Use a macro for ehb unless explicit support for MIPSR2 is enabled
 126  */
 127 __asm__(
 128         "       .macro  ehb                                     \n\t"
 129         "       sll     $0, $0, 3                               \n\t"
 130         "       .endm                                           \n\t"
 131         "                                                       \n\t"
 132         "       .macro\tirq_enable_hazard                       \n\t"
 133         "       ehb                                             \n\t"
 134         "       .endm                                           \n\t"
 135         "                                                       \n\t"
 136         "       .macro\tirq_disable_hazard                      \n\t"
 137         "       ehb                                             \n\t"
 138         "       .endm");
 139
 140 #define irq_enable_hazard()                                             \
 141         __asm__ __volatile__(                                           \
 142         "ehb\t\t\t\t# irq_enable_hazard")
 143
 144 #define irq_disable_hazard()                                            \
 145         __asm__ __volatile__(                                           \
 146         "ehb\t\t\t\t# irq_disable_hazard")
 147
 148 #elif defined(CONFIG_CPU_R10000)
 149
 150 /*
 151  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
 152  */
 153
 154 __asm__(
 155         "       .macro\tirq_enable_hazard                       \n\t"
 156         "       .endm                                           \n\t"
 157         "                                                       \n\t"
 158         "       .macro\tirq_disable_hazard                      \n\t"
 159         "       .endm");
 160
 161 #define irq_enable_hazard()     do { } while (0)
 162 #define irq_disable_hazard()    do { } while (0)
 163
 164 #else
 165
 166 /*
 167  * Default for classic MIPS processors.  Assume worst case hazards but don't
 168  * care about the irq_enable_hazard - sooner or later the hardware will
 169  * enable it and we don't care when exactly.
 170  */
 171
 172 __asm__(
 173         "       .macro  _ssnop                                  \n\t"
 174         "       sll     $0, $2, 1                               \n\t"
 175         "       .endm                                           \n\t"
 176         "                                                       \n\t"
 177         "       #                                               \n\t"
 178         "       # There is a hazard but we do not care          \n\t"
 179         "       #                                               \n\t"
 180         "       .macro\tirq_enable_hazard                       \n\t"
 181         "       .endm                                           \n\t"
 182         "                                                       \n\t"
 183         "       .macro\tirq_disable_hazard                      \n\t"
 184         "       _ssnop; _ssnop; _ssnop                          \n\t"
 185         "       .endm");
 186
 187 #define irq_enable_hazard()     do { } while (0)
 188 #define irq_disable_hazard()                                            \
 189         __asm__ __volatile__(                                           \
 190         "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
 191
 192 #endif
 193
 194 #endif /* __ASSEMBLY__ */
 195
 196 #endif /* _ASM_HAZARDS_H */