2 * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2004 Ladislav Michl
12 #ifndef __ASM_MACE_H__
13 #define __ASM_MACE_H__
15 #include <linux/config.h>
21 #define MACE_BASE 0x1f000000 /* physical */
24 #define BIT(x) (1ULL << (x))
28 volatile unsigned long long reg;
33 volatile unsigned long reg;
38 volatile unsigned long reg;
42 volatile unsigned long reg;
46 #define mace_read(r) \
47 (sizeof(r.reg) == 4 ? readl(&r.reg) : readq(&r.reg))
48 #define mace_write(v,r) \
49 (sizeof(r.reg) == 4 ? writel(v,&r.reg) : writeq(v,&r.reg))
55 volatile unsigned int error_addr;
56 volatile unsigned int error;
57 #define MACEPCI_ERROR_MASTER_ABORT BIT(31)
58 #define MACEPCI_ERROR_TARGET_ABORT BIT(30)
59 #define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
60 #define MACEPCI_ERROR_RETRY_ERR BIT(28)
61 #define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
62 #define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
63 #define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
64 #define MACEPCI_ERROR_PARITY_ERR BIT(24)
65 #define MACEPCI_ERROR_OVERRUN BIT(23)
66 #define MACEPCI_ERROR_RSVD BIT(22)
67 #define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
68 #define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
69 #define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
70 #define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
71 #define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
72 #define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
73 #define MACEPCI_ERROR_SIG_TABORT BIT(4)
74 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
75 #define MACEPCI_ERROR_DEVSEL_FAST 0
76 #define MACEPCI_ERROR_DEVSEL_MED 0x40
77 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
78 #define MACEPCI_ERROR_FBB BIT(1)
79 #define MACEPCI_ERROR_66MHZ BIT(0)
80 volatile unsigned int control;
81 #define MACEPCI_CONTROL_INT(x) BIT(x)
82 #define MACEPCI_CONTROL_INT_MASK 0xff
83 #define MACEPCI_CONTROL_SERR_ENA BIT(8)
84 #define MACEPCI_CONTROL_ARB_N6 BIT(9)
85 #define MACEPCI_CONTROL_PARITY_ERR BIT(10)
86 #define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
87 #define MACEPCI_CONTROL_ARB_N3 BIT(12)
88 #define MACEPCI_CONTROL_ARB_N4 BIT(13)
89 #define MACEPCI_CONTROL_ARB_N5 BIT(14)
90 #define MACEPCI_CONTROL_PARK_LIU BIT(15)
91 #define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
92 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
93 #define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
94 #define MACEPCI_CONTROL_PARITY_INT BIT(25)
95 #define MACEPCI_CONTROL_SERR_INT BIT(26)
96 #define MACEPCI_CONTROL_IT_INT BIT(27)
97 #define MACEPCI_CONTROL_RE_INT BIT(28)
98 #define MACEPCI_CONTROL_DPED_INT BIT(29)
99 #define MACEPCI_CONTROL_TAR_INT BIT(30)
100 #define MACEPCI_CONTROL_MAR_INT BIT(31)
101 volatile unsigned int rev;
102 unsigned int _pad[0xcf8/4 - 4];
103 volatile unsigned int config_addr;
105 volatile unsigned char b[4];
106 volatile unsigned short w[2];
107 volatile unsigned int l;
110 #define MACEPCI_LOW_MEMORY 0x1a000000
111 #define MACEPCI_LOW_IO 0x18000000
112 #define MACEPCI_SWAPPED_VIEW 0
113 #define MACEPCI_NATIVE_VIEW 0x40000000
114 #define MACEPCI_IO 0x80000000
115 #define MACEPCI_HI_MEMORY 0x280000000
116 #define MACEPCI_HI_IO 0x100000000
122 mace32_t xxx; /* later... */
128 struct mace_ethernet {
138 mace32_t rx_buff_al1;
139 mace32_t rx_buff_al2;
143 mace32_t phy_trans_go;
144 mace32_t backoff_seed;
145 /*===================================*/
146 mace64_t imq_reserved[4];
149 mace64_t mcast_filter;
150 mace32_t tx_ring_base;
151 /* Following are read-only registers for debugging */
152 mace64_t tx_pkt1_hdr;
153 mace64_t tx_pkt1_ptr[3];
154 mace64_t tx_pkt2_hdr;
155 mace64_t tx_pkt2_ptr[3];
156 /*===================================*/
159 #define mace_eth_read(r) \
160 mace_read(mace->eth.r)
161 #define mace_eth_write(v,r) \
162 mace_write(v,mace->eth.r)
169 /* Audio registers */
172 mace32_t codec_control; /* codec status control */
173 mace32_t codec_mask; /* codec status input mask */
174 mace32_t codec_read; /* codec status read data */
176 mace32_t control; /* channel control */
177 mace32_t read_ptr; /* channel read pointer */
178 mace32_t write_ptr; /* channel write pointer */
179 mace32_t depth; /* channel depth */
182 #define mace_perif_audio_read(r) \
183 mace_read(mace->perif.audio.r)
184 #define mace_perif_audio_write(v,r) \
185 mace_write(v,mace->perif.audio.r)
187 /* ISA Control and DMA registers */
188 struct mace_isactrl {
190 #define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
193 #define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
194 #define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
195 #define MACEISA_NIC_DEASSERT BIT(2)
196 #define MACEISA_NIC_DATA BIT(3)
197 #define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */
198 #define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */
199 #define MACEISA_DP_RAM_ENABLE BIT(6)
203 #define MACEISA_AUDIO_SW_INT BIT(0)
204 #define MACEISA_AUDIO_SC_INT BIT(1)
205 #define MACEISA_AUDIO1_DMAT_INT BIT(2)
206 #define MACEISA_AUDIO1_OF_INT BIT(3)
207 #define MACEISA_AUDIO2_DMAT_INT BIT(4)
208 #define MACEISA_AUDIO2_MERR_INT BIT(5)
209 #define MACEISA_AUDIO3_DMAT_INT BIT(6)
210 #define MACEISA_AUDIO3_MERR_INT BIT(7)
211 #define MACEISA_RTC_INT BIT(8)
212 #define MACEISA_KEYB_INT BIT(9)
213 #define MACEISA_KEYB_POLL_INT BIT(10)
214 #define MACEISA_MOUSE_INT BIT(11)
215 #define MACEISA_MOUSE_POLL_INT BIT(12)
216 #define MACEISA_TIMER0_INT BIT(13)
217 #define MACEISA_TIMER1_INT BIT(14)
218 #define MACEISA_TIMER2_INT BIT(15)
219 #define MACEISA_PARALLEL_INT BIT(16)
220 #define MACEISA_PAR_CTXA_INT BIT(17)
221 #define MACEISA_PAR_CTXB_INT BIT(18)
222 #define MACEISA_PAR_MERR_INT BIT(19)
223 #define MACEISA_SERIAL1_INT BIT(20)
224 #define MACEISA_SERIAL1_TDMAT_INT BIT(21)
225 #define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
226 #define MACEISA_SERIAL1_TDMAME_INT BIT(23)
227 #define MACEISA_SERIAL1_RDMAT_INT BIT(24)
228 #define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
229 #define MACEISA_SERIAL2_INT BIT(26)
230 #define MACEISA_SERIAL2_TDMAT_INT BIT(27)
231 #define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
232 #define MACEISA_SERIAL2_TDMAME_INT BIT(29)
233 #define MACEISA_SERIAL2_RDMAT_INT BIT(30)
234 #define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
236 mace64_t _pad[0x2000/8 - 4];
238 mace64_t dp_ram[0x400];
240 #define mace_perif_ctrl_read(r) \
241 mace_read(mace->perif.ctrl.r)
242 #define mace_perif_ctrl_write(v,r) \
243 mace_write(v,mace->perif.ctrl.r)
245 /* Keyboard & Mouse registers
246 * -> drivers/input/serio/maceps2.c */
247 struct mace_ps2port {
255 struct mace_ps2port keyb;
256 struct mace_ps2port mouse;
260 * -> drivers/i2c/algos/i2c-algo-sgi.c */
263 #define MACEI2C_RESET BIT(0)
264 #define MACEI2C_FAST BIT(1)
265 #define MACEI2C_DATA_OVERRIDE BIT(2)
266 #define MACEI2C_CLOCK_OVERRIDE BIT(3)
267 #define MACEI2C_DATA_STATUS BIT(4)
268 #define MACEI2C_CLOCK_STATUS BIT(5)
273 /* Timer registers */
277 volatile unsigned int ust;
278 volatile unsigned int msc;
284 #define MACE_UST_PERIOD_NS 960
291 timer_reg audio_out1;
292 timer_reg audio_out2;
299 struct mace_audio audio;
300 char _pad0[0x10000 - sizeof(struct mace_audio)];
302 struct mace_isactrl ctrl;
303 char _pad1[0x10000 - sizeof(struct mace_isactrl)];
306 char _pad2[0x10000 - sizeof(struct mace_ps2)];
309 char _pad3[0x10000 - sizeof(struct mace_i2c)];
311 struct mace_timers timers;
312 char _pad4[0x10000 - sizeof(struct mace_timers)];
321 struct mace_parallel { /* later... */
324 struct mace_ecp1284 { /* later... */
329 mace64_t xxx; /* later... */
333 struct mace_parallel parallel;
334 char _pad1[0x8000 - sizeof(struct mace_parallel)];
336 struct mace_ecp1284 ecp1284;
337 char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
339 struct mace_serial serial1;
340 char _pad3[0x8000 - sizeof(struct mace_serial)];
342 struct mace_serial serial2;
343 char _pad4[0x8000 - sizeof(struct mace_serial)];
345 volatile unsigned char rtc[0x10000];
349 char _reserved[0x80000];
352 char _pad0[0x80000 - sizeof(struct mace_pci)];
354 struct mace_video video_in1;
355 char _pad1[0x80000 - sizeof(struct mace_video)];
357 struct mace_video video_in2;
358 char _pad2[0x80000 - sizeof(struct mace_video)];
360 struct mace_video video_out;
361 char _pad3[0x80000 - sizeof(struct mace_video)];
363 struct mace_ethernet eth;
364 char _pad4[0x80000 - sizeof(struct mace_ethernet)];
366 struct mace_perif perif;
367 char _pad5[0x80000 - sizeof(struct mace_perif)];
370 char _pad6[0x80000 - sizeof(struct mace_isa)];
373 extern struct sgi_mace *mace;
375 #endif /* __ASM_MACE_H__ */