include/asm-mips/it8172/it8172.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      IT8172 system controller defines.
   5  *
   6  * Copyright 2000 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *              ppopov@mvista.com or source@mvista.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #ifndef __IT8172__H__
  32 #define __IT8172__H__
  33
  34 #include <asm/addrspace.h>
  35
  36 #define IT8172_BASE                     0x18000000
  37 #define IT8172_PCI_IO_BASE              0x14000000
  38 #define IT8172_PCI_MEM_BASE             0x10000000
  39
  40 // System registers offsets from IT8172_BASE
  41 #define IT_CMFPCR                       0x0
  42 #define IT_DSRR                         0x2
  43 #define IT_PCDCR                        0x4
  44 #define IT_SPLLCR                       0x6
  45 #define IT_CIDR                         0x10
  46 #define IT_CRNR                         0x12
  47 #define IT_CPUTR                        0x14
  48 #define IT_CTCR                         0x16
  49 #define IT_SDPR                         0xF0
  50
  51 // Power management register offset from IT8172_PCI_IO_BASE
  52 // Power Management Device Standby Register
  53 #define IT_PM_DSR               0x15800
  54
  55 #define IT_PM_DSR_TMR0SB        0x0001
  56 #define IT_PM_DSR_TMR1SB        0x0002
  57 #define IT_PM_DSR_CIR0SB        0x0004
  58 #define IT_PM_DSR_CIR1SB        0x0008
  59 #define IT_PM_DSR_SCR0SB        0x0010
  60 #define IT_PM_DSR_SCR1SB        0x0020
  61 #define IT_PM_DSR_PPSB          0x0040
  62 #define IT_PM_DSR_I2CSB         0x0080
  63 #define IT_PM_DSR_UARTSB        0x0100
  64 #define IT_PM_DSR_IDESB         0x0200
  65 #define IT_PM_DSR_ACSB          0x0400
  66 #define IT_PM_DSR_M68KSB        0x0800
  67
  68 // Power Management PCI Device Software Reset Register
  69 #define IT_PM_PCISR             0x15802
  70
  71 #define IT_PM_PCISR_IDESR       0x0001
  72 #define IT_PM_PCISR_CDMASR      0x0002
  73 #define IT_PM_PCISR_USBSR       0x0004
  74 #define IT_PM_PCISR_DMASR       0x0008
  75 #define IT_PM_PCISR_ACSR        0x0010
  76 #define IT_PM_PCISR_MEMSR       0x0020
  77 #define IT_PM_PCISR_68KSR       0x0040
  78
  79
  80 // PCI Configuration address and data register offsets
  81 // from IT8172_BASE
  82 #define IT_CONFADDR                     0x4000
  83 #define IT_BUSNUM_SHF                   16
  84 #define IT_DEVNUM_SHF                   11
  85 #define IT_FUNCNUM_SHF                  8
  86 #define IT_REGNUM_SHF                   2
  87
  88 #define IT_CONFDATA                     0x4004
  89
  90 // PCI configuration header common register offsets
  91 #define IT_VID                          0x00
  92 #define IT_DID                          0x02
  93 #define IT_PCICMD                       0x04
  94 #define IT_PCISTS                       0x06
  95 #define IT_RID                          0x08
  96 #define IT_CLASSC                       0x09
  97 #define IT_HEADT                        0x0E
  98 #define IT_SERIRQC                      0x49
  99
 100 // PCI to Internal/LPC Bus Bridge configuration header register offset
 101 #define IT_P2I_BCR                              0x4C
 102 #define IT_P2I_D0IOSC                           0x50
 103 #define IT_P2I_D1IOSC                           0x54
 104 #define IT_P2I_D2IOSC                           0x58
 105 #define IT_P2I_D3IOSC                           0x5C
 106 #define IT_P2I_D4IOSC                           0x60
 107 #define IT_P2I_D5IOSC                           0x64
 108 #define IT_P2I_D6IOSC                           0x68
 109 #define IT_P2I_D7IOSC                           0x6C
 110 #define IT_P2I_D8IOSC                           0x70
 111 #define IT_P2I_D9IOSC                           0x74
 112 #define IT_P2I_D10IOSC                          0x78
 113 #define IT_P2I_D11IOSC                          0x7C
 114
 115 // Memory controller register offsets from IT8172_BASE
 116 #define IT_MC_SDRMR                                     0x1000
 117 #define IT_MC_SDRTR                                     0x1004
 118 #define IT_MC_MCR                                       0x1008
 119 #define IT_MC_SDTYPE                                    0x100C
 120 #define IT_MC_WPBA                                      0x1010
 121 #define IT_MC_WPTA                                      0x1014
 122 #define IT_MC_HATR                                      0x1018
 123 #define IT_MC_PCICR                                     0x101C
 124
 125 // Flash/ROM control register offsets from IT8172_BASE
 126 #define IT_FC_BRCR                                      0x2000
 127 #define IT_FC_FCR                                       0x2004
 128 #define IT_FC_DCR                                       0x2008
 129
 130 // M68K interface bridge configuration header register offset
 131 #define IT_M68K_MBCSR                                   0x54
 132 #define IT_M68K_TMR                                     0x58
 133 #define IT_M68K_BCR                                     0x5C
 134 #define IT_M68K_BSR                                     0x5D
 135 #define IT_M68K_DTR                                     0x5F
 136
 137 // Register offset from IT8172_PCI_IO_BASE
 138 // These registers are accessible through 8172 PCI IO window.
 139
 140 // INTC
 141 #define IT_INTC_BASE                            0x10000
 142 #define IT_INTC_LBDNIRR                         0x10000
 143 #define IT_INTC_LBDNIMR                         0x10002
 144 #define IT_INTC_LBDNITR                         0x10004
 145 #define IT_INTC_LBDNIAR                         0x10006
 146 #define IT_INTC_LPCNIRR                         0x10010
 147 #define IT_INTC_LPCNIMR                         0x10012
 148 #define IT_INTC_LPCNITR                         0x10014
 149 #define IT_INTC_LPCNIAR                         0x10016
 150 #define IT_INTC_PDNIRR                          0x10020
 151 #define IT_INTC_PDNIMR                          0x10022
 152 #define IT_INTC_PDNITR                          0x10024
 153 #define IT_INTC_PDNIAR                          0x10026
 154 #define IT_INTC_UMNIRR                          0x10030
 155 #define IT_INTC_UMNITR                          0x10034
 156 #define IT_INTC_UMNIAR                          0x10036
 157 #define IT_INTC_TYPER                           0x107FE
 158
 159 // IT8172 PCI device number
 160 #define IT_C2P_DEVICE                           0
 161 #define IT_AUDIO_DEVICE                         1
 162 #define IT_DMAC_DEVICE                          1
 163 #define IT_CDMAC_DEVICE                         1
 164 #define IT_USB_DEVICE                           1
 165 #define IT_P2I_DEVICE                           1
 166 #define IT_IDE_DEVICE                           1
 167 #define IT_M68K_DEVICE                          1
 168
 169 // IT8172 PCI function number
 170 #define IT_C2P_FUNCION                          0
 171 #define IT_AUDIO_FUNCTION                       0
 172 #define IT_DMAC_FUNCTION                        1
 173 #define IT_CDMAC_FUNCTION                       2
 174 #define IT_USB_FUNCTION                         3
 175 #define IT_P2I_FUNCTION                         4
 176 #define IT_IDE_FUNCTION                         5
 177 #define IT_M68K_FUNCTION                        6
 178
 179 // IT8172 GPIO
 180 #define IT_GPADR                                0x13800
 181 #define IT_GPBDR                                0x13808
 182 #define IT_GPCDR                                0x13810
 183 #define IT_GPACR                                0x13802
 184 #define IT_GPBCR                                0x1380A
 185 #define IT_GPCCR                                0x13812
 186 #define IT_GPAICR                               0x13804
 187 #define IT_GPBICR                               0x1380C
 188 #define IT_GPCICR                               0x13814
 189 #define IT_GPAISR                               0x13806
 190 #define IT_GPBISR                               0x1380E
 191 #define IT_GPCISR                               0x13816
 192 #define IT_GCR                                  0x13818
 193
 194 // IT8172 RTC
 195 #define IT_RTC_BASE                             0x14800
 196 #define IT_RTC_CENTURY                          0x14808
 197
 198 #define IT_RTC_RIR0                             0x00
 199 #define IT_RTC_RTR0                             0x01
 200 #define IT_RTC_RIR1                             0x02
 201 #define IT_RTC_RTR1                             0x03
 202 #define IT_RTC_RIR2                             0x04
 203 #define IT_RTC_RTR2                             0x05
 204 #define IT_RTC_RCTR                             0x08
 205 #define IT_RTC_RA                               0x0A
 206 #define IT_RTC_RB                               0x0B
 207 #define IT_RTC_RC                               0x0C
 208 #define IT_RTC_RD                               0x0D
 209
 210 #define RTC_SEC_INDEX                           0x00
 211 #define RTC_MIN_INDEX                           0x02
 212 #define RTC_HOUR_INDEX                          0x04
 213 #define RTC_DAY_INDEX                           0x06
 214 #define RTC_DATE_INDEX                          0x07
 215 #define RTC_MONTH_INDEX                         0x08
 216 #define RTC_YEAR_INDEX                          0x09
 217
 218 // IT8172 internal device registers
 219 #define IT_TIMER_BASE                           0x10800
 220 #define IT_CIR0_BASE                            0x11000
 221 #define IT_UART_BASE                            0x11800
 222 #define IT_SCR0_BASE                            0x12000
 223 #define IT_SCR1_BASE                            0x12800
 224 #define IT_PP_BASE                              0x13000
 225 #define IT_I2C_BASE                             0x14000
 226 #define IT_CIR1_BASE                            0x15000
 227
 228 // IT8172 Smart Card Reader offsets from IT_SCR*_BASE
 229 #define IT_SCR_SFR                              0x08
 230 #define IT_SCR_SCDR                             0x09
 231
 232 // IT8172 IT_SCR_SFR bit definition & mask
 233 #define IT_SCR_SFR_GATE_UART                    0x40
 234 #define IT_SCR_SFR_GATE_UART_BIT                6
 235 #define IT_SCR_SFR_GATE_UART_OFF                0
 236 #define IT_SCR_SFR_GATE_UART_ON                 1
 237 #define IT_SCR_SFR_FET_CHARGE                   0x30
 238 #define IT_SCR_SFR_FET_CHARGE_BIT               4
 239 #define IT_SCR_SFR_FET_CHARGE_3_3_US            3
 240 #define IT_SCR_SFR_FET_CHARGE_13_US             2
 241 #define IT_SCR_SFR_FET_CHARGE_53_US             1
 242 #define IT_SCR_SFR_FET_CHARGE_213_US            0
 243 #define IT_SCR_SFR_CARD_FREQ                    0x0C
 244 #define IT_SCR_SFR_CARD_FREQ_BIT                2
 245 #define IT_SCR_SFR_CARD_FREQ_STOP               3
 246 #define IT_SCR_SFR_CARD_FREQ_3_5_MHZ            0
 247 #define IT_SCR_SFR_CARD_FREQ_7_1_MHZ            2
 248 #define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ         1
 249 #define IT_SCR_SFR_FET_ACTIVE                   0x02
 250 #define IT_SCR_SFR_FET_ACTIVE_BIT               1
 251 #define IT_SCR_SFR_FET_ACTIVE_INVERT            0
 252 #define IT_SCR_SFR_FET_ACTIVE_NONINVERT         1
 253 #define IT_SCR_SFR_ENABLE                       0x01
 254 #define IT_SCR_SFR_ENABLE_BIT                   0
 255 #define IT_SCR_SFR_ENABLE_OFF                   0
 256 #define IT_SCR_SFR_ENABLE_ON                    1
 257
 258 // IT8172 IT_SCR_SCDR bit definition & mask
 259 #define IT_SCR_SCDR_RESET_MODE                  0x80
 260 #define IT_SCR_SCDR_RESET_MODE_BIT              7
 261 #define IT_SCR_SCDR_RESET_MODE_ASYNC            0
 262 #define IT_SCR_SCDR_RESET_MODE_SYNC             1
 263 #define IT_SCR_SCDR_DIVISOR                     0x7F
 264 #define IT_SCR_SCDR_DIVISOR_BIT                 0
 265 #define IT_SCR_SCDR_DIVISOR_STOP_VAL_1          0x00
 266 #define IT_SCR_SCDR_DIVISOR_STOP_VAL_2          0x01
 267 #define IT_SCR_SCDR_DIVISOR_STOP_VAL_3          0x7F
 268
 269 // IT8172 DMA
 270 #define IT_DMAC_BASE                            0x16000
 271 #define IT_DMAC_BCAR0                           0x00
 272 #define IT_DMAC_BCAR1                           0x04
 273 #define IT_DMAC_BCAR2                           0x08
 274 #define IT_DMAC_BCAR3                           0x0C
 275 #define IT_DMAC_BCCR0                           0x02
 276 #define IT_DMAC_BCCR1                           0x06
 277 #define IT_DMAC_BCCR2                           0x0a
 278 #define IT_DMAC_BCCR3                           0x0e
 279 #define IT_DMAC_CR                              0x10
 280 #define IT_DMAC_SR                              0x12
 281 #define IT_DMAC_ESR                             0x13
 282 #define IT_DMAC_RQR                             0x14
 283 #define IT_DMAC_MR                              0x16
 284 #define IT_DMAC_EMR                             0x17
 285 #define IT_DMAC_MKR                             0x18
 286 #define IT_DMAC_PAR0                            0x20
 287 #define IT_DMAC_PAR1                            0x22
 288 #define IT_DMAC_PAR2                            0x24
 289 #define IT_DMAC_PAR3                            0x26
 290
 291 // IT8172 IDE
 292 #define IT_IDE_BASE                             0x17800
 293 #define IT_IDE_STATUS                           0x1F7
 294
 295 // IT8172 Audio Controller
 296 #define IT_AC_BASE                              0x17000
 297 #define IT_AC_PCMOV                             0x00
 298 #define IT_AC_FMOV                              0x02
 299 #define IT_AC_I2SV                              0x04
 300 #define IT_AC_DRSS                              0x06
 301 #define IT_AC_PCC                               0x08
 302 #define IT_AC_PCDL                              0x0A
 303 #define IT_AC_PCB1STA                           0x0C
 304 #define IT_AC_PCB2STA                           0x10
 305 #define IT_AC_CAPCC                             0x14
 306 #define IT_AC_CAPCDL                            0x16
 307 #define IT_AC_CAPB1STA                          0x18
 308 #define IT_AC_CAPB2STA                          0x1C
 309 #define IT_AC_CODECC                            0x22
 310 #define IT_AC_I2SMC                             0x24
 311 #define IT_AC_VS                                0x26
 312 #define IT_AC_SRCS                              0x28
 313 #define IT_AC_CIRCP                             0x2A
 314 #define IT_AC_CIRDP                             0x2C
 315 #define IT_AC_TM                                0x4A
 316 #define IT_AC_PFDP                              0x4C
 317 #define IT_AC_GC                                0x54
 318 #define IT_AC_IMC                               0x56
 319 #define IT_AC_ISC                               0x5B
 320 #define IT_AC_OPL3SR                            0x68
 321 #define IT_AC_OPL3DWDR                          0x69
 322 #define IT_AC_OPL3AB1W                          0x6A
 323 #define IT_AC_OPL3DW                            0x6B
 324 #define IT_AC_BPDC                              0x70
 325
 326
 327 // IT8172 Timer
 328 #define IT_TIMER_BASE                           0x10800
 329 #define TIMER_TCVR0                             0x00
 330 #define TIMER_TRVR0                             0x02
 331 #define TIMER_TCR0                              0x04
 332 #define TIMER_TIRR                              0x06
 333 #define TIMER_TCVR1                             0x08
 334 #define TIMER_TRVR1                             0x0A
 335 #define TIMER_TCR1                              0x0C
 336 #define TIMER_TIDR                              0x0E
 337
 338
 339 #define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
 340 #define IT_READ(ofs, data)  data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
 341
 342 #define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
 343 #define IT_IO_READ(ofs, data)  data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
 344
 345 #define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
 346 #define IT_IO_READ16(ofs, data)  data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
 347
 348 #endif