3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
43 /* cpu pipeline flush */
44 void static inline au_sync(void)
46 __asm__ volatile ("sync");
49 void static inline au_sync_udelay(int us)
51 __asm__ volatile ("sync");
55 void static inline au_sync_delay(int ms)
57 __asm__ volatile ("sync");
61 void static inline au_writeb(u8 val, int reg)
63 *(volatile u8 *)(reg) = val;
66 void static inline au_writew(u16 val, int reg)
68 *(volatile u16 *)(reg) = val;
71 void static inline au_writel(u32 val, int reg)
73 *(volatile u32 *)(reg) = val;
76 static inline u8 au_readb(unsigned long port)
78 return (*(volatile u8 *)port);
81 static inline u16 au_readw(unsigned long port)
83 return (*(volatile u16 *)port);
86 static inline u32 au_readl(unsigned long port)
88 return (*(volatile u32 *)port);
91 /* These next three functions should be a generic part of the MIPS
92 * kernel (with the 'au_' removed from the name) and selected for
93 * processors that support the instructions.
94 * Taken from PPC tree. -- Dan
96 /* Return the bit position of the most significant 1 bit in a word */
97 static __inline__ int __ilog2(unsigned int x)
102 ".set\tnoreorder\n\t"
115 static __inline__ int au_ffz(unsigned int x)
119 return __ilog2(x & -x);
123 * ffs: find first bit set. This is defined the same way as
124 * the libc and compiler builtin ffs routines, therefore
125 * differs in spirit from the above ffz (man ffs).
127 static __inline__ int au_ffs(int x)
129 return __ilog2(x & -x) + 1;
132 /* arch/mips/au1000/common/clocks.c */
133 extern void set_au1x00_speed(unsigned int new_freq);
134 extern unsigned int get_au1x00_speed(void);
135 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
136 extern unsigned long get_au1x00_uart_baud_base(void);
137 extern void set_au1x00_lcd_clock(void);
138 extern unsigned int get_au1x00_lcd_clock(void);
141 * Every board describes its IRQ mapping with this table.
143 typedef struct au1xxx_irqmap {
150 * init_IRQ looks for a table with this name.
152 extern au1xxx_irq_map_t au1xxx_irq_map[];
154 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
157 /* no CP0 timer irq */
158 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
160 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
163 /* SDRAM Controller */
164 #define MEM_SDMODE0 0xB4000000
165 #define MEM_SDMODE1 0xB4000004
166 #define MEM_SDMODE2 0xB4000008
168 #define MEM_SDADDR0 0xB400000C
169 #define MEM_SDADDR1 0xB4000010
170 #define MEM_SDADDR2 0xB4000014
172 #define MEM_SDREFCFG 0xB4000018
173 #define MEM_SDPRECMD 0xB400001C
174 #define MEM_SDAUTOREF 0xB4000020
176 #define MEM_SDWRMD0 0xB4000024
177 #define MEM_SDWRMD1 0xB4000028
178 #define MEM_SDWRMD2 0xB400002C
180 #define MEM_SDSLEEP 0xB4000030
181 #define MEM_SDSMCKE 0xB4000034
183 /* Static Bus Controller */
184 #define MEM_STCFG0 0xB4001000
185 #define MEM_STTIME0 0xB4001004
186 #define MEM_STADDR0 0xB4001008
188 #define MEM_STCFG1 0xB4001010
189 #define MEM_STTIME1 0xB4001014
190 #define MEM_STADDR1 0xB4001018
192 #define MEM_STCFG2 0xB4001020
193 #define MEM_STTIME2 0xB4001024
194 #define MEM_STADDR2 0xB4001028
196 #define MEM_STCFG3 0xB4001030
197 #define MEM_STTIME3 0xB4001034
198 #define MEM_STADDR3 0xB4001038
200 #ifdef CONFIG_SOC_AU1550
201 #define MEM_STNDCTL 0xB4001100
202 #define MEM_STSTAT 0xB4001104
204 #define MEM_STNAND_CMD (0x0)
205 #define MEM_STNAND_ADDR (0x4)
206 #define MEM_STNAND_DATA (0x20)
209 /* Interrupt Controller 0 */
210 #define IC0_CFG0RD 0xB0400040
211 #define IC0_CFG0SET 0xB0400040
212 #define IC0_CFG0CLR 0xB0400044
214 #define IC0_CFG1RD 0xB0400048
215 #define IC0_CFG1SET 0xB0400048
216 #define IC0_CFG1CLR 0xB040004C
218 #define IC0_CFG2RD 0xB0400050
219 #define IC0_CFG2SET 0xB0400050
220 #define IC0_CFG2CLR 0xB0400054
222 #define IC0_REQ0INT 0xB0400054
223 #define IC0_SRCRD 0xB0400058
224 #define IC0_SRCSET 0xB0400058
225 #define IC0_SRCCLR 0xB040005C
226 #define IC0_REQ1INT 0xB040005C
228 #define IC0_ASSIGNRD 0xB0400060
229 #define IC0_ASSIGNSET 0xB0400060
230 #define IC0_ASSIGNCLR 0xB0400064
232 #define IC0_WAKERD 0xB0400068
233 #define IC0_WAKESET 0xB0400068
234 #define IC0_WAKECLR 0xB040006C
236 #define IC0_MASKRD 0xB0400070
237 #define IC0_MASKSET 0xB0400070
238 #define IC0_MASKCLR 0xB0400074
240 #define IC0_RISINGRD 0xB0400078
241 #define IC0_RISINGCLR 0xB0400078
242 #define IC0_FALLINGRD 0xB040007C
243 #define IC0_FALLINGCLR 0xB040007C
245 #define IC0_TESTBIT 0xB0400080
247 /* Interrupt Controller 1 */
248 #define IC1_CFG0RD 0xB1800040
249 #define IC1_CFG0SET 0xB1800040
250 #define IC1_CFG0CLR 0xB1800044
252 #define IC1_CFG1RD 0xB1800048
253 #define IC1_CFG1SET 0xB1800048
254 #define IC1_CFG1CLR 0xB180004C
256 #define IC1_CFG2RD 0xB1800050
257 #define IC1_CFG2SET 0xB1800050
258 #define IC1_CFG2CLR 0xB1800054
260 #define IC1_REQ0INT 0xB1800054
261 #define IC1_SRCRD 0xB1800058
262 #define IC1_SRCSET 0xB1800058
263 #define IC1_SRCCLR 0xB180005C
264 #define IC1_REQ1INT 0xB180005C
266 #define IC1_ASSIGNRD 0xB1800060
267 #define IC1_ASSIGNSET 0xB1800060
268 #define IC1_ASSIGNCLR 0xB1800064
270 #define IC1_WAKERD 0xB1800068
271 #define IC1_WAKESET 0xB1800068
272 #define IC1_WAKECLR 0xB180006C
274 #define IC1_MASKRD 0xB1800070
275 #define IC1_MASKSET 0xB1800070
276 #define IC1_MASKCLR 0xB1800074
278 #define IC1_RISINGRD 0xB1800078
279 #define IC1_RISINGCLR 0xB1800078
280 #define IC1_FALLINGRD 0xB180007C
281 #define IC1_FALLINGCLR 0xB180007C
283 #define IC1_TESTBIT 0xB1800080
285 /* Interrupt Configuration Modes */
286 #define INTC_INT_DISABLED 0
287 #define INTC_INT_RISE_EDGE 0x1
288 #define INTC_INT_FALL_EDGE 0x2
289 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
290 #define INTC_INT_HIGH_LEVEL 0x5
291 #define INTC_INT_LOW_LEVEL 0x6
292 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
294 /* Interrupt Numbers */
295 #define AU1000_UART0_INT 0
296 #define AU1000_UART1_INT 1 /* au1000 */
297 #define AU1000_UART2_INT 2 /* au1000 */
299 #define AU1000_PCI_INTA 1 /* au1500 */
300 #define AU1000_PCI_INTB 2 /* au1500 */
302 #define AU1000_UART3_INT 3
304 #define AU1000_SSI0_INT 4 /* au1000 */
305 #define AU1000_SSI1_INT 5 /* au1000 */
307 #define AU1000_PCI_INTC 4 /* au1500 */
308 #define AU1000_PCI_INTD 5 /* au1500 */
310 #define AU1000_DMA_INT_BASE 6
311 #define AU1000_TOY_INT 14
312 #define AU1000_TOY_MATCH0_INT 15
313 #define AU1000_TOY_MATCH1_INT 16
314 #define AU1000_TOY_MATCH2_INT 17
315 #define AU1000_RTC_INT 18
316 #define AU1000_RTC_MATCH0_INT 19
317 #define AU1000_RTC_MATCH1_INT 20
318 #define AU1000_RTC_MATCH2_INT 21
319 #define AU1000_IRDA_TX_INT 22 /* au1000 */
320 #define AU1000_IRDA_RX_INT 23 /* au1000 */
321 #define AU1000_USB_DEV_REQ_INT 24
322 #define AU1000_USB_DEV_SUS_INT 25
323 #define AU1000_USB_HOST_INT 26
324 #define AU1000_ACSYNC_INT 27
325 #define AU1000_MAC0_DMA_INT 28
326 #define AU1000_MAC1_DMA_INT 29
327 #define AU1000_ETH0_IRQ AU1000_MAC0_DMA_INT
328 #define AU1000_ETH1_IRQ AU1000_MAC1_DMA_INT
329 #define AU1000_I2S_UO_INT 30 /* au1000 */
330 #define AU1000_AC97C_INT 31
331 #define AU1000_LAST_INTC0_INT AU1000_AC97C_INT
332 #define AU1000_GPIO_0 32
333 #define AU1000_GPIO_1 33
334 #define AU1000_GPIO_2 34
335 #define AU1000_GPIO_3 35
336 #define AU1000_GPIO_4 36
337 #define AU1000_GPIO_5 37
338 #define AU1000_GPIO_6 38
339 #define AU1000_GPIO_7 39
340 #define AU1000_GPIO_8 40
341 #define AU1000_GPIO_9 41
342 #define AU1000_GPIO_10 42
343 #define AU1000_GPIO_11 43
344 #define AU1000_GPIO_12 44
345 #define AU1000_GPIO_13 45
346 #define AU1000_GPIO_14 46
347 #define AU1000_GPIO_15 47
350 #define AU1000_GPIO_16 48
351 #define AU1000_GPIO_17 49
352 #define AU1000_GPIO_18 50
353 #define AU1000_GPIO_19 51
354 #define AU1000_GPIO_20 52
355 #define AU1000_GPIO_21 53
356 #define AU1000_GPIO_22 54
357 #define AU1000_GPIO_23 55
358 #define AU1000_GPIO_24 56
359 #define AU1000_GPIO_25 57
360 #define AU1000_GPIO_26 58
361 #define AU1000_GPIO_27 59
362 #define AU1000_GPIO_28 60
363 #define AU1000_GPIO_29 61
364 #define AU1000_GPIO_30 62
365 #define AU1000_GPIO_31 63
368 #define AU1500_GPIO_200 48
369 #define AU1500_GPIO_201 49
370 #define AU1500_GPIO_202 50
371 #define AU1500_GPIO_203 51
372 #define AU1500_GPIO_20 52
373 #define AU1500_GPIO_204 53
374 #define AU1500_GPIO_205 54
375 #define AU1500_GPIO_23 55
376 #define AU1500_GPIO_24 56
377 #define AU1500_GPIO_25 57
378 #define AU1500_GPIO_26 58
379 #define AU1500_GPIO_27 59
380 #define AU1500_GPIO_28 60
381 #define AU1500_GPIO_206 61
382 #define AU1500_GPIO_207 62
383 #define AU1500_GPIO_208_215 63
385 #define AU1000_MAX_INTR 63
388 #define AU1100_GPIO_208_215 29
389 // Seperate defines for AU1550 SOC
390 #define AU1550_UART0_INT AU1000_UART0_INT
391 #define AU1550_PCI_INTA AU1000_PCI_INTA
392 #define AU1550_PCI_INTB AU1000_PCI_INTB
393 #define AU1550_DDMA_INT 3
394 #define AU1550_CRYPTO_INT 4
395 #define AU1550_PCI_INTC 5
396 #define AU1550_PCI_INTD 6
397 #define AU1550_PCI_RST_INT 7
398 #define AU1550_UART1_INT 8
399 #define AU1550_UART3_INT 9
400 #define AU1550_PSC0_INT 10
401 #define AU1550_PSC1_INT 11
402 #define AU1550_PSC2_INT 12
403 #define AU1550_PSC3_INT 13
404 #define AU1550_TOY_INT 14
405 #define AU1550_TOY_MATCH0_INT 15
406 #define AU1550_TOY_MATCH1_INT 16
407 #define AU1550_TOY_MATCH2_INT 17
408 #define AU1550_RTC_INT 18
409 #define AU1550_RTC_MATCH0_INT 19
410 #define AU1550_RTC_MATCH1_INT 20
411 #define AU1550_RTC_MATCH2_INT 21
412 #define AU1550_NAND_INT 23
413 #define AU1550_USB_DEV_REQ_INT 24
414 #define AU1550_USB_DEV_SUS_INT 25
415 #define AU1550_USB_HOST_INT 26
416 #define AU1550_MAC0_DMA_INT 27
417 #define AU1550_MAC1_DMA_INT 28
418 #define AU1550_ETH0_IRQ AU1550_MAC0_DMA_INT
419 #define AU1550_ETH1_IRQ AU1550_MAC1_DMA_INT
421 #define AU1550_GPIO_200 48
422 #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
423 #define AU1500_GPIO_16 50
424 #define AU1500_GPIO_17 51
425 #define AU1500_GPIO_20 52
426 #define AU1500_GPIO_21 53
427 #define AU1500_GPIO_22 54
428 #define AU1500_GPIO_23 55
429 #define AU1500_GPIO_24 56
430 #define AU1500_GPIO_25 57
431 #define AU1500_GPIO_26 58
432 #define AU1500_GPIO_27 59
433 #define AU1500_GPIO_28 60
434 #define AU1500_GPIO_206 61
435 #define AU1500_GPIO_207 62
436 #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
438 // REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE
441 /* Programmable Counters 0 and 1 */
442 #define SYS_BASE 0xB1900000
443 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
444 #define SYS_CNTRL_E1S (1<<23)
445 #define SYS_CNTRL_T1S (1<<20)
446 #define SYS_CNTRL_M21 (1<<19)
447 #define SYS_CNTRL_M11 (1<<18)
448 #define SYS_CNTRL_M01 (1<<17)
449 #define SYS_CNTRL_C1S (1<<16)
450 #define SYS_CNTRL_BP (1<<14)
451 #define SYS_CNTRL_EN1 (1<<13)
452 #define SYS_CNTRL_BT1 (1<<12)
453 #define SYS_CNTRL_EN0 (1<<11)
454 #define SYS_CNTRL_BT0 (1<<10)
455 #define SYS_CNTRL_E0 (1<<8)
456 #define SYS_CNTRL_E0S (1<<7)
457 #define SYS_CNTRL_32S (1<<5)
458 #define SYS_CNTRL_T0S (1<<4)
459 #define SYS_CNTRL_M20 (1<<3)
460 #define SYS_CNTRL_M10 (1<<2)
461 #define SYS_CNTRL_M00 (1<<1)
462 #define SYS_CNTRL_C0S (1<<0)
464 /* Programmable Counter 0 Registers */
465 #define SYS_TOYTRIM (SYS_BASE + 0)
466 #define SYS_TOYWRITE (SYS_BASE + 4)
467 #define SYS_TOYMATCH0 (SYS_BASE + 8)
468 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
469 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
470 #define SYS_TOYREAD (SYS_BASE + 0x40)
472 /* Programmable Counter 1 Registers */
473 #define SYS_RTCTRIM (SYS_BASE + 0x44)
474 #define SYS_RTCWRITE (SYS_BASE + 0x48)
475 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
476 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
477 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
478 #define SYS_RTCREAD (SYS_BASE + 0x58)
481 #define I2S_DATA 0xB1000000
482 #define I2S_DATA_MASK (0xffffff)
483 #define I2S_CONFIG 0xB1000004
484 #define I2S_CONFIG_XU (1<<25)
485 #define I2S_CONFIG_XO (1<<24)
486 #define I2S_CONFIG_RU (1<<23)
487 #define I2S_CONFIG_RO (1<<22)
488 #define I2S_CONFIG_TR (1<<21)
489 #define I2S_CONFIG_TE (1<<20)
490 #define I2S_CONFIG_TF (1<<19)
491 #define I2S_CONFIG_RR (1<<18)
492 #define I2S_CONFIG_RE (1<<17)
493 #define I2S_CONFIG_RF (1<<16)
494 #define I2S_CONFIG_PD (1<<11)
495 #define I2S_CONFIG_LB (1<<10)
496 #define I2S_CONFIG_IC (1<<9)
497 #define I2S_CONFIG_FM_BIT 7
498 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
499 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
500 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
501 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
502 #define I2S_CONFIG_TN (1<<6)
503 #define I2S_CONFIG_RN (1<<5)
504 #define I2S_CONFIG_SZ_BIT 0
505 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
507 #define I2S_CONTROL 0xB1000008
508 #define I2S_CONTROL_D (1<<1)
509 #define I2S_CONTROL_CE (1<<0)
511 /* USB Host Controller */
512 // We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address
513 #if defined( CONFIG_SOC_AU1550 )
514 #define USB_OHCI_BASE 0x14020000
515 #define USB_OHCI_LEN 0x00100000
516 #define USB_HOST_CONFIG 0xB4027ffc
518 #define USB_OHCI_BASE 0x10100000
519 #define USB_OHCI_LEN 0x00100000
520 #define USB_HOST_CONFIG 0xB017fffc
523 /* USB Device Controller */
524 #define USBD_EP0RD 0xB0200000
525 #define USBD_EP0WR 0xB0200004
526 #define USBD_EP2WR 0xB0200008
527 #define USBD_EP3WR 0xB020000C
528 #define USBD_EP4RD 0xB0200010
529 #define USBD_EP5RD 0xB0200014
530 #define USBD_INTEN 0xB0200018
531 #define USBD_INTSTAT 0xB020001C
532 #define USBDEV_INT_SOF (1<<12)
533 #define USBDEV_INT_HF_BIT 6
534 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
535 #define USBDEV_INT_CMPLT_BIT 0
536 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
537 #define USBD_CONFIG 0xB0200020
538 #define USBD_EP0CS 0xB0200024
539 #define USBD_EP2CS 0xB0200028
540 #define USBD_EP3CS 0xB020002C
541 #define USBD_EP4CS 0xB0200030
542 #define USBD_EP5CS 0xB0200034
543 #define USBDEV_CS_SU (1<<14)
544 #define USBDEV_CS_NAK (1<<13)
545 #define USBDEV_CS_ACK (1<<12)
546 #define USBDEV_CS_BUSY (1<<11)
547 #define USBDEV_CS_TSIZE_BIT 1
548 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
549 #define USBDEV_CS_STALL (1<<0)
550 #define USBD_EP0RDSTAT 0xB0200040
551 #define USBD_EP0WRSTAT 0xB0200044
552 #define USBD_EP2WRSTAT 0xB0200048
553 #define USBD_EP3WRSTAT 0xB020004C
554 #define USBD_EP4RDSTAT 0xB0200050
555 #define USBD_EP5RDSTAT 0xB0200054
556 #define USBDEV_FSTAT_FLUSH (1<<6)
557 #define USBDEV_FSTAT_UF (1<<5)
558 #define USBDEV_FSTAT_OF (1<<4)
559 #define USBDEV_FSTAT_FCNT_BIT 0
560 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
561 #define USBD_ENABLE 0xB0200058
562 #define USBDEV_ENABLE (1<<1)
563 #define USBDEV_CE (1<<0)
565 /* Ethernet Controllers */
566 #define AU1000_ETH0_BASE 0xB0500000
567 #define AU1000_ETH1_BASE 0xB0510000
568 #define AU1500_ETH0_BASE 0xB1500000
569 #define AU1500_ETH1_BASE 0xB1510000
570 #define AU1100_ETH0_BASE 0xB0500000
571 #define AU1550_ETH0_BASE 0xB0500000
572 #define AU1550_ETH1_BASE 0xB0510000
574 /* 4 byte offsets from AU1000_ETH_BASE */
575 #define MAC_CONTROL 0x0
576 #define MAC_RX_ENABLE (1<<2)
577 #define MAC_TX_ENABLE (1<<3)
578 #define MAC_DEF_CHECK (1<<5)
579 #define MAC_SET_BL(X) (((X)&0x3)<<6)
580 #define MAC_AUTO_PAD (1<<8)
581 #define MAC_DISABLE_RETRY (1<<10)
582 #define MAC_DISABLE_BCAST (1<<11)
583 #define MAC_LATE_COL (1<<12)
584 #define MAC_HASH_MODE (1<<13)
585 #define MAC_HASH_ONLY (1<<15)
586 #define MAC_PASS_ALL (1<<16)
587 #define MAC_INVERSE_FILTER (1<<17)
588 #define MAC_PROMISCUOUS (1<<18)
589 #define MAC_PASS_ALL_MULTI (1<<19)
590 #define MAC_FULL_DUPLEX (1<<20)
591 #define MAC_NORMAL_MODE 0
592 #define MAC_INT_LOOPBACK (1<<21)
593 #define MAC_EXT_LOOPBACK (1<<22)
594 #define MAC_DISABLE_RX_OWN (1<<23)
595 #define MAC_BIG_ENDIAN (1<<30)
596 #define MAC_RX_ALL (1<<31)
597 #define MAC_ADDRESS_HIGH 0x4
598 #define MAC_ADDRESS_LOW 0x8
599 #define MAC_MCAST_HIGH 0xC
600 #define MAC_MCAST_LOW 0x10
601 #define MAC_MII_CNTRL 0x14
602 #define MAC_MII_BUSY (1<<0)
603 #define MAC_MII_READ 0
604 #define MAC_MII_WRITE (1<<1)
605 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
606 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
607 #define MAC_MII_DATA 0x18
608 #define MAC_FLOW_CNTRL 0x1C
609 #define MAC_FLOW_CNTRL_BUSY (1<<0)
610 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
611 #define MAC_PASS_CONTROL (1<<2)
612 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
613 #define MAC_VLAN1_TAG 0x20
614 #define MAC_VLAN2_TAG 0x24
616 /* Ethernet Controller Enable */
617 #define AU1000_MAC0_ENABLE 0xB0520000
618 #define AU1000_MAC1_ENABLE 0xB0520004
619 #define AU1500_MAC0_ENABLE 0xB1520000
620 #define AU1500_MAC1_ENABLE 0xB1520004
621 #define AU1100_MAC0_ENABLE 0xB0520000
623 #define MAC_EN_CLOCK_ENABLE (1<<0)
624 #define MAC_EN_RESET0 (1<<1)
625 #define MAC_EN_TOSS (0<<2)
626 #define MAC_EN_CACHEABLE (1<<3)
627 #define MAC_EN_RESET1 (1<<4)
628 #define MAC_EN_RESET2 (1<<5)
629 #define MAC_DMA_RESET (1<<6)
631 /* Ethernet Controller DMA Channels */
633 #define MAC0_TX_DMA_ADDR 0xB4004000
634 #define MAC1_TX_DMA_ADDR 0xB4004200
635 /* offsets from MAC_TX_RING_ADDR address */
636 #define MAC_TX_BUFF0_STATUS 0x0
637 #define TX_FRAME_ABORTED (1<<0)
638 #define TX_JAB_TIMEOUT (1<<1)
639 #define TX_NO_CARRIER (1<<2)
640 #define TX_LOSS_CARRIER (1<<3)
641 #define TX_EXC_DEF (1<<4)
642 #define TX_LATE_COLL_ABORT (1<<5)
643 #define TX_EXC_COLL (1<<6)
644 #define TX_UNDERRUN (1<<7)
645 #define TX_DEFERRED (1<<8)
646 #define TX_LATE_COLL (1<<9)
647 #define TX_COLL_CNT_MASK (0xF<<10)
648 #define TX_PKT_RETRY (1<<31)
649 #define MAC_TX_BUFF0_ADDR 0x4
650 #define TX_DMA_ENABLE (1<<0)
651 #define TX_T_DONE (1<<1)
652 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
653 #define MAC_TX_BUFF0_LEN 0x8
654 #define MAC_TX_BUFF1_STATUS 0x10
655 #define MAC_TX_BUFF1_ADDR 0x14
656 #define MAC_TX_BUFF1_LEN 0x18
657 #define MAC_TX_BUFF2_STATUS 0x20
658 #define MAC_TX_BUFF2_ADDR 0x24
659 #define MAC_TX_BUFF2_LEN 0x28
660 #define MAC_TX_BUFF3_STATUS 0x30
661 #define MAC_TX_BUFF3_ADDR 0x34
662 #define MAC_TX_BUFF3_LEN 0x38
664 #define MAC0_RX_DMA_ADDR 0xB4004100
665 #define MAC1_RX_DMA_ADDR 0xB4004300
666 /* offsets from MAC_RX_RING_ADDR */
667 #define MAC_RX_BUFF0_STATUS 0x0
668 #define RX_FRAME_LEN_MASK 0x3fff
669 #define RX_WDOG_TIMER (1<<14)
670 #define RX_RUNT (1<<15)
671 #define RX_OVERLEN (1<<16)
672 #define RX_COLL (1<<17)
673 #define RX_ETHER (1<<18)
674 #define RX_MII_ERROR (1<<19)
675 #define RX_DRIBBLING (1<<20)
676 #define RX_CRC_ERROR (1<<21)
677 #define RX_VLAN1 (1<<22)
678 #define RX_VLAN2 (1<<23)
679 #define RX_LEN_ERROR (1<<24)
680 #define RX_CNTRL_FRAME (1<<25)
681 #define RX_U_CNTRL_FRAME (1<<26)
682 #define RX_MCAST_FRAME (1<<27)
683 #define RX_BCAST_FRAME (1<<28)
684 #define RX_FILTER_FAIL (1<<29)
685 #define RX_PACKET_FILTER (1<<30)
686 #define RX_MISSED_FRAME (1<<31)
688 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
689 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
690 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
691 #define MAC_RX_BUFF0_ADDR 0x4
692 #define RX_DMA_ENABLE (1<<0)
693 #define RX_T_DONE (1<<1)
694 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
695 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
696 #define MAC_RX_BUFF1_STATUS 0x10
697 #define MAC_RX_BUFF1_ADDR 0x14
698 #define MAC_RX_BUFF2_STATUS 0x20
699 #define MAC_RX_BUFF2_ADDR 0x24
700 #define MAC_RX_BUFF3_STATUS 0x30
701 #define MAC_RX_BUFF3_ADDR 0x34
705 #define UART0_ADDR 0xB1100000
706 #define UART1_ADDR 0xB1200000
707 #define UART2_ADDR 0xB1300000
708 #define UART3_ADDR 0xB1400000
709 #define UART_BASE UART0_ADDR
710 #define UART_DEBUG_BASE UART3_ADDR
712 #define UART_RX 0 /* Receive buffer */
713 #define UART_TX 4 /* Transmit buffer */
714 #define UART_IER 8 /* Interrupt Enable Register */
715 #define UART_IIR 0xC /* Interrupt ID Register */
716 #define UART_FCR 0x10 /* FIFO Control Register */
717 #define UART_LCR 0x14 /* Line Control Register */
718 #define UART_MCR 0x18 /* Modem Control Register */
719 #define UART_LSR 0x1C /* Line Status Register */
720 #define UART_MSR 0x20 /* Modem Status Register */
721 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
722 #define UART_MOD_CNTRL 0x100 /* Module Control */
724 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
725 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
726 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
727 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
728 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
729 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
730 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
731 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
732 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
733 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
734 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
735 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
736 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
739 * These are the definitions for the Line Control Register
741 #define UART_LCR_SBC 0x40 /* Set break control */
742 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
743 #define UART_LCR_EPAR 0x10 /* Even parity select */
744 #define UART_LCR_PARITY 0x08 /* Parity Enable */
745 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
746 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
747 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
748 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
749 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
752 * These are the definitions for the Line Status Register
754 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
755 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
756 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
757 #define UART_LSR_FE 0x08 /* Frame error indicator */
758 #define UART_LSR_PE 0x04 /* Parity error indicator */
759 #define UART_LSR_OE 0x02 /* Overrun error indicator */
760 #define UART_LSR_DR 0x01 /* Receiver data ready */
763 * These are the definitions for the Interrupt Identification Register
765 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
766 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
767 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
768 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
769 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
770 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
773 * These are the definitions for the Interrupt Enable Register
775 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
776 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
777 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
778 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
781 * These are the definitions for the Modem Control Register
783 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
784 #define UART_MCR_OUT2 0x08 /* Out2 complement */
785 #define UART_MCR_OUT1 0x04 /* Out1 complement */
786 #define UART_MCR_RTS 0x02 /* RTS complement */
787 #define UART_MCR_DTR 0x01 /* DTR complement */
790 * These are the definitions for the Modem Status Register
792 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
793 #define UART_MSR_RI 0x40 /* Ring Indicator */
794 #define UART_MSR_DSR 0x20 /* Data Set Ready */
795 #define UART_MSR_CTS 0x10 /* Clear to Send */
796 #define UART_MSR_DDCD 0x08 /* Delta DCD */
797 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
798 #define UART_MSR_DDSR 0x02 /* Delta DSR */
799 #define UART_MSR_DCTS 0x01 /* Delta CTS */
800 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
805 #define SSI0_STATUS 0xB1600000
806 #define SSI_STATUS_BF (1<<4)
807 #define SSI_STATUS_OF (1<<3)
808 #define SSI_STATUS_UF (1<<2)
809 #define SSI_STATUS_D (1<<1)
810 #define SSI_STATUS_B (1<<0)
811 #define SSI0_INT 0xB1600004
812 #define SSI_INT_OI (1<<3)
813 #define SSI_INT_UI (1<<2)
814 #define SSI_INT_DI (1<<1)
815 #define SSI0_INT_ENABLE 0xB1600008
816 #define SSI_INTE_OIE (1<<3)
817 #define SSI_INTE_UIE (1<<2)
818 #define SSI_INTE_DIE (1<<1)
819 #define SSI0_CONFIG 0xB1600020
820 #define SSI_CONFIG_AO (1<<24)
821 #define SSI_CONFIG_DO (1<<23)
822 #define SSI_CONFIG_ALEN_BIT 20
823 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
824 #define SSI_CONFIG_DLEN_BIT 16
825 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
826 #define SSI_CONFIG_DD (1<<11)
827 #define SSI_CONFIG_AD (1<<10)
828 #define SSI_CONFIG_BM_BIT 8
829 #define SSI_CONFIG_BM_MASK (0x3<<8)
830 #define SSI_CONFIG_CE (1<<7)
831 #define SSI_CONFIG_DP (1<<6)
832 #define SSI_CONFIG_DL (1<<5)
833 #define SSI_CONFIG_EP (1<<4)
834 #define SSI0_ADATA 0xB1600024
835 #define SSI_AD_D (1<<24)
836 #define SSI_AD_ADDR_BIT 16
837 #define SSI_AD_ADDR_MASK (0xff<<16)
838 #define SSI_AD_DATA_BIT 0
839 #define SSI_AD_DATA_MASK (0xfff<<0)
840 #define SSI0_CLKDIV 0xB1600028
841 #define SSI0_CONTROL 0xB1600100
842 #define SSI_CONTROL_CD (1<<1)
843 #define SSI_CONTROL_E (1<<0)
846 #define SSI1_STATUS 0xB1680000
847 #define SSI1_INT 0xB1680004
848 #define SSI1_INT_ENABLE 0xB1680008
849 #define SSI1_CONFIG 0xB1680020
850 #define SSI1_ADATA 0xB1680024
851 #define SSI1_CLKDIV 0xB1680028
852 #define SSI1_ENABLE 0xB1680100
855 * Register content definitions
857 #define SSI_STATUS_BF (1<<4)
858 #define SSI_STATUS_OF (1<<3)
859 #define SSI_STATUS_UF (1<<2)
860 #define SSI_STATUS_D (1<<1)
861 #define SSI_STATUS_B (1<<0)
864 #define SSI_INT_OI (1<<3)
865 #define SSI_INT_UI (1<<2)
866 #define SSI_INT_DI (1<<1)
869 #define SSI_INTEN_OIE (1<<3)
870 #define SSI_INTEN_UIE (1<<2)
871 #define SSI_INTEN_DIE (1<<1)
873 #define SSI_CONFIG_AO (1<<24)
874 #define SSI_CONFIG_DO (1<<23)
875 #define SSI_CONFIG_ALEN (7<<20)
876 #define SSI_CONFIG_DLEN (15<<16)
877 #define SSI_CONFIG_DD (1<<11)
878 #define SSI_CONFIG_AD (1<<10)
879 #define SSI_CONFIG_BM (3<<8)
880 #define SSI_CONFIG_CE (1<<7)
881 #define SSI_CONFIG_DP (1<<6)
882 #define SSI_CONFIG_DL (1<<5)
883 #define SSI_CONFIG_EP (1<<4)
884 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
885 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
886 #define SSI_CONFIG_BM_HI (0<<8)
887 #define SSI_CONFIG_BM_LO (1<<8)
888 #define SSI_CONFIG_BM_CY (2<<8)
890 #define SSI_ADATA_D (1<<24)
891 #define SSI_ADATA_ADDR (0xFF<<16)
892 #define SSI_ADATA_DATA (0x0FFF)
893 #define SSI_ADATA_ADDR_N(N) (N<<16)
895 #define SSI_ENABLE_CD (1<<1)
896 #define SSI_ENABLE_E (1<<0)
899 /* IrDA Controller */
900 #define IRDA_BASE 0xB0300000
901 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
902 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
903 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
904 #define IR_RING_SIZE (IRDA_BASE+0x0C)
905 #define IR_RING_PROMPT (IRDA_BASE+0x10)
906 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
907 #define IR_INT_CLEAR (IRDA_BASE+0x18)
908 #define IR_CONFIG_1 (IRDA_BASE+0x20)
909 #define IR_RX_INVERT_LED (1<<0)
910 #define IR_TX_INVERT_LED (1<<1)
913 #define IR_SIR (1<<4)
914 #define IR_MIR (1<<5)
915 #define IR_FIR (1<<6)
916 #define IR_16CRC (1<<7)
918 #define IR_RX_ALL (1<<9)
919 #define IR_DMA_ENABLE (1<<10)
920 #define IR_RX_ENABLE (1<<11)
921 #define IR_TX_ENABLE (1<<12)
922 #define IR_LOOPBACK (1<<14)
923 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
924 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
925 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
926 #define IR_ENABLE (IRDA_BASE+0x28)
927 #define IR_RX_STATUS (1<<9)
928 #define IR_TX_STATUS (1<<10)
929 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
930 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
931 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
932 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
933 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
934 #define IR_MODE_INV (1<<0)
935 #define IR_ONE_PIN (1<<1)
936 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
939 #define SYS_PINFUNC 0xB190002C
940 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
941 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
942 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
943 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
944 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
945 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
946 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
947 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
948 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
949 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
950 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
951 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
952 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
953 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
954 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
955 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
958 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
959 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
960 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
961 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */
963 /* Au1550 Only. Redefines lots of pins */
964 #define SYS_PF_PSC2_MASK (7 << 17)
965 #define SYS_PF_PSC2_AC97 (0)
966 #define SYS_PF_PSC2_SPI (0)
967 #define SYS_PF_PSC2_I2S (1 << 17)
968 #define SYS_PF_PSC2_SMBUS (3 << 17)
969 #define SYS_PF_PSC2_GPIO (7 << 17)
970 #define SYS_PF_PSC3_MASK (7 << 20)
971 #define SYS_PF_PSC3_AC97 (0)
972 #define SYS_PF_PSC3_SPI (0)
973 #define SYS_PF_PSC3_I2S (1 << 20)
974 #define SYS_PF_PSC3_SMBUS (3 << 20)
975 #define SYS_PF_PSC3_GPIO (7 << 20)
976 #define SYS_PF_PSC1_S1 (1 << 1)
977 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
980 #define SYS_TRIOUTRD 0xB1900100
981 #define SYS_TRIOUTCLR 0xB1900100
982 #define SYS_OUTPUTRD 0xB1900108
983 #define SYS_OUTPUTSET 0xB1900108
984 #define SYS_OUTPUTCLR 0xB190010C
985 #define SYS_PINSTATERD 0xB1900110
986 #define SYS_PININPUTEN 0xB1900110
988 /* GPIO2, Au1500, Au1550 only */
989 #define GPIO2_BASE 0xB1700000
990 #define GPIO2_DIR (GPIO2_BASE + 0)
991 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
992 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
993 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
994 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
996 /* Power Management */
997 #define SYS_SCRATCH0 0xB1900018
998 #define SYS_SCRATCH1 0xB190001C
999 #define SYS_WAKEMSK 0xB1900034
1000 #define SYS_ENDIAN 0xB1900038
1001 #define SYS_POWERCTRL 0xB190003C
1002 #define SYS_WAKESRC 0xB190005C
1003 #define SYS_SLPPWR 0xB1900078
1004 #define SYS_SLEEP 0xB190007C
1006 /* Clock Controller */
1007 #define SYS_FREQCTRL0 0xB1900020
1008 #define SYS_FC_FRDIV2_BIT 22
1009 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1010 #define SYS_FC_FE2 (1<<21)
1011 #define SYS_FC_FS2 (1<<20)
1012 #define SYS_FC_FRDIV1_BIT 12
1013 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1014 #define SYS_FC_FE1 (1<<11)
1015 #define SYS_FC_FS1 (1<<10)
1016 #define SYS_FC_FRDIV0_BIT 2
1017 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1018 #define SYS_FC_FE0 (1<<1)
1019 #define SYS_FC_FS0 (1<<0)
1020 #define SYS_FREQCTRL1 0xB1900024
1021 #define SYS_FC_FRDIV5_BIT 22
1022 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1023 #define SYS_FC_FE5 (1<<21)
1024 #define SYS_FC_FS5 (1<<20)
1025 #define SYS_FC_FRDIV4_BIT 12
1026 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1027 #define SYS_FC_FE4 (1<<11)
1028 #define SYS_FC_FS4 (1<<10)
1029 #define SYS_FC_FRDIV3_BIT 2
1030 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1031 #define SYS_FC_FE3 (1<<1)
1032 #define SYS_FC_FS3 (1<<0)
1033 #define SYS_CLKSRC 0xB1900028
1034 #define SYS_CS_ME1_BIT 27
1035 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1036 #define SYS_CS_DE1 (1<<26)
1037 #define SYS_CS_CE1 (1<<25)
1038 #define SYS_CS_ME0_BIT 22
1039 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1040 #define SYS_CS_DE0 (1<<21)
1041 #define SYS_CS_CE0 (1<<20)
1042 #define SYS_CS_MI2_BIT 17
1043 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1044 #define SYS_CS_DI2 (1<<16)
1045 #define SYS_CS_CI2 (1<<15)
1046 #define SYS_CS_MUH_BIT 12
1047 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1048 #define SYS_CS_DUH (1<<11)
1049 #define SYS_CS_CUH (1<<10)
1050 #define SYS_CS_MUD_BIT 7
1051 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1052 #define SYS_CS_DUD (1<<6)
1053 #define SYS_CS_CUD (1<<5)
1054 #define SYS_CS_MIR_BIT 2
1055 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1056 #define SYS_CS_DIR (1<<1)
1057 #define SYS_CS_CIR (1<<0)
1059 #define SYS_CS_MUX_AUX 0x1
1060 #define SYS_CS_MUX_FQ0 0x2
1061 #define SYS_CS_MUX_FQ1 0x3
1062 #define SYS_CS_MUX_FQ2 0x4
1063 #define SYS_CS_MUX_FQ3 0x5
1064 #define SYS_CS_MUX_FQ4 0x6
1065 #define SYS_CS_MUX_FQ5 0x7
1066 #define SYS_CPUPLL 0xB1900060
1067 #define SYS_AUXPLL 0xB1900064
1069 /* AC97 Controller */
1070 #define AC97C_CONFIG 0xB0000000
1071 #define AC97C_RECV_SLOTS_BIT 13
1072 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1073 #define AC97C_XMIT_SLOTS_BIT 3
1074 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1075 #define AC97C_SG (1<<2)
1076 #define AC97C_SYNC (1<<1)
1077 #define AC97C_RESET (1<<0)
1078 #define AC97C_STATUS 0xB0000004
1079 #define AC97C_XU (1<<11)
1080 #define AC97C_XO (1<<10)
1081 #define AC97C_RU (1<<9)
1082 #define AC97C_RO (1<<8)
1083 #define AC97C_READY (1<<7)
1084 #define AC97C_CP (1<<6)
1085 #define AC97C_TR (1<<5)
1086 #define AC97C_TE (1<<4)
1087 #define AC97C_TF (1<<3)
1088 #define AC97C_RR (1<<2)
1089 #define AC97C_RE (1<<1)
1090 #define AC97C_RF (1<<0)
1091 #define AC97C_DATA 0xB0000008
1092 #define AC97C_CMD 0xB000000C
1093 #define AC97C_WD_BIT 16
1094 #define AC97C_READ (1<<7)
1095 #define AC97C_INDEX_MASK 0x7f
1096 #define AC97C_CNTRL 0xB0000010
1097 #define AC97C_RS (1<<1)
1098 #define AC97C_CE (1<<0)
1101 /* Secure Digital (SD) Controller */
1102 #define SD0_XMIT_FIFO 0xB0600000
1103 #define SD0_RECV_FIFO 0xB0600004
1104 #define SD1_XMIT_FIFO 0xB0680000
1105 #define SD1_RECV_FIFO 0xB0680004
1108 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1109 /* Au1500 PCI Controller */
1110 #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1111 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1112 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1113 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1114 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1115 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1116 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1117 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1118 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1119 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1120 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1121 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1122 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1123 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1124 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1125 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1127 #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
1129 /* All of our structures, like pci resource, have 32 bit members.
1130 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1131 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1132 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1133 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1134 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1135 * ourselves and then adjust the device's resources.
1137 #define Au1500_EXT_CFG 0x600000000
1138 #define Au1500_EXT_CFG_TYPE1 0x680000000
1139 #define Au1500_PCI_IO_START 0x500000000
1140 #define Au1500_PCI_IO_END 0x5000FFFFF
1141 #define Au1500_PCI_MEM_START 0x440000000
1142 #define Au1500_PCI_MEM_END 0x44FFFFFFF
1144 #define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
1145 #define PCI_IO_END (Au1500_PCI_IO_END)
1146 #define PCI_MEM_START (Au1500_PCI_MEM_START)
1147 #define PCI_MEM_END (Au1500_PCI_MEM_END)
1148 #define PCI_FIRST_DEVFN (0<<3)
1149 #define PCI_LAST_DEVFN (19<<3)
1151 #define IOPORT_RESOURCE_START 0x00000000
1152 #define IOPORT_RESOURCE_END 0xffffffff
1153 #define IOMEM_RESOURCE_START 0x10000000
1154 #define IOMEM_RESOURCE_END 0xffffffff
1157 * Borrowed from the PPC arch:
1158 * The following macro is used to lookup irqs in a standard table
1159 * format for those PPC systems that do not already have PCI
1160 * interrupts properly routed.
1162 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1163 #define PCI_IRQ_TABLE_LOOKUP \
1164 ({ long _ctl_ = -1; \
1165 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1166 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1170 #else /* Au1000 and Au1100 */
1172 /* don't allow any legacy ports probing */
1173 #define IOPORT_RESOURCE_START 0x10000000;
1174 #define IOPORT_RESOURCE_END 0xffffffff
1175 #define IOMEM_RESOURCE_START 0x10000000
1176 #define IOMEM_RESOURCE_END 0xffffffff
1178 #ifdef CONFIG_MIPS_PB1000
1179 #define PCI_IO_START 0x10000000
1180 #define PCI_IO_END 0x1000ffff
1181 #define PCI_MEM_START 0x18000000
1182 #define PCI_MEM_END 0x18ffffff
1183 #define PCI_FIRST_DEVFN 0
1184 #define PCI_LAST_DEVFN 1
1186 /* no PCI bus controller */
1187 #define PCI_IO_START 0
1188 #define PCI_IO_END 0
1189 #define PCI_MEM_START 0
1190 #define PCI_MEM_END 0
1191 #define PCI_FIRST_DEVFN 0
1192 #define PCI_LAST_DEVFN 0
1197 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1198 #define NUM_ETH_INTERFACES 2
1199 #elif defined(CONFIG_SOC_AU1100)
1200 #define NUM_ETH_INTERFACES 1