include/asm-mips/sibyte/bcm1480_scd.h

   1 /*  *********************************************************************
   2     *  BCM1280/BCM1400 Board Support Package
   3     *
   4     *  SCD Constants and Macros                     File: bcm1480_scd.h
   5     *
   6     *  This module contains constants and macros useful for
   7     *  manipulating the System Control and Debug module.
   8     *
   9     *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This program is free software; you can redistribute it and/or
  17     *  modify it under the terms of the GNU General Public License as
  18     *  published by the Free Software Foundation; either version 2 of
  19     *  the License, or (at your option) any later version.
  20     *
  21     *  This program is distributed in the hope that it will be useful,
  22     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  23     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24     *  GNU General Public License for more details.
  25     *
  26     *  You should have received a copy of the GNU General Public License
  27     *  along with this program; if not, write to the Free Software
  28     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29     *  MA 02111-1307 USA
  30     ********************************************************************* */
  31
  32 #ifndef _BCM1480_SCD_H
  33 #define _BCM1480_SCD_H
  34
  35 #include "sb1250_defs.h"
  36
  37 /*  *********************************************************************
  38     *  Pull in the BCM1250's SCD since lots of stuff is the same.
  39     ********************************************************************* */
  40
  41 #include "sb1250_scd.h"
  42
  43 /*  *********************************************************************
  44     *  Some general notes:
  45     *
  46     *  This file is basically a "what's new" header file.  Since the
  47     *  BCM1250 and the new BCM1480 (and derivatives) share many common
  48     *  features, this file contains only what's new or changed from
  49     *  the 1250.  (above, you can see that we include the 1250 symbols
  50     *  to get the base functionality).
  51     *
  52     *  In software, be sure to use the correct symbols, particularly
  53     *  for blocks that are different between the two chip families.
  54     *  All BCM1480-specific symbols have _BCM1480_ in their names,
  55     *  and all BCM1250-specific and "base" functions that are common in
  56     *  both chips have no special names (this is for compatibility with
  57     *  older include files).  Therefore, if you're working with the
  58     *  SCD, which is very different on each chip, A_SCD_xxx implies
  59     *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
  60     *  version.
  61     ********************************************************************* */
  62
  63 /*  *********************************************************************
  64     *  System control/debug registers
  65     ********************************************************************* */
  66
  67 /*
  68  * System Identification and Revision Register (Table 12)
  69  * Register: SCD_SYSTEM_REVISION
  70  * This register is field compatible with the 1250.
  71  */
  72
  73 /*
  74  * New part definitions
  75  */
  76
  77 #define K_SYS_PART_BCM1480          0x1406
  78 #define K_SYS_PART_BCM1280          0x1206
  79 #define K_SYS_PART_BCM1455          0x1407
  80 #define K_SYS_PART_BCM1255          0x1257
  81
  82 /*
  83  * Manufacturing Information Register (Table 14)
  84  * Register: SCD_SYSTEM_MANUF
  85  */
  86
  87 /*
  88  * System Configuration Register (Table 15)
  89  * Register: SCD_SYSTEM_CFG
  90  * Entire register is different from 1250, all new constants below
  91  */
  92
  93 #define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
  94 #define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
  95 #define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
  96 #define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
  97 #define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
  98 #define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
  99
 100 #define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
 101 #define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV)
 102 #define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV)
 103 #define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV)
 104
 105 #define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
 106 #define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV)
 107 #define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV)
 108 #define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV)
 109
 110 #define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
 111 #define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
 112
 113 #define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
 114 #define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE)
 115 #define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE)
 116 #define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE)
 117 #define K_BCM1480_SYS_BOOT_MODE_ROM32       0
 118 #define K_BCM1480_SYS_BOOT_MODE_ROM8        1
 119 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
 120 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
 121 #define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
 122
 123 #define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
 124 #define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
 125 #define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
 126 #define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
 127 #define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
 128 #define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
 129
 130 #define S_BCM1480_SYS_CONFIG                26
 131 #define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG)
 132 #define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG)
 133 #define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG)
 134
 135 #define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32,15)
 136
 137 #define S_BCM1480_SYS_NODEID                47
 138 #define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID)
 139 #define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID)
 140 #define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID)
 141
 142 #define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
 143 #define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
 144 #define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
 145 #define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
 146 #define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
 147 #define S_BCM1480_SYS_DISABLECPU0           56
 148 #define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
 149 #define S_BCM1480_SYS_DISABLECPU1           57
 150 #define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
 151 #define S_BCM1480_SYS_DISABLECPU2           58
 152 #define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
 153 #define S_BCM1480_SYS_DISABLECPU3           59
 154 #define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
 155
 156 #define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
 157 #define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
 158 #define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
 159 #define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
 160
 161 /*
 162  * Scratch Register (Table 16)
 163  * Register: SCD_SYSTEM_SCRATCH
 164  * Same as BCM1250
 165  */
 166
 167
 168 /*
 169  * Mailbox Registers (Table 17)
 170  * Registers: SCD_MBOX_{0,1}_CPU_x
 171  * Same as BCM1250
 172  */
 173
 174
 175 /*
 176  * See bcm1480_int.h for interrupt mapper registers.
 177  */
 178
 179
 180 /*
 181  * Watchdog Timer Initial Count Registers (Table 23)
 182  * Registers: SCD_WDOG_INIT_CNT_x
 183  *
 184  * The watchdogs are almost the same as the 1250, except
 185  * the configuration register has more bits to control the
 186  * other CPUs.
 187  */
 188
 189
 190 /*
 191  * Watchdog Timer Configuration Registers (Table 25)
 192  * Registers: SCD_WDOG_CFG_x
 193  */
 194
 195 #define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
 196
 197 #define S_BCM1480_SCD_WDOG_RESET_TYPE       2
 198 #define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE)
 199 #define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE)
 200 #define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE)
 201
 202 #define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
 203 #define K_BCM1480_SCD_WDOG_RESET_SOFT       1
 204 #define K_BCM1480_SCD_WDOG_RESET_CPU0       3
 205 #define K_BCM1480_SCD_WDOG_RESET_CPU1       5
 206 #define K_BCM1480_SCD_WDOG_RESET_CPU2       9
 207 #define K_BCM1480_SCD_WDOG_RESET_CPU3       17
 208 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
 209
 210
 211 #define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
 212
 213 /*
 214  * General Timer Initial Count Registers (Table 26)
 215  * Registers: SCD_TIMER_INIT_x
 216  *
 217  * The timer registers are the same as the BCM1250
 218  */
 219
 220
 221 /*
 222  * ZBbus Count Register (Table 29)
 223  * Register: ZBBUS_CYCLE_COUNT
 224  *
 225  * Same as BCM1250
 226  */
 227
 228 /*
 229  * ZBbus Compare Registers (Table 30)
 230  * Registers: ZBBUS_CYCLE_CPx
 231  *
 232  * Same as BCM1250
 233  */
 234
 235
 236 /*
 237  * System Performance Counter Configuration Register (Table 31)
 238  * Register: PERF_CNT_CFG_0
 239  *
 240  * Since the clear/enable bits are moved compared to the
 241  * 1250 and there are more fields, this register will be BCM1480 specific.
 242  */
 243
 244 #define S_BCM1480_SPC_CFG_SRC0              0
 245 #define M_BCM1480_SPC_CFG_SRC0              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0)
 246 #define V_BCM1480_SPC_CFG_SRC0(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0)
 247 #define G_BCM1480_SPC_CFG_SRC0(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0)
 248
 249 #define S_BCM1480_SPC_CFG_SRC1              8
 250 #define M_BCM1480_SPC_CFG_SRC1              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1)
 251 #define V_BCM1480_SPC_CFG_SRC1(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1)
 252 #define G_BCM1480_SPC_CFG_SRC1(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1)
 253
 254 #define S_BCM1480_SPC_CFG_SRC2              16
 255 #define M_BCM1480_SPC_CFG_SRC2              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2)
 256 #define V_BCM1480_SPC_CFG_SRC2(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2)
 257 #define G_BCM1480_SPC_CFG_SRC2(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2)
 258
 259 #define S_BCM1480_SPC_CFG_SRC3              24
 260 #define M_BCM1480_SPC_CFG_SRC3              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3)
 261 #define V_BCM1480_SPC_CFG_SRC3(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3)
 262 #define G_BCM1480_SPC_CFG_SRC3(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3)
 263
 264 #define S_BCM1480_SPC_CFG_SRC4              32
 265 #define M_BCM1480_SPC_CFG_SRC4              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
 266 #define V_BCM1480_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
 267 #define G_BCM1480_SPC_CFG_SRC4(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
 268
 269 #define S_BCM1480_SPC_CFG_SRC5              40
 270 #define M_BCM1480_SPC_CFG_SRC5              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
 271 #define V_BCM1480_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
 272 #define G_BCM1480_SPC_CFG_SRC5(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
 273
 274 #define S_BCM1480_SPC_CFG_SRC6              48
 275 #define M_BCM1480_SPC_CFG_SRC6              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
 276 #define V_BCM1480_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
 277 #define G_BCM1480_SPC_CFG_SRC6(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
 278
 279 #define S_BCM1480_SPC_CFG_SRC7              56
 280 #define M_BCM1480_SPC_CFG_SRC7              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
 281 #define V_BCM1480_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
 282 #define G_BCM1480_SPC_CFG_SRC7(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
 283
 284 /*
 285  * System Performance Counter Control Register (Table 32)
 286  * Register: PERF_CNT_CFG_1
 287  * BCM1480 specific
 288  */
 289
 290 #define M_BCM1480_SPC_CFG_CLEAR             _SB_MAKEMASK1(0)
 291 #define M_BCM1480_SPC_CFG_ENABLE            _SB_MAKEMASK1(1)
 292
 293 /*
 294  * System Performance Counters (Table 33)
 295  * Registers: PERF_CNT_x
 296  */
 297
 298 #define S_BCM1480_SPC_CNT_COUNT             0
 299 #define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT)
 300 #define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT)
 301 #define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT)
 302
 303 #define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
 304
 305
 306 /*
 307  * Bus Watcher Error Status Register (Tables 36, 37)
 308  * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
 309  * Same as BCM1250.
 310  */
 311
 312 /*
 313  * Bus Watcher Error Data Registers (Table 38)
 314  * Registers: BUS_ERR_DATA_x
 315  * Same as BCM1250.
 316  */
 317
 318 /*
 319  * Bus Watcher L2 ECC Counter Register (Table 39)
 320  * Register: BUS_L2_ERRORS
 321  * Same as BCM1250.
 322  */
 323
 324
 325 /*
 326  * Bus Watcher Memory and I/O Error Counter Register (Table 40)
 327  * Register: BUS_MEM_IO_ERRORS
 328  * Same as BCM1250.
 329  */
 330
 331
 332 /*
 333  * Address Trap Registers
 334  *
 335  * Register layout same as BCM1250, almost.  The bus agents
 336  * are different, and the address trap configuration bits are
 337  * slightly different.
 338  */
 339
 340 #define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4,0)
 341 #define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40,0)
 342
 343 #define S_BCM1480_ATRAP_CFG_CNT            0
 344 #define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT)
 345 #define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT)
 346 #define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT)
 347
 348 #define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
 349 #define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
 350 #define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
 351 #define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
 352 #define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
 353
 354 #define S_BCM1480_ATRAP_CFG_AGENTID     8
 355 #define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID)
 356 #define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID)
 357 #define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID)
 358
 359
 360 #define K_BCM1480_BUS_AGENT_CPU0            0
 361 #define K_BCM1480_BUS_AGENT_CPU1            1
 362 #define K_BCM1480_BUS_AGENT_NC              2
 363 #define K_BCM1480_BUS_AGENT_IOB             3
 364 #define K_BCM1480_BUS_AGENT_SCD             4
 365 #define K_BCM1480_BUS_AGENT_L2C             6
 366 #define K_BCM1480_BUS_AGENT_MC              7
 367 #define K_BCM1480_BUS_AGENT_CPU2            8
 368 #define K_BCM1480_BUS_AGENT_CPU3            9
 369 #define K_BCM1480_BUS_AGENT_PM              10
 370
 371 #define S_BCM1480_ATRAP_CFG_CATTR           12
 372 #define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR)
 373 #define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR)
 374 #define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR)
 375
 376 #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
 377 #define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
 378 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
 379 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
 380
 381 #define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
 382
 383
 384 /*
 385  * Trace Event Registers (Table 47)
 386  * Same as BCM1250.
 387  */
 388
 389 /*
 390  * Trace Sequence Control Registers (Table 48)
 391  * Registers: TRACE_SEQUENCE_x
 392  *
 393  * Same as BCM1250 except for two new fields.
 394  */
 395
 396
 397 #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
 398
 399 #define S_BCM1480_SCD_TRSEQ_SWFUNC          26
 400 #define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC)
 401 #define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC)
 402 #define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC)
 403
 404 /*
 405  * Trace Control Register (Table 49)
 406  * Register: TRACE_CFG
 407  *
 408  * Bits 0..8 are the same as the BCM1250, rest are different.
 409  * Entire register is redefined below.
 410  */
 411
 412 #define M_BCM1480_SCD_TRACE_CFG_RESET       _SB_MAKEMASK1(0)
 413 #define M_BCM1480_SCD_TRACE_CFG_START_READ  _SB_MAKEMASK1(1)
 414 #define M_BCM1480_SCD_TRACE_CFG_START       _SB_MAKEMASK1(2)
 415 #define M_BCM1480_SCD_TRACE_CFG_STOP        _SB_MAKEMASK1(3)
 416 #define M_BCM1480_SCD_TRACE_CFG_FREEZE      _SB_MAKEMASK1(4)
 417 #define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
 418 #define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL  _SB_MAKEMASK1(6)
 419 #define M_BCM1480_SCD_TRACE_CFG_FULL        _SB_MAKEMASK1(7)
 420 #define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT   _SB_MAKEMASK1(8)
 421
 422 #define S_BCM1480_SCD_TRACE_CFG_MODE        16
 423 #define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
 424 #define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
 425 #define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE)
 426
 427 #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
 428 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
 429 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
 430
 431 #define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR    24
 432 #define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR    _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
 433 #define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
 434 #define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
 435
 436 #endif /* _BCM1480_SCD_H */