include/asm-mips/vr41xx/eagle.h

   1 /*
   2  * FILE NAME
   3  *      include/asm-mips/vr41xx/eagle.h
   4  *
   5  * BRIEF MODULE DESCRIPTION
   6  *      Include file for NEC Eagle board.
   7  *
   8  * Author: MontaVista Software, Inc.
   9  *         yyuasa@mvista.com or source@mvista.com
  10  *
  11  * Copyright 2001-2003 MontaVista Software Inc.
  12  *
  13  *  This program is free software; you can redistribute it and/or modify it
  14  *  under the terms of the GNU General Public License as published by the
  15  *  Free Software Foundation; either version 2 of the License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  26  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  27  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the GNU General Public License along
  30  *  with this program; if not, write to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  */
  33 #ifndef __NEC_EAGLE_H
  34 #define __NEC_EAGLE_H
  35
  36 #include <asm/addrspace.h>
  37 #include <asm/vr41xx/vr41xx.h>
  38
  39 /*
  40  * Board specific address mapping
  41  */
  42 #define VR41XX_PCI_MEM1_BASE            0x10000000
  43 #define VR41XX_PCI_MEM1_SIZE            0x04000000
  44 #define VR41XX_PCI_MEM1_MASK            0x7c000000
  45
  46 #define VR41XX_PCI_MEM2_BASE            0x14000000
  47 #define VR41XX_PCI_MEM2_SIZE            0x02000000
  48 #define VR41XX_PCI_MEM2_MASK            0x7e000000
  49
  50 #define VR41XX_PCI_IO_BASE              0x16000000
  51 #define VR41XX_PCI_IO_SIZE              0x02000000
  52 #define VR41XX_PCI_IO_MASK              0x7e000000
  53
  54 #define VR41XX_PCI_IO_START             0x01000000
  55 #define VR41XX_PCI_IO_END               0x01ffffff
  56
  57 #define VR41XX_PCI_MEM_START            0x12000000
  58 #define VR41XX_PCI_MEM_END              0x15ffffff
  59
  60 #define IO_PORT_BASE                    KSEG1ADDR(VR41XX_PCI_IO_BASE)
  61 #define IO_PORT_RESOURCE_START          0
  62 #define IO_PORT_RESOURCE_END            VR41XX_PCI_IO_SIZE
  63 #define IO_MEM1_RESOURCE_START          VR41XX_PCI_MEM1_BASE
  64 #define IO_MEM1_RESOURCE_END            (VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE)
  65 #define IO_MEM2_RESOURCE_START          VR41XX_PCI_MEM2_BASE
  66 #define IO_MEM2_RESOURCE_END            (VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE)
  67
  68 /*
  69  * General-Purpose I/O Pin Number
  70  */
  71 #define VRC4173_PIN                     1
  72 #define PCISLOT_PIN                     4
  73 #define FPGA_PIN                        5
  74 #define DCD_PIN                         15
  75
  76 /*
  77  * Interrupt Number
  78  */
  79 #define VRC4173_CASCADE_IRQ             GIU_IRQ(VRC4173_PIN)
  80 #define PCISLOT_IRQ                     GIU_IRQ(PCISLOT_PIN)
  81 #define FPGA_CASCADE_IRQ                GIU_IRQ(FPGA_PIN)
  82 #define DCD_IRQ                         GIU_IRQ(DCD_PIN)
  83
  84 #define SDBINT_IRQ_BASE                 88
  85 #define SDBINT_IRQ(x)                   (SDBINT_IRQ_BASE + (x))
  86 /* RFU */
  87 #define DEG_IRQ                         SDBINT_IRQ(1)
  88 #define ENUM_IRQ                        SDBINT_IRQ(2)
  89 #define SIO1INT_IRQ                     SDBINT_IRQ(3)
  90 #define SIO2INT_IRQ                     SDBINT_IRQ(4)
  91 #define PARINT_IRQ                      SDBINT_IRQ(5)
  92 #define SDBINT_IRQ_LAST                 PARINT_IRQ
  93
  94 #define PCIINT_IRQ_BASE                 96
  95 #define PCIINT_IRQ(x)                   (PCIINT_IRQ_BASE + (x))
  96 #define CP_INTA_IRQ                     PCIINT_IRQ(0)
  97 #define CP_INTB_IRQ                     PCIINT_IRQ(1)
  98 #define CP_INTC_IRQ                     PCIINT_IRQ(2)
  99 #define CP_INTD_IRQ                     PCIINT_IRQ(3)
 100 #define LANINTA_IRQ                     PCIINT_IRQ(4)
 101 #define PCIINT_IRQ_LAST                 LANINTA_IRQ
 102
 103 /*
 104  * On board Devices I/O Mapping
 105  */
 106 #define NEC_EAGLE_SIO1RB                KSEG1ADDR(0x0DFFFEC0)
 107 #define NEC_EAGLE_SIO1TH                KSEG1ADDR(0x0DFFFEC0)
 108 #define NEC_EAGLE_SIO1IE                KSEG1ADDR(0x0DFFFEC2)
 109 #define NEC_EAGLE_SIO1IID               KSEG1ADDR(0x0DFFFEC4)
 110 #define NEC_EAGLE_SIO1FC                KSEG1ADDR(0x0DFFFEC4)
 111 #define NEC_EAGLE_SIO1LC                KSEG1ADDR(0x0DFFFEC6)
 112 #define NEC_EAGLE_SIO1MC                KSEG1ADDR(0x0DFFFEC8)
 113 #define NEC_EAGLE_SIO1LS                KSEG1ADDR(0x0DFFFECA)
 114 #define NEC_EAGLE_SIO1MS                KSEG1ADDR(0x0DFFFECC)
 115 #define NEC_EAGLE_SIO1SC                KSEG1ADDR(0x0DFFFECE)
 116
 117 #define NEC_EAGLE_SIO2TH                KSEG1ADDR(0x0DFFFED0)
 118 #define NEC_EAGLE_SIO2IE                KSEG1ADDR(0x0DFFFED2)
 119 #define NEC_EAGLE_SIO2IID               KSEG1ADDR(0x0DFFFED4)
 120 #define NEC_EAGLE_SIO2FC                KSEG1ADDR(0x0DFFFED4)
 121 #define NEC_EAGLE_SIO2LC                KSEG1ADDR(0x0DFFFED6)
 122 #define NEC_EAGLE_SIO2MC                KSEG1ADDR(0x0DFFFED8)
 123 #define NEC_EAGLE_SIO2LS                KSEG1ADDR(0x0DFFFEDA)
 124 #define NEC_EAGLE_SIO2MS                KSEG1ADDR(0x0DFFFEDC)
 125 #define NEC_EAGLE_SIO2SC                KSEG1ADDR(0x0DFFFEDE)
 126
 127 #define NEC_EAGLE_PIOPP_DATA            KSEG1ADDR(0x0DFFFEE0)
 128 #define NEC_EAGLE_PIOPP_STATUS          KSEG1ADDR(0x0DFFFEE2)
 129 #define NEC_EAGLE_PIOPP_CNT             KSEG1ADDR(0x0DFFFEE4)
 130 #define NEC_EAGLE_PIOPP_EPPADDR         KSEG1ADDR(0x0DFFFEE6)
 131 #define NEC_EAGLE_PIOPP_EPPDATA0        KSEG1ADDR(0x0DFFFEE8)
 132 #define NEC_EAGLE_PIOPP_EPPDATA1        KSEG1ADDR(0x0DFFFEEA)
 133 #define NEC_EAGLE_PIOPP_EPPDATA2        KSEG1ADDR(0x0DFFFEEC)
 134
 135 #define NEC_EAGLE_PIOECP_DATA           KSEG1ADDR(0x0DFFFEF0)
 136 #define NEC_EAGLE_PIOECP_CONFIG         KSEG1ADDR(0x0DFFFEF2)
 137 #define NEC_EAGLE_PIOECP_EXTCNT         KSEG1ADDR(0x0DFFFEF4)
 138
 139 /*
 140  *  FLSHCNT Register
 141  */
 142 #define NEC_EAGLE_FLSHCNT               KSEG1ADDR(0x0DFFFFA0)
 143 #define NEC_EAGLE_FLSHCNT_FRDY          0x80
 144 #define NEC_EAGLE_FLSHCNT_VPPE          0x40
 145 #define NEC_EAGLE_FLSHCNT_WP2           0x01
 146
 147 /*
 148  * FLSHBANK Register
 149  */
 150 #define NEC_EAGLE_FLSHBANK              KSEG1ADDR(0x0DFFFFA4)
 151 #define NEC_EAGLE_FLSHBANK_S_BANK2      0x40
 152 #define NEC_EAGLE_FLSHBANK_S_BANK1      0x20
 153 #define NEC_EAGLE_FLSHBANK_BNKQ4        0x10
 154 #define NEC_EAGLE_FLSHBANK_BNKQ3        0x08
 155 #define NEC_EAGLE_FLSHBANK_BNKQ2        0x04
 156 #define NEC_EAGLE_FLSHBANK_BNKQ1        0x02
 157 #define NEC_EAGLE_FLSHBANK_BNKQ0        0x01
 158
 159 /*
 160  * SWITCH Setting Register
 161  */
 162 #define NEC_EAGLE_SWTCHSET              KSEG1ADDR(0x0DFFFFA8)
 163 #define NEC_EAGLE_SWTCHSET_DP2SW4       0x80
 164 #define NEC_EAGLE_SWTCHSET_DP2SW3       0x40
 165 #define NEC_EAGLE_SWTCHSET_DP2SW2       0x20
 166 #define NEC_EAGLE_SWTCHSET_DP2SW1       0x10
 167 #define NEC_EAGLE_SWTCHSET_DP1SW4       0x08
 168 #define NEC_EAGLE_SWTCHSET_DP1SW3       0x04
 169 #define NEC_EAGLE_SWTCHSET_DP1SW2       0x02
 170 #define NEC_EAGLE_SWTCHSET_DP1SW1       0x01
 171
 172 /*
 173  * PPT Parallel Port Device Controller
 174  */
 175 #define NEC_EAGLE_PPT_WRITE_DATA        KSEG1ADDR(0x0DFFFFB0)
 176 #define NEC_EAGLE_PPT_READ_DATA         KSEG1ADDR(0x0DFFFFB2)
 177 #define NEC_EAGLE_PPT_CNT               KSEG1ADDR(0x0DFFFFB4)
 178 #define NEC_EAGLE_PPT_CNT2              KSEG1ADDR(0x0DFFFFB4)
 179
 180 /* Control Register */
 181 #define NEC_EAGLE_PPT_INTMSK            0x20
 182 #define NEC_EAGLE_PPT_PARIINT           0x10
 183 #define NEC_EAGLE_PPT_SELECTIN          0x08
 184 #define NEC_EAGLE_PPT_INIT              0x04
 185 #define NEC_EAGLE_PPT_AUTOFD            0x02
 186 #define NEC_EAGLE_PPT_STROBE            0x01
 187
 188 /* Control Rgister 2 */
 189 #define NEC_EAGLE_PPT_PAREN             0x80
 190 #define NEC_EAGLE_PPT_AUTOEN            0x20
 191 #define NEC_EAGLE_PPT_BUSY              0x10
 192 #define NEC_EAGLE_PPT_ACK               0x08
 193 #define NEC_EAGLE_PPT_PE                0x04
 194 #define NEC_EAGLE_PPT_SELECT            0x02
 195 #define NEC_EAGLE_PPT_FAULT             0x01
 196
 197 /*
 198  * LEDWR Register
 199  */
 200 #define NEC_EAGLE_LEDWR1                KSEG1ADDR(0x0DFFFFC0)
 201 #define NEC_EAGLE_LEDWR2                KSEG1ADDR(0x0DFFFFC4)
 202
 203 /*
 204  * SDBINT Register
 205  */
 206 #define NEC_EAGLE_SDBINT                KSEG1ADDR(0x0DFFFFD0)
 207 #define NEC_EAGLE_SDBINT_PARINT         0x20
 208 #define NEC_EAGLE_SDBINT_SIO2INT        0x10
 209 #define NEC_EAGLE_SDBINT_SIO1INT        0x08
 210 #define NEC_EAGLE_SDBINT_ENUM           0x04
 211 #define NEC_EAGLE_SDBINT_DEG            0x02
 212
 213 /*
 214  * SDB INTMSK Register
 215  */
 216 #define NEC_EAGLE_SDBINTMSK             KSEG1ADDR(0x0DFFFFD4)
 217 #define NEC_EAGLE_SDBINTMSK_MSKPAR      0x20
 218 #define NEC_EAGLE_SDBINTMSK_MSKSIO2     0x10
 219 #define NEC_EAGLE_SDBINTMSK_MSKSIO1     0x08
 220 #define NEC_EAGLE_SDBINTMSK_MSKENUM     0x04
 221 #define NEC_EAGLE_SDBINTMSK_MSKDEG      0x02
 222
 223 /*
 224  * RSTREG Register
 225  */
 226 #define NEC_EAGLE_RSTREG                KSEG1ADDR(0x0DFFFFD8)
 227 #define NEC_EAGLE_RST_RSTSW             0x02
 228 #define NEC_EAGLE_RST_LEDOFF            0x01
 229
 230 /*
 231  * PCI INT Rgister
 232  */
 233 #define NEC_EAGLE_PCIINTREG             KSEG1ADDR(0x0DFFFFDC)
 234 #define NEC_EAGLE_PCIINT_LANINT         0x10
 235 #define NEC_EAGLE_PCIINT_CP_INTD        0x08
 236 #define NEC_EAGLE_PCIINT_CP_INTC        0x04
 237 #define NEC_EAGLE_PCIINT_CP_INTB        0x02
 238 #define NEC_EAGLE_PCIINT_CP_INTA        0x01
 239
 240 /*
 241  * PCI INT Mask Register
 242  */
 243 #define NEC_EAGLE_PCIINTMSKREG          KSEG1ADDR(0x0DFFFFE0)
 244 #define NEC_EAGLE_PCIINTMSK_MSKLANINT   0x10
 245 #define NEC_EAGLE_PCIINTMSK_MSKCP_INTD  0x08
 246 #define NEC_EAGLE_PCIINTMSK_MSKCP_INTC  0x04
 247 #define NEC_EAGLE_PCIINTMSK_MSKCP_INTB  0x02
 248 #define NEC_EAGLE_PCIINTMSK_MSKCP_INTA  0x01
 249
 250 /*
 251  * CLK Division Register
 252  */
 253 #define NEC_EAGLE_CLKDIV                KSEG1ADDR(0x0DFFFFE4)
 254 #define NEC_EAGLE_CLKDIV_PCIDIV1        0x10
 255 #define NEC_EAGLE_CLKDIV_PCIDIV0        0x08
 256 #define NEC_EAGLE_CLKDIV_VTDIV2         0x04
 257 #define NEC_EAGLE_CLKDIV_VTDIV1         0x02
 258 #define NEC_EAGLE_CLKDIV_VTDIV0         0x01
 259
 260 /*
 261  * Source Revision Register
 262  */
 263 #define NEC_EAGLE_REVISION              KSEG1ADDR(0x0DFFFFE8)
 264
 265 #endif /* __NEC_EAGLE_H */