2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
20 #include <linux/config.h>
21 #include <asm/8xx_immap.h>
23 /* CPM Command register.
25 #define CPM_CR_RST ((ushort)0x8000)
26 #define CPM_CR_OPCODE ((ushort)0x0f00)
27 #define CPM_CR_CHAN ((ushort)0x00f0)
28 #define CPM_CR_FLG ((ushort)0x0001)
30 /* Some commands (there are more...later)
32 #define CPM_CR_INIT_TRX ((ushort)0x0000)
33 #define CPM_CR_INIT_RX ((ushort)0x0001)
34 #define CPM_CR_INIT_TX ((ushort)0x0002)
35 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
36 #define CPM_CR_STOP_TX ((ushort)0x0004)
37 #define CPM_CR_RESTART_TX ((ushort)0x0006)
38 #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
39 #define CPM_CR_SET_GADDR ((ushort)0x0008)
40 #define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
44 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
45 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
46 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
47 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
48 #define CPM_CR_CH_TIMER CPM_CR_CH_SPI
49 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
50 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
51 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
52 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
54 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
56 /* The dual ported RAM is multi-functional. Some areas can be (and are
57 * being) used for microcode. There is an area that can only be used
58 * as data ram for buffer descriptors, which is all we use right now.
59 * Currently the first 512 and last 256 bytes are used for microcode.
61 #define CPM_DATAONLY_BASE ((uint)0x0800)
62 #define CPM_DATAONLY_SIZE ((uint)0x0700)
63 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
65 /* Export the base address of the communication processor registers
68 extern cpm8xx_t *cpmp; /* Pointer to comm processor */
69 uint m8xx_cpm_dpalloc(uint size);
70 uint m8xx_cpm_hostalloc(uint size);
71 void m8xx_cpm_setbrg(uint brg, uint rate);
73 /* Buffer descriptors used by many of the CPM protocols.
75 typedef struct cpm_buf_desc {
76 ushort cbd_sc; /* Status and Control */
77 ushort cbd_datlen; /* Data length in buffer */
78 uint cbd_bufaddr; /* Buffer address in host memory */
81 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
82 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
83 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
84 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
85 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
86 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
87 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
88 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
89 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
90 #define BD_SC_BR ((ushort)0x0020) /* Break received */
91 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
92 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
93 #define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
94 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
95 #define BD_SC_UN ((ushort)0x0002) /* Underrun */
96 #define BD_SC_CD ((ushort)0x0001) /* ?? */
97 #define BD_SC_CL ((ushort)0x0001) /* Collision */
99 /* Parameter RAM offsets.
101 #define PROFF_SCC1 ((uint)0x0000)
102 #define PROFF_IIC ((uint)0x0080)
103 #define PROFF_SCC2 ((uint)0x0100)
104 #define PROFF_SPI ((uint)0x0180)
105 #define PROFF_SCC3 ((uint)0x0200)
106 #define PROFF_SMC1 ((uint)0x0280)
107 #define PROFF_SCC4 ((uint)0x0300)
108 #define PROFF_SMC2 ((uint)0x0380)
110 /* Define enough so I can at least use the serial port as a UART.
111 * The MBX uses SMC1 as the host serial port.
113 typedef struct smc_uart {
114 ushort smc_rbase; /* Rx Buffer descriptor base address */
115 ushort smc_tbase; /* Tx Buffer descriptor base address */
116 u_char smc_rfcr; /* Rx function code */
117 u_char smc_tfcr; /* Tx function code */
118 ushort smc_mrblr; /* Max receive buffer length */
119 uint smc_rstate; /* Internal */
120 uint smc_idp; /* Internal */
121 ushort smc_rbptr; /* Internal */
122 ushort smc_ibc; /* Internal */
123 uint smc_rxtmp; /* Internal */
124 uint smc_tstate; /* Internal */
125 uint smc_tdp; /* Internal */
126 ushort smc_tbptr; /* Internal */
127 ushort smc_tbc; /* Internal */
128 uint smc_txtmp; /* Internal */
129 ushort smc_maxidl; /* Maximum idle characters */
130 ushort smc_tmpidl; /* Temporary idle counter */
131 ushort smc_brklen; /* Last received break length */
132 ushort smc_brkec; /* rcv'd break condition counter */
133 ushort smc_brkcr; /* xmt break count register */
134 ushort smc_rmask; /* Temporary bit mask */
137 /* Function code bits.
139 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
141 /* SMC uart mode register.
143 #define SMCMR_REN ((ushort)0x0001)
144 #define SMCMR_TEN ((ushort)0x0002)
145 #define SMCMR_DM ((ushort)0x000c)
146 #define SMCMR_SM_GCI ((ushort)0x0000)
147 #define SMCMR_SM_UART ((ushort)0x0020)
148 #define SMCMR_SM_TRANS ((ushort)0x0030)
149 #define SMCMR_SM_MASK ((ushort)0x0030)
150 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
151 #define SMCMR_REVD SMCMR_PM_EVEN
152 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
153 #define SMCMR_BS SMCMR_PEN
154 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
155 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
156 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
158 /* SMC2 as Centronics parallel printer. It is half duplex, in that
159 * it can only receive or transmit. The parameter ram values for
160 * each direction are either unique or properly overlap, so we can
161 * include them in one structure.
163 typedef struct smc_centronics {
181 ushort scent_character1;
182 ushort scent_character2;
183 ushort scent_character3;
184 ushort scent_character4;
185 ushort scent_character5;
186 ushort scent_character6;
187 ushort scent_character7;
188 ushort scent_character8;
193 /* Centronics Status Mask Register.
195 #define SMC_CENT_F ((u_char)0x08)
196 #define SMC_CENT_PE ((u_char)0x04)
197 #define SMC_CENT_S ((u_char)0x02)
199 /* SMC Event and Mask register.
201 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
202 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
203 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
204 #define SMCM_BSY ((unsigned char)0x04)
205 #define SMCM_TX ((unsigned char)0x02)
206 #define SMCM_RX ((unsigned char)0x01)
208 /* Baud rate generators.
210 #define CPM_BRG_RST ((uint)0x00020000)
211 #define CPM_BRG_EN ((uint)0x00010000)
212 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
213 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
214 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
215 #define CPM_BRG_ATB ((uint)0x00002000)
216 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
217 #define CPM_BRG_DIV16 ((uint)0x00000001)
219 /* SI Clock Route Register
221 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
222 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
223 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
224 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
225 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
226 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
227 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
228 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
232 #define SCC_GSMRH_IRP ((uint)0x00040000)
233 #define SCC_GSMRH_GDE ((uint)0x00010000)
234 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
235 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
236 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
237 #define SCC_GSMRH_REVD ((uint)0x00002000)
238 #define SCC_GSMRH_TRX ((uint)0x00001000)
239 #define SCC_GSMRH_TTX ((uint)0x00000800)
240 #define SCC_GSMRH_CDP ((uint)0x00000400)
241 #define SCC_GSMRH_CTSP ((uint)0x00000200)
242 #define SCC_GSMRH_CDS ((uint)0x00000100)
243 #define SCC_GSMRH_CTSS ((uint)0x00000080)
244 #define SCC_GSMRH_TFL ((uint)0x00000040)
245 #define SCC_GSMRH_RFW ((uint)0x00000020)
246 #define SCC_GSMRH_TXSY ((uint)0x00000010)
247 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
248 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
249 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
250 #define SCC_GSMRH_RTSM ((uint)0x00000002)
251 #define SCC_GSMRH_RSYN ((uint)0x00000001)
253 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
254 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
255 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
256 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
257 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
258 #define SCC_GSMRL_TCI ((uint)0x10000000)
259 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
260 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
261 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
262 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
263 #define SCC_GSMRL_RINV ((uint)0x02000000)
264 #define SCC_GSMRL_TINV ((uint)0x01000000)
265 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
266 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
267 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
268 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
269 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
270 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
271 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
272 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
273 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
274 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
275 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
276 #define SCC_GSMRL_TEND ((uint)0x00040000)
277 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
278 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
279 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
280 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
281 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
282 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
283 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
284 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
285 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
286 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
287 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
288 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
289 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
290 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
291 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
292 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
293 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
294 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
295 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
296 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
297 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
298 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
299 #define SCC_GSMRL_ENR ((uint)0x00000020)
300 #define SCC_GSMRL_ENT ((uint)0x00000010)
301 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
302 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
303 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
304 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
305 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
306 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
307 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
308 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
309 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
310 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
312 #define SCC_TODR_TOD ((ushort)0x8000)
314 /* SCC Event and Mask register.
316 #define SCCM_TXE ((unsigned char)0x10)
317 #define SCCM_BSY ((unsigned char)0x04)
318 #define SCCM_TX ((unsigned char)0x02)
319 #define SCCM_RX ((unsigned char)0x01)
321 typedef struct scc_param {
322 ushort scc_rbase; /* Rx Buffer descriptor base address */
323 ushort scc_tbase; /* Tx Buffer descriptor base address */
324 u_char scc_rfcr; /* Rx function code */
325 u_char scc_tfcr; /* Tx function code */
326 ushort scc_mrblr; /* Max receive buffer length */
327 uint scc_rstate; /* Internal */
328 uint scc_idp; /* Internal */
329 ushort scc_rbptr; /* Internal */
330 ushort scc_ibc; /* Internal */
331 uint scc_rxtmp; /* Internal */
332 uint scc_tstate; /* Internal */
333 uint scc_tdp; /* Internal */
334 ushort scc_tbptr; /* Internal */
335 ushort scc_tbc; /* Internal */
336 uint scc_txtmp; /* Internal */
337 uint scc_rcrc; /* Internal */
338 uint scc_tcrc; /* Internal */
341 /* Function code bits.
343 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
345 /* CPM Ethernet through SCCx.
347 typedef struct scc_enet {
349 uint sen_cpres; /* Preset CRC */
350 uint sen_cmask; /* Constant mask for CRC */
351 uint sen_crcec; /* CRC Error counter */
352 uint sen_alec; /* alignment error counter */
353 uint sen_disfc; /* discard frame counter */
354 ushort sen_pads; /* Tx short frame pad character */
355 ushort sen_retlim; /* Retry limit threshold */
356 ushort sen_retcnt; /* Retry limit counter */
357 ushort sen_maxflr; /* maximum frame length register */
358 ushort sen_minflr; /* minimum frame length register */
359 ushort sen_maxd1; /* maximum DMA1 length */
360 ushort sen_maxd2; /* maximum DMA2 length */
361 ushort sen_maxd; /* Rx max DMA */
362 ushort sen_dmacnt; /* Rx DMA counter */
363 ushort sen_maxb; /* Max BD byte count */
364 ushort sen_gaddr1; /* Group address filter */
368 uint sen_tbuf0data0; /* Save area 0 - current frame */
369 uint sen_tbuf0data1; /* Save area 1 - current frame */
370 uint sen_tbuf0rba; /* Internal */
371 uint sen_tbuf0crc; /* Internal */
372 ushort sen_tbuf0bcnt; /* Internal */
373 ushort sen_paddrh; /* physical address (MSB) */
375 ushort sen_paddrl; /* physical address (LSB) */
376 ushort sen_pper; /* persistence */
377 ushort sen_rfbdptr; /* Rx first BD pointer */
378 ushort sen_tfbdptr; /* Tx first BD pointer */
379 ushort sen_tlbdptr; /* Tx last BD pointer */
380 uint sen_tbuf1data0; /* Save area 0 - current frame */
381 uint sen_tbuf1data1; /* Save area 1 - current frame */
382 uint sen_tbuf1rba; /* Internal */
383 uint sen_tbuf1crc; /* Internal */
384 ushort sen_tbuf1bcnt; /* Internal */
385 ushort sen_txlen; /* Tx Frame length counter */
386 ushort sen_iaddr1; /* Individual address filter */
390 ushort sen_boffcnt; /* Backoff counter */
392 /* NOTE: Some versions of the manual have the following items
393 * incorrectly documented. Below is the proper order.
395 ushort sen_taddrh; /* temp address (MSB) */
397 ushort sen_taddrl; /* temp address (LSB) */
400 /* SCC Event register as used by Ethernet.
402 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
403 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
404 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
405 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
406 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
407 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
409 /* SCC Mode Register (PMSR) as used by Ethernet.
411 #define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
412 #define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
413 #define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
414 #define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
415 #define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
416 #define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
417 #define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
418 #define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
419 #define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
420 #define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
421 #define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
422 #define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
423 #define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
425 /* Buffer descriptor control/status used by Ethernet receive.
427 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
428 #define BD_ENET_RX_WRAP ((ushort)0x2000)
429 #define BD_ENET_RX_INTR ((ushort)0x1000)
430 #define BD_ENET_RX_LAST ((ushort)0x0800)
431 #define BD_ENET_RX_FIRST ((ushort)0x0400)
432 #define BD_ENET_RX_MISS ((ushort)0x0100)
433 #define BD_ENET_RX_LG ((ushort)0x0020)
434 #define BD_ENET_RX_NO ((ushort)0x0010)
435 #define BD_ENET_RX_SH ((ushort)0x0008)
436 #define BD_ENET_RX_CR ((ushort)0x0004)
437 #define BD_ENET_RX_OV ((ushort)0x0002)
438 #define BD_ENET_RX_CL ((ushort)0x0001)
439 #define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
440 #define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
441 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
443 /* Buffer descriptor control/status used by Ethernet transmit.
445 #define BD_ENET_TX_READY ((ushort)0x8000)
446 #define BD_ENET_TX_PAD ((ushort)0x4000)
447 #define BD_ENET_TX_WRAP ((ushort)0x2000)
448 #define BD_ENET_TX_INTR ((ushort)0x1000)
449 #define BD_ENET_TX_LAST ((ushort)0x0800)
450 #define BD_ENET_TX_TC ((ushort)0x0400)
451 #define BD_ENET_TX_DEF ((ushort)0x0200)
452 #define BD_ENET_TX_HB ((ushort)0x0100)
453 #define BD_ENET_TX_LC ((ushort)0x0080)
454 #define BD_ENET_TX_RL ((ushort)0x0040)
455 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
456 #define BD_ENET_TX_UN ((ushort)0x0002)
457 #define BD_ENET_TX_CSL ((ushort)0x0001)
458 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
462 typedef struct scc_uart {
464 uint scc_res1; /* Reserved */
465 uint scc_res2; /* Reserved */
466 ushort scc_maxidl; /* Maximum idle chars */
467 ushort scc_idlc; /* temp idle counter */
468 ushort scc_brkcr; /* Break count register */
469 ushort scc_parec; /* receive parity error counter */
470 ushort scc_frmec; /* receive framing error counter */
471 ushort scc_nosec; /* receive noise counter */
472 ushort scc_brkec; /* receive break condition counter */
473 ushort scc_brkln; /* last received break length */
474 ushort scc_uaddr1; /* UART address character 1 */
475 ushort scc_uaddr2; /* UART address character 2 */
476 ushort scc_rtemp; /* Temp storage */
477 ushort scc_toseq; /* Transmit out of sequence char */
478 ushort scc_char1; /* control character 1 */
479 ushort scc_char2; /* control character 2 */
480 ushort scc_char3; /* control character 3 */
481 ushort scc_char4; /* control character 4 */
482 ushort scc_char5; /* control character 5 */
483 ushort scc_char6; /* control character 6 */
484 ushort scc_char7; /* control character 7 */
485 ushort scc_char8; /* control character 8 */
486 ushort scc_rccm; /* receive control character mask */
487 ushort scc_rccr; /* receive control character register */
488 ushort scc_rlbc; /* receive last break character */
491 /* SCC Event and Mask registers when it is used as a UART.
493 #define UART_SCCM_GLR ((ushort)0x1000)
494 #define UART_SCCM_GLT ((ushort)0x0800)
495 #define UART_SCCM_AB ((ushort)0x0200)
496 #define UART_SCCM_IDL ((ushort)0x0100)
497 #define UART_SCCM_GRA ((ushort)0x0080)
498 #define UART_SCCM_BRKE ((ushort)0x0040)
499 #define UART_SCCM_BRKS ((ushort)0x0020)
500 #define UART_SCCM_CCR ((ushort)0x0008)
501 #define UART_SCCM_BSY ((ushort)0x0004)
502 #define UART_SCCM_TX ((ushort)0x0002)
503 #define UART_SCCM_RX ((ushort)0x0001)
505 /* The SCC PMSR when used as a UART.
507 #define SCU_PMSR_FLC ((ushort)0x8000)
508 #define SCU_PMSR_SL ((ushort)0x4000)
509 #define SCU_PMSR_CL ((ushort)0x3000)
510 #define SCU_PMSR_UM ((ushort)0x0c00)
511 #define SCU_PMSR_FRZ ((ushort)0x0200)
512 #define SCU_PMSR_RZS ((ushort)0x0100)
513 #define SCU_PMSR_SYN ((ushort)0x0080)
514 #define SCU_PMSR_DRT ((ushort)0x0040)
515 #define SCU_PMSR_PEN ((ushort)0x0010)
516 #define SCU_PMSR_RPM ((ushort)0x000c)
517 #define SCU_PMSR_REVP ((ushort)0x0008)
518 #define SCU_PMSR_TPM ((ushort)0x0003)
519 #define SCU_PMSR_TEVP ((ushort)0x0002)
521 /* CPM Transparent mode SCC.
523 typedef struct scc_trans {
525 uint st_cpres; /* Preset CRC */
526 uint st_cmask; /* Constant mask for CRC */
529 #define BD_SCC_TX_LAST ((ushort)0x0800)
531 /* IIC parameter RAM.
534 ushort iic_rbase; /* Rx Buffer descriptor base address */
535 ushort iic_tbase; /* Tx Buffer descriptor base address */
536 u_char iic_rfcr; /* Rx function code */
537 u_char iic_tfcr; /* Tx function code */
538 ushort iic_mrblr; /* Max receive buffer length */
539 uint iic_rstate; /* Internal */
540 uint iic_rdp; /* Internal */
541 ushort iic_rbptr; /* Internal */
542 ushort iic_rbc; /* Internal */
543 uint iic_rxtmp; /* Internal */
544 uint iic_tstate; /* Internal */
545 uint iic_tdp; /* Internal */
546 ushort iic_tbptr; /* Internal */
547 ushort iic_tbc; /* Internal */
548 uint iic_txtmp; /* Internal */
549 uint iic_res; /* reserved */
550 ushort iic_rpbase; /* Relocation pointer */
551 ushort iic_res2; /* reserved */
554 #define BD_IIC_START ((ushort)0x0400)
556 /* SPI parameter RAM.
559 ushort spi_rbase; /* Rx Buffer descriptor base address */
560 ushort spi_tbase; /* Tx Buffer descriptor base address */
561 u_char spi_rfcr; /* Rx function code */
562 u_char spi_tfcr; /* Tx function code */
563 ushort spi_mrblr; /* Max receive buffer length */
564 uint spi_rstate; /* Internal */
565 uint spi_rdp; /* Internal */
566 ushort spi_rbptr; /* Internal */
567 ushort spi_rbc; /* Internal */
568 uint spi_rxtmp; /* Internal */
569 uint spi_tstate; /* Internal */
570 uint spi_tdp; /* Internal */
571 ushort spi_tbptr; /* Internal */
572 ushort spi_tbc; /* Internal */
573 uint spi_txtmp; /* Internal */
575 ushort spi_rpbase; /* Relocation pointer */
579 /* SPI Mode register.
581 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
582 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
583 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
584 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
585 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
586 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
587 #define SPMODE_EN ((ushort)0x0100) /* Enable */
588 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
589 #define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
590 #define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
591 #define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
592 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
595 #define SPIE_MME 0x20
596 #define SPIE_TXE 0x10
597 #define SPIE_BSY 0x04
598 #define SPIE_TXB 0x02
599 #define SPIE_RXB 0x01
602 * RISC Controller Configuration Register definitons
604 #define RCCR_TIME 0x8000 /* RISC Timer Enable */
605 #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
606 #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
608 /* RISC Timer Parameter RAM offset */
609 #define PROFF_RTMR ((uint)0x01B0)
611 typedef struct risc_timer_pram {
612 unsigned short tm_base; /* RISC Timer Table Base Address */
613 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
614 unsigned short r_tmr; /* RISC Timer Mode Register */
615 unsigned short r_tmv; /* RISC Timer Valid Register */
616 unsigned long tm_cmd; /* RISC Timer Command Register */
617 unsigned long tm_cnt; /* RISC Timer Internal Count */
620 /* Bits in RISC Timer Command Register */
621 #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
622 #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
623 #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
624 #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
625 #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
627 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
628 * channels or devices. All of these are presented to the PPC core
629 * as a single interrupt. The CPM interrupt handler dispatches its
630 * own handlers, in a similar fashion to the PPC core handler. We
631 * use the table as defined in the manuals (i.e. no special high
632 * priority and SCC1 == SCCa, etc...).
635 #define CPMVEC_PIO_PC15 ((ushort)0x1f)
636 #define CPMVEC_SCC1 ((ushort)0x1e)
637 #define CPMVEC_SCC2 ((ushort)0x1d)
638 #define CPMVEC_SCC3 ((ushort)0x1c)
639 #define CPMVEC_SCC4 ((ushort)0x1b)
640 #define CPMVEC_PIO_PC14 ((ushort)0x1a)
641 #define CPMVEC_TIMER1 ((ushort)0x19)
642 #define CPMVEC_PIO_PC13 ((ushort)0x18)
643 #define CPMVEC_PIO_PC12 ((ushort)0x17)
644 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
645 #define CPMVEC_IDMA1 ((ushort)0x15)
646 #define CPMVEC_IDMA2 ((ushort)0x14)
647 #define CPMVEC_TIMER2 ((ushort)0x12)
648 #define CPMVEC_RISCTIMER ((ushort)0x11)
649 #define CPMVEC_I2C ((ushort)0x10)
650 #define CPMVEC_PIO_PC11 ((ushort)0x0f)
651 #define CPMVEC_PIO_PC10 ((ushort)0x0e)
652 #define CPMVEC_TIMER3 ((ushort)0x0c)
653 #define CPMVEC_PIO_PC9 ((ushort)0x0b)
654 #define CPMVEC_PIO_PC8 ((ushort)0x0a)
655 #define CPMVEC_PIO_PC7 ((ushort)0x09)
656 #define CPMVEC_TIMER4 ((ushort)0x07)
657 #define CPMVEC_PIO_PC6 ((ushort)0x06)
658 #define CPMVEC_SPI ((ushort)0x05)
659 #define CPMVEC_SMC1 ((ushort)0x04)
660 #define CPMVEC_SMC2 ((ushort)0x03)
661 #define CPMVEC_PIO_PC5 ((ushort)0x02)
662 #define CPMVEC_PIO_PC4 ((ushort)0x01)
663 #define CPMVEC_ERROR ((ushort)0x00)
665 /* CPM interrupt configuration vector.
667 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
668 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
669 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
670 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
671 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
672 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
673 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
674 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
676 extern void cpm_install_handler(int vec,
677 void (*handler)(void *, struct pt_regs *regs), void *dev_id);
678 extern void cpm_free_handler(int vec);
680 #endif /* __CPM_8XX__ */