2 * include/asm-ppc/gt64260_defs.h
4 * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
7 * Author: Mark A. Greer <mgreer@mvista.com>
9 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #ifndef __ASMPPC_MV64x60_DEFS_H
15 #define __ASMPPC_MV64x60_DEFS_H
18 * Define the Marvell bridges that are supported
20 #define MV64x60_TYPE_INVALID 0
21 #define MV64x60_TYPE_GT64260A 1
22 #define MV64x60_TYPE_GT64260B 2
23 #define MV64x60_TYPE_MV64360 3
24 #define MV64x60_TYPE_MV64361 4
25 #define MV64x60_TYPE_MV64362 5
26 #define MV64x60_TYPE_MV64460 6
29 /* Revisions of each supported chip */
30 #define GT64260_REV_A 0x10
31 #define GT64260_REV_B 0x20
35 /* Minimum window size supported by 64260 is 1MB */
36 #define GT64260_WINDOW_SIZE_MIN 0x00100000
37 #define MV64360_WINDOW_SIZE_MIN 0x00010000
39 /* IRQ's for embedded controllers */
40 #define MV64x60_IRQ_DEV 1
41 #define MV64x60_IRQ_CPU_ERR 3
42 #define MV64x60_IRQ_TIMER_0_1 8
43 #define MV64x60_IRQ_TIMER_2_3 9
44 #define MV64x60_IRQ_TIMER_4_5 10
45 #define MV64x60_IRQ_TIMER_6_7 11
46 #define MV64x60_IRQ_ETH_0 32
47 #define MV64x60_IRQ_ETH_1 33
48 #define MV64x60_IRQ_ETH_2 34
49 #define MV64x60_IRQ_SDMA_0 36
50 #define MV64x60_IRQ_I2C 37
51 #define MV64x60_IRQ_BRG 39
52 #define MV64x60_IRQ_MPSC_0 40
53 #define MV64x60_IRQ_MPSC_1 42
54 #define MV64x60_IRQ_COMM 43
56 #define MV64360_IRQ_PCI0 12
57 #define MV64360_IRQ_SRAM_PAR_ERR 13
58 #define MV64360_IRQ_PCI1 16
59 #define MV64360_IRQ_SDMA_1 38
61 /* Offsets for register blocks */
62 #define GT64260_ENET_PHY_ADDR 0x2000
63 #define GT64260_ENET_ESMIR 0x2010
64 #define GT64260_ENET_0_OFFSET 0x2400
65 #define GT64260_ENET_1_OFFSET 0x2800
66 #define GT64260_ENET_2_OFFSET 0x2c00
67 #define MV64x60_SDMA_0_OFFSET 0x4000
68 #define MV64x60_SDMA_1_OFFSET 0x6000
69 #define MV64x60_MPSC_0_OFFSET 0x8000
70 #define MV64x60_MPSC_1_OFFSET 0x9000
71 #define MV64x60_MPSC_ROUTING_OFFSET 0xb400
72 #define MV64x60_SDMA_INTR_OFFSET 0xb800
73 #define MV64x60_BRG_0_OFFSET 0xb200
74 #define MV64x60_BRG_1_OFFSET 0xb208
77 *****************************************************************************
79 * CPU Interface Registers
81 *****************************************************************************
84 /* CPU physical address of bridge's registers */
85 #define MV64x60_INTERNAL_SPACE_DECODE 0x0068
86 #define MV64x60_INTERNAL_SPACE_SIZE 0x10000
87 #define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000
89 #define MV64360_CPU_BAR_ENABLE 0x0278
91 /* CPU Memory Controller Window Registers (4 windows) */
92 #define MV64x60_CPU2MEM_WINDOWS 4
94 #define MV64x60_CPU2MEM_0_BASE 0x0008
95 #define MV64x60_CPU2MEM_0_SIZE 0x0010
96 #define MV64x60_CPU2MEM_1_BASE 0x0208
97 #define MV64x60_CPU2MEM_1_SIZE 0x0210
98 #define MV64x60_CPU2MEM_2_BASE 0x0018
99 #define MV64x60_CPU2MEM_2_SIZE 0x0020
100 #define MV64x60_CPU2MEM_3_BASE 0x0218
101 #define MV64x60_CPU2MEM_3_SIZE 0x0220
103 /* CPU Device Controller Window Registers (4 windows) */
104 #define MV64x60_CPU2DEV_WINDOWS 4
106 #define MV64x60_CPU2DEV_0_BASE 0x0028
107 #define MV64x60_CPU2DEV_0_SIZE 0x0030
108 #define MV64x60_CPU2DEV_1_BASE 0x0228
109 #define MV64x60_CPU2DEV_1_SIZE 0x0230
110 #define MV64x60_CPU2DEV_2_BASE 0x0248
111 #define MV64x60_CPU2DEV_2_SIZE 0x0250
112 #define MV64x60_CPU2DEV_3_BASE 0x0038
113 #define MV64x60_CPU2DEV_3_SIZE 0x0040
115 #define MV64x60_CPU2BOOT_0_BASE 0x0238
116 #define MV64x60_CPU2BOOT_0_SIZE 0x0240
118 #define MV64360_CPU2SRAM_BASE 0x0268
120 /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
121 #define MV64x60_PCI_BUSES 2
122 #define MV64x60_PCI_IO_WINDOWS_PER_BUS 1
123 #define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4
125 #define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000
126 #define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
127 #define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000
128 #define MV64x60_CPU2PCI_SWAP_WORD 0x03000000
130 #define MV64x60_CPU2PCI_MEM_REQ64 (1<<27)
132 #define MV64x60_CPU2PCI0_IO_BASE 0x0048
133 #define MV64x60_CPU2PCI0_IO_SIZE 0x0050
134 #define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
135 #define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
136 #define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080
137 #define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088
138 #define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258
139 #define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260
140 #define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280
141 #define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288
143 #define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
144 #define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
145 #define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
146 #define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100
147 #define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328
148 #define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8
149 #define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330
150 #define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300
151 #define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338
153 #define MV64x60_CPU2PCI1_IO_BASE 0x0090
154 #define MV64x60_CPU2PCI1_IO_SIZE 0x0098
155 #define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
156 #define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
157 #define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0
158 #define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8
159 #define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0
160 #define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8
161 #define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0
162 #define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8
164 #define MV64x60_CPU2PCI1_IO_REMAP 0x0108
165 #define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
166 #define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
167 #define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118
168 #define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348
169 #define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310
170 #define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350
171 #define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318
172 #define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358
174 /* CPU Control Registers */
175 #define MV64x60_CPU_CONFIG 0x0000
176 #define MV64x60_CPU_MODE 0x0120
177 #define MV64x60_CPU_MASTER_CNTL 0x0160
178 #define MV64x60_CPU_XBAR_CNTL_LO 0x0150
179 #define MV64x60_CPU_XBAR_CNTL_HI 0x0158
180 #define MV64x60_CPU_XBAR_TO 0x0168
182 #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170
183 #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178
185 #define MV64360_CPU_PADS_CALIBRATION 0x03b4
186 #define MV64360_CPU_RESET_SAMPLE_LO 0x03c4
187 #define MV64360_CPU_RESET_SAMPLE_HI 0x03d4
189 /* SMP Register Map */
190 #define MV64360_WHO_AM_I 0x0200
191 #define MV64360_CPU0_DOORBELL 0x0214
192 #define MV64360_CPU0_DOORBELL_CLR 0x021c
193 #define MV64360_CPU0_DOORBELL_MASK 0x0234
194 #define MV64360_CPU1_DOORBELL 0x0224
195 #define MV64360_CPU1_DOORBELL_CLR 0x022c
196 #define MV64360_CPU1_DOORBELL_MASK 0x023c
197 #define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10))
198 #define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10))
199 #define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08))
200 #define MV64360_SEMAPHORE_0 0x0244
201 #define MV64360_SEMAPHORE_1 0x024c
202 #define MV64360_SEMAPHORE_2 0x0254
203 #define MV64360_SEMAPHORE_3 0x025c
204 #define MV64360_SEMAPHORE_4 0x0264
205 #define MV64360_SEMAPHORE_5 0x026c
206 #define MV64360_SEMAPHORE_6 0x0274
207 #define MV64360_SEMAPHORE_7 0x027c
209 /* CPU Sync Barrier Registers */
210 #define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0
211 #define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8
213 #define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0
214 #define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8
215 #define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0
216 #define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8
218 /* CPU Deadlock and Ordering registers (Rev B part only) */
219 #define GT64260_CPU_DEADLOCK_ORDERING 0x02d0
220 #define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8
221 #define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0
223 /* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
224 #define MV64x260_CPU_PROT_WINDOWS 4
226 #define GT64260_CPU_PROT_ACCPROTECT (1<<16)
227 #define GT64260_CPU_PROT_WRPROTECT (1<<17)
228 #define GT64260_CPU_PROT_CACHEPROTECT (1<<18)
230 #define MV64360_CPU_PROT_ACCPROTECT (1<<20)
231 #define MV64360_CPU_PROT_WRPROTECT (1<<21)
232 #define MV64360_CPU_PROT_CACHEPROTECT (1<<22)
233 #define MV64360_CPU_PROT_WIN_ENABLE (1<<31)
235 #define MV64x60_CPU_PROT_BASE_0 0x0180
236 #define MV64x60_CPU_PROT_SIZE_0 0x0188
237 #define MV64x60_CPU_PROT_BASE_1 0x0190
238 #define MV64x60_CPU_PROT_SIZE_1 0x0198
239 #define MV64x60_CPU_PROT_BASE_2 0x01a0
240 #define MV64x60_CPU_PROT_SIZE_2 0x01a8
241 #define MV64x60_CPU_PROT_BASE_3 0x01b0
242 #define MV64x60_CPU_PROT_SIZE_3 0x01b8
244 #define GT64260_CPU_PROT_BASE_4 0x01c0
245 #define GT64260_CPU_PROT_SIZE_4 0x01c8
246 #define GT64260_CPU_PROT_BASE_5 0x01d0
247 #define GT64260_CPU_PROT_SIZE_5 0x01d8
248 #define GT64260_CPU_PROT_BASE_6 0x01e0
249 #define GT64260_CPU_PROT_SIZE_6 0x01e8
250 #define GT64260_CPU_PROT_BASE_7 0x01f0
251 #define GT64260_CPU_PROT_SIZE_7 0x01f8
253 /* CPU Snoop Control Registers (64260 only) */
254 #define GT64260_CPU_SNOOP_WINDOWS 4
256 #define GT64260_CPU_SNOOP_NONE 0x00000000
257 #define GT64260_CPU_SNOOP_WT 0x00010000
258 #define GT64260_CPU_SNOOP_WB 0x00020000
259 #define GT64260_CPU_SNOOP_MASK 0x00030000
260 #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK
262 #define GT64260_CPU_SNOOP_BASE_0 0x0380
263 #define GT64260_CPU_SNOOP_SIZE_0 0x0388
264 #define GT64260_CPU_SNOOP_BASE_1 0x0390
265 #define GT64260_CPU_SNOOP_SIZE_1 0x0398
266 #define GT64260_CPU_SNOOP_BASE_2 0x03a0
267 #define GT64260_CPU_SNOOP_SIZE_2 0x03a8
268 #define GT64260_CPU_SNOOP_BASE_3 0x03b0
269 #define GT64260_CPU_SNOOP_SIZE_3 0x03b8
271 /* CPU Snoop Control Registers (64360 only) */
272 #define MV64360_CPU_SNOOP_WINDOWS 4
273 #define MV64360_CPU_SNOOP_NONE 0x00000000
274 #define MV64360_CPU_SNOOP_WT 0x00010000
275 #define MV64360_CPU_SNOOP_WB 0x00020000
276 #define MV64360_CPU_SNOOP_MASK 0x00030000
277 #define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK
280 /* CPU Error Report Registers */
281 #define MV64x60_CPU_ERR_ADDR_LO 0x0070
282 #define MV64x60_CPU_ERR_ADDR_HI 0x0078
283 #define MV64x60_CPU_ERR_DATA_LO 0x0128
284 #define MV64x60_CPU_ERR_DATA_HI 0x0130
285 #define MV64x60_CPU_ERR_PARITY 0x0138
286 #define MV64x60_CPU_ERR_CAUSE 0x0140
287 #define MV64x60_CPU_ERR_MASK 0x0148
290 *****************************************************************************
292 * SRAM Cotnroller Registers
294 *****************************************************************************
297 #define MV64360_SRAM_CONFIG 0x0380
298 #define MV64360_SRAM_TEST_MODE 0x03f4
299 #define MV64360_SRAM_ERR_CAUSE 0x0388
300 #define MV64360_SRAM_ERR_ADDR_LO 0x0390
301 #define MV64360_SRAM_ERR_ADDR_HI 0x03f8
302 #define MV64360_SRAM_ERR_DATA_LO 0x0398
303 #define MV64360_SRAM_ERR_DATA_HI 0x03a0
304 #define MV64360_SRAM_ERR_PARITY 0x03a8
306 #define MV64360_SRAM_SIZE 0x00040000 /* 256 KB of SRAM */
309 *****************************************************************************
311 * SDRAM/MEM Cotnroller Registers
313 *****************************************************************************
316 /* SDRAM Config Registers (64260) */
317 #define GT64260_SDRAM_CONFIG 0x0448
319 /* SDRAM Error Report Registers (64260) */
320 #define GT64260_SDRAM_ERR_DATA_LO 0x0484
321 #define GT64260_SDRAM_ERR_DATA_HI 0x0480
322 #define GT64260_SDRAM_ERR_ADDR 0x0490
323 #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488
324 #define GT64260_SDRAM_ERR_ECC_CALC 0x048c
325 #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494
326 #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498
328 /* SDRAM Config Registers (64360) */
329 #define MV64360_SDRAM_CONFIG 0x1400
331 /* SDRAM Control Registers */
332 #define MV64360_D_UNIT_CONTROL_LOW 0x1404
333 #define MV64360_D_UNIT_CONTROL_HIGH 0x1424
335 /* SDRAM Error Report Registers (64360) */
336 #define MV64360_SDRAM_ERR_DATA_LO 0x1444
337 #define MV64360_SDRAM_ERR_DATA_HI 0x1440
338 #define MV64360_SDRAM_ERR_ADDR 0x1450
339 #define MV64360_SDRAM_ERR_ECC_RCVD 0x1448
340 #define MV64360_SDRAM_ERR_ECC_CALC 0x144c
341 #define MV64360_SDRAM_ERR_ECC_CNTL 0x1454
342 #define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458
345 *****************************************************************************
347 * Device/BOOT Cotnroller Registers
349 *****************************************************************************
352 /* Device Control Registers */
353 #define MV64x60_DEV_BANK_PARAMS_0 0x045c
354 #define MV64x60_DEV_BANK_PARAMS_1 0x0460
355 #define MV64x60_DEV_BANK_PARAMS_2 0x0464
356 #define MV64x60_DEV_BANK_PARAMS_3 0x0468
357 #define MV64x60_DEV_BOOT_PARAMS 0x046c
358 #define MV64x60_DEV_IF_CNTL 0x04c0
359 #define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8
360 #define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc
361 #define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4
363 /* Device Interrupt Registers */
364 #define MV64x60_DEV_INTR_CAUSE 0x04d0
365 #define MV64x60_DEV_INTR_MASK 0x04d4
366 #define MV64x60_DEV_INTR_ERR_ADDR 0x04d8
368 #define MV64360_DEV_INTR_ERR_DATA 0x04dc
369 #define MV64360_DEV_INTR_ERR_PAR 0x04e0
372 *****************************************************************************
374 * PCI Bridge Interface Registers
376 *****************************************************************************
379 /* PCI Configuration Access Registers */
380 #define MV64x60_PCI0_CONFIG_ADDR 0x0cf8
381 #define MV64x60_PCI0_CONFIG_DATA 0x0cfc
382 #define MV64x60_PCI0_IACK 0x0c34
384 #define MV64x60_PCI1_CONFIG_ADDR 0x0c78
385 #define MV64x60_PCI1_CONFIG_DATA 0x0c7c
386 #define MV64x60_PCI1_IACK 0x0cb4
388 /* PCI Control Registers */
389 #define MV64x60_PCI0_CMD 0x0c00
390 #define MV64x60_PCI0_MODE 0x0d00
391 #define MV64x60_PCI0_TO_RETRY 0x0c04
392 #define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04
393 #define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38
394 #define MV64x60_PCI0_ARBITER_CNTL 0x1d00
395 #define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08
396 #define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c
397 #define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04
398 #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18
399 #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c
400 #define MV64x60_PCI0_SYNC_BARRIER 0x1d10
401 #define MV64x60_PCI0_P2P_CONFIG 0x1d14
402 #define MV64x60_PCI0_INTR_MASK
404 #define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54
406 #define MV64x60_PCI1_CMD 0x0c80
407 #define MV64x60_PCI1_MODE 0x0d80
408 #define MV64x60_PCI1_TO_RETRY 0x0c84
409 #define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84
410 #define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8
411 #define MV64x60_PCI1_ARBITER_CNTL 0x1d80
412 #define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88
413 #define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c
414 #define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84
415 #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98
416 #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c
417 #define MV64x60_PCI1_SYNC_BARRIER 0x1d90
418 #define MV64x60_PCI1_P2P_CONFIG 0x1d94
420 #define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4
422 /* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
423 #define MV64x60_PCIMODE_CONVENTIONAL 0
424 #define MV64x60_PCIMODE_PCIX_66 (1 << 4)
425 #define MV64x60_PCIMODE_PCIX_100 (2 << 4)
426 #define MV64x60_PCIMODE_PCIX_133 (3 << 4)
427 #define MV64x60_PCIMODE_MASK (0x3 << 4)
429 /* PCI Access Control Regions Registers */
430 #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12)
431 #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13)
432 #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16)
433 #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17)
434 #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18)
435 #define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000
436 #define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000
437 #define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000
438 #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000
439 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
440 #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000
441 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000
442 #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000
443 #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000
444 #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28)
445 #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29)
447 #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \
448 GT64260_PCI_ACC_CNTL_DREADEN | \
449 GT64260_PCI_ACC_CNTL_RDPREFETCH | \
450 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
451 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
452 GT64260_PCI_ACC_CNTL_MBURST_MASK | \
453 GT64260_PCI_ACC_CNTL_SWAP_MASK | \
454 GT64260_PCI_ACC_CNTL_ACCPROT| \
455 GT64260_PCI_ACC_CNTL_WRPROT)
457 #define MV64360_PCI_ACC_CNTL_ENABLE (1<<0)
458 #define MV64360_PCI_ACC_CNTL_REQ64 (1<<1)
459 #define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
460 #define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004
461 #define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008
462 #define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
463 #define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4)
464 #define MV64360_PCI_ACC_CNTL_WRPROT (1<<5)
465 #define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
466 #define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040
467 #define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
468 #define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
469 #define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
470 #define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
471 #define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
472 #define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
473 #define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300
474 #define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
475 #define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
476 #define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
477 #define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
478 #define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
480 #define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \
481 MV64360_PCI_ACC_CNTL_REQ64 | \
482 MV64360_PCI_ACC_CNTL_SNOOP_MASK | \
483 MV64360_PCI_ACC_CNTL_ACCPROT | \
484 MV64360_PCI_ACC_CNTL_WRPROT | \
485 MV64360_PCI_ACC_CNTL_SWAP_MASK | \
486 MV64360_PCI_ACC_CNTL_MBURST_MASK | \
487 MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
489 #define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
490 #define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
491 #define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
492 #define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
493 #define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
494 #define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
495 #define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
496 #define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
497 #define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
498 #define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
499 #define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
500 #define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
501 #define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
502 #define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
503 #define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
504 #define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
505 #define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
506 #define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
508 #define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60
509 #define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64
510 #define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68
511 #define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70
512 #define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74
513 #define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78
515 #define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
516 #define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
517 #define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
518 #define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
519 #define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
520 #define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
521 #define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
522 #define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
523 #define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
524 #define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
525 #define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
526 #define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
527 #define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
528 #define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
529 #define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
530 #define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
531 #define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
532 #define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
534 #define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0
535 #define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4
536 #define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8
537 #define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0
538 #define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4
539 #define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8
541 /* PCI Snoop Control Registers (64260 only) */
542 #define GT64260_PCI_SNOOP_NONE 0x00000000
543 #define GT64260_PCI_SNOOP_WT 0x00001000
544 #define GT64260_PCI_SNOOP_WB 0x00002000
546 #define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00
547 #define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04
548 #define GT64260_PCI0_SNOOP_0_SIZE 0x1f08
549 #define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10
550 #define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14
551 #define GT64260_PCI0_SNOOP_1_SIZE 0x1f18
552 #define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20
553 #define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24
554 #define GT64260_PCI0_SNOOP_2_SIZE 0x1f28
555 #define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30
556 #define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34
557 #define GT64260_PCI0_SNOOP_3_SIZE 0x1f38
559 #define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80
560 #define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84
561 #define GT64260_PCI1_SNOOP_0_SIZE 0x1f88
562 #define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90
563 #define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94
564 #define GT64260_PCI1_SNOOP_1_SIZE 0x1f98
565 #define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0
566 #define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4
567 #define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8
568 #define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0
569 #define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4
570 #define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8
572 /* PCI Error Report Registers */
573 #define MV64x60_PCI0_ERR_SERR_MASK 0x0c28
574 #define MV64x60_PCI0_ERR_ADDR_LO 0x1d40
575 #define MV64x60_PCI0_ERR_ADDR_HI 0x1d44
576 #define MV64x60_PCI0_ERR_DATA_LO 0x1d48
577 #define MV64x60_PCI0_ERR_DATA_HI 0x1d4c
578 #define MV64x60_PCI0_ERR_CMD 0x1d50
579 #define MV64x60_PCI0_ERR_CAUSE 0x1d58
580 #define MV64x60_PCI0_ERR_MASK 0x1d5c
582 #define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8
583 #define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0
584 #define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4
585 #define MV64x60_PCI1_ERR_DATA_LO 0x1dc8
586 #define MV64x60_PCI1_ERR_DATA_HI 0x1dcc
587 #define MV64x60_PCI1_ERR_CMD 0x1dd0
588 #define MV64x60_PCI1_ERR_CAUSE 0x1dd8
589 #define MV64x60_PCI1_ERR_MASK 0x1ddc
591 /* PCI Slave Address Decoding Registers */
592 #define MV64x60_PCI0_MEM_0_SIZE 0x0c08
593 #define MV64x60_PCI0_MEM_1_SIZE 0x0d08
594 #define MV64x60_PCI0_MEM_2_SIZE 0x0c0c
595 #define MV64x60_PCI0_MEM_3_SIZE 0x0d0c
596 #define MV64x60_PCI1_MEM_0_SIZE 0x0c88
597 #define MV64x60_PCI1_MEM_1_SIZE 0x0d88
598 #define MV64x60_PCI1_MEM_2_SIZE 0x0c8c
599 #define MV64x60_PCI1_MEM_3_SIZE 0x0d8c
601 #define MV64x60_PCI0_BAR_ENABLE 0x0c3c
602 #define MV64x60_PCI1_BAR_ENABLE 0x0cbc
604 #define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
605 #define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
607 #define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48
608 #define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48
609 #define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c
610 #define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c
611 #define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50
612 #define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50
613 #define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58
614 #define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54
615 #define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54
616 #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c
617 #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60
618 #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64
619 #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68
620 #define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c
621 #define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70
623 #define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8
624 #define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8
625 #define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc
626 #define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc
627 #define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0
628 #define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0
629 #define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8
630 #define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4
631 #define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4
632 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc
633 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0
634 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4
635 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8
636 #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec
637 #define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0
640 *****************************************************************************
642 * ENET Controller Interface Registers
644 *****************************************************************************
647 /* ENET Controller Window Registers (6 windows) */
648 #define MV64360_ENET2MEM_WINDOWS 6
650 #define MV64360_ENET2MEM_0_BASE 0x2200
651 #define MV64360_ENET2MEM_0_SIZE 0x2204
652 #define MV64360_ENET2MEM_1_BASE 0x2208
653 #define MV64360_ENET2MEM_1_SIZE 0x220c
654 #define MV64360_ENET2MEM_2_BASE 0x2210
655 #define MV64360_ENET2MEM_2_SIZE 0x2214
656 #define MV64360_ENET2MEM_3_BASE 0x2218
657 #define MV64360_ENET2MEM_3_SIZE 0x221c
658 #define MV64360_ENET2MEM_4_BASE 0x2220
659 #define MV64360_ENET2MEM_4_SIZE 0x2224
660 #define MV64360_ENET2MEM_5_BASE 0x2228
661 #define MV64360_ENET2MEM_5_SIZE 0x222c
663 #define MV64360_ENET2MEM_SNOOP_NONE 0x00000000
664 #define MV64360_ENET2MEM_SNOOP_WT 0x00001000
665 #define MV64360_ENET2MEM_SNOOP_WB 0x00002000
667 #define MV64360_ENET2MEM_BAR_ENABLE 0x2290
669 #define MV64360_ENET2MEM_ACC_PROT_0 0x2294
670 #define MV64360_ENET2MEM_ACC_PROT_1 0x2298
671 #define MV64360_ENET2MEM_ACC_PROT_2 0x229c
674 *****************************************************************************
676 * MPSC Controller Interface Registers
678 *****************************************************************************
681 /* MPSC Controller Window Registers (4 windows) */
682 #define MV64360_MPSC2MEM_WINDOWS 4
684 #define MV64360_MPSC2MEM_0_BASE 0xf200
685 #define MV64360_MPSC2MEM_0_SIZE 0xf204
686 #define MV64360_MPSC2MEM_1_BASE 0xf208
687 #define MV64360_MPSC2MEM_1_SIZE 0xf20c
688 #define MV64360_MPSC2MEM_2_BASE 0xf210
689 #define MV64360_MPSC2MEM_2_SIZE 0xf214
690 #define MV64360_MPSC2MEM_3_BASE 0xf218
691 #define MV64360_MPSC2MEM_3_SIZE 0xf21c
693 #define MV64360_MPSC_0_REMAP 0xf240
694 #define MV64360_MPSC_1_REMAP 0xf244
696 #define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000
697 #define MV64360_MPSC2MEM_SNOOP_WT 0x00001000
698 #define MV64360_MPSC2MEM_SNOOP_WB 0x00002000
700 #define MV64360_MPSC2MEM_BAR_ENABLE 0xf250
702 #define MV64360_MPSC2MEM_ACC_PROT_0 0xf254
703 #define MV64360_MPSC2MEM_ACC_PROT_1 0xf258
705 #define MV64360_MPSC2REGS_BASE 0xf25c
708 *****************************************************************************
710 * Timer/Counter Interface Registers
712 *****************************************************************************
715 #define MV64x60_TIMR_CNTR_0 0x0850
716 #define MV64x60_TIMR_CNTR_1 0x0854
717 #define MV64x60_TIMR_CNTR_2 0x0858
718 #define MV64x60_TIMR_CNTR_3 0x085c
719 #define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864
720 #define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868
721 #define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c
723 #define GT64260_TIMR_CNTR_4 0x0950
724 #define GT64260_TIMR_CNTR_5 0x0954
725 #define GT64260_TIMR_CNTR_6 0x0958
726 #define GT64260_TIMR_CNTR_7 0x095c
727 #define GT64260_TIMR_CNTR_4_7_CNTL 0x0964
728 #define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968
729 #define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c
732 *****************************************************************************
734 * Communications Controller
736 *****************************************************************************
739 #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320
740 #define GT64260_SER_INIT_LAST_DATA 0xf324
741 #define GT64260_SER_INIT_CONTROL 0xf328
742 #define GT64260_SER_INIT_STATUS 0xf32c
744 #define MV64x60_COMM_ARBITER_CNTL 0xf300
745 #define MV64x60_COMM_CONFIG 0xb40c
746 #define MV64x60_COMM_XBAR_TO 0xf304
747 #define MV64x60_COMM_INTR_CAUSE 0xf310
748 #define MV64x60_COMM_INTR_MASK 0xf314
749 #define MV64x60_COMM_ERR_ADDR 0xf318
751 #define MV64360_COMM_ARBITER_CNTL 0xf300
754 *****************************************************************************
756 * IDMA Controller Interface Registers
758 *****************************************************************************
761 /* IDMA Controller Window Registers (8 windows) */
762 #define MV64360_IDMA2MEM_WINDOWS 8
764 #define MV64360_IDMA2MEM_0_BASE 0x0a00
765 #define MV64360_IDMA2MEM_0_SIZE 0x0a04
766 #define MV64360_IDMA2MEM_1_BASE 0x0a08
767 #define MV64360_IDMA2MEM_1_SIZE 0x0a0c
768 #define MV64360_IDMA2MEM_2_BASE 0x0a10
769 #define MV64360_IDMA2MEM_2_SIZE 0x0a14
770 #define MV64360_IDMA2MEM_3_BASE 0x0a18
771 #define MV64360_IDMA2MEM_3_SIZE 0x0a1c
772 #define MV64360_IDMA2MEM_4_BASE 0x0a20
773 #define MV64360_IDMA2MEM_4_SIZE 0x0a24
774 #define MV64360_IDMA2MEM_5_BASE 0x0a28
775 #define MV64360_IDMA2MEM_5_SIZE 0x0a2c
776 #define MV64360_IDMA2MEM_6_BASE 0x0a30
777 #define MV64360_IDMA2MEM_6_SIZE 0x0a34
778 #define MV64360_IDMA2MEM_7_BASE 0x0a38
779 #define MV64360_IDMA2MEM_7_SIZE 0x0a3c
781 #define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000
782 #define MV64360_IDMA2MEM_SNOOP_WT 0x00001000
783 #define MV64360_IDMA2MEM_SNOOP_WB 0x00002000
785 #define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80
787 #define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70
788 #define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74
789 #define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78
790 #define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c
792 #define MV64x60_IDMA_0_OFFSET 0x0800
793 #define MV64x60_IDMA_1_OFFSET 0x0804
794 #define MV64x60_IDMA_2_OFFSET 0x0808
795 #define MV64x60_IDMA_3_OFFSET 0x080c
796 #define MV64x60_IDMA_4_OFFSET 0x0900
797 #define MV64x60_IDMA_5_OFFSET 0x0904
798 #define MV64x60_IDMA_6_OFFSET 0x0908
799 #define MV64x60_IDMA_7_OFFSET 0x090c
801 #define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET)
802 #define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET)
803 #define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET)
804 #define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET)
805 #define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET)
806 #define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET)
807 #define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET)
808 #define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET)
809 #define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET)
810 #define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET)
812 #define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860
813 #define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960
815 #define MV64x60_IDMA_0_3_XBAR_TO 0x08d0
816 #define MV64x60_IDMA_4_7_XBAR_TO 0x09d0
818 #define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0
819 #define MV64x60_IDMA_0_3_INTR_MASK 0x08c4
820 #define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8
821 #define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc
822 #define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0
823 #define MV64x60_IDMA_4_7_INTR_MASK 0x09c4
824 #define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8
825 #define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc
828 *****************************************************************************
830 * Watchdog Timer Interface Registers
832 *****************************************************************************
835 #define MV64x60_WDT_WDC 0xb410
836 #define MV64x60_WDT_WDV 0xb414
840 *****************************************************************************
842 * General Purpose Pins Controller Interface Registers
844 *****************************************************************************
847 #define MV64x60_GPP_IO_CNTL 0xf100
848 #define MV64x60_GPP_LEVEL_CNTL 0xf110
849 #define MV64x60_GPP_VALUE 0xf104
850 #define MV64x60_GPP_INTR_CAUSE 0xf108
851 #define MV64x60_GPP_INTR_MASK 0xf10c
852 #define MV64x60_GPP_VALUE_SET 0xf118
853 #define MV64x60_GPP_VALUE_CLR 0xf11c
857 *****************************************************************************
859 * Multi-Purpose Pins Controller Interface Registers
861 *****************************************************************************
864 #define MV64x60_MPP_CNTL_0 0xf000
865 #define MV64x60_MPP_CNTL_1 0xf004
866 #define MV64x60_MPP_CNTL_2 0xf008
867 #define MV64x60_MPP_CNTL_3 0xf00c
868 #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010
870 #define MV64x60_ETH_BAR_GAP 0x8
871 #define MV64x60_ETH_SIZE_REG_GAP 0x8
872 #define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
873 #define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4
875 #define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00
876 #define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00
877 #define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00
878 #define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700
880 #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
881 #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
882 #define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000
883 #define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800
887 *****************************************************************************
889 * Interrupt Controller Interface Registers
891 *****************************************************************************
894 #define GT64260_IC_OFFSET 0x0c18
896 #define GT64260_IC_MAIN_CAUSE_LO 0x0c18
897 #define GT64260_IC_MAIN_CAUSE_HI 0x0c68
898 #define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c
899 #define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c
900 #define GT64260_IC_CPU_SELECT_CAUSE 0x0c70
901 #define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24
902 #define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64
903 #define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74
904 #define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4
905 #define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4
906 #define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4
907 #define GT64260_IC_CPU_INT_0_MASK 0x0e60
908 #define GT64260_IC_CPU_INT_1_MASK 0x0e64
909 #define GT64260_IC_CPU_INT_2_MASK 0x0e68
910 #define GT64260_IC_CPU_INT_3_MASK 0x0e6c
912 #define MV64360_IC_OFFSET 0x0000
914 #define MV64360_IC_MAIN_CAUSE_LO 0x0004
915 #define MV64360_IC_MAIN_CAUSE_HI 0x000c
916 #define MV64360_IC_CPU0_INTR_MASK_LO 0x0014
917 #define MV64360_IC_CPU0_INTR_MASK_HI 0x001c
918 #define MV64360_IC_CPU0_SELECT_CAUSE 0x0024
919 #define MV64360_IC_CPU1_INTR_MASK_LO 0x0034
920 #define MV64360_IC_CPU1_INTR_MASK_HI 0x003c
921 #define MV64360_IC_CPU1_SELECT_CAUSE 0x0044
922 #define MV64360_IC_INT0_MASK_LO 0x0054
923 #define MV64360_IC_INT0_MASK_HI 0x005c
924 #define MV64360_IC_INT0_SELECT_CAUSE 0x0064
925 #define MV64360_IC_INT1_MASK_LO 0x0074
926 #define MV64360_IC_INT1_MASK_HI 0x007c
927 #define MV64360_IC_INT1_SELECT_CAUSE 0x0084
929 #endif /* __ASMPPC_MV64x60_DEFS_H */