include/asm-ppc64/cputable.h

   1 /*
   2  *  include/asm-ppc64/cputable.h
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #ifndef __ASM_PPC_CPUTABLE_H
  16 #define __ASM_PPC_CPUTABLE_H
  17
  18 #include <linux/config.h>
  19
  20 /* Exposed to userland CPU features - Must match ppc32 definitions */
  21 #define PPC_FEATURE_32                  0x80000000
  22 #define PPC_FEATURE_64                  0x40000000
  23 #define PPC_FEATURE_601_INSTR           0x20000000
  24 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
  25 #define PPC_FEATURE_HAS_FPU             0x08000000
  26 #define PPC_FEATURE_HAS_MMU             0x04000000
  27 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
  28 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  29
  30 #ifdef __KERNEL__
  31
  32 #ifndef __ASSEMBLY__
  33
  34 /* This structure can grow, it's real size is used by head.S code
  35  * via the mkdefs mechanism.
  36  */
  37 struct cpu_spec;
  38
  39 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  40
  41 struct cpu_spec {
  42         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  43         unsigned int    pvr_mask;
  44         unsigned int    pvr_value;
  45
  46         char            *cpu_name;
  47         unsigned long   cpu_features;           /* Kernel features */
  48         unsigned int    cpu_user_features;      /* Userland features */
  49
  50         /* cache line sizes */
  51         unsigned int    icache_bsize;
  52         unsigned int    dcache_bsize;
  53
  54         /* this is called to initialize various CPU bits like L1 cache,
  55          * BHT, SPD, etc... from head.S before branching to identify_machine
  56          */
  57         cpu_setup_t     cpu_setup;
  58
  59         /* This is used to identify firmware features which are available
  60          * to the kernel.
  61          */
  62         unsigned long   firmware_features;
  63 };
  64
  65 extern struct cpu_spec          cpu_specs[];
  66 extern struct cpu_spec          *cur_cpu_spec;
  67
  68
  69 /* firmware feature bitmask values */
  70 #define FIRMWARE_MAX_FEATURES 63
  71
  72 #define FW_FEATURE_PFT          (1UL<<0)
  73 #define FW_FEATURE_TCE          (1UL<<1)
  74 #define FW_FEATURE_SPRG0        (1UL<<2)
  75 #define FW_FEATURE_DABR         (1UL<<3)
  76 #define FW_FEATURE_COPY         (1UL<<4)
  77 #define FW_FEATURE_ASR          (1UL<<5)
  78 #define FW_FEATURE_DEBUG        (1UL<<6)
  79 #define FW_FEATURE_TERM         (1UL<<7)
  80 #define FW_FEATURE_PERF         (1UL<<8)
  81 #define FW_FEATURE_DUMP         (1UL<<9)
  82 #define FW_FEATURE_INTERRUPT    (1UL<<10)
  83 #define FW_FEATURE_MIGRATE      (1UL<<11)
  84 #define FW_FEATURE_PERFMON      (1UL<<12)
  85 #define FW_FEATURE_CRQ          (1UL<<13)
  86 #define FW_FEATURE_VIO          (1UL<<14)
  87 #define FW_FEATURE_RDMA         (1UL<<15)
  88 #define FW_FEATURE_LLAN         (1UL<<16)
  89 #define FW_FEATURE_BULK         (1UL<<17)
  90 #define FW_FEATURE_XDABR        (1UL<<18)
  91 #define FW_FEATURE_MULTITCE     (1UL<<19)
  92 #define FW_FEATURE_SPLPAR       (1UL<<20)
  93
  94 typedef struct {
  95     unsigned long val;
  96     char * name;
  97 } firmware_feature_t;
  98
  99 extern firmware_feature_t firmware_features_table[];
 100
 101 #endif /* __ASSEMBLY__ */
 102
 103 /* CPU kernel features */
 104
 105 /* Retain the 32b definitions for the time being - use bottom half of word */
 106 #define CPU_FTR_SPLIT_ID_CACHE          0x0000000000000001
 107 #define CPU_FTR_L2CR                    0x0000000000000002
 108 #define CPU_FTR_SPEC7450                0x0000000000000004
 109 #define CPU_FTR_ALTIVEC                 0x0000000000000008
 110 #define CPU_FTR_TAU                     0x0000000000000010
 111 #define CPU_FTR_CAN_DOZE                0x0000000000000020
 112 #define CPU_FTR_USE_TB                  0x0000000000000040
 113 #define CPU_FTR_604_PERF_MON            0x0000000000000080
 114 #define CPU_FTR_601                     0x0000000000000100
 115 #define CPU_FTR_HPTE_TABLE              0x0000000000000200
 116 #define CPU_FTR_CAN_NAP                 0x0000000000000400
 117 #define CPU_FTR_L3CR                    0x0000000000000800
 118 #define CPU_FTR_L3_DISABLE_NAP          0x0000000000001000
 119 #define CPU_FTR_NAP_DISABLE_L2_PR       0x0000000000002000
 120 #define CPU_FTR_DUAL_PLL_750FX          0x0000000000004000
 121
 122 /* Add the 64b processor unique features in the top half of the word */
 123 #define CPU_FTR_SLB                     0x0000000100000000
 124 #define CPU_FTR_16M_PAGE                0x0000000200000000
 125 #define CPU_FTR_TLBIEL                  0x0000000400000000
 126 #define CPU_FTR_NOEXECUTE               0x0000000800000000
 127 #define CPU_FTR_NODSISRALIGN            0x0000001000000000
 128 #define CPU_FTR_IABR                    0x0000002000000000
 129 #define CPU_FTR_MMCRA                   0x0000004000000000
 130 #define CPU_FTR_PMC8                    0x0000008000000000
 131 #define CPU_FTR_SMT                     0x0000010000000000
 132 #define CPU_FTR_COHERENT_ICACHE         0x0000020000000000
 133 #define CPU_FTR_LOCKLESS_TLBIE          0x0000040000000000
 134
 135 /* Platform firmware features */
 136 #define FW_FTR_                         0x0000000000000001
 137
 138 #ifndef __ASSEMBLY__
 139 #define COMMON_USER_PPC64       (PPC_FEATURE_32 | PPC_FEATURE_64 | \
 140                                  PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
 141
 142 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
 143                                  CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 144                                  CPU_FTR_NODSISRALIGN)
 145
 146 /* iSeries doesn't support large pages */
 147 #ifdef CONFIG_PPC_ISERIES
 148 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
 149 #else
 150 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
 151 #endif
 152
 153 #define COMMON_PPC64_FW (0)
 154 #endif
 155
 156 #ifdef __ASSEMBLY__
 157
 158 #define BEGIN_FTR_SECTION               98:
 159
 160 #define END_FTR_SECTION(msk, val)               \
 161 99:                                             \
 162         .section __ftr_fixup,"a";               \
 163         .align 3;                               \
 164         .llong msk;                             \
 165         .llong val;                             \
 166         .llong 98b;                             \
 167         .llong 99b;                             \
 168         .previous
 169
 170 #else
 171
 172 #define BEGIN_FTR_SECTION               "98:\n"
 173 #define END_FTR_SECTION(msk, val)               \
 174 "99:\n"                                         \
 175 "       .section __ftr_fixup,\"a\";\n"          \
 176 "       .align 3;\n"                            \
 177 "       .llong "#msk";\n"                       \
 178 "       .llong "#val";\n"                       \
 179 "       .llong 98b;\n"                          \
 180 "       .llong 99b;\n"                          \
 181 "       .previous\n"
 182
 183 #endif /* __ASSEMBLY__ */
 184
 185 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
 186 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
 187
 188 #endif /* __ASM_PPC_CPUTABLE_H */
 189 #endif /* __KERNEL__ */
 190