include/asm-s390/system.h

   1 /*
   2  *  include/asm-s390/system.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
   7  *
   8  *  Derived from "include/asm-i386/system.h"
   9  */
  10
  11 #ifndef __ASM_SYSTEM_H
  12 #define __ASM_SYSTEM_H
  13
  14 #include <linux/config.h>
  15 #include <linux/kernel.h>
  16 #include <asm/types.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/setup.h>
  19
  20 #ifdef __KERNEL__
  21
  22 struct task_struct;
  23
  24 extern struct task_struct *__switch_to(void *, void *);
  25
  26 #ifdef __s390x__
  27 #define __FLAG_SHIFT 56
  28 #else /* ! __s390x__ */
  29 #define __FLAG_SHIFT 24
  30 #endif /* ! __s390x__ */
  31
  32 static inline void save_fp_regs(s390_fp_regs *fpregs)
  33 {
  34         asm volatile (
  35                 "   std   0,8(%1)\n"
  36                 "   std   2,24(%1)\n"
  37                 "   std   4,40(%1)\n"
  38                 "   std   6,56(%1)"
  39                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
  40         if (!MACHINE_HAS_IEEE)
  41                 return;
  42         asm volatile(
  43                 "   stfpc 0(%1)\n"
  44                 "   std   1,16(%1)\n"
  45                 "   std   3,32(%1)\n"
  46                 "   std   5,48(%1)\n"
  47                 "   std   7,64(%1)\n"
  48                 "   std   8,72(%1)\n"
  49                 "   std   9,80(%1)\n"
  50                 "   std   10,88(%1)\n"
  51                 "   std   11,96(%1)\n"
  52                 "   std   12,104(%1)\n"
  53                 "   std   13,112(%1)\n"
  54                 "   std   14,120(%1)\n"
  55                 "   std   15,128(%1)\n"
  56                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
  57 }
  58
  59 static inline void restore_fp_regs(s390_fp_regs *fpregs)
  60 {
  61         asm volatile (
  62                 "   ld    0,8(%0)\n"
  63                 "   ld    2,24(%0)\n"
  64                 "   ld    4,40(%0)\n"
  65                 "   ld    6,56(%0)"
  66                 : : "a" (fpregs), "m" (*fpregs) );
  67         if (!MACHINE_HAS_IEEE)
  68                 return;
  69         asm volatile(
  70                 "   lfpc  0(%0)\n"
  71                 "   ld    1,16(%0)\n"
  72                 "   ld    3,32(%0)\n"
  73                 "   ld    5,48(%0)\n"
  74                 "   ld    7,64(%0)\n"
  75                 "   ld    8,72(%0)\n"
  76                 "   ld    9,80(%0)\n"
  77                 "   ld    10,88(%0)\n"
  78                 "   ld    11,96(%0)\n"
  79                 "   ld    12,104(%0)\n"
  80                 "   ld    13,112(%0)\n"
  81                 "   ld    14,120(%0)\n"
  82                 "   ld    15,128(%0)\n"
  83                 : : "a" (fpregs), "m" (*fpregs) );
  84 }
  85
  86 static inline void save_access_regs(unsigned int *acrs)
  87 {
  88         asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
  89 }
  90
  91 static inline void restore_access_regs(unsigned int *acrs)
  92 {
  93         asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
  94 }
  95
  96 #define switch_to(prev,next,last) do {                                       \
  97         if (prev == next)                                                    \
  98                 break;                                                       \
  99         save_fp_regs(&prev->thread.fp_regs);                                 \
 100         restore_fp_regs(&next->thread.fp_regs);                              \
 101         save_access_regs(&prev->thread.acrs[0]);                             \
 102         restore_access_regs(&next->thread.acrs[0]);                          \
 103         prev = __switch_to(prev,next);                                       \
 104 } while (0)
 105
 106 #define prepare_arch_switch(rq, next)   do { } while(0)
 107 #define task_running(rq, p)             ((rq)->curr == (p))
 108 #define finish_arch_switch(rq, prev) do {                                    \
 109         set_fs(current->thread.mm_segment);                                  \
 110         spin_unlock_irq(&(rq)->lock);                                        \
 111 } while (0)
 112
 113 #define nop() __asm__ __volatile__ ("nop")
 114
 115 #define xchg(ptr,x) \
 116   ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
 117
 118 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 119 {
 120         unsigned long addr, old;
 121         int shift;
 122
 123         switch (size) {
 124         case 1:
 125                 addr = (unsigned long) ptr;
 126                 shift = (3 ^ (addr & 3)) << 3;
 127                 addr ^= addr & 3;
 128                 asm volatile(
 129                         "    l   %0,0(%4)\n"
 130                         "0:  lr  0,%0\n"
 131                         "    nr  0,%3\n"
 132                         "    or  0,%2\n"
 133                         "    cs  %0,0,0(%4)\n"
 134                         "    jl  0b\n"
 135                         : "=&d" (old), "=m" (*(int *) addr)
 136                         : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
 137                           "m" (*(int *) addr) : "memory", "cc", "0" );
 138                 x = old >> shift;
 139                 break;
 140         case 2:
 141                 addr = (unsigned long) ptr;
 142                 shift = (2 ^ (addr & 2)) << 3;
 143                 addr ^= addr & 2;
 144                 asm volatile(
 145                         "    l   %0,0(%4)\n"
 146                         "0:  lr  0,%0\n"
 147                         "    nr  0,%3\n"
 148                         "    or  0,%2\n"
 149                         "    cs  %0,0,0(%4)\n"
 150                         "    jl  0b\n"
 151                         : "=&d" (old), "=m" (*(int *) addr)
 152                         : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
 153                           "m" (*(int *) addr) : "memory", "cc", "0" );
 154                 x = old >> shift;
 155                 break;
 156         case 4:
 157                 asm volatile (
 158                         "    l   %0,0(%3)\n"
 159                         "0:  cs  %0,%2,0(%3)\n"
 160                         "    jl  0b\n"
 161                         : "=&d" (old), "=m" (*(int *) ptr)
 162                         : "d" (x), "a" (ptr), "m" (*(int *) ptr)
 163                         : "memory", "cc" );
 164                 x = old;
 165                 break;
 166 #ifdef __s390x__
 167         case 8:
 168                 asm volatile (
 169                         "    lg  %0,0(%3)\n"
 170                         "0:  csg %0,%2,0(%3)\n"
 171                         "    jl  0b\n"
 172                         : "=&d" (old), "=m" (*(long *) ptr)
 173                         : "d" (x), "a" (ptr), "m" (*(long *) ptr)
 174                         : "memory", "cc" );
 175                 x = old;
 176                 break;
 177 #endif /* __s390x__ */
 178         }
 179         return x;
 180 }
 181
 182 /*
 183  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 184  * store NEW in MEM.  Return the initial value in MEM.  Success is
 185  * indicated by comparing RETURN with OLD.
 186  */
 187
 188 #define __HAVE_ARCH_CMPXCHG 1
 189
 190 #define cmpxchg(ptr,o,n)\
 191         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 192                                         (unsigned long)(n),sizeof(*(ptr))))
 193
 194 static inline unsigned long
 195 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 196 {
 197         unsigned long addr, prev, tmp;
 198         int shift;
 199
 200         switch (size) {
 201         case 1:
 202                 addr = (unsigned long) ptr;
 203                 shift = (3 ^ (addr & 3)) << 3;
 204                 addr ^= addr & 3;
 205                 asm volatile(
 206                         "    l   %0,0(%4)\n"
 207                         "0:  nr  %0,%5\n"
 208                         "    lr  %1,%0\n"
 209                         "    or  %0,%2\n"
 210                         "    or  %1,%3\n"
 211                         "    cs  %0,%1,0(%4)\n"
 212                         "    jnl 1f\n"
 213                         "    xr  %1,%0\n"
 214                         "    nr  %1,%5\n"
 215                         "    jnz 0b\n"
 216                         "1:"
 217                         : "=&d" (prev), "=&d" (tmp)
 218                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 219                           "d" (~(255 << shift))
 220                         : "memory", "cc" );
 221                 return prev >> shift;
 222         case 2:
 223                 addr = (unsigned long) ptr;
 224                 shift = (2 ^ (addr & 2)) << 3;
 225                 addr ^= addr & 2;
 226                 asm volatile(
 227                         "    l   %0,0(%4)\n"
 228                         "0:  nr  %0,%5\n"
 229                         "    lr  %1,%0\n"
 230                         "    or  %0,%2\n"
 231                         "    or  %1,%3\n"
 232                         "    cs  %0,%1,0(%4)\n"
 233                         "    jnl 1f\n"
 234                         "    xr  %1,%0\n"
 235                         "    nr  %1,%5\n"
 236                         "    jnz 0b\n"
 237                         "1:"
 238                         : "=&d" (prev), "=&d" (tmp)
 239                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 240                           "d" (~(65535 << shift))
 241                         : "memory", "cc" );
 242                 return prev >> shift;
 243         case 4:
 244                 asm volatile (
 245                         "    cs  %0,%2,0(%3)\n"
 246                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 247                         : "memory", "cc" );
 248                 return prev;
 249 #ifdef __s390x__
 250         case 8:
 251                 asm volatile (
 252                         "    csg %0,%2,0(%3)\n"
 253                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 254                         : "memory", "cc" );
 255                 return prev;
 256 #endif /* __s390x__ */
 257         }
 258         return old;
 259 }
 260
 261 /*
 262  * Force strict CPU ordering.
 263  * And yes, this is required on UP too when we're talking
 264  * to devices.
 265  *
 266  * This is very similar to the ppc eieio/sync instruction in that is
 267  * does a checkpoint syncronisation & makes sure that
 268  * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 269  */
 270
 271 #define eieio()  __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
 272 # define SYNC_OTHER_CORES(x)   eieio()
 273 #define mb()    eieio()
 274 #define rmb()   eieio()
 275 #define wmb()   eieio()
 276 #define read_barrier_depends() do { } while(0)
 277 #define smp_mb()       mb()
 278 #define smp_rmb()      rmb()
 279 #define smp_wmb()      wmb()
 280 #define smp_read_barrier_depends()    read_barrier_depends()
 281 #define smp_mb__before_clear_bit()     smp_mb()
 282 #define smp_mb__after_clear_bit()      smp_mb()
 283
 284
 285 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 286 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
 287
 288 /* interrupt control.. */
 289 #define local_irq_enable() ({ \
 290         unsigned long  __dummy; \
 291         __asm__ __volatile__ ( \
 292                 "stosm 0(%1),0x03" \
 293                 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
 294         })
 295
 296 #define local_irq_disable() ({ \
 297         unsigned long __flags; \
 298         __asm__ __volatile__ ( \
 299                 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
 300         __flags; \
 301         })
 302
 303 #define local_save_flags(x) \
 304         __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
 305
 306 #define local_irq_restore(x) \
 307         __asm__ __volatile__("ssm   0(%0)" : : "a" (&x), "m" (x) : "memory")
 308
 309 #define irqs_disabled()                 \
 310 ({                                      \
 311         unsigned long flags;            \
 312         local_save_flags(flags);        \
 313         !((flags >> __FLAG_SHIFT) & 3); \
 314 })
 315
 316 #ifdef __s390x__
 317
 318 #define __load_psw(psw) \
 319         __asm__ __volatile__("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
 320
 321 #define __ctl_load(array, low, high) ({ \
 322         __asm__ __volatile__ ( \
 323                 "   bras  1,0f\n" \
 324                 "   lctlg 0,0,0(%0)\n" \
 325                 "0: ex    %1,0(1)" \
 326                 : : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
 327         })
 328
 329 #define __ctl_store(array, low, high) ({ \
 330         __asm__ __volatile__ ( \
 331                 "   bras  1,0f\n" \
 332                 "   stctg 0,0,0(%1)\n" \
 333                 "0: ex    %2,0(1)" \
 334                 : "=m" (array) : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
 335         })
 336
 337 #define __ctl_set_bit(cr, bit) ({ \
 338         __u8 __dummy[24]; \
 339         __asm__ __volatile__ ( \
 340                 "    bras  1,0f\n"       /* skip indirect insns */ \
 341                 "    stctg 0,0,0(%1)\n" \
 342                 "    lctlg 0,0,0(%1)\n" \
 343                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 344                 "    lg    0,0(%1)\n" \
 345                 "    ogr   0,%3\n"       /* set the bit */ \
 346                 "    stg   0,0(%1)\n" \
 347                 "1:  ex    %2,6(1)"      /* execute lctl */ \
 348                 : "=m" (__dummy) \
 349                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 350                   "a" (cr*17), "a" (1L<<(bit)) \
 351                 : "cc", "0", "1" ); \
 352         })
 353
 354 #define __ctl_clear_bit(cr, bit) ({ \
 355         __u8 __dummy[16]; \
 356         __asm__ __volatile__ ( \
 357                 "    bras  1,0f\n"       /* skip indirect insns */ \
 358                 "    stctg 0,0,0(%1)\n" \
 359                 "    lctlg 0,0,0(%1)\n" \
 360                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 361                 "    lg    0,0(%1)\n" \
 362                 "    ngr   0,%3\n"       /* set the bit */ \
 363                 "    stg   0,0(%1)\n" \
 364                 "1:  ex    %2,6(1)"      /* execute lctl */ \
 365                 : "=m" (__dummy) \
 366                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 367                   "a" (cr*17), "a" (~(1L<<(bit))) \
 368                 : "cc", "0", "1" ); \
 369         })
 370
 371 #else /* __s390x__ */
 372
 373 #define __load_psw(psw) \
 374         __asm__ __volatile__("lpsw 0(%0)" : : "a" (&psw) : "cc" );
 375
 376 #define __ctl_load(array, low, high) ({ \
 377         __asm__ __volatile__ ( \
 378                 "   bras  1,0f\n" \
 379                 "   lctl 0,0,0(%0)\n" \
 380                 "0: ex    %1,0(1)" \
 381                 : : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
 382         })
 383
 384 #define __ctl_store(array, low, high) ({ \
 385         __asm__ __volatile__ ( \
 386                 "   bras  1,0f\n" \
 387                 "   stctl 0,0,0(%1)\n" \
 388                 "0: ex    %2,0(1)" \
 389                 : "=m" (array) : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
 390         })
 391
 392 #define __ctl_set_bit(cr, bit) ({ \
 393         __u8 __dummy[16]; \
 394         __asm__ __volatile__ ( \
 395                 "    bras  1,0f\n"       /* skip indirect insns */ \
 396                 "    stctl 0,0,0(%1)\n" \
 397                 "    lctl  0,0,0(%1)\n" \
 398                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 399                 "    l     0,0(%1)\n" \
 400                 "    or    0,%3\n"       /* set the bit */ \
 401                 "    st    0,0(%1)\n" \
 402                 "1:  ex    %2,4(1)"      /* execute lctl */ \
 403                 : "=m" (__dummy) \
 404                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 405                   "a" (cr*17), "a" (1<<(bit)) \
 406                 : "cc", "0", "1" ); \
 407         })
 408
 409 #define __ctl_clear_bit(cr, bit) ({ \
 410         __u8 __dummy[16]; \
 411         __asm__ __volatile__ ( \
 412                 "    bras  1,0f\n"       /* skip indirect insns */ \
 413                 "    stctl 0,0,0(%1)\n" \
 414                 "    lctl  0,0,0(%1)\n" \
 415                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 416                 "    l     0,0(%1)\n" \
 417                 "    nr    0,%3\n"       /* set the bit */ \
 418                 "    st    0,0(%1)\n" \
 419                 "1:  ex    %2,4(1)"      /* execute lctl */ \
 420                 : "=m" (__dummy) \
 421                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 422                   "a" (cr*17), "a" (~(1<<(bit))) \
 423                 : "cc", "0", "1" ); \
 424         })
 425 #endif /* __s390x__ */
 426
 427 /* For spinlocks etc */
 428 #define local_irq_save(x)       ((x) = local_irq_disable())
 429
 430 #ifdef CONFIG_SMP
 431
 432 extern void smp_ctl_set_bit(int cr, int bit);
 433 extern void smp_ctl_clear_bit(int cr, int bit);
 434 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
 435 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
 436
 437 #else
 438
 439 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
 440 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
 441
 442 #endif /* CONFIG_SMP */
 443
 444 extern void (*_machine_restart)(char *command);
 445 extern void (*_machine_halt)(void);
 446 extern void (*_machine_power_off)(void);
 447
 448 #endif /* __KERNEL__ */
 449
 450 #endif
 451