include/asm-sparc/system.h

   1 /* $Id: system.h,v 1.86 2001/10/30 04:57:10 davem Exp $ */
   2 #include <linux/config.h>
   3
   4 #ifndef __SPARC_SYSTEM_H
   5 #define __SPARC_SYSTEM_H
   6
   7 #include <linux/config.h>
   8 #include <linux/kernel.h>
   9 #include <linux/threads.h>      /* NR_CPUS */
  10 #include <linux/thread_info.h>
  11
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/psr.h>
  15 #include <asm/ptrace.h>
  16 #include <asm/btfixup.h>
  17
  18 #ifndef __ASSEMBLY__
  19
  20 /*
  21  * Sparc (general) CPU types
  22  */
  23 enum sparc_cpu {
  24   sun4        = 0x00,
  25   sun4c       = 0x01,
  26   sun4m       = 0x02,
  27   sun4d       = 0x03,
  28   sun4e       = 0x04,
  29   sun4u       = 0x05, /* V8 ploos ploos */
  30   sun_unknown = 0x06,
  31   ap1000      = 0x07, /* almost a sun4m */
  32 };
  33
  34 /* Really, userland should not be looking at any of this... */
  35 #ifdef __KERNEL__
  36
  37 extern enum sparc_cpu sparc_cpu_model;
  38
  39 #ifndef CONFIG_SUN4
  40 #define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
  41 #define ARCH_SUN4 0
  42 #else
  43 #define ARCH_SUN4C_SUN4 1
  44 #define ARCH_SUN4 1
  45 #endif
  46
  47 #define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
  48
  49 extern struct thread_info *current_set[NR_CPUS];
  50
  51 extern unsigned long empty_bad_page;
  52 extern unsigned long empty_bad_page_table;
  53 extern unsigned long empty_zero_page;
  54
  55 extern void sun_do_break(void);
  56 extern int serial_console;
  57 extern int stop_a_enabled;
  58
  59 static __inline__ int con_is_present(void)
  60 {
  61         return serial_console ? 0 : 1;
  62 }
  63
  64 /* When a context switch happens we must flush all user windows so that
  65  * the windows of the current process are flushed onto its stack. This
  66  * way the windows are all clean for the next process and the stack
  67  * frames are up to date.
  68  */
  69 extern void flush_user_windows(void);
  70 extern void kill_user_windows(void);
  71 extern void synchronize_user_stack(void);
  72 extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
  73                    void *fpqueue, unsigned long *fpqdepth);
  74
  75 #ifdef CONFIG_SMP
  76 #define SWITCH_ENTER(prv) \
  77         do {                    \
  78         if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
  79                 put_psr(get_psr() | PSR_EF); \
  80                 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
  81                        &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
  82                 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
  83                 (prv)->thread.kregs->psr &= ~PSR_EF; \
  84         } \
  85         } while(0)
  86
  87 #define SWITCH_DO_LAZY_FPU(next)        /* */
  88 #else
  89 #define SWITCH_ENTER(prv)               /* */
  90 #define SWITCH_DO_LAZY_FPU(nxt) \
  91         do {                    \
  92         if (last_task_used_math != (nxt))               \
  93                 (nxt)->thread.kregs->psr&=~PSR_EF;      \
  94         } while(0)
  95 #endif
  96
  97 /*
  98  * Flush windows so that the VM switch which follows
  99  * would not pull the stack from under us.
 100  *
 101  * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
 102  * XXX WTF is the above comment? Found in late teen 2.4.x.
 103  */
 104 #define prepare_arch_switch(rq, next) do { \
 105         __asm__ __volatile__( \
 106         ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
 107         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
 108         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
 109         "save %sp, -0x40, %sp\n\t" \
 110         "restore; restore; restore; restore; restore; restore; restore"); \
 111 } while(0)
 112 #define finish_arch_switch(rq, next)    spin_unlock_irq(&(rq)->lock)
 113 #define task_running(rq, p)             ((rq)->curr == (p))
 114
 115         /* Much care has gone into this code, do not touch it.
 116          *
 117          * We need to loadup regs l0/l1 for the newly forked child
 118          * case because the trap return path relies on those registers
 119          * holding certain values, gcc is told that they are clobbered.
 120          * Gcc needs registers for 3 values in and 1 value out, so we
 121          * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
 122          *
 123          * Hey Dave, that do not touch sign is too much of an incentive
 124          * - Anton & Pete
 125          */
 126 #define switch_to(prev, next, last) do {                                                \
 127         SWITCH_ENTER(prev);                                                             \
 128         SWITCH_DO_LAZY_FPU(next);                                                       \
 129         cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask);                      \
 130         __asm__ __volatile__(                                                           \
 131         "sethi  %%hi(here - 0x8), %%o7\n\t"                                             \
 132         "mov    %%g6, %%g3\n\t"                                                         \
 133         "or     %%o7, %%lo(here - 0x8), %%o7\n\t"                                       \
 134         "rd     %%psr, %%g4\n\t"                                                        \
 135         "std    %%sp, [%%g6 + %4]\n\t"                                                  \
 136         "rd     %%wim, %%g5\n\t"                                                        \
 137         "wr     %%g4, 0x20, %%psr\n\t"                                                  \
 138         "nop\n\t"                                                                       \
 139         "std    %%g4, [%%g6 + %3]\n\t"                                                  \
 140         "ldd    [%2 + %3], %%g4\n\t"                                                    \
 141         "mov    %2, %%g6\n\t"                                                           \
 142         ".globl patchme_store_new_current\n"                                            \
 143 "patchme_store_new_current:\n\t"                                                        \
 144         "st     %2, [%1]\n\t"                                                           \
 145         "wr     %%g4, 0x20, %%psr\n\t"                                                  \
 146         "nop\n\t"                                                                       \
 147         "nop\n\t"                                                                       \
 148         "nop\n\t"       /* LEON needs all 3 nops: load to %sp depends on CWP. */                \
 149         "ldd    [%%g6 + %4], %%sp\n\t"                                                  \
 150         "wr     %%g5, 0x0, %%wim\n\t"                                                   \
 151         "ldd    [%%sp + 0x00], %%l0\n\t"                                                \
 152         "ldd    [%%sp + 0x38], %%i6\n\t"                                                \
 153         "wr     %%g4, 0x0, %%psr\n\t"                                                   \
 154         "nop\n\t"                                                                       \
 155         "nop\n\t"                                                                       \
 156         "jmpl   %%o7 + 0x8, %%g0\n\t"                                                   \
 157         " ld    [%%g3 + %5], %0\n\t"                                                    \
 158         "here:\n"                                                                       \
 159         : "=&r" (last)                                                                  \
 160         : "r" (&(current_set[hard_smp_processor_id()])),        \
 161           "r" ((next)->thread_info),                            \
 162           "i" (TI_KPSR),                                        \
 163           "i" (TI_KSP),                                         \
 164           "i" (TI_TASK)                                         \
 165         :       "g1", "g2", "g3", "g4", "g5",       "g7",       \
 166           "l0", "l1",       "l3", "l4", "l5", "l6", "l7",       \
 167           "i0", "i1", "i2", "i3", "i4", "i5",                   \
 168           "o0", "o1", "o2", "o3",                   "o7");      \
 169         } while(0)
 170
 171 /*
 172  * Changing the IRQ level on the Sparc.
 173  */
 174 extern void local_irq_restore(unsigned long);
 175 extern unsigned long __local_irq_save(void);
 176 extern void local_irq_enable(void);
 177
 178 static inline unsigned long getipl(void)
 179 {
 180         unsigned long retval;
 181
 182         __asm__ __volatile__("rd        %%psr, %0" : "=r" (retval));
 183         return retval;
 184 }
 185
 186 #define local_save_flags(flags) ((flags) = getipl())
 187 #define local_irq_save(flags)   ((flags) = __local_irq_save())
 188 #define local_irq_disable()     ((void) __local_irq_save())
 189 #define irqs_disabled()         ((getipl() & PSR_PIL) != 0)
 190
 191 /* XXX Change this if we ever use a PSO mode kernel. */
 192 #define mb()    __asm__ __volatile__ ("" : : : "memory")
 193 #define rmb()   mb()
 194 #define wmb()   mb()
 195 #define read_barrier_depends()  do { } while(0)
 196 #define set_mb(__var, __value)  do { __var = __value; mb(); } while(0)
 197 #define set_wmb(__var, __value) set_mb(__var, __value)
 198 #define smp_mb()        __asm__ __volatile__("":::"memory")
 199 #define smp_rmb()       __asm__ __volatile__("":::"memory")
 200 #define smp_wmb()       __asm__ __volatile__("":::"memory")
 201 #define smp_read_barrier_depends()      do { } while(0)
 202
 203 #define nop() __asm__ __volatile__ ("nop")
 204
 205 /* This has special calling conventions */
 206 #ifndef CONFIG_SMP
 207 BTFIXUPDEF_CALL(void, ___xchg32, void)
 208 #endif
 209
 210 extern __inline__ unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
 211 {
 212 #ifdef CONFIG_SMP
 213         __asm__ __volatile__("swap [%2], %0"
 214                              : "=&r" (val)
 215                              : "0" (val), "r" (m)
 216                              : "memory");
 217         return val;
 218 #else
 219         register unsigned long *ptr asm("g1");
 220         register unsigned long ret asm("g2");
 221
 222         ptr = (unsigned long *) m;
 223         ret = val;
 224
 225         /* Note: this is magic and the nop there is
 226            really needed. */
 227         __asm__ __volatile__(
 228         "mov    %%o7, %%g4\n\t"
 229         "call   ___f____xchg32\n\t"
 230         " nop\n\t"
 231         : "=&r" (ret)
 232         : "0" (ret), "r" (ptr)
 233         : "g3", "g4", "g7", "memory", "cc");
 234
 235         return ret;
 236 #endif
 237 }
 238
 239 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 240 #define tas(ptr) (xchg((ptr),1))
 241
 242 extern void __xchg_called_with_bad_pointer(void);
 243
 244 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
 245 {
 246         switch (size) {
 247         case 4:
 248                 return xchg_u32(ptr, x);
 249         };
 250         __xchg_called_with_bad_pointer();
 251         return x;
 252 }
 253
 254 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 255
 256 #endif /* __KERNEL__ */
 257
 258 #endif /* __ASSEMBLY__ */
 259
 260 #define arch_align_stack(x) (x)
 261
 262 #endif /* !(__SPARC_SYSTEM_H) */