include/asm-sparc64/system.h

   1 /* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
   2 #ifndef __SPARC64_SYSTEM_H
   3 #define __SPARC64_SYSTEM_H
   4
   5 #include <linux/config.h>
   6 #include <asm/ptrace.h>
   7 #include <asm/processor.h>
   8 #include <asm/visasm.h>
   9
  10 #ifndef __ASSEMBLY__
  11 /*
  12  * Sparc (general) CPU types
  13  */
  14 enum sparc_cpu {
  15   sun4        = 0x00,
  16   sun4c       = 0x01,
  17   sun4m       = 0x02,
  18   sun4d       = 0x03,
  19   sun4e       = 0x04,
  20   sun4u       = 0x05, /* V8 ploos ploos */
  21   sun_unknown = 0x06,
  22   ap1000      = 0x07, /* almost a sun4m */
  23 };
  24
  25 #define sparc_cpu_model sun4u
  26
  27 /* This cannot ever be a sun4c nor sun4 :) That's just history. */
  28 #define ARCH_SUN4C_SUN4 0
  29 #define ARCH_SUN4 0
  30
  31 #endif
  32
  33 #define setipl(__new_ipl) \
  34         __asm__ __volatile__("wrpr      %0, %%pil"  : : "r" (__new_ipl) : "memory")
  35
  36 #define local_irq_disable() \
  37         __asm__ __volatile__("wrpr      15, %%pil" : : : "memory")
  38
  39 #define local_irq_enable() \
  40         __asm__ __volatile__("wrpr      0, %%pil" : : : "memory")
  41
  42 #define getipl() \
  43 ({ unsigned long retval; __asm__ __volatile__("rdpr     %%pil, %0" : "=r" (retval)); retval; })
  44
  45 #define swap_pil(__new_pil) \
  46 ({      unsigned long retval; \
  47         __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
  48                              "wrpr      %1, %%pil" \
  49                              : "=&r" (retval) \
  50                              : "r" (__new_pil) \
  51                              : "memory"); \
  52         retval; \
  53 })
  54
  55 #define read_pil_and_cli() \
  56 ({      unsigned long retval; \
  57         __asm__ __volatile__("rdpr      %%pil, %0\n\t" \
  58                              "wrpr      15, %%pil" \
  59                              : "=r" (retval) \
  60                              : : "memory"); \
  61         retval; \
  62 })
  63
  64 #define local_save_flags(flags)         ((flags) = getipl())
  65 #define local_irq_save(flags)           ((flags) = read_pil_and_cli())
  66 #define local_irq_restore(flags)                setipl((flags))
  67
  68 /* On sparc64 IRQ flags are the PIL register.  A value of zero
  69  * means all interrupt levels are enabled, any other value means
  70  * only IRQ levels greater than that value will be received.
  71  * Consequently this means that the lowest IRQ level is one.
  72  */
  73 #define irqs_disabled()         \
  74 ({      unsigned long flags;    \
  75         local_save_flags(flags);\
  76         (flags > 0);            \
  77 })
  78
  79 #define nop()           __asm__ __volatile__ ("nop")
  80
  81 #define membar(type)    __asm__ __volatile__ ("membar " type : : : "memory")
  82 #define mb()            \
  83         membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
  84 #define rmb()           membar("#LoadLoad")
  85 #define wmb()           membar("#StoreStore")
  86 #define read_barrier_depends()          do { } while(0)
  87 #define set_mb(__var, __value) \
  88         do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0)
  89 #define set_wmb(__var, __value) \
  90         do { __var = __value; membar("#StoreStore"); } while(0)
  91
  92 #ifdef CONFIG_SMP
  93 #define smp_mb()        mb()
  94 #define smp_rmb()       rmb()
  95 #define smp_wmb()       wmb()
  96 #define smp_read_barrier_depends()      read_barrier_depends()
  97 #else
  98 #define smp_mb()        __asm__ __volatile__("":::"memory")
  99 #define smp_rmb()       __asm__ __volatile__("":::"memory")
 100 #define smp_wmb()       __asm__ __volatile__("":::"memory")
 101 #define smp_read_barrier_depends()      do { } while(0)
 102 #endif
 103
 104 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
 105
 106 #define flushw_all()    __asm__ __volatile__("flushw")
 107
 108 /* Performance counter register access. */
 109 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
 110 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
 111 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
 112
 113 /* Blackbird errata workaround.  See commentary in
 114  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
 115  * for more information.
 116  */
 117 #define reset_pic()                                             \
 118         __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
 119                              ".align    64\n"                   \
 120                           "99:wr        %g0, 0x0, %pic\n\t"     \
 121                              "rd        %pic, %g0")
 122
 123 #ifndef __ASSEMBLY__
 124
 125 extern void sun_do_break(void);
 126 extern int serial_console;
 127 extern int stop_a_enabled;
 128
 129 static __inline__ int con_is_present(void)
 130 {
 131         return serial_console ? 0 : 1;
 132 }
 133
 134 extern void synchronize_user_stack(void);
 135
 136 extern void __flushw_user(void);
 137 #define flushw_user() __flushw_user()
 138
 139 #define flush_user_windows flushw_user
 140 #define flush_register_windows flushw_all
 141
 142 #define prepare_arch_switch(rq, next)           \
 143 do {    spin_lock(&(next)->switch_lock);        \
 144         spin_unlock(&(rq)->lock);               \
 145         flushw_all();                           \
 146 } while (0)
 147
 148 #define finish_arch_switch(rq, prev)            \
 149 do {    spin_unlock_irq(&(prev)->switch_lock);  \
 150 } while (0)
 151
 152 #define task_running(rq, p) \
 153         ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
 154
 155         /* See what happens when you design the chip correctly?
 156          *
 157          * We tell gcc we clobber all non-fixed-usage registers except
 158          * for l0/l1.  It will use one for 'next' and the other to hold
 159          * the output value of 'last'.  'next' is not referenced again
 160          * past the invocation of switch_to in the scheduler, so we need
 161          * not preserve it's value.  Hairy, but it lets us remove 2 loads
 162          * and 2 stores in this critical code path.  -DaveM
 163          */
 164 #if __GNUC__ >= 3
 165 #define EXTRA_CLOBBER ,"%l1"
 166 #else
 167 #define EXTRA_CLOBBER
 168 #endif
 169 #define switch_to(prev, next, last)                                     \
 170 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
 171                 unsigned long __tmp;                                    \
 172                 read_pcr(__tmp);                                        \
 173                 current_thread_info()->pcr_reg = __tmp;                 \
 174                 read_pic(__tmp);                                        \
 175                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
 176                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
 177         }                                                               \
 178         flush_tlb_pending();                                            \
 179         save_and_clear_fpu();                                           \
 180         /* If you are tempted to conditionalize the following */        \
 181         /* so that ASI is only written if it changes, think again. */   \
 182         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
 183         : : "r" (__thread_flag_byte_ptr(next->thread_info)[TI_FLAG_BYTE_CURRENT_DS]));\
 184         __asm__ __volatile__(                                           \
 185         "mov    %%g4, %%g7\n\t"                                         \
 186         "wrpr   %%g0, 0x95, %%pstate\n\t"                               \
 187         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
 188         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
 189         "rdpr   %%wstate, %%o5\n\t"                                     \
 190         "stx    %%o6, [%%g6 + %3]\n\t"                                  \
 191         "stb    %%o5, [%%g6 + %2]\n\t"                                  \
 192         "rdpr   %%cwp, %%o5\n\t"                                        \
 193         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
 194         "mov    %1, %%g6\n\t"                                           \
 195         "ldub   [%1 + %5], %%g1\n\t"                                    \
 196         "wrpr   %%g1, %%cwp\n\t"                                        \
 197         "ldx    [%%g6 + %3], %%o6\n\t"                                  \
 198         "ldub   [%%g6 + %2], %%o5\n\t"                                  \
 199         "ldx    [%%g6 + %4], %%o7\n\t"                                  \
 200         "mov    %%g6, %%l2\n\t"                                         \
 201         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
 202         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
 203         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
 204         "wrpr   %%g0, 0x94, %%pstate\n\t"                               \
 205         "mov    %%l2, %%g6\n\t"                                         \
 206         "ldx    [%%g6 + %7], %%g4\n\t"                                  \
 207         "wrpr   %%g0, 0x96, %%pstate\n\t"                               \
 208         "andcc  %%o7, %6, %%g0\n\t"                                     \
 209         "beq,pt %%icc, 1f\n\t"                                          \
 210         " mov   %%g7, %0\n\t"                                           \
 211         "b,a ret_from_syscall\n\t"                                      \
 212         "1:\n\t"                                                        \
 213         : "=&r" (last)                                                  \
 214         : "0" (next->thread_info),                                      \
 215           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP),  \
 216           "i" (_TIF_NEWCHILD), "i" (TI_TASK)                            \
 217         : "cc",                                                         \
 218                 "g1", "g2", "g3",                   "g7",               \
 219                       "l2", "l3", "l4", "l5", "l6", "l7",               \
 220           "i0", "i1", "i2", "i3", "i4", "i5",                           \
 221           "o0", "o1", "o2", "o3", "o4", "o5",       "o7" EXTRA_CLOBBER);\
 222         /* If you fuck with this, update ret_from_syscall code too. */  \
 223         if (test_thread_flag(TIF_PERFCTR)) {                            \
 224                 write_pcr(current_thread_info()->pcr_reg);              \
 225                 reset_pic();                                            \
 226         }                                                               \
 227 } while(0)
 228
 229 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
 230 {
 231         unsigned long tmp1, tmp2;
 232
 233         __asm__ __volatile__(
 234 "       membar          #StoreLoad | #LoadLoad\n"
 235 "       mov             %0, %1\n"
 236 "1:     lduw            [%4], %2\n"
 237 "       cas             [%4], %2, %0\n"
 238 "       cmp             %2, %0\n"
 239 "       bne,a,pn        %%icc, 1b\n"
 240 "        mov            %1, %0\n"
 241 "       membar          #StoreLoad | #StoreStore\n"
 242         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 243         : "0" (val), "r" (m)
 244         : "cc", "memory");
 245         return val;
 246 }
 247
 248 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
 249 {
 250         unsigned long tmp1, tmp2;
 251
 252         __asm__ __volatile__(
 253 "       membar          #StoreLoad | #LoadLoad\n"
 254 "       mov             %0, %1\n"
 255 "1:     ldx             [%4], %2\n"
 256 "       casx            [%4], %2, %0\n"
 257 "       cmp             %2, %0\n"
 258 "       bne,a,pn        %%xcc, 1b\n"
 259 "        mov            %1, %0\n"
 260 "       membar          #StoreLoad | #StoreStore\n"
 261         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 262         : "0" (val), "r" (m)
 263         : "cc", "memory");
 264         return val;
 265 }
 266
 267 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 268 #define tas(ptr) (xchg((ptr),1))
 269
 270 extern void __xchg_called_with_bad_pointer(void);
 271
 272 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
 273                                        int size)
 274 {
 275         switch (size) {
 276         case 4:
 277                 return xchg32(ptr, x);
 278         case 8:
 279                 return xchg64(ptr, x);
 280         };
 281         __xchg_called_with_bad_pointer();
 282         return x;
 283 }
 284
 285 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 286
 287 /*
 288  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 289  * store NEW in MEM.  Return the initial value in MEM.  Success is
 290  * indicated by comparing RETURN with OLD.
 291  */
 292
 293 #define __HAVE_ARCH_CMPXCHG 1
 294
 295 static __inline__ unsigned long
 296 __cmpxchg_u32(volatile int *m, int old, int new)
 297 {
 298         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
 299                              "cas [%2], %3, %0\n\t"
 300                              "membar #StoreLoad | #StoreStore"
 301                              : "=&r" (new)
 302                              : "0" (new), "r" (m), "r" (old)
 303                              : "memory");
 304
 305         return new;
 306 }
 307
 308 static __inline__ unsigned long
 309 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
 310 {
 311         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
 312                              "casx [%2], %3, %0\n\t"
 313                              "membar #StoreLoad | #StoreStore"
 314                              : "=&r" (new)
 315                              : "0" (new), "r" (m), "r" (old)
 316                              : "memory");
 317
 318         return new;
 319 }
 320
 321 /* This function doesn't exist, so you'll get a linker error
 322    if something tries to do an invalid cmpxchg().  */
 323 extern void __cmpxchg_called_with_bad_pointer(void);
 324
 325 static __inline__ unsigned long
 326 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 327 {
 328         switch (size) {
 329                 case 4:
 330                         return __cmpxchg_u32(ptr, old, new);
 331                 case 8:
 332                         return __cmpxchg_u64(ptr, old, new);
 333         }
 334         __cmpxchg_called_with_bad_pointer();
 335         return old;
 336 }
 337
 338 #define cmpxchg(ptr,o,n)                                                 \
 339   ({                                                                     \
 340      __typeof__(*(ptr)) _o_ = (o);                                       \
 341      __typeof__(*(ptr)) _n_ = (n);                                       \
 342      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 343                                     (unsigned long)_n_, sizeof(*(ptr))); \
 344   })
 345
 346 #endif /* !(__ASSEMBLY__) */
 347
 348 #define arch_align_stack(x) (x)
 349
 350 #endif /* !(__SPARC64_SYSTEM_H) */