include/asm-x86_64/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define                 APIC_ID_MASK            (0x0F<<24)
  15 #define                 GET_APIC_ID(x)          (((x)>>24)&0x0F)
  16 #define         APIC_LVR        0x30
  17 #define                 APIC_LVR_MASK           0xFF00FF
  18 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  19 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  20 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  21 #define         APIC_TASKPRI    0x80
  22 #define                 APIC_TPRI_MASK          0xFF
  23 #define         APIC_ARBPRI     0x90
  24 #define                 APIC_ARBPRI_MASK        0xFF
  25 #define         APIC_PROCPRI    0xA0
  26 #define         APIC_EOI        0xB0
  27 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  28 #define         APIC_RRR        0xC0
  29 #define         APIC_LDR        0xD0
  30 #define                 APIC_LDR_MASK           (0xFF<<24)
  31 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  32 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  33 #define                 APIC_ALL_CPUS           0xFF
  34 #define         APIC_DFR        0xE0
  35 #define         APIC_SPIV       0xF0
  36 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  37 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  38 #define         APIC_ISR        0x100
  39 #define         APIC_TMR        0x180
  40 #define         APIC_IRR        0x200
  41 #define         APIC_ESR        0x280
  42 #define                 APIC_ESR_SEND_CS        0x00001
  43 #define                 APIC_ESR_RECV_CS        0x00002
  44 #define                 APIC_ESR_SEND_ACC       0x00004
  45 #define                 APIC_ESR_RECV_ACC       0x00008
  46 #define                 APIC_ESR_SENDILL        0x00020
  47 #define                 APIC_ESR_RECVILL        0x00040
  48 #define                 APIC_ESR_ILLREGA        0x00080
  49 #define         APIC_ICR        0x300
  50 #define                 APIC_DEST_SELF          0x40000
  51 #define                 APIC_DEST_ALLINC        0x80000
  52 #define                 APIC_DEST_ALLBUT        0xC0000
  53 #define                 APIC_ICR_RR_MASK        0x30000
  54 #define                 APIC_ICR_RR_INVALID     0x00000
  55 #define                 APIC_ICR_RR_INPROG      0x10000
  56 #define                 APIC_ICR_RR_VALID       0x20000
  57 #define                 APIC_INT_LEVELTRIG      0x08000
  58 #define                 APIC_INT_ASSERT         0x04000
  59 #define                 APIC_ICR_BUSY           0x01000
  60 #define                 APIC_DEST_LOGICAL       0x00800
  61 #define                 APIC_DM_FIXED           0x00000
  62 #define                 APIC_DM_LOWEST          0x00100
  63 #define                 APIC_DM_SMI             0x00200
  64 #define                 APIC_DM_REMRD           0x00300
  65 #define                 APIC_DM_NMI             0x00400
  66 #define                 APIC_DM_INIT            0x00500
  67 #define                 APIC_DM_STARTUP         0x00600
  68 #define                 APIC_DM_EXTINT          0x00700
  69 #define                 APIC_VECTOR_MASK        0x000FF
  70 #define         APIC_ICR2       0x310
  71 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  72 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  73 #define         APIC_LVTT       0x320
  74 #define         APIC_LVTTHMR    0x330
  75 #define         APIC_LVTPC      0x340
  76 #define         APIC_LVT0       0x350
  77 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  78 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  79 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  80 #define                 APIC_TIMER_BASE_CLKIN           0x0
  81 #define                 APIC_TIMER_BASE_TMBASE          0x1
  82 #define                 APIC_TIMER_BASE_DIV             0x2
  83 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  84 #define                 APIC_LVT_MASKED                 (1<<16)
  85 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  86 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  87 #define                 APIC_INPUT_POLARITY             (1<<13)
  88 #define                 APIC_SEND_PENDING               (1<<12)
  89 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  90 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  91 #define                         APIC_MODE_FIXED         0x0
  92 #define                         APIC_MODE_NMI           0x4
  93 #define                         APIC_MODE_EXINT         0x7
  94 #define         APIC_LVT1       0x360
  95 #define         APIC_LVTERR     0x370
  96 #define         APIC_TMICT      0x380
  97 #define         APIC_TMCCT      0x390
  98 #define         APIC_TDCR       0x3E0
  99 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 100 #define                 APIC_TDR_DIV_1          0xB
 101 #define                 APIC_TDR_DIV_2          0x0
 102 #define                 APIC_TDR_DIV_4          0x1
 103 #define                 APIC_TDR_DIV_8          0x2
 104 #define                 APIC_TDR_DIV_16         0x3
 105 #define                 APIC_TDR_DIV_32         0x8
 106 #define                 APIC_TDR_DIV_64         0x9
 107 #define                 APIC_TDR_DIV_128        0xA
 108
 109 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 110
 111 #define MAX_IO_APICS 16
 112
 113 /*
 114  * the local APIC register structure, memory mapped. Not terribly well
 115  * tested, but we might eventually use this one in the future - the
 116  * problem why we cannot use it right now is the P5 APIC, it has an
 117  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 118  */
 119 #define u32 unsigned int
 120
 121 #define lapic ((volatile struct local_apic *)APIC_BASE)
 122
 123 struct local_apic {
 124
 125 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 126
 127 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 128
 129 /*020*/ struct { /* APIC ID Register */
 130                 u32   __reserved_1      : 24,
 131                         phys_apic_id    :  4,
 132                         __reserved_2    :  4;
 133                 u32 __reserved[3];
 134         } id;
 135
 136 /*030*/ const
 137         struct { /* APIC Version Register */
 138                 u32   version           :  8,
 139                         __reserved_1    :  8,
 140                         max_lvt         :  8,
 141                         __reserved_2    :  8;
 142                 u32 __reserved[3];
 143         } version;
 144
 145 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 146
 147 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 148
 149 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 150
 151 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 152
 153 /*080*/ struct { /* Task Priority Register */
 154                 u32   priority  :  8,
 155                         __reserved_1    : 24;
 156                 u32 __reserved_2[3];
 157         } tpr;
 158
 159 /*090*/ const
 160         struct { /* Arbitration Priority Register */
 161                 u32   priority  :  8,
 162                         __reserved_1    : 24;
 163                 u32 __reserved_2[3];
 164         } apr;
 165
 166 /*0A0*/ const
 167         struct { /* Processor Priority Register */
 168                 u32   priority  :  8,
 169                         __reserved_1    : 24;
 170                 u32 __reserved_2[3];
 171         } ppr;
 172
 173 /*0B0*/ struct { /* End Of Interrupt Register */
 174                 u32   eoi;
 175                 u32 __reserved[3];
 176         } eoi;
 177
 178 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 179
 180 /*0D0*/ struct { /* Logical Destination Register */
 181                 u32   __reserved_1      : 24,
 182                         logical_dest    :  8;
 183                 u32 __reserved_2[3];
 184         } ldr;
 185
 186 /*0E0*/ struct { /* Destination Format Register */
 187                 u32   __reserved_1      : 28,
 188                         model           :  4;
 189                 u32 __reserved_2[3];
 190         } dfr;
 191
 192 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 193                 u32     spurious_vector :  8,
 194                         apic_enabled    :  1,
 195                         focus_cpu       :  1,
 196                         __reserved_2    : 22;
 197                 u32 __reserved_3[3];
 198         } svr;
 199
 200 /*100*/ struct { /* In Service Register */
 201 /*170*/         u32 bitfield;
 202                 u32 __reserved[3];
 203         } isr [8];
 204
 205 /*180*/ struct { /* Trigger Mode Register */
 206 /*1F0*/         u32 bitfield;
 207                 u32 __reserved[3];
 208         } tmr [8];
 209
 210 /*200*/ struct { /* Interrupt Request Register */
 211 /*270*/         u32 bitfield;
 212                 u32 __reserved[3];
 213         } irr [8];
 214
 215 /*280*/ union { /* Error Status Register */
 216                 struct {
 217                         u32   send_cs_error                     :  1,
 218                                 receive_cs_error                :  1,
 219                                 send_accept_error               :  1,
 220                                 receive_accept_error            :  1,
 221                                 __reserved_1                    :  1,
 222                                 send_illegal_vector             :  1,
 223                                 receive_illegal_vector          :  1,
 224                                 illegal_register_address        :  1,
 225                                 __reserved_2                    : 24;
 226                         u32 __reserved_3[3];
 227                 } error_bits;
 228                 struct {
 229                         u32 errors;
 230                         u32 __reserved_3[3];
 231                 } all_errors;
 232         } esr;
 233
 234 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 235
 236 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 237
 238 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 239
 240 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 241
 242 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 243
 244 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 245
 246 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 247
 248 /*300*/ struct { /* Interrupt Command Register 1 */
 249                 u32   vector                    :  8,
 250                         delivery_mode           :  3,
 251                         destination_mode        :  1,
 252                         delivery_status         :  1,
 253                         __reserved_1            :  1,
 254                         level                   :  1,
 255                         trigger                 :  1,
 256                         __reserved_2            :  2,
 257                         shorthand               :  2,
 258                         __reserved_3            :  12;
 259                 u32 __reserved_4[3];
 260         } icr1;
 261
 262 /*310*/ struct { /* Interrupt Command Register 2 */
 263                 union {
 264                         u32   __reserved_1      : 24,
 265                                 phys_dest       :  4,
 266                                 __reserved_2    :  4;
 267                         u32   __reserved_3      : 24,
 268                                 logical_dest    :  8;
 269                 } dest;
 270                 u32 __reserved_4[3];
 271         } icr2;
 272
 273 /*320*/ struct { /* LVT - Timer */
 274                 u32   vector            :  8,
 275                         __reserved_1    :  4,
 276                         delivery_status :  1,
 277                         __reserved_2    :  3,
 278                         mask            :  1,
 279                         timer_mode      :  1,
 280                         __reserved_3    : 14;
 281                 u32 __reserved_4[3];
 282         } lvt_timer;
 283
 284 /*330*/ struct { /* LVT - Thermal Sensor */
 285                 u32  vector             :  8,
 286                         delivery_mode   :  3,
 287                         __reserved_1    :  1,
 288                         delivery_status :  1,
 289                         __reserved_2    :  3,
 290                         mask            :  1,
 291                         __reserved_3    : 15;
 292                 u32 __reserved_4[3];
 293         } lvt_thermal;
 294
 295 /*340*/ struct { /* LVT - Performance Counter */
 296                 u32   vector            :  8,
 297                         delivery_mode   :  3,
 298                         __reserved_1    :  1,
 299                         delivery_status :  1,
 300                         __reserved_2    :  3,
 301                         mask            :  1,
 302                         __reserved_3    : 15;
 303                 u32 __reserved_4[3];
 304         } lvt_pc;
 305
 306 /*350*/ struct { /* LVT - LINT0 */
 307                 u32   vector            :  8,
 308                         delivery_mode   :  3,
 309                         __reserved_1    :  1,
 310                         delivery_status :  1,
 311                         polarity        :  1,
 312                         remote_irr      :  1,
 313                         trigger         :  1,
 314                         mask            :  1,
 315                         __reserved_2    : 15;
 316                 u32 __reserved_3[3];
 317         } lvt_lint0;
 318
 319 /*360*/ struct { /* LVT - LINT1 */
 320                 u32   vector            :  8,
 321                         delivery_mode   :  3,
 322                         __reserved_1    :  1,
 323                         delivery_status :  1,
 324                         polarity        :  1,
 325                         remote_irr      :  1,
 326                         trigger         :  1,
 327                         mask            :  1,
 328                         __reserved_2    : 15;
 329                 u32 __reserved_3[3];
 330         } lvt_lint1;
 331
 332 /*370*/ struct { /* LVT - Error */
 333                 u32   vector            :  8,
 334                         __reserved_1    :  4,
 335                         delivery_status :  1,
 336                         __reserved_2    :  3,
 337                         mask            :  1,
 338                         __reserved_3    : 15;
 339                 u32 __reserved_4[3];
 340         } lvt_error;
 341
 342 /*380*/ struct { /* Timer Initial Count Register */
 343                 u32   initial_count;
 344                 u32 __reserved_2[3];
 345         } timer_icr;
 346
 347 /*390*/ const
 348         struct { /* Timer Current Count Register */
 349                 u32   curr_count;
 350                 u32 __reserved_2[3];
 351         } timer_ccr;
 352
 353 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 354
 355 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 356
 357 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 358
 359 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 360
 361 /*3E0*/ struct { /* Timer Divide Configuration Register */
 362                 u32   divisor           :  4,
 363                         __reserved_1    : 28;
 364                 u32 __reserved_2[3];
 365         } timer_dcr;
 366
 367 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 368
 369 } __attribute__ ((packed));
 370
 371 #undef u32
 372
 373 #define BAD_APICID 0xFFu
 374
 375 #endif