2 * include/asm-x86_64/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_X86_64_PROCESSOR_H
8 #define __ASM_X86_64_PROCESSOR_H
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
15 #include <linux/threads.h>
17 #include <asm/current.h>
18 #include <asm/system.h>
19 #include <asm/mmsegment.h>
20 #include <asm/percpu.h>
21 #include <linux/personality.h>
22 #include <linux/cpumask.h>
24 #define TF_MASK 0x00000100
25 #define IF_MASK 0x00000200
26 #define IOPL_MASK 0x00003000
27 #define NT_MASK 0x00004000
28 #define VM_MASK 0x00020000
29 #define AC_MASK 0x00040000
30 #define VIF_MASK 0x00080000 /* virtual interrupt flag */
31 #define VIP_MASK 0x00100000 /* virtual interrupt pending */
32 #define ID_MASK 0x00200000
34 #define desc_empty(desc) \
35 (!((desc)->a | (desc)->b))
37 #define desc_equal(desc1, desc2) \
38 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
41 * Default implementation of macro that returns current
42 * instruction pointer ("program counter").
44 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
47 * CPU type and hardware bug flags. Kept separately for each CPU.
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
55 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
56 __u32 x86_capability[NCAPINTS];
57 char x86_vendor_id[16];
58 char x86_model_id[64];
59 int x86_cache_size; /* in KB */
61 int x86_cache_alignment;
62 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
63 __u8 x86_virt_bits, x86_phys_bits;
64 __u8 x86_max_cores; /* cpuid returned max cores value */
66 __u32 extended_cpuid_level; /* Max extended CPUID function supported */
67 unsigned long loops_per_jiffy;
69 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
73 __u8 booted_cores; /* number of cores as seen by OS */
74 __u8 phys_proc_id; /* Physical Processor id. */
75 __u8 cpu_core_id; /* Core id. */
77 } ____cacheline_aligned;
79 #define X86_VENDOR_INTEL 0
80 #define X86_VENDOR_CYRIX 1
81 #define X86_VENDOR_AMD 2
82 #define X86_VENDOR_UMC 3
83 #define X86_VENDOR_NEXGEN 4
84 #define X86_VENDOR_CENTAUR 5
85 #define X86_VENDOR_RISE 6
86 #define X86_VENDOR_TRANSMETA 7
87 #define X86_VENDOR_NUM 8
88 #define X86_VENDOR_UNKNOWN 0xff
91 extern struct cpuinfo_x86 cpu_data[];
92 #define current_cpu_data cpu_data[smp_processor_id()]
94 #define cpu_data (&boot_cpu_data)
95 #define current_cpu_data boot_cpu_data
98 extern char ignore_irq13;
100 extern void identify_cpu(struct cpuinfo_x86 *);
101 extern void print_cpu_info(struct cpuinfo_x86 *);
102 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
103 extern unsigned short num_cache_leaves;
108 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
109 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
110 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
111 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
112 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
113 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
114 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
115 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
116 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
117 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
118 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
119 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
120 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
121 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
122 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
123 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
124 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
127 * Intel CPU features in CR4
129 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
130 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
131 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
132 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
133 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
134 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
135 #define X86_CR4_MCE 0x0040 /* Machine check enable */
136 #define X86_CR4_PGE 0x0080 /* enable global pages */
137 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
138 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
139 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
142 * Save the cr4 feature set we're using (ie
143 * Pentium 4MB enable and PPro Global page
144 * enable), so that any CPU's that boot up
145 * after us can get the correct flags.
147 extern unsigned long mmu_cr4_features;
149 static inline void set_in_cr4 (unsigned long mask)
151 mmu_cr4_features |= mask;
152 __asm__("movq %%cr4,%%rax\n\t"
159 static inline void clear_in_cr4 (unsigned long mask)
161 mmu_cr4_features &= ~mask;
162 __asm__("movq %%cr4,%%rax\n\t"
174 #define MCA_bus__is_a_macro
177 * User space process size. 47bits minus one guard page.
179 #define TASK_SIZE64 (0x800000000000UL - 4096)
181 /* This decides where the kernel will search for a free chunk of vm
182 * space during mmap's.
184 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
186 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
187 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
189 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
194 #define IO_BITMAP_BITS 65536
195 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
196 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
197 #ifndef CONFIG_X86_NO_TSS
198 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
200 #define INVALID_IO_BITMAP_OFFSET 0x8000
202 struct i387_fxsave_struct {
211 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
212 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 128 bytes */
214 } __attribute__ ((aligned (16)));
217 struct i387_fxsave_struct fxsave;
220 #ifndef CONFIG_X86_NO_TSS
233 * The extra 1 is there because the CPU will access an
234 * additional byte beyond the end of the IO permission
235 * bitmap. The extra byte must be all 1 bits, and must
236 * be within the limit. Thus we have:
238 * 128 bytes, the bitmap itself, for ports 0..0x3ff
239 * 8 bytes, for an extra "long" of ~0UL
241 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
242 } __attribute__((packed)) ____cacheline_aligned;
244 DECLARE_PER_CPU(struct tss_struct,init_tss);
248 extern struct cpuinfo_x86 boot_cpu_data;
249 /* Save the original ist values for checking stack pointers during debugging */
251 unsigned long ist[7];
253 DECLARE_PER_CPU(struct orig_ist, orig_ist);
255 #ifdef CONFIG_X86_VSMP
256 #define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
257 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
259 #define ARCH_MIN_TASKALIGN 16
260 #define ARCH_MIN_MMSTRUCT_ALIGN 0
263 struct thread_struct {
266 unsigned long userrsp; /* Copy from PDA */
269 unsigned short es, ds, fsindex, gsindex;
270 /* Hardware debugging registers */
271 unsigned long debugreg0;
272 unsigned long debugreg1;
273 unsigned long debugreg2;
274 unsigned long debugreg3;
275 unsigned long debugreg6;
276 unsigned long debugreg7;
278 unsigned long cr2, trap_no, error_code;
279 /* floating point info */
280 union i387_union i387 __attribute__((aligned(16)));
281 /* IO permissions. the bitmap could be moved into the GDT, that would make
282 switch faster for a limited number of ioperm using tasks. -AK */
284 unsigned long *io_bitmap_ptr;
285 unsigned io_bitmap_max;
286 /* cached TLS descriptors. */
287 u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
289 } __attribute__((aligned(16)));
291 #define INIT_THREAD { \
292 .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
295 #ifndef CONFIG_X86_NO_TSS
297 .rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
302 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
304 #define start_thread(regs,new_rip,new_rsp) do { \
305 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
307 (regs)->rip = (new_rip); \
308 (regs)->rsp = (new_rsp); \
309 write_pda(oldrsp, (new_rsp)); \
310 (regs)->cs = __USER_CS; \
311 (regs)->ss = __USER_DS; \
312 (regs)->eflags = 0x200; \
316 #define get_debugreg(var, register) \
317 var = HYPERVISOR_get_debugreg(register)
318 #define set_debugreg(value, register) \
319 HYPERVISOR_set_debugreg(register, value)
324 /* Free all resources held by a thread. */
325 extern void release_thread(struct task_struct *);
327 /* Prepare to copy thread state - unlazy all lazy status */
328 extern void prepare_to_copy(struct task_struct *tsk);
331 * create a kernel thread without removing it from tasklists
333 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
336 * Return saved PC of a blocked thread.
337 * What is this good for? it will be always the scheduler or ret_from_fork.
339 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
341 extern unsigned long get_wchan(struct task_struct *p);
342 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.rsp0 - 1)
343 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->rip)
344 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
347 struct microcode_header {
355 unsigned int datasize;
356 unsigned int totalsize;
357 unsigned int reserved[3];
361 struct microcode_header hdr;
362 unsigned int bits[0];
365 typedef struct microcode microcode_t;
366 typedef struct microcode_header microcode_header_t;
368 /* microcode format is extended from prescott processors */
369 struct extended_signature {
375 struct extended_sigtable {
378 unsigned int reserved[3];
379 struct extended_signature sigs[0];
383 #define ASM_NOP1 K8_NOP1
384 #define ASM_NOP2 K8_NOP2
385 #define ASM_NOP3 K8_NOP3
386 #define ASM_NOP4 K8_NOP4
387 #define ASM_NOP5 K8_NOP5
388 #define ASM_NOP6 K8_NOP6
389 #define ASM_NOP7 K8_NOP7
390 #define ASM_NOP8 K8_NOP8
393 #define K8_NOP1 ".byte 0x90\n"
394 #define K8_NOP2 ".byte 0x66,0x90\n"
395 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
396 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
397 #define K8_NOP5 K8_NOP3 K8_NOP2
398 #define K8_NOP6 K8_NOP3 K8_NOP3
399 #define K8_NOP7 K8_NOP4 K8_NOP3
400 #define K8_NOP8 K8_NOP4 K8_NOP4
402 #define ASM_NOP_MAX 8
404 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
405 static inline void rep_nop(void)
407 __asm__ __volatile__("rep;nop": : :"memory");
410 /* Stop speculative execution */
411 static inline void sync_core(void)
414 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
417 #define cpu_has_fpu 1
419 #define ARCH_HAS_PREFETCH
420 static inline void prefetch(void *x)
422 asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
425 #define ARCH_HAS_PREFETCHW 1
426 static inline void prefetchw(void *x)
428 alternative_input("prefetcht0 (%1)",
434 #define ARCH_HAS_SPINLOCK_PREFETCH 1
436 #define spin_lock_prefetch(x) prefetchw(x)
438 #define cpu_relax() rep_nop()
441 * NSC/Cyrix CPU configuration register indexes
443 #define CX86_CCR0 0xc0
444 #define CX86_CCR1 0xc1
445 #define CX86_CCR2 0xc2
446 #define CX86_CCR3 0xc3
447 #define CX86_CCR4 0xe8
448 #define CX86_CCR5 0xe9
449 #define CX86_CCR6 0xea
450 #define CX86_CCR7 0xeb
451 #define CX86_DIR0 0xfe
452 #define CX86_DIR1 0xff
453 #define CX86_ARR_BASE 0xc4
454 #define CX86_RCR_BASE 0xdc
457 * NSC/Cyrix CPU indexed register access macros
460 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
462 #define setCx86(reg, data) do { \
464 outb((data), 0x23); \
467 static inline void serialize_cpu(void)
469 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
472 static inline void __monitor(const void *eax, unsigned long ecx,
475 /* "monitor %eax,%ecx,%edx;" */
477 ".byte 0x0f,0x01,0xc8;"
478 : :"a" (eax), "c" (ecx), "d"(edx));
481 static inline void __mwait(unsigned long eax, unsigned long ecx)
483 /* "mwait %eax,%ecx;" */
485 ".byte 0x0f,0x01,0xc9;"
486 : :"a" (eax), "c" (ecx));
489 #define stack_current() \
491 struct thread_info *ti; \
492 asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
496 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
498 extern unsigned long boot_option_idle_override;
499 /* Boot loader type from the setup header */
500 extern int bootloader_type;
502 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
504 #endif /* __ASM_X86_64_PROCESSOR_H */