include/asm-x86_64/mach-xen/asm/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/config.h>
   5 #include <linux/kernel.h>
   6 #include <asm/segment.h>
   7 #include <asm/synch_bitops.h>
   8 #include <asm/hypervisor.h>
   9 #include <xen/interface/arch-x86_64.h>
  10
  11 #ifdef __KERNEL__
  12
  13 #ifdef CONFIG_SMP
  14 #define __vcpu_id smp_processor_id()
  15 #else
  16 #define __vcpu_id 0
  17 #endif
  18
  19 #ifdef CONFIG_SMP
  20 #define LOCK_PREFIX "lock ; "
  21 #else
  22 #define LOCK_PREFIX ""
  23 #endif
  24
  25 #define __STR(x) #x
  26 #define STR(x) __STR(x)
  27
  28 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  29 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  30
  31 /* frame pointer must be last for get_wchan */
  32 #define SAVE_CONTEXT    "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  33 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\n\t"
  34
  35 #define __EXTRA_CLOBBER  \
  36         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  37
  38 #define switch_to(prev,next,last) \
  39         asm volatile(SAVE_CONTEXT                                                   \
  40                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  41                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  42                      "call __switch_to\n\t"                                       \
  43                      ".globl thread_return\n"                                   \
  44                      "thread_return:\n\t"                                           \
  45                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  46                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  47                      LOCK "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"               \
  48                      "movq %%rax,%%rdi\n\t"                                       \
  49                      "jc   ret_from_fork\n\t"                                     \
  50                      RESTORE_CONTEXT                                                \
  51                      : "=a" (last)                                                \
  52                      : [next] "S" (next), [prev] "D" (prev),                      \
  53                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
  54                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  55                        [tif_fork] "i" (TIF_FORK),                         \
  56                        [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
  57                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  58                      : "memory", "cc" __EXTRA_CLOBBER)
  59
  60
  61 extern void load_gs_index(unsigned);
  62
  63 /*
  64  * Load a segment. Fall back on loading the zero
  65  * segment if something goes wrong..
  66  */
  67 #define loadsegment(seg,value)  \
  68         asm volatile("\n"                       \
  69                 "1:\t"                          \
  70                 "movl %k0,%%" #seg "\n"         \
  71                 "2:\n"                          \
  72                 ".section .fixup,\"ax\"\n"      \
  73                 "3:\t"                          \
  74                 "movl %1,%%" #seg "\n\t"        \
  75                 "jmp 2b\n"                      \
  76                 ".previous\n"                   \
  77                 ".section __ex_table,\"a\"\n\t" \
  78                 ".align 8\n\t"                  \
  79                 ".quad 1b,3b\n"                 \
  80                 ".previous"                     \
  81                 : :"r" (value), "r" (0))
  82
  83 #ifdef __KERNEL__
  84 struct alt_instr {
  85         __u8 *instr;            /* original instruction */
  86         __u8 *replacement;
  87         __u8  cpuid;            /* cpuid bit set for replacement */
  88         __u8  instrlen;         /* length of original instruction */
  89         __u8  replacementlen;   /* length of new instruction, <= instrlen */
  90         __u8  pad[5];
  91 };
  92 #endif
  93
  94 /*
  95  * Alternative instructions for different CPU types or capabilities.
  96  *
  97  * This allows to use optimized instructions even on generic binary
  98  * kernels.
  99  *
 100  * length of oldinstr must be longer or equal the length of newinstr
 101  * It can be padded with nops as needed.
 102  *
 103  * For non barrier like inlines please define new variants
 104  * without volatile and memory clobber.
 105  */
 106 #define alternative(oldinstr, newinstr, feature)        \
 107         asm volatile ("661:\n\t" oldinstr "\n662:\n"                 \
 108                       ".section .altinstructions,\"a\"\n"            \
 109                       "  .align 8\n"                                   \
 110                       "  .quad 661b\n"            /* label */          \
 111                       "  .quad 663f\n"            /* new instruction */ \
 112                       "  .byte %c0\n"             /* feature bit */    \
 113                       "  .byte 662b-661b\n"       /* sourcelen */      \
 114                       "  .byte 664f-663f\n"       /* replacementlen */ \
 115                       ".previous\n"                                     \
 116                       ".section .altinstr_replacement,\"ax\"\n"         \
 117                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 118                       ".previous" :: "i" (feature) : "memory")
 119
 120 /*
 121  * Alternative inline assembly with input.
 122  *
 123  * Peculiarities:
 124  * No memory clobber here.
 125  * Argument numbers start with 1.
 126  * Best is to use constraints that are fixed size (like (%1) ... "r")
 127  * If you use variable sized constraints like "m" or "g" in the
 128  * replacement make sure to pad to the worst case length.
 129  */
 130 #define alternative_input(oldinstr, newinstr, feature, input...)        \
 131         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
 132                       ".section .altinstructions,\"a\"\n"               \
 133                       "  .align 8\n"                                    \
 134                       "  .quad 661b\n"            /* label */           \
 135                       "  .quad 663f\n"            /* new instruction */ \
 136                       "  .byte %c0\n"             /* feature bit */     \
 137                       "  .byte 662b-661b\n"       /* sourcelen */       \
 138                       "  .byte 664f-663f\n"       /* replacementlen */  \
 139                       ".previous\n"                                     \
 140                       ".section .altinstr_replacement,\"ax\"\n"         \
 141                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 142                       ".previous" :: "i" (feature), ##input)
 143
 144 /* Like alternative_input, but with a single output argument */
 145 #define alternative_io(oldinstr, newinstr, feature, output, input...) \
 146         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
 147                       ".section .altinstructions,\"a\"\n"               \
 148                       "  .align 8\n"                                    \
 149                       "  .quad 661b\n"            /* label */           \
 150                       "  .quad 663f\n"            /* new instruction */ \
 151                       "  .byte %c[feat]\n"        /* feature bit */     \
 152                       "  .byte 662b-661b\n"       /* sourcelen */       \
 153                       "  .byte 664f-663f\n"       /* replacementlen */  \
 154                       ".previous\n"                                     \
 155                       ".section .altinstr_replacement,\"ax\"\n"         \
 156                       "663:\n\t" newinstr "\n664:\n"   /* replacement */ \
 157                       ".previous" : output : [feat] "i" (feature), ##input)
 158
 159 /*
 160  * Clear and set 'TS' bit respectively
 161  */
 162 #define clts() (HYPERVISOR_fpu_taskswitch(0))
 163
 164 static inline unsigned long read_cr0(void)
 165 {
 166         unsigned long cr0;
 167         asm volatile("movq %%cr0,%0" : "=r" (cr0));
 168         return cr0;
 169 }
 170
 171 static inline void write_cr0(unsigned long val)
 172 {
 173         asm volatile("movq %0,%%cr0" :: "r" (val));
 174 }
 175
 176 #define read_cr3() ({ \
 177         unsigned long __dummy; \
 178         asm("movq %%cr3,%0" : "=r" (__dummy)); \
 179         machine_to_phys(__dummy); \
 180 })
 181
 182 static inline unsigned long read_cr4(void)
 183 {
 184         unsigned long cr4;
 185         asm("movq %%cr4,%0" : "=r" (cr4));
 186         return cr4;
 187 }
 188
 189 static inline void write_cr4(unsigned long val)
 190 {
 191         asm volatile("movq %0,%%cr4" :: "r" (val));
 192 }
 193
 194 #define stts() (HYPERVISOR_fpu_taskswitch(1))
 195
 196 #define wbinvd() \
 197         __asm__ __volatile__ ("wbinvd": : :"memory");
 198
 199 /*
 200  * On SMP systems, when the scheduler does migration-cost autodetection,
 201  * it needs a way to flush as much of the CPU's caches as possible.
 202  */
 203 static inline void sched_cacheflush(void)
 204 {
 205         wbinvd();
 206 }
 207
 208 #endif  /* __KERNEL__ */
 209
 210 #define nop() __asm__ __volatile__ ("nop")
 211
 212 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 213
 214 #define tas(ptr) (xchg((ptr),1))
 215
 216 #define __xg(x) ((volatile long *)(x))
 217
 218 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
 219 {
 220         *ptr = val;
 221 }
 222
 223 #define _set_64bit set_64bit
 224
 225 /*
 226  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 227  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 228  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 229  */
 230 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 231 {
 232         switch (size) {
 233                 case 1:
 234                         __asm__ __volatile__("xchgb %b0,%1"
 235                                 :"=q" (x)
 236                                 :"m" (*__xg(ptr)), "0" (x)
 237                                 :"memory");
 238                         break;
 239                 case 2:
 240                         __asm__ __volatile__("xchgw %w0,%1"
 241                                 :"=r" (x)
 242                                 :"m" (*__xg(ptr)), "0" (x)
 243                                 :"memory");
 244                         break;
 245                 case 4:
 246                         __asm__ __volatile__("xchgl %k0,%1"
 247                                 :"=r" (x)
 248                                 :"m" (*__xg(ptr)), "0" (x)
 249                                 :"memory");
 250                         break;
 251                 case 8:
 252                         __asm__ __volatile__("xchgq %0,%1"
 253                                 :"=r" (x)
 254                                 :"m" (*__xg(ptr)), "0" (x)
 255                                 :"memory");
 256                         break;
 257         }
 258         return x;
 259 }
 260
 261 /*
 262  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 263  * store NEW in MEM.  Return the initial value in MEM.  Success is
 264  * indicated by comparing RETURN with OLD.
 265  */
 266
 267 #define __HAVE_ARCH_CMPXCHG 1
 268
 269 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 270                                       unsigned long new, int size)
 271 {
 272         unsigned long prev;
 273         switch (size) {
 274         case 1:
 275                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 276                                      : "=a"(prev)
 277                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 278                                      : "memory");
 279                 return prev;
 280         case 2:
 281                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 282                                      : "=a"(prev)
 283                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 284                                      : "memory");
 285                 return prev;
 286         case 4:
 287                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
 288                                      : "=a"(prev)
 289                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 290                                      : "memory");
 291                 return prev;
 292         case 8:
 293                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
 294                                      : "=a"(prev)
 295                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 296                                      : "memory");
 297                 return prev;
 298         }
 299         return old;
 300 }
 301
 302 #define cmpxchg(ptr,o,n)\
 303         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 304                                         (unsigned long)(n),sizeof(*(ptr))))
 305
 306 #ifdef CONFIG_SMP
 307 #define smp_mb()        mb()
 308 #define smp_rmb()       rmb()
 309 #define smp_wmb()       wmb()
 310 #define smp_read_barrier_depends()      do {} while(0)
 311 #else
 312 #define smp_mb()        barrier()
 313 #define smp_rmb()       barrier()
 314 #define smp_wmb()       barrier()
 315 #define smp_read_barrier_depends()      do {} while(0)
 316 #endif
 317
 318
 319 /*
 320  * Force strict CPU ordering.
 321  * And yes, this is required on UP too when we're talking
 322  * to devices.
 323  */
 324 #define mb()    asm volatile("mfence":::"memory")
 325 #define rmb()   asm volatile("lfence":::"memory")
 326
 327 #ifdef CONFIG_UNORDERED_IO
 328 #define wmb()   asm volatile("sfence" ::: "memory")
 329 #else
 330 #define wmb()   asm volatile("" ::: "memory")
 331 #endif
 332 #define read_barrier_depends()  do {} while(0)
 333 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 334 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 335
 336 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 337
 338
 339 /*
 340  * The use of 'barrier' in the following reflects their use as local-lock
 341  * operations. Reentrancy must be prevented (e.g., __cli()) /before/ following
 342  * critical operations are executed. All critical operations must complete
 343  * /before/ reentrancy is permitted (e.g., __sti()). Alpha architecture also
 344  * includes these barriers, for example.
 345  */
 346
 347 #define __cli()                                                         \
 348 do {                                                                    \
 349         vcpu_info_t *_vcpu;                                             \
 350         preempt_disable();                                              \
 351         _vcpu = &HYPERVISOR_shared_info->vcpu_info[__vcpu_id];          \
 352         _vcpu->evtchn_upcall_mask = 1;                                  \
 353         preempt_enable_no_resched();                                    \
 354         barrier();                                                      \
 355 } while (0)
 356
 357 #define __sti()                                                         \
 358 do {                                                                    \
 359         vcpu_info_t *_vcpu;                                             \
 360         barrier();                                                      \
 361         preempt_disable();                                              \
 362         _vcpu = &HYPERVISOR_shared_info->vcpu_info[__vcpu_id];          \
 363         _vcpu->evtchn_upcall_mask = 0;                                  \
 364         barrier(); /* unmask then check (avoid races) */                \
 365         if ( unlikely(_vcpu->evtchn_upcall_pending) )                   \
 366                 force_evtchn_callback();                                \
 367         preempt_enable();                                               \
 368 } while (0)
 369
 370 #define __save_flags(x)                                                 \
 371 do {                                                                    \
 372         vcpu_info_t *_vcpu;                                             \
 373         preempt_disable();                                              \
 374         _vcpu = &HYPERVISOR_shared_info->vcpu_info[__vcpu_id];          \
 375         (x) = _vcpu->evtchn_upcall_mask;                                \
 376         preempt_enable();                                               \
 377 } while (0)
 378
 379 #define __restore_flags(x)                                              \
 380 do {                                                                    \
 381         vcpu_info_t *_vcpu;                                             \
 382         barrier();                                                      \
 383         preempt_disable();                                              \
 384         _vcpu = &HYPERVISOR_shared_info->vcpu_info[__vcpu_id];          \
 385         if ((_vcpu->evtchn_upcall_mask = (x)) == 0) {                   \
 386                 barrier(); /* unmask then check (avoid races) */        \
 387                 if ( unlikely(_vcpu->evtchn_upcall_pending) )           \
 388                         force_evtchn_callback();                        \
 389                 preempt_enable();                                       \
 390         } else                                                          \
 391                 preempt_enable_no_resched();                            \
 392 } while (0)
 393
 394 #define __save_and_cli(x)                                               \
 395 do {                                                                    \
 396         vcpu_info_t *_vcpu;                                             \
 397         preempt_disable();                                              \
 398         _vcpu = &HYPERVISOR_shared_info->vcpu_info[__vcpu_id];          \
 399         (x) = _vcpu->evtchn_upcall_mask;                                \
 400         _vcpu->evtchn_upcall_mask = 1;                                  \
 401         preempt_enable_no_resched();                                    \
 402         barrier();                                                      \
 403 } while (0)
 404
 405 #define local_irq_save(x)       __save_and_cli(x)
 406 #define local_irq_restore(x)    __restore_flags(x)
 407 #define local_save_flags(x)     __save_flags(x)
 408 #define local_irq_disable()     __cli()
 409 #define local_irq_enable()      __sti()
 410
 411 /* Cannot use preempt_enable() here as we would recurse in preempt_sched(). */
 412 #define irqs_disabled()                                                 \
 413 ({      int ___x;                                                       \
 414         vcpu_info_t *_vcpu;                                             \
 415         preempt_disable();                                              \
 416         _vcpu = &HYPERVISOR_shared_info->vcpu_info[__vcpu_id];          \
 417         ___x = (_vcpu->evtchn_upcall_mask != 0);                        \
 418         preempt_enable_no_resched();                                    \
 419         ___x; })
 420
 421 void safe_halt(void);
 422 void halt(void);
 423
 424 void cpu_idle_wait(void);
 425
 426 extern unsigned long arch_align_stack(unsigned long sp);
 427
 428 #endif