include/asm-x86_64/mach-xen/asm/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/synch_bitops.h>
   7 #include <asm/hypervisor.h>
   8 #include <xen/interface/arch-x86_64.h>
   9
  10 #ifdef __KERNEL__
  11
  12 #ifdef CONFIG_SMP
  13 #define __vcpu_id smp_processor_id()
  14 #else
  15 #define __vcpu_id 0
  16 #endif
  17
  18 #define __STR(x) #x
  19 #define STR(x) __STR(x)
  20
  21 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  22 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  23
  24 /* frame pointer must be last for get_wchan */
  25 #define SAVE_CONTEXT    "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  26 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\n\t"
  27
  28 #define __EXTRA_CLOBBER  \
  29         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  30
  31 #define switch_to(prev,next,last) \
  32         asm volatile(SAVE_CONTEXT                                                   \
  33                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  34                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  35                      "call __switch_to\n\t"                                       \
  36                      ".globl thread_return\n"                                   \
  37                      "thread_return:\n\t"                                           \
  38                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  39                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  40                      LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
  41                      "movq %%rax,%%rdi\n\t"                                       \
  42                      "jc   ret_from_fork\n\t"                                     \
  43                      RESTORE_CONTEXT                                                \
  44                      : "=a" (last)                                                \
  45                      : [next] "S" (next), [prev] "D" (prev),                      \
  46                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
  47                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  48                        [tif_fork] "i" (TIF_FORK),                         \
  49                        [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
  50                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  51                      : "memory", "cc" __EXTRA_CLOBBER)
  52
  53
  54 extern void load_gs_index(unsigned);
  55
  56 /*
  57  * Load a segment. Fall back on loading the zero
  58  * segment if something goes wrong..
  59  */
  60 #define loadsegment(seg,value)  \
  61         asm volatile("\n"                       \
  62                 "1:\t"                          \
  63                 "movl %k0,%%" #seg "\n"         \
  64                 "2:\n"                          \
  65                 ".section .fixup,\"ax\"\n"      \
  66                 "3:\t"                          \
  67                 "movl %1,%%" #seg "\n\t"        \
  68                 "jmp 2b\n"                      \
  69                 ".previous\n"                   \
  70                 ".section __ex_table,\"a\"\n\t" \
  71                 ".align 8\n\t"                  \
  72                 ".quad 1b,3b\n"                 \
  73                 ".previous"                     \
  74                 : :"r" (value), "r" (0))
  75
  76 /*
  77  * Clear and set 'TS' bit respectively
  78  */
  79 #define clts() (HYPERVISOR_fpu_taskswitch(0))
  80
  81 static inline unsigned long read_cr0(void)
  82 {
  83         unsigned long cr0;
  84         asm volatile("movq %%cr0,%0" : "=r" (cr0));
  85         return cr0;
  86 }
  87
  88 static inline void write_cr0(unsigned long val)
  89 {
  90         asm volatile("movq %0,%%cr0" :: "r" (val));
  91 }
  92
  93 #define read_cr3() ({ \
  94         unsigned long __dummy; \
  95         asm("movq %%cr3,%0" : "=r" (__dummy)); \
  96         machine_to_phys(__dummy); \
  97 })
  98
  99 static inline unsigned long read_cr4(void)
 100 {
 101         unsigned long cr4;
 102         asm("movq %%cr4,%0" : "=r" (cr4));
 103         return cr4;
 104 }
 105
 106 static inline void write_cr4(unsigned long val)
 107 {
 108         asm volatile("movq %0,%%cr4" :: "r" (val));
 109 }
 110
 111 #define stts() (HYPERVISOR_fpu_taskswitch(1))
 112
 113 #define wbinvd() \
 114         __asm__ __volatile__ ("wbinvd": : :"memory");
 115
 116 /*
 117  * On SMP systems, when the scheduler does migration-cost autodetection,
 118  * it needs a way to flush as much of the CPU's caches as possible.
 119  */
 120 static inline void sched_cacheflush(void)
 121 {
 122         wbinvd();
 123 }
 124
 125 #endif  /* __KERNEL__ */
 126
 127 #define nop() __asm__ __volatile__ ("nop")
 128
 129 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 130
 131 #define tas(ptr) (xchg((ptr),1))
 132
 133 #define __xg(x) ((volatile long *)(x))
 134
 135 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
 136 {
 137         *ptr = val;
 138 }
 139
 140 #define _set_64bit set_64bit
 141
 142 /*
 143  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 144  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 145  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 146  */
 147 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 148 {
 149         switch (size) {
 150                 case 1:
 151                         __asm__ __volatile__("xchgb %b0,%1"
 152                                 :"=q" (x)
 153                                 :"m" (*__xg(ptr)), "0" (x)
 154                                 :"memory");
 155                         break;
 156                 case 2:
 157                         __asm__ __volatile__("xchgw %w0,%1"
 158                                 :"=r" (x)
 159                                 :"m" (*__xg(ptr)), "0" (x)
 160                                 :"memory");
 161                         break;
 162                 case 4:
 163                         __asm__ __volatile__("xchgl %k0,%1"
 164                                 :"=r" (x)
 165                                 :"m" (*__xg(ptr)), "0" (x)
 166                                 :"memory");
 167                         break;
 168                 case 8:
 169                         __asm__ __volatile__("xchgq %0,%1"
 170                                 :"=r" (x)
 171                                 :"m" (*__xg(ptr)), "0" (x)
 172                                 :"memory");
 173                         break;
 174         }
 175         return x;
 176 }
 177
 178 /*
 179  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 180  * store NEW in MEM.  Return the initial value in MEM.  Success is
 181  * indicated by comparing RETURN with OLD.
 182  */
 183
 184 #define __HAVE_ARCH_CMPXCHG 1
 185
 186 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 187                                       unsigned long new, int size)
 188 {
 189         unsigned long prev;
 190         switch (size) {
 191         case 1:
 192                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 193                                      : "=a"(prev)
 194                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 195                                      : "memory");
 196                 return prev;
 197         case 2:
 198                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 199                                      : "=a"(prev)
 200                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 201                                      : "memory");
 202                 return prev;
 203         case 4:
 204                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
 205                                      : "=a"(prev)
 206                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 207                                      : "memory");
 208                 return prev;
 209         case 8:
 210                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
 211                                      : "=a"(prev)
 212                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 213                                      : "memory");
 214                 return prev;
 215         }
 216         return old;
 217 }
 218
 219 #define cmpxchg(ptr,o,n)\
 220         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 221                                         (unsigned long)(n),sizeof(*(ptr))))
 222
 223 #ifdef CONFIG_SMP
 224 #define smp_mb()        mb()
 225 #define smp_rmb()       rmb()
 226 #define smp_wmb()       wmb()
 227 #define smp_read_barrier_depends()      do {} while(0)
 228 #else
 229 #define smp_mb()        barrier()
 230 #define smp_rmb()       barrier()
 231 #define smp_wmb()       barrier()
 232 #define smp_read_barrier_depends()      do {} while(0)
 233 #endif
 234
 235
 236 /*
 237  * Force strict CPU ordering.
 238  * And yes, this is required on UP too when we're talking
 239  * to devices.
 240  */
 241 #define mb()    asm volatile("mfence":::"memory")
 242 #define rmb()   asm volatile("lfence":::"memory")
 243
 244 #ifdef CONFIG_UNORDERED_IO
 245 #define wmb()   asm volatile("sfence" ::: "memory")
 246 #else
 247 #define wmb()   asm volatile("" ::: "memory")
 248 #endif
 249 #define read_barrier_depends()  do {} while(0)
 250 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 251
 252 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 253
 254 void safe_halt(void);
 255 void halt(void);
 256
 257 #include <linux/irqflags.h>
 258
 259 void cpu_idle_wait(void);
 260
 261 extern unsigned long arch_align_stack(unsigned long sp);
 262 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 263
 264 #endif