include/asm-x86_64/mmu_context.h

   1 #ifndef __X86_64_MMU_CONTEXT_H
   2 #define __X86_64_MMU_CONTEXT_H
   3
   4 #include <linux/config.h>
   5 #include <asm/desc.h>
   6 #include <asm/atomic.h>
   7 #include <asm/pgalloc.h>
   8 #include <asm/pda.h>
   9 #include <asm/pgtable.h>
  10 #include <asm/tlbflush.h>
  11
  12 /*
  13  * possibly do the LDT unload here?
  14  */
  15 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
  16 void destroy_context(struct mm_struct *mm);
  17
  18 #ifdef CONFIG_SMP
  19
  20 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  21 {
  22         if (read_pda(mmu_state) == TLBSTATE_OK)
  23                 write_pda(mmu_state, TLBSTATE_LAZY);
  24 }
  25 #else
  26 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  27 {
  28 }
  29 #endif
  30
  31 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  32                              struct task_struct *tsk)
  33 {
  34         unsigned cpu = smp_processor_id();
  35         if (likely(prev != next)) {
  36                 /* stop flush ipis for the previous mm */
  37                 clear_bit(cpu, &prev->cpu_vm_mask);
  38 #ifdef CONFIG_SMP
  39                 write_pda(mmu_state, TLBSTATE_OK);
  40                 write_pda(active_mm, next);
  41 #endif
  42                 set_bit(cpu, &next->cpu_vm_mask);
  43                 asm volatile("movq %0,%%cr3" :: "r" (__pa(next->pgd)) : "memory");
  44                 if (unlikely(next->context.ldt != prev->context.ldt))
  45                         load_LDT_nolock(&next->context, cpu);
  46         }
  47 #ifdef CONFIG_SMP
  48         else {
  49                 write_pda(mmu_state, TLBSTATE_OK);
  50                 if (read_pda(active_mm) != next)
  51                         out_of_line_bug();
  52                 if(!test_and_set_bit(cpu, &next->cpu_vm_mask)) {
  53                         /* We were in lazy tlb mode and leave_mm disabled
  54                          * tlb flush IPI delivery. We must reload CR3
  55                          * to make sure to use no freed page tables.
  56                          */
  57                         asm volatile("movq %0,%%cr3" :: "r" (__pa(next->pgd)) : "memory");
  58                         load_LDT_nolock(&next->context, cpu);
  59                 }
  60         }
  61 #endif
  62 }
  63
  64 #define deactivate_mm(tsk,mm)   do { \
  65         load_gs_index(0); \
  66         asm volatile("movl %0,%%fs"::"r"(0));  \
  67 } while(0)
  68
  69 #define activate_mm(prev, next) \
  70         switch_mm((prev),(next),NULL)
  71
  72
  73 #endif