include/asm-x86_64/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7
   8 /*
   9  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  10  *
  11  * Simple spin lock operations.  There are two variants, one clears IRQ's
  12  * on the local processor, one does not.
  13  *
  14  * We make no fairness assumptions. They have a cost.
  15  *
  16  * (the type definitions are in asm/spinlock_types.h)
  17  */
  18
  19 #define __raw_spin_is_locked(x) \
  20                 (*(volatile signed int *)(&(x)->slock) <= 0)
  21
  22 #define __raw_spin_lock_string \
  23         "\n1:\t" \
  24         LOCK_PREFIX " ; decl %0\n\t" \
  25         "js 2f\n" \
  26         LOCK_SECTION_START("") \
  27         "2:\t" \
  28         "rep;nop\n\t" \
  29         "cmpl $0,%0\n\t" \
  30         "jle 2b\n\t" \
  31         "jmp 1b\n" \
  32         LOCK_SECTION_END
  33
  34 #define __raw_spin_lock_string_up \
  35         "\n\tdecl %0"
  36
  37 #define __raw_spin_unlock_string \
  38         "movl $1,%0" \
  39                 :"=m" (lock->slock) : : "memory"
  40
  41 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  42 {
  43         asm volatile(__raw_spin_lock_string : "=m" (lock->slock) : : "memory");
  44 }
  45
  46 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  47
  48 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  49 {
  50         int oldval;
  51
  52         __asm__ __volatile__(
  53                 "xchgl %0,%1"
  54                 :"=q" (oldval), "=m" (lock->slock)
  55                 :"0" (0) : "memory");
  56
  57         return oldval > 0;
  58 }
  59
  60 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  61 {
  62         __asm__ __volatile__(
  63                 __raw_spin_unlock_string
  64         );
  65 }
  66
  67 #define __raw_spin_unlock_wait(lock) \
  68         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
  69
  70 /*
  71  * Read-write spinlocks, allowing multiple readers
  72  * but only one writer.
  73  *
  74  * NOTE! it is quite common to have readers in interrupts
  75  * but no interrupt writers. For those circumstances we
  76  * can "mix" irq-safe locks - any writer needs to get a
  77  * irq-safe write-lock, but readers can get non-irqsafe
  78  * read-locks.
  79  *
  80  * On x86, we implement read-write locks as a 32-bit counter
  81  * with the high bit (sign) being the "contended" bit.
  82  */
  83
  84 #define __raw_read_can_lock(x)          ((int)(x)->lock > 0)
  85 #define __raw_write_can_lock(x)         ((x)->lock == RW_LOCK_BIAS)
  86
  87 static inline void __raw_read_lock(raw_rwlock_t *rw)
  88 {
  89         __build_read_lock(rw);
  90 }
  91
  92 static inline void __raw_write_lock(raw_rwlock_t *rw)
  93 {
  94         __build_write_lock(rw);
  95 }
  96
  97 static inline int __raw_read_trylock(raw_rwlock_t *lock)
  98 {
  99         atomic_t *count = (atomic_t *)lock;
 100         atomic_dec(count);
 101         if (atomic_read(count) >= 0)
 102                 return 1;
 103         atomic_inc(count);
 104         return 0;
 105 }
 106
 107 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 108 {
 109         atomic_t *count = (atomic_t *)lock;
 110         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 111                 return 1;
 112         atomic_add(RW_LOCK_BIAS, count);
 113         return 0;
 114 }
 115
 116 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 117 {
 118         asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory");
 119 }
 120
 121 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 122 {
 123         asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0"
 124                                 : "=m" (rw->lock) : : "memory");
 125 }
 126
 127 #endif /* __ASM_SPINLOCK_H */