5 * Offsets into HPET Registers
9 u64 hpet_cap; /* capabilities */
10 u64 res0; /* reserved */
11 u64 hpet_config; /* configuration */
12 u64 res1; /* reserved */
13 u64 hpet_isr; /* interrupt status reg */
14 u64 res2[25]; /* reserved */
15 union { /* main counter */
18 unsigned long _hpet_mc;
20 u64 res3; /* reserved */
22 u64 hpet_config; /* configuration/cap */
23 union { /* timer compare register */
26 unsigned long _hpet_compare;
28 u64 hpet_fsb[2]; /* FSB route */
32 #define hpet_mc _u0._hpet_mc
33 #define hpet_compare _u1._hpet_compare
35 #define HPET_MAX_TIMERS (32)
38 * HPET general capabilities register
41 #define HPET_COUNTER_CLK_PERIOD_MASK (0xffffffff00000000ULL)
42 #define HPET_COUNTER_CLK_PERIOD_SHIFT (32UL)
43 #define HPET_VENDOR_ID_MASK (0x00000000ffff0000ULL)
44 #define HPET_VENDOR_ID_SHIFT (16ULL)
45 #define HPET_LEG_RT_CAP_MASK (0x8000)
46 #define HPET_COUNTER_SIZE_MASK (0x2000)
47 #define HPET_NUM_TIM_CAP_MASK (0x1f00)
48 #define HPET_NUM_TIM_CAP_SHIFT (8ULL)
51 * HPET general configuration register
54 #define HPET_LEG_RT_CNF_MASK (2UL)
55 #define HPET_ENABLE_CNF_MASK (1UL)
58 * HPET interrupt status register
61 #define HPET_ISR_CLEAR(HPET, TIMER) \
62 (HPET)->hpet_isr |= (1UL << TIMER)
65 * Timer configuration register
68 #define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL)
69 #define Tn_INI_ROUTE_CAP_SHIFT (32UL)
70 #define Tn_FSB_INT_DELCAP_MASK (0x8000UL)
71 #define Tn_FSB_INT_DELCAP_SHIFT (15)
72 #define Tn_FSB_EN_CNF_MASK (0x4000UL)
73 #define Tn_FSB_EN_CNF_SHIFT (14)
74 #define Tn_INT_ROUTE_CNF_MASK (0x3e00UL)
75 #define Tn_INT_ROUTE_CNF_SHIFT (9)
76 #define Tn_32MODE_CNF_MASK (0x0100UL)
77 #define Tn_VAL_SET_CNF_MASK (0x0040UL)
78 #define Tn_SIZE_CAP_MASK (0x0020UL)
79 #define Tn_PER_INT_CAP_MASK (0x0010UL)
80 #define Tn_TYPE_CNF_MASK (0x0008UL)
81 #define Tn_INT_ENB_CNF_MASK (0x0004UL)
82 #define Tn_INT_TYPE_CNF_MASK (0x0002UL)
85 * Timer FSB Interrupt Route Register
88 #define Tn_FSB_INT_ADDR_MASK (0xffffffff00000000ULL)
89 #define Tn_FSB_INT_ADDR_SHIFT (32UL)
90 #define Tn_FSB_INT_VAL_MASK (0x00000000ffffffffULL)
93 unsigned long hi_ireqfreq; /* Hz */
94 unsigned long hi_flags; /* information */
95 unsigned short hi_hpet;
96 unsigned short hi_timer;
99 #define HPET_INFO_PERIODIC 0x0001 /* timer is periodic */
101 #define HPET_IE_ON _IO('h', 0x01) /* interrupt on */
102 #define HPET_IE_OFF _IO('h', 0x02) /* interrupt off */
103 #define HPET_INFO _IOR('h', 0x03, struct hpet_info)
104 #define HPET_EPI _IO('h', 0x04) /* enable periodic */
105 #define HPET_DPI _IO('h', 0x05) /* disable periodic */
106 #define HPET_IRQFREQ _IOW('h', 0x6, unsigned long) /* IRQFREQ usec */
109 * exported interfaces
113 void (*ht_func) (void *);
119 unsigned long hd_address;
120 unsigned short hd_nirqs;
121 unsigned short hd_flags;
122 unsigned int hd_state; /* timer allocated */
123 unsigned int hd_irq[HPET_MAX_TIMERS];
126 #define HPET_DATA_PLATFORM 0x0001 /* platform call to hpet_alloc */
128 int hpet_alloc(struct hpet_data *);
129 int hpet_register(struct hpet_task *, int);
130 int hpet_unregister(struct hpet_task *);
131 int hpet_control(struct hpet_task *, unsigned int, unsigned long);
133 #endif /* !__HPET__ */