2 * I2O kernel space accessible structures/APIs
4 * (c) Copyright 1999, 2000 Red Hat Software
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 *************************************************************************
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
21 #ifdef __KERNEL__ /* This file to be included by kernel only */
23 #include <linux/i2o-dev.h>
25 /* How many different OSM's are we allowing */
26 #define MAX_I2O_MODULES 4
28 /* How many OSMs can register themselves for device status updates? */
29 #define I2O_MAX_MANAGERS 4
31 #include <asm/semaphore.h> /* Needed for MUTEX init macros */
32 #include <linux/config.h>
33 #include <linux/notifier.h>
34 #include <asm/atomic.h>
47 u32 initiator_context;
52 * Each I2O device entity has one or more of these. There is one
57 i2o_lct_entry lct_data; /* Device LCT information */
59 int i2oversion; /* I2O version supported. Actually
60 * there should be high and low
63 struct proc_dir_entry *proc_entry; /* /proc dir */
66 struct i2o_handler *owner;
68 /* Management users */
69 struct i2o_handler *managers[I2O_MAX_MANAGERS];
72 struct i2o_controller *controller; /* Controlling IOP */
73 struct i2o_device *next; /* Chain */
74 struct i2o_device *prev;
75 char dev_name[8]; /* linux /dev name if available */
79 * context queue entry, used for 32-bit context on 64-bit systems
81 struct i2o_context_list_element {
82 struct i2o_context_list_element *next;
89 * Each I2O controller has one of these objects
98 struct pci_dev *pdev; /* PCI device */
100 int short_req:1; /* Use small block sizes */
101 int dpt:1; /* Don't quiesce */
102 int raptor:1; /* split bar */
103 int promise:1; /* Promise controller */
109 struct notifier_block *event_notifer; /* Events */
111 struct i2o_device *devices; /* I2O device chain */
112 struct i2o_controller *next; /* Controller chain */
113 void *post_port; /* Inbout port address */
114 void *reply_port; /* Outbound port address */
115 void *irq_mask; /* Interrupt register address */
117 /* Dynamic LCT related data */
118 struct semaphore lct_sem;
122 i2o_status_block *status_block; /* IOP status block */
123 dma_addr_t status_block_phys;
124 i2o_lct *lct; /* Logical Config Table */
126 i2o_lct *dlct; /* Temp LCT */
127 dma_addr_t dlct_phys;
128 i2o_hrt *hrt; /* HW Resource Table */
132 void *base_virt; /* base virtual address */
133 unsigned long base_phys; /* base physical address */
135 void *msg_virt; /* messages virtual address */
136 unsigned long msg_phys; /* messages physical address */
138 int battery:1; /* Has a battery backup */
139 int io_alloc:1; /* An I/O resource was allocated */
140 int mem_alloc:1; /* A memory resource was allocated */
142 struct resource io_resource; /* I/O resource allocated to the IOP */
143 struct resource mem_resource; /* Mem resource allocated to the IOP */
145 struct proc_dir_entry *proc_entry; /* /proc dir */
148 void *page_frame; /* Message buffers */
149 dma_addr_t page_frame_map; /* Cache map */
150 #if BITS_PER_LONG == 64
151 spinlock_t context_list_lock; /* lock for context_list */
152 struct i2o_context_list_element *context_list; /* list of context id's
158 * OSM resgistration block
160 * Each OSM creates at least one of these and registers it with the
161 * I2O core through i2o_register_handler. An OSM may want to
162 * register more than one if it wants a fast path to a reply
163 * handler by having a separate initiator context for each
168 /* Message reply handler */
169 void (*reply)(struct i2o_handler *, struct i2o_controller *,
170 struct i2o_message *);
172 /* New device notification handler */
173 void (*new_dev_notify)(struct i2o_controller *, struct i2o_device *);
175 /* Device deltion handler */
176 void (*dev_del_notify)(struct i2o_controller *, struct i2o_device *);
178 /* Reboot notification handler */
179 void (*reboot_notify)(void);
181 char *name; /* OSM name */
182 int context; /* Low 8 bits of the transaction info */
183 u32 class; /* I2O classes that this driver handles */
184 /* User data follows */
189 * Used by bus specific modules to communicate with the core
191 * This is needed because the bus modules cannot make direct
192 * calls to the core as this results in the i2o_bus_specific_module
193 * being dependent on the core, not the otherway around.
194 * In that case, a 'modprobe i2o_lan' loads i2o_core & i2o_lan,
195 * but _not_ i2o_pci...which makes the whole thing pretty useless :)
198 struct i2o_core_func_table
200 int (*install)(struct i2o_controller *);
201 int (*activate)(struct i2o_controller *);
202 struct i2o_controller *(*find)(int);
203 void (*unlock)(struct i2o_controller *);
204 void (*run_queue)(struct i2o_controller * c);
205 int (*delete)(struct i2o_controller *);
210 * I2O System table entry
212 * The system table contains information about all the IOPs in the
213 * system. It is sent to all IOPs so that they can create peer2peer
214 * connections between them.
216 struct i2o_sys_tbl_entry
229 u32 iop_capabilities;
242 struct i2o_sys_tbl_entry iops[0];
248 static inline u32 I2O_POST_READ32(struct i2o_controller *c)
250 return readl(c->post_port);
253 static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val)
255 writel(val, c->post_port);
259 static inline u32 I2O_REPLY_READ32(struct i2o_controller *c)
261 return readl(c->reply_port);
264 static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val)
266 writel(val, c->reply_port);
270 static inline u32 I2O_IRQ_READ32(struct i2o_controller *c)
272 return readl(c->irq_mask);
275 static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val)
277 writel(val, c->irq_mask);
281 static inline void i2o_post_message(struct i2o_controller *c, u32 m)
283 /* The second line isnt spurious - thats forcing PCI posting */
284 I2O_POST_WRITE32(c, m);
285 (void) I2O_IRQ_READ32(c);
288 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
290 I2O_REPLY_WRITE32(c, m);
294 * Endian handling wrapped into the macro - keeps the core code
298 #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
300 extern struct i2o_controller *i2o_find_controller(int);
301 extern void i2o_unlock_controller(struct i2o_controller *);
302 extern struct i2o_controller *i2o_controller_chain;
303 extern int i2o_num_controllers;
304 extern int i2o_status_get(struct i2o_controller *);
306 extern int i2o_install_handler(struct i2o_handler *);
307 extern int i2o_remove_handler(struct i2o_handler *);
309 extern int i2o_claim_device(struct i2o_device *, struct i2o_handler *);
310 extern int i2o_release_device(struct i2o_device *, struct i2o_handler *);
311 extern int i2o_device_notify_on(struct i2o_device *, struct i2o_handler *);
312 extern int i2o_device_notify_off(struct i2o_device *,
313 struct i2o_handler *);
315 extern int i2o_post_this(struct i2o_controller *, u32 *, int);
316 extern int i2o_post_wait(struct i2o_controller *, u32 *, int, int);
317 extern int i2o_post_wait_mem(struct i2o_controller *, u32 *, int, int,
318 void *, void *, dma_addr_t, dma_addr_t, int, int);
320 extern int i2o_query_scalar(struct i2o_controller *, int, int, int, void *,
322 extern int i2o_set_scalar(struct i2o_controller *, int, int, int, void *,
324 extern int i2o_query_table(int, struct i2o_controller *, int, int, int,
325 void *, int, void *, int);
326 extern int i2o_clear_table(struct i2o_controller *, int, int);
327 extern int i2o_row_add_table(struct i2o_controller *, int, int, int,
329 extern int i2o_issue_params(int, struct i2o_controller *, int, void *, int,
332 extern int i2o_event_register(struct i2o_controller *, u32, u32, u32, u32);
333 extern int i2o_event_ack(struct i2o_controller *, u32 *);
335 extern void i2o_report_status(const char *, const char *, u32 *);
336 extern void i2o_dump_message(u32 *);
337 extern const char *i2o_get_class_name(int);
339 extern int i2o_install_controller(struct i2o_controller *);
340 extern int i2o_activate_controller(struct i2o_controller *);
341 extern void i2o_run_queue(struct i2o_controller *);
342 extern int i2o_delete_controller(struct i2o_controller *);
344 #if BITS_PER_LONG == 64
345 extern u32 i2o_context_list_add(void *, struct i2o_controller *);
346 extern void *i2o_context_list_get(u32, struct i2o_controller *);
347 extern u32 i2o_context_list_remove(void *, struct i2o_controller *);
349 static inline u32 i2o_context_list_add(void *ptr, struct i2o_controller *c)
354 static inline void *i2o_context_list_get(u32 context, struct i2o_controller *c)
356 return (void *)context;
359 static inline u32 i2o_context_list_remove(void *ptr, struct i2o_controller *c)
370 /* The NULL strategy leaves everything up to the controller. This tends to be a
371 * pessimal but functional choice.
374 /* Prefetch data when reading. We continually attempt to load the next 32 sectors
375 * into the controller cache.
377 #define CACHE_PREFETCH 1
378 /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
379 * into the controller cache. When an I/O is less <= 8K we assume its probably
380 * not sequential and don't prefetch (default)
382 #define CACHE_SMARTFETCH 2
383 /* Data is written to the cache and then out on to the disk. The I/O must be
384 * physically on the medium before the write is acknowledged (default without
387 #define CACHE_WRITETHROUGH 17
388 /* Data is written to the cache and then out on to the disk. The controller
389 * is permitted to write back the cache any way it wants. (default if battery
390 * backed NVRAM is present). It can be useful to set this for swap regardless of
393 #define CACHE_WRITEBACK 18
394 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
395 * write large I/O's directly to disk bypassing the cache to avoid the extra
396 * memory copy hits. Small writes are writeback cached
398 #define CACHE_SMARTBACK 19
399 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
400 * write large I/O's directly to disk bypassing the cache to avoid the extra
401 * memory copy hits. Small writes are writethrough cached. Suitable for devices
402 * lacking battery backup
404 #define CACHE_SMARTTHROUGH 20
411 #define BLKI2OGRSTRAT _IOR('2', 1, int)
412 #define BLKI2OGWSTRAT _IOR('2', 2, int)
413 #define BLKI2OSRSTRAT _IOW('2', 3, int)
414 #define BLKI2OSWSTRAT _IOW('2', 4, int)
426 #define I2O_CMD_ADAPTER_ASSIGN 0xB3
427 #define I2O_CMD_ADAPTER_READ 0xB2
428 #define I2O_CMD_ADAPTER_RELEASE 0xB5
429 #define I2O_CMD_BIOS_INFO_SET 0xA5
430 #define I2O_CMD_BOOT_DEVICE_SET 0xA7
431 #define I2O_CMD_CONFIG_VALIDATE 0xBB
432 #define I2O_CMD_CONN_SETUP 0xCA
433 #define I2O_CMD_DDM_DESTROY 0xB1
434 #define I2O_CMD_DDM_ENABLE 0xD5
435 #define I2O_CMD_DDM_QUIESCE 0xC7
436 #define I2O_CMD_DDM_RESET 0xD9
437 #define I2O_CMD_DDM_SUSPEND 0xAF
438 #define I2O_CMD_DEVICE_ASSIGN 0xB7
439 #define I2O_CMD_DEVICE_RELEASE 0xB9
440 #define I2O_CMD_HRT_GET 0xA8
441 #define I2O_CMD_ADAPTER_CLEAR 0xBE
442 #define I2O_CMD_ADAPTER_CONNECT 0xC9
443 #define I2O_CMD_ADAPTER_RESET 0xBD
444 #define I2O_CMD_LCT_NOTIFY 0xA2
445 #define I2O_CMD_OUTBOUND_INIT 0xA1
446 #define I2O_CMD_PATH_ENABLE 0xD3
447 #define I2O_CMD_PATH_QUIESCE 0xC5
448 #define I2O_CMD_PATH_RESET 0xD7
449 #define I2O_CMD_STATIC_MF_CREATE 0xDD
450 #define I2O_CMD_STATIC_MF_RELEASE 0xDF
451 #define I2O_CMD_STATUS_GET 0xA0
452 #define I2O_CMD_SW_DOWNLOAD 0xA9
453 #define I2O_CMD_SW_UPLOAD 0xAB
454 #define I2O_CMD_SW_REMOVE 0xAD
455 #define I2O_CMD_SYS_ENABLE 0xD1
456 #define I2O_CMD_SYS_MODIFY 0xC1
457 #define I2O_CMD_SYS_QUIESCE 0xC3
458 #define I2O_CMD_SYS_TAB_SET 0xA3
463 #define I2O_CMD_UTIL_NOP 0x00
464 #define I2O_CMD_UTIL_ABORT 0x01
465 #define I2O_CMD_UTIL_CLAIM 0x09
466 #define I2O_CMD_UTIL_RELEASE 0x0B
467 #define I2O_CMD_UTIL_PARAMS_GET 0x06
468 #define I2O_CMD_UTIL_PARAMS_SET 0x05
469 #define I2O_CMD_UTIL_EVT_REGISTER 0x13
470 #define I2O_CMD_UTIL_EVT_ACK 0x14
471 #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
472 #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
473 #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
474 #define I2O_CMD_UTIL_LOCK 0x17
475 #define I2O_CMD_UTIL_LOCK_RELEASE 0x19
476 #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
479 * SCSI Host Bus Adapter Class
481 #define I2O_CMD_SCSI_EXEC 0x81
482 #define I2O_CMD_SCSI_ABORT 0x83
483 #define I2O_CMD_SCSI_BUSRESET 0x27
486 * Random Block Storage Class
488 #define I2O_CMD_BLOCK_READ 0x30
489 #define I2O_CMD_BLOCK_WRITE 0x31
490 #define I2O_CMD_BLOCK_CFLUSH 0x37
491 #define I2O_CMD_BLOCK_MLOCK 0x49
492 #define I2O_CMD_BLOCK_MUNLOCK 0x4B
493 #define I2O_CMD_BLOCK_MMOUNT 0x41
494 #define I2O_CMD_BLOCK_MEJECT 0x43
495 #define I2O_CMD_BLOCK_POWER 0x70
497 #define I2O_PRIVATE_MSG 0xFF
499 /* Command status values */
501 #define I2O_CMD_IN_PROGRESS 0x01
502 #define I2O_CMD_REJECTED 0x02
503 #define I2O_CMD_FAILED 0x03
504 #define I2O_CMD_COMPLETED 0x04
506 /* I2O API function return values */
508 #define I2O_RTN_NO_ERROR 0
509 #define I2O_RTN_NOT_INIT 1
510 #define I2O_RTN_FREE_Q_EMPTY 2
511 #define I2O_RTN_TCB_ERROR 3
512 #define I2O_RTN_TRANSACTION_ERROR 4
513 #define I2O_RTN_ADAPTER_ALREADY_INIT 5
514 #define I2O_RTN_MALLOC_ERROR 6
515 #define I2O_RTN_ADPTR_NOT_REGISTERED 7
516 #define I2O_RTN_MSG_REPLY_TIMEOUT 8
517 #define I2O_RTN_NO_STATUS 9
518 #define I2O_RTN_NO_FIRM_VER 10
519 #define I2O_RTN_NO_LINK_SPEED 11
521 /* Reply message status defines for all messages */
523 #define I2O_REPLY_STATUS_SUCCESS 0x00
524 #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
525 #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
526 #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
527 #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
528 #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
529 #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
530 #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
531 #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
532 #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
533 #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
534 #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
536 /* Status codes and Error Information for Parameter functions */
538 #define I2O_PARAMS_STATUS_SUCCESS 0x00
539 #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
540 #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
541 #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
542 #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
543 #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
544 #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
545 #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
546 #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
547 #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
548 #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
549 #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
550 #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
551 #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
552 #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
553 #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
554 #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
556 /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
557 * messages: Table 3-2 Detailed Status Codes.*/
559 #define I2O_DSC_SUCCESS 0x0000
560 #define I2O_DSC_BAD_KEY 0x0002
561 #define I2O_DSC_TCL_ERROR 0x0003
562 #define I2O_DSC_REPLY_BUFFER_FULL 0x0004
563 #define I2O_DSC_NO_SUCH_PAGE 0x0005
564 #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
565 #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
566 #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
567 #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
568 #define I2O_DSC_DEVICE_LOCKED 0x000B
569 #define I2O_DSC_DEVICE_RESET 0x000C
570 #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
571 #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
572 #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
573 #define I2O_DSC_INVALID_OFFSET 0x0010
574 #define I2O_DSC_INVALID_PARAMETER 0x0011
575 #define I2O_DSC_INVALID_REQUEST 0x0012
576 #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
577 #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
578 #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
579 #define I2O_DSC_MISSING_PARAMETER 0x0016
580 #define I2O_DSC_TIMEOUT 0x0017
581 #define I2O_DSC_UNKNOWN_ERROR 0x0018
582 #define I2O_DSC_UNKNOWN_FUNCTION 0x0019
583 #define I2O_DSC_UNSUPPORTED_VERSION 0x001A
584 #define I2O_DSC_DEVICE_BUSY 0x001B
585 #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
587 /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
590 #define I2O_BSA_DSC_SUCCESS 0x0000
591 #define I2O_BSA_DSC_MEDIA_ERROR 0x0001
592 #define I2O_BSA_DSC_ACCESS_ERROR 0x0002
593 #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
594 #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
595 #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
596 #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
597 #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
598 #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
599 #define I2O_BSA_DSC_BUS_FAILURE 0x0009
600 #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
601 #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
602 #define I2O_BSA_DSC_DEVICE_RESET 0x000C
603 #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
604 #define I2O_BSA_DSC_TIMEOUT 0x000E
606 /* FailureStatusCodes, Table 3-3 Message Failure Codes */
608 #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
609 #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
610 #define I2O_FSC_TRANSPORT_CONGESTION 0x83
611 #define I2O_FSC_TRANSPORT_FAILURE 0x84
612 #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
613 #define I2O_FSC_TRANSPORT_TIME_OUT 0x86
614 #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
615 #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
616 #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
617 #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
618 #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
619 #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
620 #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
621 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
622 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
623 #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
625 /* Device Claim Types */
626 #define I2O_CLAIM_PRIMARY 0x01000000
627 #define I2O_CLAIM_MANAGEMENT 0x02000000
628 #define I2O_CLAIM_AUTHORIZED 0x03000000
629 #define I2O_CLAIM_SECONDARY 0x04000000
631 /* Message header defines for VersionOffset */
632 #define I2OVER15 0x0001
633 #define I2OVER20 0x0002
635 /* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */
636 #define I2OVERSION I2OVER15
638 #define SGL_OFFSET_0 I2OVERSION
639 #define SGL_OFFSET_4 (0x0040 | I2OVERSION)
640 #define SGL_OFFSET_5 (0x0050 | I2OVERSION)
641 #define SGL_OFFSET_6 (0x0060 | I2OVERSION)
642 #define SGL_OFFSET_7 (0x0070 | I2OVERSION)
643 #define SGL_OFFSET_8 (0x0080 | I2OVERSION)
644 #define SGL_OFFSET_9 (0x0090 | I2OVERSION)
645 #define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
647 #define TRL_OFFSET_5 (0x0050 | I2OVERSION)
648 #define TRL_OFFSET_6 (0x0060 | I2OVERSION)
650 /* Transaction Reply Lists (TRL) Control Word structure */
651 #define TRL_SINGLE_FIXED_LENGTH 0x00
652 #define TRL_SINGLE_VARIABLE_LENGTH 0x40
653 #define TRL_MULTIPLE_FIXED_LENGTH 0x80
656 /* msg header defines for MsgFlags */
657 #define MSG_STATIC 0x0100
658 #define MSG_64BIT_CNTXT 0x0200
659 #define MSG_MULTI_TRANS 0x1000
660 #define MSG_FAIL 0x2000
661 #define MSG_FINAL 0x4000
662 #define MSG_REPLY 0x8000
664 /* minimum size msg */
665 #define THREE_WORD_MSG_SIZE 0x00030000
666 #define FOUR_WORD_MSG_SIZE 0x00040000
667 #define FIVE_WORD_MSG_SIZE 0x00050000
668 #define SIX_WORD_MSG_SIZE 0x00060000
669 #define SEVEN_WORD_MSG_SIZE 0x00070000
670 #define EIGHT_WORD_MSG_SIZE 0x00080000
671 #define NINE_WORD_MSG_SIZE 0x00090000
672 #define TEN_WORD_MSG_SIZE 0x000A0000
673 #define ELEVEN_WORD_MSG_SIZE 0x000B0000
674 #define I2O_MESSAGE_SIZE(x) ((x)<<16)
677 /* Special TID Assignments */
679 #define ADAPTER_TID 0
682 #define MSG_FRAME_SIZE 64 /* i2o_scsi assumes >= 32 */
683 #define REPLY_FRAME_SIZE 17
684 #define SG_TABLESIZE 30
685 #define NMBR_MSG_FRAMES 128
687 #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
689 #define I2O_POST_WAIT_OK 0
690 #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
692 #define I2O_CONTEXT_LIST_MIN_LENGTH 15
693 #define I2O_CONTEXT_LIST_USED 0x01
694 #define I2O_CONTEXT_LIST_DELETED 0x02
696 #endif /* __KERNEL__ */