2 * I2O kernel space accessible structures/APIs
4 * (c) Copyright 1999, 2000 Red Hat Software
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 *************************************************************************
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
21 #ifdef __KERNEL__ /* This file to be included by kernel only */
23 #include <linux/i2o-dev.h>
25 /* How many different OSM's are we allowing */
26 #define MAX_I2O_MODULES 4
28 /* How many OSMs can register themselves for device status updates? */
29 #define I2O_MAX_MANAGERS 4
31 #include <asm/semaphore.h> /* Needed for MUTEX init macros */
32 #include <linux/config.h>
33 #include <linux/notifier.h>
34 #include <asm/atomic.h>
47 u32 initiator_context;
52 * Each I2O device entity has one or more of these. There is one
57 i2o_lct_entry lct_data; /* Device LCT information */
59 int i2oversion; /* I2O version supported. Actually
60 * there should be high and low
63 struct proc_dir_entry *proc_entry; /* /proc dir */
66 struct i2o_handler *owner;
68 /* Management users */
69 struct i2o_handler *managers[I2O_MAX_MANAGERS];
72 struct i2o_controller *controller; /* Controlling IOP */
73 struct i2o_device *next; /* Chain */
74 struct i2o_device *prev;
75 char dev_name[8]; /* linux /dev name if available */
79 * Each I2O controller has one of these objects
88 struct pci_dev *pdev; /* PCI device */
90 int short_req:1; /* Use small block sizes */
91 int dpt:1; /* Don't quiesce */
92 int promise:1; /* Promise controller */
98 struct notifier_block *event_notifer; /* Events */
100 struct i2o_device *devices; /* I2O device chain */
101 struct i2o_controller *next; /* Controller chain */
102 unsigned long post_port; /* Inbout port address */
103 unsigned long reply_port; /* Outbound port address */
104 unsigned long irq_mask; /* Interrupt register address */
106 /* Dynamic LCT related data */
107 struct semaphore lct_sem;
111 i2o_status_block *status_block; /* IOP status block */
112 dma_addr_t status_block_phys;
113 i2o_lct *lct; /* Logical Config Table */
115 i2o_lct *dlct; /* Temp LCT */
116 dma_addr_t dlct_phys;
117 i2o_hrt *hrt; /* HW Resource Table */
121 unsigned long mem_offset; /* MFA offset */
122 unsigned long mem_phys; /* MFA physical */
124 int battery:1; /* Has a battery backup */
125 int io_alloc:1; /* An I/O resource was allocated */
126 int mem_alloc:1; /* A memory resource was allocated */
128 struct resource io_resource; /* I/O resource allocated to the IOP */
129 struct resource mem_resource; /* Mem resource allocated to the IOP */
131 struct proc_dir_entry *proc_entry; /* /proc dir */
134 void *page_frame; /* Message buffers */
135 dma_addr_t page_frame_map; /* Cache map */
139 * OSM resgistration block
141 * Each OSM creates at least one of these and registers it with the
142 * I2O core through i2o_register_handler. An OSM may want to
143 * register more than one if it wants a fast path to a reply
144 * handler by having a separate initiator context for each
149 /* Message reply handler */
150 void (*reply)(struct i2o_handler *, struct i2o_controller *,
151 struct i2o_message *);
153 /* New device notification handler */
154 void (*new_dev_notify)(struct i2o_controller *, struct i2o_device *);
156 /* Device deltion handler */
157 void (*dev_del_notify)(struct i2o_controller *, struct i2o_device *);
159 /* Reboot notification handler */
160 void (*reboot_notify)(void);
162 char *name; /* OSM name */
163 int context; /* Low 8 bits of the transaction info */
164 u32 class; /* I2O classes that this driver handles */
165 /* User data follows */
170 * Used by bus specific modules to communicate with the core
172 * This is needed because the bus modules cannot make direct
173 * calls to the core as this results in the i2o_bus_specific_module
174 * being dependent on the core, not the otherway around.
175 * In that case, a 'modprobe i2o_lan' loads i2o_core & i2o_lan,
176 * but _not_ i2o_pci...which makes the whole thing pretty useless :)
179 struct i2o_core_func_table
181 int (*install)(struct i2o_controller *);
182 int (*activate)(struct i2o_controller *);
183 struct i2o_controller *(*find)(int);
184 void (*unlock)(struct i2o_controller *);
185 void (*run_queue)(struct i2o_controller * c);
186 int (*delete)(struct i2o_controller *);
191 * I2O System table entry
193 * The system table contains information about all the IOPs in the
194 * system. It is sent to all IOPs so that they can create peer2peer
195 * connections between them.
197 struct i2o_sys_tbl_entry
210 u32 iop_capabilities;
223 struct i2o_sys_tbl_entry iops[0];
229 static inline u32 I2O_POST_READ32(struct i2o_controller *c)
231 return readl(c->post_port);
234 static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val)
236 writel(val, c->post_port);
240 static inline u32 I2O_REPLY_READ32(struct i2o_controller *c)
242 return readl(c->reply_port);
245 static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val)
247 writel(val, c->reply_port);
251 static inline u32 I2O_IRQ_READ32(struct i2o_controller *c)
253 return readl(c->irq_mask);
256 static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val)
258 writel(val, c->irq_mask);
262 static inline void i2o_post_message(struct i2o_controller *c, u32 m)
264 /* The second line isnt spurious - thats forcing PCI posting */
265 I2O_POST_WRITE32(c, m);
266 (void) I2O_IRQ_READ32(c);
269 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
271 I2O_REPLY_WRITE32(c, m);
275 * Endian handling wrapped into the macro - keeps the core code
279 #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
281 extern struct i2o_controller *i2o_find_controller(int);
282 extern void i2o_unlock_controller(struct i2o_controller *);
283 extern struct i2o_controller *i2o_controller_chain;
284 extern int i2o_num_controllers;
285 extern int i2o_status_get(struct i2o_controller *);
287 extern int i2o_install_handler(struct i2o_handler *);
288 extern int i2o_remove_handler(struct i2o_handler *);
290 extern int i2o_claim_device(struct i2o_device *, struct i2o_handler *);
291 extern int i2o_release_device(struct i2o_device *, struct i2o_handler *);
292 extern int i2o_device_notify_on(struct i2o_device *, struct i2o_handler *);
293 extern int i2o_device_notify_off(struct i2o_device *,
294 struct i2o_handler *);
296 extern int i2o_post_this(struct i2o_controller *, u32 *, int);
297 extern int i2o_post_wait(struct i2o_controller *, u32 *, int, int);
298 extern int i2o_post_wait_mem(struct i2o_controller *, u32 *, int, int,
299 void *, void *, dma_addr_t, dma_addr_t, int, int);
301 extern int i2o_query_scalar(struct i2o_controller *, int, int, int, void *,
303 extern int i2o_set_scalar(struct i2o_controller *, int, int, int, void *,
305 extern int i2o_query_table(int, struct i2o_controller *, int, int, int,
306 void *, int, void *, int);
307 extern int i2o_clear_table(struct i2o_controller *, int, int);
308 extern int i2o_row_add_table(struct i2o_controller *, int, int, int,
310 extern int i2o_issue_params(int, struct i2o_controller *, int, void *, int,
313 extern int i2o_event_register(struct i2o_controller *, u32, u32, u32, u32);
314 extern int i2o_event_ack(struct i2o_controller *, u32 *);
316 extern void i2o_report_status(const char *, const char *, u32 *);
317 extern void i2o_dump_message(u32 *);
318 extern const char *i2o_get_class_name(int);
320 extern int i2o_install_controller(struct i2o_controller *);
321 extern int i2o_activate_controller(struct i2o_controller *);
322 extern void i2o_run_queue(struct i2o_controller *);
323 extern int i2o_delete_controller(struct i2o_controller *);
330 /* The NULL strategy leaves everything up to the controller. This tends to be a
331 * pessimal but functional choice.
334 /* Prefetch data when reading. We continually attempt to load the next 32 sectors
335 * into the controller cache.
337 #define CACHE_PREFETCH 1
338 /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
339 * into the controller cache. When an I/O is less <= 8K we assume its probably
340 * not sequential and don't prefetch (default)
342 #define CACHE_SMARTFETCH 2
343 /* Data is written to the cache and then out on to the disk. The I/O must be
344 * physically on the medium before the write is acknowledged (default without
347 #define CACHE_WRITETHROUGH 17
348 /* Data is written to the cache and then out on to the disk. The controller
349 * is permitted to write back the cache any way it wants. (default if battery
350 * backed NVRAM is present). It can be useful to set this for swap regardless of
353 #define CACHE_WRITEBACK 18
354 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
355 * write large I/O's directly to disk bypassing the cache to avoid the extra
356 * memory copy hits. Small writes are writeback cached
358 #define CACHE_SMARTBACK 19
359 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
360 * write large I/O's directly to disk bypassing the cache to avoid the extra
361 * memory copy hits. Small writes are writethrough cached. Suitable for devices
362 * lacking battery backup
364 #define CACHE_SMARTTHROUGH 20
371 #define BLKI2OGRSTRAT _IOR('2', 1, int)
372 #define BLKI2OGWSTRAT _IOR('2', 2, int)
373 #define BLKI2OSRSTRAT _IOW('2', 3, int)
374 #define BLKI2OSWSTRAT _IOW('2', 4, int)
386 #define I2O_CMD_ADAPTER_ASSIGN 0xB3
387 #define I2O_CMD_ADAPTER_READ 0xB2
388 #define I2O_CMD_ADAPTER_RELEASE 0xB5
389 #define I2O_CMD_BIOS_INFO_SET 0xA5
390 #define I2O_CMD_BOOT_DEVICE_SET 0xA7
391 #define I2O_CMD_CONFIG_VALIDATE 0xBB
392 #define I2O_CMD_CONN_SETUP 0xCA
393 #define I2O_CMD_DDM_DESTROY 0xB1
394 #define I2O_CMD_DDM_ENABLE 0xD5
395 #define I2O_CMD_DDM_QUIESCE 0xC7
396 #define I2O_CMD_DDM_RESET 0xD9
397 #define I2O_CMD_DDM_SUSPEND 0xAF
398 #define I2O_CMD_DEVICE_ASSIGN 0xB7
399 #define I2O_CMD_DEVICE_RELEASE 0xB9
400 #define I2O_CMD_HRT_GET 0xA8
401 #define I2O_CMD_ADAPTER_CLEAR 0xBE
402 #define I2O_CMD_ADAPTER_CONNECT 0xC9
403 #define I2O_CMD_ADAPTER_RESET 0xBD
404 #define I2O_CMD_LCT_NOTIFY 0xA2
405 #define I2O_CMD_OUTBOUND_INIT 0xA1
406 #define I2O_CMD_PATH_ENABLE 0xD3
407 #define I2O_CMD_PATH_QUIESCE 0xC5
408 #define I2O_CMD_PATH_RESET 0xD7
409 #define I2O_CMD_STATIC_MF_CREATE 0xDD
410 #define I2O_CMD_STATIC_MF_RELEASE 0xDF
411 #define I2O_CMD_STATUS_GET 0xA0
412 #define I2O_CMD_SW_DOWNLOAD 0xA9
413 #define I2O_CMD_SW_UPLOAD 0xAB
414 #define I2O_CMD_SW_REMOVE 0xAD
415 #define I2O_CMD_SYS_ENABLE 0xD1
416 #define I2O_CMD_SYS_MODIFY 0xC1
417 #define I2O_CMD_SYS_QUIESCE 0xC3
418 #define I2O_CMD_SYS_TAB_SET 0xA3
423 #define I2O_CMD_UTIL_NOP 0x00
424 #define I2O_CMD_UTIL_ABORT 0x01
425 #define I2O_CMD_UTIL_CLAIM 0x09
426 #define I2O_CMD_UTIL_RELEASE 0x0B
427 #define I2O_CMD_UTIL_PARAMS_GET 0x06
428 #define I2O_CMD_UTIL_PARAMS_SET 0x05
429 #define I2O_CMD_UTIL_EVT_REGISTER 0x13
430 #define I2O_CMD_UTIL_EVT_ACK 0x14
431 #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
432 #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
433 #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
434 #define I2O_CMD_UTIL_LOCK 0x17
435 #define I2O_CMD_UTIL_LOCK_RELEASE 0x19
436 #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
439 * SCSI Host Bus Adapter Class
441 #define I2O_CMD_SCSI_EXEC 0x81
442 #define I2O_CMD_SCSI_ABORT 0x83
443 #define I2O_CMD_SCSI_BUSRESET 0x27
446 * Random Block Storage Class
448 #define I2O_CMD_BLOCK_READ 0x30
449 #define I2O_CMD_BLOCK_WRITE 0x31
450 #define I2O_CMD_BLOCK_CFLUSH 0x37
451 #define I2O_CMD_BLOCK_MLOCK 0x49
452 #define I2O_CMD_BLOCK_MUNLOCK 0x4B
453 #define I2O_CMD_BLOCK_MMOUNT 0x41
454 #define I2O_CMD_BLOCK_MEJECT 0x43
455 #define I2O_CMD_BLOCK_POWER 0x70
457 #define I2O_PRIVATE_MSG 0xFF
459 /* Command status values */
461 #define I2O_CMD_IN_PROGRESS 0x01
462 #define I2O_CMD_REJECTED 0x02
463 #define I2O_CMD_FAILED 0x03
464 #define I2O_CMD_COMPLETED 0x04
466 /* I2O API function return values */
468 #define I2O_RTN_NO_ERROR 0
469 #define I2O_RTN_NOT_INIT 1
470 #define I2O_RTN_FREE_Q_EMPTY 2
471 #define I2O_RTN_TCB_ERROR 3
472 #define I2O_RTN_TRANSACTION_ERROR 4
473 #define I2O_RTN_ADAPTER_ALREADY_INIT 5
474 #define I2O_RTN_MALLOC_ERROR 6
475 #define I2O_RTN_ADPTR_NOT_REGISTERED 7
476 #define I2O_RTN_MSG_REPLY_TIMEOUT 8
477 #define I2O_RTN_NO_STATUS 9
478 #define I2O_RTN_NO_FIRM_VER 10
479 #define I2O_RTN_NO_LINK_SPEED 11
481 /* Reply message status defines for all messages */
483 #define I2O_REPLY_STATUS_SUCCESS 0x00
484 #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
485 #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
486 #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
487 #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
488 #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
489 #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
490 #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
491 #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
492 #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
493 #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
494 #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
496 /* Status codes and Error Information for Parameter functions */
498 #define I2O_PARAMS_STATUS_SUCCESS 0x00
499 #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
500 #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
501 #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
502 #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
503 #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
504 #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
505 #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
506 #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
507 #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
508 #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
509 #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
510 #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
511 #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
512 #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
513 #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
514 #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
516 /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
517 * messages: Table 3-2 Detailed Status Codes.*/
519 #define I2O_DSC_SUCCESS 0x0000
520 #define I2O_DSC_BAD_KEY 0x0002
521 #define I2O_DSC_TCL_ERROR 0x0003
522 #define I2O_DSC_REPLY_BUFFER_FULL 0x0004
523 #define I2O_DSC_NO_SUCH_PAGE 0x0005
524 #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
525 #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
526 #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
527 #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
528 #define I2O_DSC_DEVICE_LOCKED 0x000B
529 #define I2O_DSC_DEVICE_RESET 0x000C
530 #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
531 #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
532 #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
533 #define I2O_DSC_INVALID_OFFSET 0x0010
534 #define I2O_DSC_INVALID_PARAMETER 0x0011
535 #define I2O_DSC_INVALID_REQUEST 0x0012
536 #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
537 #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
538 #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
539 #define I2O_DSC_MISSING_PARAMETER 0x0016
540 #define I2O_DSC_TIMEOUT 0x0017
541 #define I2O_DSC_UNKNOWN_ERROR 0x0018
542 #define I2O_DSC_UNKNOWN_FUNCTION 0x0019
543 #define I2O_DSC_UNSUPPORTED_VERSION 0x001A
544 #define I2O_DSC_DEVICE_BUSY 0x001B
545 #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
547 /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
550 #define I2O_BSA_DSC_SUCCESS 0x0000
551 #define I2O_BSA_DSC_MEDIA_ERROR 0x0001
552 #define I2O_BSA_DSC_ACCESS_ERROR 0x0002
553 #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
554 #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
555 #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
556 #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
557 #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
558 #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
559 #define I2O_BSA_DSC_BUS_FAILURE 0x0009
560 #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
561 #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
562 #define I2O_BSA_DSC_DEVICE_RESET 0x000C
563 #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
564 #define I2O_BSA_DSC_TIMEOUT 0x000E
566 /* FailureStatusCodes, Table 3-3 Message Failure Codes */
568 #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
569 #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
570 #define I2O_FSC_TRANSPORT_CONGESTION 0x83
571 #define I2O_FSC_TRANSPORT_FAILURE 0x84
572 #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
573 #define I2O_FSC_TRANSPORT_TIME_OUT 0x86
574 #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
575 #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
576 #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
577 #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
578 #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
579 #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
580 #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
581 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
582 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
583 #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
585 /* Device Claim Types */
586 #define I2O_CLAIM_PRIMARY 0x01000000
587 #define I2O_CLAIM_MANAGEMENT 0x02000000
588 #define I2O_CLAIM_AUTHORIZED 0x03000000
589 #define I2O_CLAIM_SECONDARY 0x04000000
591 /* Message header defines for VersionOffset */
592 #define I2OVER15 0x0001
593 #define I2OVER20 0x0002
595 /* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */
596 #define I2OVERSION I2OVER15
598 #define SGL_OFFSET_0 I2OVERSION
599 #define SGL_OFFSET_4 (0x0040 | I2OVERSION)
600 #define SGL_OFFSET_5 (0x0050 | I2OVERSION)
601 #define SGL_OFFSET_6 (0x0060 | I2OVERSION)
602 #define SGL_OFFSET_7 (0x0070 | I2OVERSION)
603 #define SGL_OFFSET_8 (0x0080 | I2OVERSION)
604 #define SGL_OFFSET_9 (0x0090 | I2OVERSION)
605 #define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
607 #define TRL_OFFSET_5 (0x0050 | I2OVERSION)
608 #define TRL_OFFSET_6 (0x0060 | I2OVERSION)
610 /* Transaction Reply Lists (TRL) Control Word structure */
611 #define TRL_SINGLE_FIXED_LENGTH 0x00
612 #define TRL_SINGLE_VARIABLE_LENGTH 0x40
613 #define TRL_MULTIPLE_FIXED_LENGTH 0x80
616 /* msg header defines for MsgFlags */
617 #define MSG_STATIC 0x0100
618 #define MSG_64BIT_CNTXT 0x0200
619 #define MSG_MULTI_TRANS 0x1000
620 #define MSG_FAIL 0x2000
621 #define MSG_FINAL 0x4000
622 #define MSG_REPLY 0x8000
624 /* minimum size msg */
625 #define THREE_WORD_MSG_SIZE 0x00030000
626 #define FOUR_WORD_MSG_SIZE 0x00040000
627 #define FIVE_WORD_MSG_SIZE 0x00050000
628 #define SIX_WORD_MSG_SIZE 0x00060000
629 #define SEVEN_WORD_MSG_SIZE 0x00070000
630 #define EIGHT_WORD_MSG_SIZE 0x00080000
631 #define NINE_WORD_MSG_SIZE 0x00090000
632 #define TEN_WORD_MSG_SIZE 0x000A0000
633 #define ELEVEN_WORD_MSG_SIZE 0x000B0000
634 #define I2O_MESSAGE_SIZE(x) ((x)<<16)
637 /* Special TID Assignments */
639 #define ADAPTER_TID 0
642 #define MSG_FRAME_SIZE 64 /* i2o_scsi assumes >= 32 */
643 #define NMBR_MSG_FRAMES 128
645 #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
647 #define I2O_POST_WAIT_OK 0
648 #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
650 #endif /* __KERNEL__ */