linux-2.6-001-bcm5720.patch

   1 diff -Nurb linux-2.6.32-27.planetlab.i686/drivers/net/tg3.c ../kernel-2.6/linux-2.6.32-27.planetlab.i686/drivers/net/tg3.c
   2 --- linux-2.6.32-27.planetlab.i686/drivers/net/tg3.c    2011-05-10 14:38:09.000000000 -0400
   3 +++ ../kernel-2.6/linux-2.6.32-27.planetlab.i686/drivers/net/tg3.c      2012-05-01 10:09:30.502846530 -0400
   4 @@ -103,14 +103,12 @@
   5   * them in the NIC onboard memory.
   6   */
   7  #define TG3_RX_STD_RING_SIZE(tp) \
   8 -       ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
   9 -         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
  10 -        RX_STD_MAX_SIZE_5717 : 512)
  11 +       ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
  12 +        TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
  13  #define TG3_DEF_RX_RING_PENDING                200
  14  #define TG3_RX_JMB_RING_SIZE(tp) \
  15 -       ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
  16 -         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
  17 -        1024 : 256)
  18 +       ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
  19 +        TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
  20  #define TG3_DEF_RX_JUMBO_RING_PENDING  100
  21  #define TG3_RSS_INDIR_TBL_SIZE         128
  22
  23 @@ -276,6 +274,7 @@
  24         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
  25         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
  26         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
  27 +       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
  28         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  29         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  30         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  31 @@ -1090,8 +1089,7 @@
  32         u32 reg;
  33         struct phy_device *phydev;
  34
  35 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  36 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
  37 +       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
  38                 u32 is_serdes;
  39
  40                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
  41 @@ -1669,8 +1667,7 @@
  42         u32 reg;
  43
  44         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  45 -           ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  46 -             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
  47 +           ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
  48              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  49                 return;
  50
  51 @@ -2080,8 +2077,7 @@
  52                 }
  53         }
  54
  55 -       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  56 -            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
  57 +       if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
  58             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
  59                 return 0;
  60
  61 @@ -2167,7 +2163,8 @@
  62
  63         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  64             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
  65 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  66 +           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  67 +            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  68                 struct net_device *dev_peer;
  69
  70                 dev_peer = pci_get_drvdata(tp->pdev_peer);
  71 @@ -4431,6 +4428,7 @@
  72
  73  static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  74  {
  75 +       u32 val;
  76         int err;
  77
  78         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  79 @@ -4441,7 +4439,7 @@
  80                 err = tg3_setup_copper_phy(tp, force_reset);
  81
  82         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  83 -               u32 val, scale;
  84 +               u32 scale;
  85
  86                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  87                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  88 @@ -4456,17 +4454,20 @@
  89                 tw32(GRC_MISC_CFG, val);
  90         }
  91
  92 +       val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  93 +             (6 << TX_LENGTHS_IPG_SHIFT);
  94 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  95 +               val |= tr32(MAC_TX_LENGTHS) &
  96 +                      (TX_LENGTHS_JMB_FRM_LEN_MSK |
  97 +                       TX_LENGTHS_CNT_DWN_VAL_MSK);
  98 +
  99         if (tp->link_config.active_speed == SPEED_1000 &&
 100             tp->link_config.active_duplex == DUPLEX_HALF)
 101 -               tw32(MAC_TX_LENGTHS,
 102 -                    ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
 103 -                     (6 << TX_LENGTHS_IPG_SHIFT) |
 104 -                     (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
 105 +               tw32(MAC_TX_LENGTHS, val |
 106 +                    (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
 107         else
 108 -               tw32(MAC_TX_LENGTHS,
 109 -                    ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
 110 -                     (6 << TX_LENGTHS_IPG_SHIFT) |
 111 -                     (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
 112 +               tw32(MAC_TX_LENGTHS, val |
 113 +                    (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
 114
 115         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 116                 if (netif_carrier_ok(tp->dev)) {
 117 @@ -4478,7 +4479,7 @@
 118         }
 119
 120         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
 121 -               u32 val = tr32(PCIE_PWR_MGMT_THRESH);
 122 +               val = tr32(PCIE_PWR_MGMT_THRESH);
 123                 if (!netif_carrier_ok(tp->dev))
 124                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
 125                               tp->pwrmgmt_thresh;
 126 @@ -7085,7 +7086,7 @@
 127         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
 128                 /* Force PCIe 1.0a mode */
 129                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
 130 -                   !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
 131 +                   !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
 132                     tr32(TG3_PCIE_PHY_TSTCTL) ==
 133                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
 134                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
 135 @@ -7236,12 +7237,17 @@
 136         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
 137             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
 138             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
 139 -           !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
 140 +           !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
 141                 val = tr32(0x7c00);
 142
 143                 tw32(0x7c00, val | (1 << 25));
 144         }
 145
 146 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 147 +               val = tr32(TG3_CPMU_CLCK_ORIDE);
 148 +               tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
 149 +       }
 150 +
 151         /* Reprobe ASF enable state.  */
 152         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
 153         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
 154 @@ -7659,6 +7665,8 @@
 155         /* Disable all transmit rings but the first. */
 156         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
 157                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
 158 +       else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
 159 +               limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
 160         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
 161                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
 162         else
 163 @@ -7671,8 +7679,7 @@
 164
 165
 166         /* Disable all receive return rings but the first. */
 167 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 168 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
 169 +       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
 170                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
 171         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
 172                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
 173 @@ -7943,7 +7950,7 @@
 174         if (err)
 175                 return err;
 176
 177 -       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 178 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
 179                 val = tr32(TG3PCI_DMA_RW_CTRL) &
 180                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
 181                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
 182 @@ -8074,8 +8081,7 @@
 183              ((u64) tpr->rx_std_mapping >> 32));
 184         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
 185              ((u64) tpr->rx_std_mapping & 0xffffffff));
 186 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
 187 -           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
 188 +       if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
 189                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
 190                      NIC_SRAM_RX_BUFFER_DESC);
 191
 192 @@ -8097,9 +8103,10 @@
 193                              ((u64) tpr->rx_jmb_mapping >> 32));
 194                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
 195                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
 196 +                       val = TG3_RX_JMB_RING_SIZE(tp) <<
 197 +                             BDINFO_FLAGS_MAXLEN_SHIFT;
 198                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
 199 -                            (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
 200 -                            BDINFO_FLAGS_USE_EXT_RECV);
 201 +                            val | BDINFO_FLAGS_USE_EXT_RECV);
 202                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
 203                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
 204                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
 205 @@ -8109,17 +8116,17 @@
 206                              BDINFO_FLAGS_DISABLED);
 207                 }
 208
 209 -               if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 210 +               if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
 211                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
 212 -                               val = RX_STD_MAX_SIZE_5705;
 213 +                               val = TG3_RX_STD_MAX_SIZE_5700;
 214                         else
 215 -                               val = RX_STD_MAX_SIZE_5717;
 216 +                               val = TG3_RX_STD_MAX_SIZE_5717;
 217                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
 218                         val |= (TG3_RX_STD_DMA_SZ << 2);
 219                 } else
 220                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
 221         } else
 222 -               val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
 223 +               val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
 224
 225         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
 226
 227 @@ -8130,7 +8137,7 @@
 228                           tp->rx_jumbo_pending : 0;
 229         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
 230
 231 -       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 232 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
 233                 tw32(STD_REPLENISH_LWM, 32);
 234                 tw32(JMB_REPLENISH_LWM, 16);
 235         }
 236 @@ -8147,10 +8154,16 @@
 237         /* The slot time is changed by tg3_setup_phy if we
 238          * run at gigabit with half duplex.
 239          */
 240 -       tw32(MAC_TX_LENGTHS,
 241 -            (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
 242 +       val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
 243              (6 << TX_LENGTHS_IPG_SHIFT) |
 244 -            (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
 245 +             (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
 246 +
 247 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
 248 +               val |= tr32(MAC_TX_LENGTHS) &
 249 +                      (TX_LENGTHS_JMB_FRM_LEN_MSK |
 250 +                       TX_LENGTHS_CNT_DWN_VAL_MSK);
 251 +
 252 +       tw32(MAC_TX_LENGTHS, val);
 253
 254         /* Receive rules. */
 255         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
 256 @@ -8199,13 +8212,17 @@
 257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
 258                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
 259
 260 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
 261 +               rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
 262 +
 263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
 264             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
 265             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
 266             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
 267 -           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
 268 +           (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
 269                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
 270 -               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
 271 +               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
 272 +                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 273                         val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
 274                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
 275                 }
 276 @@ -8213,7 +8230,8 @@
 277                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
 278         }
 279
 280 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
 281 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
 282 +           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 283                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
 284                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
 285                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
 286 @@ -8403,8 +8421,7 @@
 287         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
 288         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
 289         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
 290 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 291 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
 292 +       if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
 293                 val |= RCVDBDI_MODE_LRG_RING_SZ;
 294         tw32(RCVDBDI_MODE, val);
 295         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
 296 @@ -8429,9 +8446,17 @@
 297         }
 298
 299         tp->tx_mode = TX_MODE_ENABLE;
 300 +
 301         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
 302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
 303                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
 304 +
 305 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 306 +               val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
 307 +               tp->tx_mode &= ~val;
 308 +               tp->tx_mode |= tr32(MAC_TX_MODE) & val;
 309 +       }
 310 +
 311         tw32_f(MAC_TX_MODE, tp->tx_mode);
 312         udelay(100);
 313
 314 @@ -8850,7 +8875,7 @@
 315          * Turn off MSI one shot mode.  Otherwise this test has no
 316          * observable way to know whether the interrupt was delivered.
 317          */
 318 -       if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
 319 +       if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
 320             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
 321                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
 322                 tw32(MSGINT_MODE, val);
 323 @@ -8893,7 +8918,7 @@
 324
 325         if (intr_ok) {
 326                 /* Reenable MSI one shot mode. */
 327 -               if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
 328 +               if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
 329                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
 330                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
 331                         tw32(MSGINT_MODE, val);
 332 @@ -9034,7 +9059,9 @@
 333         tp->dev->real_num_tx_queues = 1;
 334         if (tp->irq_cnt > 1) {
 335                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
 336 -               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
 337 +
 338 +               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
 339 +                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 340                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
 341                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
 342                 }
 343 @@ -9186,7 +9213,7 @@
 344                         goto err_out2;
 345                 }
 346
 347 -               if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
 348 +               if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
 349                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
 350                         u32 val = tr32(PCIE_TRANSACTION_CFG);
 351
 352 @@ -10796,8 +10823,7 @@
 353         int err = 0;
 354         int i;
 355
 356 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 357 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
 358 +       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
 359                 mem_tbl = mem_tbl_5717;
 360         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
 361                 mem_tbl = mem_tbl_57765;
 362 @@ -11788,6 +11814,8 @@
 363
 364                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
 365                 case FLASH_5717VENDOR_ATMEL_MDB021D:
 366 +                       /* Detect size with tg3_nvram_get_size() */
 367 +                       break;
 368                 case FLASH_5717VENDOR_ATMEL_ADB021B:
 369                 case FLASH_5717VENDOR_ATMEL_ADB021D:
 370                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
 371 @@ -11813,8 +11841,10 @@
 372
 373                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
 374                 case FLASH_5717VENDOR_ST_M_M25PE20:
 375 -               case FLASH_5717VENDOR_ST_A_M25PE20:
 376                 case FLASH_5717VENDOR_ST_M_M45PE20:
 377 +                       /* Detect size with tg3_nvram_get_size() */
 378 +                       break;
 379 +               case FLASH_5717VENDOR_ST_A_M25PE20:
 380                 case FLASH_5717VENDOR_ST_A_M45PE20:
 381                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
 382                         break;
 383 @@ -11833,6 +11863,118 @@
 384                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
 385  }
 386
 387 +static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
 388 +{
 389 +       u32 nvcfg1, nvmpinstrp;
 390 +
 391 +       nvcfg1 = tr32(NVRAM_CFG1);
 392 +       nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
 393 +
 394 +       switch (nvmpinstrp) {
 395 +       case FLASH_5720_EEPROM_HD:
 396 +       case FLASH_5720_EEPROM_LD:
 397 +               tp->nvram_jedecnum = JEDEC_ATMEL;
 398 +               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
 399 +
 400 +               nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
 401 +               tw32(NVRAM_CFG1, nvcfg1);
 402 +               if (nvmpinstrp == FLASH_5720_EEPROM_HD)
 403 +                       tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
 404 +               else
 405 +                       tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
 406 +               return;
 407 +       case FLASH_5720VENDOR_M_ATMEL_DB011D:
 408 +       case FLASH_5720VENDOR_A_ATMEL_DB011B:
 409 +       case FLASH_5720VENDOR_A_ATMEL_DB011D:
 410 +       case FLASH_5720VENDOR_M_ATMEL_DB021D:
 411 +       case FLASH_5720VENDOR_A_ATMEL_DB021B:
 412 +       case FLASH_5720VENDOR_A_ATMEL_DB021D:
 413 +       case FLASH_5720VENDOR_M_ATMEL_DB041D:
 414 +       case FLASH_5720VENDOR_A_ATMEL_DB041B:
 415 +       case FLASH_5720VENDOR_A_ATMEL_DB041D:
 416 +       case FLASH_5720VENDOR_M_ATMEL_DB081D:
 417 +       case FLASH_5720VENDOR_A_ATMEL_DB081D:
 418 +       case FLASH_5720VENDOR_ATMEL_45USPT:
 419 +               tp->nvram_jedecnum = JEDEC_ATMEL;
 420 +               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
 421 +               tp->tg3_flags2 |= TG3_FLG2_FLASH;
 422 +
 423 +               switch (nvmpinstrp) {
 424 +               case FLASH_5720VENDOR_M_ATMEL_DB021D:
 425 +               case FLASH_5720VENDOR_A_ATMEL_DB021B:
 426 +               case FLASH_5720VENDOR_A_ATMEL_DB021D:
 427 +                       tp->nvram_size = TG3_NVRAM_SIZE_256KB;
 428 +                       break;
 429 +               case FLASH_5720VENDOR_M_ATMEL_DB041D:
 430 +               case FLASH_5720VENDOR_A_ATMEL_DB041B:
 431 +               case FLASH_5720VENDOR_A_ATMEL_DB041D:
 432 +                       tp->nvram_size = TG3_NVRAM_SIZE_512KB;
 433 +                       break;
 434 +               case FLASH_5720VENDOR_M_ATMEL_DB081D:
 435 +               case FLASH_5720VENDOR_A_ATMEL_DB081D:
 436 +                       tp->nvram_size = TG3_NVRAM_SIZE_1MB;
 437 +                       break;
 438 +               default:
 439 +                       tp->nvram_size = TG3_NVRAM_SIZE_128KB;
 440 +                       break;
 441 +               }
 442 +               break;
 443 +       case FLASH_5720VENDOR_M_ST_M25PE10:
 444 +       case FLASH_5720VENDOR_M_ST_M45PE10:
 445 +       case FLASH_5720VENDOR_A_ST_M25PE10:
 446 +       case FLASH_5720VENDOR_A_ST_M45PE10:
 447 +       case FLASH_5720VENDOR_M_ST_M25PE20:
 448 +       case FLASH_5720VENDOR_M_ST_M45PE20:
 449 +       case FLASH_5720VENDOR_A_ST_M25PE20:
 450 +       case FLASH_5720VENDOR_A_ST_M45PE20:
 451 +       case FLASH_5720VENDOR_M_ST_M25PE40:
 452 +       case FLASH_5720VENDOR_M_ST_M45PE40:
 453 +       case FLASH_5720VENDOR_A_ST_M25PE40:
 454 +       case FLASH_5720VENDOR_A_ST_M45PE40:
 455 +       case FLASH_5720VENDOR_M_ST_M25PE80:
 456 +       case FLASH_5720VENDOR_M_ST_M45PE80:
 457 +       case FLASH_5720VENDOR_A_ST_M25PE80:
 458 +       case FLASH_5720VENDOR_A_ST_M45PE80:
 459 +       case FLASH_5720VENDOR_ST_25USPT:
 460 +       case FLASH_5720VENDOR_ST_45USPT:
 461 +               tp->nvram_jedecnum = JEDEC_ST;
 462 +               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
 463 +               tp->tg3_flags2 |= TG3_FLG2_FLASH;
 464 +
 465 +               switch (nvmpinstrp) {
 466 +               case FLASH_5720VENDOR_M_ST_M25PE20:
 467 +               case FLASH_5720VENDOR_M_ST_M45PE20:
 468 +               case FLASH_5720VENDOR_A_ST_M25PE20:
 469 +               case FLASH_5720VENDOR_A_ST_M45PE20:
 470 +                       tp->nvram_size = TG3_NVRAM_SIZE_256KB;
 471 +                       break;
 472 +               case FLASH_5720VENDOR_M_ST_M25PE40:
 473 +               case FLASH_5720VENDOR_M_ST_M45PE40:
 474 +               case FLASH_5720VENDOR_A_ST_M25PE40:
 475 +               case FLASH_5720VENDOR_A_ST_M45PE40:
 476 +                       tp->nvram_size = TG3_NVRAM_SIZE_512KB;
 477 +                       break;
 478 +               case FLASH_5720VENDOR_M_ST_M25PE80:
 479 +               case FLASH_5720VENDOR_M_ST_M45PE80:
 480 +               case FLASH_5720VENDOR_A_ST_M25PE80:
 481 +               case FLASH_5720VENDOR_A_ST_M45PE80:
 482 +                       tp->nvram_size = TG3_NVRAM_SIZE_1MB;
 483 +                       break;
 484 +               default:
 485 +                       tp->nvram_size = TG3_NVRAM_SIZE_128KB;
 486 +                       break;
 487 +               }
 488 +               break;
 489 +       default:
 490 +               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
 491 +               return;
 492 +       }
 493 +
 494 +       tg3_nvram_get_pagesize(tp, nvcfg1);
 495 +       if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
 496 +               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
 497 +}
 498 +
 499  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 500  static void __devinit tg3_nvram_init(struct tg3 *tp)
 501  {
 502 @@ -11880,6 +12022,8 @@
 503                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 504                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
 505                         tg3_get_5717_nvram_info(tp);
 506 +               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
 507 +                       tg3_get_5720_nvram_info(tp);
 508                 else
 509                         tg3_get_nvram_info(tp);
 510
 511 @@ -12417,7 +12561,7 @@
 512                 if (cfg2 & (1 << 18))
 513                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
 514
 515 -               if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
 516 +               if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
 517                     ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
 518                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
 519                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
 520 @@ -12425,7 +12569,7 @@
 521
 522                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
 523                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
 524 -                   !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
 525 +                   !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
 526                         u32 cfg3;
 527
 528                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
 529 @@ -13029,14 +13173,13 @@
 530
 531  static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
 532  {
 533 -       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 534 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
 535 -               return 4096;
 536 +       if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
 537 +               return TG3_RX_RET_MAX_SIZE_5717;
 538         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
 539                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 540 -               return 1024;
 541 +               return TG3_RX_RET_MAX_SIZE_5700;
 542         else
 543 -               return 512;
 544 +               return TG3_RX_RET_MAX_SIZE_5705;
 545  }
 546
 547  static int __devinit tg3_get_invariants(struct tg3 *tp)
 548 @@ -13084,6 +13227,7 @@
 549                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
 550                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
 551                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
 552 +                   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
 553                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
 554                         pci_read_config_dword(tp->pdev,
 555                                               TG3PCI_GEN2_PRODID_ASICREV,
 556 @@ -13239,14 +13383,19 @@
 557
 558         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 559             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
 560 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
 561 +           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 562 +           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
 563                 tp->pdev_peer = tg3_find_peer(tp);
 564
 565         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 566             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
 567 -           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
 568 +           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
 569                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
 570
 571 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
 572 +           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
 573 +               tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
 574 +
 575         /* Intentionally exclude ASIC_REV_5906 */
 576         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
 577             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
 578 @@ -13254,7 +13403,7 @@
 579             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
 580             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
 581             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
 582 -           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
 583 +           (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
 584                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
 585
 586         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
 587 @@ -13284,7 +13433,7 @@
 588         }
 589
 590         /* Determine TSO capabilities */
 591 -       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
 592 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
 593                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
 594         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
 595                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
 596 @@ -13320,7 +13469,7 @@
 597                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
 598                 }
 599
 600 -               if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 601 +               if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
 602                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
 603                         tp->irq_max = TG3_IRQ_MAX_VECS;
 604                 }
 605 @@ -13336,6 +13485,9 @@
 606         }
 607
 608         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
 609 +               tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
 610 +
 611 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
 612                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
 613
 614         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
 615 @@ -13353,7 +13505,8 @@
 616                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
 617
 618                 tp->pcie_readrq = 4096;
 619 -               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
 620 +               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
 621 +                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 622                         u16 word;
 623
 624                         pci_read_config_word(tp->pdev,
 625 @@ -13574,7 +13727,7 @@
 626             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
 627             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
 628             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
 629 -           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
 630 +           (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
 631                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
 632
 633         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
 634 @@ -13653,7 +13806,7 @@
 635             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 636             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
 637             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
 638 -           !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
 639 +           !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
 640                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
 641                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
 642                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
 643 @@ -13694,7 +13847,15 @@
 644
 645         /* Initialize data/descriptor byte/word swapping. */
 646         val = tr32(GRC_MODE);
 647 +       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
 648 +               val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
 649 +                       GRC_MODE_WORD_SWAP_B2HRX_DATA |
 650 +                       GRC_MODE_B2HRX_ENABLE |
 651 +                       GRC_MODE_HTX2B_ENABLE |
 652 +                       GRC_MODE_HOST_STACKUP);
 653 +       else
 654         val &= GRC_MODE_HOST_STACKUP;
 655 +
 656         tw32(GRC_MODE, val | tp->grc_mode);
 657
 658         tg3_switch_clocks(tp);
 659 @@ -13900,8 +14061,7 @@
 660                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
 661                 else
 662                         tg3_nvram_unlock(tp);
 663 -       } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
 664 -                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
 665 +       } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 666                 if (PCI_FUNC(tp->pdev->devfn) & 1)
 667                         mac_offset = 0xcc;
 668                 if (PCI_FUNC(tp->pdev->devfn) > 1)
 669 @@ -13990,7 +14150,7 @@
 670  #endif
 671  #endif
 672
 673 -       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 674 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
 675                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
 676                 goto out;
 677         }
 678 @@ -14201,7 +14361,7 @@
 679
 680         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
 681
 682 -       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
 683 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
 684                 goto out;
 685
 686         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
 687 @@ -14398,7 +14558,7 @@
 688
 689  static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
 690  {
 691 -       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
 692 +       if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
 693                 tp->bufmgr_config.mbuf_read_dma_low_water =
 694                         DEFAULT_MB_RDMA_LOW_WATER_5705;
 695                 tp->bufmgr_config.mbuf_mac_rx_low_water =
 696 @@ -14476,6 +14636,7 @@
 697         case TG3_PHY_ID_BCM5718S:       return "5718S";
 698         case TG3_PHY_ID_BCM57765:       return "57765";
 699         case TG3_PHY_ID_BCM5719C:       return "5719C";
 700 +       case TG3_PHY_ID_BCM5720C:       return "5720C";
 701         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
 702         case 0:                 return "serdes";
 703         default:                return "unknown";
 704 @@ -14724,8 +14885,7 @@
 705         }
 706
 707         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
 708 -           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
 709 -           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
 710 +           !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
 711                 dev->netdev_ops = &tg3_netdev_ops;
 712         else
 713                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
 714 diff -Nurb linux-2.6.32-27.planetlab.i686/drivers/net/tg3.h ../kernel-2.6/linux-2.6.32-27.planetlab.i686/drivers/net/tg3.h
 715 --- linux-2.6.32-27.planetlab.i686/drivers/net/tg3.h    2011-05-10 14:38:09.000000000 -0400
 716 +++ ../kernel-2.6/linux-2.6.32-27.planetlab.i686/drivers/net/tg3.h      2012-05-01 09:39:43.237312425 -0400
 717 @@ -25,9 +25,13 @@
 718
 719  #define TG3_RX_INTERNAL_RING_SZ_5906   32
 720
 721 -#define RX_STD_MAX_SIZE_5705           512
 722 -#define RX_STD_MAX_SIZE_5717           2048
 723 -#define RX_JUMBO_MAX_SIZE              0xdeadbeef /* XXX */
 724 +#define TG3_RX_STD_MAX_SIZE_5700       512
 725 +#define TG3_RX_STD_MAX_SIZE_5717       2048
 726 +#define TG3_RX_JMB_MAX_SIZE_5700       256
 727 +#define TG3_RX_JMB_MAX_SIZE_5717       1024
 728 +#define TG3_RX_RET_MAX_SIZE_5700       1024
 729 +#define TG3_RX_RET_MAX_SIZE_5705       512
 730 +#define TG3_RX_RET_MAX_SIZE_5717       4096
 731
 732  /* First 256 bytes are a mirror of PCI config space. */
 733  #define TG3PCI_VENDOR                  0x00000000
 734 @@ -55,6 +59,7 @@
 735  #define  TG3PCI_DEVICE_TIGON3_57791     0x16b2
 736  #define  TG3PCI_DEVICE_TIGON3_57795     0x16b6
 737  #define  TG3PCI_DEVICE_TIGON3_5719      0x1657
 738 +#define  TG3PCI_DEVICE_TIGON3_5720      0x165f
 739  /* 0x04 --> 0x2c unused */
 740  #define TG3PCI_SUBVENDOR_ID_BROADCOM           PCI_VENDOR_ID_BROADCOM
 741  #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6   0x1644
 742 @@ -163,6 +168,7 @@
 743  #define   ASIC_REV_5717                         0x5717
 744  #define   ASIC_REV_57765                0x57785
 745  #define   ASIC_REV_5719                         0x5719
 746 +#define   ASIC_REV_5720                         0x5720
 747  #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 748  #define   CHIPREV_5700_AX               0x70
 749  #define   CHIPREV_5700_BX               0x71
 750 @@ -473,6 +479,8 @@
 751  #define  TX_MODE_BIG_BCKOFF_ENABLE      0x00000020
 752  #define  TX_MODE_LONG_PAUSE_ENABLE      0x00000040
 753  #define  TX_MODE_MBUF_LOCKUP_FIX        0x00000100
 754 +#define  TX_MODE_JMB_FRM_LEN            0x00400000
 755 +#define  TX_MODE_CNT_DN_MODE            0x00800000
 756  #define MAC_TX_STATUS                  0x00000460
 757  #define  TX_STATUS_XOFFED               0x00000001
 758  #define  TX_STATUS_SENT_XOFF            0x00000002
 759 @@ -487,6 +495,8 @@
 760  #define  TX_LENGTHS_IPG_SHIFT           8
 761  #define  TX_LENGTHS_IPG_CRS_MASK        0x00003000
 762  #define  TX_LENGTHS_IPG_CRS_SHIFT       12
 763 +#define  TX_LENGTHS_JMB_FRM_LEN_MSK     0x00ff0000
 764 +#define  TX_LENGTHS_CNT_DWN_VAL_MSK     0xff000000
 765  #define MAC_RX_MODE                    0x00000468
 766  #define  RX_MODE_RESET                  0x00000001
 767  #define  RX_MODE_ENABLE                         0x00000002
 768 @@ -1079,6 +1089,9 @@
 769  #define  CPMU_HST_ACC_MACCLK_6_25       0x00130000
 770  /* 0x3620 --> 0x3630 unused */
 771
 772 +#define TG3_CPMU_CLCK_ORIDE            0x00003624
 773 +#define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN   0x80000000
 774 +
 775  #define TG3_CPMU_CLCK_STAT             0x00003630
 776  #define  CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000
 777  #define  CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000
 778 @@ -1321,6 +1334,7 @@
 779  #define  RDMAC_MODE_MULT_DMA_RD_DIS     0x01000000
 780  #define  RDMAC_MODE_IPV4_LSO_EN                 0x08000000
 781  #define  RDMAC_MODE_IPV6_LSO_EN                 0x10000000
 782 +#define  RDMAC_MODE_H2BNC_VLAN_DET      0x20000000
 783  #define RDMAC_STATUS                   0x00004804
 784  #define  RDMAC_STATUS_TGTABORT          0x00000004
 785  #define  RDMAC_STATUS_MSTABORT          0x00000008
 786 @@ -1609,6 +1623,8 @@
 787  #define  GRC_MODE_WSWAP_NONFRM_DATA    0x00000004
 788  #define  GRC_MODE_BSWAP_DATA           0x00000010
 789  #define  GRC_MODE_WSWAP_DATA           0x00000020
 790 +#define  GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
 791 +#define  GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
 792  #define  GRC_MODE_SPLITHDR             0x00000100
 793  #define  GRC_MODE_NOFRM_CRACKING       0x00000200
 794  #define  GRC_MODE_INCL_CRC             0x00000400
 795 @@ -1616,8 +1632,10 @@
 796  #define  GRC_MODE_NOIRQ_ON_SENDS       0x00002000
 797  #define  GRC_MODE_NOIRQ_ON_RCV         0x00004000
 798  #define  GRC_MODE_FORCE_PCI32BIT       0x00008000
 799 +#define  GRC_MODE_B2HRX_ENABLE         0x00008000
 800  #define  GRC_MODE_HOST_STACKUP         0x00010000
 801  #define  GRC_MODE_HOST_SENDBDS         0x00020000
 802 +#define  GRC_MODE_HTX2B_ENABLE         0x00040000
 803  #define  GRC_MODE_NO_TX_PHDR_CSUM      0x00100000
 804  #define  GRC_MODE_NVRAM_WR_ENABLE      0x00200000
 805  #define  GRC_MODE_PCIE_TL_SEL          0x00000000
 806 @@ -1814,6 +1832,38 @@
 807  #define  FLASH_5717VENDOR_ATMEL_45USPT  0x03400000
 808  #define  FLASH_5717VENDOR_ST_25USPT     0x03400002
 809  #define  FLASH_5717VENDOR_ST_45USPT     0x03400001
 810 +#define  FLASH_5720_EEPROM_HD           0x00000001
 811 +#define  FLASH_5720_EEPROM_LD           0x00000003
 812 +#define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
 813 +#define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
 814 +#define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
 815 +#define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
 816 +#define  FLASH_5720VENDOR_M_ST_M25PE10  0x02000000
 817 +#define  FLASH_5720VENDOR_M_ST_M25PE20  0x02000002
 818 +#define  FLASH_5720VENDOR_M_ST_M25PE40  0x02000001
 819 +#define  FLASH_5720VENDOR_M_ST_M25PE80  0x02000003
 820 +#define  FLASH_5720VENDOR_M_ST_M45PE10  0x03000000
 821 +#define  FLASH_5720VENDOR_M_ST_M45PE20  0x03000002
 822 +#define  FLASH_5720VENDOR_M_ST_M45PE40  0x03000001
 823 +#define  FLASH_5720VENDOR_M_ST_M45PE80  0x03000003
 824 +#define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
 825 +#define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
 826 +#define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
 827 +#define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
 828 +#define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
 829 +#define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
 830 +#define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
 831 +#define  FLASH_5720VENDOR_A_ST_M25PE10  0x02800000
 832 +#define  FLASH_5720VENDOR_A_ST_M25PE20  0x02800002
 833 +#define  FLASH_5720VENDOR_A_ST_M25PE40  0x02800001
 834 +#define  FLASH_5720VENDOR_A_ST_M25PE80  0x02800003
 835 +#define  FLASH_5720VENDOR_A_ST_M45PE10  0x02c00000
 836 +#define  FLASH_5720VENDOR_A_ST_M45PE20  0x02c00002
 837 +#define  FLASH_5720VENDOR_A_ST_M45PE40  0x02c00001
 838 +#define  FLASH_5720VENDOR_A_ST_M45PE80  0x02c00003
 839 +#define  FLASH_5720VENDOR_ATMEL_45USPT  0x03c00000
 840 +#define  FLASH_5720VENDOR_ST_25USPT     0x03c00002
 841 +#define  FLASH_5720VENDOR_ST_45USPT     0x03c00001
 842  #define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
 843  #define  FLASH_5752PAGE_SIZE_256        0x00000000
 844  #define  FLASH_5752PAGE_SIZE_512        0x10000000
 845 @@ -2889,6 +2939,7 @@
 846  #define TG3_FLG3_5701_DMA_BUG          0x00000008
 847  #define TG3_FLG3_USE_PHYLIB            0x00000010
 848  #define TG3_FLG3_MDIOBUS_INITED                0x00000020
 849 +#define TG3_FLG3_LRG_PROD_RING_CAP     0x00000080
 850  #define TG3_FLG3_RGMII_INBAND_DISABLE  0x00000100
 851  #define TG3_FLG3_RGMII_EXT_IBND_RX_EN  0x00000200
 852  #define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
 853 @@ -2902,7 +2953,8 @@
 854  #define TG3_FLG3_SHORT_DMA_BUG         0x00200000
 855  #define TG3_FLG3_USE_JUMBO_BDFLAG      0x00400000
 856  #define TG3_FLG3_L1PLLPD_EN            0x00800000
 857 -#define TG3_FLG3_5717_PLUS             0x01000000
 858 +#define TG3_FLG3_57765_PLUS            0x01000000
 859 +#define TG3_FLG3_5717_PLUS             0x04000000
 860
 861         struct timer_list               timer;
 862         u16                             timer_counter;
 863 @@ -2974,6 +3026,7 @@
 864  #define TG3_PHY_ID_BCM5718S            0xbc050ff0
 865  #define TG3_PHY_ID_BCM57765            0x5c0d8a40
 866  #define TG3_PHY_ID_BCM5719C            0x5c0d8a20
 867 +#define TG3_PHY_ID_BCM5720C            0x5c0d8b60
 868  #define TG3_PHY_ID_BCM5906             0xdc00ac40
 869  #define TG3_PHY_ID_BCM8002             0x60010140
 870  #define TG3_PHY_ID_INVALID             0xffffffff
 871 @@ -3040,6 +3093,7 @@
 872
 873         int                             nvram_lock_cnt;
 874         u32                             nvram_size;
 875 +#define TG3_NVRAM_SIZE_2KB             0x00000800
 876  #define TG3_NVRAM_SIZE_64KB            0x00010000
 877  #define TG3_NVRAM_SIZE_128KB           0x00020000
 878  #define TG3_NVRAM_SIZE_256KB           0x00040000
 879 @@ -3055,6 +3109,9 @@
 880  #define JEDEC_SAIFUN                   0x4f
 881  #define JEDEC_SST                      0xbf
 882
 883 +#define ATMEL_AT24C02_CHIP_SIZE                TG3_NVRAM_SIZE_2KB
 884 +#define ATMEL_AT24C02_PAGE_SIZE                (8)
 885 +
 886  #define ATMEL_AT24C64_CHIP_SIZE                TG3_NVRAM_SIZE_64KB
 887  #define ATMEL_AT24C64_PAGE_SIZE                (32)
 888