linux-2.6-010-e1000e-ich10lan.patch

   1 diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
   2 index 14b0e6c..4b21fa9 100644
   3 --- a/drivers/net/e1000e/defines.h
   4 +++ b/drivers/net/e1000e/defines.h
   5 @@ -505,6 +505,7 @@
   6  #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
   7
   8  /* Autoneg Expansion Register */
   9 +#define NWAY_ER_LP_NWAY_CAPS     0x0001 /* LP has Auto Neg Capability */
  10
  11  /* 1000BASE-T Control Register */
  12  #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
  13 @@ -540,6 +541,7 @@
  14  #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
  15  #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
  16  #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
  17 +#define E1000_EECD_PRES      0x00000100 /* NVM Present */
  18  #define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
  19  /* NVM Addressing bits based on type (0-small, 1-large) */
  20  #define E1000_EECD_ADDR_BITS 0x00000400
  21 diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
  22 index 4ee3d97..d5f8e8a 100644
  23 --- a/drivers/net/e1000e/e1000.h
  24 +++ b/drivers/net/e1000e/e1000.h
  25 @@ -98,6 +98,7 @@ enum e1000_boards {
  26         board_80003es2lan,
  27         board_ich8lan,
  28         board_ich9lan,
  29 +       board_ich10lan,
  30  };
  31
  32  struct e1000_queue_stats {
  33 @@ -381,6 +382,7 @@ extern struct e1000_info e1000_82572_info;
  34  extern struct e1000_info e1000_82573_info;
  35  extern struct e1000_info e1000_ich8_info;
  36  extern struct e1000_info e1000_ich9_info;
  37 +extern struct e1000_info e1000_ich10_info;
  38  extern struct e1000_info e1000_es2_info;
  39
  40  extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
  41 @@ -454,6 +456,7 @@ extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
  42  extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
  43  extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  44  extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
  45 +extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
  46  extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
  47  extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
  48  extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
  49 diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
  50 index e2a30dd..5b7e6b5 100644
  51 --- a/drivers/net/e1000e/ethtool.c
  52 +++ b/drivers/net/e1000e/ethtool.c
  53 @@ -788,6 +788,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
  54         case e1000_82573:
  55         case e1000_ich8lan:
  56         case e1000_ich9lan:
  57 +       case e1000_ich10lan:
  58                 toggle = 0x7FFFF033;
  59                 break;
  60         default:
  61 @@ -840,7 +841,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
  62         REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
  63         for (i = 0; i < mac->rar_entry_count; i++)
  64                 REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
  65 -                                      0x8003FFFF, 0xFFFFFFFF);
  66 +                                      ((mac->type == e1000_ich10lan) ?
  67 +                                          0x8007FFFF : 0x8003FFFF),
  68 +                                      0xFFFFFFFF);
  69
  70         for (i = 0; i < mac->mta_reg_count; i++)
  71                 REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
  72 @@ -912,12 +915,23 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
  73
  74         /* Test each interrupt */
  75         for (i = 0; i < 10; i++) {
  76 -               if ((adapter->flags & FLAG_IS_ICH) && (i == 8))
  77 -                       continue;
  78 -
  79                 /* Interrupt to test */
  80                 mask = 1 << i;
  81
  82 +               if (adapter->flags & FLAG_IS_ICH) {
  83 +                       switch (mask) {
  84 +                       case E1000_ICR_RXSEQ:
  85 +                               continue;
  86 +                       case 0x00000100:
  87 +                               if (adapter->hw.mac.type == e1000_ich8lan ||
  88 +                                   adapter->hw.mac.type == e1000_ich9lan)
  89 +                                       continue;
  90 +                               break;
  91 +                       default:
  92 +                               break;
  93 +                       }
  94 +               }
  95 +
  96                 if (!shared_int) {
  97                         /*
  98                          * Disable the interrupt to be reported in
  99 diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
 100 index 74f263a..3005394 100644
 101 --- a/drivers/net/e1000e/hw.h
 102 +++ b/drivers/net/e1000e/hw.h
 103 @@ -356,6 +356,8 @@ enum e1e_registers {
 104  #define E1000_DEV_ID_ICH10_R_BM_LM             0x10CC
 105  #define E1000_DEV_ID_ICH10_R_BM_LF             0x10CD
 106  #define E1000_DEV_ID_ICH10_R_BM_V              0x10CE
 107 +#define E1000_DEV_ID_ICH10_D_BM_LM             0x10DE
 108 +#define E1000_DEV_ID_ICH10_D_BM_LF             0x10DF
 109
 110  #define E1000_FUNC_1 1
 111
 112 @@ -366,6 +368,7 @@ enum e1000_mac_type {
 113         e1000_80003es2lan,
 114         e1000_ich8lan,
 115         e1000_ich9lan,
 116 +       e1000_ich10lan,
 117  };
 118
 119  enum e1000_media_type {
 120 diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
 121 index 79be768..d2acf48 100644
 122 --- a/drivers/net/e1000e/ich8lan.c
 123 +++ b/drivers/net/e1000e/ich8lan.c
 124 @@ -171,12 +171,15 @@ static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 125  static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 126  static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 127                                                 u32 offset, u8 byte);
 128 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 129 +                                        u8 *data);
 130  static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 131                                          u16 *data);
 132  static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 133                                          u8 size, u16 *data);
 134  static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 135  static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 136 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 137
 138  static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 139  {
 140 @@ -928,6 +931,56 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 141  }
 142
 143  /**
 144 + *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
 145 + *  @hw: pointer to the HW structure
 146 + *  @bank:  pointer to the variable that returns the active bank
 147 + *
 148 + *  Reads signature byte from the NVM using the flash access registers.
 149 + **/
 150 +static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 151 +{
 152 +       struct e1000_nvm_info *nvm = &hw->nvm;
 153 +       /* flash bank size is in words */
 154 +       u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
 155 +       u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
 156 +       u8 bank_high_byte = 0;
 157 +
 158 +       if (hw->mac.type != e1000_ich10lan) {
 159 +               if (er32(EECD) & E1000_EECD_SEC1VAL)
 160 +                       *bank = 1;
 161 +               else
 162 +                       *bank = 0;
 163 +       } else {
 164 +               /*
 165 +                * Make sure the signature for bank 0 is valid,
 166 +                * if not check for bank1
 167 +                */
 168 +               e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
 169 +               if ((bank_high_byte & 0xC0) == 0x80) {
 170 +                       *bank = 0;
 171 +               } else {
 172 +                       /*
 173 +                        * find if segment 1 is valid by verifying
 174 +                        * bit 15:14 = 10b in word 0x13
 175 +                        */
 176 +                       e1000_read_flash_byte_ich8lan(hw,
 177 +                                                     act_offset + bank1_offset,
 178 +                                                     &bank_high_byte);
 179 +
 180 +                       /* bank1 has a valid signature equivalent to SEC1V */
 181 +                       if ((bank_high_byte & 0xC0) == 0x80) {
 182 +                               *bank = 1;
 183 +                       } else {
 184 +                               hw_dbg(hw, "ERROR: EEPROM not present\n");
 185 +                               return -E1000_ERR_NVM;
 186 +                       }
 187 +               }
 188 +       }
 189 +
 190 +       return 0;
 191 +}
 192 +
 193 +/**
 194   *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
 195   *  @hw: pointer to the HW structure
 196   *  @offset: The offset (in bytes) of the word(s) to read.
 197 @@ -943,6 +996,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 198         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 199         u32 act_offset;
 200         s32 ret_val;
 201 +       u32 bank = 0;
 202         u16 i, word;
 203
 204         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
 205 @@ -955,10 +1009,11 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 206         if (ret_val)
 207                 return ret_val;
 208
 209 -       /* Start with the bank offset, then add the relative offset. */
 210 -       act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
 211 -                    ? nvm->flash_bank_size
 212 -                    : 0;
 213 +       ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
 214 +       if (ret_val)
 215 +               return ret_val;
 216 +
 217 +       act_offset = (bank) ? nvm->flash_bank_size : 0;
 218         act_offset += offset;
 219
 220         for (i = 0; i < words; i++) {
 221 @@ -1106,6 +1161,29 @@ static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 222  }
 223
 224  /**
 225 + *  e1000_read_flash_byte_ich8lan - Read byte from flash
 226 + *  @hw: pointer to the HW structure
 227 + *  @offset: The offset of the byte to read.
 228 + *  @data: Pointer to a byte to store the value read.
 229 + *
 230 + *  Reads a single byte from the NVM using the flash access registers.
 231 + **/
 232 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 233 +                                        u8 *data)
 234 +{
 235 +       s32 ret_val;
 236 +       u16 word = 0;
 237 +
 238 +       ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
 239 +       if (ret_val)
 240 +               return ret_val;
 241 +
 242 +       *data = (u8)word;
 243 +
 244 +       return 0;
 245 +}
 246 +
 247 +/**
 248   *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
 249   *  @hw: pointer to the HW structure
 250   *  @offset: The offset (in bytes) of the byte or word to read.
 251 @@ -1236,7 +1314,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 252  {
 253         struct e1000_nvm_info *nvm = &hw->nvm;
 254         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 255 -       u32 i, act_offset, new_bank_offset, old_bank_offset;
 256 +       u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
 257         s32 ret_val;
 258         u16 data;
 259
 260 @@ -1256,7 +1334,11 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 261          * write to bank 0 etc.  We also need to erase the segment that
 262          * is going to be written
 263          */
 264 -       if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
 265 +       ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
 266 +       if (ret_val)
 267 +               return ret_val;
 268 +
 269 +       if (bank == 0) {
 270                 new_bank_offset = nvm->flash_bank_size;
 271                 old_bank_offset = 0;
 272                 e1000_erase_flash_bank_ich8lan(hw, 1);
 273 @@ -2272,13 +2354,14 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
 274   *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
 275   *  to a lower speed.
 276   *
 277 - *  Should only be called for ICH9 devices.
 278 + *  Should only be called for ICH9 and ICH10 devices.
 279   **/
 280  void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
 281  {
 282         u32 phy_ctrl;
 283
 284 -       if (hw->mac.type == e1000_ich9lan) {
 285 +       if ((hw->mac.type == e1000_ich10lan) ||
 286 +           (hw->mac.type == e1000_ich9lan)) {
 287                 phy_ctrl = er32(PHY_CTRL);
 288                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
 289                             E1000_PHY_CTRL_GBE_DISABLE;
 290 @@ -2336,6 +2419,39 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
 291  }
 292
 293  /**
 294 + *  e1000_get_cfg_done_ich8lan - Read config done bit
 295 + *  @hw: pointer to the HW structure
 296 + *
 297 + *  Read the management control register for the config done bit for
 298 + *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
 299 + *  to read the config done bit, so an error is *ONLY* logged and returns
 300 + *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
 301 + *  would not be able to be reset or change link.
 302 + **/
 303 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
 304 +{
 305 +       u32 bank = 0;
 306 +
 307 +       e1000e_get_cfg_done(hw);
 308 +
 309 +       /* If EEPROM is not marked present, init the IGP 3 PHY manually */
 310 +       if (hw->mac.type != e1000_ich10lan) {
 311 +               if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
 312 +                   (hw->phy.type == e1000_phy_igp_3)) {
 313 +                       e1000e_phy_init_script_igp3(hw);
 314 +               }
 315 +       } else {
 316 +               if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
 317 +                       /* Maybe we should do a basic PHY config */
 318 +                       hw_dbg(hw, "EEPROM not present\n");
 319 +                       return -E1000_ERR_CONFIG;
 320 +               }
 321 +       }
 322 +
 323 +       return 0;
 324 +}
 325 +
 326 +/**
 327   *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
 328   *  @hw: pointer to the HW structure
 329   *
 330 @@ -2385,7 +2501,7 @@ static struct e1000_phy_operations ich8_phy_ops = {
 331         .check_reset_block      = e1000_check_reset_block_ich8lan,
 332         .commit_phy             = NULL,
 333         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
 334 -       .get_cfg_done           = e1000e_get_cfg_done,
 335 +       .get_cfg_done           = e1000_get_cfg_done_ich8lan,
 336         .get_cable_length       = e1000e_get_cable_length_igp_2,
 337         .get_phy_info           = e1000_get_phy_info_ich8lan,
 338         .read_phy_reg           = e1000e_read_phy_reg_igp,
 339 @@ -2440,3 +2556,20 @@ struct e1000_info e1000_ich9_info = {
 340         .nvm_ops                = &ich8_nvm_ops,
 341  };
 342
 343 +struct e1000_info e1000_ich10_info = {
 344 +       .mac                    = e1000_ich10lan,
 345 +       .flags                  = FLAG_HAS_JUMBO_FRAMES
 346 +                                 | FLAG_IS_ICH
 347 +                                 | FLAG_HAS_WOL
 348 +                                 | FLAG_RX_CSUM_ENABLED
 349 +                                 | FLAG_HAS_CTRLEXT_ON_LOAD
 350 +                                 | FLAG_HAS_AMT
 351 +                                 | FLAG_HAS_ERT
 352 +                                 | FLAG_HAS_FLASH
 353 +                                 | FLAG_APME_IN_WUC,
 354 +       .pba                    = 10,
 355 +       .get_variants           = e1000_get_variants_ich8lan,
 356 +       .mac_ops                = &ich8_mac_ops,
 357 +       .phy_ops                = &ich8_phy_ops,
 358 +       .nvm_ops                = &ich8_nvm_ops,
 359 +};
 360 diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
 361 index c476982..c4287ca 100644
 362 --- a/drivers/net/e1000e/netdev.c
 363 +++ b/drivers/net/e1000e/netdev.c
 364 @@ -58,6 +58,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
 365         [board_80003es2lan]     = &e1000_es2_info,
 366         [board_ich8lan]         = &e1000_ich8_info,
 367         [board_ich9lan]         = &e1000_ich9_info,
 368 +       [board_ich10lan]        = &e1000_ich10_info,
 369  };
 370
 371  #ifdef DEBUG
 372 @@ -3211,6 +3212,27 @@ static void e1000_watchdog_task(struct work_struct *work)
 373                                                    &adapter->link_duplex);
 374                         e1000_print_link_info(adapter);
 375                         /*
 376 +                        * On supported PHYs, check for duplex mismatch only
 377 +                        * if link has autonegotiated at 10/100 half
 378 +                        */
 379 +                       if ((hw->phy.type == e1000_phy_igp_3 ||
 380 +                            hw->phy.type == e1000_phy_bm) &&
 381 +                           (hw->mac.autoneg == true) &&
 382 +                           (adapter->link_speed == SPEED_10 ||
 383 +                            adapter->link_speed == SPEED_100) &&
 384 +                           (adapter->link_duplex == HALF_DUPLEX)) {
 385 +                               u16 autoneg_exp;
 386 +
 387 +                               e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
 388 +
 389 +                               if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
 390 +                                       e_info("Autonegotiated half duplex but"
 391 +                                              " link partner cannot autoneg. "
 392 +                                              " Try forcing full duplex if "
 393 +                                              "link gets many collisions.\n");
 394 +                       }
 395 +
 396 +                       /*
 397                          * tweak tx_queue_len according to speed/duplex
 398                          * and adjust the timeout factor
 399                          */
 400 @@ -4793,6 +4815,9 @@ static struct pci_device_id e1000_pci_tbl[] = {
 401         { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
 402         { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
 403
 404 +       { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
 405 +       { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
 406 +
 407         { }     /* terminate list */
 408  };
 409  MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
 410 diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
 411 index b133dcf..16724f8 100644
 412 --- a/drivers/net/e1000e/phy.c
 413 +++ b/drivers/net/e1000e/phy.c
 414 @@ -1720,6 +1720,91 @@ s32 e1000e_get_cfg_done(struct e1000_hw *hw)
 415         return 0;
 416  }
 417
 418 +/**
 419 + *  e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
 420 + *  @hw: pointer to the HW structure
 421 + *
 422 + *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
 423 + **/
 424 +s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
 425 +{
 426 +       hw_dbg(hw, "Running IGP 3 PHY init script\n");
 427 +
 428 +       /* PHY init IGP 3 */
 429 +       /* Enable rise/fall, 10-mode work in class-A */
 430 +       e1e_wphy(hw, 0x2F5B, 0x9018);
 431 +       /* Remove all caps from Replica path filter */
 432 +       e1e_wphy(hw, 0x2F52, 0x0000);
 433 +       /* Bias trimming for ADC, AFE and Driver (Default) */
 434 +       e1e_wphy(hw, 0x2FB1, 0x8B24);
 435 +       /* Increase Hybrid poly bias */
 436 +       e1e_wphy(hw, 0x2FB2, 0xF8F0);
 437 +       /* Add 4% to Tx amplitude in Gig mode */
 438 +       e1e_wphy(hw, 0x2010, 0x10B0);
 439 +       /* Disable trimming (TTT) */
 440 +       e1e_wphy(hw, 0x2011, 0x0000);
 441 +       /* Poly DC correction to 94.6% + 2% for all channels */
 442 +       e1e_wphy(hw, 0x20DD, 0x249A);
 443 +       /* ABS DC correction to 95.9% */
 444 +       e1e_wphy(hw, 0x20DE, 0x00D3);
 445 +       /* BG temp curve trim */
 446 +       e1e_wphy(hw, 0x28B4, 0x04CE);
 447 +       /* Increasing ADC OPAMP stage 1 currents to max */
 448 +       e1e_wphy(hw, 0x2F70, 0x29E4);
 449 +       /* Force 1000 ( required for enabling PHY regs configuration) */
 450 +       e1e_wphy(hw, 0x0000, 0x0140);
 451 +       /* Set upd_freq to 6 */
 452 +       e1e_wphy(hw, 0x1F30, 0x1606);
 453 +       /* Disable NPDFE */
 454 +       e1e_wphy(hw, 0x1F31, 0xB814);
 455 +       /* Disable adaptive fixed FFE (Default) */
 456 +       e1e_wphy(hw, 0x1F35, 0x002A);
 457 +       /* Enable FFE hysteresis */
 458 +       e1e_wphy(hw, 0x1F3E, 0x0067);
 459 +       /* Fixed FFE for short cable lengths */
 460 +       e1e_wphy(hw, 0x1F54, 0x0065);
 461 +       /* Fixed FFE for medium cable lengths */
 462 +       e1e_wphy(hw, 0x1F55, 0x002A);
 463 +       /* Fixed FFE for long cable lengths */
 464 +       e1e_wphy(hw, 0x1F56, 0x002A);
 465 +       /* Enable Adaptive Clip Threshold */
 466 +       e1e_wphy(hw, 0x1F72, 0x3FB0);
 467 +       /* AHT reset limit to 1 */
 468 +       e1e_wphy(hw, 0x1F76, 0xC0FF);
 469 +       /* Set AHT master delay to 127 msec */
 470 +       e1e_wphy(hw, 0x1F77, 0x1DEC);
 471 +       /* Set scan bits for AHT */
 472 +       e1e_wphy(hw, 0x1F78, 0xF9EF);
 473 +       /* Set AHT Preset bits */
 474 +       e1e_wphy(hw, 0x1F79, 0x0210);
 475 +       /* Change integ_factor of channel A to 3 */
 476 +       e1e_wphy(hw, 0x1895, 0x0003);
 477 +       /* Change prop_factor of channels BCD to 8 */
 478 +       e1e_wphy(hw, 0x1796, 0x0008);
 479 +       /* Change cg_icount + enable integbp for channels BCD */
 480 +       e1e_wphy(hw, 0x1798, 0xD008);
 481 +       /*
 482 +        * Change cg_icount + enable integbp + change prop_factor_master
 483 +        * to 8 for channel A
 484 +        */
 485 +       e1e_wphy(hw, 0x1898, 0xD918);
 486 +       /* Disable AHT in Slave mode on channel A */
 487 +       e1e_wphy(hw, 0x187A, 0x0800);
 488 +       /*
 489 +        * Enable LPLU and disable AN to 1000 in non-D0a states,
 490 +        * Enable SPD+B2B
 491 +        */
 492 +       e1e_wphy(hw, 0x0019, 0x008D);
 493 +       /* Enable restart AN on an1000_dis change */
 494 +       e1e_wphy(hw, 0x001B, 0x2080);
 495 +       /* Enable wh_fifo read clock in 10/100 modes */
 496 +       e1e_wphy(hw, 0x0014, 0x0045);
 497 +       /* Restart AN, Speed selection is 1000 */
 498 +       e1e_wphy(hw, 0x0000, 0x1340);
 499 +
 500 +       return 0;
 501 +}
 502 +
 503  /* Internal function pointers */
 504
 505  /**