1 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.c linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.c
2 --- linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.c 2009-06-24 00:32:20.000000000 +0200
5 +/*******************************************************************************
7 + Intel PRO/1000 Linux driver
8 + Copyright(c) 1999 - 2009 Intel Corporation.
10 + This program is free software; you can redistribute it and/or modify it
11 + under the terms and conditions of the GNU General Public License,
12 + version 2, as published by the Free Software Foundation.
14 + This program is distributed in the hope it will be useful, but WITHOUT
15 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 + You should have received a copy of the GNU General Public License along with
20 + this program; if not, write to the Free Software Foundation, Inc.,
21 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 + The full GNU General Public License is included in this distribution in
24 + the file called "COPYING".
26 + Contact Information:
27 + Linux NICS <linux.nics@intel.com>
28 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
29 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 +*******************************************************************************/
34 + * 80003ES2LAN Gigabit Ethernet Controller (Copper)
35 + * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
40 +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
41 +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
42 +static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
43 +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
44 +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
45 +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
46 +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
47 +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
53 +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
54 + u16 words, u16 *data);
55 +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
56 +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
57 +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
58 +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
60 +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
61 +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
62 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
63 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
64 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
65 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
66 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
67 +static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
68 +static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
70 +static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
72 +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
73 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
74 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
75 +static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
76 +static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79 + * A table for the GG82563 cable length where the range is defined
80 + * with a lower bound at "index" and the upper bound at
83 +static const u16 e1000_gg82563_cable_length_table[] =
84 + { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
85 +#define GG82563_CABLE_LENGTH_TABLE_SIZE \
86 + (sizeof(e1000_gg82563_cable_length_table) / \
87 + sizeof(e1000_gg82563_cable_length_table[0]))
90 + * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
91 + * @hw: pointer to the HW structure
93 +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
95 + struct e1000_phy_info *phy = &hw->phy;
96 + s32 ret_val = E1000_SUCCESS;
98 + if (hw->phy.media_type != e1000_media_type_copper) {
99 + phy->type = e1000_phy_none;
102 + phy->ops.power_up = e1000_power_up_phy_copper;
103 + phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
107 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
108 + phy->reset_delay_us = 100;
109 + phy->type = e1000_phy_gg82563;
111 + phy->ops.acquire = e1000_acquire_phy_80003es2lan;
112 + phy->ops.check_polarity = e1000_check_polarity_m88;
113 + phy->ops.check_reset_block = e1000e_check_reset_block_generic;
114 + phy->ops.commit = e1000e_phy_sw_reset;
115 + phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
116 + phy->ops.get_info = e1000e_get_phy_info_m88;
117 + phy->ops.release = e1000_release_phy_80003es2lan;
118 + phy->ops.reset = e1000e_phy_hw_reset_generic;
119 + phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state;
121 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
122 + phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
123 + phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
124 + phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
126 + phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
128 + /* This can only be done after all function pointers are setup. */
129 + ret_val = e1000e_get_phy_id(hw);
131 + /* Verify phy id */
132 + if (phy->id != GG82563_E_PHY_ID) {
133 + ret_val = -E1000_ERR_PHY;
142 + * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
143 + * @hw: pointer to the HW structure
145 +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
147 + struct e1000_nvm_info *nvm = &hw->nvm;
148 + u32 eecd = er32(EECD);
151 + nvm->opcode_bits = 8;
152 + nvm->delay_usec = 1;
153 + switch (nvm->override) {
154 + case e1000_nvm_override_spi_large:
155 + nvm->page_size = 32;
156 + nvm->address_bits = 16;
158 + case e1000_nvm_override_spi_small:
159 + nvm->page_size = 8;
160 + nvm->address_bits = 8;
163 + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
164 + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
168 + nvm->type = e1000_nvm_eeprom_spi;
170 + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
171 + E1000_EECD_SIZE_EX_SHIFT);
174 + * Added to a constant, "size" becomes the left-shift value
175 + * for setting word_size.
177 + size += NVM_WORD_SIZE_BASE_SHIFT;
179 + /* EEPROM access above 16k is unsupported */
182 + nvm->word_size = 1 << size;
184 + /* Function Pointers */
185 + nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
186 + nvm->ops.read = e1000e_read_nvm_eerd;
187 + nvm->ops.release = e1000_release_nvm_80003es2lan;
188 + nvm->ops.update = e1000e_update_nvm_checksum_generic;
189 + nvm->ops.valid_led_default = e1000e_valid_led_default;
190 + nvm->ops.validate = e1000e_validate_nvm_checksum_generic;
191 + nvm->ops.write = e1000_write_nvm_80003es2lan;
193 + return E1000_SUCCESS;
197 + * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
198 + * @hw: pointer to the HW structure
200 +static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
202 + struct e1000_mac_info *mac = &hw->mac;
203 + s32 ret_val = E1000_SUCCESS;
205 + /* Set media type */
206 + switch (hw->device_id) {
207 + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
208 + hw->phy.media_type = e1000_media_type_internal_serdes;
211 + hw->phy.media_type = e1000_media_type_copper;
215 + /* Set mta register count */
216 + mac->mta_reg_count = 128;
217 + /* Set rar entry count */
218 + mac->rar_entry_count = E1000_RAR_ENTRIES;
219 + /* Set if part includes ASF firmware */
220 + mac->asf_firmware_present = true;
221 + /* Set if manageability features are enabled. */
222 + mac->arc_subsystem_valid =
223 + (er32(FWSM) & E1000_FWSM_MODE_MASK)
226 + /* Function pointers */
228 + /* bus type/speed/width */
229 + mac->ops.get_bus_info = e1000e_get_bus_info_pcie;
231 + mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
232 + /* hw initialization */
233 + mac->ops.init_hw = e1000_init_hw_80003es2lan;
235 + mac->ops.setup_link = e1000e_setup_link;
236 + /* physical interface link setup */
237 + mac->ops.setup_physical_interface =
238 + (hw->phy.media_type == e1000_media_type_copper)
239 + ? e1000_setup_copper_link_80003es2lan
240 + : e1000e_setup_fiber_serdes_link;
241 + /* check for link */
242 + switch (hw->phy.media_type) {
243 + case e1000_media_type_copper:
244 + mac->ops.check_for_link = e1000e_check_for_copper_link;
246 + case e1000_media_type_fiber:
247 + mac->ops.check_for_link = e1000e_check_for_fiber_link;
249 + case e1000_media_type_internal_serdes:
250 + mac->ops.check_for_link = e1000e_check_for_serdes_link;
253 + ret_val = -E1000_ERR_CONFIG;
257 + /* check management mode */
258 + mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
259 + /* multicast address update */
260 + mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
262 + mac->ops.write_vfta = e1000e_write_vfta_generic;
263 + /* clearing VFTA */
264 + mac->ops.clear_vfta = e1000e_clear_vfta_generic;
266 + mac->ops.mta_set = e1000_mta_set_generic;
267 + /* read mac address */
268 + mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
270 + mac->ops.id_led_init = e1000e_id_led_init;
272 + mac->ops.blink_led = e1000e_blink_led;
274 + mac->ops.setup_led = e1000_setup_led_generic;
276 + mac->ops.cleanup_led = e1000e_cleanup_led_generic;
277 + /* turn on/off LED */
278 + mac->ops.led_on = e1000e_led_on_generic;
279 + mac->ops.led_off = e1000e_led_off_generic;
280 + /* clear hardware counters */
281 + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
283 + mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
290 + * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
291 + * @hw: pointer to the HW structure
293 + * Called to initialize all function pointers and parameters.
295 +void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
297 + e1000_init_mac_ops_generic(hw);
298 + e1000_init_nvm_ops_generic(hw);
299 + hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
300 + hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
301 + hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
302 + e1000e_get_bus_info_pcie(hw);
306 + * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
307 + * @hw: pointer to the HW structure
309 + * A wrapper to acquire access rights to the correct PHY.
311 +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
315 + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
316 + return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
320 + * e1000_release_phy_80003es2lan - Release rights to access PHY
321 + * @hw: pointer to the HW structure
323 + * A wrapper to release access rights to the correct PHY.
325 +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
329 + mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
330 + e1000_release_swfw_sync_80003es2lan(hw, mask);
335 + * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
336 + * @hw: pointer to the HW structure
338 + * Acquire the semaphore to access the Kumeran interface.
341 +static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
345 + mask = E1000_SWFW_CSR_SM;
347 + return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
351 + * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
352 + * @hw: pointer to the HW structure
354 + * Release the semaphore used to access the Kumeran interface
356 +static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
360 + mask = E1000_SWFW_CSR_SM;
362 + e1000_release_swfw_sync_80003es2lan(hw, mask);
366 + * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
367 + * @hw: pointer to the HW structure
369 + * Acquire the semaphore to access the EEPROM.
371 +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
375 + ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
379 + ret_val = e1000e_acquire_nvm(hw);
382 + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
389 + * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
390 + * @hw: pointer to the HW structure
392 + * Release the semaphore used to access the EEPROM.
394 +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
396 + e1000e_release_nvm(hw);
397 + e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
401 + * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
402 + * @hw: pointer to the HW structure
403 + * @mask: specifies which semaphore to acquire
405 + * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
406 + * will also specify which port we're acquiring the lock for.
408 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
412 + u32 fwmask = mask << 16;
413 + s32 ret_val = E1000_SUCCESS;
414 + s32 i = 0, timeout = 50;
416 + while (i < timeout) {
417 + if (e1000e_get_hw_semaphore(hw)) {
418 + ret_val = -E1000_ERR_SWFW_SYNC;
422 + swfw_sync = er32(SW_FW_SYNC);
423 + if (!(swfw_sync & (fwmask | swmask)))
427 + * Firmware currently using resource (fwmask)
428 + * or other software thread using resource (swmask)
430 + e1000e_put_hw_semaphore(hw);
435 + if (i == timeout) {
436 + e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
437 + ret_val = -E1000_ERR_SWFW_SYNC;
441 + swfw_sync |= swmask;
442 + ew32(SW_FW_SYNC, swfw_sync);
444 + e1000e_put_hw_semaphore(hw);
451 + * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
452 + * @hw: pointer to the HW structure
453 + * @mask: specifies which semaphore to acquire
455 + * Release the SW/FW semaphore used to access the PHY or NVM. The mask
456 + * will also specify which port we're releasing the lock for.
458 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
462 + while (e1000e_get_hw_semaphore(hw) != E1000_SUCCESS)
465 + swfw_sync = er32(SW_FW_SYNC);
466 + swfw_sync &= ~mask;
467 + ew32(SW_FW_SYNC, swfw_sync);
469 + e1000e_put_hw_semaphore(hw);
473 + * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
474 + * @hw: pointer to the HW structure
475 + * @offset: offset of the register to read
476 + * @data: pointer to the data returned from the operation
478 + * Read the GG82563 PHY register.
480 +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
481 + u32 offset, u16 *data)
487 + ret_val = e1000_acquire_phy_80003es2lan(hw);
491 + /* Select Configuration Page */
492 + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
493 + page_select = GG82563_PHY_PAGE_SELECT;
496 + * Use Alternative Page Select register to access
497 + * registers 30 and 31
499 + page_select = GG82563_PHY_PAGE_SELECT_ALT;
502 + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
503 + ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
505 + e1000_release_phy_80003es2lan(hw);
510 + * The "ready" bit in the MDIC register may be incorrectly set
511 + * before the device has completed the "Page Select" MDI
512 + * transaction. So we wait 200us after each MDI command...
516 + /* ...and verify the command was successful. */
517 + ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
519 + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
520 + ret_val = -E1000_ERR_PHY;
521 + e1000_release_phy_80003es2lan(hw);
527 + ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
531 + e1000_release_phy_80003es2lan(hw);
538 + * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
539 + * @hw: pointer to the HW structure
540 + * @offset: offset of the register to read
541 + * @data: value to write to the register
543 + * Write to the GG82563 PHY register.
545 +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
546 + u32 offset, u16 data)
552 + ret_val = e1000_acquire_phy_80003es2lan(hw);
556 + /* Select Configuration Page */
557 + if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
558 + page_select = GG82563_PHY_PAGE_SELECT;
561 + * Use Alternative Page Select register to access
562 + * registers 30 and 31
564 + page_select = GG82563_PHY_PAGE_SELECT_ALT;
567 + temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
568 + ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
570 + e1000_release_phy_80003es2lan(hw);
576 + * The "ready" bit in the MDIC register may be incorrectly set
577 + * before the device has completed the "Page Select" MDI
578 + * transaction. So we wait 200us after each MDI command...
582 + /* ...and verify the command was successful. */
583 + ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
585 + if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
586 + ret_val = -E1000_ERR_PHY;
587 + e1000_release_phy_80003es2lan(hw);
593 + ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
597 + e1000_release_phy_80003es2lan(hw);
604 + * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
605 + * @hw: pointer to the HW structure
606 + * @offset: offset of the register to read
607 + * @words: number of words to write
608 + * @data: buffer of data to write to the NVM
610 + * Write "words" of data to the ESB2 NVM.
612 +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
613 + u16 words, u16 *data)
615 + return e1000e_write_nvm_spi(hw, offset, words, data);
619 + * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
620 + * @hw: pointer to the HW structure
622 + * Wait a specific amount of time for manageability processes to complete.
623 + * This is a function pointer entry point called by the phy module.
625 +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
627 + s32 timeout = PHY_CFG_TIMEOUT;
628 + s32 ret_val = E1000_SUCCESS;
629 + u32 mask = E1000_NVM_CFG_DONE_PORT_0;
631 + if (hw->bus.func == 1)
632 + mask = E1000_NVM_CFG_DONE_PORT_1;
635 + if (er32(EEMNGCTL) & mask)
641 + e_dbg("MNG configuration cycle has not completed.\n");
642 + ret_val = -E1000_ERR_RESET;
651 + * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
652 + * @hw: pointer to the HW structure
654 + * Force the speed and duplex settings onto the PHY. This is a
655 + * function pointer entry point called by the phy module.
657 +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
659 + s32 ret_val = E1000_SUCCESS;
663 + if (!(hw->phy.ops.read_reg))
667 + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
668 + * forced whenever speed and duplex are forced.
670 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
674 + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
675 + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
679 + e_dbg("GG82563 PSCR: %X\n", phy_data);
681 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
685 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
687 + /* Reset the phy to commit changes. */
688 + phy_data |= MII_CR_RESET;
690 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
696 + if (hw->phy.autoneg_wait_to_complete) {
697 + e_dbg("Waiting for forced speed/duplex link "
698 + "on GG82563 phy.\n");
700 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
707 + * We didn't get link.
708 + * Reset the DSP and cross our fingers.
710 + ret_val = e1000e_phy_reset_dsp(hw);
715 + /* Try once more */
716 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
722 + ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
727 + * Resetting the phy means we need to verify the TX_CLK corresponds
728 + * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
730 + phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
731 + if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
732 + phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
734 + phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
737 + * In addition, we must re-enable CRS on Tx for both half and full
740 + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
741 + ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
748 + * e1000_get_cable_length_80003es2lan - Set approximate cable length
749 + * @hw: pointer to the HW structure
751 + * Find the approximate cable length as measured by the GG82563 PHY.
752 + * This is a function pointer entry point called by the phy module.
754 +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
756 + struct e1000_phy_info *phy = &hw->phy;
757 + s32 ret_val = E1000_SUCCESS;
758 + u16 phy_data, index;
760 + if (!(hw->phy.ops.read_reg))
763 + ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
767 + index = phy_data & GG82563_DSPD_CABLE_LENGTH;
769 + if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE + 5) {
770 + ret_val = E1000_ERR_PHY;
774 + phy->min_cable_length = e1000_gg82563_cable_length_table[index];
775 + phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
777 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
784 + * e1000_get_link_up_info_80003es2lan - Report speed and duplex
785 + * @hw: pointer to the HW structure
786 + * @speed: pointer to speed buffer
787 + * @duplex: pointer to duplex buffer
789 + * Retrieve the current speed and duplex configuration.
791 +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
796 + if (hw->phy.media_type == e1000_media_type_copper) {
797 + ret_val = e1000e_get_speed_and_duplex_copper(hw,
800 + hw->phy.ops.cfg_on_link_up(hw);
802 + ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
811 + * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
812 + * @hw: pointer to the HW structure
814 + * Perform a global reset to the ESB2 controller.
816 +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
822 + * Prevent the PCI-E bus from sticking if there is no TLP connection
823 + * on the last TLP read/write transaction when MAC is reset.
825 + ret_val = e1000e_disable_pcie_master(hw);
827 + e_dbg("PCI-E Master disable polling has failed.\n");
829 + e_dbg("Masking off all interrupts\n");
830 + ew32(IMC, 0xffffffff);
833 + ew32(TCTL, E1000_TCTL_PSP);
840 + ret_val = e1000_acquire_phy_80003es2lan(hw);
841 + e_dbg("Issuing a global reset to MAC\n");
842 + ew32(CTRL, ctrl | E1000_CTRL_RST);
843 + e1000_release_phy_80003es2lan(hw);
845 + ret_val = e1000e_get_auto_rd_done(hw);
847 + /* We don't want to continue accessing MAC registers. */
850 + /* Clear any pending interrupt events. */
851 + ew32(IMC, 0xffffffff);
854 + ret_val = e1000_check_alt_mac_addr_generic(hw);
861 + * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
862 + * @hw: pointer to the HW structure
864 + * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
866 +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
868 + struct e1000_mac_info *mac = &hw->mac;
873 + e1000_initialize_hw_bits_80003es2lan(hw);
875 + /* Initialize identification LED */
876 + ret_val = mac->ops.id_led_init(hw);
878 + e_dbg("Error initializing identification LED\n");
879 + /* This is not fatal and we should not stop init due to this */
882 + /* Disabling VLAN filtering */
883 + e_dbg("Initializing the IEEE VLAN\n");
884 + e1000e_clear_vfta(hw);
886 + /* Setup the receive address. */
887 + e1000e_init_rx_addrs(hw, mac->rar_entry_count);
889 + /* Zero out the Multicast HASH table */
890 + e_dbg("Zeroing the MTA\n");
891 + for (i = 0; i < mac->mta_reg_count; i++)
892 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
894 + /* Setup link and flow control */
895 + ret_val = mac->ops.setup_link(hw);
897 + /* Set the transmit descriptor write-back policy */
898 + reg_data = er32(TXDCTL(0));
899 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
900 + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
901 + ew32(TXDCTL(0), reg_data);
903 + /* ...for both queues. */
904 + reg_data = er32(TXDCTL(1));
905 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
906 + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
907 + ew32(TXDCTL(1), reg_data);
909 + /* Enable retransmit on late collisions */
910 + reg_data = er32(TCTL);
911 + reg_data |= E1000_TCTL_RTLC;
912 + ew32(TCTL, reg_data);
914 + /* Configure Gigabit Carry Extend Padding */
915 + reg_data = er32(TCTL_EXT);
916 + reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
917 + reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
918 + ew32(TCTL_EXT, reg_data);
920 + /* Configure Transmit Inter-Packet Gap */
921 + reg_data = er32(TIPG);
922 + reg_data &= ~E1000_TIPG_IPGT_MASK;
923 + reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
924 + ew32(TIPG, reg_data);
926 + reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
927 + reg_data &= ~0x00100000;
928 + E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
931 + * Clear all of the statistics registers (clear on read). It is
932 + * important that we do this after we have tried to establish link
933 + * because the symbol error count will increment wildly if there
936 + e1000_clear_hw_cntrs_80003es2lan(hw);
942 + * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
943 + * @hw: pointer to the HW structure
945 + * Initializes required hardware-dependent bits needed for normal operation.
947 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
951 + /* Transmit Descriptor Control 0 */
952 + reg = er32(TXDCTL(0));
954 + ew32(TXDCTL(0), reg);
956 + /* Transmit Descriptor Control 1 */
957 + reg = er32(TXDCTL(1));
959 + ew32(TXDCTL(1), reg);
961 + /* Transmit Arbitration Control 0 */
962 + reg = er32(TARC(0));
963 + reg &= ~(0xF << 27); /* 30:27 */
964 + if (hw->phy.media_type != e1000_media_type_copper)
966 + ew32(TARC(0), reg);
968 + /* Transmit Arbitration Control 1 */
969 + reg = er32(TARC(1));
970 + if (er32(TCTL) & E1000_TCTL_MULR)
974 + ew32(TARC(1), reg);
980 + * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
981 + * @hw: pointer to the HW structure
983 + * Setup some GG82563 PHY registers for obtaining link
985 +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
987 + struct e1000_phy_info *phy = &hw->phy;
992 + if (!phy->reset_disable) {
993 + ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
998 + data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
999 + /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1000 + data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1002 + ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
1009 + * MDI/MDI-X = 0 (default)
1010 + * 0 - Auto for all speeds
1013 + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1015 + ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
1019 + data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1021 + switch (phy->mdix) {
1023 + data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1026 + data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1030 + data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1036 + * disable_polarity_correction = 0 (default)
1037 + * Automatic Correction for Reversed Cable Polarity
1041 + data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1042 + if (phy->disable_polarity_correction)
1043 + data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1045 + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1049 + /* SW Reset the PHY so all changes take effect */
1050 + ret_val = e1000e_commit_phy(hw);
1052 + e_dbg("Error Resetting the PHY\n");
1058 + /* Bypass Rx and Tx FIFO's */
1059 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1060 + E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1061 + E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1062 + E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1066 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1067 + E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1071 + data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1072 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1073 + E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1078 + ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1082 + data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1083 + ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1087 + ctrl_ext = er32(CTRL_EXT);
1088 + ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1089 + ew32(CTRL_EXT, ctrl_ext);
1091 + ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1096 + * Do not init these registers when the HW is in IAMT mode, since the
1097 + * firmware will have already initialized them. We only initialize
1098 + * them if the HW is not in IAMT mode.
1100 + if (!(hw->mac.ops.check_mng_mode(hw))) {
1101 + /* Enable Electrical Idle on the PHY */
1102 + data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1103 + ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL,
1108 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1113 + data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1114 + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1121 + * Workaround: Disable padding in Kumeran interface in the MAC
1122 + * and in the PHY to avoid CRC errors.
1124 + ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1128 + data |= GG82563_ICR_DIS_PADDING;
1129 + ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1138 + * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1139 + * @hw: pointer to the HW structure
1141 + * Essentially a wrapper for setting up all things "copper" related.
1142 + * This is a function pointer entry point called by the mac module.
1144 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1150 + ctrl = er32(CTRL);
1151 + ctrl |= E1000_CTRL_SLU;
1152 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1156 + * Set the mac to wait the maximum time between each
1157 + * iteration and increase the max iterations when
1158 + * polling the phy; this fixes erroneous timeouts at 10Mbps.
1160 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1164 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1169 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1173 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1174 + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1178 + reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1179 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1180 + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1185 + ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1189 + ret_val = e1000e_setup_copper_link(hw);
1196 + * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1197 + * @hw: pointer to the HW structure
1198 + * @duplex: current duplex setting
1200 + * Configure the KMRN interface by applying last minute quirks for
1201 + * 10/100 operation.
1203 +static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1205 + s32 ret_val = E1000_SUCCESS;
1209 + if (hw->phy.media_type == e1000_media_type_copper) {
1210 + ret_val = e1000e_get_speed_and_duplex_copper(hw,
1216 + if (speed == SPEED_1000)
1217 + ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1219 + ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1227 + * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1228 + * @hw: pointer to the HW structure
1229 + * @duplex: current duplex setting
1231 + * Configure the KMRN interface by applying last minute quirks for
1232 + * 10/100 operation.
1234 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1236 + s32 ret_val = E1000_SUCCESS;
1239 + u16 reg_data, reg_data2;
1241 + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1242 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1243 + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1248 + /* Configure Transmit Inter-Packet Gap */
1249 + tipg = er32(TIPG);
1250 + tipg &= ~E1000_TIPG_IPGT_MASK;
1251 + tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1256 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1261 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1266 + } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1268 + if (duplex == HALF_DUPLEX)
1269 + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1271 + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1273 + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1280 + * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1281 + * @hw: pointer to the HW structure
1283 + * Configure the KMRN interface by applying last minute quirks for
1284 + * gigabit operation.
1286 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1288 + s32 ret_val = E1000_SUCCESS;
1289 + u16 reg_data, reg_data2;
1293 + reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1294 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1295 + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1300 + /* Configure Transmit Inter-Packet Gap */
1301 + tipg = er32(TIPG);
1302 + tipg &= ~E1000_TIPG_IPGT_MASK;
1303 + tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1308 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1313 + ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1318 + } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1320 + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1321 + ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1328 + * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1329 + * @hw: pointer to the HW structure
1330 + * @offset: register offset to be read
1331 + * @data: pointer to the read data
1333 + * Acquire semaphore, then read the PHY register at offset
1334 + * using the kumeran interface. The information retrieved is stored in data.
1335 + * Release the semaphore before exiting.
1337 +static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1341 + s32 ret_val = E1000_SUCCESS;
1343 + ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1347 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1348 + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1349 + ew32(KMRNCTRLSTA, kmrnctrlsta);
1353 + kmrnctrlsta = er32(KMRNCTRLSTA);
1354 + *data = (u16)kmrnctrlsta;
1356 + e1000_release_mac_csr_80003es2lan(hw);
1363 + * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1364 + * @hw: pointer to the HW structure
1365 + * @offset: register offset to write to
1366 + * @data: data to write at register offset
1368 + * Acquire semaphore, then write the data to PHY register
1369 + * at the offset using the kumeran interface. Release semaphore
1372 +static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1376 + s32 ret_val = E1000_SUCCESS;
1378 + ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1382 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1383 + E1000_KMRNCTRLSTA_OFFSET) | data;
1384 + ew32(KMRNCTRLSTA, kmrnctrlsta);
1388 + e1000_release_mac_csr_80003es2lan(hw);
1395 + * e1000_read_mac_addr_80003es2lan - Read device MAC address
1396 + * @hw: pointer to the HW structure
1398 +static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1400 + s32 ret_val = E1000_SUCCESS;
1403 + * If there's an alternate MAC address place it in RAR0
1404 + * so that it will override the Si installed default perm
1407 + ret_val = e1000_check_alt_mac_addr_generic(hw);
1411 + ret_val = e1000e_read_mac_addr_generic(hw);
1418 + * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1419 + * @hw: pointer to the HW structure
1421 + * In the case of a PHY power down to save power, or to turn off link during a
1422 + * driver unload, or wake on lan is not enabled, remove the link.
1424 +static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1426 + /* If the management interface is not enabled, then power down */
1427 + if (!(hw->mac.ops.check_mng_mode(hw) ||
1428 + e1000_check_reset_block(hw)))
1429 + e1000_power_down_phy_copper(hw);
1435 + * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1436 + * @hw: pointer to the HW structure
1438 + * Clears the hardware counters by reading the counter registers.
1440 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1442 + e1000e_clear_hw_cntrs_base(hw);
1479 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.h linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.h
1480 --- linux-2.6.22-0/drivers/net/e1000e/e1000_80003es2lan.h 1970-01-01 01:00:00.000000000 +0100
1481 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_80003es2lan.h 2009-06-24 00:32:20.000000000 +0200
1483 +/*******************************************************************************
1485 + Intel PRO/1000 Linux driver
1486 + Copyright(c) 1999 - 2009 Intel Corporation.
1488 + This program is free software; you can redistribute it and/or modify it
1489 + under the terms and conditions of the GNU General Public License,
1490 + version 2, as published by the Free Software Foundation.
1492 + This program is distributed in the hope it will be useful, but WITHOUT
1493 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1494 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1497 + You should have received a copy of the GNU General Public License along with
1498 + this program; if not, write to the Free Software Foundation, Inc.,
1499 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1501 + The full GNU General Public License is included in this distribution in
1502 + the file called "COPYING".
1504 + Contact Information:
1505 + Linux NICS <linux.nics@intel.com>
1506 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1507 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
1509 +*******************************************************************************/
1511 +#ifndef _E1000_80003ES2LAN_H_
1512 +#define _E1000_80003ES2LAN_H_
1514 +#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
1515 +#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
1516 +#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
1517 +#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
1519 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
1520 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
1521 +#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
1523 +#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
1524 +#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
1525 +#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
1527 +#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1528 +#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
1530 +#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
1531 +#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
1533 +/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
1534 +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */
1535 +#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
1536 +#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
1537 +#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
1538 +#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
1540 +/* PHY Specific Control Register 2 (Page 0, Register 26) */
1541 +#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
1542 + /* 1=Reverse Auto-Negotiation */
1544 +/* MAC Specific Control Register (Page 2, Register 21) */
1545 +/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
1546 +#define GG82563_MSCR_TX_CLK_MASK 0x0007
1547 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
1548 +#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
1549 +#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006
1550 +#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
1552 +#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
1554 +/* DSP Distance Register (Page 5, Register 26) */
1562 +#define GG82563_DSPD_CABLE_LENGTH 0x0007
1564 +/* Kumeran Mode Control Register (Page 193, Register 16) */
1565 +#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
1567 +/* Max number of times Kumeran read/write should be validated */
1568 +#define GG82563_MAX_KMRN_RETRY 0x5
1570 +/* Power Management Control Register (Page 193, Register 20) */
1571 +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
1572 + /* 1=Enable SERDES Electrical Idle */
1574 +/* In-Band Control Register (Page 194, Register 18) */
1575 +#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
1578 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_82571.c linux-2.6.22-10/drivers/net/e1000e/e1000_82571.c
1579 --- linux-2.6.22-0/drivers/net/e1000e/e1000_82571.c 1970-01-01 01:00:00.000000000 +0100
1580 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_82571.c 2009-06-24 00:32:20.000000000 +0200
1582 +/*******************************************************************************
1584 + Intel PRO/1000 Linux driver
1585 + Copyright(c) 1999 - 2009 Intel Corporation.
1587 + This program is free software; you can redistribute it and/or modify it
1588 + under the terms and conditions of the GNU General Public License,
1589 + version 2, as published by the Free Software Foundation.
1591 + This program is distributed in the hope it will be useful, but WITHOUT
1592 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1593 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1596 + You should have received a copy of the GNU General Public License along with
1597 + this program; if not, write to the Free Software Foundation, Inc.,
1598 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1600 + The full GNU General Public License is included in this distribution in
1601 + the file called "COPYING".
1603 + Contact Information:
1604 + Linux NICS <linux.nics@intel.com>
1605 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1606 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
1608 +*******************************************************************************/
1611 + * 82571EB Gigabit Ethernet Controller
1612 + * 82571EB Gigabit Ethernet Controller (Copper)
1613 + * 82571EB Gigabit Ethernet Controller (Fiber)
1614 + * 82571EB Dual Port Gigabit Mezzanine Adapter
1615 + * 82571EB Quad Port Gigabit Mezzanine Adapter
1616 + * 82571PT Gigabit PT Quad Port Server ExpressModule
1617 + * 82572EI Gigabit Ethernet Controller (Copper)
1618 + * 82572EI Gigabit Ethernet Controller (Fiber)
1619 + * 82572EI Gigabit Ethernet Controller
1620 + * 82573V Gigabit Ethernet Controller (Copper)
1621 + * 82573E Gigabit Ethernet Controller (Copper)
1622 + * 82573L Gigabit Ethernet Controller
1623 + * 82574L Gigabit Network Connection
1624 + * 82574L Gigabit Network Connection
1625 + * 82583V Gigabit Network Connection
1630 +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
1631 +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
1632 +static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
1633 +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
1634 +static void e1000_release_nvm_82571(struct e1000_hw *hw);
1635 +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
1636 + u16 words, u16 *data);
1637 +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
1638 +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
1639 +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
1640 +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
1642 +static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
1643 +static s32 e1000_init_hw_82571(struct e1000_hw *hw);
1644 +static void e1000_clear_vfta_82571(struct e1000_hw *hw);
1645 +static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
1646 +static s32 e1000_led_on_82574(struct e1000_hw *hw);
1647 +static s32 e1000_setup_link_82571(struct e1000_hw *hw);
1648 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
1649 +static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
1650 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
1651 +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
1652 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
1653 +static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
1654 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
1655 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
1656 +static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
1657 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
1658 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
1659 + u16 words, u16 *data);
1660 +static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
1661 +static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
1664 + * e1000_init_phy_params_82571 - Init PHY func ptrs.
1665 + * @hw: pointer to the HW structure
1667 +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
1669 + struct e1000_phy_info *phy = &hw->phy;
1670 + s32 ret_val = E1000_SUCCESS;
1672 + if (hw->phy.media_type != e1000_media_type_copper) {
1673 + phy->type = e1000_phy_none;
1678 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1679 + phy->reset_delay_us = 100;
1681 + phy->ops.acquire = e1000_get_hw_semaphore_82571;
1682 + phy->ops.check_polarity = e1000_check_polarity_igp;
1683 + phy->ops.check_reset_block = e1000e_check_reset_block_generic;
1684 + phy->ops.release = e1000_put_hw_semaphore_82571;
1685 + phy->ops.reset = e1000e_phy_hw_reset_generic;
1686 + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
1687 + phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state;
1688 + phy->ops.power_up = e1000_power_up_phy_copper;
1689 + phy->ops.power_down = e1000_power_down_phy_copper_82571;
1691 + switch (hw->mac.type) {
1694 + phy->type = e1000_phy_igp_2;
1695 + phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
1696 + phy->ops.get_info = e1000e_get_phy_info_igp;
1697 + phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
1698 + phy->ops.get_cable_length = e1000e_get_cable_length_igp_2;
1699 + phy->ops.read_reg = e1000e_read_phy_reg_igp;
1700 + phy->ops.write_reg = e1000e_write_phy_reg_igp;
1702 + /* This uses above function pointers */
1703 + ret_val = e1000_get_phy_id_82571(hw);
1705 + /* Verify PHY ID */
1706 + if (phy->id != IGP01E1000_I_PHY_ID) {
1707 + ret_val = -E1000_ERR_PHY;
1712 + phy->type = e1000_phy_m88;
1713 + phy->ops.get_cfg_done = e1000e_get_cfg_done;
1714 + phy->ops.get_info = e1000e_get_phy_info_m88;
1715 + phy->ops.commit = e1000e_phy_sw_reset;
1716 + phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
1717 + phy->ops.get_cable_length = e1000e_get_cable_length_m88;
1718 + phy->ops.read_reg = e1000e_read_phy_reg_m88;
1719 + phy->ops.write_reg = e1000e_write_phy_reg_m88;
1721 + /* This uses above function pointers */
1722 + ret_val = e1000_get_phy_id_82571(hw);
1724 + /* Verify PHY ID */
1725 + if (phy->id != M88E1111_I_PHY_ID) {
1726 + ret_val = -E1000_ERR_PHY;
1727 + e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
1733 + phy->type = e1000_phy_bm;
1734 + phy->ops.get_cfg_done = e1000e_get_cfg_done;
1735 + phy->ops.get_info = e1000e_get_phy_info_m88;
1736 + phy->ops.commit = e1000e_phy_sw_reset;
1737 + phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
1738 + phy->ops.get_cable_length = e1000e_get_cable_length_m88;
1739 + phy->ops.read_reg = e1000e_read_phy_reg_bm2;
1740 + phy->ops.write_reg = e1000e_write_phy_reg_bm2;
1742 + /* This uses above function pointers */
1743 + ret_val = e1000_get_phy_id_82571(hw);
1744 + /* Verify PHY ID */
1745 + if (phy->id != BME1000_E_PHY_ID_R2) {
1746 + ret_val = -E1000_ERR_PHY;
1747 + e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
1752 + ret_val = -E1000_ERR_PHY;
1762 + * e1000_init_nvm_params_82571 - Init NVM func ptrs.
1763 + * @hw: pointer to the HW structure
1765 +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
1767 + struct e1000_nvm_info *nvm = &hw->nvm;
1768 + u32 eecd = er32(EECD);
1771 + nvm->opcode_bits = 8;
1772 + nvm->delay_usec = 1;
1773 + switch (nvm->override) {
1774 + case e1000_nvm_override_spi_large:
1775 + nvm->page_size = 32;
1776 + nvm->address_bits = 16;
1778 + case e1000_nvm_override_spi_small:
1779 + nvm->page_size = 8;
1780 + nvm->address_bits = 8;
1783 + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
1784 + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
1788 + switch (hw->mac.type) {
1792 + if (((eecd >> 15) & 0x3) == 0x3) {
1793 + nvm->type = e1000_nvm_flash_hw;
1794 + nvm->word_size = 2048;
1796 + * Autonomous Flash update bit must be cleared due
1797 + * to Flash update issue.
1799 + eecd &= ~E1000_EECD_AUPDEN;
1803 + /* Fall Through */
1805 + nvm->type = e1000_nvm_eeprom_spi;
1806 + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
1807 + E1000_EECD_SIZE_EX_SHIFT);
1809 + * Added to a constant, "size" becomes the left-shift value
1810 + * for setting word_size.
1812 + size += NVM_WORD_SIZE_BASE_SHIFT;
1814 + /* EEPROM access above 16k is unsupported */
1817 + nvm->word_size = 1 << size;
1821 + /* Function Pointers */
1822 + nvm->ops.acquire = e1000_acquire_nvm_82571;
1823 + nvm->ops.read = e1000e_read_nvm_eerd;
1824 + nvm->ops.release = e1000_release_nvm_82571;
1825 + nvm->ops.update = e1000_update_nvm_checksum_82571;
1826 + nvm->ops.validate = e1000_validate_nvm_checksum_82571;
1827 + nvm->ops.valid_led_default = e1000_valid_led_default_82571;
1828 + nvm->ops.write = e1000_write_nvm_82571;
1830 + return E1000_SUCCESS;
1834 + * e1000_init_mac_params_82571 - Init MAC func ptrs.
1835 + * @hw: pointer to the HW structure
1837 +static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
1839 + struct e1000_mac_info *mac = &hw->mac;
1840 + s32 ret_val = E1000_SUCCESS;
1843 + bool force_clear_smbi = false;
1845 + /* Set media type */
1846 + switch (hw->device_id) {
1847 + case E1000_DEV_ID_82571EB_FIBER:
1848 + case E1000_DEV_ID_82572EI_FIBER:
1849 + case E1000_DEV_ID_82571EB_QUAD_FIBER:
1850 + hw->phy.media_type = e1000_media_type_fiber;
1852 + case E1000_DEV_ID_82571EB_SERDES:
1853 + case E1000_DEV_ID_82571EB_SERDES_DUAL:
1854 + case E1000_DEV_ID_82571EB_SERDES_QUAD:
1855 + case E1000_DEV_ID_82572EI_SERDES:
1856 + hw->phy.media_type = e1000_media_type_internal_serdes;
1859 + hw->phy.media_type = e1000_media_type_copper;
1863 + /* Set mta register count */
1864 + mac->mta_reg_count = 128;
1865 + /* Set rar entry count */
1866 + mac->rar_entry_count = E1000_RAR_ENTRIES;
1867 + /* Set if part includes ASF firmware */
1868 + mac->asf_firmware_present = true;
1869 + /* Set if manageability features are enabled. */
1870 + mac->arc_subsystem_valid =
1871 + (er32(FWSM) & E1000_FWSM_MODE_MASK)
1874 + /* Function pointers */
1876 + /* bus type/speed/width */
1877 + mac->ops.get_bus_info = e1000e_get_bus_info_pcie;
1879 + switch (hw->mac.type) {
1883 + mac->ops.set_lan_id = e1000_set_lan_id_single_port;
1889 + mac->ops.reset_hw = e1000_reset_hw_82571;
1890 + /* hw initialization */
1891 + mac->ops.init_hw = e1000_init_hw_82571;
1893 + mac->ops.setup_link = e1000_setup_link_82571;
1894 + /* physical interface link setup */
1895 + mac->ops.setup_physical_interface =
1896 + (hw->phy.media_type == e1000_media_type_copper)
1897 + ? e1000_setup_copper_link_82571
1898 + : e1000_setup_fiber_serdes_link_82571;
1899 + /* check for link */
1900 + switch (hw->phy.media_type) {
1901 + case e1000_media_type_copper:
1902 + mac->ops.check_for_link = e1000e_check_for_copper_link;
1904 + case e1000_media_type_fiber:
1905 + mac->ops.check_for_link = e1000e_check_for_fiber_link;
1907 + case e1000_media_type_internal_serdes:
1908 + mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
1911 + ret_val = -E1000_ERR_CONFIG;
1915 + /* check management mode */
1916 + switch (hw->mac.type) {
1919 + mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
1922 + mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
1925 + /* multicast address update */
1926 + mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
1927 + /* writing VFTA */
1928 + mac->ops.write_vfta = e1000e_write_vfta_generic;
1929 + /* clearing VFTA */
1930 + mac->ops.clear_vfta = e1000_clear_vfta_82571;
1932 + mac->ops.mta_set = e1000_mta_set_generic;
1933 + /* read mac address */
1934 + mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
1936 + mac->ops.id_led_init = e1000e_id_led_init;
1938 + mac->ops.blink_led = e1000e_blink_led;
1940 + mac->ops.setup_led = e1000_setup_led_generic;
1942 + mac->ops.cleanup_led = e1000e_cleanup_led_generic;
1943 + /* turn on/off LED */
1944 + switch (hw->mac.type) {
1947 + mac->ops.led_on = e1000_led_on_82574;
1950 + mac->ops.led_on = e1000e_led_on_generic;
1953 + mac->ops.led_off = e1000e_led_off_generic;
1954 + /* clear hardware counters */
1955 + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
1957 + mac->ops.get_link_up_info =
1958 + (hw->phy.media_type == e1000_media_type_copper)
1959 + ? e1000e_get_speed_and_duplex_copper
1960 + : e1000e_get_speed_and_duplex_fiber_serdes;
1963 + * Ensure that the inter-port SWSM.SMBI lock bit is clear before
1964 + * first NVM or PHY acess. This should be done for single-port
1965 + * devices, and for one port only on dual-port devices so that
1966 + * for those devices we can still use the SMBI lock to synchronize
1967 + * inter-port accesses to the PHY & NVM.
1969 + switch (hw->mac.type) {
1972 + swsm2 = er32(SWSM2);
1974 + if (!(swsm2 & E1000_SWSM2_LOCK)) {
1975 + /* Only do this for the first interface on this card */
1977 + swsm2 | E1000_SWSM2_LOCK);
1978 + force_clear_smbi = true;
1980 + force_clear_smbi = false;
1983 + force_clear_smbi = true;
1987 + if (force_clear_smbi) {
1988 + /* Make sure SWSM.SMBI is clear */
1989 + swsm = er32(SWSM);
1990 + if (swsm & E1000_SWSM_SMBI) {
1991 + /* This bit should not be set on a first interface, and
1992 + * indicates that the bootagent or EFI code has
1993 + * improperly left this bit enabled
1995 + e_dbg("Please update your 82571 Bootagent\n");
1997 + ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
2001 + * Initialze device specific counter of SMBI acquisition
2004 + hw->dev_spec._82571.smb_counter = 0;
2011 + * e1000_init_function_pointers_82571 - Init func ptrs.
2012 + * @hw: pointer to the HW structure
2014 + * Called to initialize all function pointers and parameters.
2016 +void e1000_init_function_pointers_82571(struct e1000_hw *hw)
2018 + e1000_init_mac_ops_generic(hw);
2019 + e1000_init_nvm_ops_generic(hw);
2020 + hw->mac.ops.init_params = e1000_init_mac_params_82571;
2021 + hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
2022 + hw->phy.ops.init_params = e1000_init_phy_params_82571;
2026 + * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
2027 + * @hw: pointer to the HW structure
2029 + * Reads the PHY registers and stores the PHY ID and possibly the PHY
2030 + * revision in the hardware structure.
2032 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
2034 + struct e1000_phy_info *phy = &hw->phy;
2035 + s32 ret_val = E1000_SUCCESS;
2038 + switch (hw->mac.type) {
2042 + * The 82571 firmware may still be configuring the PHY.
2043 + * In this case, we cannot access the PHY until the
2044 + * configuration is done. So we explicitly set the
2047 + phy->id = IGP01E1000_I_PHY_ID;
2050 + ret_val = e1000e_get_phy_id(hw);
2054 + ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
2058 + phy->id = (u32)(phy_id << 16);
2060 + ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
2064 + phy->id |= (u32)(phy_id);
2065 + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
2068 + ret_val = -E1000_ERR_PHY;
2077 + * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
2078 + * @hw: pointer to the HW structure
2080 + * Acquire the HW semaphore to access the PHY or NVM
2082 +s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
2085 + s32 ret_val = E1000_SUCCESS;
2086 + s32 sw_timeout = hw->nvm.word_size + 1;
2087 + s32 fw_timeout = hw->nvm.word_size + 1;
2091 + * If we have timedout 3 times on trying to acquire
2092 + * the inter-port SMBI semaphore, there is old code
2093 + * operating on the other port, and it is not
2094 + * releasing SMBI. Modify the number of times that
2095 + * we try for the semaphore to interwork with this
2098 + if (hw->dev_spec._82571.smb_counter > 2)
2101 + /* Get the SW semaphore */
2102 + while (i < sw_timeout) {
2103 + swsm = er32(SWSM);
2104 + if (!(swsm & E1000_SWSM_SMBI))
2111 + if (i == sw_timeout) {
2112 + e_dbg("Driver can't access device - SMBI bit is set.\n");
2113 + hw->dev_spec._82571.smb_counter++;
2115 + /* Get the FW semaphore. */
2116 + for (i = 0; i < fw_timeout; i++) {
2117 + swsm = er32(SWSM);
2118 + ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
2120 + /* Semaphore acquired if bit latched */
2121 + if (er32(SWSM) & E1000_SWSM_SWESMBI)
2127 + if (i == fw_timeout) {
2128 + /* Release semaphores */
2129 + e1000_put_hw_semaphore_82571(hw);
2130 + e_dbg("Driver can't access the NVM\n");
2131 + ret_val = -E1000_ERR_NVM;
2140 + * e1000_put_hw_semaphore_82571 - Release hardware semaphore
2141 + * @hw: pointer to the HW structure
2143 + * Release hardware semaphore used to access the PHY or NVM
2145 +void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
2149 + swsm = er32(SWSM);
2150 + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
2154 + * e1000_acquire_nvm_82571 - Request for access to the EEPROM
2155 + * @hw: pointer to the HW structure
2157 + * To gain access to the EEPROM, first we must obtain a hardware semaphore.
2158 + * Then for non-82573 hardware, set the EEPROM access request bit and wait
2159 + * for EEPROM access grant bit. If the access grant bit is not set, release
2160 + * hardware semaphore.
2162 +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
2166 + ret_val = e1000_get_hw_semaphore_82571(hw);
2170 + switch (hw->mac.type) {
2176 + ret_val = e1000e_acquire_nvm(hw);
2181 + e1000_put_hw_semaphore_82571(hw);
2188 + * e1000_release_nvm_82571 - Release exclusive access to EEPROM
2189 + * @hw: pointer to the HW structure
2191 + * Stop any current commands to the EEPROM and clear the EEPROM request bit.
2193 +static void e1000_release_nvm_82571(struct e1000_hw *hw)
2195 + e1000e_release_nvm(hw);
2196 + e1000_put_hw_semaphore_82571(hw);
2200 + * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
2201 + * @hw: pointer to the HW structure
2202 + * @offset: offset within the EEPROM to be written to
2203 + * @words: number of words to write
2204 + * @data: 16 bit word(s) to be written to the EEPROM
2206 + * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
2208 + * If e1000_update_nvm_checksum is not called after this function, the
2209 + * EEPROM will most likely contain an invalid checksum.
2211 +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
2214 + s32 ret_val = E1000_SUCCESS;
2216 + switch (hw->mac.type) {
2220 + ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
2224 + ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
2227 + ret_val = -E1000_ERR_NVM;
2235 + * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
2236 + * @hw: pointer to the HW structure
2238 + * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2239 + * up to the checksum. Then calculates the EEPROM checksum and writes the
2240 + * value to the EEPROM.
2242 +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
2248 + ret_val = e1000e_update_nvm_checksum_generic(hw);
2253 + * If our nvm is an EEPROM, then we're done
2254 + * otherwise, commit the checksum to the flash NVM.
2256 + if (hw->nvm.type != e1000_nvm_flash_hw)
2259 + /* Check for pending operations. */
2260 + for (i = 0; i < E1000_FLASH_UPDATES; i++) {
2262 + if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
2266 + if (i == E1000_FLASH_UPDATES) {
2267 + ret_val = -E1000_ERR_NVM;
2271 + /* Reset the firmware if using STM opcode. */
2272 + if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
2274 + * The enabling of and the actual reset must be done
2275 + * in two write cycles.
2277 + ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
2279 + ew32(HICR, E1000_HICR_FW_RESET);
2282 + /* Commit the write to flash */
2283 + eecd = er32(EECD) | E1000_EECD_FLUPD;
2286 + for (i = 0; i < E1000_FLASH_UPDATES; i++) {
2288 + if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
2292 + if (i == E1000_FLASH_UPDATES) {
2293 + ret_val = -E1000_ERR_NVM;
2302 + * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
2303 + * @hw: pointer to the HW structure
2305 + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2306 + * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2308 +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
2310 + if (hw->nvm.type == e1000_nvm_flash_hw)
2311 + e1000_fix_nvm_checksum_82571(hw);
2313 + return e1000e_validate_nvm_checksum_generic(hw);
2317 + * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
2318 + * @hw: pointer to the HW structure
2319 + * @offset: offset within the EEPROM to be written to
2320 + * @words: number of words to write
2321 + * @data: 16 bit word(s) to be written to the EEPROM
2323 + * After checking for invalid values, poll the EEPROM to ensure the previous
2324 + * command has completed before trying to write the next word. After write
2325 + * poll for completion.
2327 + * If e1000_update_nvm_checksum is not called after this function, the
2328 + * EEPROM will most likely contain an invalid checksum.
2330 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
2331 + u16 words, u16 *data)
2333 + struct e1000_nvm_info *nvm = &hw->nvm;
2338 + * A check for invalid values: offset too large, too many words,
2339 + * and not enough words.
2341 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2343 + e_dbg("nvm parameter(s) out of bounds\n");
2344 + ret_val = -E1000_ERR_NVM;
2348 + for (i = 0; i < words; i++) {
2349 + eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
2350 + ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
2351 + E1000_NVM_RW_REG_START;
2353 + ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
2359 + ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
2369 + * e1000_get_cfg_done_82571 - Poll for configuration done
2370 + * @hw: pointer to the HW structure
2372 + * Reads the management control register for the config done bit to be set.
2374 +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
2376 + s32 timeout = PHY_CFG_TIMEOUT;
2377 + s32 ret_val = E1000_SUCCESS;
2380 + if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
2386 + e_dbg("MNG configuration cycle has not completed.\n");
2387 + ret_val = -E1000_ERR_RESET;
2396 + * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
2397 + * @hw: pointer to the HW structure
2398 + * @active: true to enable LPLU, false to disable
2400 + * Sets the LPLU D0 state according to the active flag. When activating LPLU
2401 + * this function also disables smart speed and vice versa. LPLU will not be
2402 + * activated unless the device autonegotiation advertisement meets standards
2403 + * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
2404 + * pointer entry point only called by PHY setup routines.
2406 +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
2408 + struct e1000_phy_info *phy = &hw->phy;
2409 + s32 ret_val = E1000_SUCCESS;
2412 + if (!(phy->ops.read_reg))
2415 + ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2420 + data |= IGP02E1000_PM_D0_LPLU;
2421 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
2426 + /* When LPLU is enabled, we should disable SmartSpeed */
2427 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2429 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2430 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2435 + data &= ~IGP02E1000_PM_D0_LPLU;
2436 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
2439 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2440 + * during Dx states where the power conservation is most
2441 + * important. During driver activity we should enable
2442 + * SmartSpeed, so performance is maintained.
2444 + if (phy->smart_speed == e1000_smart_speed_on) {
2445 + ret_val = e1e_rphy(hw,
2446 + IGP01E1000_PHY_PORT_CONFIG,
2451 + data |= IGP01E1000_PSCFR_SMART_SPEED;
2452 + ret_val = e1e_wphy(hw,
2453 + IGP01E1000_PHY_PORT_CONFIG,
2457 + } else if (phy->smart_speed == e1000_smart_speed_off) {
2458 + ret_val = e1e_rphy(hw,
2459 + IGP01E1000_PHY_PORT_CONFIG,
2464 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2465 + ret_val = e1e_wphy(hw,
2466 + IGP01E1000_PHY_PORT_CONFIG,
2478 + * e1000_reset_hw_82571 - Reset hardware
2479 + * @hw: pointer to the HW structure
2481 + * This resets the hardware into a known state.
2483 +static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
2485 + u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
2490 + * Prevent the PCI-E bus from sticking if there is no TLP connection
2491 + * on the last TLP read/write transaction when MAC is reset.
2493 + ret_val = e1000e_disable_pcie_master(hw);
2495 + e_dbg("PCI-E Master disable polling has failed.\n");
2497 + e_dbg("Masking off all interrupts\n");
2498 + ew32(IMC, 0xffffffff);
2501 + ew32(TCTL, E1000_TCTL_PSP);
2507 + * Must acquire the MDIO ownership before MAC reset.
2508 + * Ownership defaults to firmware after a reset.
2510 + switch (hw->mac.type) {
2514 + extcnf_ctrl = er32(EXTCNF_CTRL);
2515 + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
2518 + ew32(EXTCNF_CTRL, extcnf_ctrl);
2519 + extcnf_ctrl = er32(EXTCNF_CTRL);
2521 + if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2524 + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
2528 + } while (i < MDIO_OWNERSHIP_TIMEOUT);
2534 + ctrl = er32(CTRL);
2536 + e_dbg("Issuing a global reset to MAC\n");
2537 + ew32(CTRL, ctrl | E1000_CTRL_RST);
2539 + if (hw->nvm.type == e1000_nvm_flash_hw) {
2541 + ctrl_ext = er32(CTRL_EXT);
2542 + ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2543 + ew32(CTRL_EXT, ctrl_ext);
2547 + ret_val = e1000e_get_auto_rd_done(hw);
2549 + /* We don't want to continue accessing MAC registers. */
2553 + * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
2554 + * Need to wait for Phy configuration completion before accessing
2558 + switch (hw->mac.type) {
2568 + /* Clear any pending interrupt events. */
2569 + ew32(IMC, 0xffffffff);
2572 + /* Install any alternate MAC address into RAR0 */
2573 + ret_val = e1000_check_alt_mac_addr_generic(hw);
2577 + e1000e_set_laa_state_82571(hw, true);
2579 + /* Reinitialize the 82571 serdes link state machine */
2580 + if (hw->phy.media_type == e1000_media_type_internal_serdes)
2581 + hw->mac.serdes_link_state = e1000_serdes_link_down;
2588 + * e1000_init_hw_82571 - Initialize hardware
2589 + * @hw: pointer to the HW structure
2591 + * This inits the hardware readying it for operation.
2593 +static s32 e1000_init_hw_82571(struct e1000_hw *hw)
2595 + struct e1000_mac_info *mac = &hw->mac;
2598 + u16 i, rar_count = mac->rar_entry_count;
2600 + e1000_initialize_hw_bits_82571(hw);
2602 + /* Initialize identification LED */
2603 + ret_val = mac->ops.id_led_init(hw);
2605 + e_dbg("Error initializing identification LED\n");
2606 + /* This is not fatal and we should not stop init due to this */
2609 + /* Disabling VLAN filtering */
2610 + e_dbg("Initializing the IEEE VLAN\n");
2611 + e1000e_clear_vfta(hw);
2613 + /* Setup the receive address. */
2615 + * If, however, a locally administered address was assigned to the
2616 + * 82571, we must reserve a RAR for it to work around an issue where
2617 + * resetting one port will reload the MAC on the other port.
2619 + if (e1000e_get_laa_state_82571(hw))
2621 + e1000e_init_rx_addrs(hw, rar_count);
2623 + /* Zero out the Multicast HASH table */
2624 + e_dbg("Zeroing the MTA\n");
2625 + for (i = 0; i < mac->mta_reg_count; i++)
2626 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2628 + /* Setup link and flow control */
2629 + ret_val = mac->ops.setup_link(hw);
2631 + /* Set the transmit descriptor write-back policy */
2632 + reg_data = er32(TXDCTL(0));
2633 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
2634 + E1000_TXDCTL_FULL_TX_DESC_WB |
2635 + E1000_TXDCTL_COUNT_DESC;
2636 + ew32(TXDCTL(0), reg_data);
2638 + /* ...for both queues. */
2639 + switch (mac->type) {
2643 + e1000e_enable_tx_pkt_filtering(hw);
2644 + reg_data = er32(GCR);
2645 + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2646 + ew32(GCR, reg_data);
2649 + reg_data = er32(TXDCTL(1));
2650 + reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
2651 + E1000_TXDCTL_FULL_TX_DESC_WB |
2652 + E1000_TXDCTL_COUNT_DESC;
2653 + ew32(TXDCTL(1), reg_data);
2658 + * Clear all of the statistics registers (clear on read). It is
2659 + * important that we do this after we have tried to establish link
2660 + * because the symbol error count will increment wildly if there
2663 + e1000_clear_hw_cntrs_82571(hw);
2669 + * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
2670 + * @hw: pointer to the HW structure
2672 + * Initializes required hardware-dependent bits needed for normal operation.
2674 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
2678 + /* Transmit Descriptor Control 0 */
2679 + reg = er32(TXDCTL(0));
2681 + ew32(TXDCTL(0), reg);
2683 + /* Transmit Descriptor Control 1 */
2684 + reg = er32(TXDCTL(1));
2686 + ew32(TXDCTL(1), reg);
2688 + /* Transmit Arbitration Control 0 */
2689 + reg = er32(TARC(0));
2690 + reg &= ~(0xF << 27); /* 30:27 */
2691 + switch (hw->mac.type) {
2694 + reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
2699 + ew32(TARC(0), reg);
2701 + /* Transmit Arbitration Control 1 */
2702 + reg = er32(TARC(1));
2703 + switch (hw->mac.type) {
2706 + reg &= ~((1 << 29) | (1 << 30));
2707 + reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
2708 + if (er32(TCTL) & E1000_TCTL_MULR)
2709 + reg &= ~(1 << 28);
2712 + ew32(TARC(1), reg);
2718 + /* Device Control */
2720 + switch (hw->mac.type) {
2725 + reg &= ~(1 << 29);
2732 + /* Extended Device Control */
2733 + switch (hw->mac.type) {
2737 + reg = er32(CTRL_EXT);
2738 + reg &= ~(1 << 23);
2740 + ew32(CTRL_EXT, reg);
2747 + if (hw->mac.type == e1000_82571) {
2748 + reg = er32(PBA_ECC);
2749 + reg |= E1000_PBA_ECC_CORR_EN;
2750 + ew32(PBA_ECC, reg);
2754 + * Workaround for hardware errata.
2755 + * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
2758 + if ((hw->mac.type == e1000_82571) ||
2759 + (hw->mac.type == e1000_82572)) {
2760 + reg = er32(CTRL_EXT);
2761 + reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
2762 + ew32(CTRL_EXT, reg);
2765 + /* PCI-Ex Control Registers */
2767 + switch (hw->mac.type) {
2774 + * Workaround for hardware errata.
2775 + * apply workaround for hardware errata documented in errata
2776 + * docs Fixes issue where some error prone or unreliable PCIe
2777 + * completions are occurring, particularly with ASPM enabled.
2778 + * Without fix, issue can cause tx timeouts.
2792 + * e1000_clear_vfta_82571 - Clear VLAN filter table
2793 + * @hw: pointer to the HW structure
2795 + * Clears the register array which contains the VLAN filter table by
2796 + * setting all the values to 0.
2798 +static void e1000_clear_vfta_82571(struct e1000_hw *hw)
2801 + u32 vfta_value = 0;
2802 + u32 vfta_offset = 0;
2803 + u32 vfta_bit_in_reg = 0;
2805 + switch (hw->mac.type) {
2809 + if (hw->mng_cookie.vlan_id != 0) {
2811 + *The VFTA is a 4096b bit-field, each identifying
2812 + *a single VLAN ID. The following operations
2813 + *determine which 32b entry (i.e. offset) into the
2814 + *array we want to set the VLAN ID (i.e. bit) of
2815 + *the manageability unit.
2817 + vfta_offset = (hw->mng_cookie.vlan_id >>
2818 + E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
2819 + vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
2820 + E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
2823 + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2825 + *If the offset we want to clear is the same offset of
2826 + *the manageability VLAN ID, then clear all bits except
2827 + *that of the manageability unit
2829 + vfta_value = (offset == vfta_offset) ?
2830 + vfta_bit_in_reg : 0;
2831 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset,
2842 + * e1000_check_mng_mode_82574 - Check manageability is enabled
2843 + * @hw: pointer to the HW structure
2845 + * Reads the NVM Initialization Control Word 2 and returns true
2846 + * (>0) if any manageability is enabled, else false (0).
2848 +static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
2852 + e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2853 + return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
2857 + * e1000_led_on_82574 - Turn LED on
2858 + * @hw: pointer to the HW structure
2862 +static s32 e1000_led_on_82574(struct e1000_hw *hw)
2867 + ctrl = hw->mac.ledctl_mode2;
2868 + if (!(E1000_STATUS_LU & er32(STATUS))) {
2870 + * If no link, then turn LED on by setting the invert bit
2871 + * for each LED that's "on" (0x0E) in ledctl_mode2.
2873 + for (i = 0; i < 4; i++)
2874 + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
2875 + E1000_LEDCTL_MODE_LED_ON)
2876 + ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
2878 + ew32(LEDCTL, ctrl);
2880 + return E1000_SUCCESS;
2885 + * e1000_setup_link_82571 - Setup flow control and link settings
2886 + * @hw: pointer to the HW structure
2888 + * Determines which flow control settings to use, then configures flow
2889 + * control. Calls the appropriate media-specific link configuration
2890 + * function. Assuming the adapter has a valid link partner, a valid link
2891 + * should be established. Assumes the hardware has previously been reset
2892 + * and the transmitter and receiver are not enabled.
2894 +static s32 e1000_setup_link_82571(struct e1000_hw *hw)
2897 + * 82573 does not have a word in the NVM to determine
2898 + * the default flow control setting, so we explicitly
2901 + switch (hw->mac.type) {
2905 + if (hw->fc.requested_mode == e1000_fc_default)
2906 + hw->fc.requested_mode = e1000_fc_full;
2911 + return e1000e_setup_link(hw);
2915 + * e1000_setup_copper_link_82571 - Configure copper link settings
2916 + * @hw: pointer to the HW structure
2918 + * Configures the link for auto-neg or forced speed and duplex. Then we check
2919 + * for link, once link is established calls to configure collision distance
2920 + * and flow control are called.
2922 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
2927 + ctrl = er32(CTRL);
2928 + ctrl |= E1000_CTRL_SLU;
2929 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2932 + switch (hw->phy.type) {
2933 + case e1000_phy_m88:
2934 + case e1000_phy_bm:
2935 + ret_val = e1000e_copper_link_setup_m88(hw);
2937 + case e1000_phy_igp_2:
2938 + ret_val = e1000e_copper_link_setup_igp(hw);
2941 + ret_val = -E1000_ERR_PHY;
2948 + ret_val = e1000e_setup_copper_link(hw);
2955 + * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
2956 + * @hw: pointer to the HW structure
2958 + * Configures collision distance and flow control for fiber and serdes links.
2959 + * Upon successful setup, poll for link.
2961 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
2963 + switch (hw->mac.type) {
2967 + * If SerDes loopback mode is entered, there is no form
2968 + * of reset to take the adapter out of that mode. So we
2969 + * have to explicitly take the adapter out of loopback
2970 + * mode. This prevents drivers from twiddling their thumbs
2971 + * if another tool failed to take it out of loopback mode.
2973 + ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
2979 + return e1000e_setup_fiber_serdes_link(hw);
2983 + * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
2984 + * @hw: pointer to the HW structure
2986 + * Reports the link state as up or down.
2988 + * If autonegotiation is supported by the link partner, the link state is
2989 + * determined by the result of autongotiation. This is the most likely case.
2990 + * If autonegotiation is not supported by the link partner, and the link
2991 + * has a valid signal, force the link up.
2993 + * The link state is represented internally here by 4 states:
2996 + * 2) autoneg_progress
2997 + * 3) autoneg_complete (the link sucessfully autonegotiated)
2998 + * 4) forced_up (the link has been forced up, it did not autonegotiate)
3001 +s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
3003 + struct e1000_mac_info *mac = &hw->mac;
3007 + s32 ret_val = E1000_SUCCESS;
3009 + ctrl = er32(CTRL);
3010 + status = er32(STATUS);
3011 + rxcw = er32(RXCW);
3013 + if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
3015 + /* Receiver is synchronized with no invalid bits. */
3016 + switch (mac->serdes_link_state) {
3017 + case e1000_serdes_link_autoneg_complete:
3018 + if (!(status & E1000_STATUS_LU)) {
3020 + * We have lost link, retry autoneg before
3021 + * reporting link failure
3023 + mac->serdes_link_state =
3024 + e1000_serdes_link_autoneg_progress;
3025 + mac->serdes_has_link = false;
3026 + e_dbg("AN_UP -> AN_PROG\n");
3030 + case e1000_serdes_link_forced_up:
3032 + * If we are receiving /C/ ordered sets, re-enable
3033 + * auto-negotiation in the TXCW register and disable
3034 + * forced link in the Device Control register in an
3035 + * attempt to auto-negotiate with our link partner.
3037 + if (rxcw & E1000_RXCW_C) {
3038 + /* Enable autoneg, and unforce link up */
3039 + ew32(TXCW, mac->txcw);
3041 + (ctrl & ~E1000_CTRL_SLU));
3042 + mac->serdes_link_state =
3043 + e1000_serdes_link_autoneg_progress;
3044 + mac->serdes_has_link = false;
3045 + e_dbg("FORCED_UP -> AN_PROG\n");
3049 + case e1000_serdes_link_autoneg_progress:
3050 + if (rxcw & E1000_RXCW_C) {
3051 + /* We received /C/ ordered sets, meaning the
3052 + * link partner has autonegotiated, and we can
3053 + * trust the Link Up (LU) status bit
3055 + if (status & E1000_STATUS_LU) {
3056 + mac->serdes_link_state =
3057 + e1000_serdes_link_autoneg_complete;
3058 + e_dbg("AN_PROG -> AN_UP\n");
3059 + mac->serdes_has_link = true;
3061 + /* Autoneg completed, but failed */
3062 + mac->serdes_link_state =
3063 + e1000_serdes_link_down;
3064 + e_dbg("AN_PROG -> DOWN\n");
3067 + /* The link partner did not autoneg.
3068 + * Force link up and full duplex, and change
3069 + * state to forced.
3072 + (mac->txcw & ~E1000_TXCW_ANE));
3073 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3076 + /* Configure Flow Control after link up. */
3078 + e1000e_config_fc_after_link_up(hw);
3080 + e_dbg("Error config flow control\n");
3083 + mac->serdes_link_state =
3084 + e1000_serdes_link_forced_up;
3085 + mac->serdes_has_link = true;
3086 + e_dbg("AN_PROG -> FORCED_UP\n");
3090 + case e1000_serdes_link_down:
3092 + /* The link was down but the receiver has now gained
3093 + * valid sync, so lets see if we can bring the link
3095 + ew32(TXCW, mac->txcw);
3097 + (ctrl & ~E1000_CTRL_SLU));
3098 + mac->serdes_link_state =
3099 + e1000_serdes_link_autoneg_progress;
3100 + e_dbg("DOWN -> AN_PROG\n");
3104 + if (!(rxcw & E1000_RXCW_SYNCH)) {
3105 + mac->serdes_has_link = false;
3106 + mac->serdes_link_state = e1000_serdes_link_down;
3107 + e_dbg("ANYSTATE -> DOWN\n");
3110 + * We have sync, and can tolerate one
3111 + * invalid (IV) codeword before declaring
3112 + * link down, so reread to look again
3115 + rxcw = er32(RXCW);
3116 + if (rxcw & E1000_RXCW_IV) {
3117 + mac->serdes_link_state = e1000_serdes_link_down;
3118 + mac->serdes_has_link = false;
3119 + e_dbg("ANYSTATE -> DOWN\n");
3128 + * e1000_valid_led_default_82571 - Verify a valid default LED config
3129 + * @hw: pointer to the HW structure
3130 + * @data: pointer to the NVM (EEPROM)
3132 + * Read the EEPROM for the current default LED configuration. If the
3133 + * LED configuration is not valid, set to a valid LED configuration.
3135 +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
3139 + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3141 + e_dbg("NVM Read Error\n");
3145 + switch (hw->mac.type) {
3149 + if(*data == ID_LED_RESERVED_F746)
3150 + *data = ID_LED_DEFAULT_82573;
3153 + if (*data == ID_LED_RESERVED_0000 ||
3154 + *data == ID_LED_RESERVED_FFFF)
3155 + *data = ID_LED_DEFAULT;
3164 + * e1000e_get_laa_state_82571 - Get locally administered address state
3165 + * @hw: pointer to the HW structure
3167 + * Retrieve and return the current locally administered address state.
3169 +bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
3171 + if (hw->mac.type != e1000_82571)
3174 + return hw->dev_spec._82571.laa_is_present;
3178 + * e1000e_set_laa_state_82571 - Set locally administered address state
3179 + * @hw: pointer to the HW structure
3180 + * @state: enable/disable locally administered address
3182 + * Enable/Disable the current locally administered address state.
3184 +void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
3186 + if (hw->mac.type != e1000_82571)
3189 + hw->dev_spec._82571.laa_is_present = state;
3191 + /* If workaround is activated... */
3194 + * Hold a copy of the LAA in RAR[14] This is done so that
3195 + * between the time RAR[0] gets clobbered and the time it
3196 + * gets fixed, the actual LAA is in one of the RARs and no
3197 + * incoming packets directed to this port are dropped.
3198 + * Eventually the LAA will be in RAR[0] and RAR[14].
3200 + e1000e_rar_set(hw, hw->mac.addr,
3201 + hw->mac.rar_entry_count - 1);
3206 + * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
3207 + * @hw: pointer to the HW structure
3209 + * Verifies that the EEPROM has completed the update. After updating the
3210 + * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
3211 + * the checksum fix is not implemented, we need to set the bit and update
3212 + * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
3213 + * we need to return bad checksum.
3215 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
3217 + struct e1000_nvm_info *nvm = &hw->nvm;
3218 + s32 ret_val = E1000_SUCCESS;
3221 + if (nvm->type != e1000_nvm_flash_hw)
3225 + * Check bit 4 of word 10h. If it is 0, firmware is done updating
3226 + * 10h-12h. Checksum may need to be fixed.
3228 + ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
3232 + if (!(data & 0x10)) {
3234 + * Read 0x23 and check bit 15. This bit is a 1
3235 + * when the checksum has already been fixed. If
3236 + * the checksum is still wrong and this bit is a
3237 + * 1, we need to return bad checksum. Otherwise,
3238 + * we need to set this bit to a 1 and update the
3241 + ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
3245 + if (!(data & 0x8000)) {
3247 + ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
3250 + ret_val = e1000e_update_nvm_checksum(hw);
3260 + * e1000_read_mac_addr_82571 - Read device MAC address
3261 + * @hw: pointer to the HW structure
3263 +static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
3265 + s32 ret_val = E1000_SUCCESS;
3268 + * If there's an alternate MAC address place it in RAR0
3269 + * so that it will override the Si installed default perm
3272 + ret_val = e1000_check_alt_mac_addr_generic(hw);
3276 + ret_val = e1000e_read_mac_addr_generic(hw);
3283 + * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
3284 + * @hw: pointer to the HW structure
3286 + * In the case of a PHY power down to save power, or to turn off link during a
3287 + * driver unload, or wake on lan is not enabled, remove the link.
3289 +static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
3291 + struct e1000_phy_info *phy = &hw->phy;
3292 + struct e1000_mac_info *mac = &hw->mac;
3294 + if (!(phy->ops.check_reset_block))
3297 + /* If the management interface is not enabled, then power down */
3298 + if (!(mac->ops.check_mng_mode(hw) || e1000_check_reset_block(hw)))
3299 + e1000_power_down_phy_copper(hw);
3305 + * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
3306 + * @hw: pointer to the HW structure
3308 + * Clears the hardware counters by reading the counter registers.
3310 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
3312 + e1000e_clear_hw_cntrs_base(hw);
3349 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_82571.h linux-2.6.22-10/drivers/net/e1000e/e1000_82571.h
3350 --- linux-2.6.22-0/drivers/net/e1000e/e1000_82571.h 1970-01-01 01:00:00.000000000 +0100
3351 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_82571.h 2009-06-24 00:32:20.000000000 +0200
3353 +/*******************************************************************************
3355 + Intel PRO/1000 Linux driver
3356 + Copyright(c) 1999 - 2009 Intel Corporation.
3358 + This program is free software; you can redistribute it and/or modify it
3359 + under the terms and conditions of the GNU General Public License,
3360 + version 2, as published by the Free Software Foundation.
3362 + This program is distributed in the hope it will be useful, but WITHOUT
3363 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3364 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3367 + You should have received a copy of the GNU General Public License along with
3368 + this program; if not, write to the Free Software Foundation, Inc.,
3369 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3371 + The full GNU General Public License is included in this distribution in
3372 + the file called "COPYING".
3374 + Contact Information:
3375 + Linux NICS <linux.nics@intel.com>
3376 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
3377 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
3379 +*******************************************************************************/
3381 +#ifndef _E1000_82571_H_
3382 +#define _E1000_82571_H_
3384 +#define ID_LED_RESERVED_F746 0xF746
3385 +#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
3386 + (ID_LED_OFF1_ON2 << 8) | \
3387 + (ID_LED_DEF1_DEF2 << 4) | \
3388 + (ID_LED_DEF1_DEF2))
3390 +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
3392 +/* Intr Throttling - RW */
3393 +#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
3395 +#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
3396 +#define E1000_EIAC_MASK_82574 0x01F00000
3398 +#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
3400 +#define E1000_RXCFGL 0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
3402 +bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
3403 +void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
3406 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_defines.h linux-2.6.22-10/drivers/net/e1000e/e1000_defines.h
3407 --- linux-2.6.22-0/drivers/net/e1000e/e1000_defines.h 1970-01-01 01:00:00.000000000 +0100
3408 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_defines.h 2009-06-24 00:32:20.000000000 +0200
3410 +/*******************************************************************************
3412 + Intel PRO/1000 Linux driver
3413 + Copyright(c) 1999 - 2009 Intel Corporation.
3415 + This program is free software; you can redistribute it and/or modify it
3416 + under the terms and conditions of the GNU General Public License,
3417 + version 2, as published by the Free Software Foundation.
3419 + This program is distributed in the hope it will be useful, but WITHOUT
3420 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3421 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3424 + You should have received a copy of the GNU General Public License along with
3425 + this program; if not, write to the Free Software Foundation, Inc.,
3426 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3428 + The full GNU General Public License is included in this distribution in
3429 + the file called "COPYING".
3431 + Contact Information:
3432 + Linux NICS <linux.nics@intel.com>
3433 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
3434 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
3436 +*******************************************************************************/
3438 +#ifndef _E1000_DEFINES_H_
3439 +#define _E1000_DEFINES_H_
3441 +/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
3442 +#define REQ_TX_DESCRIPTOR_MULTIPLE 8
3443 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8
3445 +/* Definitions for power management and wakeup registers */
3446 +/* Wake Up Control */
3447 +#define E1000_WUC_APME 0x00000001 /* APM Enable */
3448 +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
3449 +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
3450 +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
3451 +#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
3452 +#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
3453 +#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
3454 +#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
3456 +/* Wake Up Filter Control */
3457 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
3458 +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
3459 +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
3460 +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
3461 +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
3462 +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
3463 +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
3464 +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
3465 +#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
3466 +#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */
3467 +#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */
3468 +#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */
3469 +#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */
3470 +#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */
3471 +#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */
3472 +#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
3473 +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
3474 +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
3475 +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
3476 +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
3477 +#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
3478 +#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
3479 +#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/
3480 +#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
3481 +#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/
3482 +#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */
3483 +#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/
3484 +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
3485 +#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask for all 6 wakeup filters*/
3486 +#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
3487 +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /*Mask for the 4 flexible filters */
3488 +#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flexible filters */
3490 +/* Wake Up Status */
3491 +#define E1000_WUS_LNKC E1000_WUFC_LNKC
3492 +#define E1000_WUS_MAG E1000_WUFC_MAG
3493 +#define E1000_WUS_EX E1000_WUFC_EX
3494 +#define E1000_WUS_MC E1000_WUFC_MC
3495 +#define E1000_WUS_BC E1000_WUFC_BC
3496 +#define E1000_WUS_ARP E1000_WUFC_ARP
3497 +#define E1000_WUS_IPV4 E1000_WUFC_IPV4
3498 +#define E1000_WUS_IPV6 E1000_WUFC_IPV6
3499 +#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY
3500 +#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY
3501 +#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY
3502 +#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY
3503 +#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4
3504 +#define E1000_WUS_FLX0 E1000_WUFC_FLX0
3505 +#define E1000_WUS_FLX1 E1000_WUFC_FLX1
3506 +#define E1000_WUS_FLX2 E1000_WUFC_FLX2
3507 +#define E1000_WUS_FLX3 E1000_WUFC_FLX3
3508 +#define E1000_WUS_FLX4 E1000_WUFC_FLX4
3509 +#define E1000_WUS_FLX5 E1000_WUFC_FLX5
3510 +#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY
3511 +#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY
3512 +#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
3513 +#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6
3514 +#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6
3516 +/* Wake Up Packet Length */
3517 +#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
3519 +/* Four Flexible Filters are supported */
3520 +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
3521 +/* Six Flexible Filters are supported */
3522 +#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6
3524 +/* Each Flexible Filter is at most 128 (0x80) bytes in length */
3525 +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
3527 +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
3528 +#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
3529 +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
3530 +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
3532 +/* Extended Device Control */
3533 +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
3534 +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
3535 +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
3536 +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
3537 +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
3538 +/* Reserved (bits 4,5) in >= 82575 */
3539 +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
3540 +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
3541 +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
3542 +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
3543 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
3544 +/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
3545 +#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
3546 +#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
3547 +#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
3548 +#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
3549 +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
3550 +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
3551 +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
3552 +#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
3553 +#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
3554 +#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
3555 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
3556 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
3557 +#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
3558 +#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
3559 +#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
3560 +#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
3561 +#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
3562 +#define E1000_CTRL_EXT_EIAME 0x01000000
3563 +#define E1000_CTRL_EXT_IRCA 0x00000001
3564 +#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
3565 +#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
3566 +#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
3567 +#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
3568 +#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
3569 +#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
3570 +#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
3571 +/* IAME enable bit (27) was removed in >= 82575 */
3572 +#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */
3573 +#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error
3574 + * detection enabled */
3575 +#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity
3576 + * error detection enable */
3577 +#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
3578 +#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
3579 +#define E1000_CTRL_EXT_LSECCK 0x00001000
3580 +#define E1000_CTRL_EXT_PHYPDEN 0x00100000
3581 +#define E1000_I2CCMD_REG_ADDR_SHIFT 16
3582 +#define E1000_I2CCMD_REG_ADDR 0x00FF0000
3583 +#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
3584 +#define E1000_I2CCMD_PHY_ADDR 0x07000000
3585 +#define E1000_I2CCMD_OPCODE_READ 0x08000000
3586 +#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
3587 +#define E1000_I2CCMD_RESET 0x10000000
3588 +#define E1000_I2CCMD_READY 0x20000000
3589 +#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
3590 +#define E1000_I2CCMD_ERROR 0x80000000
3591 +#define E1000_MAX_SGMII_PHY_REG_ADDR 255
3592 +#define E1000_I2CCMD_PHY_TIMEOUT 200
3594 +/* Receive Descriptor bit definitions */
3595 +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
3596 +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
3597 +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
3598 +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
3599 +#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
3600 +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
3601 +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
3602 +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
3603 +#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
3604 +#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
3605 +#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
3606 +#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
3607 +#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
3608 +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
3609 +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
3610 +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
3611 +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
3612 +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
3613 +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
3614 +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
3615 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
3616 +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
3617 +#define E1000_RXD_SPC_PRI_SHIFT 13
3618 +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
3619 +#define E1000_RXD_SPC_CFI_SHIFT 12
3621 +#define E1000_RXDEXT_STATERR_CE 0x01000000
3622 +#define E1000_RXDEXT_STATERR_SE 0x02000000
3623 +#define E1000_RXDEXT_STATERR_SEQ 0x04000000
3624 +#define E1000_RXDEXT_STATERR_CXE 0x10000000
3625 +#define E1000_RXDEXT_STATERR_TCPE 0x20000000
3626 +#define E1000_RXDEXT_STATERR_IPE 0x40000000
3627 +#define E1000_RXDEXT_STATERR_RXE 0x80000000
3629 +#define E1000_RXDEXT_LSECH 0x01000000
3630 +#define E1000_RXDEXT_LSECE_MASK 0x60000000
3631 +#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000
3632 +#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000
3633 +#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
3634 +#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000
3636 +/* mask to determine if packets should be dropped due to frame errors */
3637 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
3638 + E1000_RXD_ERR_CE | \
3639 + E1000_RXD_ERR_SE | \
3640 + E1000_RXD_ERR_SEQ | \
3641 + E1000_RXD_ERR_CXE | \
3642 + E1000_RXD_ERR_RXE)
3644 +/* Same mask, but for extended and packet split descriptors */
3645 +#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
3646 + E1000_RXDEXT_STATERR_CE | \
3647 + E1000_RXDEXT_STATERR_SE | \
3648 + E1000_RXDEXT_STATERR_SEQ | \
3649 + E1000_RXDEXT_STATERR_CXE | \
3650 + E1000_RXDEXT_STATERR_RXE)
3652 +#define E1000_MRQC_ENABLE_MASK 0x00000007
3653 +#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
3654 +#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
3655 +#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
3656 +#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
3657 +#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
3658 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
3659 +#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
3660 +#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
3661 +#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
3663 +#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
3664 +#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
3666 +/* Management Control */
3667 +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
3668 +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
3669 +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
3670 +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
3671 +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
3672 +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
3673 +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
3674 +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
3675 +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
3676 +/* Enable Neighbor Discovery Filtering */
3677 +#define E1000_MANC_NEIGHBOR_EN 0x00004000
3678 +#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
3679 +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
3680 +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
3681 +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
3682 +#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
3683 +#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
3684 +/* Enable MAC address filtering */
3685 +#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
3686 +/* Enable MNG packets to host memory */
3687 +#define E1000_MANC_EN_MNG2HOST 0x00200000
3688 +/* Enable IP address filtering */
3689 +#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
3690 +#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
3691 +#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
3692 +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
3693 +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
3694 +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
3695 +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
3696 +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
3697 +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
3699 +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
3700 +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
3702 +/* Receive Control */
3703 +#define E1000_RCTL_RST 0x00000001 /* Software reset */
3704 +#define E1000_RCTL_EN 0x00000002 /* enable */
3705 +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
3706 +#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
3707 +#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
3708 +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
3709 +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
3710 +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
3711 +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
3712 +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
3713 +#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
3714 +#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
3715 +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */
3716 +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */
3717 +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */
3718 +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
3719 +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
3720 +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
3721 +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
3722 +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
3723 +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
3724 +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
3725 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
3726 +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
3727 +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
3728 +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
3729 +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
3730 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
3731 +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
3732 +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
3733 +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
3734 +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
3735 +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
3736 +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
3737 +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
3738 +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
3739 +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
3740 +#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
3741 +#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
3742 +#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
3745 + * Use byte values for the following shift parameters
3747 + * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
3748 + * E1000_PSRCTL_BSIZE0_MASK) |
3749 + * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
3750 + * E1000_PSRCTL_BSIZE1_MASK) |
3751 + * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
3752 + * E1000_PSRCTL_BSIZE2_MASK) |
3753 + * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
3754 + * E1000_PSRCTL_BSIZE3_MASK))
3755 + * where value0 = [128..16256], default=256
3756 + * value1 = [1024..64512], default=4096
3757 + * value2 = [0..64512], default=4096
3758 + * value3 = [0..64512], default=0
3761 +#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
3762 +#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
3763 +#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
3764 +#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
3766 +#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
3767 +#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
3768 +#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
3769 +#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
3771 +/* SWFW_SYNC Definitions */
3772 +#define E1000_SWFW_EEP_SM 0x01
3773 +#define E1000_SWFW_PHY0_SM 0x02
3774 +#define E1000_SWFW_PHY1_SM 0x04
3775 +#define E1000_SWFW_CSR_SM 0x08
3777 +/* FACTPS Definitions */
3778 +#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
3779 +/* Device Control */
3780 +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
3781 +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
3782 +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
3783 +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
3784 +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
3785 +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
3786 +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
3787 +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
3788 +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
3789 +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
3790 +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
3791 +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
3792 +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
3793 +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
3794 +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
3795 +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
3796 +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
3797 +#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
3798 +#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
3799 + * indication in SDP[0] */
3800 +#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
3802 +#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
3803 + * LINK_0 and LINK_1 pins */
3804 +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
3805 +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
3806 +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
3807 +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
3808 +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
3809 +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
3810 +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
3811 +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
3812 +#define E1000_CTRL_RST 0x04000000 /* Global reset */
3813 +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
3814 +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
3815 +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
3816 +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
3817 +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
3818 +#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
3819 +#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
3822 + * Bit definitions for the Management Data IO (MDIO) and Management Data
3823 + * Clock (MDC) pins in the Device Control Register.
3825 +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
3826 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
3827 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
3828 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
3829 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
3830 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
3831 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
3832 +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
3834 +#define E1000_CONNSW_ENRGSRC 0x4
3835 +#define E1000_PCS_CFG_PCS_EN 8
3836 +#define E1000_PCS_LCTL_FLV_LINK_UP 1
3837 +#define E1000_PCS_LCTL_FSV_10 0
3838 +#define E1000_PCS_LCTL_FSV_100 2
3839 +#define E1000_PCS_LCTL_FSV_1000 4
3840 +#define E1000_PCS_LCTL_FDV_FULL 8
3841 +#define E1000_PCS_LCTL_FSD 0x10
3842 +#define E1000_PCS_LCTL_FORCE_LINK 0x20
3843 +#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
3844 +#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
3845 +#define E1000_PCS_LCTL_AN_ENABLE 0x10000
3846 +#define E1000_PCS_LCTL_AN_RESTART 0x20000
3847 +#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
3848 +#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
3849 +#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
3850 +#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
3851 +#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
3852 +#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
3853 +#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
3855 +#define E1000_PCS_LSTS_LINK_OK 1
3856 +#define E1000_PCS_LSTS_SPEED_10 0
3857 +#define E1000_PCS_LSTS_SPEED_100 2
3858 +#define E1000_PCS_LSTS_SPEED_1000 4
3859 +#define E1000_PCS_LSTS_DUPLEX_FULL 8
3860 +#define E1000_PCS_LSTS_SYNK_OK 0x10
3861 +#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
3862 +#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
3863 +#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
3864 +#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
3865 +#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
3867 +/* Device Status */
3868 +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
3869 +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
3870 +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
3871 +#define E1000_STATUS_FUNC_SHIFT 2
3872 +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
3873 +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
3874 +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
3875 +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
3876 +#define E1000_STATUS_SPEED_MASK 0x000000C0
3877 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
3878 +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
3879 +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
3880 +#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
3881 +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
3882 +#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
3883 +#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state.
3884 + * Clear on write '0'. */
3885 +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
3886 +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
3887 +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
3888 +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
3889 +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
3890 +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
3891 +#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
3892 +#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
3893 +#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
3894 +#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
3895 +#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution
3897 +#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
3898 +#define E1000_STATUS_FUSE_8 0x04000000
3899 +#define E1000_STATUS_FUSE_9 0x08000000
3900 +#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
3901 +#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
3903 +/* Constants used to interpret the masked PCI-X bus speed. */
3904 +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
3905 +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
3906 +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
3908 +#define SPEED_10 10
3909 +#define SPEED_100 100
3910 +#define SPEED_1000 1000
3911 +#define HALF_DUPLEX 1
3912 +#define FULL_DUPLEX 2
3914 +#define PHY_FORCE_TIME 20
3916 +#define ADVERTISE_10_HALF 0x0001
3917 +#define ADVERTISE_10_FULL 0x0002
3918 +#define ADVERTISE_100_HALF 0x0004
3919 +#define ADVERTISE_100_FULL 0x0008
3920 +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
3921 +#define ADVERTISE_1000_FULL 0x0020
3923 +/* 1000/H is not supported, nor spec-compliant. */
3924 +#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
3925 + ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
3926 + ADVERTISE_1000_FULL)
3927 +#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
3928 + ADVERTISE_100_HALF | ADVERTISE_100_FULL)
3929 +#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
3930 +#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
3931 +#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
3932 + ADVERTISE_1000_FULL)
3933 +#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
3935 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
3938 +#define E1000_PHY_LED0_MODE_MASK 0x00000007
3939 +#define E1000_PHY_LED0_IVRT 0x00000008
3940 +#define E1000_PHY_LED0_BLINK 0x00000010
3941 +#define E1000_PHY_LED0_MASK 0x0000001F
3943 +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
3944 +#define E1000_LEDCTL_LED0_MODE_SHIFT 0
3945 +#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
3946 +#define E1000_LEDCTL_LED0_IVRT 0x00000040
3947 +#define E1000_LEDCTL_LED0_BLINK 0x00000080
3948 +#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
3949 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8
3950 +#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
3951 +#define E1000_LEDCTL_LED1_IVRT 0x00004000
3952 +#define E1000_LEDCTL_LED1_BLINK 0x00008000
3953 +#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
3954 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16
3955 +#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
3956 +#define E1000_LEDCTL_LED2_IVRT 0x00400000
3957 +#define E1000_LEDCTL_LED2_BLINK 0x00800000
3958 +#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
3959 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24
3960 +#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
3961 +#define E1000_LEDCTL_LED3_IVRT 0x40000000
3962 +#define E1000_LEDCTL_LED3_BLINK 0x80000000
3964 +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
3965 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
3966 +#define E1000_LEDCTL_MODE_LINK_UP 0x2
3967 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3
3968 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
3969 +#define E1000_LEDCTL_MODE_LINK_10 0x5
3970 +#define E1000_LEDCTL_MODE_LINK_100 0x6
3971 +#define E1000_LEDCTL_MODE_LINK_1000 0x7
3972 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
3973 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
3974 +#define E1000_LEDCTL_MODE_COLLISION 0xA
3975 +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
3976 +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
3977 +#define E1000_LEDCTL_MODE_PAUSED 0xD
3978 +#define E1000_LEDCTL_MODE_LED_ON 0xE
3979 +#define E1000_LEDCTL_MODE_LED_OFF 0xF
3981 +/* Transmit Descriptor bit definitions */
3982 +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
3983 +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
3984 +#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
3985 +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
3986 +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
3987 +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
3988 +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
3989 +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
3990 +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
3991 +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
3992 +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
3993 +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
3994 +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
3995 +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
3996 +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
3997 +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
3998 +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
3999 +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
4000 +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
4001 +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
4002 +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
4003 +/* Extended desc bits for Linksec and timesync */
4004 +#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */
4005 +#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
4007 +/* Transmit Control */
4008 +#define E1000_TCTL_RST 0x00000001 /* software reset */
4009 +#define E1000_TCTL_EN 0x00000002 /* enable tx */
4010 +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
4011 +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
4012 +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
4013 +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
4014 +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
4015 +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
4016 +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
4017 +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
4018 +#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
4020 +/* Transmit Arbitration Count */
4021 +#define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
4023 +/* SerDes Control */
4024 +#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
4026 +/* Receive Checksum Control */
4027 +#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
4028 +#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
4029 +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
4030 +#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
4031 +#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
4032 +#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
4033 +#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
4035 +/* Header split receive */
4036 +#define E1000_RFCTL_ISCSI_DIS 0x00000001
4037 +#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
4038 +#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
4039 +#define E1000_RFCTL_NFSW_DIS 0x00000040
4040 +#define E1000_RFCTL_NFSR_DIS 0x00000080
4041 +#define E1000_RFCTL_NFS_VER_MASK 0x00000300
4042 +#define E1000_RFCTL_NFS_VER_SHIFT 8
4043 +#define E1000_RFCTL_IPV6_DIS 0x00000400
4044 +#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
4045 +#define E1000_RFCTL_ACK_DIS 0x00001000
4046 +#define E1000_RFCTL_ACKD_DIS 0x00002000
4047 +#define E1000_RFCTL_IPFRSP_DIS 0x00004000
4048 +#define E1000_RFCTL_EXTEN 0x00008000
4049 +#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
4050 +#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
4051 +#define E1000_RFCTL_LEF 0x00040000
4053 +/* Collision related configuration parameters */
4054 +#define E1000_COLLISION_THRESHOLD 15
4055 +#define E1000_CT_SHIFT 4
4056 +#define E1000_COLLISION_DISTANCE 63
4057 +#define E1000_COLD_SHIFT 12
4059 +/* Default values for the transmit IPG register */
4060 +#define DEFAULT_82543_TIPG_IPGT_FIBER 9
4061 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8
4063 +#define E1000_TIPG_IPGT_MASK 0x000003FF
4064 +#define E1000_TIPG_IPGR1_MASK 0x000FFC00
4065 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000
4067 +#define DEFAULT_82543_TIPG_IPGR1 8
4068 +#define E1000_TIPG_IPGR1_SHIFT 10
4070 +#define DEFAULT_82543_TIPG_IPGR2 6
4071 +#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
4072 +#define E1000_TIPG_IPGR2_SHIFT 20
4074 +/* Ethertype field values */
4075 +#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
4077 +#define ETHERNET_FCS_SIZE 4
4078 +#define MAX_JUMBO_FRAME_SIZE 0x3F00
4080 +/* Extended Configuration Control and Size */
4081 +#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
4082 +#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
4083 +#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
4084 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
4085 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
4086 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
4087 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
4089 +#define E1000_PHY_CTRL_SPD_EN 0x00000001
4090 +#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
4091 +#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
4092 +#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
4093 +#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
4095 +#define E1000_KABGTXD_BGSQLBIAS 0x00050000
4097 +/* PBA constants */
4098 +#define E1000_PBA_6K 0x0006 /* 6KB */
4099 +#define E1000_PBA_8K 0x0008 /* 8KB */
4100 +#define E1000_PBA_10K 0x000A /* 10KB */
4101 +#define E1000_PBA_12K 0x000C /* 12KB */
4102 +#define E1000_PBA_14K 0x000E /* 14KB */
4103 +#define E1000_PBA_16K 0x0010 /* 16KB */
4104 +#define E1000_PBA_18K 0x0012
4105 +#define E1000_PBA_20K 0x0014
4106 +#define E1000_PBA_22K 0x0016
4107 +#define E1000_PBA_24K 0x0018
4108 +#define E1000_PBA_26K 0x001A
4109 +#define E1000_PBA_30K 0x001E
4110 +#define E1000_PBA_32K 0x0020
4111 +#define E1000_PBA_34K 0x0022
4112 +#define E1000_PBA_35K 0x0023
4113 +#define E1000_PBA_38K 0x0026
4114 +#define E1000_PBA_40K 0x0028
4115 +#define E1000_PBA_48K 0x0030 /* 48KB */
4116 +#define E1000_PBA_64K 0x0040 /* 64KB */
4118 +#define E1000_PBS_16K E1000_PBA_16K
4119 +#define E1000_PBS_24K E1000_PBA_24K
4123 +#define IFS_RATIO 4
4124 +#define IFS_STEP 10
4125 +#define MIN_NUM_XMITS 1000
4127 +/* SW Semaphore Register */
4128 +#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
4129 +#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
4130 +#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
4131 +#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
4133 +#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
4135 +/* Interrupt Cause Read */
4136 +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
4137 +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
4138 +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
4139 +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
4140 +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
4141 +#define E1000_ICR_RXO 0x00000040 /* rx overrun */
4142 +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
4143 +#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
4144 +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
4145 +#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
4146 +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
4147 +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
4148 +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
4149 +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
4150 +#define E1000_ICR_TXD_LOW 0x00008000
4151 +#define E1000_ICR_SRPD 0x00010000
4152 +#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
4153 +#define E1000_ICR_MNG 0x00040000 /* Manageability event */
4154 +#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
4155 +#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver
4156 + * should claim the interrupt */
4157 +#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
4158 +#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
4159 +#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
4160 +#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
4161 +#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
4162 +#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
4163 +#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
4164 +#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW
4165 + * bit in the FWSM */
4166 +#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates
4168 +#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
4169 +#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
4170 +#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
4171 +#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
4172 +#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
4173 +#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
4174 +#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
4176 +/* PBA ECC Register */
4177 +#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
4178 +#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
4179 +#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
4180 +#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
4181 +#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
4184 + * This defines the bits that are set in the Interrupt Mask
4185 + * Set/Read Register. Each bit is documented below:
4186 + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
4187 + * o RXSEQ = Receive Sequence Error
4189 +#define POLL_IMS_ENABLE_MASK ( \
4190 + E1000_IMS_RXDMT0 | \
4194 + * This defines the bits that are set in the Interrupt Mask
4195 + * Set/Read Register. Each bit is documented below:
4196 + * o RXT0 = Receiver Timer Interrupt (ring 0)
4197 + * o TXDW = Transmit Descriptor Written Back
4198 + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
4199 + * o RXSEQ = Receive Sequence Error
4200 + * o LSC = Link Status Change
4202 +#define IMS_ENABLE_MASK ( \
4203 + E1000_IMS_RXT0 | \
4204 + E1000_IMS_TXDW | \
4205 + E1000_IMS_RXDMT0 | \
4206 + E1000_IMS_RXSEQ | \
4209 +/* Interrupt Mask Set */
4210 +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
4211 +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
4212 +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
4213 +#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
4214 +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
4215 +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
4216 +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
4217 +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
4218 +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
4219 +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
4220 +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
4221 +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
4222 +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
4223 +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
4224 +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
4225 +#define E1000_IMS_SRPD E1000_ICR_SRPD
4226 +#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
4227 +#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
4228 +#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
4229 +#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
4231 +#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
4233 +#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer
4235 +#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity
4237 +#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
4239 +#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
4241 +#define E1000_IMS_DSW E1000_ICR_DSW
4242 +#define E1000_IMS_PHYINT E1000_ICR_PHYINT
4243 +#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
4244 +#define E1000_IMS_EPRST E1000_ICR_EPRST
4245 +#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
4246 +#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
4247 +#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
4248 +#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
4249 +#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
4251 +/* Interrupt Cause Set */
4252 +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */
4253 +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
4254 +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
4255 +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
4256 +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
4257 +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
4258 +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
4259 +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
4260 +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
4261 +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
4262 +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
4263 +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
4264 +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
4265 +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
4266 +#define E1000_ICS_SRPD E1000_ICR_SRPD
4267 +#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
4268 +#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
4269 +#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
4270 +#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
4272 +#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
4274 +#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer
4276 +#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity
4278 +#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
4280 +#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
4282 +#define E1000_ICS_DSW E1000_ICR_DSW
4283 +#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
4284 +#define E1000_ICS_PHYINT E1000_ICR_PHYINT
4285 +#define E1000_ICS_EPRST E1000_ICR_EPRST
4287 +/* Transmit Descriptor Control */
4288 +#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
4289 +#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
4290 +#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
4291 +#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
4292 +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
4293 +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
4294 +#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
4295 +/* Enable the counting of descriptors still to be processed. */
4296 +#define E1000_TXDCTL_COUNT_DESC 0x00400000
4298 +/* Flow Control Constants */
4299 +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
4300 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
4301 +#define FLOW_CONTROL_TYPE 0x8808
4303 +/* 802.1q VLAN Packet Size */
4304 +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
4305 +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
4307 +/* Receive Address */
4309 + * Number of high/low register pairs in the RAR. The RAR (Receive Address
4310 + * Registers) holds the directed and multicast addresses that we monitor.
4311 + * Technically, we have 16 spots. However, we reserve one of these spots
4312 + * (RAR[15]) for our directed address used by controllers with
4313 + * manageability enabled, allowing us room for 15 multicast addresses.
4315 +#define E1000_RAR_ENTRIES 15
4316 +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
4317 +#define E1000_RAL_MAC_ADDR_LEN 4
4318 +#define E1000_RAH_MAC_ADDR_LEN 2
4319 +#define E1000_RAH_POOL_MASK 0x03FC0000
4320 +#define E1000_RAH_POOL_1 0x00040000
4323 +#define E1000_SUCCESS 0
4324 +#define E1000_ERR_NVM 1
4325 +#define E1000_ERR_PHY 2
4326 +#define E1000_ERR_CONFIG 3
4327 +#define E1000_ERR_PARAM 4
4328 +#define E1000_ERR_MAC_INIT 5
4329 +#define E1000_ERR_PHY_TYPE 6
4330 +#define E1000_ERR_RESET 9
4331 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10
4332 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11
4333 +#define E1000_BLK_PHY_RESET 12
4334 +#define E1000_ERR_SWFW_SYNC 13
4335 +#define E1000_NOT_IMPLEMENTED 14
4336 +#define E1000_ERR_MBX 15
4338 +/* Loop limit on how long we wait for auto-negotiation to complete */
4339 +#define FIBER_LINK_UP_LIMIT 50
4340 +#define COPPER_LINK_UP_LIMIT 10
4341 +#define PHY_AUTO_NEG_LIMIT 45
4342 +#define PHY_FORCE_LIMIT 20
4343 +/* Number of 100 microseconds we wait for PCI Express master disable */
4344 +#define MASTER_DISABLE_TIMEOUT 800
4345 +/* Number of milliseconds we wait for PHY configuration done after MAC reset */
4346 +#define PHY_CFG_TIMEOUT 100
4347 +/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
4348 +#define MDIO_OWNERSHIP_TIMEOUT 10
4349 +/* Number of milliseconds for NVM auto read done after MAC reset. */
4350 +#define AUTO_READ_DONE_TIMEOUT 10
4353 +#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
4354 +#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
4355 +#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
4356 +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
4358 +/* Transmit Configuration Word */
4359 +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
4360 +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
4361 +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
4362 +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
4363 +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
4364 +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
4365 +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
4366 +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
4367 +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
4368 +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
4370 +/* Receive Configuration Word */
4371 +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
4372 +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
4373 +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
4374 +#define E1000_RXCW_CC 0x10000000 /* Receive config change */
4375 +#define E1000_RXCW_C 0x20000000 /* Receive config */
4376 +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
4377 +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
4380 +/* PCI Express Control */
4381 +#define E1000_GCR_RXD_NO_SNOOP 0x00000001
4382 +#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
4383 +#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
4384 +#define E1000_GCR_TXD_NO_SNOOP 0x00000008
4385 +#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
4386 +#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
4387 +#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
4388 +#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
4389 +#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
4390 +#define E1000_GCR_CAP_VER2 0x00040000
4392 +#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
4393 + E1000_GCR_RXDSCW_NO_SNOOP | \
4394 + E1000_GCR_RXDSCR_NO_SNOOP | \
4395 + E1000_GCR_TXD_NO_SNOOP | \
4396 + E1000_GCR_TXDSCW_NO_SNOOP | \
4397 + E1000_GCR_TXDSCR_NO_SNOOP)
4399 +/* PHY Control Register */
4400 +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
4401 +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
4402 +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
4403 +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
4404 +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
4405 +#define MII_CR_POWER_DOWN 0x0800 /* Power down */
4406 +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
4407 +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
4408 +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
4409 +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
4410 +#define MII_CR_SPEED_1000 0x0040
4411 +#define MII_CR_SPEED_100 0x2000
4412 +#define MII_CR_SPEED_10 0x0000
4414 +/* PHY Status Register */
4415 +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
4416 +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
4417 +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
4418 +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
4419 +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
4420 +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
4421 +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
4422 +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
4423 +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
4424 +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
4425 +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
4426 +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
4427 +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
4428 +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
4429 +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
4431 +/* Autoneg Advertisement Register */
4432 +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
4433 +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
4434 +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
4435 +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
4436 +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
4437 +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
4438 +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
4439 +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
4440 +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
4441 +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
4443 +/* Link Partner Ability Register (Base Page) */
4444 +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
4445 +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
4446 +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
4447 +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
4448 +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
4449 +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
4450 +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
4451 +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
4452 +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
4453 +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
4454 +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
4456 +/* Autoneg Expansion Register */
4457 +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
4458 +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
4459 +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
4460 +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
4461 +#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
4463 +/* 1000BASE-T Control Register */
4464 +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
4465 +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
4466 +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
4467 +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
4468 + /* 0=DTE device */
4469 +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
4470 + /* 0=Configure PHY as Slave */
4471 +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
4472 + /* 0=Automatic Master/Slave config */
4473 +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
4474 +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
4475 +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
4476 +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
4477 +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
4479 +/* 1000BASE-T Status Register */
4480 +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
4481 +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
4482 +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
4483 +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
4484 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
4485 +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
4486 +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
4487 +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
4489 +#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
4491 +/* PHY 1000 MII Register/Bit Definitions */
4492 +/* PHY Registers defined by IEEE */
4493 +#define PHY_CONTROL 0x00 /* Control Register */
4494 +#define PHY_STATUS 0x01 /* Status Register */
4495 +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
4496 +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
4497 +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
4498 +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
4499 +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
4500 +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
4501 +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
4502 +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
4503 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
4504 +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
4506 +#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
4509 +#define E1000_EECD_SK 0x00000001 /* NVM Clock */
4510 +#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
4511 +#define E1000_EECD_DI 0x00000004 /* NVM Data In */
4512 +#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
4513 +#define E1000_EECD_FWE_MASK 0x00000030
4514 +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
4515 +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
4516 +#define E1000_EECD_FWE_SHIFT 4
4517 +#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
4518 +#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
4519 +#define E1000_EECD_PRES 0x00000100 /* NVM Present */
4520 +#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
4521 +/* NVM Addressing bits based on type 0=small, 1=large */
4522 +#define E1000_EECD_ADDR_BITS 0x00000400
4523 +#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
4524 +#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
4525 +#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
4526 +#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
4527 +#define E1000_EECD_SIZE_EX_SHIFT 11
4528 +#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
4529 +#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
4530 +#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
4531 +#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
4532 +#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
4533 +#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
4534 +#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
4535 +#define E1000_EECD_SECVAL_SHIFT 22
4536 +#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
4538 +#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
4539 +#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
4540 +#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
4541 +#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
4542 +#define E1000_NVM_RW_REG_START 1 /* Start operation */
4543 +#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
4544 +#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
4545 +#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
4546 +#define E1000_FLASH_UPDATES 2000
4548 +/* NVM Word Offsets */
4549 +#define NVM_COMPAT 0x0003
4550 +#define NVM_ID_LED_SETTINGS 0x0004
4551 +#define NVM_VERSION 0x0005
4552 +#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
4553 +#define NVM_PHY_CLASS_WORD 0x0007
4554 +#define NVM_INIT_CONTROL1_REG 0x000A
4555 +#define NVM_INIT_CONTROL2_REG 0x000F
4556 +#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
4557 +#define NVM_INIT_CONTROL3_PORT_B 0x0014
4558 +#define NVM_INIT_3GIO_3 0x001A
4559 +#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
4560 +#define NVM_INIT_CONTROL3_PORT_A 0x0024
4561 +#define NVM_CFG 0x0012
4562 +#define NVM_FLASH_VERSION 0x0032
4563 +#define NVM_ALT_MAC_ADDR_PTR 0x0037
4564 +#define NVM_CHECKSUM_REG 0x003F
4566 +#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
4567 +#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
4569 +/* Mask bits for fields in Word 0x0f of the NVM */
4570 +#define NVM_WORD0F_PAUSE_MASK 0x3000
4571 +#define NVM_WORD0F_PAUSE 0x1000
4572 +#define NVM_WORD0F_ASM_DIR 0x2000
4573 +#define NVM_WORD0F_ANE 0x0800
4574 +#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
4575 +#define NVM_WORD0F_LPLU 0x0001
4577 +/* Mask bits for fields in Word 0x1a of the NVM */
4578 +#define NVM_WORD1A_ASPM_MASK 0x000C
4580 +/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
4581 +#define NVM_SUM 0xBABA
4583 +#define NVM_MAC_ADDR_OFFSET 0
4584 +#define NVM_PBA_OFFSET_0 8
4585 +#define NVM_PBA_OFFSET_1 9
4586 +#define NVM_RESERVED_WORD 0xFFFF
4587 +#define NVM_PHY_CLASS_A 0x8000
4588 +#define NVM_SERDES_AMPLITUDE_MASK 0x000F
4589 +#define NVM_SIZE_MASK 0x1C00
4590 +#define NVM_SIZE_SHIFT 10
4591 +#define NVM_WORD_SIZE_BASE_SHIFT 6
4592 +#define NVM_SWDPIO_EXT_SHIFT 4
4594 +/* NVM Commands - SPI */
4595 +#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
4596 +#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
4597 +#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
4598 +#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
4599 +#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
4600 +#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
4601 +#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
4602 +#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
4604 +/* SPI NVM Status Register */
4605 +#define NVM_STATUS_RDY_SPI 0x01
4606 +#define NVM_STATUS_WEN_SPI 0x02
4607 +#define NVM_STATUS_BP0_SPI 0x04
4608 +#define NVM_STATUS_BP1_SPI 0x08
4609 +#define NVM_STATUS_WPEN_SPI 0x80
4611 +/* Word definitions for ID LED Settings */
4612 +#define ID_LED_RESERVED_0000 0x0000
4613 +#define ID_LED_RESERVED_FFFF 0xFFFF
4614 +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
4615 + (ID_LED_OFF1_OFF2 << 8) | \
4616 + (ID_LED_DEF1_DEF2 << 4) | \
4617 + (ID_LED_DEF1_DEF2))
4618 +#define ID_LED_DEF1_DEF2 0x1
4619 +#define ID_LED_DEF1_ON2 0x2
4620 +#define ID_LED_DEF1_OFF2 0x3
4621 +#define ID_LED_ON1_DEF2 0x4
4622 +#define ID_LED_ON1_ON2 0x5
4623 +#define ID_LED_ON1_OFF2 0x6
4624 +#define ID_LED_OFF1_DEF2 0x7
4625 +#define ID_LED_OFF1_ON2 0x8
4626 +#define ID_LED_OFF1_OFF2 0x9
4628 +#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
4629 +#define IGP_ACTIVITY_LED_ENABLE 0x0300
4630 +#define IGP_LED3_MODE 0x07000000
4632 +/* PCI/PCI-X/PCI-EX Config space */
4633 +#define PCI_HEADER_TYPE_REGISTER 0x0E
4634 +#define PCIE_LINK_STATUS 0x12
4635 +#define PCIE_DEVICE_CONTROL2 0x28
4637 +#define PCI_HEADER_TYPE_MULTIFUNC 0x80
4638 +#define PCIE_LINK_WIDTH_MASK 0x3F0
4639 +#define PCIE_LINK_WIDTH_SHIFT 4
4640 +#define PCIE_DEVICE_CONTROL2_16ms 0x0005
4642 +#ifndef ETH_ADDR_LEN
4643 +#define ETH_ADDR_LEN 6
4646 +#define PHY_REVISION_MASK 0xFFFFFFF0
4647 +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
4648 +#define MAX_PHY_MULTI_PAGE_REG 0xF
4650 +/* Bit definitions for valid PHY IDs. */
4655 +#define M88E1000_E_PHY_ID 0x01410C50
4656 +#define M88E1000_I_PHY_ID 0x01410C30
4657 +#define M88E1011_I_PHY_ID 0x01410C20
4658 +#define IGP01E1000_I_PHY_ID 0x02A80380
4659 +#define M88E1011_I_REV_4 0x04
4660 +#define M88E1111_I_PHY_ID 0x01410CC0
4661 +#define GG82563_E_PHY_ID 0x01410CA0
4662 +#define IGP03E1000_E_PHY_ID 0x02A80390
4663 +#define IFE_E_PHY_ID 0x02A80330
4664 +#define IFE_PLUS_E_PHY_ID 0x02A80320
4665 +#define IFE_C_E_PHY_ID 0x02A80310
4666 +#define BME1000_E_PHY_ID 0x01410CB0
4667 +#define BME1000_E_PHY_ID_R2 0x01410CB1
4668 +#define I82577_E_PHY_ID 0x01540050
4669 +#define I82578_E_PHY_ID 0x004DD040
4670 +#define M88_VENDOR 0x0141
4672 +/* M88E1000 Specific Registers */
4673 +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
4674 +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
4675 +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
4676 +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
4677 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
4678 +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
4680 +#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
4681 +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
4682 +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
4683 +#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
4684 +#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
4686 +/* M88E1000 PHY Specific Control Register */
4687 +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
4688 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
4689 +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
4690 +/* 1=CLK125 low, 0=CLK125 toggling */
4691 +#define M88E1000_PSCR_CLK125_DISABLE 0x0010
4692 +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
4693 + /* Manual MDI configuration */
4694 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
4695 +/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
4696 +#define M88E1000_PSCR_AUTO_X_1000T 0x0040
4697 +/* Auto crossover enabled all speeds */
4698 +#define M88E1000_PSCR_AUTO_X_MODE 0x0060
4700 + * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
4701 + * 0=Normal 10BASE-T Rx Threshold
4703 +#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
4704 +/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
4705 +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
4706 +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
4707 +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
4708 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
4710 +/* M88E1000 PHY Specific Status Register */
4711 +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
4712 +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
4713 +#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
4714 +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
4722 +#define M88E1000_PSSR_CABLE_LENGTH 0x0380
4723 +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
4724 +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
4725 +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
4726 +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
4727 +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
4728 +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
4729 +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
4730 +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
4732 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
4734 +/* M88E1000 Extended PHY Specific Control Register */
4735 +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
4737 + * 1 = Lost lock detect enabled.
4738 + * Will assert lost lock and bring
4739 + * link down if idle not seen
4740 + * within 1ms in 1000BASE-T
4742 +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
4744 + * Number of times we will attempt to autonegotiate before downshifting if we
4747 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
4748 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
4749 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
4750 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
4751 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
4753 + * Number of times we will attempt to autonegotiate before downshifting if we
4756 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
4757 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
4758 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
4759 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
4760 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
4761 +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
4762 +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
4763 +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
4765 +/* M88EC018 Rev 2 specific DownShift settings */
4766 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
4767 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
4768 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
4769 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
4770 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
4771 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
4772 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
4773 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
4774 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
4776 +#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
4777 +#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
4779 +/* BME1000 PHY Specific Control Register */
4780 +#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
4785 + * 4-0: register offset
4787 +#define GG82563_PAGE_SHIFT 5
4788 +#define GG82563_REG(page, reg) \
4789 + (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
4790 +#define GG82563_MIN_ALT_REG 30
4792 +/* GG82563 Specific Registers */
4793 +#define GG82563_PHY_SPEC_CTRL \
4794 + GG82563_REG(0, 16) /* PHY Specific Control */
4795 +#define GG82563_PHY_SPEC_STATUS \
4796 + GG82563_REG(0, 17) /* PHY Specific Status */
4797 +#define GG82563_PHY_INT_ENABLE \
4798 + GG82563_REG(0, 18) /* Interrupt Enable */
4799 +#define GG82563_PHY_SPEC_STATUS_2 \
4800 + GG82563_REG(0, 19) /* PHY Specific Status 2 */
4801 +#define GG82563_PHY_RX_ERR_CNTR \
4802 + GG82563_REG(0, 21) /* Receive Error Counter */
4803 +#define GG82563_PHY_PAGE_SELECT \
4804 + GG82563_REG(0, 22) /* Page Select */
4805 +#define GG82563_PHY_SPEC_CTRL_2 \
4806 + GG82563_REG(0, 26) /* PHY Specific Control 2 */
4807 +#define GG82563_PHY_PAGE_SELECT_ALT \
4808 + GG82563_REG(0, 29) /* Alternate Page Select */
4809 +#define GG82563_PHY_TEST_CLK_CTRL \
4810 + GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
4812 +#define GG82563_PHY_MAC_SPEC_CTRL \
4813 + GG82563_REG(2, 21) /* MAC Specific Control Register */
4814 +#define GG82563_PHY_MAC_SPEC_CTRL_2 \
4815 + GG82563_REG(2, 26) /* MAC Specific Control 2 */
4817 +#define GG82563_PHY_DSP_DISTANCE \
4818 + GG82563_REG(5, 26) /* DSP Distance */
4820 +/* Page 193 - Port Control Registers */
4821 +#define GG82563_PHY_KMRN_MODE_CTRL \
4822 + GG82563_REG(193, 16) /* Kumeran Mode Control */
4823 +#define GG82563_PHY_PORT_RESET \
4824 + GG82563_REG(193, 17) /* Port Reset */
4825 +#define GG82563_PHY_REVISION_ID \
4826 + GG82563_REG(193, 18) /* Revision ID */
4827 +#define GG82563_PHY_DEVICE_ID \
4828 + GG82563_REG(193, 19) /* Device ID */
4829 +#define GG82563_PHY_PWR_MGMT_CTRL \
4830 + GG82563_REG(193, 20) /* Power Management Control */
4831 +#define GG82563_PHY_RATE_ADAPT_CTRL \
4832 + GG82563_REG(193, 25) /* Rate Adaptation Control */
4834 +/* Page 194 - KMRN Registers */
4835 +#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
4836 + GG82563_REG(194, 16) /* FIFO's Control/Status */
4837 +#define GG82563_PHY_KMRN_CTRL \
4838 + GG82563_REG(194, 17) /* Control */
4839 +#define GG82563_PHY_INBAND_CTRL \
4840 + GG82563_REG(194, 18) /* Inband Control */
4841 +#define GG82563_PHY_KMRN_DIAGNOSTIC \
4842 + GG82563_REG(194, 19) /* Diagnostic */
4843 +#define GG82563_PHY_ACK_TIMEOUTS \
4844 + GG82563_REG(194, 20) /* Acknowledge Timeouts */
4845 +#define GG82563_PHY_ADV_ABILITY \
4846 + GG82563_REG(194, 21) /* Advertised Ability */
4847 +#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
4848 + GG82563_REG(194, 23) /* Link Partner Advertised Ability */
4849 +#define GG82563_PHY_ADV_NEXT_PAGE \
4850 + GG82563_REG(194, 24) /* Advertised Next Page */
4851 +#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
4852 + GG82563_REG(194, 25) /* Link Partner Advertised Next page */
4853 +#define GG82563_PHY_KMRN_MISC \
4854 + GG82563_REG(194, 26) /* Misc. */
4857 +#define E1000_MDIC_DATA_MASK 0x0000FFFF
4858 +#define E1000_MDIC_REG_MASK 0x001F0000
4859 +#define E1000_MDIC_REG_SHIFT 16
4860 +#define E1000_MDIC_PHY_MASK 0x03E00000
4861 +#define E1000_MDIC_PHY_SHIFT 21
4862 +#define E1000_MDIC_OP_WRITE 0x04000000
4863 +#define E1000_MDIC_OP_READ 0x08000000
4864 +#define E1000_MDIC_READY 0x10000000
4865 +#define E1000_MDIC_INT_EN 0x20000000
4866 +#define E1000_MDIC_ERROR 0x40000000
4868 +/* SerDes Control */
4869 +#define E1000_GEN_CTL_READY 0x80000000
4870 +#define E1000_GEN_CTL_ADDRESS_SHIFT 8
4871 +#define E1000_GEN_POLL_TIMEOUT 640
4875 +#endif /* _E1000_DEFINES_H_ */
4876 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000.h linux-2.6.22-10/drivers/net/e1000e/e1000.h
4877 --- linux-2.6.22-0/drivers/net/e1000e/e1000.h 1970-01-01 01:00:00.000000000 +0100
4878 +++ linux-2.6.22-10/drivers/net/e1000e/e1000.h 2009-06-24 00:32:20.000000000 +0200
4880 +/*******************************************************************************
4882 + Intel PRO/1000 Linux driver
4883 + Copyright(c) 1999 - 2009 Intel Corporation.
4885 + This program is free software; you can redistribute it and/or modify it
4886 + under the terms and conditions of the GNU General Public License,
4887 + version 2, as published by the Free Software Foundation.
4889 + This program is distributed in the hope it will be useful, but WITHOUT
4890 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4891 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4894 + You should have received a copy of the GNU General Public License along with
4895 + this program; if not, write to the Free Software Foundation, Inc.,
4896 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4898 + The full GNU General Public License is included in this distribution in
4899 + the file called "COPYING".
4901 + Contact Information:
4902 + Linux NICS <linux.nics@intel.com>
4903 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
4904 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
4906 +*******************************************************************************/
4908 +/* Linux PRO/1000 Ethernet Driver main header file */
4913 +#include <linux/types.h>
4914 +#include <asm/io.h>
4915 +#include <linux/netdevice.h>
4916 +#include <linux/pci.h>
4918 +#include "kcompat.h"
4923 +#define e_printk(level, adapter, format, arg...) \
4924 + printk(level "%s: %s: " format, pci_name(adapter->pdev), \
4925 + (strchr(adapter->netdev->name, '%') ? "" : \
4926 + adapter->netdev->name), ## arg)
4929 +#define e_dbg(format, arg...) \
4930 + e_printk(KERN_DEBUG, hw->adapter, format, ## arg)
4932 +#define e_dbg(format, arg...) do { (void)(hw); } while (0)
4935 +#define e_err(format, arg...) \
4936 + e_printk(KERN_ERR, adapter, format, ## arg)
4937 +#define e_info(format, arg...) \
4938 + e_printk(KERN_INFO, adapter, format, ## arg)
4939 +#define e_warn(format, arg...) \
4940 + e_printk(KERN_WARNING, adapter, format, ## arg)
4941 +#define e_notice(format, arg...) \
4942 + e_printk(KERN_NOTICE, adapter, format, ## arg)
4945 +#ifdef CONFIG_E1000E_MSIX
4946 +/* Interrupt modes, as used by the IntMode paramter */
4947 +#define E1000E_INT_MODE_LEGACY 0
4948 +#define E1000E_INT_MODE_MSI 1
4949 +#define E1000E_INT_MODE_MSIX 2
4951 +#endif /* CONFIG_E1000E_MSIX */
4952 +#ifndef CONFIG_E1000E_NAPI
4953 +#define E1000_MAX_INTR 10
4955 +#endif /* CONFIG_E1000E_NAPI */
4956 +/* Tx/Rx descriptor defines */
4957 +#define E1000_DEFAULT_TXD 256
4958 +#define E1000_MAX_TXD 4096
4959 +#define E1000_MIN_TXD 64
4961 +#define E1000_DEFAULT_RXD 256
4962 +#define E1000_MAX_RXD 4096
4963 +#define E1000_MIN_RXD 64
4965 +#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
4966 +#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
4968 +/* Early Receive defines */
4969 +#define E1000_ERT_2048 0x100
4971 +#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
4973 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
4974 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
4975 +#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
4977 +#define AUTO_ALL_MODES 0
4978 +#define E1000_EEPROM_APME 0x0400
4980 +#define E1000_MNG_VLAN_NONE (-1)
4982 +/* Number of packet split data buffers (not including the header buffer) */
4983 +#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
4985 +#define DEFAULT_JUMBO 9234
4987 +enum e1000_boards {
4992 + board_80003es2lan,
5000 +struct e1000_queue_stats {
5005 +struct e1000_ps_page {
5006 + struct page *page;
5007 + u64 dma; /* must be u64 - written to hw */
5011 + * wrappers around a pointer to a socket buffer,
5012 + * so a DMA handle can be stored along with the buffer
5014 +struct e1000_buffer {
5016 + struct sk_buff *skb;
5020 + unsigned long time_stamp;
5022 + u16 next_to_watch;
5025 + /* arrays of page information for packet split */
5026 + struct e1000_ps_page *ps_pages;
5028 + struct page *page;
5031 +struct e1000_ring {
5032 + void *desc; /* pointer to ring memory */
5033 + dma_addr_t dma; /* phys address of ring */
5034 + unsigned int size; /* length of ring in bytes */
5035 + unsigned int count; /* number of desc. in ring */
5038 + u16 next_to_clean;
5043 + /* array of buffer information structs */
5044 + struct e1000_buffer *buffer_info;
5046 +#ifdef CONFIG_E1000E_MSIX
5047 + char name[IFNAMSIZ + 5];
5053 +#endif /* CONFIG_E1000E_MSIX */
5054 + struct sk_buff *rx_skb_top;
5056 + struct e1000_queue_stats stats;
5060 +/* PHY register snapshot values */
5061 +struct e1000_phy_regs {
5062 + u16 bmcr; /* basic mode control register */
5063 + u16 bmsr; /* basic mode status register */
5064 + u16 advertise; /* auto-negotiation advertisement */
5065 + u16 lpa; /* link partner ability register */
5066 + u16 expansion; /* auto-negotiation expansion reg */
5067 + u16 ctrl1000; /* 1000BASE-T control register */
5068 + u16 stat1000; /* 1000BASE-T status register */
5069 + u16 estatus; /* extended status register */
5073 +/* board specific private data structure */
5074 +struct e1000_adapter {
5075 + struct timer_list watchdog_timer;
5076 + struct timer_list phy_info_timer;
5077 + struct timer_list blink_timer;
5079 + struct work_struct reset_task;
5080 + struct work_struct watchdog_task;
5082 + const struct e1000_info *ei;
5084 + struct vlan_group *vlgrp;
5086 + u32 rx_buffer_len;
5092 + /* track device up/down/testing state */
5093 + unsigned long state;
5095 + /* Interrupt Throttle Rate */
5104 + struct e1000_ring *tx_ring /* One per active queue */
5105 + ____cacheline_aligned_in_smp;
5107 +#ifdef CONFIG_E1000E_NAPI
5108 + struct napi_struct napi;
5111 + unsigned long tx_queue_len;
5112 + unsigned int restart_queue;
5115 + bool detect_tx_hung;
5116 + u8 tx_timeout_factor;
5119 + u32 tx_abs_int_delay;
5121 + unsigned int total_tx_bytes;
5122 + unsigned int total_tx_packets;
5123 + unsigned int total_rx_bytes;
5124 + unsigned int total_rx_packets;
5131 + u32 tx_timeout_count;
5135 + u32 tx_dma_failed;
5140 +#ifdef CONFIG_E1000E_NAPI
5141 + bool (*clean_rx) (struct e1000_adapter *adapter,
5142 + int *work_done, int work_to_do)
5143 + ____cacheline_aligned_in_smp;
5145 + bool (*clean_rx) (struct e1000_adapter *adapter)
5146 + ____cacheline_aligned_in_smp;
5148 + void (*alloc_rx_buf) (struct e1000_adapter *adapter,
5149 + int cleaned_count);
5150 + struct e1000_ring *rx_ring;
5153 + u32 rx_abs_int_delay;
5161 + u32 alloc_rx_buff_failed;
5162 + u32 rx_dma_failed;
5164 + unsigned int rx_ps_pages;
5166 +#ifndef CONFIG_E1000E_NAPI
5167 + u64 rx_dropped_backlog; /* count drops from rx int handler */
5169 + u32 max_frame_size;
5170 + u32 min_frame_size;
5172 + /* OS defined structs */
5173 + struct net_device *netdev;
5174 + struct pci_dev *pdev;
5175 + struct net_device_stats net_stats;
5177 + /* structs defined in e1000_hw.h */
5178 + struct e1000_hw hw;
5180 + struct e1000_hw_stats stats;
5181 + struct e1000_phy_info phy_info;
5182 + struct e1000_phy_stats phy_stats;
5185 + /* Snapshot of PHY registers */
5186 + struct e1000_phy_regs phy_regs;
5189 + struct e1000_ring test_tx_ring;
5190 + struct e1000_ring test_rx_ring;
5194 +#ifdef CONFIG_E1000E_MSIX
5195 + struct msix_entry *msix_entries;
5198 +#endif /* CONFIG_E1000E_MSIX */
5203 + u32 max_hw_frame_size;
5207 + unsigned long led_status;
5209 + unsigned int flags;
5210 + unsigned int flags2;
5211 + struct work_struct downshift_task;
5212 + struct work_struct update_phy_task;
5213 + struct work_struct led_blink_task;
5214 + u32 *config_space;
5217 +struct e1000_info {
5218 + enum e1000_mac_type mac;
5219 + unsigned int flags;
5220 + unsigned int flags2;
5222 + u32 max_hw_frame_size;
5223 + s32 (*get_variants)(struct e1000_adapter *);
5224 + void (*init_ops)(struct e1000_hw *);
5227 +/* hardware capability, feature, and workaround flags */
5228 +#define FLAG_HAS_AMT (1 << 0)
5229 +#define FLAG_HAS_FLASH (1 << 1)
5230 +#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
5231 +#define FLAG_HAS_WOL (1 << 3)
5232 +#define FLAG_HAS_ERT (1 << 4)
5233 +#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
5234 +#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
5235 +#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
5236 +#define FLAG_IS_ICH (1 << 9)
5237 +#ifdef CONFIG_E1000E_MSIX
5238 +#define FLAG_HAS_MSIX (1 << 10)
5240 +#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
5241 +#define FLAG_IS_QUAD_PORT_A (1 << 12)
5242 +#define FLAG_IS_QUAD_PORT (1 << 13)
5243 +#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
5244 +#define FLAG_APME_IN_WUC (1 << 15)
5245 +#define FLAG_APME_IN_CTRL3 (1 << 16)
5246 +#define FLAG_APME_CHECK_PORT_B (1 << 17)
5247 +#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
5248 +#define FLAG_NO_WAKE_UCAST (1 << 19)
5249 +#define FLAG_MNG_PT_ENABLED (1 << 20)
5250 +#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
5251 +#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
5252 +#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
5253 +#define FLAG_RX_NEEDS_RESTART (1 << 24)
5254 +#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
5255 +#define FLAG_SMART_POWER_DOWN (1 << 26)
5256 +#define FLAG_MSI_ENABLED (1 << 27)
5257 +#define FLAG_RX_CSUM_ENABLED (1 << 28)
5258 +#define FLAG_TSO_FORCE (1 << 29)
5259 +#define FLAG_RX_RESTART_NOW (1 << 30)
5260 +#define FLAG_MSI_TEST_FAILED (1 << 31)
5262 +/* CRC Stripping defines */
5263 +#define FLAG2_CRC_STRIPPING (1 << 0)
5264 +#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
5266 +#define E1000_RX_DESC_PS(R, i) \
5267 + (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
5268 +#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
5269 +#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
5270 +#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
5271 +#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
5273 +enum e1000_state_t {
5275 + __E1000_RESETTING,
5279 +enum latency_range {
5280 + lowest_latency = 0,
5283 + latency_invalid = 255
5286 +extern char e1000e_driver_name[];
5287 +extern const char e1000e_driver_version[];
5289 +extern void e1000e_check_options(struct e1000_adapter *adapter);
5290 +extern void e1000e_set_ethtool_ops(struct net_device *netdev);
5291 +#ifdef ETHTOOL_OPS_COMPAT
5292 +extern int ethtool_ioctl(struct ifreq *ifr);
5295 +extern int e1000e_up(struct e1000_adapter *adapter);
5296 +extern void e1000e_down(struct e1000_adapter *adapter);
5297 +extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
5298 +extern void e1000e_reset(struct e1000_adapter *adapter);
5299 +extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
5300 +extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
5301 +extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
5302 +extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
5303 +extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
5304 +extern void e1000e_update_stats(struct e1000_adapter *adapter);
5305 +extern bool e1000_has_link(struct e1000_adapter *adapter);
5306 +#ifdef CONFIG_E1000E_MSIX
5307 +extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
5308 +extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
5311 +extern unsigned int copybreak;
5313 +extern void e1000_init_function_pointers_82571(struct e1000_hw *hw);
5314 +extern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
5315 +extern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
5317 +extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
5319 +static inline s32 e1000e_commit_phy(struct e1000_hw *hw)
5321 + if (hw->phy.ops.commit)
5322 + return hw->phy.ops.commit(hw);
5327 +extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
5329 +extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
5330 +extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
5332 +extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5334 +extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
5335 +extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
5336 +extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
5338 +extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
5339 +extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
5340 +extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
5341 +extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
5342 +extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
5343 +extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
5344 +extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
5345 +extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
5346 +extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
5347 +extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
5348 +extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
5349 +extern s32 e1000e_id_led_init(struct e1000_hw *hw);
5350 +extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
5351 +extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
5352 +extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
5353 +extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
5354 +extern s32 e1000e_setup_link(struct e1000_hw *hw);
5355 +static inline void e1000e_clear_vfta(struct e1000_hw *hw)
5357 + hw->mac.ops.clear_vfta(hw);
5359 +extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
5360 +extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
5362 + u32 mc_addr_count);
5363 +extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
5364 +extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
5365 +extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
5366 +extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
5367 +extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
5368 +extern void e1000e_config_collision_dist(struct e1000_hw *hw);
5369 +extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
5370 +extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
5371 +extern s32 e1000e_blink_led(struct e1000_hw *hw);
5372 +extern void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
5373 +static inline void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5375 + if (hw->mac.ops.write_vfta)
5376 + hw->mac.ops.write_vfta(hw, offset, value);
5378 +extern void e1000e_reset_adaptive(struct e1000_hw *hw);
5379 +extern void e1000e_update_adaptive(struct e1000_hw *hw);
5381 +extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
5382 +extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
5383 +extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
5384 +extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
5385 +extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
5386 +extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
5387 +extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5388 +extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
5389 +extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
5390 +extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5391 +extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
5392 +extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
5393 +extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
5394 +extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
5395 +extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
5396 +extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
5397 +extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
5398 +extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
5399 +extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
5400 +extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
5401 +extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
5402 +extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
5403 +extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5404 +extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5405 +extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
5406 + u32 usec_interval, bool *success);
5407 +extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
5408 +extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
5409 +extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
5410 +extern s32 e1000e_check_downshift(struct e1000_hw *hw);
5412 +static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
5414 + if (hw->phy.ops.reset)
5415 + return hw->phy.ops.reset(hw);
5420 +static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
5422 + if (hw->phy.ops.check_reset_block)
5423 + return hw->phy.ops.check_reset_block(hw);
5428 +static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
5430 + if (hw->phy.ops.read_reg)
5431 + return hw->phy.ops.read_reg(hw, offset, data);
5436 +static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
5438 + if (hw->phy.ops.write_reg)
5439 + return hw->phy.ops.write_reg(hw, offset, data);
5444 +static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
5446 + if (hw->phy.ops.get_cable_length)
5447 + return hw->phy.ops.get_cable_length(hw);
5452 +extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
5453 +extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
5454 +extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
5455 +extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
5456 +extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
5457 +extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
5458 +extern void e1000e_release_nvm(struct e1000_hw *hw);
5460 +static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
5462 + if (hw->mac.ops.read_mac_addr)
5463 + return hw->mac.ops.read_mac_addr(hw);
5465 + return e1000e_read_mac_addr_generic(hw);
5468 +static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
5470 + return hw->nvm.ops.validate(hw);
5473 +static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
5475 + return hw->nvm.ops.update(hw);
5478 +static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5480 + return hw->nvm.ops.read(hw, offset, words, data);
5483 +static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5485 + return hw->nvm.ops.write(hw, offset, words, data);
5488 +static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
5490 + if (hw->phy.ops.get_info)
5491 + return hw->phy.ops.get_info(hw);
5496 +extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
5497 +extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
5499 +static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
5501 + return readl(hw->hw_addr + reg);
5504 +static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
5506 + writel(val, hw->hw_addr + reg);
5509 +#define er32(reg) __er32(hw, E1000_##reg)
5510 +#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
5511 +#define e1e_flush() er32(STATUS)
5513 +#define E1000_WRITE_REG(a, reg, value) ( \
5514 + writel((value), ((a)->hw_addr + reg)))
5516 +#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
5518 +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
5519 + writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
5521 +#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
5522 + readl((a)->hw_addr + reg + ((offset) << 2)))
5524 +#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
5525 +#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
5527 +static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
5529 + return readw(hw->flash_address + reg);
5532 +static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
5534 + return readl(hw->flash_address + reg);
5537 +static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
5539 + writew(val, hw->flash_address + reg);
5542 +static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
5544 + writel(val, hw->flash_address + reg);
5547 +#define er16flash(reg) __er16flash(hw, (reg))
5548 +#define er32flash(reg) __er32flash(hw, (reg))
5549 +#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
5550 +#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
5552 +#endif /* _E1000_H_ */
5553 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.c linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.c
5554 --- linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.c 1970-01-01 01:00:00.000000000 +0100
5555 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.c 2009-06-24 00:32:20.000000000 +0200
5557 +/*******************************************************************************
5559 + Intel PRO/1000 Linux driver
5560 + Copyright(c) 1999 - 2009 Intel Corporation.
5562 + This program is free software; you can redistribute it and/or modify it
5563 + under the terms and conditions of the GNU General Public License,
5564 + version 2, as published by the Free Software Foundation.
5566 + This program is distributed in the hope it will be useful, but WITHOUT
5567 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5568 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5571 + You should have received a copy of the GNU General Public License along with
5572 + this program; if not, write to the Free Software Foundation, Inc.,
5573 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
5575 + The full GNU General Public License is included in this distribution in
5576 + the file called "COPYING".
5578 + Contact Information:
5579 + Linux NICS <linux.nics@intel.com>
5580 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
5581 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
5583 +*******************************************************************************/
5586 + * 82562G 10/100 Network Connection
5587 + * 82562G-2 10/100 Network Connection
5588 + * 82562GT 10/100 Network Connection
5589 + * 82562GT-2 10/100 Network Connection
5590 + * 82562V 10/100 Network Connection
5591 + * 82562V-2 10/100 Network Connection
5592 + * 82566DC-2 Gigabit Network Connection
5593 + * 82566DC Gigabit Network Connection
5594 + * 82566DM-2 Gigabit Network Connection
5595 + * 82566DM Gigabit Network Connection
5596 + * 82566MC Gigabit Network Connection
5597 + * 82566MM Gigabit Network Connection
5598 + * 82567LM Gigabit Network Connection
5599 + * 82567LF Gigabit Network Connection
5600 + * 82567V Gigabit Network Connection
5601 + * 82567LM-2 Gigabit Network Connection
5602 + * 82567LF-2 Gigabit Network Connection
5603 + * 82567V-2 Gigabit Network Connection
5604 + * 82567LF-3 Gigabit Network Connection
5605 + * 82567LM-3 Gigabit Network Connection
5606 + * 82567LM-4 Gigabit Network Connection
5607 + * 82577LM Gigabit Network Connection
5608 + * 82577LC Gigabit Network Connection
5609 + * 82578DM Gigabit Network Connection
5610 + * 82578DC Gigabit Network Connection
5615 +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
5616 +static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
5617 +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
5618 +static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
5619 +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
5620 +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
5621 +static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
5622 +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
5623 +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
5624 +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
5625 +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
5627 +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
5629 +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
5630 + u16 words, u16 *data);
5631 +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
5632 + u16 words, u16 *data);
5633 +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
5634 +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
5635 +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
5637 +static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
5638 +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
5639 +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
5640 +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
5641 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
5642 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
5643 +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
5644 + u16 *speed, u16 *duplex);
5645 +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
5646 +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
5647 +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
5648 +static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
5649 +static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
5650 +static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
5651 +static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
5652 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
5653 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
5654 +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
5655 +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
5656 +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
5657 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
5658 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
5659 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
5660 + u32 offset, u8 *data);
5661 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
5662 + u8 size, u16 *data);
5663 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
5664 + u32 offset, u16 *data);
5665 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
5666 + u32 offset, u8 byte);
5667 +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
5668 + u32 offset, u8 data);
5669 +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
5670 + u8 size, u16 data);
5671 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
5672 +static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
5673 +static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
5675 +/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
5676 +/* Offset 04h HSFSTS */
5677 +union ich8_hws_flash_status {
5678 + struct ich8_hsfsts {
5679 + u16 flcdone :1; /* bit 0 Flash Cycle Done */
5680 + u16 flcerr :1; /* bit 1 Flash Cycle Error */
5681 + u16 dael :1; /* bit 2 Direct Access error Log */
5682 + u16 berasesz :2; /* bit 4:3 Sector Erase Size */
5683 + u16 flcinprog :1; /* bit 5 flash cycle in Progress */
5684 + u16 reserved1 :2; /* bit 13:6 Reserved */
5685 + u16 reserved2 :6; /* bit 13:6 Reserved */
5686 + u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
5687 + u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
5692 +/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
5693 +/* Offset 06h FLCTL */
5694 +union ich8_hws_flash_ctrl {
5695 + struct ich8_hsflctl {
5696 + u16 flcgo :1; /* 0 Flash Cycle Go */
5697 + u16 flcycle :2; /* 2:1 Flash Cycle */
5698 + u16 reserved :5; /* 7:3 Reserved */
5699 + u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
5700 + u16 flockdn :6; /* 15:10 Reserved */
5705 +/* ICH Flash Region Access Permissions */
5706 +union ich8_hws_flash_regacc {
5707 + struct ich8_flracc {
5708 + u32 grra :8; /* 0:7 GbE region Read Access */
5709 + u32 grwa :8; /* 8:15 GbE region Write Access */
5710 + u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
5711 + u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
5717 + * e1000_init_phy_params_pchlan - Initialize PHY function pointers
5718 + * @hw: pointer to the HW structure
5720 + * Initialize family-specific PHY parameters and function pointers.
5722 +static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
5724 + struct e1000_phy_info *phy = &hw->phy;
5725 + s32 ret_val = E1000_SUCCESS;
5728 + phy->reset_delay_us = 100;
5730 + phy->ops.acquire = e1000_acquire_swflag_ich8lan;
5731 + phy->ops.check_polarity = e1000_check_polarity_ife;
5732 + phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
5733 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
5734 + phy->ops.get_cable_length = e1000e_get_cable_length_igp_2;
5735 + phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
5736 + phy->ops.get_info = e1000_get_phy_info_ich8lan;
5737 + phy->ops.read_reg = e1000_read_phy_reg_hv;
5738 + phy->ops.release = e1000_release_swflag_ich8lan;
5739 + phy->ops.reset = e1000_phy_hw_reset_ich8lan;
5740 + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
5741 + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
5742 + phy->ops.write_reg = e1000_write_phy_reg_hv;
5743 + phy->ops.power_up = e1000_power_up_phy_copper;
5744 + phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
5745 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
5747 + phy->id = e1000_phy_unknown;
5748 + e1000e_get_phy_id(hw);
5749 + phy->type = e1000e_get_phy_type_from_id(phy->id);
5751 + if (phy->type == e1000_phy_82577) {
5752 + phy->ops.check_polarity = e1000_check_polarity_82577;
5753 + phy->ops.force_speed_duplex =
5754 + e1000_phy_force_speed_duplex_82577;
5755 + phy->ops.get_cable_length = e1000_get_cable_length_82577;
5756 + phy->ops.get_info = e1000_get_phy_info_82577;
5757 + phy->ops.commit = e1000e_phy_sw_reset;
5764 + * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
5765 + * @hw: pointer to the HW structure
5767 + * Initialize family-specific PHY parameters and function pointers.
5769 +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
5771 + struct e1000_phy_info *phy = &hw->phy;
5772 + s32 ret_val = E1000_SUCCESS;
5776 + phy->reset_delay_us = 100;
5778 + phy->ops.acquire = e1000_acquire_swflag_ich8lan;
5779 + phy->ops.check_polarity = e1000_check_polarity_ife;
5780 + phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
5781 + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
5782 + phy->ops.get_cable_length = e1000e_get_cable_length_igp_2;
5783 + phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
5784 + phy->ops.get_info = e1000_get_phy_info_ich8lan;
5785 + phy->ops.read_reg = e1000e_read_phy_reg_igp;
5786 + phy->ops.release = e1000_release_swflag_ich8lan;
5787 + phy->ops.reset = e1000_phy_hw_reset_ich8lan;
5788 + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
5789 + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
5790 + phy->ops.write_reg = e1000e_write_phy_reg_igp;
5791 + phy->ops.power_up = e1000_power_up_phy_copper;
5792 + phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
5795 + * We may need to do this twice - once for IGP and if that fails,
5796 + * we'll set BM func pointers and try again
5798 + ret_val = e1000e_determine_phy_address(hw);
5800 + phy->ops.write_reg = e1000e_write_phy_reg_bm;
5801 + phy->ops.read_reg = e1000e_read_phy_reg_bm;
5802 + ret_val = e1000e_determine_phy_address(hw);
5804 + e_dbg("Cannot determine PHY addr. Erroring out\n");
5810 + while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
5813 + ret_val = e1000e_get_phy_id(hw);
5818 + /* Verify phy id */
5819 + switch (phy->id) {
5820 + case IGP03E1000_E_PHY_ID:
5821 + phy->type = e1000_phy_igp_3;
5822 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
5824 + case IFE_E_PHY_ID:
5825 + case IFE_PLUS_E_PHY_ID:
5826 + case IFE_C_E_PHY_ID:
5827 + phy->type = e1000_phy_ife;
5828 + phy->autoneg_mask = E1000_ALL_NOT_GIG;
5830 + case BME1000_E_PHY_ID:
5831 + phy->type = e1000_phy_bm;
5832 + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
5833 + phy->ops.read_reg = e1000e_read_phy_reg_bm;
5834 + phy->ops.write_reg = e1000e_write_phy_reg_bm;
5835 + phy->ops.commit = e1000e_phy_sw_reset;
5838 + ret_val = -E1000_ERR_PHY;
5847 + * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
5848 + * @hw: pointer to the HW structure
5850 + * Initialize family-specific NVM parameters and function
5853 +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
5855 + struct e1000_nvm_info *nvm = &hw->nvm;
5856 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5857 + union ich8_hws_flash_status hsfsts;
5858 + u32 gfpreg, sector_base_addr, sector_end_addr;
5859 + s32 ret_val = E1000_SUCCESS;
5862 + /* Can't read flash registers if the register set isn't mapped. */
5863 + if (!hw->flash_address) {
5864 + e_dbg("ERROR: Flash registers not mapped\n");
5865 + ret_val = -E1000_ERR_CONFIG;
5869 + nvm->type = e1000_nvm_flash_sw;
5871 + gfpreg = er32flash(ICH_FLASH_GFPREG);
5874 + * sector_X_addr is a "sector"-aligned address (4096 bytes)
5875 + * Add 1 to sector_end_addr since this sector is included in
5876 + * the overall size.
5878 + sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
5879 + sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
5881 + /* flash_base_addr is byte-aligned */
5882 + nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
5885 + * find total size of the NVM, then cut in half since the total
5886 + * size represents two separate NVM banks.
5888 + nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
5889 + << FLASH_SECTOR_ADDR_SHIFT;
5890 + nvm->flash_bank_size /= 2;
5891 + /* Adjust to word count */
5892 + nvm->flash_bank_size /= sizeof(u16);
5895 + * Make sure the flash bank size does not overwrite the 4k
5896 + * sector ranges. We may have 64k allotted to us but we only care
5897 + * about the first 2 4k sectors. Therefore, if we have anything less
5898 + * than 64k set in the HSFSTS register, we will reduce the bank size
5899 + * down to 4k and let the rest remain unused. If berasesz == 3, then
5900 + * we are working in 64k mode. Otherwise we are not.
5902 + if (nvm->flash_bank_size > E1000_ICH8_SHADOW_RAM_WORDS) {
5903 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
5904 + if (hsfsts.hsf_status.berasesz != 3)
5905 + nvm->flash_bank_size = E1000_ICH8_SHADOW_RAM_WORDS;
5908 + nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
5910 + /* Clear shadow ram */
5911 + for (i = 0; i < nvm->word_size; i++) {
5912 + dev_spec->shadow_ram[i].modified = false;
5913 + dev_spec->shadow_ram[i].value = 0xFFFF;
5916 + /* Function Pointers */
5917 + nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
5918 + nvm->ops.read = e1000_read_nvm_ich8lan;
5919 + nvm->ops.release = e1000_release_swflag_ich8lan;
5920 + nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
5921 + nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
5922 + nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
5923 + nvm->ops.write = e1000_write_nvm_ich8lan;
5930 + * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
5931 + * @hw: pointer to the HW structure
5933 + * Initialize family-specific MAC parameters and function
5936 +static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
5938 + struct e1000_mac_info *mac = &hw->mac;
5940 + /* Set media type function pointer */
5941 + hw->phy.media_type = e1000_media_type_copper;
5943 + /* Set mta register count */
5944 + mac->mta_reg_count = 32;
5945 + /* Set rar entry count */
5946 + mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
5947 + if (mac->type == e1000_ich8lan)
5948 + mac->rar_entry_count--;
5949 + /* Set if part includes ASF firmware */
5950 + mac->asf_firmware_present = true;
5951 + /* Set if manageability features are enabled. */
5952 + mac->arc_subsystem_valid = true;
5954 + /* Function pointers */
5956 + /* bus type/speed/width */
5957 + mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
5959 + mac->ops.set_lan_id = e1000_set_lan_id_single_port;
5961 + mac->ops.reset_hw = e1000_reset_hw_ich8lan;
5962 + /* hw initialization */
5963 + mac->ops.init_hw = e1000_init_hw_ich8lan;
5965 + mac->ops.setup_link = e1000_setup_link_ich8lan;
5966 + /* physical interface setup */
5967 + mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
5968 + /* check for link */
5969 + mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
5970 + /* check management mode */
5971 + mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
5973 + mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
5974 + /* multicast address update */
5975 + mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
5977 + mac->ops.mta_set = e1000_mta_set_generic;
5978 + /* clear hardware counters */
5979 + mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
5981 + /* LED operations */
5982 + switch (mac->type) {
5983 + case e1000_ich8lan:
5984 + case e1000_ich9lan:
5985 + case e1000_ich10lan:
5987 + mac->ops.id_led_init = e1000e_id_led_init;
5989 + mac->ops.blink_led = e1000e_blink_led;
5991 + mac->ops.setup_led = e1000_setup_led_generic;
5993 + mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
5994 + /* turn on/off LED */
5995 + mac->ops.led_on = e1000_led_on_ich8lan;
5996 + mac->ops.led_off = e1000_led_off_ich8lan;
5998 + case e1000_pchlan:
6000 + mac->ops.id_led_init = e1000_id_led_init_pchlan;
6002 + mac->ops.setup_led = e1000_setup_led_pchlan;
6004 + mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
6005 + /* turn on/off LED */
6006 + mac->ops.led_on = e1000_led_on_pchlan;
6007 + mac->ops.led_off = e1000_led_off_pchlan;
6013 + /* Enable PCS Lock-loss workaround for ICH8 */
6014 + if (mac->type == e1000_ich8lan)
6015 + e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
6018 + return E1000_SUCCESS;
6022 + * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
6023 + * @hw: pointer to the HW structure
6025 + * Checks to see of the link status of the hardware has changed. If a
6026 + * change in link status has been detected, then we read the PHY registers
6027 + * to get the current speed/duplex if link exists.
6029 +static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
6031 + struct e1000_mac_info *mac = &hw->mac;
6036 + * We only want to go out to the PHY registers to see if Auto-Neg
6037 + * has completed and/or if our link status has changed. The
6038 + * get_link_status flag is set upon receiving a Link Status
6039 + * Change or Rx Sequence Error interrupt.
6041 + if (!mac->get_link_status) {
6042 + ret_val = E1000_SUCCESS;
6046 + if (hw->mac.type == e1000_pchlan) {
6047 + ret_val = e1000e_write_kmrn_reg(hw,
6048 + E1000_KMRNCTRLSTA_K1_CONFIG,
6049 + E1000_KMRNCTRLSTA_K1_ENABLE);
6055 + * First we want to see if the MII Status Register reports
6056 + * link. If so, then we want to get the current speed/duplex
6059 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
6064 + goto out; /* No link detected */
6066 + mac->get_link_status = false;
6068 + if (hw->phy.type == e1000_phy_82578) {
6069 + ret_val = e1000_link_stall_workaround_hv(hw);
6075 + * Check if there was DownShift, must be checked
6076 + * immediately after link-up
6078 + e1000e_check_downshift(hw);
6081 + * If we are forcing speed/duplex, then we simply return since
6082 + * we have already determined whether we have link or not.
6084 + if (!mac->autoneg) {
6085 + ret_val = -E1000_ERR_CONFIG;
6090 + * Auto-Neg is enabled. Auto Speed Detection takes care
6091 + * of MAC speed/duplex configuration. So we only need to
6092 + * configure Collision Distance in the MAC.
6094 + e1000e_config_collision_dist(hw);
6097 + * Configure Flow Control now that Auto-Neg has completed.
6098 + * First, we need to restore the desired flow control
6099 + * settings because we may have had to re-autoneg with a
6100 + * different link partner.
6102 + ret_val = e1000e_config_fc_after_link_up(hw);
6104 + e_dbg("Error configuring flow control\n");
6111 + * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
6112 + * @hw: pointer to the HW structure
6114 + * Initialize family-specific function pointers for PHY, MAC, and NVM.
6116 +void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
6118 + e1000_init_mac_ops_generic(hw);
6119 + e1000_init_nvm_ops_generic(hw);
6120 + hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
6121 + hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
6122 + switch (hw->mac.type) {
6123 + case e1000_ich8lan:
6124 + case e1000_ich9lan:
6125 + case e1000_ich10lan:
6126 + hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
6128 + case e1000_pchlan:
6129 + hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
6136 +static DEFINE_MUTEX(nvm_mutex);
6139 + * e1000_acquire_swflag_ich8lan - Acquire software control flag
6140 + * @hw: pointer to the HW structure
6142 + * Acquires the software control flag for performing NVM and PHY
6143 + * operations. This is a function pointer entry point only called by
6144 + * read/write routines for the PHY and NVM parts.
6146 +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
6148 + u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
6149 + s32 ret_val = E1000_SUCCESS;
6153 + mutex_lock(&nvm_mutex);
6156 + extcnf_ctrl = er32(EXTCNF_CTRL);
6158 + if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
6159 + extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
6160 + ew32(EXTCNF_CTRL, extcnf_ctrl);
6162 + extcnf_ctrl = er32(EXTCNF_CTRL);
6163 + if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
6171 + e_dbg("SW/FW/HW has locked the resource for too long.\n");
6172 + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
6173 + ew32(EXTCNF_CTRL, extcnf_ctrl);
6174 + mutex_unlock(&nvm_mutex);
6175 + ret_val = -E1000_ERR_CONFIG;
6184 + * e1000_release_swflag_ich8lan - Release software control flag
6185 + * @hw: pointer to the HW structure
6187 + * Releases the software control flag for performing NVM and PHY operations.
6188 + * This is a function pointer entry point only called by read/write
6189 + * routines for the PHY and NVM parts.
6191 +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
6195 + extcnf_ctrl = er32(EXTCNF_CTRL);
6196 + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
6197 + ew32(EXTCNF_CTRL, extcnf_ctrl);
6199 + mutex_unlock(&nvm_mutex);
6203 + * e1000_check_mng_mode_ich8lan - Checks management mode
6204 + * @hw: pointer to the HW structure
6206 + * This checks if the adapter has manageability enabled.
6207 + * This is a function pointer entry point only called by read/write
6208 + * routines for the PHY and NVM parts.
6210 +static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
6214 + fwsm = er32(FWSM);
6215 + return (fwsm & E1000_FWSM_MODE_MASK) ==
6216 + (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
6219 + * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
6220 + * @hw: pointer to the HW structure
6222 + * Checks if firmware is blocking the reset of the PHY.
6223 + * This is a function pointer entry point only called by
6226 +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
6230 + fwsm = er32(FWSM);
6231 + return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
6232 + : E1000_BLK_PHY_RESET;
6236 + * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
6237 + * done after every PHY reset.
6239 +static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
6241 + s32 ret_val = E1000_SUCCESS;
6243 + if (hw->mac.type != e1000_pchlan)
6246 + if (((hw->phy.type == e1000_phy_82577) &&
6247 + ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
6248 + ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
6249 + /* Disable generation of early preamble */
6250 + ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
6254 + /* Preamble tuning for SSC */
6255 + ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
6260 + if (hw->phy.type == e1000_phy_82578) {
6262 + * Return registers to default by doing a soft reset then
6263 + * writing 0x3140 to the control register.
6265 + if (hw->phy.revision < 2) {
6266 + e1000e_phy_sw_reset(hw);
6267 + ret_val = e1e_wphy(hw, PHY_CONTROL,
6272 + /* Select page 0 */
6273 + ret_val = hw->phy.ops.acquire(hw);
6277 + e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
6278 + hw->phy.ops.release(hw);
6284 + * e1000_lan_init_done_ich8lan - Check for PHY config completion
6285 + * @hw: pointer to the HW structure
6287 + * Check the appropriate indication the MAC has finished configuring the
6288 + * PHY after a software reset.
6290 +static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
6292 + u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
6294 + /* Wait for basic configuration completes before proceeding */
6296 + data = er32(STATUS);
6297 + data &= E1000_STATUS_LAN_INIT_DONE;
6299 + } while ((!data) && --loop);
6302 + * If basic configuration is incomplete before the above loop
6303 + * count reaches 0, loading the configuration from NVM will
6304 + * leave the PHY in a bad state possibly resulting in no link.
6307 + e_dbg("LAN_INIT_DONE not set, increase timeout\n");
6309 + /* Clear the Init Done bit for the next init event */
6310 + data = er32(STATUS);
6311 + data &= ~E1000_STATUS_LAN_INIT_DONE;
6312 + ew32(STATUS, data);
6316 + * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
6317 + * @hw: pointer to the HW structure
6320 + * This is a function pointer entry point called by drivers
6321 + * or other shared routines.
6323 +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
6325 + struct e1000_phy_info *phy = &hw->phy;
6326 + u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
6328 + u16 word_addr, reg_data, reg_addr, phy_page = 0;
6330 + ret_val = e1000e_phy_hw_reset_generic(hw);
6334 + /* Allow time for h/w to get to a quiescent state after reset */
6337 + if (hw->mac.type == e1000_pchlan) {
6338 + ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
6344 + * Initialize the PHY from the NVM on ICH platforms. This
6345 + * is needed due to an issue where the NVM configuration is
6346 + * not properly autoloaded after power transitions.
6347 + * Therefore, after each PHY reset, we will load the
6348 + * configuration data out of the NVM manually.
6350 + if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
6351 + /* Check if SW needs configure the PHY */
6352 + if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
6353 + (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
6354 + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
6356 + sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
6358 + data = er32(FEXTNVM);
6359 + if (!(data & sw_cfg_mask))
6362 + /* Wait for basic configuration completes before proceeding */
6363 + e1000_lan_init_done_ich8lan(hw);
6366 + * Make sure HW does not configure LCD from PHY
6367 + * extended configuration before SW configuration
6369 + data = er32(EXTCNF_CTRL);
6370 + if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
6373 + cnf_size = er32(EXTCNF_SIZE);
6374 + cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
6375 + cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
6379 + cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
6380 + cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
6382 + /* Configure LCD from extended configuration region. */
6384 + /* cnf_base_addr is in DWORD */
6385 + word_addr = (u16)(cnf_base_addr << 1);
6387 + for (i = 0; i < cnf_size; i++) {
6388 + ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
6393 + ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
6398 + /* Save off the PHY page for future writes. */
6399 + if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
6400 + phy_page = reg_data;
6404 + reg_addr |= phy_page;
6406 + ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
6417 + * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
6418 + * @hw: pointer to the HW structure
6420 + * Wrapper for calling the get_phy_info routines for the appropriate phy type.
6422 +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
6424 + s32 ret_val = -E1000_ERR_PHY_TYPE;
6426 + switch (hw->phy.type) {
6427 + case e1000_phy_ife:
6428 + ret_val = e1000_get_phy_info_ife_ich8lan(hw);
6430 + case e1000_phy_igp_3:
6431 + case e1000_phy_bm:
6432 + case e1000_phy_82578:
6433 + case e1000_phy_82577:
6434 + ret_val = e1000e_get_phy_info_igp(hw);
6444 + * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
6445 + * @hw: pointer to the HW structure
6447 + * Populates "phy" structure with various feature states.
6448 + * This function is only called by other family-specific
6451 +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
6453 + struct e1000_phy_info *phy = &hw->phy;
6458 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
6463 + e_dbg("Phy info is only valid if link is up\n");
6464 + ret_val = -E1000_ERR_CONFIG;
6468 + ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
6471 + phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
6474 + if (phy->polarity_correction) {
6475 + ret_val = e1000_check_polarity_ife(hw);
6479 + /* Polarity is forced */
6480 + phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
6481 + ? e1000_rev_polarity_reversed
6482 + : e1000_rev_polarity_normal;
6485 + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
6489 + phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
6491 + /* The following parameters are undefined for 10/100 operation. */
6492 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
6493 + phy->local_rx = e1000_1000t_rx_status_undefined;
6494 + phy->remote_rx = e1000_1000t_rx_status_undefined;
6501 + * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
6502 + * @hw: pointer to the HW structure
6503 + * @active: true to enable LPLU, false to disable
6505 + * Sets the LPLU D0 state according to the active flag. When
6506 + * activating LPLU this function also disables smart speed
6507 + * and vice versa. LPLU will not be activated unless the
6508 + * device autonegotiation advertisement meets standards of
6509 + * either 10 or 10/100 or 10/100/1000 at all duplexes.
6510 + * This is a function pointer entry point only called by
6511 + * PHY setup routines.
6513 +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
6515 + struct e1000_phy_info *phy = &hw->phy;
6517 + s32 ret_val = E1000_SUCCESS;
6520 + if (phy->type == e1000_phy_ife)
6523 + phy_ctrl = er32(PHY_CTRL);
6526 + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
6527 + ew32(PHY_CTRL, phy_ctrl);
6529 + if (phy->type != e1000_phy_igp_3)
6533 + * Call gig speed drop workaround on LPLU before accessing
6534 + * any PHY registers
6536 + if (hw->mac.type == e1000_ich8lan)
6537 + e1000e_gig_downshift_workaround_ich8lan(hw);
6539 + /* When LPLU is enabled, we should disable SmartSpeed */
6540 + ret_val = e1e_rphy(hw,
6541 + IGP01E1000_PHY_PORT_CONFIG,
6543 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6544 + ret_val = e1e_wphy(hw,
6545 + IGP01E1000_PHY_PORT_CONFIG,
6550 + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
6551 + ew32(PHY_CTRL, phy_ctrl);
6553 + if (phy->type != e1000_phy_igp_3)
6557 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
6558 + * during Dx states where the power conservation is most
6559 + * important. During driver activity we should enable
6560 + * SmartSpeed, so performance is maintained.
6562 + if (phy->smart_speed == e1000_smart_speed_on) {
6563 + ret_val = e1e_rphy(hw,
6564 + IGP01E1000_PHY_PORT_CONFIG,
6569 + data |= IGP01E1000_PSCFR_SMART_SPEED;
6570 + ret_val = e1e_wphy(hw,
6571 + IGP01E1000_PHY_PORT_CONFIG,
6575 + } else if (phy->smart_speed == e1000_smart_speed_off) {
6576 + ret_val = e1e_rphy(hw,
6577 + IGP01E1000_PHY_PORT_CONFIG,
6582 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6583 + ret_val = e1e_wphy(hw,
6584 + IGP01E1000_PHY_PORT_CONFIG,
6596 + * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
6597 + * @hw: pointer to the HW structure
6598 + * @active: true to enable LPLU, false to disable
6600 + * Sets the LPLU D3 state according to the active flag. When
6601 + * activating LPLU this function also disables smart speed
6602 + * and vice versa. LPLU will not be activated unless the
6603 + * device autonegotiation advertisement meets standards of
6604 + * either 10 or 10/100 or 10/100/1000 at all duplexes.
6605 + * This is a function pointer entry point only called by
6606 + * PHY setup routines.
6608 +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
6610 + struct e1000_phy_info *phy = &hw->phy;
6612 + s32 ret_val = E1000_SUCCESS;
6615 + phy_ctrl = er32(PHY_CTRL);
6618 + phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
6619 + ew32(PHY_CTRL, phy_ctrl);
6621 + if (phy->type != e1000_phy_igp_3)
6625 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
6626 + * during Dx states where the power conservation is most
6627 + * important. During driver activity we should enable
6628 + * SmartSpeed, so performance is maintained.
6630 + if (phy->smart_speed == e1000_smart_speed_on) {
6631 + ret_val = e1e_rphy(hw,
6632 + IGP01E1000_PHY_PORT_CONFIG,
6637 + data |= IGP01E1000_PSCFR_SMART_SPEED;
6638 + ret_val = e1e_wphy(hw,
6639 + IGP01E1000_PHY_PORT_CONFIG,
6643 + } else if (phy->smart_speed == e1000_smart_speed_off) {
6644 + ret_val = e1e_rphy(hw,
6645 + IGP01E1000_PHY_PORT_CONFIG,
6650 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6651 + ret_val = e1e_wphy(hw,
6652 + IGP01E1000_PHY_PORT_CONFIG,
6657 + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
6658 + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
6659 + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
6660 + phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
6661 + ew32(PHY_CTRL, phy_ctrl);
6663 + if (phy->type != e1000_phy_igp_3)
6667 + * Call gig speed drop workaround on LPLU before accessing
6668 + * any PHY registers
6670 + if (hw->mac.type == e1000_ich8lan)
6671 + e1000e_gig_downshift_workaround_ich8lan(hw);
6673 + /* When LPLU is enabled, we should disable SmartSpeed */
6674 + ret_val = e1e_rphy(hw,
6675 + IGP01E1000_PHY_PORT_CONFIG,
6680 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6681 + ret_val = e1e_wphy(hw,
6682 + IGP01E1000_PHY_PORT_CONFIG,
6691 + * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
6692 + * @hw: pointer to the HW structure
6693 + * @bank: pointer to the variable that returns the active bank
6695 + * Reads signature byte from the NVM using the flash access registers.
6696 + * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
6698 +static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
6701 + struct e1000_nvm_info *nvm = &hw->nvm;
6702 + u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
6703 + u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
6705 + s32 ret_val = E1000_SUCCESS;
6707 + switch (hw->mac.type) {
6708 + case e1000_ich8lan:
6709 + case e1000_ich9lan:
6710 + eecd = er32(EECD);
6711 + if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
6712 + E1000_EECD_SEC1VAL_VALID_MASK) {
6713 + if (eecd & E1000_EECD_SEC1VAL)
6720 + e_dbg("Unable to determine valid NVM bank via EEC - "
6721 + "reading flash signature\n");
6724 + /* set bank to 0 in case flash read fails */
6727 + /* Check bank 0 */
6728 + ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
6732 + if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
6733 + E1000_ICH_NVM_SIG_VALUE) {
6738 + /* Check bank 1 */
6739 + ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
6744 + if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
6745 + E1000_ICH_NVM_SIG_VALUE) {
6750 + e_dbg("ERROR: No valid NVM bank present\n");
6751 + ret_val = -E1000_ERR_NVM;
6759 + * e1000_read_nvm_ich8lan - Read word(s) from the NVM
6760 + * @hw: pointer to the HW structure
6761 + * @offset: The offset (in bytes) of the word(s) to read.
6762 + * @words: Size of data to read in words
6763 + * @data: Pointer to the word(s) to read at offset.
6765 + * Reads a word(s) from the NVM using the flash access registers.
6767 +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
6770 + struct e1000_nvm_info *nvm = &hw->nvm;
6771 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
6773 + s32 ret_val = E1000_SUCCESS;
6777 + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
6779 + e_dbg("nvm parameter(s) out of bounds\n");
6780 + ret_val = -E1000_ERR_NVM;
6784 + ret_val = nvm->ops.acquire(hw);
6788 + ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
6789 + if (ret_val != E1000_SUCCESS)
6792 + act_offset = (bank) ? nvm->flash_bank_size : 0;
6793 + act_offset += offset;
6795 + for (i = 0; i < words; i++) {
6796 + if ((dev_spec->shadow_ram) &&
6797 + (dev_spec->shadow_ram[offset+i].modified)) {
6798 + data[i] = dev_spec->shadow_ram[offset+i].value;
6800 + ret_val = e1000_read_flash_word_ich8lan(hw,
6810 + nvm->ops.release(hw);
6814 + e_dbg("NVM read error: %d\n", ret_val);
6820 + * e1000_flash_cycle_init_ich8lan - Initialize flash
6821 + * @hw: pointer to the HW structure
6823 + * This function does initial flash setup so that a new read/write/erase cycle
6826 +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
6828 + union ich8_hws_flash_status hsfsts;
6829 + s32 ret_val = -E1000_ERR_NVM;
6832 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
6834 + /* Check if the flash descriptor is valid */
6835 + if (hsfsts.hsf_status.fldesvalid == 0) {
6836 + e_dbg("Flash descriptor invalid. "
6837 + "SW Sequencing must be used.");
6841 + /* Clear FCERR and DAEL in hw status by writing 1 */
6842 + hsfsts.hsf_status.flcerr = 1;
6843 + hsfsts.hsf_status.dael = 1;
6845 + ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
6848 + * Either we should have a hardware SPI cycle in progress
6849 + * bit to check against, in order to start a new cycle or
6850 + * FDONE bit should be changed in the hardware so that it
6851 + * is 1 after hardware reset, which can then be used as an
6852 + * indication whether a cycle is in progress or has been
6856 + if (hsfsts.hsf_status.flcinprog == 0) {
6858 + * There is no cycle running at present,
6859 + * so we can start a cycle.
6860 + * Begin by setting Flash Cycle Done.
6862 + hsfsts.hsf_status.flcdone = 1;
6863 + ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
6864 + ret_val = E1000_SUCCESS;
6867 + * Otherwise poll for sometime so the current
6868 + * cycle has a chance to end before giving up.
6870 + for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
6871 + hsfsts.regval = er16flash(
6872 + ICH_FLASH_HSFSTS);
6873 + if (hsfsts.hsf_status.flcinprog == 0) {
6874 + ret_val = E1000_SUCCESS;
6879 + if (ret_val == E1000_SUCCESS) {
6881 + * Successful in waiting for previous cycle to timeout,
6882 + * now set the Flash Cycle Done.
6884 + hsfsts.hsf_status.flcdone = 1;
6885 + ew16flash(ICH_FLASH_HSFSTS,
6888 + e_dbg("Flash controller busy, cannot get access");
6897 + * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
6898 + * @hw: pointer to the HW structure
6899 + * @timeout: maximum time to wait for completion
6901 + * This function starts a flash cycle and waits for its completion.
6903 +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
6905 + union ich8_hws_flash_ctrl hsflctl;
6906 + union ich8_hws_flash_status hsfsts;
6907 + s32 ret_val = -E1000_ERR_NVM;
6910 + /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
6911 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
6912 + hsflctl.hsf_ctrl.flcgo = 1;
6913 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
6915 + /* wait till FDONE bit is set to 1 */
6917 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
6918 + if (hsfsts.hsf_status.flcdone == 1)
6921 + } while (i++ < timeout);
6923 + if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
6924 + ret_val = E1000_SUCCESS;
6930 + * e1000_read_flash_word_ich8lan - Read word from flash
6931 + * @hw: pointer to the HW structure
6932 + * @offset: offset to data location
6933 + * @data: pointer to the location for storing the data
6935 + * Reads the flash word at offset into data. Offset is converted
6936 + * to bytes before read.
6938 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
6944 + ret_val = -E1000_ERR_NVM;
6948 + /* Must convert offset into bytes. */
6951 + ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
6958 + * e1000_read_flash_byte_ich8lan - Read byte from flash
6959 + * @hw: pointer to the HW structure
6960 + * @offset: The offset of the byte to read.
6961 + * @data: Pointer to a byte to store the value read.
6963 + * Reads a single byte from the NVM using the flash access registers.
6965 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
6968 + s32 ret_val = E1000_SUCCESS;
6971 + ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
6982 + * e1000_read_flash_data_ich8lan - Read byte or word from NVM
6983 + * @hw: pointer to the HW structure
6984 + * @offset: The offset (in bytes) of the byte or word to read.
6985 + * @size: Size of data to read, 1=byte 2=word
6986 + * @data: Pointer to the word to store the value read.
6988 + * Reads a byte or word from the NVM using the flash access registers.
6990 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
6991 + u8 size, u16 *data)
6993 + union ich8_hws_flash_status hsfsts;
6994 + union ich8_hws_flash_ctrl hsflctl;
6995 + u32 flash_linear_addr;
6996 + u32 flash_data = 0;
6997 + s32 ret_val = -E1000_ERR_NVM;
7000 + if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
7002 + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
7003 + hw->nvm.flash_base_addr;
7008 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7009 + if (ret_val != E1000_SUCCESS)
7012 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
7013 + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7014 + hsflctl.hsf_ctrl.fldbcount = size - 1;
7015 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
7016 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
7018 + ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
7020 + ret_val = e1000_flash_cycle_ich8lan(hw,
7021 + ICH_FLASH_READ_COMMAND_TIMEOUT);
7024 + * Check if FCERR is set to 1, if set to 1, clear it
7025 + * and try the whole sequence a few more times, else
7026 + * read in (shift in) the Flash Data0, the order is
7027 + * least significant byte first msb to lsb
7029 + if (ret_val == E1000_SUCCESS) {
7030 + flash_data = er32flash(ICH_FLASH_FDATA0);
7032 + *data = (u8)(flash_data & 0x000000FF);
7033 + else if (size == 2)
7034 + *data = (u16)(flash_data & 0x0000FFFF);
7038 + * If we've gotten here, then things are probably
7039 + * completely hosed, but if the error condition is
7040 + * detected, it won't hurt to give it another try...
7041 + * ICH_FLASH_CYCLE_REPEAT_COUNT times.
7043 + hsfsts.regval = er16flash(
7044 + ICH_FLASH_HSFSTS);
7045 + if (hsfsts.hsf_status.flcerr == 1) {
7046 + /* Repeat for some time before giving up. */
7048 + } else if (hsfsts.hsf_status.flcdone == 0) {
7049 + e_dbg("Timeout error - flash cycle "
7050 + "did not complete.");
7054 + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7061 + * e1000_write_nvm_ich8lan - Write word(s) to the NVM
7062 + * @hw: pointer to the HW structure
7063 + * @offset: The offset (in bytes) of the word(s) to write.
7064 + * @words: Size of data to write in words
7065 + * @data: Pointer to the word(s) to write at offset.
7067 + * Writes a byte or word to the NVM using the flash access registers.
7069 +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
7072 + struct e1000_nvm_info *nvm = &hw->nvm;
7073 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
7074 + s32 ret_val = E1000_SUCCESS;
7077 + if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
7079 + e_dbg("nvm parameter(s) out of bounds\n");
7080 + ret_val = -E1000_ERR_NVM;
7084 + ret_val = nvm->ops.acquire(hw);
7088 + for (i = 0; i < words; i++) {
7089 + dev_spec->shadow_ram[offset+i].modified = true;
7090 + dev_spec->shadow_ram[offset+i].value = data[i];
7093 + nvm->ops.release(hw);
7100 + * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
7101 + * @hw: pointer to the HW structure
7103 + * The NVM checksum is updated by calling the generic update_nvm_checksum,
7104 + * which writes the checksum to the shadow ram. The changes in the shadow
7105 + * ram are then committed to the EEPROM by processing each bank at a time
7106 + * checking for the modified bit and writing only the pending changes.
7107 + * After a successful commit, the shadow ram is cleared and is ready for
7110 +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
7112 + struct e1000_nvm_info *nvm = &hw->nvm;
7113 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
7114 + u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
7118 + ret_val = e1000e_update_nvm_checksum_generic(hw);
7122 + if (nvm->type != e1000_nvm_flash_sw)
7125 + ret_val = nvm->ops.acquire(hw);
7130 + * We're writing to the opposite bank so if we're on bank 1,
7131 + * write to bank 0 etc. We also need to erase the segment that
7132 + * is going to be written
7134 + ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
7135 + if (ret_val != E1000_SUCCESS) {
7136 + nvm->ops.release(hw);
7141 + new_bank_offset = nvm->flash_bank_size;
7142 + old_bank_offset = 0;
7143 + ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
7145 + nvm->ops.release(hw);
7149 + old_bank_offset = nvm->flash_bank_size;
7150 + new_bank_offset = 0;
7151 + ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
7153 + nvm->ops.release(hw);
7158 + for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
7160 + * Determine whether to write the value stored
7161 + * in the other NVM bank or a modified value stored
7162 + * in the shadow RAM
7164 + if (dev_spec->shadow_ram[i].modified) {
7165 + data = dev_spec->shadow_ram[i].value;
7167 + ret_val = e1000_read_flash_word_ich8lan(hw, i +
7175 + * If the word is 0x13, then make sure the signature bits
7176 + * (15:14) are 11b until the commit has completed.
7177 + * This will allow us to write 10b which indicates the
7178 + * signature is valid. We want to do this after the write
7179 + * has completed so that we don't mark the segment valid
7180 + * while the write is still in progress
7182 + if (i == E1000_ICH_NVM_SIG_WORD)
7183 + data |= E1000_ICH_NVM_SIG_MASK;
7185 + /* Convert offset to bytes. */
7186 + act_offset = (i + new_bank_offset) << 1;
7189 + /* Write the bytes to the new bank. */
7190 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7197 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7205 + * Don't bother writing the segment valid bits if sector
7206 + * programming failed.
7209 + e_dbg("Flash commit failed.\n");
7210 + nvm->ops.release(hw);
7215 + * Finally validate the new segment by setting bit 15:14
7216 + * to 10b in word 0x13 , this can be done without an
7217 + * erase as well since these bits are 11 to start with
7218 + * and we need to change bit 14 to 0b
7220 + act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
7221 + ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
7223 + nvm->ops.release(hw);
7227 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
7228 + act_offset * 2 + 1,
7231 + nvm->ops.release(hw);
7236 + * And invalidate the previously valid segment by setting
7237 + * its signature word (0x13) high_byte to 0b. This can be
7238 + * done without an erase because flash erase sets all bits
7239 + * to 1's. We can write 1's to 0's without an erase
7241 + act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
7242 + ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
7244 + nvm->ops.release(hw);
7248 + /* Great! Everything worked, we can now clear the cached entries. */
7249 + for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
7250 + dev_spec->shadow_ram[i].modified = false;
7251 + dev_spec->shadow_ram[i].value = 0xFFFF;
7254 + nvm->ops.release(hw);
7257 + * Reload the EEPROM, or else modifications will not appear
7258 + * until after the next adapter reset.
7260 + nvm->ops.reload(hw);
7265 + e_dbg("NVM update error: %d\n", ret_val);
7271 + * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
7272 + * @hw: pointer to the HW structure
7274 + * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
7275 + * If the bit is 0, that the EEPROM had been modified, but the checksum was not
7276 + * calculated, in which case we need to calculate the checksum and set bit 6.
7278 +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
7280 + s32 ret_val = E1000_SUCCESS;
7284 + * Read 0x19 and check bit 6. If this bit is 0, the checksum
7285 + * needs to be fixed. This bit is an indication that the NVM
7286 + * was prepared by OEM software and did not calculate the
7287 + * checksum...a likely scenario.
7289 + ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
7293 + if ((data & 0x40) == 0) {
7295 + ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
7298 + ret_val = e1000e_update_nvm_checksum(hw);
7303 + ret_val = e1000e_validate_nvm_checksum_generic(hw);
7310 + * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
7311 + * @hw: pointer to the HW structure
7312 + * @offset: The offset (in bytes) of the byte/word to read.
7313 + * @size: Size of data to read, 1=byte 2=word
7314 + * @data: The byte(s) to write to the NVM.
7316 + * Writes one/two bytes to the NVM using the flash access registers.
7318 +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
7319 + u8 size, u16 data)
7321 + union ich8_hws_flash_status hsfsts;
7322 + union ich8_hws_flash_ctrl hsflctl;
7323 + u32 flash_linear_addr;
7324 + u32 flash_data = 0;
7325 + s32 ret_val = -E1000_ERR_NVM;
7328 + if (size < 1 || size > 2 || data > size * 0xff ||
7329 + offset > ICH_FLASH_LINEAR_ADDR_MASK)
7332 + flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
7333 + hw->nvm.flash_base_addr;
7338 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7339 + if (ret_val != E1000_SUCCESS)
7342 + hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
7343 + /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7344 + hsflctl.hsf_ctrl.fldbcount = size - 1;
7345 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
7346 + ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
7348 + ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
7351 + flash_data = (u32)data & 0x00FF;
7353 + flash_data = (u32)data;
7355 + ew32flash(ICH_FLASH_FDATA0, flash_data);
7358 + * check if FCERR is set to 1 , if set to 1, clear it
7359 + * and try the whole sequence a few more times else done
7361 + ret_val = e1000_flash_cycle_ich8lan(hw,
7362 + ICH_FLASH_WRITE_COMMAND_TIMEOUT);
7363 + if (ret_val == E1000_SUCCESS)
7367 + * If we're here, then things are most likely
7368 + * completely hosed, but if the error condition
7369 + * is detected, it won't hurt to give it another
7370 + * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
7372 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7373 + if (hsfsts.hsf_status.flcerr == 1) {
7374 + /* Repeat for some time before giving up. */
7376 + } else if (hsfsts.hsf_status.flcdone == 0) {
7377 + e_dbg("Timeout error - flash cycle "
7378 + "did not complete.");
7381 + } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7388 + * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
7389 + * @hw: pointer to the HW structure
7390 + * @offset: The index of the byte to read.
7391 + * @data: The byte to write to the NVM.
7393 + * Writes a single byte to the NVM using the flash access registers.
7395 +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
7398 + u16 word = (u16)data;
7400 + return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
7404 + * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
7405 + * @hw: pointer to the HW structure
7406 + * @offset: The offset of the byte to write.
7407 + * @byte: The byte to write to the NVM.
7409 + * Writes a single byte to the NVM using the flash access registers.
7410 + * Goes through a retry algorithm before giving up.
7412 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
7413 + u32 offset, u8 byte)
7416 + u16 program_retries;
7418 + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
7419 + if (ret_val == E1000_SUCCESS)
7422 + for (program_retries = 0; program_retries < 100; program_retries++) {
7423 + e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
7425 + ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
7426 + if (ret_val == E1000_SUCCESS)
7429 + if (program_retries == 100) {
7430 + ret_val = -E1000_ERR_NVM;
7439 + * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
7440 + * @hw: pointer to the HW structure
7441 + * @bank: 0 for first bank, 1 for second bank, etc.
7443 + * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
7444 + * bank N is 4096 * N + flash_reg_addr.
7446 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
7448 + struct e1000_nvm_info *nvm = &hw->nvm;
7449 + union ich8_hws_flash_status hsfsts;
7450 + union ich8_hws_flash_ctrl hsflctl;
7451 + u32 flash_linear_addr;
7452 + /* bank size is in 16bit words - adjust to bytes */
7453 + u32 flash_bank_size = nvm->flash_bank_size * 2;
7454 + s32 ret_val = E1000_SUCCESS;
7456 + s32 j, iteration, sector_size;
7458 + hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
7461 + * Determine HW Sector size: Read BERASE bits of hw flash status
7463 + * 00: The Hw sector is 256 bytes, hence we need to erase 16
7464 + * consecutive sectors. The start index for the nth Hw sector
7465 + * can be calculated as = bank * 4096 + n * 256
7466 + * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
7467 + * The start index for the nth Hw sector can be calculated
7468 + * as = bank * 4096
7469 + * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
7470 + * (ich9 only, otherwise error condition)
7471 + * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
7473 + switch (hsfsts.hsf_status.berasesz) {
7475 + /* Hw sector size 256 */
7476 + sector_size = ICH_FLASH_SEG_SIZE_256;
7477 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
7480 + sector_size = ICH_FLASH_SEG_SIZE_4K;
7484 + if (hw->mac.type == e1000_ich9lan) {
7485 + sector_size = ICH_FLASH_SEG_SIZE_8K;
7486 + iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
7488 + ret_val = -E1000_ERR_NVM;
7493 + sector_size = ICH_FLASH_SEG_SIZE_64K;
7497 + ret_val = -E1000_ERR_NVM;
7501 + /* Start with the base address, then add the sector offset. */
7502 + flash_linear_addr = hw->nvm.flash_base_addr;
7503 + flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
7505 + for (j = 0; j < iteration ; j++) {
7508 + ret_val = e1000_flash_cycle_init_ich8lan(hw);
7513 + * Write a value 11 (block Erase) in Flash
7514 + * Cycle field in hw flash control
7516 + hsflctl.regval = er16flash(
7517 + ICH_FLASH_HSFCTL);
7518 + hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
7519 + ew16flash(ICH_FLASH_HSFCTL,
7523 + * Write the last 24 bits of an index within the
7524 + * block into Flash Linear address field in Flash
7527 + flash_linear_addr += (j * sector_size);
7528 + ew32flash(ICH_FLASH_FADDR,
7529 + flash_linear_addr);
7531 + ret_val = e1000_flash_cycle_ich8lan(hw,
7532 + ICH_FLASH_ERASE_COMMAND_TIMEOUT);
7533 + if (ret_val == E1000_SUCCESS)
7537 + * Check if FCERR is set to 1. If 1,
7538 + * clear it and try the whole sequence
7539 + * a few more times else Done
7541 + hsfsts.regval = er16flash(
7542 + ICH_FLASH_HSFSTS);
7543 + if (hsfsts.hsf_status.flcerr == 1)
7544 + /* repeat for some time before giving up */
7546 + else if (hsfsts.hsf_status.flcdone == 0)
7548 + } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
7556 + * e1000_valid_led_default_ich8lan - Set the default LED settings
7557 + * @hw: pointer to the HW structure
7558 + * @data: Pointer to the LED settings
7560 + * Reads the LED default settings from the NVM to data. If the NVM LED
7561 + * settings is all 0's or F's, set the LED default to a valid LED default
7564 +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
7568 + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
7570 + e_dbg("NVM Read Error\n");
7574 + if (*data == ID_LED_RESERVED_0000 ||
7575 + *data == ID_LED_RESERVED_FFFF)
7576 + *data = ID_LED_DEFAULT_ICH8LAN;
7583 + * e1000_id_led_init_pchlan - store LED configurations
7584 + * @hw: pointer to the HW structure
7586 + * PCH does not control LEDs via the LEDCTL register, rather it uses
7587 + * the PHY LED configuration register.
7589 + * PCH also does not have an "always on" or "always off" mode which
7590 + * complicates the ID feature. Instead of using the "on" mode to indicate
7591 + * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
7592 + * use "link_up" mode. The LEDs will still ID on request if there is no
7593 + * link based on logic in e1000_led_[on|off]_pchlan().
7595 +static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
7597 + struct e1000_mac_info *mac = &hw->mac;
7599 + const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
7600 + const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
7601 + u16 data, i, temp, shift;
7603 + /* Get default ID LED modes */
7604 + ret_val = hw->nvm.ops.valid_led_default(hw, &data);
7608 + mac->ledctl_default = er32(LEDCTL);
7609 + mac->ledctl_mode1 = mac->ledctl_default;
7610 + mac->ledctl_mode2 = mac->ledctl_default;
7612 + for (i = 0; i < 4; i++) {
7613 + temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
7616 + case ID_LED_ON1_DEF2:
7617 + case ID_LED_ON1_ON2:
7618 + case ID_LED_ON1_OFF2:
7619 + mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
7620 + mac->ledctl_mode1 |= (ledctl_on << shift);
7622 + case ID_LED_OFF1_DEF2:
7623 + case ID_LED_OFF1_ON2:
7624 + case ID_LED_OFF1_OFF2:
7625 + mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
7626 + mac->ledctl_mode1 |= (ledctl_off << shift);
7633 + case ID_LED_DEF1_ON2:
7634 + case ID_LED_ON1_ON2:
7635 + case ID_LED_OFF1_ON2:
7636 + mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
7637 + mac->ledctl_mode2 |= (ledctl_on << shift);
7639 + case ID_LED_DEF1_OFF2:
7640 + case ID_LED_ON1_OFF2:
7641 + case ID_LED_OFF1_OFF2:
7642 + mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
7643 + mac->ledctl_mode2 |= (ledctl_off << shift);
7656 + * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
7657 + * @hw: pointer to the HW structure
7659 + * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
7660 + * register, so the the bus width is hard coded.
7662 +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
7664 + struct e1000_bus_info *bus = &hw->bus;
7667 + ret_val = e1000e_get_bus_info_pcie(hw);
7670 + * ICH devices are "PCI Express"-ish. They have
7671 + * a configuration space, but do not contain
7672 + * PCI Express Capability registers, so bus width
7673 + * must be hardcoded.
7675 + if (bus->width == e1000_bus_width_unknown)
7676 + bus->width = e1000_bus_width_pcie_x1;
7682 + * e1000_reset_hw_ich8lan - Reset the hardware
7683 + * @hw: pointer to the HW structure
7685 + * Does a full reset of the hardware which includes a reset of the PHY and
7688 +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
7690 + u32 ctrl, icr, kab;
7694 + * Prevent the PCI-E bus from sticking if there is no TLP connection
7695 + * on the last TLP read/write transaction when MAC is reset.
7697 + ret_val = e1000e_disable_pcie_master(hw);
7699 + e_dbg("PCI-E Master disable polling has failed.\n");
7701 + e_dbg("Masking off all interrupts\n");
7702 + ew32(IMC, 0xffffffff);
7705 + * Disable the Transmit and Receive units. Then delay to allow
7706 + * any pending transactions to complete before we hit the MAC
7707 + * with the global reset.
7710 + ew32(TCTL, E1000_TCTL_PSP);
7715 + /* Workaround for ICH8 bit corruption issue in FIFO memory */
7716 + if (hw->mac.type == e1000_ich8lan) {
7717 + /* Set Tx and Rx buffer allocation to 8k apiece. */
7718 + ew32(PBA, E1000_PBA_8K);
7719 + /* Set Packet Buffer Size to 16k. */
7720 + ew32(PBS, E1000_PBS_16K);
7723 + ctrl = er32(CTRL);
7725 + if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) {
7726 + /* Clear PHY Reset Asserted bit */
7727 + if (hw->mac.type >= e1000_pchlan) {
7728 + u32 status = er32(STATUS);
7729 + ew32(STATUS, status &
7730 + ~E1000_STATUS_PHYRA);
7734 + * PHY HW reset requires MAC CORE reset at the same
7735 + * time to make sure the interface between MAC and the
7736 + * external PHY is reset.
7738 + ctrl |= E1000_CTRL_PHY_RST;
7740 + ret_val = e1000_acquire_swflag_ich8lan(hw);
7741 + e_dbg("Issuing a global reset to ich8lan\n");
7742 + ew32(CTRL, (ctrl | E1000_CTRL_RST));
7746 + e1000_release_swflag_ich8lan(hw);
7748 + if (ctrl & E1000_CTRL_PHY_RST)
7749 + ret_val = hw->phy.ops.get_cfg_done(hw);
7751 + if (hw->mac.type >= e1000_ich10lan) {
7752 + e1000_lan_init_done_ich8lan(hw);
7755 + /* release the swflag because it is not reset by
7758 + e1000_release_swflag_ich8lan(hw);
7761 + ret_val = e1000e_get_auto_rd_done(hw);
7764 + * When auto config read does not complete, do not
7765 + * return with an error. This can happen in situations
7766 + * where there is no eeprom and prevents getting link.
7768 + e_dbg("Auto Read Done did not complete\n");
7773 + * For PCH, this write will make sure that any noise
7774 + * will be detected as a CRC error and be dropped rather than show up
7775 + * as a bad packet to the DMA engine.
7777 + if (hw->mac.type == e1000_pchlan)
7778 + ew32(CRC_OFFSET, 0x65656565);
7780 + ew32(IMC, 0xffffffff);
7783 + kab = er32(KABGTXD);
7784 + kab |= E1000_KABGTXD_BGSQLBIAS;
7785 + ew32(KABGTXD, kab);
7787 + if (hw->mac.type == e1000_pchlan)
7788 + ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
7794 + * e1000_init_hw_ich8lan - Initialize the hardware
7795 + * @hw: pointer to the HW structure
7797 + * Prepares the hardware for transmit and receive by doing the following:
7798 + * - initialize hardware bits
7799 + * - initialize LED identification
7800 + * - setup receive address registers
7801 + * - setup flow control
7802 + * - setup transmit descriptors
7803 + * - clear statistics
7805 +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
7807 + struct e1000_mac_info *mac = &hw->mac;
7808 + u32 ctrl_ext, txdctl, snoop;
7812 + e1000_initialize_hw_bits_ich8lan(hw);
7814 + /* Initialize identification LED */
7815 + ret_val = mac->ops.id_led_init(hw);
7817 + /* This is not fatal and we should not stop init due to this */
7818 + e_dbg("Error initializing identification LED\n");
7820 + /* Setup the receive address. */
7821 + e1000e_init_rx_addrs(hw, mac->rar_entry_count);
7823 + /* Zero out the Multicast HASH table */
7824 + e_dbg("Zeroing the MTA\n");
7825 + for (i = 0; i < mac->mta_reg_count; i++)
7826 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
7829 + * The 82578 Rx buffer will stall if wakeup is enabled in host and
7830 + * the ME. Reading the BM_WUC register will clear the host wakeup bit.
7831 + * Reset the phy after disabling host wakeup to reset the Rx buffer.
7833 + if (hw->phy.type == e1000_phy_82578) {
7834 + e1e_rphy(hw, BM_WUC, &i);
7835 + ret_val = e1000_phy_hw_reset_ich8lan(hw);
7840 + /* Setup link and flow control */
7841 + ret_val = mac->ops.setup_link(hw);
7843 + /* Set the transmit descriptor write-back policy for both queues */
7844 + txdctl = er32(TXDCTL(0));
7845 + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
7846 + E1000_TXDCTL_FULL_TX_DESC_WB;
7847 + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
7848 + E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
7849 + ew32(TXDCTL(0), txdctl);
7850 + txdctl = er32(TXDCTL(1));
7851 + txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
7852 + E1000_TXDCTL_FULL_TX_DESC_WB;
7853 + txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
7854 + E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
7855 + ew32(TXDCTL(1), txdctl);
7858 + * ICH8 has opposite polarity of no_snoop bits.
7859 + * By default, we should use snoop behavior.
7861 + if (mac->type == e1000_ich8lan)
7862 + snoop = PCIE_ICH8_SNOOP_ALL;
7864 + snoop = (u32)~(PCIE_NO_SNOOP_ALL);
7865 + e1000e_set_pcie_no_snoop(hw, snoop);
7867 + ctrl_ext = er32(CTRL_EXT);
7868 + ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
7869 + ew32(CTRL_EXT, ctrl_ext);
7872 + * Clear all of the statistics registers (clear on read). It is
7873 + * important that we do this after we have tried to establish link
7874 + * because the symbol error count will increment wildly if there
7877 + e1000_clear_hw_cntrs_ich8lan(hw);
7882 + * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
7883 + * @hw: pointer to the HW structure
7885 + * Sets/Clears required hardware bits necessary for correctly setting up the
7886 + * hardware for transmit and receive.
7888 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
7892 + /* Extended Device Control */
7893 + reg = er32(CTRL_EXT);
7895 + /* Enable PHY low-power state when MAC is at D3 w/o WoL */
7896 + if (hw->mac.type >= e1000_pchlan)
7897 + reg |= E1000_CTRL_EXT_PHYPDEN;
7898 + ew32(CTRL_EXT, reg);
7900 + /* Transmit Descriptor Control 0 */
7901 + reg = er32(TXDCTL(0));
7903 + ew32(TXDCTL(0), reg);
7905 + /* Transmit Descriptor Control 1 */
7906 + reg = er32(TXDCTL(1));
7908 + ew32(TXDCTL(1), reg);
7910 + /* Transmit Arbitration Control 0 */
7911 + reg = er32(TARC(0));
7912 + if (hw->mac.type == e1000_ich8lan)
7913 + reg |= (1 << 28) | (1 << 29);
7914 + reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
7915 + ew32(TARC(0), reg);
7917 + /* Transmit Arbitration Control 1 */
7918 + reg = er32(TARC(1));
7919 + if (er32(TCTL) & E1000_TCTL_MULR)
7920 + reg &= ~(1 << 28);
7923 + reg |= (1 << 24) | (1 << 26) | (1 << 30);
7924 + ew32(TARC(1), reg);
7926 + /* Device Status */
7927 + if (hw->mac.type == e1000_ich8lan) {
7928 + reg = er32(STATUS);
7929 + reg &= ~(1 << 31);
7930 + ew32(STATUS, reg);
7937 + * e1000_setup_link_ich8lan - Setup flow control and link settings
7938 + * @hw: pointer to the HW structure
7940 + * Determines which flow control settings to use, then configures flow
7941 + * control. Calls the appropriate media-specific link configuration
7942 + * function. Assuming the adapter has a valid link partner, a valid link
7943 + * should be established. Assumes the hardware has previously been reset
7944 + * and the transmitter and receiver are not enabled.
7946 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
7948 + s32 ret_val = E1000_SUCCESS;
7950 + if (e1000_check_reset_block(hw))
7954 + * ICH parts do not have a word in the NVM to determine
7955 + * the default flow control setting, so we explicitly
7958 + if (hw->fc.requested_mode == e1000_fc_default)
7959 + hw->fc.requested_mode = e1000_fc_full;
7962 + * Save off the requested flow control mode for use later. Depending
7963 + * on the link partner's capabilities, we may or may not use this mode.
7965 + hw->fc.current_mode = hw->fc.requested_mode;
7967 + e_dbg("After fix-ups FlowControl is now = %x\n",
7968 + hw->fc.current_mode);
7970 + /* Continue to configure the copper link. */
7971 + ret_val = hw->mac.ops.setup_physical_interface(hw);
7975 + ew32(FCTTV, hw->fc.pause_time);
7976 + if ((hw->phy.type == e1000_phy_82578) ||
7977 + (hw->phy.type == e1000_phy_82577)) {
7978 + ret_val = e1e_wphy(hw,
7979 + PHY_REG(BM_PORT_CTRL_PAGE, 27),
7980 + hw->fc.pause_time);
7985 + ret_val = e1000e_set_fc_watermarks(hw);
7992 + * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
7993 + * @hw: pointer to the HW structure
7995 + * Configures the kumeran interface to the PHY to wait the appropriate time
7996 + * when polling the PHY, then call the generic setup_copper_link to finish
7997 + * configuring the copper link.
7999 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
8005 + ctrl = er32(CTRL);
8006 + ctrl |= E1000_CTRL_SLU;
8007 + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
8011 + * Set the mac to wait the maximum time between each iteration
8012 + * and increase the max iterations when polling the phy;
8013 + * this fixes erroneous timeouts at 10Mbps.
8015 + ret_val = e1000e_write_kmrn_reg(hw,
8016 + E1000_KMRNCTRLSTA_TIMEOUTS,
8020 + ret_val = e1000e_read_kmrn_reg(hw,
8021 + E1000_KMRNCTRLSTA_INBAND_PARAM,
8026 + ret_val = e1000e_write_kmrn_reg(hw,
8027 + E1000_KMRNCTRLSTA_INBAND_PARAM,
8032 + switch (hw->phy.type) {
8033 + case e1000_phy_igp_3:
8034 + ret_val = e1000e_copper_link_setup_igp(hw);
8038 + case e1000_phy_bm:
8039 + case e1000_phy_82578:
8040 + ret_val = e1000e_copper_link_setup_m88(hw);
8044 + case e1000_phy_82577:
8045 + ret_val = e1000_copper_link_setup_82577(hw);
8049 + case e1000_phy_ife:
8050 + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL,
8055 + reg_data &= ~IFE_PMC_AUTO_MDIX;
8057 + switch (hw->phy.mdix) {
8059 + reg_data &= ~IFE_PMC_FORCE_MDIX;
8062 + reg_data |= IFE_PMC_FORCE_MDIX;
8066 + reg_data |= IFE_PMC_AUTO_MDIX;
8069 + ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL,
8077 + ret_val = e1000e_setup_copper_link(hw);
8084 + * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
8085 + * @hw: pointer to the HW structure
8086 + * @speed: pointer to store current link speed
8087 + * @duplex: pointer to store the current link duplex
8089 + * Calls the generic get_speed_and_duplex to retrieve the current link
8090 + * information and then calls the Kumeran lock loss workaround for links at
8093 +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
8098 + ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
8102 + if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
8103 + ret_val = e1000e_write_kmrn_reg(hw,
8104 + E1000_KMRNCTRLSTA_K1_CONFIG,
8105 + E1000_KMRNCTRLSTA_K1_DISABLE);
8110 + if ((hw->mac.type == e1000_ich8lan) &&
8111 + (hw->phy.type == e1000_phy_igp_3) &&
8112 + (*speed == SPEED_1000)) {
8113 + ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
8121 + * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
8122 + * @hw: pointer to the HW structure
8124 + * Work-around for 82566 Kumeran PCS lock loss:
8125 + * On link status change (i.e. PCI reset, speed change) and link is up and
8126 + * speed is gigabit-
8127 + * 0) if workaround is optionally disabled do nothing
8128 + * 1) wait 1ms for Kumeran link to come up
8129 + * 2) check Kumeran Diagnostic register PCS lock loss bit
8130 + * 3) if not set the link is locked (all is good), otherwise...
8131 + * 4) reset the PHY
8132 + * 5) repeat up to 10 times
8133 + * Note: this is only called for IGP3 copper when speed is 1gb.
8135 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
8137 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
8139 + s32 ret_val = E1000_SUCCESS;
8143 + if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
8147 + * Make sure link is up before proceeding. If not just return.
8148 + * Attempting this while link is negotiating fouled up link
8151 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
8153 + ret_val = E1000_SUCCESS;
8157 + for (i = 0; i < 10; i++) {
8158 + /* read once to clear */
8159 + ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
8162 + /* and again to get new status */
8163 + ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
8167 + /* check for PCS lock */
8168 + if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
8169 + ret_val = E1000_SUCCESS;
8173 + /* Issue PHY reset */
8174 + e1000_phy_hw_reset(hw);
8177 + /* Disable GigE link negotiation */
8178 + phy_ctrl = er32(PHY_CTRL);
8179 + phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
8180 + E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
8181 + ew32(PHY_CTRL, phy_ctrl);
8184 + * Call gig speed drop workaround on Gig disable before accessing
8185 + * any PHY registers
8187 + e1000e_gig_downshift_workaround_ich8lan(hw);
8189 + /* unable to acquire PCS lock */
8190 + ret_val = -E1000_ERR_PHY;
8197 + * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
8198 + * @hw: pointer to the HW structure
8199 + * @state: boolean value used to set the current Kumeran workaround state
8201 + * If ICH8, set the current Kumeran workaround state (enabled - true
8202 + * /disabled - false).
8204 +void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
8207 + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
8209 + if (hw->mac.type != e1000_ich8lan) {
8210 + e_dbg("Workaround applies to ICH8 only.\n");
8214 + dev_spec->kmrn_lock_loss_workaround_enabled = state;
8220 + * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
8221 + * @hw: pointer to the HW structure
8223 + * Workaround for 82566 power-down on D3 entry:
8224 + * 1) disable gigabit link
8225 + * 2) write VR power-down enable
8227 + * Continue if successful, else issue LCD reset and repeat
8229 +void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
8235 + if (hw->phy.type != e1000_phy_igp_3)
8238 + /* Try the workaround twice (if needed) */
8240 + /* Disable link */
8241 + reg = er32(PHY_CTRL);
8242 + reg |= (E1000_PHY_CTRL_GBE_DISABLE |
8243 + E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
8244 + ew32(PHY_CTRL, reg);
8247 + * Call gig speed drop workaround on Gig disable before
8248 + * accessing any PHY registers
8250 + if (hw->mac.type == e1000_ich8lan)
8251 + e1000e_gig_downshift_workaround_ich8lan(hw);
8253 + /* Write VR power-down enable */
8254 + e1e_rphy(hw, IGP3_VR_CTRL, &data);
8255 + data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
8256 + e1e_wphy(hw, IGP3_VR_CTRL,
8257 + data | IGP3_VR_CTRL_MODE_SHUTDOWN);
8259 + /* Read it back and test */
8260 + e1e_rphy(hw, IGP3_VR_CTRL, &data);
8261 + data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
8262 + if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
8265 + /* Issue PHY reset and repeat at most one more time */
8267 + ew32(CTRL, reg | E1000_CTRL_PHY_RST);
8276 + * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
8277 + * @hw: pointer to the HW structure
8279 + * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
8280 + * LPLU, Gig disable, MDIC PHY reset):
8281 + * 1) Set Kumeran Near-end loopback
8282 + * 2) Clear Kumeran Near-end loopback
8283 + * Should only be called for ICH8[m] devices with IGP_3 Phy.
8285 +void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
8287 + s32 ret_val = E1000_SUCCESS;
8290 + if ((hw->mac.type != e1000_ich8lan) ||
8291 + (hw->phy.type != e1000_phy_igp_3))
8294 + ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
8298 + reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
8299 + ret_val = e1000e_write_kmrn_reg(hw,
8300 + E1000_KMRNCTRLSTA_DIAG_OFFSET,
8304 + reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
8305 + ret_val = e1000e_write_kmrn_reg(hw,
8306 + E1000_KMRNCTRLSTA_DIAG_OFFSET,
8313 + * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
8314 + * @hw: pointer to the HW structure
8316 + * During S0 to Sx transition, it is possible the link remains at gig
8317 + * instead of negotiating to a lower speed. Before going to Sx, set
8318 + * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
8319 + * to a lower speed.
8321 + * Should only be called for applicable parts.
8323 +void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
8327 + switch (hw->mac.type) {
8328 + case e1000_ich9lan:
8329 + case e1000_ich10lan:
8330 + case e1000_pchlan:
8331 + phy_ctrl = er32(PHY_CTRL);
8332 + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
8333 + E1000_PHY_CTRL_GBE_DISABLE;
8334 + ew32(PHY_CTRL, phy_ctrl);
8336 + /* Workaround SWFLAG unexpectedly set during S0->Sx */
8337 + if (hw->mac.type == e1000_pchlan)
8347 + * e1000_cleanup_led_ich8lan - Restore the default LED operation
8348 + * @hw: pointer to the HW structure
8350 + * Return the LED back to the default configuration.
8352 +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
8354 + s32 ret_val = E1000_SUCCESS;
8356 + if (hw->phy.type == e1000_phy_ife)
8357 + ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
8360 + ew32(LEDCTL, hw->mac.ledctl_default);
8366 + * e1000_led_on_ich8lan - Turn LEDs on
8367 + * @hw: pointer to the HW structure
8369 + * Turn on the LEDs.
8371 +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
8373 + s32 ret_val = E1000_SUCCESS;
8375 + if (hw->phy.type == e1000_phy_ife)
8376 + ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
8377 + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
8379 + ew32(LEDCTL, hw->mac.ledctl_mode2);
8385 + * e1000_led_off_ich8lan - Turn LEDs off
8386 + * @hw: pointer to the HW structure
8388 + * Turn off the LEDs.
8390 +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
8392 + s32 ret_val = E1000_SUCCESS;
8394 + if (hw->phy.type == e1000_phy_ife)
8395 + ret_val = e1e_wphy(hw,
8396 + IFE_PHY_SPECIAL_CONTROL_LED,
8397 + (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
8399 + ew32(LEDCTL, hw->mac.ledctl_mode1);
8405 + * e1000_setup_led_pchlan - Configures SW controllable LED
8406 + * @hw: pointer to the HW structure
8408 + * This prepares the SW controllable LED for use.
8410 +static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
8412 + return e1e_wphy(hw, HV_LED_CONFIG,
8413 + (u16)hw->mac.ledctl_mode1);
8417 + * e1000_cleanup_led_pchlan - Restore the default LED operation
8418 + * @hw: pointer to the HW structure
8420 + * Return the LED back to the default configuration.
8422 +static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
8424 + return e1e_wphy(hw, HV_LED_CONFIG,
8425 + (u16)hw->mac.ledctl_default);
8429 + * e1000_led_on_pchlan - Turn LEDs on
8430 + * @hw: pointer to the HW structure
8432 + * Turn on the LEDs.
8434 +static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
8436 + u16 data = (u16)hw->mac.ledctl_mode2;
8440 + * If no link, then turn LED on by setting the invert bit
8441 + * for each LED that's mode is "link_up" in ledctl_mode2.
8443 + if (!(er32(STATUS) & E1000_STATUS_LU)) {
8444 + for (i = 0; i < 3; i++) {
8445 + led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
8446 + if ((led & E1000_PHY_LED0_MODE_MASK) !=
8447 + E1000_LEDCTL_MODE_LINK_UP)
8449 + if (led & E1000_PHY_LED0_IVRT)
8450 + data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
8452 + data |= (E1000_PHY_LED0_IVRT << (i * 5));
8456 + return e1e_wphy(hw, HV_LED_CONFIG, data);
8460 + * e1000_led_off_pchlan - Turn LEDs off
8461 + * @hw: pointer to the HW structure
8463 + * Turn off the LEDs.
8465 +static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
8467 + u16 data = (u16)hw->mac.ledctl_mode1;
8471 + * If no link, then turn LED off by clearing the invert bit
8472 + * for each LED that's mode is "link_up" in ledctl_mode1.
8474 + if (!(er32(STATUS) & E1000_STATUS_LU)) {
8475 + for (i = 0; i < 3; i++) {
8476 + led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
8477 + if ((led & E1000_PHY_LED0_MODE_MASK) !=
8478 + E1000_LEDCTL_MODE_LINK_UP)
8480 + if (led & E1000_PHY_LED0_IVRT)
8481 + data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
8483 + data |= (E1000_PHY_LED0_IVRT << (i * 5));
8487 + return e1e_wphy(hw, HV_LED_CONFIG, data);
8491 + * e1000_get_cfg_done_ich8lan - Read config done bit
8492 + * @hw: pointer to the HW structure
8494 + * Read the management control register for the config done bit for
8495 + * completion status. NOTE: silicon which is EEPROM-less will fail trying
8496 + * to read the config done bit, so an error is *ONLY* logged and returns
8497 + * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
8498 + * would not be able to be reset or change link.
8500 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
8502 + s32 ret_val = E1000_SUCCESS;
8505 + if (hw->mac.type >= e1000_pchlan) {
8506 + u32 status = er32(STATUS);
8508 + if (status & E1000_STATUS_PHYRA) {
8509 + ew32(STATUS, status &
8510 + ~E1000_STATUS_PHYRA);
8512 + e_dbg("PHY Reset Asserted not set - needs delay\n");
8515 + e1000e_get_cfg_done(hw);
8517 + /* If EEPROM is not marked present, init the IGP 3 PHY manually */
8518 + if ((hw->mac.type != e1000_ich10lan) &&
8519 + (hw->mac.type != e1000_pchlan)) {
8520 + if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
8521 + (hw->phy.type == e1000_phy_igp_3)) {
8522 + e1000_phy_init_script_igp3(hw);
8525 + if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
8526 + /* Maybe we should do a basic PHY config */
8527 + e_dbg("EEPROM not present\n");
8528 + ret_val = -E1000_ERR_CONFIG;
8536 + * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
8537 + * @hw: pointer to the HW structure
8539 + * In the case of a PHY power down to save power, or to turn off link during a
8540 + * driver unload, or wake on lan is not enabled, remove the link.
8542 +static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
8544 + /* If the management interface is not enabled, then power down */
8545 + if (!(hw->mac.ops.check_mng_mode(hw) ||
8546 + e1000_check_reset_block(hw)))
8547 + e1000_power_down_phy_copper(hw);
8553 + * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
8554 + * @hw: pointer to the HW structure
8556 + * Clears hardware counters specific to the silicon family and calls
8557 + * clear_hw_cntrs_generic to clear all general purpose counters.
8559 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
8563 + e1000e_clear_hw_cntrs_base(hw);
8579 + /* Clear PHY statistics registers */
8580 + if ((hw->phy.type == e1000_phy_82578) ||
8581 + (hw->phy.type == e1000_phy_82577)) {
8582 + e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
8583 + e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
8584 + e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
8585 + e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
8586 + e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
8587 + e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
8588 + e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
8589 + e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
8590 + e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
8591 + e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
8592 + e1e_rphy(hw, HV_DC_UPPER, &phy_data);
8593 + e1e_rphy(hw, HV_DC_LOWER, &phy_data);
8594 + e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
8595 + e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
8599 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.h linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.h
8600 --- linux-2.6.22-0/drivers/net/e1000e/e1000_ich8lan.h 1970-01-01 01:00:00.000000000 +0100
8601 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_ich8lan.h 2009-06-24 00:32:20.000000000 +0200
8603 +/*******************************************************************************
8605 + Intel PRO/1000 Linux driver
8606 + Copyright(c) 1999 - 2009 Intel Corporation.
8608 + This program is free software; you can redistribute it and/or modify it
8609 + under the terms and conditions of the GNU General Public License,
8610 + version 2, as published by the Free Software Foundation.
8612 + This program is distributed in the hope it will be useful, but WITHOUT
8613 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8614 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8617 + You should have received a copy of the GNU General Public License along with
8618 + this program; if not, write to the Free Software Foundation, Inc.,
8619 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8621 + The full GNU General Public License is included in this distribution in
8622 + the file called "COPYING".
8624 + Contact Information:
8625 + Linux NICS <linux.nics@intel.com>
8626 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
8627 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
8629 +*******************************************************************************/
8631 +#ifndef _E1000_ICH8LAN_H_
8632 +#define _E1000_ICH8LAN_H_
8634 +#define ICH_FLASH_GFPREG 0x0000
8635 +#define ICH_FLASH_HSFSTS 0x0004
8636 +#define ICH_FLASH_HSFCTL 0x0006
8637 +#define ICH_FLASH_FADDR 0x0008
8638 +#define ICH_FLASH_FDATA0 0x0010
8640 +/* Requires up to 10 seconds when MNG might be accessing part. */
8641 +#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
8642 +#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
8643 +#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
8644 +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
8645 +#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
8647 +#define ICH_CYCLE_READ 0
8648 +#define ICH_CYCLE_WRITE 2
8649 +#define ICH_CYCLE_ERASE 3
8651 +#define FLASH_GFPREG_BASE_MASK 0x1FFF
8652 +#define FLASH_SECTOR_ADDR_SHIFT 12
8654 +#define ICH_FLASH_SEG_SIZE_256 256
8655 +#define ICH_FLASH_SEG_SIZE_4K 4096
8656 +#define ICH_FLASH_SEG_SIZE_8K 8192
8657 +#define ICH_FLASH_SEG_SIZE_64K 65536
8658 +#define ICH_FLASH_SECTOR_SIZE 4096
8660 +#define ICH_FLASH_REG_MAPSIZE 0x00A0
8662 +#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
8663 +#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
8664 +/* FW established a valid mode */
8665 +#define E1000_ICH_FWSM_FW_VALID 0x00008000
8667 +#define E1000_ICH_MNG_IAMT_MODE 0x2
8669 +#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
8670 + (ID_LED_OFF1_OFF2 << 8) | \
8671 + (ID_LED_OFF1_ON2 << 4) | \
8672 + (ID_LED_DEF1_DEF2))
8674 +#define E1000_ICH_NVM_SIG_WORD 0x13
8675 +#define E1000_ICH_NVM_SIG_MASK 0xC000
8676 +#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
8677 +#define E1000_ICH_NVM_SIG_VALUE 0x80
8679 +#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
8681 +#define E1000_FEXTNVM_SW_CONFIG 1
8682 +#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
8684 +#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
8686 +#define E1000_ICH_RAR_ENTRIES 7
8688 +#define PHY_PAGE_SHIFT 5
8689 +#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
8690 + ((reg) & MAX_PHY_REG_ADDRESS))
8691 +#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
8692 +#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
8693 +#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
8694 +#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
8696 +#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
8697 +#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
8698 +#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
8699 +#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
8701 +/* PHY Wakeup Registers and defines */
8702 +#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
8703 +#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
8704 +#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
8705 +#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
8706 +#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
8707 +#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
8708 +#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
8709 +#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
8710 +#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
8712 +#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
8713 +#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
8714 +#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
8715 +#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
8716 +#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
8717 +#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
8718 +#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
8720 +#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
8721 +#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
8722 +#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
8723 +#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
8724 +#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
8725 +#define HV_SCC_LOWER PHY_REG(778, 17)
8726 +#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
8727 +#define HV_ECOL_LOWER PHY_REG(778, 19)
8728 +#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
8729 +#define HV_MCC_LOWER PHY_REG(778, 21)
8730 +#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
8731 +#define HV_LATECOL_LOWER PHY_REG(778, 24)
8732 +#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
8733 +#define HV_COLC_LOWER PHY_REG(778, 26)
8734 +#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
8735 +#define HV_DC_LOWER PHY_REG(778, 28)
8736 +#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
8737 +#define HV_TNCRS_LOWER PHY_REG(778, 30)
8740 + * Additional interrupts need to be handled for ICH family:
8741 + * DSW = The FW changed the status of the DISSW bit in FWSM
8742 + * PHYINT = The LAN connected device generates an interrupt
8743 + * EPRST = Manageability reset event
8745 +#define IMS_ICH_ENABLE_MASK (\
8747 + E1000_IMS_PHYINT | \
8750 +/* Additional interrupt register bit definitions */
8751 +#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
8752 +#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
8753 +#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
8755 +/* Security Processing bit Indication */
8756 +#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
8757 +#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
8758 +#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
8759 +#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
8760 +#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
8763 +void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
8765 +void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
8766 +void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
8767 +void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
8770 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_mac.c linux-2.6.22-10/drivers/net/e1000e/e1000_mac.c
8771 --- linux-2.6.22-0/drivers/net/e1000e/e1000_mac.c 1970-01-01 01:00:00.000000000 +0100
8772 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_mac.c 2009-06-24 00:32:20.000000000 +0200
8774 +/*******************************************************************************
8776 + Intel PRO/1000 Linux driver
8777 + Copyright(c) 1999 - 2009 Intel Corporation.
8779 + This program is free software; you can redistribute it and/or modify it
8780 + under the terms and conditions of the GNU General Public License,
8781 + version 2, as published by the Free Software Foundation.
8783 + This program is distributed in the hope it will be useful, but WITHOUT
8784 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8785 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8788 + You should have received a copy of the GNU General Public License along with
8789 + this program; if not, write to the Free Software Foundation, Inc.,
8790 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8792 + The full GNU General Public License is included in this distribution in
8793 + the file called "COPYING".
8795 + Contact Information:
8796 + Linux NICS <linux.nics@intel.com>
8797 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
8798 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
8800 +*******************************************************************************/
8804 +static u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
8805 +static s32 e1000_set_default_fc_generic(struct e1000_hw *hw);
8806 +static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw);
8807 +static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
8808 +static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
8809 +static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
8812 + * e1000_init_mac_ops_generic - Initialize MAC function pointers
8813 + * @hw: pointer to the HW structure
8815 + * Setups up the function pointers to no-op functions
8817 +void e1000_init_mac_ops_generic(struct e1000_hw *hw)
8819 + struct e1000_mac_info *mac = &hw->mac;
8820 + /* General Setup */
8821 + mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
8822 + mac->ops.read_mac_addr = e1000e_read_mac_addr_generic;
8823 + mac->ops.config_collision_dist = e1000e_config_collision_dist;
8825 + mac->ops.wait_autoneg = e1000_wait_autoneg;
8827 + mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
8828 + mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
8829 + mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
8830 + /* VLAN, MC, etc. */
8831 + mac->ops.rar_set = e1000e_rar_set;
8832 + mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
8836 + * e1000e_get_bus_info_pcie - Get PCIe bus information
8837 + * @hw: pointer to the HW structure
8839 + * Determines and stores the system bus information for a particular
8840 + * network interface. The following bus information is determined and stored:
8841 + * bus speed, bus width, type (PCIe), and PCIe function.
8843 +s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
8845 + struct e1000_mac_info *mac = &hw->mac;
8846 + struct e1000_bus_info *bus = &hw->bus;
8849 + u16 pcie_link_status;
8851 + bus->type = e1000_bus_type_pci_express;
8852 + bus->speed = e1000_bus_speed_2500;
8854 + ret_val = e1000_read_pcie_cap_reg(hw,
8856 + &pcie_link_status);
8858 + bus->width = e1000_bus_width_unknown;
8860 + bus->width = (enum e1000_bus_width)((pcie_link_status &
8861 + PCIE_LINK_WIDTH_MASK) >>
8862 + PCIE_LINK_WIDTH_SHIFT);
8864 + mac->ops.set_lan_id(hw);
8866 + return E1000_SUCCESS;
8870 + * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
8872 + * @hw: pointer to the HW structure
8874 + * Determines the LAN function id by reading memory-mapped registers
8875 + * and swaps the port value if requested.
8877 +static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
8879 + struct e1000_bus_info *bus = &hw->bus;
8883 + * The status register reports the correct function number
8884 + * for the device regardless of function swap state.
8886 + reg = er32(STATUS);
8887 + bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
8891 + * e1000_set_lan_id_single_port - Set LAN id for a single port device
8892 + * @hw: pointer to the HW structure
8894 + * Sets the LAN function id to zero for a single port device.
8896 +void e1000_set_lan_id_single_port(struct e1000_hw *hw)
8898 + struct e1000_bus_info *bus = &hw->bus;
8904 + * e1000e_clear_vfta_generic - Clear VLAN filter table
8905 + * @hw: pointer to the HW structure
8907 + * Clears the register array which contains the VLAN filter table by
8908 + * setting all the values to 0.
8910 +void e1000e_clear_vfta_generic(struct e1000_hw *hw)
8914 + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
8915 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
8921 + * e1000e_write_vfta_generic - Write value to VLAN filter table
8922 + * @hw: pointer to the HW structure
8923 + * @offset: register offset in VLAN filter table
8924 + * @value: register value written to VLAN filter table
8926 + * Writes value at the given offset in the register array which stores
8927 + * the VLAN filter table.
8929 +void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
8931 + E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
8936 + * e1000e_init_rx_addrs - Initialize receive address's
8937 + * @hw: pointer to the HW structure
8938 + * @rar_count: receive address registers
8940 + * Setups the receive address registers by setting the base receive address
8941 + * register to the devices MAC address and clearing all the other receive
8942 + * address registers to 0.
8944 +void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
8947 + u8 mac_addr[ETH_ADDR_LEN] = {0};
8949 + /* Setup the receive address */
8950 + e_dbg("Programming MAC Address into RAR[0]\n");
8952 + hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
8954 + /* Zero out the other (rar_entry_count - 1) receive addresses */
8955 + e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
8956 + for (i = 1; i < rar_count; i++)
8957 + hw->mac.ops.rar_set(hw, mac_addr, i);
8961 + * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
8962 + * @hw: pointer to the HW structure
8964 + * Checks the nvm for an alternate MAC address. An alternate MAC address
8965 + * can be setup by pre-boot software and must be treated like a permanent
8966 + * address and must override the actual permanent MAC address. If an
8967 + * alternate MAC address is found it is programmed into RAR0, replacing
8968 + * the permanent address that was installed into RAR0 by the Si on reset.
8969 + * This function will return SUCCESS unless it encounters an error while
8970 + * reading the EEPROM.
8972 +s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
8975 + s32 ret_val = E1000_SUCCESS;
8976 + u16 offset, nvm_alt_mac_addr_offset, nvm_data;
8977 + u8 alt_mac_addr[ETH_ADDR_LEN];
8979 + ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
8980 + &nvm_alt_mac_addr_offset);
8982 + e_dbg("NVM Read Error\n");
8986 + if (nvm_alt_mac_addr_offset == 0xFFFF) {
8987 + /* There is no Alternate MAC Address */
8991 + if (hw->bus.func == E1000_FUNC_1)
8992 + nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
8993 + for (i = 0; i < ETH_ADDR_LEN; i += 2) {
8994 + offset = nvm_alt_mac_addr_offset + (i >> 1);
8995 + ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
8997 + e_dbg("NVM Read Error\n");
9001 + alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
9002 + alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
9005 + /* if multicast bit is set, the alternate address will not be used */
9006 + if (alt_mac_addr[0] & 0x01) {
9007 + e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
9012 + * We have a valid alternate MAC address, and we want to treat it the
9013 + * same as the normal permanent MAC address stored by the HW into the
9014 + * RAR. Do this by mapping this address into RAR0.
9016 + hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
9023 + * e1000e_rar_set - Set receive address register
9024 + * @hw: pointer to the HW structure
9025 + * @addr: pointer to the receive address
9026 + * @index: receive address array register
9028 + * Sets the receive address array register at index to the address passed
9031 +void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
9033 + u32 rar_low, rar_high;
9036 + * HW expects these in little endian so we reverse the byte order
9037 + * from network order (big endian) to little endian
9039 + rar_low = ((u32) addr[0] |
9040 + ((u32) addr[1] << 8) |
9041 + ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
9043 + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
9045 + /* If MAC address zero, no need to set the AV bit */
9046 + if (rar_low || rar_high)
9047 + rar_high |= E1000_RAH_AV;
9050 + * Some bridges will combine consecutive 32-bit writes into
9051 + * a single burst write, which will malfunction on some parts.
9052 + * The flushes avoid this.
9054 + ew32(RAL(index), rar_low);
9056 + ew32(RAH(index), rar_high);
9061 + * e1000_mta_set_generic - Set multicast filter table address
9062 + * @hw: pointer to the HW structure
9063 + * @hash_value: determines the MTA register and bit to set
9065 + * The multicast table address is a register array of 32-bit registers.
9066 + * The hash_value is used to determine what register the bit is in, the
9067 + * current value is read, the new bit is OR'd in and the new value is
9068 + * written back into the register.
9070 +void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
9072 + u32 hash_bit, hash_reg, mta;
9075 + * The MTA is a register array of 32-bit registers. It is
9076 + * treated like an array of (32*mta_reg_count) bits. We want to
9077 + * set bit BitArray[hash_value]. So we figure out what register
9078 + * the bit is in, read it, OR in the new bit, then write
9079 + * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
9080 + * mask to bits 31:5 of the hash value which gives us the
9081 + * register we're modifying. The hash bit within that register
9082 + * is determined by the lower 5 bits of the hash value.
9084 + hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
9085 + hash_bit = hash_value & 0x1F;
9087 + mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
9089 + mta |= (1 << hash_bit);
9091 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
9096 + * e1000e_update_mc_addr_list_generic - Update Multicast addresses
9097 + * @hw: pointer to the HW structure
9098 + * @mc_addr_list: array of multicast addresses to program
9099 + * @mc_addr_count: number of multicast addresses to program
9101 + * Updates entire Multicast Table Array.
9102 + * The caller must have a packed mc_addr_list of multicast addresses.
9104 +void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
9105 + u8 *mc_addr_list, u32 mc_addr_count)
9107 + u32 hash_value, hash_bit, hash_reg;
9110 + /* clear mta_shadow */
9111 + memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9113 + /* update mta_shadow from mc_addr_list */
9114 + for (i = 0; (u32) i < mc_addr_count; i++) {
9115 + hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
9117 + hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
9118 + hash_bit = hash_value & 0x1F;
9120 + hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
9121 + mc_addr_list += (ETH_ADDR_LEN);
9124 + /* replace the entire MTA table */
9125 + for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
9126 + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
9131 + * e1000_hash_mc_addr_generic - Generate a multicast hash value
9132 + * @hw: pointer to the HW structure
9133 + * @mc_addr: pointer to a multicast address
9135 + * Generates a multicast address hash value which is used to determine
9136 + * the multicast filter table array address and new table value. See
9137 + * e1000_mta_set_generic()
9139 +static u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
9141 + u32 hash_value, hash_mask;
9144 + /* Register count multiplied by bits per register */
9145 + hash_mask = (hw->mac.mta_reg_count * 32) - 1;
9148 + * For a mc_filter_type of 0, bit_shift is the number of left-shifts
9149 + * where 0xFF would still fall within the hash mask.
9151 + while (hash_mask >> bit_shift != 0xFF)
9155 + * The portion of the address that is used for the hash table
9156 + * is determined by the mc_filter_type setting.
9157 + * The algorithm is such that there is a total of 8 bits of shifting.
9158 + * The bit_shift for a mc_filter_type of 0 represents the number of
9159 + * left-shifts where the MSB of mc_addr[5] would still fall within
9160 + * the hash_mask. Case 0 does this exactly. Since there are a total
9161 + * of 8 bits of shifting, then mc_addr[4] will shift right the
9162 + * remaining number of bits. Thus 8 - bit_shift. The rest of the
9163 + * cases are a variation of this algorithm...essentially raising the
9164 + * number of bits to shift mc_addr[5] left, while still keeping the
9165 + * 8-bit shifting total.
9167 + * For example, given the following Destination MAC Address and an
9168 + * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
9169 + * we can see that the bit_shift for case 0 is 4. These are the hash
9170 + * values resulting from each mc_filter_type...
9171 + * [0] [1] [2] [3] [4] [5]
9172 + * 01 AA 00 12 34 56
9175 + * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
9176 + * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
9177 + * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
9178 + * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
9180 + switch (hw->mac.mc_filter_type) {
9195 + hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
9196 + (((u16) mc_addr[5]) << bit_shift)));
9198 + return hash_value;
9202 + * e1000e_clear_hw_cntrs_base - Clear base hardware counters
9203 + * @hw: pointer to the HW structure
9205 + * Clears the base hardware counters by reading the counter registers.
9207 +void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
9248 + * e1000e_check_for_copper_link - Check for link (Copper)
9249 + * @hw: pointer to the HW structure
9251 + * Checks to see of the link status of the hardware has changed. If a
9252 + * change in link status has been detected, then we read the PHY registers
9253 + * to get the current speed/duplex if link exists.
9255 +s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
9257 + struct e1000_mac_info *mac = &hw->mac;
9262 + * We only want to go out to the PHY registers to see if Auto-Neg
9263 + * has completed and/or if our link status has changed. The
9264 + * get_link_status flag is set upon receiving a Link Status
9265 + * Change or Rx Sequence Error interrupt.
9267 + if (!mac->get_link_status) {
9268 + ret_val = E1000_SUCCESS;
9273 + * First we want to see if the MII Status Register reports
9274 + * link. If so, then we want to get the current speed/duplex
9277 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
9282 + goto out; /* No link detected */
9284 + mac->get_link_status = false;
9287 + * Check if there was DownShift, must be checked
9288 + * immediately after link-up
9290 + e1000e_check_downshift(hw);
9293 + * If we are forcing speed/duplex, then we simply return since
9294 + * we have already determined whether we have link or not.
9296 + if (!mac->autoneg) {
9297 + ret_val = -E1000_ERR_CONFIG;
9302 + * Auto-Neg is enabled. Auto Speed Detection takes care
9303 + * of MAC speed/duplex configuration. So we only need to
9304 + * configure Collision Distance in the MAC.
9306 + e1000e_config_collision_dist(hw);
9309 + * Configure Flow Control now that Auto-Neg has completed.
9310 + * First, we need to restore the desired flow control
9311 + * settings because we may have had to re-autoneg with a
9312 + * different link partner.
9314 + ret_val = e1000e_config_fc_after_link_up(hw);
9316 + e_dbg("Error configuring flow control\n");
9323 + * e1000e_check_for_fiber_link - Check for link (Fiber)
9324 + * @hw: pointer to the HW structure
9326 + * Checks for link up on the hardware. If link is not up and we have
9327 + * a signal, then we need to force link up.
9329 +s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
9331 + struct e1000_mac_info *mac = &hw->mac;
9335 + s32 ret_val = E1000_SUCCESS;
9337 + ctrl = er32(CTRL);
9338 + status = er32(STATUS);
9339 + rxcw = er32(RXCW);
9342 + * If we don't have link (auto-negotiation failed or link partner
9343 + * cannot auto-negotiate), the cable is plugged in (we have signal),
9344 + * and our link partner is not trying to auto-negotiate with us (we
9345 + * are receiving idles or data), we need to force link up. We also
9346 + * need to give auto-negotiation time to complete, in case the cable
9347 + * was just plugged in. The autoneg_failed flag does this.
9349 + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
9350 + if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
9351 + (!(rxcw & E1000_RXCW_C))) {
9352 + if (mac->autoneg_failed == 0) {
9353 + mac->autoneg_failed = 1;
9356 + e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
9358 + /* Disable auto-negotiation in the TXCW register */
9359 + ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
9361 + /* Force link-up and also force full-duplex. */
9362 + ctrl = er32(CTRL);
9363 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
9366 + /* Configure Flow Control after forcing link up. */
9367 + ret_val = e1000e_config_fc_after_link_up(hw);
9369 + e_dbg("Error configuring flow control\n");
9372 + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
9374 + * If we are forcing link and we are receiving /C/ ordered
9375 + * sets, re-enable auto-negotiation in the TXCW register
9376 + * and disable forced link in the Device Control register
9377 + * in an attempt to auto-negotiate with our link partner.
9379 + e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
9380 + ew32(TXCW, mac->txcw);
9381 + ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
9383 + mac->serdes_has_link = true;
9391 + * e1000e_check_for_serdes_link - Check for link (Serdes)
9392 + * @hw: pointer to the HW structure
9394 + * Checks for link up on the hardware. If link is not up and we have
9395 + * a signal, then we need to force link up.
9397 +s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
9399 + struct e1000_mac_info *mac = &hw->mac;
9403 + s32 ret_val = E1000_SUCCESS;
9405 + ctrl = er32(CTRL);
9406 + status = er32(STATUS);
9407 + rxcw = er32(RXCW);
9410 + * If we don't have link (auto-negotiation failed or link partner
9411 + * cannot auto-negotiate), and our link partner is not trying to
9412 + * auto-negotiate with us (we are receiving idles or data),
9413 + * we need to force link up. We also need to give auto-negotiation
9414 + * time to complete.
9416 + /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
9417 + if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
9418 + if (mac->autoneg_failed == 0) {
9419 + mac->autoneg_failed = 1;
9422 + e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
9424 + /* Disable auto-negotiation in the TXCW register */
9425 + ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
9427 + /* Force link-up and also force full-duplex. */
9428 + ctrl = er32(CTRL);
9429 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
9432 + /* Configure Flow Control after forcing link up. */
9433 + ret_val = e1000e_config_fc_after_link_up(hw);
9435 + e_dbg("Error configuring flow control\n");
9438 + } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
9440 + * If we are forcing link and we are receiving /C/ ordered
9441 + * sets, re-enable auto-negotiation in the TXCW register
9442 + * and disable forced link in the Device Control register
9443 + * in an attempt to auto-negotiate with our link partner.
9445 + e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
9446 + ew32(TXCW, mac->txcw);
9447 + ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
9449 + mac->serdes_has_link = true;
9450 + } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
9452 + * If we force link for non-auto-negotiation switch, check
9453 + * link status based on MAC synchronization for internal
9454 + * serdes media type.
9456 + /* SYNCH bit and IV bit are sticky. */
9458 + rxcw = er32(RXCW);
9459 + if (rxcw & E1000_RXCW_SYNCH) {
9460 + if (!(rxcw & E1000_RXCW_IV)) {
9461 + mac->serdes_has_link = true;
9462 + e_dbg("SERDES: Link up - forced.\n");
9465 + mac->serdes_has_link = false;
9466 + e_dbg("SERDES: Link down - force failed.\n");
9470 + if (E1000_TXCW_ANE & er32(TXCW)) {
9471 + status = er32(STATUS);
9472 + if (status & E1000_STATUS_LU) {
9473 + /* SYNCH bit and IV bit are sticky, so reread rxcw. */
9475 + rxcw = er32(RXCW);
9476 + if (rxcw & E1000_RXCW_SYNCH) {
9477 + if (!(rxcw & E1000_RXCW_IV)) {
9478 + mac->serdes_has_link = true;
9479 + e_dbg("SERDES: Link up - autoneg "
9480 + "completed sucessfully.\n");
9482 + mac->serdes_has_link = false;
9483 + e_dbg("SERDES: Link down - invalid"
9484 + "codewords detected in autoneg.\n");
9487 + mac->serdes_has_link = false;
9488 + e_dbg("SERDES: Link down - no sync.\n");
9491 + mac->serdes_has_link = false;
9492 + e_dbg("SERDES: Link down - autoneg failed\n");
9501 + * e1000e_setup_link - Setup flow control and link settings
9502 + * @hw: pointer to the HW structure
9504 + * Determines which flow control settings to use, then configures flow
9505 + * control. Calls the appropriate media-specific link configuration
9506 + * function. Assuming the adapter has a valid link partner, a valid link
9507 + * should be established. Assumes the hardware has previously been reset
9508 + * and the transmitter and receiver are not enabled.
9510 +s32 e1000e_setup_link(struct e1000_hw *hw)
9512 + s32 ret_val = E1000_SUCCESS;
9515 + * In the case of the phy reset being blocked, we already have a link.
9516 + * We do not need to set it up again.
9518 + if (hw->phy.ops.check_reset_block)
9519 + if (e1000_check_reset_block(hw))
9523 + * If requested flow control is set to default, set flow control
9524 + * based on the EEPROM flow control settings.
9526 + if (hw->fc.requested_mode == e1000_fc_default) {
9527 + ret_val = e1000_set_default_fc_generic(hw);
9533 + * Save off the requested flow control mode for use later. Depending
9534 + * on the link partner's capabilities, we may or may not use this mode.
9536 + hw->fc.current_mode = hw->fc.requested_mode;
9538 + e_dbg("After fix-ups FlowControl is now = %x\n",
9539 + hw->fc.current_mode);
9541 + /* Call the necessary media_type subroutine to configure the link. */
9542 + ret_val = hw->mac.ops.setup_physical_interface(hw);
9547 + * Initialize the flow control address, type, and PAUSE timer
9548 + * registers to their default values. This is done even if flow
9549 + * control is disabled, because it does not hurt anything to
9550 + * initialize these registers.
9552 + e_dbg("Initializing the Flow Control address, type and timer regs\n");
9553 + ew32(FCT, FLOW_CONTROL_TYPE);
9554 + ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
9555 + ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
9557 + ew32(FCTTV, hw->fc.pause_time);
9559 + ret_val = e1000e_set_fc_watermarks(hw);
9566 + * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
9567 + * @hw: pointer to the HW structure
9569 + * Configures collision distance and flow control for fiber and serdes
9570 + * links. Upon successful setup, poll for link.
9572 +s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
9575 + s32 ret_val = E1000_SUCCESS;
9577 + ctrl = er32(CTRL);
9579 + /* Take the link out of reset */
9580 + ctrl &= ~E1000_CTRL_LRST;
9582 + e1000e_config_collision_dist(hw);
9584 + ret_val = e1000_commit_fc_settings_generic(hw);
9589 + * Since auto-negotiation is enabled, take the link out of reset (the
9590 + * link will be in reset, because we previously reset the chip). This
9591 + * will restart auto-negotiation. If auto-negotiation is successful
9592 + * then the link-up status bit will be set and the flow control enable
9593 + * bits (RFCE and TFCE) will be set according to their negotiated value.
9595 + e_dbg("Auto-negotiation enabled\n");
9602 + * For these adapters, the SW definable pin 1 is set when the optics
9603 + * detect a signal. If we have a signal, then poll for a "Link-Up"
9606 + if (hw->phy.media_type == e1000_media_type_internal_serdes ||
9607 + (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
9608 + ret_val = e1000_poll_fiber_serdes_link_generic(hw);
9610 + e_dbg("No signal detected\n");
9618 + * e1000e_config_collision_dist - Configure collision distance
9619 + * @hw: pointer to the HW structure
9621 + * Configures the collision distance to the default value and is used
9622 + * during link setup. Currently no func pointer exists and all
9623 + * implementations are handled in the generic version of this function.
9625 +void e1000e_config_collision_dist(struct e1000_hw *hw)
9629 + tctl = er32(TCTL);
9631 + tctl &= ~E1000_TCTL_COLD;
9632 + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
9639 + * e1000_poll_fiber_serdes_link_generic - Poll for link up
9640 + * @hw: pointer to the HW structure
9642 + * Polls for link up by reading the status register, if link fails to come
9643 + * up with auto-negotiation, then the link is forced if a signal is detected.
9645 +static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
9647 + struct e1000_mac_info *mac = &hw->mac;
9649 + s32 ret_val = E1000_SUCCESS;
9652 + * If we have a signal (the cable is plugged in, or assumed true for
9653 + * serdes media) then poll for a "Link-Up" indication in the Device
9654 + * Status Register. Time-out if a link isn't seen in 500 milliseconds
9655 + * seconds (Auto-negotiation should complete in less than 500
9656 + * milliseconds even if the other end is doing it in SW).
9658 + for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
9660 + status = er32(STATUS);
9661 + if (status & E1000_STATUS_LU)
9664 + if (i == FIBER_LINK_UP_LIMIT) {
9665 + e_dbg("Never got a valid link from auto-neg!!!\n");
9666 + mac->autoneg_failed = 1;
9668 + * AutoNeg failed to achieve a link, so we'll call
9669 + * mac->check_for_link. This routine will force the
9670 + * link up if we detect a signal. This will allow us to
9671 + * communicate with non-autonegotiating link partners.
9673 + ret_val = hw->mac.ops.check_for_link(hw);
9675 + e_dbg("Error while checking for link\n");
9678 + mac->autoneg_failed = 0;
9680 + mac->autoneg_failed = 0;
9681 + e_dbg("Valid Link Found\n");
9689 + * e1000_commit_fc_settings_generic - Configure flow control
9690 + * @hw: pointer to the HW structure
9692 + * Write the flow control settings to the Transmit Config Word Register (TXCW)
9693 + * base on the flow control settings in e1000_mac_info.
9695 +static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
9697 + struct e1000_mac_info *mac = &hw->mac;
9699 + s32 ret_val = E1000_SUCCESS;
9702 + * Check for a software override of the flow control settings, and
9703 + * setup the device accordingly. If auto-negotiation is enabled, then
9704 + * software will have to set the "PAUSE" bits to the correct value in
9705 + * the Transmit Config Word Register (TXCW) and re-start auto-
9706 + * negotiation. However, if auto-negotiation is disabled, then
9707 + * software will have to manually configure the two flow control enable
9708 + * bits in the CTRL register.
9710 + * The possible values of the "fc" parameter are:
9711 + * 0: Flow control is completely disabled
9712 + * 1: Rx flow control is enabled (we can receive pause frames,
9713 + * but not send pause frames).
9714 + * 2: Tx flow control is enabled (we can send pause frames but we
9715 + * do not support receiving pause frames).
9716 + * 3: Both Rx and Tx flow control (symmetric) are enabled.
9718 + switch (hw->fc.current_mode) {
9719 + case e1000_fc_none:
9720 + /* Flow control completely disabled by a software over-ride. */
9721 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
9723 + case e1000_fc_rx_pause:
9725 + * Rx Flow control is enabled and Tx Flow control is disabled
9726 + * by a software over-ride. Since there really isn't a way to
9727 + * advertise that we are capable of Rx Pause ONLY, we will
9728 + * advertise that we support both symmetric and asymmetric RX
9729 + * PAUSE. Later, we will disable the adapter's ability to send
9732 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
9734 + case e1000_fc_tx_pause:
9736 + * Tx Flow control is enabled, and Rx Flow control is disabled,
9737 + * by a software over-ride.
9739 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
9741 + case e1000_fc_full:
9743 + * Flow control (both Rx and Tx) is enabled by a software
9746 + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
9749 + e_dbg("Flow control param set incorrectly\n");
9750 + ret_val = -E1000_ERR_CONFIG;
9763 + * e1000e_set_fc_watermarks - Set flow control high/low watermarks
9764 + * @hw: pointer to the HW structure
9766 + * Sets the flow control high/low threshold (watermark) registers. If
9767 + * flow control XON frame transmission is enabled, then set XON frame
9768 + * transmission as well.
9770 +s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
9772 + s32 ret_val = E1000_SUCCESS;
9773 + u32 fcrtl = 0, fcrth = 0;
9776 + * Set the flow control receive threshold registers. Normally,
9777 + * these registers will be set to a default threshold that may be
9778 + * adjusted later by the driver's runtime code. However, if the
9779 + * ability to transmit pause frames is not enabled, then these
9780 + * registers will be set to 0.
9782 + if (hw->fc.current_mode & e1000_fc_tx_pause) {
9784 + * We need to set up the Receive Threshold high and low water
9785 + * marks as well as (optionally) enabling the transmission of
9788 + fcrtl = hw->fc.low_water;
9789 + if (hw->fc.send_xon)
9790 + fcrtl |= E1000_FCRTL_XONE;
9792 + fcrth = hw->fc.high_water;
9794 + ew32(FCRTL, fcrtl);
9795 + ew32(FCRTH, fcrth);
9801 + * e1000_set_default_fc_generic - Set flow control default values
9802 + * @hw: pointer to the HW structure
9804 + * Read the EEPROM for the default values for flow control and store the
9807 +static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
9809 + s32 ret_val = E1000_SUCCESS;
9813 + * Read and store word 0x0F of the EEPROM. This word contains bits
9814 + * that determine the hardware's default PAUSE (flow control) mode,
9815 + * a bit that determines whether the HW defaults to enabling or
9816 + * disabling auto-negotiation, and the direction of the
9817 + * SW defined pins. If there is no SW over-ride of the flow
9818 + * control setting, then the variable hw->fc will
9819 + * be initialized based on a value in the EEPROM.
9821 + ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
9824 + e_dbg("NVM Read Error\n");
9828 + if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
9829 + hw->fc.requested_mode = e1000_fc_none;
9830 + else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
9831 + NVM_WORD0F_ASM_DIR)
9832 + hw->fc.requested_mode = e1000_fc_tx_pause;
9834 + hw->fc.requested_mode = e1000_fc_full;
9841 + * e1000e_force_mac_fc - Force the MAC's flow control settings
9842 + * @hw: pointer to the HW structure
9844 + * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
9845 + * device control register to reflect the adapter settings. TFCE and RFCE
9846 + * need to be explicitly set by software when a copper PHY is used because
9847 + * autonegotiation is managed by the PHY rather than the MAC. Software must
9848 + * also configure these bits when link is forced on a fiber connection.
9850 +s32 e1000e_force_mac_fc(struct e1000_hw *hw)
9853 + s32 ret_val = E1000_SUCCESS;
9855 + ctrl = er32(CTRL);
9858 + * Because we didn't get link via the internal auto-negotiation
9859 + * mechanism (we either forced link or we got link via PHY
9860 + * auto-neg), we have to manually enable/disable transmit an
9861 + * receive flow control.
9863 + * The "Case" statement below enables/disable flow control
9864 + * according to the "hw->fc.current_mode" parameter.
9866 + * The possible values of the "fc" parameter are:
9867 + * 0: Flow control is completely disabled
9868 + * 1: Rx flow control is enabled (we can receive pause
9869 + * frames but not send pause frames).
9870 + * 2: Tx flow control is enabled (we can send pause frames
9871 + * frames but we do not receive pause frames).
9872 + * 3: Both Rx and Tx flow control (symmetric) is enabled.
9873 + * other: No other values should be possible at this point.
9875 + e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
9877 + switch (hw->fc.current_mode) {
9878 + case e1000_fc_none:
9879 + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
9881 + case e1000_fc_rx_pause:
9882 + ctrl &= (~E1000_CTRL_TFCE);
9883 + ctrl |= E1000_CTRL_RFCE;
9885 + case e1000_fc_tx_pause:
9886 + ctrl &= (~E1000_CTRL_RFCE);
9887 + ctrl |= E1000_CTRL_TFCE;
9889 + case e1000_fc_full:
9890 + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
9893 + e_dbg("Flow control param set incorrectly\n");
9894 + ret_val = -E1000_ERR_CONFIG;
9905 + * e1000e_config_fc_after_link_up - Configures flow control after link
9906 + * @hw: pointer to the HW structure
9908 + * Checks the status of auto-negotiation after link up to ensure that the
9909 + * speed and duplex were not forced. If the link needed to be forced, then
9910 + * flow control needs to be forced also. If auto-negotiation is enabled
9911 + * and did not fail, then we configure flow control based on our link
9914 +s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
9916 + struct e1000_mac_info *mac = &hw->mac;
9917 + s32 ret_val = E1000_SUCCESS;
9918 + u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
9919 + u16 speed, duplex;
9922 + * Check for the case where we have fiber media and auto-neg failed
9923 + * so we had to force link. In this case, we need to force the
9924 + * configuration of the MAC to match the "fc" parameter.
9926 + if (mac->autoneg_failed) {
9927 + if (hw->phy.media_type == e1000_media_type_fiber ||
9928 + hw->phy.media_type == e1000_media_type_internal_serdes)
9929 + ret_val = e1000e_force_mac_fc(hw);
9931 + if (hw->phy.media_type == e1000_media_type_copper)
9932 + ret_val = e1000e_force_mac_fc(hw);
9936 + e_dbg("Error forcing flow control settings\n");
9941 + * Check for the case where we have copper media and auto-neg is
9942 + * enabled. In this case, we need to check and see if Auto-Neg
9943 + * has completed, and if so, how the PHY and link partner has
9944 + * flow control configured.
9946 + if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
9948 + * Read the MII Status Register and check to see if AutoNeg
9949 + * has completed. We read this twice because this reg has
9950 + * some "sticky" (latched) bits.
9952 + ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
9955 + ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
9959 + if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
9960 + e_dbg("Copper PHY and Auto Neg "
9961 + "has not completed.\n");
9966 + * The AutoNeg process has completed, so we now need to
9967 + * read both the Auto Negotiation Advertisement
9968 + * Register (Address 4) and the Auto_Negotiation Base
9969 + * Page Ability Register (Address 5) to determine how
9970 + * flow control was negotiated.
9972 + ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV,
9973 + &mii_nway_adv_reg);
9976 + ret_val = e1e_rphy(hw, PHY_LP_ABILITY,
9977 + &mii_nway_lp_ability_reg);
9982 + * Two bits in the Auto Negotiation Advertisement Register
9983 + * (Address 4) and two bits in the Auto Negotiation Base
9984 + * Page Ability Register (Address 5) determine flow control
9985 + * for both the PHY and the link partner. The following
9986 + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
9987 + * 1999, describes these PAUSE resolution bits and how flow
9988 + * control is determined based upon these settings.
9989 + * NOTE: DC = Don't Care
9991 + * LOCAL DEVICE | LINK PARTNER
9992 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
9993 + *-------|---------|-------|---------|--------------------
9994 + * 0 | 0 | DC | DC | e1000_fc_none
9995 + * 0 | 1 | 0 | DC | e1000_fc_none
9996 + * 0 | 1 | 1 | 0 | e1000_fc_none
9997 + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
9998 + * 1 | 0 | 0 | DC | e1000_fc_none
9999 + * 1 | DC | 1 | DC | e1000_fc_full
10000 + * 1 | 1 | 0 | 0 | e1000_fc_none
10001 + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
10003 + * Are both PAUSE bits set to 1? If so, this implies
10004 + * Symmetric Flow Control is enabled at both ends. The
10005 + * ASM_DIR bits are irrelevant per the spec.
10007 + * For Symmetric Flow Control:
10009 + * LOCAL DEVICE | LINK PARTNER
10010 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
10011 + *-------|---------|-------|---------|--------------------
10012 + * 1 | DC | 1 | DC | E1000_fc_full
10015 + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
10016 + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
10018 + * Now we need to check if the user selected Rx ONLY
10019 + * of pause frames. In this case, we had to advertise
10020 + * FULL flow control because we could not advertise RX
10021 + * ONLY. Hence, we must now check to see if we need to
10022 + * turn OFF the TRANSMISSION of PAUSE frames.
10024 + if (hw->fc.requested_mode == e1000_fc_full) {
10025 + hw->fc.current_mode = e1000_fc_full;
10026 + e_dbg("Flow Control = FULL.\r\n");
10028 + hw->fc.current_mode = e1000_fc_rx_pause;
10029 + e_dbg("Flow Control = "
10030 + "RX PAUSE frames only.\r\n");
10034 + * For receiving PAUSE frames ONLY.
10036 + * LOCAL DEVICE | LINK PARTNER
10037 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
10038 + *-------|---------|-------|---------|--------------------
10039 + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
10041 + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
10042 + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
10043 + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
10044 + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
10045 + hw->fc.current_mode = e1000_fc_tx_pause;
10046 + e_dbg("Flow Control = TX PAUSE frames only.\r\n");
10049 + * For transmitting PAUSE frames ONLY.
10051 + * LOCAL DEVICE | LINK PARTNER
10052 + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
10053 + *-------|---------|-------|---------|--------------------
10054 + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
10056 + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
10057 + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
10058 + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
10059 + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
10060 + hw->fc.current_mode = e1000_fc_rx_pause;
10061 + e_dbg("Flow Control = RX PAUSE frames only.\r\n");
10064 + * Per the IEEE spec, at this point flow control
10065 + * should be disabled.
10067 + hw->fc.current_mode = e1000_fc_none;
10068 + e_dbg("Flow Control = NONE.\r\n");
10072 + * Now we need to do one last check... If we auto-
10073 + * negotiated to HALF DUPLEX, flow control should not be
10074 + * enabled per IEEE 802.3 spec.
10076 + ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
10078 + e_dbg("Error getting link speed and duplex\n");
10082 + if (duplex == HALF_DUPLEX)
10083 + hw->fc.current_mode = e1000_fc_none;
10086 + * Now we call a subroutine to actually force the MAC
10087 + * controller to use the correct flow control settings.
10089 + ret_val = e1000e_force_mac_fc(hw);
10091 + e_dbg("Error forcing flow control settings\n");
10101 + * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
10102 + * @hw: pointer to the HW structure
10103 + * @speed: stores the current speed
10104 + * @duplex: stores the current duplex
10106 + * Read the status register for the current speed/duplex and store the current
10107 + * speed and duplex for copper connections.
10109 +s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
10114 + status = er32(STATUS);
10115 + if (status & E1000_STATUS_SPEED_1000) {
10116 + *speed = SPEED_1000;
10117 + e_dbg("1000 Mbs, ");
10118 + } else if (status & E1000_STATUS_SPEED_100) {
10119 + *speed = SPEED_100;
10120 + e_dbg("100 Mbs, ");
10122 + *speed = SPEED_10;
10123 + e_dbg("10 Mbs, ");
10126 + if (status & E1000_STATUS_FD) {
10127 + *duplex = FULL_DUPLEX;
10128 + e_dbg("Full Duplex\n");
10130 + *duplex = HALF_DUPLEX;
10131 + e_dbg("Half Duplex\n");
10134 + return E1000_SUCCESS;
10138 + * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
10139 + * @hw: pointer to the HW structure
10140 + * @speed: stores the current speed
10141 + * @duplex: stores the current duplex
10143 + * Sets the speed and duplex to gigabit full duplex (the only possible option)
10144 + * for fiber/serdes links.
10146 +s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
10147 + u16 *speed, u16 *duplex)
10149 + *speed = SPEED_1000;
10150 + *duplex = FULL_DUPLEX;
10152 + return E1000_SUCCESS;
10156 + * e1000e_get_hw_semaphore - Acquire hardware semaphore
10157 + * @hw: pointer to the HW structure
10159 + * Acquire the HW semaphore to access the PHY or NVM
10161 +s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
10164 + s32 ret_val = E1000_SUCCESS;
10165 + s32 timeout = hw->nvm.word_size + 1;
10168 + /* Get the SW semaphore */
10169 + while (i < timeout) {
10170 + swsm = er32(SWSM);
10171 + if (!(swsm & E1000_SWSM_SMBI))
10178 + if (i == timeout) {
10179 + e_dbg("Driver can't access device - SMBI bit is set.\n");
10180 + ret_val = -E1000_ERR_NVM;
10184 + /* Get the FW semaphore. */
10185 + for (i = 0; i < timeout; i++) {
10186 + swsm = er32(SWSM);
10187 + ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
10189 + /* Semaphore acquired if bit latched */
10190 + if (er32(SWSM) & E1000_SWSM_SWESMBI)
10196 + if (i == timeout) {
10197 + /* Release semaphores */
10198 + e1000e_put_hw_semaphore(hw);
10199 + e_dbg("Driver can't access the NVM\n");
10200 + ret_val = -E1000_ERR_NVM;
10209 + * e1000e_put_hw_semaphore - Release hardware semaphore
10210 + * @hw: pointer to the HW structure
10212 + * Release hardware semaphore used to access the PHY or NVM
10214 +void e1000e_put_hw_semaphore(struct e1000_hw *hw)
10218 + swsm = er32(SWSM);
10219 + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
10220 + ew32(SWSM, swsm);
10223 + * e1000e_get_auto_rd_done - Check for auto read completion
10224 + * @hw: pointer to the HW structure
10226 + * Check EEPROM for Auto Read done bit.
10228 +s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
10231 + s32 ret_val = E1000_SUCCESS;
10233 + while (i < AUTO_READ_DONE_TIMEOUT) {
10234 + if (er32(EECD) & E1000_EECD_AUTO_RD)
10240 + if (i == AUTO_READ_DONE_TIMEOUT) {
10241 + e_dbg("Auto read by HW from NVM has not completed.\n");
10242 + ret_val = -E1000_ERR_RESET;
10251 + * e1000e_valid_led_default - Verify a valid default LED config
10252 + * @hw: pointer to the HW structure
10253 + * @data: pointer to the NVM (EEPROM)
10255 + * Read the EEPROM for the current default LED configuration. If the
10256 + * LED configuration is not valid, set to a valid LED configuration.
10258 +s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
10262 + ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
10264 + e_dbg("NVM Read Error\n");
10268 + if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
10269 + *data = ID_LED_DEFAULT;
10276 + * e1000e_id_led_init -
10277 + * @hw: pointer to the HW structure
10280 +s32 e1000e_id_led_init(struct e1000_hw *hw)
10282 + struct e1000_mac_info *mac = &hw->mac;
10284 + const u32 ledctl_mask = 0x000000FF;
10285 + const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
10286 + const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
10287 + u16 data, i, temp;
10288 + const u16 led_mask = 0x0F;
10290 + ret_val = hw->nvm.ops.valid_led_default(hw, &data);
10294 + mac->ledctl_default = er32(LEDCTL);
10295 + mac->ledctl_mode1 = mac->ledctl_default;
10296 + mac->ledctl_mode2 = mac->ledctl_default;
10298 + for (i = 0; i < 4; i++) {
10299 + temp = (data >> (i << 2)) & led_mask;
10301 + case ID_LED_ON1_DEF2:
10302 + case ID_LED_ON1_ON2:
10303 + case ID_LED_ON1_OFF2:
10304 + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
10305 + mac->ledctl_mode1 |= ledctl_on << (i << 3);
10307 + case ID_LED_OFF1_DEF2:
10308 + case ID_LED_OFF1_ON2:
10309 + case ID_LED_OFF1_OFF2:
10310 + mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
10311 + mac->ledctl_mode1 |= ledctl_off << (i << 3);
10318 + case ID_LED_DEF1_ON2:
10319 + case ID_LED_ON1_ON2:
10320 + case ID_LED_OFF1_ON2:
10321 + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
10322 + mac->ledctl_mode2 |= ledctl_on << (i << 3);
10324 + case ID_LED_DEF1_OFF2:
10325 + case ID_LED_ON1_OFF2:
10326 + case ID_LED_OFF1_OFF2:
10327 + mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
10328 + mac->ledctl_mode2 |= ledctl_off << (i << 3);
10341 + * e1000_setup_led_generic - Configures SW controllable LED
10342 + * @hw: pointer to the HW structure
10344 + * This prepares the SW controllable LED for use and saves the current state
10345 + * of the LED so it can be later restored.
10347 +s32 e1000_setup_led_generic(struct e1000_hw *hw)
10350 + s32 ret_val = E1000_SUCCESS;
10352 + if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
10353 + ret_val = -E1000_ERR_CONFIG;
10357 + if (hw->phy.media_type == e1000_media_type_fiber) {
10358 + ledctl = er32(LEDCTL);
10359 + hw->mac.ledctl_default = ledctl;
10360 + /* Turn off LED0 */
10361 + ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
10362 + E1000_LEDCTL_LED0_BLINK |
10363 + E1000_LEDCTL_LED0_MODE_MASK);
10364 + ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
10365 + E1000_LEDCTL_LED0_MODE_SHIFT);
10366 + ew32(LEDCTL, ledctl);
10367 + } else if (hw->phy.media_type == e1000_media_type_copper) {
10368 + ew32(LEDCTL, hw->mac.ledctl_mode1);
10376 + * e1000e_cleanup_led_generic - Set LED config to default operation
10377 + * @hw: pointer to the HW structure
10379 + * Remove the current LED configuration and set the LED configuration
10380 + * to the default value, saved from the EEPROM.
10382 +s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
10384 + s32 ret_val = E1000_SUCCESS;
10386 + if (hw->mac.ops.cleanup_led != e1000e_cleanup_led_generic) {
10387 + ret_val = -E1000_ERR_CONFIG;
10391 + ew32(LEDCTL, hw->mac.ledctl_default);
10398 + * e1000e_blink_led - Blink LED
10399 + * @hw: pointer to the HW structure
10401 + * Blink the LEDs which are set to be on.
10403 +s32 e1000e_blink_led(struct e1000_hw *hw)
10405 + u32 ledctl_blink = 0;
10408 + if (hw->phy.media_type == e1000_media_type_fiber) {
10409 + /* always blink LED0 for PCI-E fiber */
10410 + ledctl_blink = E1000_LEDCTL_LED0_BLINK |
10411 + (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
10414 + * set the blink bit for each LED that's "on" (0x0E)
10415 + * in ledctl_mode2
10417 + ledctl_blink = hw->mac.ledctl_mode2;
10418 + for (i = 0; i < 4; i++)
10419 + if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
10420 + E1000_LEDCTL_MODE_LED_ON)
10421 + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
10425 + ew32(LEDCTL, ledctl_blink);
10427 + return E1000_SUCCESS;
10431 + * e1000e_led_on_generic - Turn LED on
10432 + * @hw: pointer to the HW structure
10436 +s32 e1000e_led_on_generic(struct e1000_hw *hw)
10440 + switch (hw->phy.media_type) {
10441 + case e1000_media_type_fiber:
10442 + ctrl = er32(CTRL);
10443 + ctrl &= ~E1000_CTRL_SWDPIN0;
10444 + ctrl |= E1000_CTRL_SWDPIO0;
10445 + ew32(CTRL, ctrl);
10447 + case e1000_media_type_copper:
10448 + ew32(LEDCTL, hw->mac.ledctl_mode2);
10454 + return E1000_SUCCESS;
10458 + * e1000e_led_off_generic - Turn LED off
10459 + * @hw: pointer to the HW structure
10463 +s32 e1000e_led_off_generic(struct e1000_hw *hw)
10467 + switch (hw->phy.media_type) {
10468 + case e1000_media_type_fiber:
10469 + ctrl = er32(CTRL);
10470 + ctrl |= E1000_CTRL_SWDPIN0;
10471 + ctrl |= E1000_CTRL_SWDPIO0;
10472 + ew32(CTRL, ctrl);
10474 + case e1000_media_type_copper:
10475 + ew32(LEDCTL, hw->mac.ledctl_mode1);
10481 + return E1000_SUCCESS;
10485 + * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
10486 + * @hw: pointer to the HW structure
10487 + * @no_snoop: bitmap of snoop events
10489 + * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
10491 +void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
10495 + if (hw->bus.type != e1000_bus_type_pci_express)
10500 + gcr &= ~(PCIE_NO_SNOOP_ALL);
10509 + * e1000e_disable_pcie_master - Disables PCI-express master access
10510 + * @hw: pointer to the HW structure
10512 + * Returns 0 (E1000_SUCCESS) if successful, else returns -10
10513 + * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
10514 + * the master requests to be disabled.
10516 + * Disables PCI-Express master access and verifies there are no pending
10519 +s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
10522 + s32 timeout = MASTER_DISABLE_TIMEOUT;
10523 + s32 ret_val = E1000_SUCCESS;
10525 + if (hw->bus.type != e1000_bus_type_pci_express)
10528 + ctrl = er32(CTRL);
10529 + ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
10530 + ew32(CTRL, ctrl);
10532 + while (timeout) {
10533 + if (!(er32(STATUS) &
10534 + E1000_STATUS_GIO_MASTER_ENABLE))
10541 + e_dbg("Master requests are pending.\n");
10542 + ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
10551 + * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
10552 + * @hw: pointer to the HW structure
10554 + * Reset the Adaptive Interframe Spacing throttle to default values.
10556 +void e1000e_reset_adaptive(struct e1000_hw *hw)
10558 + struct e1000_mac_info *mac = &hw->mac;
10560 + if (!mac->adaptive_ifs) {
10561 + e_dbg("Not in Adaptive IFS mode!\n");
10565 + mac->current_ifs_val = 0;
10566 + mac->ifs_min_val = IFS_MIN;
10567 + mac->ifs_max_val = IFS_MAX;
10568 + mac->ifs_step_size = IFS_STEP;
10569 + mac->ifs_ratio = IFS_RATIO;
10571 + mac->in_ifs_mode = false;
10578 + * e1000e_update_adaptive - Update Adaptive Interframe Spacing
10579 + * @hw: pointer to the HW structure
10581 + * Update the Adaptive Interframe Spacing Throttle value based on the
10582 + * time between transmitted packets and time between collisions.
10584 +void e1000e_update_adaptive(struct e1000_hw *hw)
10586 + struct e1000_mac_info *mac = &hw->mac;
10588 + if (!mac->adaptive_ifs) {
10589 + e_dbg("Not in Adaptive IFS mode!\n");
10593 + if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
10594 + if (mac->tx_packet_delta > MIN_NUM_XMITS) {
10595 + mac->in_ifs_mode = true;
10596 + if (mac->current_ifs_val < mac->ifs_max_val) {
10597 + if (!mac->current_ifs_val)
10598 + mac->current_ifs_val = mac->ifs_min_val;
10600 + mac->current_ifs_val +=
10601 + mac->ifs_step_size;
10602 + ew32(AIT, mac->current_ifs_val);
10606 + if (mac->in_ifs_mode &&
10607 + (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
10608 + mac->current_ifs_val = 0;
10609 + mac->in_ifs_mode = false;
10618 + * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
10619 + * @hw: pointer to the HW structure
10621 + * Verify that when not using auto-negotiation that MDI/MDIx is correctly
10622 + * set, which is forced to MDI mode only.
10624 +s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
10626 + s32 ret_val = E1000_SUCCESS;
10628 + if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
10629 + e_dbg("Invalid MDI setting detected\n");
10630 + hw->phy.mdix = 1;
10631 + ret_val = -E1000_ERR_CONFIG;
10638 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_mac.h linux-2.6.22-10/drivers/net/e1000e/e1000_mac.h
10639 --- linux-2.6.22-0/drivers/net/e1000e/e1000_mac.h 1970-01-01 01:00:00.000000000 +0100
10640 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_mac.h 2009-06-24 00:32:20.000000000 +0200
10642 +/*******************************************************************************
10644 + Intel PRO/1000 Linux driver
10645 + Copyright(c) 1999 - 2009 Intel Corporation.
10647 + This program is free software; you can redistribute it and/or modify it
10648 + under the terms and conditions of the GNU General Public License,
10649 + version 2, as published by the Free Software Foundation.
10651 + This program is distributed in the hope it will be useful, but WITHOUT
10652 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10653 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10656 + You should have received a copy of the GNU General Public License along with
10657 + this program; if not, write to the Free Software Foundation, Inc.,
10658 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
10660 + The full GNU General Public License is included in this distribution in
10661 + the file called "COPYING".
10663 + Contact Information:
10664 + Linux NICS <linux.nics@intel.com>
10665 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
10666 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10668 +*******************************************************************************/
10670 +#ifndef _E1000_MAC_H_
10671 +#define _E1000_MAC_H_
10674 + * Functions that should not be called directly from drivers but can be used
10675 + * by other files in this 'shared code'
10677 +void e1000_init_mac_ops_generic(struct e1000_hw *hw);
10678 +s32 e1000e_blink_led(struct e1000_hw *hw);
10679 +s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
10680 +s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
10681 +s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
10682 +s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
10683 +s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
10684 +s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
10685 +s32 e1000e_force_mac_fc(struct e1000_hw *hw);
10686 +s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
10687 +s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
10688 +void e1000_set_lan_id_single_port(struct e1000_hw *hw);
10689 +s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
10690 +s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
10692 +s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
10693 + u16 *speed, u16 *duplex);
10694 +s32 e1000e_id_led_init(struct e1000_hw *hw);
10695 +s32 e1000e_led_on_generic(struct e1000_hw *hw);
10696 +s32 e1000e_led_off_generic(struct e1000_hw *hw);
10697 +void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
10698 + u8 *mc_addr_list, u32 mc_addr_count);
10699 +s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
10700 +s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
10701 +s32 e1000_setup_led_generic(struct e1000_hw *hw);
10702 +s32 e1000e_setup_link(struct e1000_hw *hw);
10704 +void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
10705 +void e1000e_clear_vfta_generic(struct e1000_hw *hw);
10706 +void e1000e_config_collision_dist(struct e1000_hw *hw);
10707 +void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
10708 +void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
10709 +void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
10710 +void e1000e_put_hw_semaphore(struct e1000_hw *hw);
10711 +void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
10712 +s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
10713 +void e1000e_reset_adaptive(struct e1000_hw *hw);
10714 +void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
10715 +void e1000e_update_adaptive(struct e1000_hw *hw);
10716 +void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
10719 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_manage.c linux-2.6.22-10/drivers/net/e1000e/e1000_manage.c
10720 --- linux-2.6.22-0/drivers/net/e1000e/e1000_manage.c 1970-01-01 01:00:00.000000000 +0100
10721 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_manage.c 2009-06-24 00:32:20.000000000 +0200
10723 +/*******************************************************************************
10725 + Intel PRO/1000 Linux driver
10726 + Copyright(c) 1999 - 2009 Intel Corporation.
10728 + This program is free software; you can redistribute it and/or modify it
10729 + under the terms and conditions of the GNU General Public License,
10730 + version 2, as published by the Free Software Foundation.
10732 + This program is distributed in the hope it will be useful, but WITHOUT
10733 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10734 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10737 + You should have received a copy of the GNU General Public License along with
10738 + this program; if not, write to the Free Software Foundation, Inc.,
10739 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
10741 + The full GNU General Public License is included in this distribution in
10742 + the file called "COPYING".
10744 + Contact Information:
10745 + Linux NICS <linux.nics@intel.com>
10746 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
10747 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10749 +*******************************************************************************/
10751 +#include "e1000.h"
10753 +static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
10756 + * e1000_calculate_checksum - Calculate checksum for buffer
10757 + * @buffer: pointer to EEPROM
10758 + * @length: size of EEPROM to calculate a checksum for
10760 + * Calculates the checksum for some buffer on a specified length. The
10761 + * checksum calculated is returned.
10763 +static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
10770 + for (i = 0; i < length; i++)
10771 + sum += buffer[i];
10773 + return (u8) (0 - sum);
10777 + * e1000_mng_enable_host_if_generic - Checks host interface is enabled
10778 + * @hw: pointer to the HW structure
10780 + * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
10782 + * This function checks whether the HOST IF is enabled for command operation
10783 + * and also checks whether the previous command is completed. It busy waits
10784 + * in case of previous command is not completed.
10786 +s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
10789 + s32 ret_val = E1000_SUCCESS;
10792 + /* Check that the host interface is enabled. */
10793 + hicr = er32(HICR);
10794 + if ((hicr & E1000_HICR_EN) == 0) {
10795 + e_dbg("E1000_HOST_EN bit disabled.\n");
10796 + ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
10799 + /* check the previous command is completed */
10800 + for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
10801 + hicr = er32(HICR);
10802 + if (!(hicr & E1000_HICR_C))
10807 + if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
10808 + e_dbg("Previous command timeout failed .\n");
10809 + ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
10818 + * e1000_check_mng_mode_generic - Generic check management mode
10819 + * @hw: pointer to the HW structure
10821 + * Reads the firmware semaphore register and returns true (>0) if
10822 + * manageability is enabled, else false (0).
10824 +bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
10828 + fwsm = er32(FWSM);
10829 + return (fwsm & E1000_FWSM_MODE_MASK) ==
10830 + (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
10833 + * e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX
10834 + * @hw: pointer to the HW structure
10836 + * Enables packet filtering on transmit packets if manageability is enabled
10837 + * and host interface is enabled.
10839 +bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
10841 + struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
10842 + u32 *buffer = (u32 *)&hw->mng_cookie;
10844 + s32 ret_val, hdr_csum, csum;
10846 + bool tx_filter = true;
10848 + /* No manageability, no filtering */
10849 + if (!hw->mac.ops.check_mng_mode(hw)) {
10850 + tx_filter = false;
10855 + * If we can't read from the host interface for whatever
10856 + * reason, disable filtering.
10858 + ret_val = hw->mac.ops.mng_enable_host_if(hw);
10859 + if (ret_val != E1000_SUCCESS) {
10860 + tx_filter = false;
10864 + /* Read in the header. Length and offset are in dwords. */
10865 + len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
10866 + offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
10867 + for (i = 0; i < len; i++) {
10868 + *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
10872 + hdr_csum = hdr->checksum;
10873 + hdr->checksum = 0;
10874 + csum = e1000_calculate_checksum((u8 *)hdr,
10875 + E1000_MNG_DHCP_COOKIE_LENGTH);
10877 + * If either the checksums or signature don't match, then
10878 + * the cookie area isn't considered valid, in which case we
10879 + * take the safe route of assuming Tx filtering is enabled.
10881 + if (hdr_csum != csum)
10883 + if (hdr->signature != E1000_IAMT_SIGNATURE)
10886 + /* Cookie area is valid, make the final check for filtering. */
10887 + if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
10888 + tx_filter = false;
10891 + hw->mac.tx_pkt_filtering = tx_filter;
10892 + return tx_filter;
10896 + * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
10897 + * @hw: pointer to the HW structure
10898 + * @buffer: pointer to the host interface
10899 + * @length: size of the buffer
10901 + * Writes the DHCP information to the host interface.
10903 +s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
10906 + struct e1000_host_mng_command_header hdr;
10910 + hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
10911 + hdr.command_length = length;
10912 + hdr.reserved1 = 0;
10913 + hdr.reserved2 = 0;
10914 + hdr.checksum = 0;
10916 + /* Enable the host interface */
10917 + ret_val = hw->mac.ops.mng_enable_host_if(hw);
10921 + /* Populate the host interface with the contents of "buffer". */
10922 + ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
10923 + sizeof(hdr), &(hdr.checksum));
10927 + /* Write the manageability command header */
10928 + ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
10932 + /* Tell the ARC a new command is pending. */
10933 + hicr = er32(HICR);
10934 + ew32(HICR, hicr | E1000_HICR_C);
10941 + * e1000_mng_write_cmd_header_generic - Writes manageability command header
10942 + * @hw: pointer to the HW structure
10943 + * @hdr: pointer to the host interface command header
10945 + * Writes the command header after does the checksum calculation.
10947 +s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
10948 + struct e1000_host_mng_command_header *hdr)
10950 + u16 i, length = sizeof(struct e1000_host_mng_command_header);
10952 + /* Write the whole command header structure with new checksum. */
10954 + hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
10957 + /* Write the relevant command block into the ram area. */
10958 + for (i = 0; i < length; i++) {
10959 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
10960 + *((u32 *) hdr + i));
10964 + return E1000_SUCCESS;
10968 + * e1000_mng_host_if_write_generic - Write to the manageability host interface
10969 + * @hw: pointer to the HW structure
10970 + * @buffer: pointer to the host interface buffer
10971 + * @length: size of the buffer
10972 + * @offset: location in the buffer to write to
10973 + * @sum: sum of the data (not checksum)
10975 + * This function writes the buffer content at the offset given on the host if.
10976 + * It also does alignment considerations to do the writes in most efficient
10977 + * way. Also fills up the sum of the buffer in *buffer parameter.
10979 +s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
10980 + u16 length, u16 offset, u8 *sum)
10983 + u8 *bufptr = buffer;
10985 + s32 ret_val = E1000_SUCCESS;
10986 + u16 remaining, i, j, prev_bytes;
10988 + /* sum = only sum of the data and it is not checksum */
10990 + if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
10991 + ret_val = -E1000_ERR_PARAM;
10995 + tmp = (u8 *)&data;
10996 + prev_bytes = offset & 0x3;
10999 + if (prev_bytes) {
11000 + data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
11001 + for (j = prev_bytes; j < sizeof(u32); j++) {
11002 + *(tmp + j) = *bufptr++;
11003 + *sum += *(tmp + j);
11005 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
11006 + length -= j - prev_bytes;
11010 + remaining = length & 0x3;
11011 + length -= remaining;
11013 + /* Calculate length in DWORDs */
11017 + * The device driver writes the relevant command block into the
11020 + for (i = 0; i < length; i++) {
11021 + for (j = 0; j < sizeof(u32); j++) {
11022 + *(tmp + j) = *bufptr++;
11023 + *sum += *(tmp + j);
11026 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
11030 + for (j = 0; j < sizeof(u32); j++) {
11031 + if (j < remaining)
11032 + *(tmp + j) = *bufptr++;
11036 + *sum += *(tmp + j);
11038 + E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
11046 + * e1000e_enable_mng_pass_thru - Enable processing of ARP's
11047 + * @hw: pointer to the HW structure
11049 + * Verifies the hardware needs to allow ARPs to be processed by the host.
11051 +bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
11054 + u32 fwsm, factps;
11055 + bool ret_val = false;
11057 + if (!hw->mac.asf_firmware_present)
11060 + manc = er32(MANC);
11062 + if (!(manc & E1000_MANC_RCV_TCO_EN) ||
11063 + !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
11066 + if (hw->mac.arc_subsystem_valid) {
11067 + fwsm = er32(FWSM);
11068 + factps = er32(FACTPS);
11070 + if (!(factps & E1000_FACTPS_MNGCG) &&
11071 + ((fwsm & E1000_FWSM_MODE_MASK) ==
11072 + (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
11077 + if ((manc & E1000_MANC_SMBUS_EN) &&
11078 + !(manc & E1000_MANC_ASF_EN)) {
11088 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_manage.h linux-2.6.22-10/drivers/net/e1000e/e1000_manage.h
11089 --- linux-2.6.22-0/drivers/net/e1000e/e1000_manage.h 1970-01-01 01:00:00.000000000 +0100
11090 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_manage.h 2009-06-24 00:32:20.000000000 +0200
11092 +/*******************************************************************************
11094 + Intel PRO/1000 Linux driver
11095 + Copyright(c) 1999 - 2009 Intel Corporation.
11097 + This program is free software; you can redistribute it and/or modify it
11098 + under the terms and conditions of the GNU General Public License,
11099 + version 2, as published by the Free Software Foundation.
11101 + This program is distributed in the hope it will be useful, but WITHOUT
11102 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11103 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11106 + You should have received a copy of the GNU General Public License along with
11107 + this program; if not, write to the Free Software Foundation, Inc.,
11108 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11110 + The full GNU General Public License is included in this distribution in
11111 + the file called "COPYING".
11113 + Contact Information:
11114 + Linux NICS <linux.nics@intel.com>
11115 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11116 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11118 +*******************************************************************************/
11120 +#ifndef _E1000_MANAGE_H_
11121 +#define _E1000_MANAGE_H_
11123 +bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
11124 +bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
11125 +s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
11126 +s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
11127 + u16 length, u16 offset, u8 *sum);
11128 +s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
11129 + struct e1000_host_mng_command_header *hdr);
11130 +s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw,
11131 + u8 *buffer, u16 length);
11132 +bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
11134 +enum e1000_mng_mode {
11135 + e1000_mng_mode_none = 0,
11136 + e1000_mng_mode_asf,
11137 + e1000_mng_mode_pt,
11138 + e1000_mng_mode_ipmi,
11139 + e1000_mng_mode_host_if_only
11142 +#define E1000_FACTPS_MNGCG 0x20000000
11144 +#define E1000_FWSM_MODE_MASK 0xE
11145 +#define E1000_FWSM_MODE_SHIFT 1
11147 +#define E1000_MNG_IAMT_MODE 0x3
11148 +#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
11149 +#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
11150 +#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
11151 +#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
11152 +#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
11153 +#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
11155 +#define E1000_VFTA_ENTRY_SHIFT 5
11156 +#define E1000_VFTA_ENTRY_MASK 0x7F
11157 +#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
11159 +#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
11160 +#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
11161 +#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
11163 +#define E1000_HICR_EN 0x01 /* Enable bit - RO */
11164 +/* Driver sets this bit when done to put command in RAM */
11165 +#define E1000_HICR_C 0x02
11166 +#define E1000_HICR_SV 0x04 /* Status Validity */
11167 +#define E1000_HICR_FW_RESET_ENABLE 0x40
11168 +#define E1000_HICR_FW_RESET 0x80
11170 +/* Intel(R) Active Management Technology signature */
11171 +#define E1000_IAMT_SIGNATURE 0x544D4149
11174 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.c linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.c
11175 --- linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.c 1970-01-01 01:00:00.000000000 +0100
11176 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.c 2009-06-24 00:32:20.000000000 +0200
11178 +/*******************************************************************************
11180 + Intel PRO/1000 Linux driver
11181 + Copyright(c) 1999 - 2009 Intel Corporation.
11183 + This program is free software; you can redistribute it and/or modify it
11184 + under the terms and conditions of the GNU General Public License,
11185 + version 2, as published by the Free Software Foundation.
11187 + This program is distributed in the hope it will be useful, but WITHOUT
11188 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11189 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11192 + You should have received a copy of the GNU General Public License along with
11193 + this program; if not, write to the Free Software Foundation, Inc.,
11194 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11196 + The full GNU General Public License is included in this distribution in
11197 + the file called "COPYING".
11199 + Contact Information:
11200 + Linux NICS <linux.nics@intel.com>
11201 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11202 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11204 +*******************************************************************************/
11206 +#include "e1000.h"
11208 +static void e1000_stop_nvm(struct e1000_hw *hw);
11209 +static void e1000e_reload_nvm(struct e1000_hw *hw);
11212 + * e1000_init_nvm_ops_generic - Initialize NVM function pointers
11213 + * @hw: pointer to the HW structure
11215 + * Setups up the function pointers to no-op functions
11217 +void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
11219 + struct e1000_nvm_info *nvm = &hw->nvm;
11220 + /* Initialize function pointers */
11221 + nvm->ops.reload = e1000e_reload_nvm;
11225 + * e1000_raise_eec_clk - Raise EEPROM clock
11226 + * @hw: pointer to the HW structure
11227 + * @eecd: pointer to the EEPROM
11229 + * Enable/Raise the EEPROM clock bit.
11231 +static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
11233 + *eecd = *eecd | E1000_EECD_SK;
11234 + ew32(EECD, *eecd);
11236 + udelay(hw->nvm.delay_usec);
11240 + * e1000_lower_eec_clk - Lower EEPROM clock
11241 + * @hw: pointer to the HW structure
11242 + * @eecd: pointer to the EEPROM
11244 + * Clear/Lower the EEPROM clock bit.
11246 +static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
11248 + *eecd = *eecd & ~E1000_EECD_SK;
11249 + ew32(EECD, *eecd);
11251 + udelay(hw->nvm.delay_usec);
11255 + * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
11256 + * @hw: pointer to the HW structure
11257 + * @data: data to send to the EEPROM
11258 + * @count: number of bits to shift out
11260 + * We need to shift 'count' bits out to the EEPROM. So, the value in the
11261 + * "data" parameter will be shifted out to the EEPROM one bit at a time.
11262 + * In order to do this, "data" must be broken down into bits.
11264 +static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
11266 + struct e1000_nvm_info *nvm = &hw->nvm;
11267 + u32 eecd = er32(EECD);
11270 + mask = 0x01 << (count - 1);
11271 + if (nvm->type == e1000_nvm_eeprom_spi)
11272 + eecd |= E1000_EECD_DO;
11275 + eecd &= ~E1000_EECD_DI;
11278 + eecd |= E1000_EECD_DI;
11280 + ew32(EECD, eecd);
11283 + udelay(nvm->delay_usec);
11285 + e1000_raise_eec_clk(hw, &eecd);
11286 + e1000_lower_eec_clk(hw, &eecd);
11291 + eecd &= ~E1000_EECD_DI;
11292 + ew32(EECD, eecd);
11296 + * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
11297 + * @hw: pointer to the HW structure
11298 + * @count: number of bits to shift in
11300 + * In order to read a register from the EEPROM, we need to shift 'count' bits
11301 + * in from the EEPROM. Bits are "shifted in" by raising the clock input to
11302 + * the EEPROM (setting the SK bit), and then reading the value of the data out
11303 + * "DO" bit. During this "shifting in" process the data in "DI" bit should
11304 + * always be clear.
11306 +static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
11312 + eecd = er32(EECD);
11313 + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
11316 + for (i = 0; i < count; i++) {
11318 + e1000_raise_eec_clk(hw, &eecd);
11320 + eecd = er32(EECD);
11322 + eecd &= ~E1000_EECD_DI;
11323 + if (eecd & E1000_EECD_DO)
11326 + e1000_lower_eec_clk(hw, &eecd);
11333 + * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
11334 + * @hw: pointer to the HW structure
11335 + * @ee_reg: EEPROM flag for polling
11337 + * Polls the EEPROM status bit for either read or write completion based
11338 + * upon the value of 'ee_reg'.
11340 +s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
11342 + u32 attempts = 100000;
11344 + s32 ret_val = -E1000_ERR_NVM;
11346 + for (i = 0; i < attempts; i++) {
11347 + if (ee_reg == E1000_NVM_POLL_READ)
11348 + reg = er32(EERD);
11350 + reg = er32(EEWR);
11352 + if (reg & E1000_NVM_RW_REG_DONE) {
11353 + ret_val = E1000_SUCCESS;
11364 + * e1000e_acquire_nvm - Generic request for access to EEPROM
11365 + * @hw: pointer to the HW structure
11367 + * Set the EEPROM access request bit and wait for EEPROM access grant bit.
11368 + * Return successful if access grant bit set, else clear the request for
11369 + * EEPROM access and return -E1000_ERR_NVM (-1).
11371 +s32 e1000e_acquire_nvm(struct e1000_hw *hw)
11373 + u32 eecd = er32(EECD);
11374 + s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
11375 + s32 ret_val = E1000_SUCCESS;
11377 + ew32(EECD, eecd | E1000_EECD_REQ);
11378 + eecd = er32(EECD);
11379 + while (timeout) {
11380 + if (eecd & E1000_EECD_GNT)
11383 + eecd = er32(EECD);
11388 + eecd &= ~E1000_EECD_REQ;
11389 + ew32(EECD, eecd);
11390 + e_dbg("Could not acquire NVM grant\n");
11391 + ret_val = -E1000_ERR_NVM;
11398 + * e1000_standby_nvm - Return EEPROM to standby state
11399 + * @hw: pointer to the HW structure
11401 + * Return the EEPROM to a standby state.
11403 +static void e1000_standby_nvm(struct e1000_hw *hw)
11405 + struct e1000_nvm_info *nvm = &hw->nvm;
11406 + u32 eecd = er32(EECD);
11408 + if (nvm->type == e1000_nvm_eeprom_spi) {
11409 + /* Toggle CS to flush commands */
11410 + eecd |= E1000_EECD_CS;
11411 + ew32(EECD, eecd);
11413 + udelay(nvm->delay_usec);
11414 + eecd &= ~E1000_EECD_CS;
11415 + ew32(EECD, eecd);
11417 + udelay(nvm->delay_usec);
11422 + * e1000_stop_nvm - Terminate EEPROM command
11423 + * @hw: pointer to the HW structure
11425 + * Terminates the current command by inverting the EEPROM's chip select pin.
11427 +static void e1000_stop_nvm(struct e1000_hw *hw)
11431 + eecd = er32(EECD);
11432 + if (hw->nvm.type == e1000_nvm_eeprom_spi) {
11433 + /* Pull CS high */
11434 + eecd |= E1000_EECD_CS;
11435 + e1000_lower_eec_clk(hw, &eecd);
11440 + * e1000e_release_nvm - Release exclusive access to EEPROM
11441 + * @hw: pointer to the HW structure
11443 + * Stop any current commands to the EEPROM and clear the EEPROM request bit.
11445 +void e1000e_release_nvm(struct e1000_hw *hw)
11449 + e1000_stop_nvm(hw);
11451 + eecd = er32(EECD);
11452 + eecd &= ~E1000_EECD_REQ;
11453 + ew32(EECD, eecd);
11457 + * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
11458 + * @hw: pointer to the HW structure
11460 + * Setups the EEPROM for reading and writing.
11462 +static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
11464 + struct e1000_nvm_info *nvm = &hw->nvm;
11465 + u32 eecd = er32(EECD);
11466 + s32 ret_val = E1000_SUCCESS;
11470 + if (nvm->type == e1000_nvm_eeprom_spi) {
11471 + /* Clear SK and CS */
11472 + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
11473 + ew32(EECD, eecd);
11475 + timeout = NVM_MAX_RETRY_SPI;
11478 + * Read "Status Register" repeatedly until the LSB is cleared.
11479 + * The EEPROM will signal that the command has been completed
11480 + * by clearing bit 0 of the internal status register. If it's
11481 + * not cleared within 'timeout', then error out.
11483 + while (timeout) {
11484 + e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
11485 + hw->nvm.opcode_bits);
11486 + spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
11487 + if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
11491 + e1000_standby_nvm(hw);
11496 + e_dbg("SPI NVM Status error\n");
11497 + ret_val = -E1000_ERR_NVM;
11507 + * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
11508 + * @hw: pointer to the HW structure
11509 + * @offset: offset of word in the EEPROM to read
11510 + * @words: number of words to read
11511 + * @data: word read from the EEPROM
11513 + * Reads a 16 bit word from the EEPROM using the EERD register.
11515 +s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
11517 + struct e1000_nvm_info *nvm = &hw->nvm;
11519 + s32 ret_val = E1000_SUCCESS;
11522 + * A check for invalid values: offset too large, too many words,
11523 + * too many words for the offset, and not enough words.
11525 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11527 + e_dbg("nvm parameter(s) out of bounds\n");
11528 + ret_val = -E1000_ERR_NVM;
11532 + for (i = 0; i < words; i++) {
11533 + eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
11534 + E1000_NVM_RW_REG_START;
11536 + ew32(EERD, eerd);
11537 + ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
11541 + data[i] = (er32(EERD) >>
11542 + E1000_NVM_RW_REG_DATA);
11550 + * e1000e_write_nvm_spi - Write to EEPROM using SPI
11551 + * @hw: pointer to the HW structure
11552 + * @offset: offset within the EEPROM to be written to
11553 + * @words: number of words to write
11554 + * @data: 16 bit word(s) to be written to the EEPROM
11556 + * Writes data to EEPROM at offset using SPI interface.
11558 + * If e1000_update_nvm_checksum is not called after this function , the
11559 + * EEPROM will most likely contain an invalid checksum.
11561 +s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
11563 + struct e1000_nvm_info *nvm = &hw->nvm;
11568 + * A check for invalid values: offset too large, too many words,
11569 + * and not enough words.
11571 + if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
11573 + e_dbg("nvm parameter(s) out of bounds\n");
11574 + ret_val = -E1000_ERR_NVM;
11578 + ret_val = nvm->ops.acquire(hw);
11582 + while (widx < words) {
11583 + u8 write_opcode = NVM_WRITE_OPCODE_SPI;
11585 + ret_val = e1000_ready_nvm_eeprom(hw);
11589 + e1000_standby_nvm(hw);
11591 + /* Send the WRITE ENABLE command (8 bit opcode) */
11592 + e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
11593 + nvm->opcode_bits);
11595 + e1000_standby_nvm(hw);
11598 + * Some SPI eeproms use the 8th address bit embedded in the
11601 + if ((nvm->address_bits == 8) && (offset >= 128))
11602 + write_opcode |= NVM_A8_OPCODE_SPI;
11604 + /* Send the Write command (8-bit opcode + addr) */
11605 + e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
11606 + e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
11607 + nvm->address_bits);
11609 + /* Loop to allow for up to whole page write of eeprom */
11610 + while (widx < words) {
11611 + u16 word_out = data[widx];
11612 + word_out = (word_out >> 8) | (word_out << 8);
11613 + e1000_shift_out_eec_bits(hw, word_out, 16);
11616 + if ((((offset + widx) * 2) % nvm->page_size) == 0) {
11617 + e1000_standby_nvm(hw);
11625 + nvm->ops.release(hw);
11632 + * e1000e_read_pba_num - Read device part number
11633 + * @hw: pointer to the HW structure
11634 + * @pba_num: pointer to device part number
11636 + * Reads the product board assembly (PBA) number from the EEPROM and stores
11637 + * the value in pba_num.
11639 +s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
11644 + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
11646 + e_dbg("NVM Read Error\n");
11649 + *pba_num = (u32)(nvm_data << 16);
11651 + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
11653 + e_dbg("NVM Read Error\n");
11656 + *pba_num |= nvm_data;
11663 + * e1000e_read_mac_addr_generic - Read device MAC address
11664 + * @hw: pointer to the HW structure
11666 + * Reads the device MAC address from the EEPROM and stores the value.
11667 + * Since devices with two ports use the same EEPROM, we increment the
11668 + * last bit in the MAC address for the second port.
11670 +s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw)
11676 + rar_high = er32(RAH(0));
11677 + rar_low = er32(RAL(0));
11679 + for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
11680 + hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
11682 + for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
11683 + hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
11685 + for (i = 0; i < ETH_ADDR_LEN; i++)
11686 + hw->mac.addr[i] = hw->mac.perm_addr[i];
11688 + return E1000_SUCCESS;
11692 + * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
11693 + * @hw: pointer to the HW structure
11695 + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
11696 + * and then verifies that the sum of the EEPROM is equal to 0xBABA.
11698 +s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
11700 + s32 ret_val = E1000_SUCCESS;
11701 + u16 checksum = 0;
11704 + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
11705 + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
11707 + e_dbg("NVM Read Error\n");
11710 + checksum += nvm_data;
11713 + if (checksum != (u16) NVM_SUM) {
11714 + e_dbg("NVM Checksum Invalid\n");
11715 + ret_val = -E1000_ERR_NVM;
11724 + * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
11725 + * @hw: pointer to the HW structure
11727 + * Updates the EEPROM checksum by reading/adding each word of the EEPROM
11728 + * up to the checksum. Then calculates the EEPROM checksum and writes the
11729 + * value to the EEPROM.
11731 +s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
11734 + u16 checksum = 0;
11737 + for (i = 0; i < NVM_CHECKSUM_REG; i++) {
11738 + ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
11740 + e_dbg("NVM Read Error while updating checksum.\n");
11743 + checksum += nvm_data;
11745 + checksum = (u16) NVM_SUM - checksum;
11746 + ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
11748 + e_dbg("NVM Write Error while updating checksum.\n");
11755 + * e1000e_reload_nvm - Reloads EEPROM
11756 + * @hw: pointer to the HW structure
11758 + * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
11759 + * extended control register.
11761 +static void e1000e_reload_nvm(struct e1000_hw *hw)
11766 + ctrl_ext = er32(CTRL_EXT);
11767 + ctrl_ext |= E1000_CTRL_EXT_EE_RST;
11768 + ew32(CTRL_EXT, ctrl_ext);
11772 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.h linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.h
11773 --- linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.h 1970-01-01 01:00:00.000000000 +0100
11774 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.h 2009-06-24 00:32:20.000000000 +0200
11776 +/*******************************************************************************
11778 + Intel PRO/1000 Linux driver
11779 + Copyright(c) 1999 - 2009 Intel Corporation.
11781 + This program is free software; you can redistribute it and/or modify it
11782 + under the terms and conditions of the GNU General Public License,
11783 + version 2, as published by the Free Software Foundation.
11785 + This program is distributed in the hope it will be useful, but WITHOUT
11786 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11787 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11790 + You should have received a copy of the GNU General Public License along with
11791 + this program; if not, write to the Free Software Foundation, Inc.,
11792 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11794 + The full GNU General Public License is included in this distribution in
11795 + the file called "COPYING".
11797 + Contact Information:
11798 + Linux NICS <linux.nics@intel.com>
11799 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11800 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11802 +*******************************************************************************/
11804 +#ifndef _E1000_NVM_H_
11805 +#define _E1000_NVM_H_
11807 +void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
11808 +s32 e1000e_acquire_nvm(struct e1000_hw *hw);
11810 +s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
11811 +s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw);
11812 +s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
11813 +s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
11815 +s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
11816 +s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
11817 +s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
11818 + u16 words, u16 *data);
11819 +s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
11821 +s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
11822 +void e1000e_release_nvm(struct e1000_hw *hw);
11824 +#define E1000_STM_OPCODE 0xDB00
11827 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_phy.c linux-2.6.22-10/drivers/net/e1000e/e1000_phy.c
11828 --- linux-2.6.22-0/drivers/net/e1000e/e1000_phy.c 1970-01-01 01:00:00.000000000 +0100
11829 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_phy.c 2009-06-24 00:32:20.000000000 +0200
11831 +/*******************************************************************************
11833 + Intel PRO/1000 Linux driver
11834 + Copyright(c) 1999 - 2009 Intel Corporation.
11836 + This program is free software; you can redistribute it and/or modify it
11837 + under the terms and conditions of the GNU General Public License,
11838 + version 2, as published by the Free Software Foundation.
11840 + This program is distributed in the hope it will be useful, but WITHOUT
11841 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11842 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11845 + You should have received a copy of the GNU General Public License along with
11846 + this program; if not, write to the Free Software Foundation, Inc.,
11847 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
11849 + The full GNU General Public License is included in this distribution in
11850 + the file called "COPYING".
11852 + Contact Information:
11853 + Linux NICS <linux.nics@intel.com>
11854 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
11855 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11857 +*******************************************************************************/
11859 +#include "e1000.h"
11861 +static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
11862 +static s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
11863 +static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
11864 +static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
11865 + u16 *data, bool read);
11866 +static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11867 +static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
11868 + u16 *data, bool read);
11870 +/* Cable length tables */
11871 +static const u16 e1000_m88_cable_length_table[] =
11872 + { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
11873 +#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
11874 + (sizeof(e1000_m88_cable_length_table) / \
11875 + sizeof(e1000_m88_cable_length_table[0]))
11877 +static const u16 e1000_igp_2_cable_length_table[] =
11878 + { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
11879 + 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
11880 + 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
11881 + 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
11882 + 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
11883 + 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
11884 + 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
11885 + 104, 109, 114, 118, 121, 124};
11886 +#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
11887 + (sizeof(e1000_igp_2_cable_length_table) / \
11888 + sizeof(e1000_igp_2_cable_length_table[0]))
11891 + * e1000e_check_reset_block_generic - Check if PHY reset is blocked
11892 + * @hw: pointer to the HW structure
11894 + * Read the PHY management control register and check whether a PHY reset
11895 + * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
11896 + * return E1000_BLK_PHY_RESET (12).
11898 +s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
11902 + manc = er32(MANC);
11904 + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
11905 + E1000_BLK_PHY_RESET : E1000_SUCCESS;
11909 + * e1000e_get_phy_id - Retrieve the PHY ID and revision
11910 + * @hw: pointer to the HW structure
11912 + * Reads the PHY registers and stores the PHY ID and possibly the PHY
11913 + * revision in the hardware structure.
11915 +s32 e1000e_get_phy_id(struct e1000_hw *hw)
11917 + struct e1000_phy_info *phy = &hw->phy;
11918 + s32 ret_val = E1000_SUCCESS;
11920 + u16 retry_count = 0;
11922 + if (!(phy->ops.read_reg))
11925 + while (retry_count < 2) {
11926 + ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
11930 + phy->id = (u32)(phy_id << 16);
11932 + ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
11936 + phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
11937 + phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
11939 + if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
11943 + * If the PHY ID is still unknown, we may have an 82577 without link.
11944 + * We will try again after setting Slow MDIC mode. No harm in trying
11945 + * again in this case since the PHY ID is unknown at this point anyway
11947 + ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
11954 + /* Revert to MDIO fast mode, if applicable */
11956 + ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
11962 + * e1000e_phy_reset_dsp - Reset PHY DSP
11963 + * @hw: pointer to the HW structure
11965 + * Reset the digital signal processor.
11967 +s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
11969 + s32 ret_val = E1000_SUCCESS;
11971 + if (!(hw->phy.ops.write_reg))
11974 + ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
11978 + ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
11985 + * e1000e_read_phy_reg_mdic - Read MDI control register
11986 + * @hw: pointer to the HW structure
11987 + * @offset: register offset to be read
11988 + * @data: pointer to the read data
11990 + * Reads the MDI control register in the PHY at offset and stores the
11991 + * information read to data.
11993 +s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
11995 + struct e1000_phy_info *phy = &hw->phy;
11997 + s32 ret_val = E1000_SUCCESS;
12000 + * Set up Op-code, Phy Address, and register offset in the MDI
12001 + * Control register. The MAC will take care of interfacing with the
12002 + * PHY to retrieve the desired data.
12004 + mdic = ((offset << E1000_MDIC_REG_SHIFT) |
12005 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
12006 + (E1000_MDIC_OP_READ));
12008 + ew32(MDIC, mdic);
12011 + * Poll the ready bit to see if the MDI read completed
12012 + * Increasing the time out as testing showed failures with
12013 + * the lower time out
12015 + for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
12017 + mdic = er32(MDIC);
12018 + if (mdic & E1000_MDIC_READY)
12021 + if (!(mdic & E1000_MDIC_READY)) {
12022 + e_dbg("MDI Read did not complete\n");
12023 + ret_val = -E1000_ERR_PHY;
12026 + if (mdic & E1000_MDIC_ERROR) {
12027 + e_dbg("MDI Error\n");
12028 + ret_val = -E1000_ERR_PHY;
12031 + *data = (u16) mdic;
12038 + * e1000e_write_phy_reg_mdic - Write MDI control register
12039 + * @hw: pointer to the HW structure
12040 + * @offset: register offset to write to
12041 + * @data: data to write to register at offset
12043 + * Writes data to MDI control register in the PHY at offset.
12045 +s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
12047 + struct e1000_phy_info *phy = &hw->phy;
12049 + s32 ret_val = E1000_SUCCESS;
12052 + * Set up Op-code, Phy Address, and register offset in the MDI
12053 + * Control register. The MAC will take care of interfacing with the
12054 + * PHY to retrieve the desired data.
12056 + mdic = (((u32)data) |
12057 + (offset << E1000_MDIC_REG_SHIFT) |
12058 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
12059 + (E1000_MDIC_OP_WRITE));
12061 + ew32(MDIC, mdic);
12064 + * Poll the ready bit to see if the MDI read completed
12065 + * Increasing the time out as testing showed failures with
12066 + * the lower time out
12068 + for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
12070 + mdic = er32(MDIC);
12071 + if (mdic & E1000_MDIC_READY)
12074 + if (!(mdic & E1000_MDIC_READY)) {
12075 + e_dbg("MDI Write did not complete\n");
12076 + ret_val = -E1000_ERR_PHY;
12079 + if (mdic & E1000_MDIC_ERROR) {
12080 + e_dbg("MDI Error\n");
12081 + ret_val = -E1000_ERR_PHY;
12090 + * e1000e_read_phy_reg_m88 - Read m88 PHY register
12091 + * @hw: pointer to the HW structure
12092 + * @offset: register offset to be read
12093 + * @data: pointer to the read data
12095 + * Acquires semaphore, if necessary, then reads the PHY register at offset
12096 + * and storing the retrieved information in data. Release any acquired
12097 + * semaphores before exiting.
12099 +s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
12101 + s32 ret_val = E1000_SUCCESS;
12103 + if (!(hw->phy.ops.acquire))
12106 + ret_val = hw->phy.ops.acquire(hw);
12110 + ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
12113 + hw->phy.ops.release(hw);
12120 + * e1000e_write_phy_reg_m88 - Write m88 PHY register
12121 + * @hw: pointer to the HW structure
12122 + * @offset: register offset to write to
12123 + * @data: data to write at register offset
12125 + * Acquires semaphore, if necessary, then writes the data to PHY register
12126 + * at the offset. Release any acquired semaphores before exiting.
12128 +s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
12130 + s32 ret_val = E1000_SUCCESS;
12132 + if (!(hw->phy.ops.acquire))
12135 + ret_val = hw->phy.ops.acquire(hw);
12139 + ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
12142 + hw->phy.ops.release(hw);
12149 + * e1000e_read_phy_reg_igp - Read igp PHY register
12150 + * @hw: pointer to the HW structure
12151 + * @offset: register offset to be read
12152 + * @data: pointer to the read data
12154 + * Acquires semaphore, if necessary, then reads the PHY register at offset
12155 + * and storing the retrieved information in data. Release any acquired
12156 + * semaphores before exiting.
12158 +s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
12160 + s32 ret_val = E1000_SUCCESS;
12162 + if (!(hw->phy.ops.acquire))
12165 + ret_val = hw->phy.ops.acquire(hw);
12169 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
12170 + ret_val = e1000e_write_phy_reg_mdic(hw,
12171 + IGP01E1000_PHY_PAGE_SELECT,
12174 + hw->phy.ops.release(hw);
12179 + ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
12182 + hw->phy.ops.release(hw);
12189 + * e1000e_write_phy_reg_igp - Write igp PHY register
12190 + * @hw: pointer to the HW structure
12191 + * @offset: register offset to write to
12192 + * @data: data to write at register offset
12194 + * Acquires semaphore, if necessary, then writes the data to PHY register
12195 + * at the offset. Release any acquired semaphores before exiting.
12197 +s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
12199 + s32 ret_val = E1000_SUCCESS;
12201 + if (!(hw->phy.ops.acquire))
12204 + ret_val = hw->phy.ops.acquire(hw);
12208 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
12209 + ret_val = e1000e_write_phy_reg_mdic(hw,
12210 + IGP01E1000_PHY_PAGE_SELECT,
12213 + hw->phy.ops.release(hw);
12218 + ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
12221 + hw->phy.ops.release(hw);
12228 + * e1000e_read_kmrn_reg - Read kumeran register
12229 + * @hw: pointer to the HW structure
12230 + * @offset: register offset to be read
12231 + * @data: pointer to the read data
12233 + * Acquires semaphore, if necessary. Then reads the PHY register at offset
12234 + * using the kumeran interface. The information retrieved is stored in data.
12235 + * Release any acquired semaphores before exiting.
12237 +s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
12240 + s32 ret_val = E1000_SUCCESS;
12242 + if (!(hw->phy.ops.acquire))
12245 + ret_val = hw->phy.ops.acquire(hw);
12249 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
12250 + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
12251 + ew32(KMRNCTRLSTA, kmrnctrlsta);
12255 + kmrnctrlsta = er32(KMRNCTRLSTA);
12256 + *data = (u16)kmrnctrlsta;
12258 + hw->phy.ops.release(hw);
12265 + * e1000e_write_kmrn_reg - Write kumeran register
12266 + * @hw: pointer to the HW structure
12267 + * @offset: register offset to write to
12268 + * @data: data to write at register offset
12270 + * Acquires semaphore, if necessary. Then write the data to PHY register
12271 + * at the offset using the kumeran interface. Release any acquired semaphores
12272 + * before exiting.
12274 +s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
12277 + s32 ret_val = E1000_SUCCESS;
12279 + if (!(hw->phy.ops.acquire))
12282 + ret_val = hw->phy.ops.acquire(hw);
12286 + kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
12287 + E1000_KMRNCTRLSTA_OFFSET) | data;
12288 + ew32(KMRNCTRLSTA, kmrnctrlsta);
12291 + hw->phy.ops.release(hw);
12298 + * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
12299 + * @hw: pointer to the HW structure
12301 + * Sets up Carrier-sense on Transmit and downshift values.
12303 +s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
12305 + struct e1000_phy_info *phy = &hw->phy;
12309 + if (phy->reset_disable) {
12310 + ret_val = E1000_SUCCESS;
12314 + /* Enable CRS on TX. This must be set for half-duplex operation. */
12315 + ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
12319 + phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
12321 + /* Enable downshift */
12322 + phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
12324 + ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
12328 + /* Set number of link attempts before downshift */
12329 + ret_val = e1e_rphy(hw, I82577_CTRL_REG, &phy_data);
12332 + phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
12333 + ret_val = e1e_wphy(hw, I82577_CTRL_REG, phy_data);
12340 + * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
12341 + * @hw: pointer to the HW structure
12343 + * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
12344 + * and downshift values are set also.
12346 +s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
12348 + struct e1000_phy_info *phy = &hw->phy;
12352 + if (phy->reset_disable) {
12353 + ret_val = E1000_SUCCESS;
12357 + /* Enable CRS on TX. This must be set for half-duplex operation. */
12358 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
12362 + /* For BM PHY this bit is downshift enable */
12363 + if (phy->type != e1000_phy_bm)
12364 + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
12368 + * MDI/MDI-X = 0 (default)
12369 + * 0 - Auto for all speeds
12372 + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
12374 + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
12376 + switch (phy->mdix) {
12378 + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
12381 + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
12384 + phy_data |= M88E1000_PSCR_AUTO_X_1000T;
12388 + phy_data |= M88E1000_PSCR_AUTO_X_MODE;
12394 + * disable_polarity_correction = 0 (default)
12395 + * Automatic Correction for Reversed Cable Polarity
12399 + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
12400 + if (phy->disable_polarity_correction == 1)
12401 + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
12403 + /* Enable downshift on BM (disabled by default) */
12404 + if (phy->type == e1000_phy_bm)
12405 + phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
12407 + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
12411 + if ((phy->type == e1000_phy_m88) &&
12412 + (phy->revision < E1000_REVISION_4) &&
12413 + (phy->id != BME1000_E_PHY_ID_R2)) {
12415 + * Force TX_CLK in the Extended PHY Specific Control Register
12416 + * to 25MHz clock.
12418 + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL,
12423 + phy_data |= M88E1000_EPSCR_TX_CLK_25;
12425 + if ((phy->revision == E1000_REVISION_2) &&
12426 + (phy->id == M88E1111_I_PHY_ID)) {
12427 + /* 82573L PHY - set the downshift counter to 5x. */
12428 + phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
12429 + phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
12431 + /* Configure Master and Slave downshift values */
12432 + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
12433 + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
12434 + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
12435 + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
12437 + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL,
12443 + if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
12444 + /* Set PHY page 0, register 29 to 0x0003 */
12445 + ret_val = e1e_wphy(hw, 29, 0x0003);
12449 + /* Set PHY page 0, register 30 to 0x0000 */
12450 + ret_val = e1e_wphy(hw, 30, 0x0000);
12455 + /* Commit the changes. */
12456 + ret_val = e1000e_commit_phy(hw);
12458 + e_dbg("Error committing the PHY changes\n");
12462 + if (phy->type == e1000_phy_82578) {
12463 + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL,
12468 + /* 82578 PHY - set the downshift count to 1x. */
12469 + phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
12470 + phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
12471 + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL,
12482 + * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
12483 + * @hw: pointer to the HW structure
12485 + * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
12488 +s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
12490 + struct e1000_phy_info *phy = &hw->phy;
12494 + if (phy->reset_disable) {
12495 + ret_val = E1000_SUCCESS;
12499 + ret_val = e1000_phy_hw_reset(hw);
12501 + e_dbg("Error resetting the PHY.\n");
12506 + * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
12507 + * timeout issues when LFS is enabled.
12512 + * The NVM settings will configure LPLU in D3 for
12515 + if (phy->type == e1000_phy_igp) {
12516 + /* disable lplu d3 during driver init */
12517 + ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
12519 + e_dbg("Error Disabling LPLU D3\n");
12524 + /* disable lplu d0 during driver init */
12525 + if (hw->phy.ops.set_d0_lplu_state) {
12526 + ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
12528 + e_dbg("Error Disabling LPLU D0\n");
12532 + /* Configure mdi-mdix settings */
12533 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
12537 + data &= ~IGP01E1000_PSCR_AUTO_MDIX;
12539 + switch (phy->mdix) {
12541 + data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
12544 + data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
12548 + data |= IGP01E1000_PSCR_AUTO_MDIX;
12551 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
12555 + /* set auto-master slave resolution settings */
12556 + if (hw->mac.autoneg) {
12558 + * when autonegotiation advertisement is only 1000Mbps then we
12559 + * should disable SmartSpeed and enable Auto MasterSlave
12560 + * resolution as hardware default.
12562 + if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
12563 + /* Disable SmartSpeed */
12564 + ret_val = e1e_rphy(hw,
12565 + IGP01E1000_PHY_PORT_CONFIG,
12570 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
12571 + ret_val = e1e_wphy(hw,
12572 + IGP01E1000_PHY_PORT_CONFIG,
12577 + /* Set auto Master/Slave resolution process */
12578 + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
12582 + data &= ~CR_1000T_MS_ENABLE;
12583 + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
12588 + ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
12592 + /* load defaults for future use */
12593 + phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
12594 + ((data & CR_1000T_MS_VALUE) ?
12595 + e1000_ms_force_master :
12596 + e1000_ms_force_slave) :
12599 + switch (phy->ms_type) {
12600 + case e1000_ms_force_master:
12601 + data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
12603 + case e1000_ms_force_slave:
12604 + data |= CR_1000T_MS_ENABLE;
12605 + data &= ~(CR_1000T_MS_VALUE);
12607 + case e1000_ms_auto:
12608 + data &= ~CR_1000T_MS_ENABLE;
12612 + ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
12622 + * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
12623 + * @hw: pointer to the HW structure
12625 + * Performs initial bounds checking on autoneg advertisement parameter, then
12626 + * configure to advertise the full capability. Setup the PHY to autoneg
12627 + * and restart the negotiation process between the link partner. If
12628 + * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
12630 +static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
12632 + struct e1000_phy_info *phy = &hw->phy;
12637 + * Perform some bounds checking on the autoneg advertisement
12640 + phy->autoneg_advertised &= phy->autoneg_mask;
12643 + * If autoneg_advertised is zero, we assume it was not defaulted
12644 + * by the calling code so we set to advertise full capability.
12646 + if (phy->autoneg_advertised == 0)
12647 + phy->autoneg_advertised = phy->autoneg_mask;
12649 + e_dbg("Reconfiguring auto-neg advertisement params\n");
12650 + ret_val = e1000_phy_setup_autoneg(hw);
12652 + e_dbg("Error Setting up Auto-Negotiation\n");
12655 + e_dbg("Restarting Auto-Neg\n");
12658 + * Restart auto-negotiation by setting the Auto Neg Enable bit and
12659 + * the Auto Neg Restart bit in the PHY control register.
12661 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
12665 + phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
12666 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
12671 + * Does the user want to wait for Auto-Neg to complete here, or
12672 + * check at a later time (for example, callback routine).
12674 + if (phy->autoneg_wait_to_complete) {
12675 + ret_val = hw->mac.ops.wait_autoneg(hw);
12677 + e_dbg("Error while waiting for "
12678 + "autoneg to complete\n");
12683 + hw->mac.get_link_status = true;
12690 + * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
12691 + * @hw: pointer to the HW structure
12693 + * Reads the MII auto-neg advertisement register and/or the 1000T control
12694 + * register and if the PHY is already setup for auto-negotiation, then
12695 + * return successful. Otherwise, setup advertisement and flow control to
12696 + * the appropriate values for the wanted auto-negotiation.
12698 +static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
12700 + struct e1000_phy_info *phy = &hw->phy;
12702 + u16 mii_autoneg_adv_reg;
12703 + u16 mii_1000t_ctrl_reg = 0;
12705 + phy->autoneg_advertised &= phy->autoneg_mask;
12707 + /* Read the MII Auto-Neg Advertisement Register (Address 4). */
12708 + ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
12712 + if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
12713 + /* Read the MII 1000Base-T Control Register (Address 9). */
12714 + ret_val = e1e_rphy(hw, PHY_1000T_CTRL,
12715 + &mii_1000t_ctrl_reg);
12721 + * Need to parse both autoneg_advertised and fc and set up
12722 + * the appropriate PHY registers. First we will parse for
12723 + * autoneg_advertised software override. Since we can advertise
12724 + * a plethora of combinations, we need to check each bit
12729 + * First we clear all the 10/100 mb speed bits in the Auto-Neg
12730 + * Advertisement Register (Address 4) and the 1000 mb speed bits in
12731 + * the 1000Base-T Control Register (Address 9).
12733 + mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
12734 + NWAY_AR_100TX_HD_CAPS |
12735 + NWAY_AR_10T_FD_CAPS |
12736 + NWAY_AR_10T_HD_CAPS);
12737 + mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
12739 + e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
12741 + /* Do we want to advertise 10 Mb Half Duplex? */
12742 + if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
12743 + e_dbg("Advertise 10mb Half duplex\n");
12744 + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
12747 + /* Do we want to advertise 10 Mb Full Duplex? */
12748 + if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
12749 + e_dbg("Advertise 10mb Full duplex\n");
12750 + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
12753 + /* Do we want to advertise 100 Mb Half Duplex? */
12754 + if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
12755 + e_dbg("Advertise 100mb Half duplex\n");
12756 + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
12759 + /* Do we want to advertise 100 Mb Full Duplex? */
12760 + if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
12761 + e_dbg("Advertise 100mb Full duplex\n");
12762 + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
12765 + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
12766 + if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
12767 + e_dbg("Advertise 1000mb Half duplex request denied!\n");
12769 + /* Do we want to advertise 1000 Mb Full Duplex? */
12770 + if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
12771 + e_dbg("Advertise 1000mb Full duplex\n");
12772 + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
12776 + * Check for a software override of the flow control settings, and
12777 + * setup the PHY advertisement registers accordingly. If
12778 + * auto-negotiation is enabled, then software will have to set the
12779 + * "PAUSE" bits to the correct value in the Auto-Negotiation
12780 + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
12783 + * The possible values of the "fc" parameter are:
12784 + * 0: Flow control is completely disabled
12785 + * 1: Rx flow control is enabled (we can receive pause frames
12786 + * but not send pause frames).
12787 + * 2: Tx flow control is enabled (we can send pause frames
12788 + * but we do not support receiving pause frames).
12789 + * 3: Both Rx and Tx flow control (symmetric) are enabled.
12790 + * other: No software override. The flow control configuration
12791 + * in the EEPROM is used.
12793 + switch (hw->fc.current_mode) {
12794 + case e1000_fc_none:
12796 + * Flow control (Rx & Tx) is completely disabled by a
12797 + * software over-ride.
12799 + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
12801 + case e1000_fc_rx_pause:
12803 + * Rx Flow control is enabled, and Tx Flow control is
12804 + * disabled, by a software over-ride.
12806 + * Since there really isn't a way to advertise that we are
12807 + * capable of Rx Pause ONLY, we will advertise that we
12808 + * support both symmetric and asymmetric Rx PAUSE. Later
12809 + * (in e1000e_config_fc_after_link_up) we will disable the
12810 + * hw's ability to send PAUSE frames.
12812 + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
12814 + case e1000_fc_tx_pause:
12816 + * Tx Flow control is enabled, and Rx Flow control is
12817 + * disabled, by a software over-ride.
12819 + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
12820 + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
12822 + case e1000_fc_full:
12824 + * Flow control (both Rx and Tx) is enabled by a software
12827 + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
12830 + e_dbg("Flow control param set incorrectly\n");
12831 + ret_val = -E1000_ERR_CONFIG;
12835 + ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
12839 + e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
12841 + if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
12842 + ret_val = e1e_wphy(hw,
12844 + mii_1000t_ctrl_reg);
12854 + * e1000e_setup_copper_link - Configure copper link settings
12855 + * @hw: pointer to the HW structure
12857 + * Calls the appropriate function to configure the link for auto-neg or forced
12858 + * speed and duplex. Then we check for link, once link is established calls
12859 + * to configure collision distance and flow control are called. If link is
12860 + * not established, we return -E1000_ERR_PHY (-2).
12862 +s32 e1000e_setup_copper_link(struct e1000_hw *hw)
12867 + if (hw->mac.autoneg) {
12869 + * Setup autoneg and flow control advertisement and perform
12870 + * autonegotiation.
12872 + ret_val = e1000_copper_link_autoneg(hw);
12877 + * PHY will be set to 10H, 10F, 100H or 100F
12878 + * depending on user settings.
12880 + e_dbg("Forcing Speed and Duplex\n");
12881 + ret_val = hw->phy.ops.force_speed_duplex(hw);
12883 + e_dbg("Error Forcing Speed and Duplex\n");
12889 + * Check link status. Wait up to 100 microseconds for link to become
12892 + ret_val = e1000e_phy_has_link_generic(hw,
12893 + COPPER_LINK_UP_LIMIT,
12900 + e_dbg("Valid link established!!!\n");
12901 + e1000e_config_collision_dist(hw);
12902 + ret_val = e1000e_config_fc_after_link_up(hw);
12904 + e_dbg("Unable to establish link!!!\n");
12912 + * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
12913 + * @hw: pointer to the HW structure
12915 + * Calls the PHY setup function to force speed and duplex. Clears the
12916 + * auto-crossover to force MDI manually. Waits for link and returns
12917 + * successful if link up is successful, else -E1000_ERR_PHY (-2).
12919 +s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
12921 + struct e1000_phy_info *phy = &hw->phy;
12926 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
12930 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
12932 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
12937 + * Clear Auto-Crossover to force MDI manually. IGP requires MDI
12938 + * forced whenever speed and duplex are forced.
12940 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
12944 + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
12945 + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
12947 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
12951 + e_dbg("IGP PSCR: %X\n", phy_data);
12955 + if (phy->autoneg_wait_to_complete) {
12956 + e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
12958 + ret_val = e1000e_phy_has_link_generic(hw,
12966 + e_dbg("Link taking longer than expected.\n");
12968 + /* Try once more */
12969 + ret_val = e1000e_phy_has_link_generic(hw,
12982 + * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
12983 + * @hw: pointer to the HW structure
12985 + * Calls the PHY setup function to force speed and duplex. Clears the
12986 + * auto-crossover to force MDI manually. Resets the PHY to commit the
12987 + * changes. If time expires while waiting for link up, we reset the DSP.
12988 + * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
12989 + * successful completion, else return corresponding error code.
12991 +s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
12993 + struct e1000_phy_info *phy = &hw->phy;
12999 + * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
13000 + * forced whenever speed and duplex are forced.
13002 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
13006 + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
13007 + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
13011 + e_dbg("M88E1000 PSCR: %X\n", phy_data);
13013 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
13017 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
13019 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
13023 + /* Reset the phy to commit changes. */
13024 + ret_val = e1000e_commit_phy(hw);
13028 + if (phy->autoneg_wait_to_complete) {
13029 + e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
13031 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
13038 + * We didn't get link.
13039 + * Reset the DSP and cross our fingers.
13041 + ret_val = e1e_wphy(hw,
13042 + M88E1000_PHY_PAGE_SELECT,
13046 + ret_val = e1000e_phy_reset_dsp(hw);
13051 + /* Try once more */
13052 + ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
13058 + ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
13063 + * Resetting the phy means we need to re-force TX_CLK in the
13064 + * Extended PHY Specific Control Register to 25MHz clock from
13065 + * the reset value of 2.5MHz.
13067 + phy_data |= M88E1000_EPSCR_TX_CLK_25;
13068 + ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
13073 + * In addition, we must re-enable CRS on Tx for both half and full
13076 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
13080 + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
13081 + ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
13088 + * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
13089 + * @hw: pointer to the HW structure
13091 + * Forces the speed and duplex settings of the PHY.
13092 + * This is a function pointer entry point only called by
13093 + * PHY setup routines.
13095 +s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
13097 + struct e1000_phy_info *phy = &hw->phy;
13102 + if (phy->type != e1000_phy_ife) {
13103 + ret_val = e1000e_phy_force_speed_duplex_igp(hw);
13107 + ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
13111 + e1000e_phy_force_speed_duplex_setup(hw, &data);
13113 + ret_val = e1e_wphy(hw, PHY_CONTROL, data);
13117 + /* Disable MDI-X support for 10/100 */
13118 + ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
13122 + data &= ~IFE_PMC_AUTO_MDIX;
13123 + data &= ~IFE_PMC_FORCE_MDIX;
13125 + ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
13129 + e_dbg("IFE PMC: %X\n", data);
13133 + if (phy->autoneg_wait_to_complete) {
13134 + e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
13136 + ret_val = e1000e_phy_has_link_generic(hw,
13144 + e_dbg("Link taking longer than expected.\n");
13146 + /* Try once more */
13147 + ret_val = e1000e_phy_has_link_generic(hw,
13160 + * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
13161 + * @hw: pointer to the HW structure
13162 + * @phy_ctrl: pointer to current value of PHY_CONTROL
13164 + * Forces speed and duplex on the PHY by doing the following: disable flow
13165 + * control, force speed/duplex on the MAC, disable auto speed detection,
13166 + * disable auto-negotiation, configure duplex, configure speed, configure
13167 + * the collision distance, write configuration to CTRL register. The
13168 + * caller must write to the PHY_CONTROL register for these settings to
13171 +void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
13173 + struct e1000_mac_info *mac = &hw->mac;
13176 + /* Turn off flow control when forcing speed/duplex */
13177 + hw->fc.current_mode = e1000_fc_none;
13179 + /* Force speed/duplex on the mac */
13180 + ctrl = er32(CTRL);
13181 + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
13182 + ctrl &= ~E1000_CTRL_SPD_SEL;
13184 + /* Disable Auto Speed Detection */
13185 + ctrl &= ~E1000_CTRL_ASDE;
13187 + /* Disable autoneg on the phy */
13188 + *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
13190 + /* Forcing Full or Half Duplex? */
13191 + if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
13192 + ctrl &= ~E1000_CTRL_FD;
13193 + *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
13194 + e_dbg("Half Duplex\n");
13196 + ctrl |= E1000_CTRL_FD;
13197 + *phy_ctrl |= MII_CR_FULL_DUPLEX;
13198 + e_dbg("Full Duplex\n");
13201 + /* Forcing 10mb or 100mb? */
13202 + if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
13203 + ctrl |= E1000_CTRL_SPD_100;
13204 + *phy_ctrl |= MII_CR_SPEED_100;
13205 + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
13206 + e_dbg("Forcing 100mb\n");
13208 + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
13209 + *phy_ctrl |= MII_CR_SPEED_10;
13210 + *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
13211 + e_dbg("Forcing 10mb\n");
13214 + e1000e_config_collision_dist(hw);
13216 + ew32(CTRL, ctrl);
13220 + * e1000e_set_d3_lplu_state - Sets low power link up state for D3
13221 + * @hw: pointer to the HW structure
13222 + * @active: boolean used to enable/disable lplu
13224 + * Success returns 0, Failure returns 1
13226 + * The low power link up (lplu) state is set to the power management level D3
13227 + * and SmartSpeed is disabled when active is true, else clear lplu for D3
13228 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
13229 + * is used during Dx states where the power conservation is most important.
13230 + * During driver activity, SmartSpeed should be enabled so performance is
13233 +s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
13235 + struct e1000_phy_info *phy = &hw->phy;
13236 + s32 ret_val = E1000_SUCCESS;
13239 + if (!(hw->phy.ops.read_reg))
13242 + ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
13247 + data &= ~IGP02E1000_PM_D3_LPLU;
13248 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
13253 + * LPLU and SmartSpeed are mutually exclusive. LPLU is used
13254 + * during Dx states where the power conservation is most
13255 + * important. During driver activity we should enable
13256 + * SmartSpeed, so performance is maintained.
13258 + if (phy->smart_speed == e1000_smart_speed_on) {
13259 + ret_val = e1e_rphy(hw,
13260 + IGP01E1000_PHY_PORT_CONFIG,
13265 + data |= IGP01E1000_PSCFR_SMART_SPEED;
13266 + ret_val = e1e_wphy(hw,
13267 + IGP01E1000_PHY_PORT_CONFIG,
13271 + } else if (phy->smart_speed == e1000_smart_speed_off) {
13272 + ret_val = e1e_rphy(hw,
13273 + IGP01E1000_PHY_PORT_CONFIG,
13278 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
13279 + ret_val = e1e_wphy(hw,
13280 + IGP01E1000_PHY_PORT_CONFIG,
13285 + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
13286 + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
13287 + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
13288 + data |= IGP02E1000_PM_D3_LPLU;
13289 + ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
13294 + /* When LPLU is enabled, we should disable SmartSpeed */
13295 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
13300 + data &= ~IGP01E1000_PSCFR_SMART_SPEED;
13301 + ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
13310 + * e1000e_check_downshift - Checks whether a downshift in speed occurred
13311 + * @hw: pointer to the HW structure
13313 + * Success returns 0, Failure returns 1
13315 + * A downshift is detected by querying the PHY link health.
13317 +s32 e1000e_check_downshift(struct e1000_hw *hw)
13319 + struct e1000_phy_info *phy = &hw->phy;
13321 + u16 phy_data, offset, mask;
13323 + switch (phy->type) {
13324 + case e1000_phy_m88:
13325 + case e1000_phy_gg82563:
13326 + case e1000_phy_bm:
13327 + case e1000_phy_82578:
13328 + case e1000_phy_82577:
13329 + offset = M88E1000_PHY_SPEC_STATUS;
13330 + mask = M88E1000_PSSR_DOWNSHIFT;
13332 + case e1000_phy_igp_2:
13333 + case e1000_phy_igp:
13334 + case e1000_phy_igp_3:
13335 + offset = IGP01E1000_PHY_LINK_HEALTH;
13336 + mask = IGP01E1000_PLHR_SS_DOWNGRADE;
13339 + /* speed downshift not supported */
13340 + phy->speed_downgraded = false;
13341 + ret_val = E1000_SUCCESS;
13345 + ret_val = e1e_rphy(hw, offset, &phy_data);
13348 + phy->speed_downgraded = (phy_data & mask) ? true : false;
13355 + * e1000_check_polarity_m88 - Checks the polarity.
13356 + * @hw: pointer to the HW structure
13358 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
13360 + * Polarity is determined based on the PHY specific status register.
13362 +s32 e1000_check_polarity_m88(struct e1000_hw *hw)
13364 + struct e1000_phy_info *phy = &hw->phy;
13368 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
13371 + phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
13372 + ? e1000_rev_polarity_reversed
13373 + : e1000_rev_polarity_normal;
13379 + * e1000_check_polarity_igp - Checks the polarity.
13380 + * @hw: pointer to the HW structure
13382 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
13384 + * Polarity is determined based on the PHY port status register, and the
13385 + * current speed (since there is no polarity at 100Mbps).
13387 +s32 e1000_check_polarity_igp(struct e1000_hw *hw)
13389 + struct e1000_phy_info *phy = &hw->phy;
13391 + u16 data, offset, mask;
13394 + * Polarity is determined based on the speed of
13395 + * our connection.
13397 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
13401 + if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
13402 + IGP01E1000_PSSR_SPEED_1000MBPS) {
13403 + offset = IGP01E1000_PHY_PCS_INIT_REG;
13404 + mask = IGP01E1000_PHY_POLARITY_MASK;
13407 + * This really only applies to 10Mbps since
13408 + * there is no polarity for 100Mbps (always 0).
13410 + offset = IGP01E1000_PHY_PORT_STATUS;
13411 + mask = IGP01E1000_PSSR_POLARITY_REVERSED;
13414 + ret_val = e1e_rphy(hw, offset, &data);
13417 + phy->cable_polarity = (data & mask)
13418 + ? e1000_rev_polarity_reversed
13419 + : e1000_rev_polarity_normal;
13426 + * e1000_check_polarity_ife - Check cable polarity for IFE PHY
13427 + * @hw: pointer to the HW structure
13429 + * Polarity is determined on the polarity reversal feature being enabled.
13431 +s32 e1000_check_polarity_ife(struct e1000_hw *hw)
13433 + struct e1000_phy_info *phy = &hw->phy;
13435 + u16 phy_data, offset, mask;
13438 + * Polarity is determined based on the reversal feature being enabled.
13440 + if (phy->polarity_correction) {
13441 + offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
13442 + mask = IFE_PESC_POLARITY_REVERSED;
13444 + offset = IFE_PHY_SPECIAL_CONTROL;
13445 + mask = IFE_PSC_FORCE_POLARITY;
13448 + ret_val = e1e_rphy(hw, offset, &phy_data);
13451 + phy->cable_polarity = (phy_data & mask)
13452 + ? e1000_rev_polarity_reversed
13453 + : e1000_rev_polarity_normal;
13459 + * e1000_wait_autoneg - Wait for auto-neg completion
13460 + * @hw: pointer to the HW structure
13462 + * Waits for auto-negotiation to complete or for the auto-negotiation time
13463 + * limit to expire, which ever happens first.
13465 +s32 e1000_wait_autoneg(struct e1000_hw *hw)
13467 + s32 ret_val = E1000_SUCCESS;
13468 + u16 i, phy_status;
13470 + if (!(hw->phy.ops.read_reg))
13471 + return E1000_SUCCESS;
13473 + /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
13474 + for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
13475 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
13478 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
13481 + if (phy_status & MII_SR_AUTONEG_COMPLETE)
13487 + * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
13494 + * e1000e_phy_has_link_generic - Polls PHY for link
13495 + * @hw: pointer to the HW structure
13496 + * @iterations: number of times to poll for link
13497 + * @usec_interval: delay between polling attempts
13498 + * @success: pointer to whether polling was successful or not
13500 + * Polls the PHY status register for link, 'iterations' number of times.
13502 +s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
13503 + u32 usec_interval, bool *success)
13505 + s32 ret_val = E1000_SUCCESS;
13506 + u16 i, phy_status;
13508 + if (!(hw->phy.ops.read_reg))
13509 + return E1000_SUCCESS;
13511 + for (i = 0; i < iterations; i++) {
13513 + * Some PHYs require the PHY_STATUS register to be read
13514 + * twice due to the link bit being sticky. No harm doing
13515 + * it across the board.
13517 + ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
13520 + * If the first read fails, another entity may have
13521 + * ownership of the resources, wait and try again to
13522 + * see if they have relinquished the resources yet.
13524 + udelay(usec_interval);
13525 + ret_val = e1e_rphy(hw, PHY_STATUS,
13529 + if (phy_status & MII_SR_LINK_STATUS)
13531 + if (usec_interval >= 1000)
13532 + mdelay(usec_interval/1000);
13534 + udelay(usec_interval);
13537 + *success = (i < iterations) ? true : false;
13543 + * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
13544 + * @hw: pointer to the HW structure
13546 + * Reads the PHY specific status register to retrieve the cable length
13547 + * information. The cable length is determined by averaging the minimum and
13548 + * maximum values to get the "average" cable length. The m88 PHY has four
13549 + * possible cable length values, which are:
13550 + * Register Value Cable Length
13552 + * 1 50 - 80 meters
13553 + * 2 80 - 110 meters
13554 + * 3 110 - 140 meters
13557 +s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
13559 + struct e1000_phy_info *phy = &hw->phy;
13561 + u16 phy_data, index;
13563 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
13567 + index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
13568 + M88E1000_PSSR_CABLE_LENGTH_SHIFT;
13569 + if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) {
13570 + ret_val = E1000_ERR_PHY;
13574 + phy->min_cable_length = e1000_m88_cable_length_table[index];
13575 + phy->max_cable_length = e1000_m88_cable_length_table[index+1];
13577 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
13584 + * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
13585 + * @hw: pointer to the HW structure
13587 + * The automatic gain control (agc) normalizes the amplitude of the
13588 + * received signal, adjusting for the attenuation produced by the
13589 + * cable. By reading the AGC registers, which represent the
13590 + * combination of coarse and fine gain value, the value can be put
13591 + * into a lookup table to obtain the approximate cable length
13592 + * for each channel.
13594 +s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
13596 + struct e1000_phy_info *phy = &hw->phy;
13597 + s32 ret_val = E1000_SUCCESS;
13598 + u16 phy_data, i, agc_value = 0;
13599 + u16 cur_agc_index, max_agc_index = 0;
13600 + u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
13601 + u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
13602 + {IGP02E1000_PHY_AGC_A,
13603 + IGP02E1000_PHY_AGC_B,
13604 + IGP02E1000_PHY_AGC_C,
13605 + IGP02E1000_PHY_AGC_D};
13607 + /* Read the AGC registers for all channels */
13608 + for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
13609 + ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
13614 + * Getting bits 15:9, which represent the combination of
13615 + * coarse and fine gain values. The result is a number
13616 + * that can be put into the lookup table to obtain the
13617 + * approximate cable length.
13619 + cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
13620 + IGP02E1000_AGC_LENGTH_MASK;
13622 + /* Array index bound check. */
13623 + if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
13624 + (cur_agc_index == 0)) {
13625 + ret_val = -E1000_ERR_PHY;
13629 + /* Remove min & max AGC values from calculation. */
13630 + if (e1000_igp_2_cable_length_table[min_agc_index] >
13631 + e1000_igp_2_cable_length_table[cur_agc_index])
13632 + min_agc_index = cur_agc_index;
13633 + if (e1000_igp_2_cable_length_table[max_agc_index] <
13634 + e1000_igp_2_cable_length_table[cur_agc_index])
13635 + max_agc_index = cur_agc_index;
13637 + agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
13640 + agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
13641 + e1000_igp_2_cable_length_table[max_agc_index]);
13642 + agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
13644 + /* Calculate cable length with the error range of +/- 10 meters. */
13645 + phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
13646 + (agc_value - IGP02E1000_AGC_RANGE) : 0;
13647 + phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
13649 + phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
13656 + * e1000e_get_phy_info_m88 - Retrieve PHY information
13657 + * @hw: pointer to the HW structure
13659 + * Valid for only copper links. Read the PHY status register (sticky read)
13660 + * to verify that link is up. Read the PHY special control register to
13661 + * determine the polarity and 10base-T extended distance. Read the PHY
13662 + * special status register to determine MDI/MDIx and current speed. If
13663 + * speed is 1000, then determine cable length, local and remote receiver.
13665 +s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
13667 + struct e1000_phy_info *phy = &hw->phy;
13672 + if (hw->phy.media_type != e1000_media_type_copper) {
13673 + e_dbg("Phy info is only valid for copper media\n");
13674 + ret_val = -E1000_ERR_CONFIG;
13678 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
13683 + e_dbg("Phy info is only valid if link is up\n");
13684 + ret_val = -E1000_ERR_CONFIG;
13688 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
13692 + phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
13695 + ret_val = e1000_check_polarity_m88(hw);
13699 + ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
13703 + phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
13705 + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
13706 + ret_val = e1000_get_cable_length(hw);
13710 + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
13714 + phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
13715 + ? e1000_1000t_rx_status_ok
13716 + : e1000_1000t_rx_status_not_ok;
13718 + phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
13719 + ? e1000_1000t_rx_status_ok
13720 + : e1000_1000t_rx_status_not_ok;
13722 + /* Set values to "undefined" */
13723 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
13724 + phy->local_rx = e1000_1000t_rx_status_undefined;
13725 + phy->remote_rx = e1000_1000t_rx_status_undefined;
13733 + * e1000e_get_phy_info_igp - Retrieve igp PHY information
13734 + * @hw: pointer to the HW structure
13736 + * Read PHY status to determine if link is up. If link is up, then
13737 + * set/determine 10base-T extended distance and polarity correction. Read
13738 + * PHY port status to determine MDI/MDIx and speed. Based on the speed,
13739 + * determine on the cable length, local and remote receiver.
13741 +s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
13743 + struct e1000_phy_info *phy = &hw->phy;
13748 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
13753 + e_dbg("Phy info is only valid if link is up\n");
13754 + ret_val = -E1000_ERR_CONFIG;
13758 + phy->polarity_correction = true;
13760 + ret_val = e1000_check_polarity_igp(hw);
13764 + ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
13768 + phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
13770 + if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
13771 + IGP01E1000_PSSR_SPEED_1000MBPS) {
13772 + ret_val = e1000_get_cable_length(hw);
13776 + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
13780 + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
13781 + ? e1000_1000t_rx_status_ok
13782 + : e1000_1000t_rx_status_not_ok;
13784 + phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
13785 + ? e1000_1000t_rx_status_ok
13786 + : e1000_1000t_rx_status_not_ok;
13788 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
13789 + phy->local_rx = e1000_1000t_rx_status_undefined;
13790 + phy->remote_rx = e1000_1000t_rx_status_undefined;
13798 + * e1000e_phy_sw_reset - PHY software reset
13799 + * @hw: pointer to the HW structure
13801 + * Does a software reset of the PHY by reading the PHY control register and
13802 + * setting/write the control register reset bit to the PHY.
13804 +s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
13806 + s32 ret_val = E1000_SUCCESS;
13809 + if (!(hw->phy.ops.read_reg))
13812 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
13816 + phy_ctrl |= MII_CR_RESET;
13817 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
13828 + * e1000e_phy_hw_reset_generic - PHY hardware reset
13829 + * @hw: pointer to the HW structure
13831 + * Verify the reset block is not blocking us from resetting. Acquire
13832 + * semaphore (if necessary) and read/set/write the device control reset
13833 + * bit in the PHY. Wait the appropriate delay time for the device to
13834 + * reset and release the semaphore (if necessary).
13836 +s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
13838 + struct e1000_phy_info *phy = &hw->phy;
13839 + s32 ret_val = E1000_SUCCESS;
13842 + ret_val = e1000_check_reset_block(hw);
13844 + ret_val = E1000_SUCCESS;
13848 + ret_val = phy->ops.acquire(hw);
13852 + ctrl = er32(CTRL);
13853 + ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
13856 + udelay(phy->reset_delay_us);
13858 + ew32(CTRL, ctrl);
13863 + phy->ops.release(hw);
13865 + ret_val = phy->ops.get_cfg_done(hw);
13872 + * e1000e_get_cfg_done - Generic configuration done
13873 + * @hw: pointer to the HW structure
13875 + * Generic function to wait 10 milli-seconds for configuration to complete
13876 + * and return success.
13878 +s32 e1000e_get_cfg_done(struct e1000_hw *hw)
13882 + return E1000_SUCCESS;
13886 + * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
13887 + * @hw: pointer to the HW structure
13889 + * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
13891 +s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
13893 + e_dbg("Running IGP 3 PHY init script\n");
13895 + /* PHY init IGP 3 */
13896 + /* Enable rise/fall, 10-mode work in class-A */
13897 + e1e_wphy(hw, 0x2F5B, 0x9018);
13898 + /* Remove all caps from Replica path filter */
13899 + e1e_wphy(hw, 0x2F52, 0x0000);
13900 + /* Bias trimming for ADC, AFE and Driver (Default) */
13901 + e1e_wphy(hw, 0x2FB1, 0x8B24);
13902 + /* Increase Hybrid poly bias */
13903 + e1e_wphy(hw, 0x2FB2, 0xF8F0);
13904 + /* Add 4% to Tx amplitude in Gig mode */
13905 + e1e_wphy(hw, 0x2010, 0x10B0);
13906 + /* Disable trimming (TTT) */
13907 + e1e_wphy(hw, 0x2011, 0x0000);
13908 + /* Poly DC correction to 94.6% + 2% for all channels */
13909 + e1e_wphy(hw, 0x20DD, 0x249A);
13910 + /* ABS DC correction to 95.9% */
13911 + e1e_wphy(hw, 0x20DE, 0x00D3);
13912 + /* BG temp curve trim */
13913 + e1e_wphy(hw, 0x28B4, 0x04CE);
13914 + /* Increasing ADC OPAMP stage 1 currents to max */
13915 + e1e_wphy(hw, 0x2F70, 0x29E4);
13916 + /* Force 1000 ( required for enabling PHY regs configuration) */
13917 + e1e_wphy(hw, 0x0000, 0x0140);
13918 + /* Set upd_freq to 6 */
13919 + e1e_wphy(hw, 0x1F30, 0x1606);
13920 + /* Disable NPDFE */
13921 + e1e_wphy(hw, 0x1F31, 0xB814);
13922 + /* Disable adaptive fixed FFE (Default) */
13923 + e1e_wphy(hw, 0x1F35, 0x002A);
13924 + /* Enable FFE hysteresis */
13925 + e1e_wphy(hw, 0x1F3E, 0x0067);
13926 + /* Fixed FFE for short cable lengths */
13927 + e1e_wphy(hw, 0x1F54, 0x0065);
13928 + /* Fixed FFE for medium cable lengths */
13929 + e1e_wphy(hw, 0x1F55, 0x002A);
13930 + /* Fixed FFE for long cable lengths */
13931 + e1e_wphy(hw, 0x1F56, 0x002A);
13932 + /* Enable Adaptive Clip Threshold */
13933 + e1e_wphy(hw, 0x1F72, 0x3FB0);
13934 + /* AHT reset limit to 1 */
13935 + e1e_wphy(hw, 0x1F76, 0xC0FF);
13936 + /* Set AHT master delay to 127 msec */
13937 + e1e_wphy(hw, 0x1F77, 0x1DEC);
13938 + /* Set scan bits for AHT */
13939 + e1e_wphy(hw, 0x1F78, 0xF9EF);
13940 + /* Set AHT Preset bits */
13941 + e1e_wphy(hw, 0x1F79, 0x0210);
13942 + /* Change integ_factor of channel A to 3 */
13943 + e1e_wphy(hw, 0x1895, 0x0003);
13944 + /* Change prop_factor of channels BCD to 8 */
13945 + e1e_wphy(hw, 0x1796, 0x0008);
13946 + /* Change cg_icount + enable integbp for channels BCD */
13947 + e1e_wphy(hw, 0x1798, 0xD008);
13949 + * Change cg_icount + enable integbp + change prop_factor_master
13950 + * to 8 for channel A
13952 + e1e_wphy(hw, 0x1898, 0xD918);
13953 + /* Disable AHT in Slave mode on channel A */
13954 + e1e_wphy(hw, 0x187A, 0x0800);
13956 + * Enable LPLU and disable AN to 1000 in non-D0a states,
13959 + e1e_wphy(hw, 0x0019, 0x008D);
13960 + /* Enable restart AN on an1000_dis change */
13961 + e1e_wphy(hw, 0x001B, 0x2080);
13962 + /* Enable wh_fifo read clock in 10/100 modes */
13963 + e1e_wphy(hw, 0x0014, 0x0045);
13964 + /* Restart AN, Speed selection is 1000 */
13965 + e1e_wphy(hw, 0x0000, 0x1340);
13967 + return E1000_SUCCESS;
13971 + * e1000e_get_phy_type_from_id - Get PHY type from id
13972 + * @phy_id: phy_id read from the phy
13974 + * Returns the phy type from the id.
13976 +enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
13978 + enum e1000_phy_type phy_type = e1000_phy_unknown;
13980 + switch (phy_id) {
13981 + case M88E1000_I_PHY_ID:
13982 + case M88E1000_E_PHY_ID:
13983 + case M88E1111_I_PHY_ID:
13984 + case M88E1011_I_PHY_ID:
13985 + phy_type = e1000_phy_m88;
13987 + case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
13988 + phy_type = e1000_phy_igp_2;
13990 + case GG82563_E_PHY_ID:
13991 + phy_type = e1000_phy_gg82563;
13993 + case IGP03E1000_E_PHY_ID:
13994 + phy_type = e1000_phy_igp_3;
13996 + case IFE_E_PHY_ID:
13997 + case IFE_PLUS_E_PHY_ID:
13998 + case IFE_C_E_PHY_ID:
13999 + phy_type = e1000_phy_ife;
14001 + case BME1000_E_PHY_ID:
14002 + case BME1000_E_PHY_ID_R2:
14003 + phy_type = e1000_phy_bm;
14005 + case I82578_E_PHY_ID:
14006 + phy_type = e1000_phy_82578;
14008 + case I82577_E_PHY_ID:
14009 + phy_type = e1000_phy_82577;
14012 + phy_type = e1000_phy_unknown;
14019 + * e1000e_determine_phy_address - Determines PHY address.
14020 + * @hw: pointer to the HW structure
14022 + * This uses a trial and error method to loop through possible PHY
14023 + * addresses. It tests each by reading the PHY ID registers and
14024 + * checking for a match.
14026 +s32 e1000e_determine_phy_address(struct e1000_hw *hw)
14028 + s32 ret_val = -E1000_ERR_PHY_TYPE;
14029 + u32 phy_addr = 0;
14031 + enum e1000_phy_type phy_type = e1000_phy_unknown;
14033 + hw->phy.id = phy_type;
14035 + for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
14036 + hw->phy.addr = phy_addr;
14040 + e1000e_get_phy_id(hw);
14041 + phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
14044 + * If phy_type is valid, break - we found our
14047 + if (phy_type != e1000_phy_unknown) {
14048 + ret_val = E1000_SUCCESS;
14053 + } while (i < 10);
14061 + * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
14062 + * @page: page to access
14064 + * Returns the phy address for the page requested.
14066 +static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
14068 + u32 phy_addr = 2;
14070 + if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
14077 + * e1000e_write_phy_reg_bm - Write BM PHY register
14078 + * @hw: pointer to the HW structure
14079 + * @offset: register offset to write to
14080 + * @data: data to write at register offset
14082 + * Acquires semaphore, if necessary, then writes the data to PHY register
14083 + * at the offset. Release any acquired semaphores before exiting.
14085 +s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
14088 + u32 page_select = 0;
14089 + u32 page = offset >> IGP_PAGE_SHIFT;
14090 + u32 page_shift = 0;
14092 + /* Page 800 works differently than the rest so it has its own func */
14093 + if (page == BM_WUC_PAGE) {
14094 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
14099 + ret_val = hw->phy.ops.acquire(hw);
14103 + hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
14105 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14107 + * Page select is register 31 for phy address 1 and 22 for
14108 + * phy address 2 and 3. Page select is shifted only for
14111 + if (hw->phy.addr == 1) {
14112 + page_shift = IGP_PAGE_SHIFT;
14113 + page_select = IGP01E1000_PHY_PAGE_SELECT;
14116 + page_select = BM_PHY_PAGE_SELECT;
14119 + /* Page is shifted left, PHY expects (page x 32) */
14120 + ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
14121 + (page << page_shift));
14123 + hw->phy.ops.release(hw);
14128 + ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
14131 + hw->phy.ops.release(hw);
14138 + * e1000e_read_phy_reg_bm - Read BM PHY register
14139 + * @hw: pointer to the HW structure
14140 + * @offset: register offset to be read
14141 + * @data: pointer to the read data
14143 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14144 + * and storing the retrieved information in data. Release any acquired
14145 + * semaphores before exiting.
14147 +s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
14150 + u32 page_select = 0;
14151 + u32 page = offset >> IGP_PAGE_SHIFT;
14152 + u32 page_shift = 0;
14154 + /* Page 800 works differently than the rest so it has its own func */
14155 + if (page == BM_WUC_PAGE) {
14156 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
14161 + ret_val = hw->phy.ops.acquire(hw);
14165 + hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
14167 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14169 + * Page select is register 31 for phy address 1 and 22 for
14170 + * phy address 2 and 3. Page select is shifted only for
14173 + if (hw->phy.addr == 1) {
14174 + page_shift = IGP_PAGE_SHIFT;
14175 + page_select = IGP01E1000_PHY_PAGE_SELECT;
14178 + page_select = BM_PHY_PAGE_SELECT;
14181 + /* Page is shifted left, PHY expects (page x 32) */
14182 + ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
14183 + (page << page_shift));
14185 + hw->phy.ops.release(hw);
14190 + ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
14192 + hw->phy.ops.release(hw);
14199 + * e1000e_read_phy_reg_bm2 - Read BM PHY register
14200 + * @hw: pointer to the HW structure
14201 + * @offset: register offset to be read
14202 + * @data: pointer to the read data
14204 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14205 + * and storing the retrieved information in data. Release any acquired
14206 + * semaphores before exiting.
14208 +s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
14211 + u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
14213 + /* Page 800 works differently than the rest so it has its own func */
14214 + if (page == BM_WUC_PAGE) {
14215 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
14220 + ret_val = hw->phy.ops.acquire(hw);
14224 + hw->phy.addr = 1;
14226 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14228 + /* Page is shifted left, PHY expects (page x 32) */
14229 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
14233 + hw->phy.ops.release(hw);
14238 + ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
14240 + hw->phy.ops.release(hw);
14247 + * e1000e_write_phy_reg_bm2 - Write BM PHY register
14248 + * @hw: pointer to the HW structure
14249 + * @offset: register offset to write to
14250 + * @data: data to write at register offset
14252 + * Acquires semaphore, if necessary, then writes the data to PHY register
14253 + * at the offset. Release any acquired semaphores before exiting.
14255 +s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
14258 + u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
14260 + /* Page 800 works differently than the rest so it has its own func */
14261 + if (page == BM_WUC_PAGE) {
14262 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
14267 + ret_val = hw->phy.ops.acquire(hw);
14271 + hw->phy.addr = 1;
14273 + if (offset > MAX_PHY_MULTI_PAGE_REG) {
14274 + /* Page is shifted left, PHY expects (page x 32) */
14275 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
14279 + hw->phy.ops.release(hw);
14284 + ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
14287 + hw->phy.ops.release(hw);
14294 + * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
14295 + * @hw: pointer to the HW structure
14296 + * @offset: register offset to be read or written
14297 + * @data: pointer to the data to read or write
14298 + * @read: determines if operation is read or write
14300 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14301 + * and storing the retrieved information in data. Release any acquired
14302 + * semaphores before exiting. Note that procedure to read the wakeup
14303 + * registers are different. It works as such:
14304 + * 1) Set page 769, register 17, bit 2 = 1
14305 + * 2) Set page to 800 for host (801 if we were manageability)
14306 + * 3) Write the address using the address opcode (0x11)
14307 + * 4) Read or write the data using the data opcode (0x12)
14308 + * 5) Restore 769_17.2 to its original value
14310 +static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
14311 + u16 *data, bool read)
14314 + u16 reg = BM_PHY_REG_NUM(offset);
14316 + u8 phy_acquired = 1;
14318 + /* Gig must be disabled for MDIO accesses to page 800 */
14319 + if ((hw->mac.type == e1000_pchlan) &&
14320 + (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
14321 + e_dbg("Attempting to access page 800 while gig enabled.\n");
14323 + ret_val = hw->phy.ops.acquire(hw);
14325 + e_dbg("Could not acquire PHY\n");
14326 + phy_acquired = 0;
14330 + /* All operations in this function are phy address 1 */
14331 + hw->phy.addr = 1;
14333 + /* Set page 769 */
14334 + e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
14335 + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
14337 + ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
14339 + e_dbg("Could not read PHY page 769\n");
14343 + /* First clear bit 4 to avoid a power state change */
14344 + phy_reg &= ~(BM_WUC_HOST_WU_BIT);
14345 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
14347 + e_dbg("Could not clear PHY page 769 bit 4\n");
14351 + /* Write bit 2 = 1, and clear bit 4 to 769_17 */
14352 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
14353 + phy_reg | BM_WUC_ENABLE_BIT);
14355 + e_dbg("Could not write PHY page 769 bit 2\n");
14359 + /* Select page 800 */
14360 + ret_val = e1000e_write_phy_reg_mdic(hw,
14361 + IGP01E1000_PHY_PAGE_SELECT,
14362 + (BM_WUC_PAGE << IGP_PAGE_SHIFT));
14364 + /* Write the page 800 offset value using opcode 0x11 */
14365 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
14367 + e_dbg("Could not write address opcode to page 800\n");
14372 + /* Read the page 800 value using opcode 0x12 */
14373 + ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
14376 + /* Write the page 800 value using opcode 0x12 */
14377 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
14382 + e_dbg("Could not access data value from page 800\n");
14387 + * Restore 769_17.2 to its original value
14390 + e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
14391 + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
14393 + /* Clear 769_17.2 */
14394 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
14396 + e_dbg("Could not clear PHY page 769 bit 2\n");
14401 + if (phy_acquired == 1)
14402 + hw->phy.ops.release(hw);
14407 + * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
14408 + * @hw: pointer to the HW structure
14410 + * In the case of a PHY power down to save power, or to turn off link during a
14411 + * driver unload, or wake on lan is not enabled, restore the link to previous
14414 +void e1000_power_up_phy_copper(struct e1000_hw *hw)
14418 + /* The PHY will retain its settings across a power down/up cycle */
14419 + e1e_rphy(hw, PHY_CONTROL, &mii_reg);
14420 + mii_reg &= ~MII_CR_POWER_DOWN;
14421 + e1e_wphy(hw, PHY_CONTROL, mii_reg);
14425 + * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
14426 + * @hw: pointer to the HW structure
14428 + * In the case of a PHY power down to save power, or to turn off link during a
14429 + * driver unload, or wake on lan is not enabled, restore the link to previous
14432 +void e1000_power_down_phy_copper(struct e1000_hw *hw)
14436 + /* The PHY will retain its settings across a power down/up cycle */
14437 + e1e_rphy(hw, PHY_CONTROL, &mii_reg);
14438 + mii_reg |= MII_CR_POWER_DOWN;
14439 + e1e_wphy(hw, PHY_CONTROL, mii_reg);
14443 +s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
14445 + s32 ret_val = E1000_SUCCESS;
14448 + ret_val = hw->phy.ops.acquire(hw);
14452 + /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
14453 + hw->phy.addr = 1;
14454 + ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
14455 + (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
14457 + hw->phy.ops.release(hw);
14460 + ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
14461 + (0x2180 | (slow << 10)));
14463 + /* dummy read when reverting to fast mode - throw away result */
14465 + e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
14467 + hw->phy.ops.release(hw);
14473 + * e1000_read_phy_reg_hv - Read HV PHY register
14474 + * @hw: pointer to the HW structure
14475 + * @offset: register offset to be read
14476 + * @data: pointer to the read data
14478 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14479 + * and storing the retrieved information in data. Release any acquired
14480 + * semaphore before exiting.
14482 +s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
14485 + u16 page = BM_PHY_REG_PAGE(offset);
14486 + u16 reg = BM_PHY_REG_NUM(offset);
14487 + bool in_slow_mode = false;
14489 + /* Workaround failure in MDIO access while cable is disconnected */
14490 + if ((hw->phy.type == e1000_phy_82577) &&
14491 + !(er32(STATUS) & E1000_STATUS_LU)) {
14492 + ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
14496 + in_slow_mode = true;
14499 + /* Page 800 works differently than the rest so it has its own func */
14500 + if (page == BM_WUC_PAGE) {
14501 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
14506 + if (page > 0 && page < HV_INTC_FC_PAGE_START) {
14507 + ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
14512 + ret_val = hw->phy.ops.acquire(hw);
14516 + hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
14518 + if (page == HV_INTC_FC_PAGE_START)
14521 + if (reg > MAX_PHY_MULTI_PAGE_REG) {
14522 + if ((hw->phy.type != e1000_phy_82578) ||
14523 + ((reg != I82578_ADDR_REG) &&
14524 + (reg != I82578_ADDR_REG + 1))) {
14525 + u32 phy_addr = hw->phy.addr;
14527 + hw->phy.addr = 1;
14529 + /* Page is shifted left, PHY expects (page x 32) */
14530 + ret_val = e1000e_write_phy_reg_mdic(hw,
14531 + IGP01E1000_PHY_PAGE_SELECT,
14532 + (page << IGP_PAGE_SHIFT));
14534 + hw->phy.ops.release(hw);
14537 + hw->phy.addr = phy_addr;
14541 + ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
14543 + hw->phy.ops.release(hw);
14546 + /* Revert to MDIO fast mode, if applicable */
14547 + if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
14548 + ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
14554 + * e1000_write_phy_reg_hv - Write HV PHY register
14555 + * @hw: pointer to the HW structure
14556 + * @offset: register offset to write to
14557 + * @data: data to write at register offset
14559 + * Acquires semaphore, if necessary, then writes the data to PHY register
14560 + * at the offset. Release any acquired semaphores before exiting.
14562 +s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
14565 + u16 page = BM_PHY_REG_PAGE(offset);
14566 + u16 reg = BM_PHY_REG_NUM(offset);
14567 + bool in_slow_mode = false;
14569 + /* Workaround failure in MDIO access while cable is disconnected */
14570 + if ((hw->phy.type == e1000_phy_82577) &&
14571 + !(er32(STATUS) & E1000_STATUS_LU)) {
14572 + ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
14576 + in_slow_mode = true;
14579 + /* Page 800 works differently than the rest so it has its own func */
14580 + if (page == BM_WUC_PAGE) {
14581 + ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
14586 + if (page > 0 && page < HV_INTC_FC_PAGE_START) {
14587 + ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
14592 + ret_val = hw->phy.ops.acquire(hw);
14596 + hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
14598 + if (page == HV_INTC_FC_PAGE_START)
14602 + * Workaround MDIO accesses being disabled after entering IEEE Power
14603 + * Down (whenever bit 11 of the PHY Control register is set)
14605 + if ((hw->phy.type == e1000_phy_82578) &&
14606 + (hw->phy.revision >= 1) &&
14607 + (hw->phy.addr == 2) &&
14608 + ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
14609 + (data & (1 << 11))) {
14610 + u16 data2 = 0x7EFF;
14611 + hw->phy.ops.release(hw);
14612 + ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
14617 + ret_val = hw->phy.ops.acquire(hw);
14622 + if (reg > MAX_PHY_MULTI_PAGE_REG) {
14623 + if ((hw->phy.type != e1000_phy_82578) ||
14624 + ((reg != I82578_ADDR_REG) &&
14625 + (reg != I82578_ADDR_REG + 1))) {
14626 + u32 phy_addr = hw->phy.addr;
14628 + hw->phy.addr = 1;
14630 + /* Page is shifted left, PHY expects (page x 32) */
14631 + ret_val = e1000e_write_phy_reg_mdic(hw,
14632 + IGP01E1000_PHY_PAGE_SELECT,
14633 + (page << IGP_PAGE_SHIFT));
14635 + hw->phy.ops.release(hw);
14638 + hw->phy.addr = phy_addr;
14642 + ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
14644 + hw->phy.ops.release(hw);
14647 + /* Revert to MDIO fast mode, if applicable */
14648 + if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
14649 + ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
14655 + * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
14656 + * @page: page to be accessed
14658 +static u32 e1000_get_phy_addr_for_hv_page(u32 page)
14660 + u32 phy_addr = 2;
14662 + if (page >= HV_INTC_FC_PAGE_START)
14669 + * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
14670 + * @hw: pointer to the HW structure
14671 + * @offset: register offset to be read or written
14672 + * @data: pointer to the data to be read or written
14673 + * @read: determines if operation is read or written
14675 + * Acquires semaphore, if necessary, then reads the PHY register at offset
14676 + * and storing the retreived information in data. Release any acquired
14677 + * semaphores before exiting. Note that the procedure to read these regs
14678 + * uses the address port and data port to read/write.
14680 +static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
14681 + u16 *data, bool read)
14684 + u32 addr_reg = 0;
14685 + u32 data_reg = 0;
14686 + u8 phy_acquired = 1;
14688 + /* This takes care of the difference with desktop vs mobile phy */
14689 + addr_reg = (hw->phy.type == e1000_phy_82578) ?
14690 + I82578_ADDR_REG : I82577_ADDR_REG;
14691 + data_reg = addr_reg + 1;
14693 + ret_val = hw->phy.ops.acquire(hw);
14695 + e_dbg("Could not acquire PHY\n");
14696 + phy_acquired = 0;
14700 + /* All operations in this function are phy address 2 */
14701 + hw->phy.addr = 2;
14703 + /* masking with 0x3F to remove the page from offset */
14704 + ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
14706 + e_dbg("Could not write PHY the HV address register\n");
14710 + /* Read or write the data value next */
14712 + ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
14714 + ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
14717 + e_dbg("Could not read data value from HV data register\n");
14722 + if (phy_acquired == 1)
14723 + hw->phy.ops.release(hw);
14728 + * e1000_link_stall_workaround_hv - Si workaround
14729 + * @hw: pointer to the HW structure
14731 + * This function works around a Si bug where the link partner can get
14732 + * a link up indication before the PHY does. If small packets are sent
14733 + * by the link partner they can be placed in the packet buffer without
14734 + * being properly accounted for by the PHY and will stall preventing
14735 + * further packets from being received. The workaround is to clear the
14736 + * packet buffer after the PHY detects link up.
14738 +s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
14740 + s32 ret_val = E1000_SUCCESS;
14743 + if (hw->phy.type != e1000_phy_82578)
14746 + /* Do not apply workaround if in PHY loopback bit 14 set */
14747 + e1e_rphy(hw, PHY_CONTROL, &data);
14748 + if (data & PHY_CONTROL_LB)
14751 + /* check if link is up and at 1Gbps */
14752 + ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
14756 + data &= BM_CS_STATUS_LINK_UP |
14757 + BM_CS_STATUS_RESOLVED |
14758 + BM_CS_STATUS_SPEED_MASK;
14760 + if (data != (BM_CS_STATUS_LINK_UP |
14761 + BM_CS_STATUS_RESOLVED |
14762 + BM_CS_STATUS_SPEED_1000))
14767 + /* flush the packets in the fifo buffer */
14768 + ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
14769 + HV_MUX_DATA_CTRL_GEN_TO_MAC |
14770 + HV_MUX_DATA_CTRL_FORCE_SPEED);
14774 + ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
14775 + HV_MUX_DATA_CTRL_GEN_TO_MAC);
14782 + * e1000_check_polarity_82577 - Checks the polarity.
14783 + * @hw: pointer to the HW structure
14785 + * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
14787 + * Polarity is determined based on the PHY specific status register.
14789 +s32 e1000_check_polarity_82577(struct e1000_hw *hw)
14791 + struct e1000_phy_info *phy = &hw->phy;
14795 + ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
14798 + phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
14799 + ? e1000_rev_polarity_reversed
14800 + : e1000_rev_polarity_normal;
14806 + * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
14807 + * @hw: pointer to the HW structure
14809 + * Calls the PHY setup function to force speed and duplex. Clears the
14810 + * auto-crossover to force MDI manually. Waits for link and returns
14811 + * successful if link up is successful, else -E1000_ERR_PHY (-2).
14813 +s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
14815 + struct e1000_phy_info *phy = &hw->phy;
14820 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
14824 + e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
14826 + ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
14831 + * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
14832 + * forced whenever speed and duplex are forced.
14834 + ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
14838 + phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
14839 + phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
14841 + ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
14845 + e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data);
14849 + if (phy->autoneg_wait_to_complete) {
14850 + e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
14852 + ret_val = e1000e_phy_has_link_generic(hw,
14860 + e_dbg("Link taking longer than expected.\n");
14862 + /* Try once more */
14863 + ret_val = e1000e_phy_has_link_generic(hw,
14876 + * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
14877 + * @hw: pointer to the HW structure
14879 + * Read PHY status to determine if link is up. If link is up, then
14880 + * set/determine 10base-T extended distance and polarity correction. Read
14881 + * PHY port status to determine MDI/MDIx and speed. Based on the speed,
14882 + * determine on the cable length, local and remote receiver.
14884 +s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
14886 + struct e1000_phy_info *phy = &hw->phy;
14891 + ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
14896 + e_dbg("Phy info is only valid if link is up\n");
14897 + ret_val = -E1000_ERR_CONFIG;
14901 + phy->polarity_correction = true;
14903 + ret_val = e1000_check_polarity_82577(hw);
14907 + ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
14911 + phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
14913 + if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
14914 + I82577_PHY_STATUS2_SPEED_1000MBPS) {
14915 + ret_val = e1000_get_cable_length(hw);
14919 + ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
14923 + phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
14924 + ? e1000_1000t_rx_status_ok
14925 + : e1000_1000t_rx_status_not_ok;
14927 + phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
14928 + ? e1000_1000t_rx_status_ok
14929 + : e1000_1000t_rx_status_not_ok;
14931 + phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
14932 + phy->local_rx = e1000_1000t_rx_status_undefined;
14933 + phy->remote_rx = e1000_1000t_rx_status_undefined;
14941 + * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
14942 + * @hw: pointer to the HW structure
14944 + * Reads the diagnostic status register and verifies result is valid before
14945 + * placing it in the phy_cable_length field.
14947 +s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
14949 + struct e1000_phy_info *phy = &hw->phy;
14951 + u16 phy_data, length;
14953 + ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
14957 + length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
14958 + I82577_DSTATUS_CABLE_LENGTH_SHIFT;
14960 + if (length == E1000_CABLE_LENGTH_UNDEFINED)
14961 + ret_val = E1000_ERR_PHY;
14963 + phy->cable_length = length;
14968 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_phy.h linux-2.6.22-10/drivers/net/e1000e/e1000_phy.h
14969 --- linux-2.6.22-0/drivers/net/e1000e/e1000_phy.h 1970-01-01 01:00:00.000000000 +0100
14970 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_phy.h 2009-06-24 00:32:20.000000000 +0200
14972 +/*******************************************************************************
14974 + Intel PRO/1000 Linux driver
14975 + Copyright(c) 1999 - 2009 Intel Corporation.
14977 + This program is free software; you can redistribute it and/or modify it
14978 + under the terms and conditions of the GNU General Public License,
14979 + version 2, as published by the Free Software Foundation.
14981 + This program is distributed in the hope it will be useful, but WITHOUT
14982 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14983 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14986 + You should have received a copy of the GNU General Public License along with
14987 + this program; if not, write to the Free Software Foundation, Inc.,
14988 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
14990 + The full GNU General Public License is included in this distribution in
14991 + the file called "COPYING".
14993 + Contact Information:
14994 + Linux NICS <linux.nics@intel.com>
14995 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
14996 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
14998 +*******************************************************************************/
15000 +#ifndef _E1000_PHY_H_
15001 +#define _E1000_PHY_H_
15003 +void e1000_init_phy_ops_generic(struct e1000_hw *hw);
15004 +s32 e1000e_check_downshift(struct e1000_hw *hw);
15005 +s32 e1000_check_polarity_m88(struct e1000_hw *hw);
15006 +s32 e1000_check_polarity_igp(struct e1000_hw *hw);
15007 +s32 e1000_check_polarity_ife(struct e1000_hw *hw);
15008 +s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
15009 +s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
15010 +s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
15011 +s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
15012 +s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
15013 +s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
15014 +s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
15015 +s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
15016 +s32 e1000e_get_cfg_done(struct e1000_hw *hw);
15017 +s32 e1000e_get_phy_id(struct e1000_hw *hw);
15018 +s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
15019 +s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
15020 +s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
15021 +void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
15022 +s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
15023 +s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
15024 +s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
15025 +s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
15026 +s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
15027 +s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
15028 +s32 e1000e_setup_copper_link(struct e1000_hw *hw);
15029 +s32 e1000_wait_autoneg(struct e1000_hw *hw);
15030 +s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
15031 +s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
15032 +s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
15033 +s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
15034 +s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
15035 + u32 usec_interval, bool *success);
15036 +s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
15037 +enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
15038 +s32 e1000e_determine_phy_address(struct e1000_hw *hw);
15039 +s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
15040 +s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
15041 +s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
15042 +s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
15043 +void e1000_power_up_phy_copper(struct e1000_hw *hw);
15044 +void e1000_power_down_phy_copper(struct e1000_hw *hw);
15045 +s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
15046 +s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
15047 +s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
15048 +s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
15049 +s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow);
15050 +s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
15051 +s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
15052 +s32 e1000_check_polarity_82577(struct e1000_hw *hw);
15053 +s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
15054 +s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
15055 +s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
15057 +#define E1000_MAX_PHY_ADDR 4
15059 +/* IGP01E1000 Specific Registers */
15060 +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
15061 +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
15062 +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
15063 +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
15064 +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
15065 +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
15066 +#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
15067 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
15068 +#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
15069 +#define IGP_PAGE_SHIFT 5
15070 +#define PHY_REG_MASK 0x1F
15072 +/* BM/HV Specific Registers */
15073 +#define BM_PORT_CTRL_PAGE 769
15074 +#define BM_PCIE_PAGE 770
15075 +#define BM_WUC_PAGE 800
15076 +#define BM_WUC_ADDRESS_OPCODE 0x11
15077 +#define BM_WUC_DATA_OPCODE 0x12
15078 +#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
15079 +#define BM_WUC_ENABLE_REG 17
15080 +#define BM_WUC_ENABLE_BIT (1 << 2)
15081 +#define BM_WUC_HOST_WU_BIT (1 << 4)
15083 +#define PHY_UPPER_SHIFT 21
15084 +#define BM_PHY_REG(page, reg) \
15085 + (((reg) & MAX_PHY_REG_ADDRESS) |\
15086 + (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
15087 + (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
15088 +#define BM_PHY_REG_PAGE(offset) \
15089 + ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
15090 +#define BM_PHY_REG_NUM(offset) \
15091 + ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
15092 + (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
15093 + ~MAX_PHY_REG_ADDRESS)))
15095 +#define HV_INTC_FC_PAGE_START 768
15096 +#define I82578_ADDR_REG 29
15097 +#define I82577_ADDR_REG 16
15098 +#define I82577_CFG_REG 22
15099 +#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
15100 +#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
15101 +#define I82577_CTRL_REG 23
15102 +#define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
15104 +/* 82577 specific PHY registers */
15105 +#define I82577_PHY_CTRL_2 18
15106 +#define I82577_PHY_LBK_CTRL 19
15107 +#define I82577_PHY_STATUS_2 26
15108 +#define I82577_PHY_DIAG_STATUS 31
15110 +/* I82577 PHY Status 2 */
15111 +#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
15112 +#define I82577_PHY_STATUS2_MDIX 0x0800
15113 +#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
15114 +#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
15115 +#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100
15117 +/* I82577 PHY Control 2 */
15118 +#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
15119 +#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
15121 +/* I82577 PHY Diagnostics Status */
15122 +#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
15123 +#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
15125 +/* BM PHY Copper Specific Control 1 */
15126 +#define BM_CS_CTRL1 16
15127 +#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */
15129 +/* BM PHY Copper Specific Status */
15130 +#define BM_CS_STATUS 17
15131 +#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */
15132 +#define BM_CS_STATUS_LINK_UP 0x0400
15133 +#define BM_CS_STATUS_RESOLVED 0x0800
15134 +#define BM_CS_STATUS_SPEED_MASK 0xC000
15135 +#define BM_CS_STATUS_SPEED_1000 0x8000
15137 +#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
15138 +#define IGP01E1000_PHY_POLARITY_MASK 0x0078
15140 +#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
15141 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
15143 +#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
15145 +/* Enable flexible speed on link-up */
15146 +#define IGP01E1000_GMII_FLEX_SPD 0x0010
15147 +#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
15149 +#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
15150 +#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
15151 +#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
15153 +#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
15155 +#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
15156 +#define IGP01E1000_PSSR_MDIX 0x0800
15157 +#define IGP01E1000_PSSR_SPEED_MASK 0xC000
15158 +#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
15160 +#define IGP02E1000_PHY_CHANNEL_NUM 4
15161 +#define IGP02E1000_PHY_AGC_A 0x11B1
15162 +#define IGP02E1000_PHY_AGC_B 0x12B1
15163 +#define IGP02E1000_PHY_AGC_C 0x14B1
15164 +#define IGP02E1000_PHY_AGC_D 0x18B1
15166 +#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
15167 +#define IGP02E1000_AGC_LENGTH_MASK 0x7F
15168 +#define IGP02E1000_AGC_RANGE 15
15170 +#define IGP03E1000_PHY_MISC_CTRL 0x1B
15171 +#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
15173 +#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
15175 +#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
15176 +#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
15177 +#define E1000_KMRNCTRLSTA_REN 0x00200000
15178 +#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
15179 +#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
15180 +#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
15181 +#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
15182 +#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
15183 +#define E1000_KMRNCTRLSTA_K1_ENABLE 0x140E
15184 +#define E1000_KMRNCTRLSTA_K1_DISABLE 0x1400
15186 +#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
15187 +#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
15188 +#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
15189 +#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
15191 +/* IFE PHY Extended Status Control */
15192 +#define IFE_PESC_POLARITY_REVERSED 0x0100
15194 +/* IFE PHY Special Control */
15195 +#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
15196 +#define IFE_PSC_FORCE_POLARITY 0x0020
15197 +#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
15199 +/* IFE PHY Special Control and LED Control */
15200 +#define IFE_PSCL_PROBE_MODE 0x0020
15201 +#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
15202 +#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
15204 +/* IFE PHY MDIX Control */
15205 +#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
15206 +#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
15207 +#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
15210 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_regs.h linux-2.6.22-10/drivers/net/e1000e/e1000_regs.h
15211 --- linux-2.6.22-0/drivers/net/e1000e/e1000_regs.h 1970-01-01 01:00:00.000000000 +0100
15212 +++ linux-2.6.22-10/drivers/net/e1000e/e1000_regs.h 2009-06-24 00:32:20.000000000 +0200
15214 +/*******************************************************************************
15216 + Intel PRO/1000 Linux driver
15217 + Copyright(c) 1999 - 2009 Intel Corporation.
15219 + This program is free software; you can redistribute it and/or modify it
15220 + under the terms and conditions of the GNU General Public License,
15221 + version 2, as published by the Free Software Foundation.
15223 + This program is distributed in the hope it will be useful, but WITHOUT
15224 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15225 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15228 + You should have received a copy of the GNU General Public License along with
15229 + this program; if not, write to the Free Software Foundation, Inc.,
15230 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
15232 + The full GNU General Public License is included in this distribution in
15233 + the file called "COPYING".
15235 + Contact Information:
15236 + Linux NICS <linux.nics@intel.com>
15237 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
15238 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15240 +*******************************************************************************/
15242 +#ifndef _E1000_REGS_H_
15243 +#define _E1000_REGS_H_
15245 +#define E1000_CTRL 0x00000 /* Device Control - RW */
15246 +#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
15247 +#define E1000_STATUS 0x00008 /* Device Status - RO */
15248 +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
15249 +#define E1000_EERD 0x00014 /* EEPROM Read - RW */
15250 +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
15251 +#define E1000_FLA 0x0001C /* Flash Access - RW */
15252 +#define E1000_MDIC 0x00020 /* MDI Control - RW */
15253 +#define E1000_SCTL 0x00024 /* SerDes Control - RW */
15254 +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
15255 +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
15256 +#define E1000_FEXT 0x0002C /* Future Extended - RW */
15257 +#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
15258 +#define E1000_FCT 0x00030 /* Flow Control Type - RW */
15259 +#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
15260 +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
15261 +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
15262 +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
15263 +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
15264 +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
15265 +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
15266 +#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
15267 +#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
15268 +#define E1000_SVCR 0x000F0
15269 +#define E1000_SVT 0x000F4
15270 +#define E1000_RCTL 0x00100 /* Rx Control - RW */
15271 +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
15272 +#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
15273 +#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
15274 +#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
15275 +#define E1000_TCTL 0x00400 /* Tx Control - RW */
15276 +#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
15277 +#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
15278 +#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
15279 +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
15280 +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
15281 +#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
15282 +#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
15283 +#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
15284 +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
15285 +#define E1000_PBS 0x01008 /* Packet Buffer Size */
15286 +#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
15287 +#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
15288 +#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
15289 +#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
15290 +#define E1000_FLSWCTL 0x01030 /* FLASH control register */
15291 +#define E1000_FLSWDATA 0x01034 /* FLASH data register */
15292 +#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
15293 +#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
15294 +#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
15295 +#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
15296 +#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
15297 +#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
15298 +#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
15299 +#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
15300 +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
15301 +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
15302 +#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
15303 +#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
15304 +#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
15305 +#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
15306 +/* Split and Replication Rx Control - RW */
15307 +#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
15308 +#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
15309 +#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
15310 +#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
15311 +#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
15312 +#define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n)))
15313 +#define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n)))
15314 +#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
15315 +#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
15317 + * Convenience macros
15319 + * Note: "_n" is the queue number of the register to be written to.
15322 + * E1000_RDBAL_REG(current_rx_queue)
15324 +#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
15325 + (0x0C000 + ((_n) * 0x40)))
15326 +#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
15327 + (0x0C004 + ((_n) * 0x40)))
15328 +#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
15329 + (0x0C008 + ((_n) * 0x40)))
15330 +#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
15331 + (0x0C00C + ((_n) * 0x40)))
15332 +#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
15333 + (0x0C010 + ((_n) * 0x40)))
15334 +#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
15335 + (0x0C018 + ((_n) * 0x40)))
15336 +#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
15337 + (0x0C028 + ((_n) * 0x40)))
15338 +#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
15339 + (0x0E000 + ((_n) * 0x40)))
15340 +#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
15341 + (0x0E004 + ((_n) * 0x40)))
15342 +#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
15343 + (0x0E008 + ((_n) * 0x40)))
15344 +#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
15345 + (0x0E010 + ((_n) * 0x40)))
15346 +#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
15347 + (0x0E018 + ((_n) * 0x40)))
15348 +#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
15349 + (0x0E028 + ((_n) * 0x40)))
15350 +#define E1000_TARC(_n) (0x03840 + (_n << 8))
15351 +#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
15352 +#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
15353 +#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
15354 + (0x0E038 + ((_n) * 0x40)))
15355 +#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
15356 + (0x0E03C + ((_n) * 0x40)))
15357 +#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
15358 +#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
15359 +#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
15360 +#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
15361 +#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
15362 +#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
15363 + (0x054E0 + ((_i - 16) * 8)))
15364 +#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
15365 + (0x054E4 + ((_i - 16) * 8)))
15366 +#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
15367 +#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
15368 +#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
15369 +#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
15370 +#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
15371 +#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
15372 +#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
15373 +#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
15374 +#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
15375 +#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
15376 +#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
15377 +#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
15378 +#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
15379 +#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
15380 +#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
15381 +#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
15382 +#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
15383 +#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
15384 +#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
15385 +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
15386 +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
15387 +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
15388 +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
15389 +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
15390 +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
15391 +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
15392 +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
15393 +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
15394 +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
15395 +#define E1000_COLC 0x04028 /* Collision Count - R/clr */
15396 +#define E1000_DC 0x04030 /* Defer Count - R/clr */
15397 +#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
15398 +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
15399 +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
15400 +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
15401 +#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
15402 +#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
15403 +#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
15404 +#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
15405 +#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
15406 +#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
15407 +#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
15408 +#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
15409 +#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
15410 +#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
15411 +#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
15412 +#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
15413 +#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
15414 +#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
15415 +#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
15416 +#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
15417 +#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
15418 +#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
15419 +#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
15420 +#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
15421 +#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
15422 +#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
15423 +#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
15424 +#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
15425 +#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
15426 +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
15427 +#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
15428 +#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
15429 +#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
15430 +#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
15431 +#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
15432 +#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
15433 +#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
15434 +#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
15435 +#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
15436 +#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
15437 +#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
15438 +#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
15439 +#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
15440 +#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
15441 +#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
15442 +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
15443 +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
15444 +#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
15445 +#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
15446 +#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
15447 +#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
15448 +#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */
15449 +#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
15450 +#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */
15451 +#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
15452 +#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
15454 + * The CRC offset register is undocumented because it is for future use and
15455 + * may change in the future.
15457 +#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */
15459 +#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
15460 +#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
15461 +#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
15462 +#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */
15463 +#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
15464 +#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
15465 +#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
15466 +#define E1000_RPTHC 0x04104 /* Rx Packets To Host */
15467 +#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */
15468 +#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */
15469 +#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
15470 +#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
15471 +#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
15472 +#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
15473 +#define E1000_LENERRS 0x04138 /* Length Errors Count */
15474 +#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
15475 +#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */
15476 +#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
15477 +#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
15478 +#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
15479 +#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
15480 +#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */
15481 +#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
15482 +#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
15483 +#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
15484 +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
15485 +#define E1000_RA 0x05400 /* Receive Address - RW Array */
15486 +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
15487 +#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
15488 +#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
15489 +#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
15490 +#define E1000_WUC 0x05800 /* Wakeup Control - RW */
15491 +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
15492 +#define E1000_WUS 0x05810 /* Wakeup Status - RO */
15493 +#define E1000_MANC 0x05820 /* Management Control - RW */
15494 +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
15495 +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
15496 +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
15497 +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
15498 +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
15499 +#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
15500 +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
15501 +#define E1000_HOST_IF 0x08800 /* Host Interface */
15502 +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
15503 +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
15505 +#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
15506 +#define E1000_MDPHYA 0x0003C /* PHY address - RW */
15507 +#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
15508 +#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
15509 +#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
15510 +#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
15511 +#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
15512 +#define E1000_GCR 0x05B00 /* PCI-Ex Control */
15513 +#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
15514 +#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
15515 +#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
15516 +#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
15517 +#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
15518 +#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
15519 +#define E1000_SWSM 0x05B50 /* SW Semaphore */
15520 +#define E1000_FWSM 0x05B54 /* FW Semaphore */
15521 +#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
15522 +#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
15523 +#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
15524 +#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
15525 +#define E1000_HICR 0x08F00 /* Host Interface Control */
15527 +/* RSS registers */
15528 +#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
15529 +#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
15530 +#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
15531 +#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
15532 +#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
15533 +#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
15535 +#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
15536 + * low reg - RW */
15537 +#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
15538 + * upper reg - RW */
15539 +#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
15540 + * message reg - RW */
15541 +#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
15542 + * vector ctrl reg - RW */
15543 +#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */
15544 +#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
15545 +#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
15546 +#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
15547 +#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
15548 +#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
15549 +#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
15552 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/ethtool.c linux-2.6.22-10/drivers/net/e1000e/ethtool.c
15553 --- linux-2.6.22-0/drivers/net/e1000e/ethtool.c 1970-01-01 01:00:00.000000000 +0100
15554 +++ linux-2.6.22-10/drivers/net/e1000e/ethtool.c 2009-06-24 00:32:20.000000000 +0200
15556 +/*******************************************************************************
15558 + Intel PRO/1000 Linux driver
15559 + Copyright(c) 1999 - 2009 Intel Corporation.
15561 + This program is free software; you can redistribute it and/or modify it
15562 + under the terms and conditions of the GNU General Public License,
15563 + version 2, as published by the Free Software Foundation.
15565 + This program is distributed in the hope it will be useful, but WITHOUT
15566 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15567 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15570 + You should have received a copy of the GNU General Public License along with
15571 + this program; if not, write to the Free Software Foundation, Inc.,
15572 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
15574 + The full GNU General Public License is included in this distribution in
15575 + the file called "COPYING".
15577 + Contact Information:
15578 + Linux NICS <linux.nics@intel.com>
15579 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
15580 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15582 +*******************************************************************************/
15584 +/* ethtool support for e1000 */
15586 +#include <linux/netdevice.h>
15587 +#ifdef SIOCETHTOOL
15588 +#include <linux/ethtool.h>
15589 +#include <linux/pci.h>
15590 +#include <linux/delay.h>
15592 +#include "e1000.h"
15593 +#ifdef NETIF_F_HW_VLAN_TX
15594 +#include <linux/if_vlan.h>
15596 +#ifdef ETHTOOL_OPS_COMPAT
15597 +#include "kcompat_ethtool.c"
15600 +struct e1000_stats {
15601 + char stat_string[ETH_GSTRING_LEN];
15606 +#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
15607 + offsetof(struct e1000_adapter, m)
15608 +static const struct e1000_stats e1000_gstrings_stats[] = {
15609 + { "rx_packets", E1000_STAT(stats.gprc) },
15610 + { "tx_packets", E1000_STAT(stats.gptc) },
15611 + { "rx_bytes", E1000_STAT(stats.gorc) },
15612 + { "tx_bytes", E1000_STAT(stats.gotc) },
15613 + { "rx_broadcast", E1000_STAT(stats.bprc) },
15614 + { "tx_broadcast", E1000_STAT(stats.bptc) },
15615 + { "rx_multicast", E1000_STAT(stats.mprc) },
15616 + { "tx_multicast", E1000_STAT(stats.mptc) },
15617 + { "rx_errors", E1000_STAT(net_stats.rx_errors) },
15618 + { "tx_errors", E1000_STAT(net_stats.tx_errors) },
15619 +#ifndef CONFIG_E1000E_NAPI
15620 + { "rx_dropped_backlog", E1000_STAT(rx_dropped_backlog) },
15622 + { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
15623 + { "multicast", E1000_STAT(stats.mprc) },
15624 + { "collisions", E1000_STAT(stats.colc) },
15625 + { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
15626 + { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
15627 + { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
15628 + { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
15629 + { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
15630 + { "rx_missed_errors", E1000_STAT(stats.mpc) },
15631 + { "tx_aborted_errors", E1000_STAT(stats.ecol) },
15632 + { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
15633 + { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
15634 + { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
15635 + { "tx_window_errors", E1000_STAT(stats.latecol) },
15636 + { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
15637 + { "tx_deferred_ok", E1000_STAT(stats.dc) },
15638 + { "tx_single_coll_ok", E1000_STAT(stats.scc) },
15639 + { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
15640 + { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
15641 + { "tx_restart_queue", E1000_STAT(restart_queue) },
15642 + { "rx_long_length_errors", E1000_STAT(stats.roc) },
15643 + { "rx_short_length_errors", E1000_STAT(stats.ruc) },
15644 + { "rx_align_errors", E1000_STAT(stats.algnerrc) },
15645 + { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
15646 + { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
15647 + { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
15648 + { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
15649 + { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
15650 + { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
15651 + { "rx_long_byte_count", E1000_STAT(stats.gorc) },
15652 + { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
15653 + { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
15654 + { "rx_header_split", E1000_STAT(rx_hdr_split) },
15655 + { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
15656 + { "tx_smbus", E1000_STAT(stats.mgptc) },
15657 + { "rx_smbus", E1000_STAT(stats.mgprc) },
15658 + { "dropped_smbus", E1000_STAT(stats.mgpdc) },
15659 + { "rx_dma_failed", E1000_STAT(rx_dma_failed) },
15660 + { "tx_dma_failed", E1000_STAT(tx_dma_failed) },
15663 +#define E1000_GLOBAL_STATS_LEN ARRAY_SIZE(e1000_gstrings_stats)
15664 +#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN)
15665 +static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
15666 + "Register test (offline)", "Eeprom test (offline)",
15667 + "Interrupt test (offline)", "Loopback test (offline)",
15668 + "Link test (on/offline)"
15670 +#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test)
15672 +static int e1000_get_settings(struct net_device *netdev,
15673 + struct ethtool_cmd *ecmd)
15675 + struct e1000_adapter *adapter = netdev_priv(netdev);
15676 + struct e1000_hw *hw = &adapter->hw;
15679 + if (hw->phy.media_type == e1000_media_type_copper) {
15681 + ecmd->supported = (SUPPORTED_10baseT_Half |
15682 + SUPPORTED_10baseT_Full |
15683 + SUPPORTED_100baseT_Half |
15684 + SUPPORTED_100baseT_Full |
15685 + SUPPORTED_1000baseT_Full |
15686 + SUPPORTED_Autoneg |
15688 + if (hw->phy.type == e1000_phy_ife)
15689 + ecmd->supported &= ~SUPPORTED_1000baseT_Full;
15690 + ecmd->advertising = ADVERTISED_TP;
15692 + if (hw->mac.autoneg == 1) {
15693 + ecmd->advertising |= ADVERTISED_Autoneg;
15694 + /* the e1000 autoneg seems to match ethtool nicely */
15695 + ecmd->advertising |= hw->phy.autoneg_advertised;
15698 + ecmd->port = PORT_TP;
15699 + ecmd->phy_address = hw->phy.addr;
15700 + ecmd->transceiver = XCVR_INTERNAL;
15703 + ecmd->supported = (SUPPORTED_1000baseT_Full |
15704 + SUPPORTED_FIBRE |
15705 + SUPPORTED_Autoneg);
15707 + ecmd->advertising = (ADVERTISED_1000baseT_Full |
15708 + ADVERTISED_FIBRE |
15709 + ADVERTISED_Autoneg);
15711 + ecmd->port = PORT_FIBRE;
15712 + ecmd->transceiver = XCVR_EXTERNAL;
15715 + status = er32(STATUS);
15716 + if (status & E1000_STATUS_LU) {
15717 + if (status & E1000_STATUS_SPEED_1000)
15718 + ecmd->speed = 1000;
15719 + else if (status & E1000_STATUS_SPEED_100)
15720 + ecmd->speed = 100;
15722 + ecmd->speed = 10;
15724 + if (status & E1000_STATUS_FD)
15725 + ecmd->duplex = DUPLEX_FULL;
15727 + ecmd->duplex = DUPLEX_HALF;
15729 + ecmd->speed = -1;
15730 + ecmd->duplex = -1;
15733 + ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
15734 + hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
15738 +static u32 e1000_get_link(struct net_device *netdev)
15740 + struct e1000_adapter *adapter = netdev_priv(netdev);
15742 + return e1000_has_link(adapter);
15745 +static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
15747 + struct e1000_mac_info *mac = &adapter->hw.mac;
15749 + mac->autoneg = 0;
15751 + /* Fiber NICs only allow 1000 gbps Full duplex */
15752 + if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
15753 + spddplx != (SPEED_1000 + DUPLEX_FULL)) {
15754 + e_err("Unsupported Speed/Duplex configuration\n");
15758 + switch (spddplx) {
15759 + case SPEED_10 + DUPLEX_HALF:
15760 + mac->forced_speed_duplex = ADVERTISE_10_HALF;
15762 + case SPEED_10 + DUPLEX_FULL:
15763 + mac->forced_speed_duplex = ADVERTISE_10_FULL;
15765 + case SPEED_100 + DUPLEX_HALF:
15766 + mac->forced_speed_duplex = ADVERTISE_100_HALF;
15768 + case SPEED_100 + DUPLEX_FULL:
15769 + mac->forced_speed_duplex = ADVERTISE_100_FULL;
15771 + case SPEED_1000 + DUPLEX_FULL:
15772 + mac->autoneg = 1;
15773 + adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
15775 + case SPEED_1000 + DUPLEX_HALF: /* not supported */
15777 + e_err("Unsupported Speed/Duplex configuration\n");
15783 +static int e1000_set_settings(struct net_device *netdev,
15784 + struct ethtool_cmd *ecmd)
15786 + struct e1000_adapter *adapter = netdev_priv(netdev);
15787 + struct e1000_hw *hw = &adapter->hw;
15790 + * When SoL/IDER sessions are active, autoneg/speed/duplex
15791 + * cannot be changed
15793 + if (e1000_check_reset_block(hw)) {
15794 + e_err("Cannot change link characteristics when SoL/IDER is "
15799 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
15802 + if (ecmd->autoneg == AUTONEG_ENABLE) {
15803 + hw->mac.autoneg = 1;
15804 + if (hw->phy.media_type == e1000_media_type_fiber)
15805 + hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
15806 + ADVERTISED_FIBRE |
15807 + ADVERTISED_Autoneg;
15809 + hw->phy.autoneg_advertised = ecmd->advertising |
15811 + ADVERTISED_Autoneg;
15812 + ecmd->advertising = hw->phy.autoneg_advertised;
15813 + if (adapter->fc_autoneg) {
15814 + if (hw->mac.type == e1000_pchlan) {
15815 + /* Workaround h/w hang when Tx flow control
15817 + hw->fc.requested_mode = e1000_fc_rx_pause;
15819 + hw->fc.requested_mode = e1000_fc_default;
15823 + if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
15824 + clear_bit(__E1000_RESETTING, &adapter->state);
15829 + /* reset the link */
15831 + if (netif_running(adapter->netdev)) {
15832 + e1000e_down(adapter);
15833 + e1000e_up(adapter);
15835 + e1000e_reset(adapter);
15838 + clear_bit(__E1000_RESETTING, &adapter->state);
15842 +static void e1000_get_pauseparam(struct net_device *netdev,
15843 + struct ethtool_pauseparam *pause)
15845 + struct e1000_adapter *adapter = netdev_priv(netdev);
15846 + struct e1000_hw *hw = &adapter->hw;
15849 + (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
15851 + if (hw->fc.current_mode == e1000_fc_rx_pause) {
15852 + pause->rx_pause = 1;
15853 + } else if (hw->fc.current_mode == e1000_fc_tx_pause) {
15854 + pause->tx_pause = 1;
15855 + } else if (hw->fc.current_mode == e1000_fc_full) {
15856 + pause->rx_pause = 1;
15857 + pause->tx_pause = 1;
15861 +static int e1000_set_pauseparam(struct net_device *netdev,
15862 + struct ethtool_pauseparam *pause)
15864 + struct e1000_adapter *adapter = netdev_priv(netdev);
15865 + struct e1000_hw *hw = &adapter->hw;
15868 + adapter->fc_autoneg = pause->autoneg;
15870 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
15873 + if (adapter->fc_autoneg == AUTONEG_ENABLE) {
15874 + if (hw->mac.type == e1000_pchlan) {
15875 + /* Workaround h/w hang when Tx flow control enabled */
15876 + hw->fc.requested_mode = e1000_fc_rx_pause;
15878 + hw->fc.requested_mode = e1000_fc_default;
15880 + if (netif_running(adapter->netdev)) {
15881 + e1000e_down(adapter);
15882 + e1000e_up(adapter);
15884 + e1000e_reset(adapter);
15887 + if (pause->rx_pause && pause->tx_pause)
15888 + hw->fc.requested_mode = e1000_fc_full;
15889 + else if (pause->rx_pause && !pause->tx_pause)
15890 + hw->fc.requested_mode = e1000_fc_rx_pause;
15891 + else if (!pause->rx_pause && pause->tx_pause)
15892 + hw->fc.requested_mode = e1000_fc_tx_pause;
15893 + else if (!pause->rx_pause && !pause->tx_pause)
15894 + hw->fc.requested_mode = e1000_fc_none;
15896 + hw->fc.current_mode = hw->fc.requested_mode;
15898 + retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
15899 + hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw));
15902 + clear_bit(__E1000_RESETTING, &adapter->state);
15906 +static u32 e1000_get_rx_csum(struct net_device *netdev)
15908 + struct e1000_adapter *adapter = netdev_priv(netdev);
15909 + return adapter->flags & FLAG_RX_CSUM_ENABLED;
15912 +static int e1000_set_rx_csum(struct net_device *netdev, u32 data)
15914 + struct e1000_adapter *adapter = netdev_priv(netdev);
15917 + adapter->flags |= FLAG_RX_CSUM_ENABLED;
15919 + adapter->flags &= ~FLAG_RX_CSUM_ENABLED;
15921 + if (netif_running(netdev))
15922 + e1000e_reinit_locked(adapter);
15924 + e1000e_reset(adapter);
15928 +static u32 e1000_get_tx_csum(struct net_device *netdev)
15930 + return ((netdev->features & NETIF_F_HW_CSUM) != 0);
15933 +static int e1000_set_tx_csum(struct net_device *netdev, u32 data)
15936 + netdev->features |= NETIF_F_HW_CSUM;
15938 + netdev->features &= ~NETIF_F_HW_CSUM;
15943 +#ifdef NETIF_F_TSO
15944 +static int e1000_set_tso(struct net_device *netdev, u32 data)
15946 + struct e1000_adapter *adapter = netdev_priv(netdev);
15948 + struct net_device *v_netdev;
15951 + netdev->features |= NETIF_F_TSO;
15952 +#ifdef NETIF_F_TSO6
15953 + netdev->features |= NETIF_F_TSO6;
15956 + netdev->features &= ~NETIF_F_TSO;
15957 +#ifdef NETIF_F_TSO6
15958 + netdev->features &= ~NETIF_F_TSO6;
15960 +#ifdef NETIF_F_HW_VLAN_TX
15961 + /* disable TSO on all VLANs if they're present */
15962 + if (!adapter->vlgrp)
15964 + for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
15965 + v_netdev = vlan_group_get_device(adapter->vlgrp, i);
15969 + v_netdev->features &= ~NETIF_F_TSO;
15970 +#ifdef NETIF_F_TSO6
15971 + v_netdev->features &= ~NETIF_F_TSO6;
15973 + vlan_group_set_device(adapter->vlgrp, i, v_netdev);
15979 + e_info("TSO is %s\n", data ? "Enabled" : "Disabled");
15980 + adapter->flags |= FLAG_TSO_FORCE;
15985 +static u32 e1000_get_msglevel(struct net_device *netdev)
15987 + struct e1000_adapter *adapter = netdev_priv(netdev);
15988 + return adapter->msg_enable;
15991 +static void e1000_set_msglevel(struct net_device *netdev, u32 data)
15993 + struct e1000_adapter *adapter = netdev_priv(netdev);
15994 + adapter->msg_enable = data;
15997 +static int e1000_get_regs_len(struct net_device *netdev)
15999 +#define E1000_REGS_LEN 32 /* overestimate */
16000 + return E1000_REGS_LEN * sizeof(u32);
16003 +static void e1000_get_regs(struct net_device *netdev,
16004 + struct ethtool_regs *regs, void *p)
16006 + struct e1000_adapter *adapter = netdev_priv(netdev);
16007 + struct e1000_hw *hw = &adapter->hw;
16008 + u32 *regs_buff = p;
16012 + memset(p, 0, E1000_REGS_LEN * sizeof(u32));
16014 + pci_read_config_byte(adapter->pdev, PCI_REVISION_ID, &revision_id);
16016 + regs->version = (1 << 24) | (revision_id << 16) | adapter->pdev->device;
16018 + regs_buff[0] = er32(CTRL);
16019 + regs_buff[1] = er32(STATUS);
16021 + regs_buff[2] = er32(RCTL);
16022 + regs_buff[3] = er32(RDLEN(0));
16023 + regs_buff[4] = er32(RDH(0));
16024 + regs_buff[5] = er32(RDT(0));
16025 + regs_buff[6] = er32(RDTR);
16027 + regs_buff[7] = er32(TCTL);
16028 + regs_buff[8] = er32(TDLEN(0));
16029 + regs_buff[9] = er32(TDH(0));
16030 + regs_buff[10] = er32(TDT(0));
16031 + regs_buff[11] = er32(TIDV);
16033 + regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
16035 + /* ethtool doesn't use anything past this point, so all this
16036 + * code is likely legacy junk for apps that may or may not
16038 + if (hw->phy.type == e1000_phy_m88) {
16039 + e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
16040 + regs_buff[13] = (u32)phy_data; /* cable length */
16041 + regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
16042 + regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
16043 + regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
16044 + e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
16045 + regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
16046 + regs_buff[18] = regs_buff[13]; /* cable polarity */
16047 + regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
16048 + regs_buff[20] = regs_buff[17]; /* polarity correction */
16049 + /* phy receive errors */
16050 + regs_buff[22] = adapter->phy_stats.receive_errors;
16051 + regs_buff[23] = regs_buff[13]; /* mdix mode */
16053 + regs_buff[21] = 0; /* was idle_errors */
16054 + e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
16055 + regs_buff[24] = (u32)phy_data; /* phy local receiver status */
16056 + regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
16059 +static int e1000_get_eeprom_len(struct net_device *netdev)
16061 + struct e1000_adapter *adapter = netdev_priv(netdev);
16062 + return adapter->hw.nvm.word_size * 2;
16065 +static int e1000_get_eeprom(struct net_device *netdev,
16066 + struct ethtool_eeprom *eeprom, u8 *bytes)
16068 + struct e1000_adapter *adapter = netdev_priv(netdev);
16069 + struct e1000_hw *hw = &adapter->hw;
16070 + u16 *eeprom_buff;
16076 + if (eeprom->len == 0)
16079 + eeprom->magic = adapter->pdev->vendor | (adapter->pdev->device << 16);
16081 + first_word = eeprom->offset >> 1;
16082 + last_word = (eeprom->offset + eeprom->len - 1) >> 1;
16084 + eeprom_buff = kmalloc(sizeof(u16) *
16085 + (last_word - first_word + 1), GFP_KERNEL);
16086 + if (!eeprom_buff)
16089 + if (hw->nvm.type == e1000_nvm_eeprom_spi) {
16090 + ret_val = e1000_read_nvm(hw, first_word,
16091 + last_word - first_word + 1,
16094 + for (i = 0; i < last_word - first_word + 1; i++) {
16095 + ret_val = e1000_read_nvm(hw, first_word + i, 1,
16096 + &eeprom_buff[i]);
16103 + /* a read error occurred, throw away the result */
16104 + memset(eeprom_buff, 0xff, sizeof(eeprom_buff));
16106 + /* Device's eeprom is always little-endian, word addressable */
16107 + for (i = 0; i < last_word - first_word + 1; i++)
16108 + le16_to_cpus(&eeprom_buff[i]);
16111 + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
16112 + kfree(eeprom_buff);
16117 +static int e1000_set_eeprom(struct net_device *netdev,
16118 + struct ethtool_eeprom *eeprom, u8 *bytes)
16120 + struct e1000_adapter *adapter = netdev_priv(netdev);
16121 + struct e1000_hw *hw = &adapter->hw;
16122 + u16 *eeprom_buff;
16130 + if (eeprom->len == 0)
16131 + return -EOPNOTSUPP;
16133 + if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 16)))
16136 + max_len = hw->nvm.word_size * 2;
16138 + first_word = eeprom->offset >> 1;
16139 + last_word = (eeprom->offset + eeprom->len - 1) >> 1;
16140 + eeprom_buff = kmalloc(max_len, GFP_KERNEL);
16141 + if (!eeprom_buff)
16144 + ptr = (void *)eeprom_buff;
16146 + if (eeprom->offset & 1) {
16147 + /* need read/modify/write of first changed EEPROM word */
16148 + /* only the second byte of the word is being modified */
16149 + ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]);
16152 + if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0))
16153 + /* need read/modify/write of last changed EEPROM word */
16154 + /* only the first byte of the word is being modified */
16155 + ret_val = e1000_read_nvm(hw, last_word, 1,
16156 + &eeprom_buff[last_word - first_word]);
16161 + /* Device's eeprom is always little-endian, word addressable */
16162 + for (i = 0; i < last_word - first_word + 1; i++)
16163 + le16_to_cpus(&eeprom_buff[i]);
16165 + memcpy(ptr, bytes, eeprom->len);
16167 + for (i = 0; i < last_word - first_word + 1; i++)
16168 + eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
16170 + ret_val = e1000_write_nvm(hw, first_word,
16171 + last_word - first_word + 1, eeprom_buff);
16177 + * Update the checksum over the first part of the EEPROM if needed
16178 + * and flush shadow RAM for applicable controllers
16180 + if ((first_word <= NVM_CHECKSUM_REG) ||
16181 + (hw->mac.type == e1000_82583) ||
16182 + (hw->mac.type == e1000_82574) ||
16183 + (hw->mac.type == e1000_82573))
16184 + ret_val = e1000e_update_nvm_checksum(hw);
16187 + kfree(eeprom_buff);
16191 +static void e1000_get_drvinfo(struct net_device *netdev,
16192 + struct ethtool_drvinfo *drvinfo)
16194 + struct e1000_adapter *adapter = netdev_priv(netdev);
16195 + char firmware_version[32];
16197 + strncpy(drvinfo->driver, e1000e_driver_name, 32);
16198 + strncpy(drvinfo->version, e1000e_driver_version, 32);
16201 + * EEPROM image version # is reported as firmware version # for
16202 + * PCI-E controllers
16204 + sprintf(firmware_version, "%d.%d-%d",
16205 + (adapter->eeprom_vers & 0xF000) >> 12,
16206 + (adapter->eeprom_vers & 0x0FF0) >> 4,
16207 + (adapter->eeprom_vers & 0x000F));
16209 + strncpy(drvinfo->fw_version, firmware_version, 32);
16210 + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
16211 + drvinfo->regdump_len = e1000_get_regs_len(netdev);
16212 + drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
16215 +static void e1000_get_ringparam(struct net_device *netdev,
16216 + struct ethtool_ringparam *ring)
16218 + struct e1000_adapter *adapter = netdev_priv(netdev);
16219 + struct e1000_ring *tx_ring = adapter->tx_ring;
16220 + struct e1000_ring *rx_ring = adapter->rx_ring;
16222 + ring->rx_max_pending = E1000_MAX_RXD;
16223 + ring->tx_max_pending = E1000_MAX_TXD;
16224 + ring->rx_mini_max_pending = 0;
16225 + ring->rx_jumbo_max_pending = 0;
16226 + ring->rx_pending = rx_ring->count;
16227 + ring->tx_pending = tx_ring->count;
16228 + ring->rx_mini_pending = 0;
16229 + ring->rx_jumbo_pending = 0;
16232 +static int e1000_set_ringparam(struct net_device *netdev,
16233 + struct ethtool_ringparam *ring)
16235 + struct e1000_adapter *adapter = netdev_priv(netdev);
16236 + struct e1000_ring *tx_ring, *tx_old;
16237 + struct e1000_ring *rx_ring, *rx_old;
16240 + if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
16243 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
16246 + if (netif_running(adapter->netdev))
16247 + e1000e_down(adapter);
16249 + tx_old = adapter->tx_ring;
16250 + rx_old = adapter->rx_ring;
16253 + tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
16255 + goto err_alloc_tx;
16257 + * use a memcpy to save any previously configured
16258 + * items like napi structs from having to be
16261 + memcpy(tx_ring, tx_old, sizeof(struct e1000_ring));
16263 + rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
16265 + goto err_alloc_rx;
16266 + memcpy(rx_ring, rx_old, sizeof(struct e1000_ring));
16268 + adapter->tx_ring = tx_ring;
16269 + adapter->rx_ring = rx_ring;
16271 + rx_ring->count = max(ring->rx_pending, (u32)E1000_MIN_RXD);
16272 + rx_ring->count = min(rx_ring->count, (u32)(E1000_MAX_RXD));
16273 + rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
16275 + tx_ring->count = max(ring->tx_pending, (u32)E1000_MIN_TXD);
16276 + tx_ring->count = min(tx_ring->count, (u32)(E1000_MAX_TXD));
16277 + tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
16279 + if (netif_running(adapter->netdev)) {
16280 + /* Try to get new resources before deleting old */
16281 + err = e1000e_setup_rx_resources(adapter);
16283 + goto err_setup_rx;
16284 + err = e1000e_setup_tx_resources(adapter);
16286 + goto err_setup_tx;
16289 + * restore the old in order to free it,
16290 + * then add in the new
16292 + adapter->rx_ring = rx_old;
16293 + adapter->tx_ring = tx_old;
16294 + e1000e_free_rx_resources(adapter);
16295 + e1000e_free_tx_resources(adapter);
16298 + adapter->rx_ring = rx_ring;
16299 + adapter->tx_ring = tx_ring;
16300 + err = e1000e_up(adapter);
16305 + clear_bit(__E1000_RESETTING, &adapter->state);
16308 + e1000e_free_rx_resources(adapter);
16310 + adapter->rx_ring = rx_old;
16311 + adapter->tx_ring = tx_old;
16316 + e1000e_up(adapter);
16318 + clear_bit(__E1000_RESETTING, &adapter->state);
16322 +static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
16323 + int reg, int offset, u32 mask, u32 write)
16326 + static const u32 test[] =
16327 + {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
16328 + for (pat = 0; pat < ARRAY_SIZE(test); pat++) {
16329 + E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset,
16330 + (test[pat] & write));
16331 + val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset);
16332 + if (val != (test[pat] & write & mask)) {
16333 + e_err("Register 0x%05X pattern test failed: got 0x%08X "
16334 + "expected 0x%08X\n", reg + offset, val,
16335 + (test[pat] & write & mask));
16343 +static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
16344 + int reg, u32 mask, u32 write)
16347 + __ew32(&adapter->hw, reg, write & mask);
16348 + val = __er32(&adapter->hw, reg);
16349 + if ((write & mask) != (val & mask)) {
16350 + e_err("Register 0x%05X set/check test failed: got 0x%08X "
16351 + "expected 0x%08X\n", reg, (val & mask), (write & mask));
16357 +#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write) \
16359 + if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \
16362 +#define REG_PATTERN_TEST(reg, mask, write) \
16363 + REG_PATTERN_TEST_ARRAY(reg, 0, mask, write)
16365 +#define REG_SET_AND_CHECK(reg, mask, write) \
16367 + if (reg_set_and_check(adapter, data, reg, mask, write)) \
16371 +static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
16373 + struct e1000_hw *hw = &adapter->hw;
16374 + struct e1000_mac_info *mac = &adapter->hw.mac;
16383 + * The status register is Read Only, so a write should fail.
16384 + * Some bits that get toggled are ignored.
16386 + switch (mac->type) {
16387 + /* there are several bits on newer hardware that are r/w */
16388 + case e1000_82571:
16389 + case e1000_82572:
16390 + case e1000_80003es2lan:
16391 + toggle = 0x7FFFF3FF;
16394 + toggle = 0x7FFFF033;
16398 + before = er32(STATUS);
16399 + value = (er32(STATUS) & toggle);
16400 + ew32(STATUS, toggle);
16401 + after = er32(STATUS) & toggle;
16402 + if (value != after) {
16403 + e_err("failed STATUS register test got: 0x%08X expected: "
16404 + "0x%08X\n", after, value);
16408 + /* restore previous status */
16409 + ew32(STATUS, before);
16411 + if (!(adapter->flags & FLAG_IS_ICH)) {
16412 + REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
16413 + REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
16414 + REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
16415 + REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
16418 + REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
16419 + REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
16420 + REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF);
16421 + REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF);
16422 + REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF);
16423 + REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
16424 + REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
16425 + REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
16426 + REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
16427 + REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF);
16429 + REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
16431 + before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);
16432 + REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
16433 + REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
16435 + REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
16436 + REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
16437 + if (!(adapter->flags & FLAG_IS_ICH))
16438 + REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
16439 + REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
16440 + REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
16441 + mask = 0x8003FFFF;
16442 + switch (mac->type) {
16443 + case e1000_ich10lan:
16444 + case e1000_pchlan:
16445 + mask |= (1 << 18);
16450 + for (i = 0; i < mac->rar_entry_count; i++)
16451 + REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
16452 + mask, 0xFFFFFFFF);
16454 + for (i = 0; i < mac->mta_reg_count; i++)
16455 + REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
16461 +static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
16464 + u16 checksum = 0;
16468 + /* Read and add up the contents of the EEPROM */
16469 + for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
16470 + if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) {
16474 + checksum += temp;
16477 + /* If Checksum is not Correct return error else test passed */
16478 + if ((checksum != (u16) NVM_SUM) && !(*data))
16484 +static irqreturn_t e1000_test_intr(int irq, void *data)
16486 + struct net_device *netdev = (struct net_device *) data;
16487 + struct e1000_adapter *adapter = netdev_priv(netdev);
16488 + struct e1000_hw *hw = &adapter->hw;
16490 + adapter->test_icr |= er32(ICR);
16492 + return IRQ_HANDLED;
16495 +static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
16497 + struct net_device *netdev = adapter->netdev;
16498 + struct e1000_hw *hw = &adapter->hw;
16500 + u32 shared_int = 1;
16501 + u32 irq = adapter->pdev->irq;
16503 +#ifdef CONFIG_E1000E_MSIX
16505 + int int_mode = E1000E_INT_MODE_LEGACY;
16510 +#ifdef CONFIG_E1000E_MSIX
16511 + /* NOTE: we don't test MSI/MSI-X interrupts here, yet */
16512 + if (adapter->int_mode == E1000E_INT_MODE_MSIX) {
16513 + int_mode = adapter->int_mode;
16514 + e1000e_reset_interrupt_capability(adapter);
16515 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
16516 + e1000e_set_interrupt_capability(adapter);
16519 + /* NOTE: we don't test MSI interrupts here, yet */
16521 + /* Hook up test interrupt handler just for this test */
16522 + if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
16525 + } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
16526 + netdev->name, netdev)) {
16528 +#ifdef CONFIG_E1000E_MSIX
16535 + e_info("testing %s interrupt\n", (shared_int ? "shared" : "unshared"));
16537 + /* Disable all the interrupts */
16538 + ew32(IMC, 0xFFFFFFFF);
16541 + /* Test each interrupt */
16542 + for (i = 0; i < 10; i++) {
16543 + /* Interrupt to test */
16546 + if (adapter->flags & FLAG_IS_ICH) {
16548 + case E1000_ICR_RXSEQ:
16551 + if (adapter->hw.mac.type == e1000_ich8lan ||
16552 + adapter->hw.mac.type == e1000_ich9lan)
16560 + if (!shared_int) {
16562 + * Disable the interrupt to be reported in
16563 + * the cause register and then force the same
16564 + * interrupt and see if one gets posted. If
16565 + * an interrupt was posted to the bus, the
16568 + adapter->test_icr = 0;
16573 + if (adapter->test_icr & mask) {
16580 + * Enable the interrupt to be reported in
16581 + * the cause register and then force the same
16582 + * interrupt and see if one gets posted. If
16583 + * an interrupt was not posted to the bus, the
16586 + adapter->test_icr = 0;
16591 + if (!(adapter->test_icr & mask)) {
16596 + if (!shared_int) {
16598 + * Disable the other interrupts to be reported in
16599 + * the cause register and then force the other
16600 + * interrupts and see if any get posted. If
16601 + * an interrupt was posted to the bus, the
16604 + adapter->test_icr = 0;
16605 + ew32(IMC, ~mask & 0x00007FFF);
16606 + ew32(ICS, ~mask & 0x00007FFF);
16609 + if (adapter->test_icr) {
16616 + /* Disable all the interrupts */
16617 + ew32(IMC, 0xFFFFFFFF);
16620 + /* Unhook test interrupt handler */
16621 + free_irq(irq, netdev);
16623 +#ifdef CONFIG_E1000E_MSIX
16625 + if (int_mode == E1000E_INT_MODE_MSIX) {
16626 + e1000e_reset_interrupt_capability(adapter);
16627 + adapter->int_mode = int_mode;
16628 + e1000e_set_interrupt_capability(adapter);
16637 +static void e1000_free_desc_rings(struct e1000_adapter *adapter)
16639 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
16640 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
16641 + struct pci_dev *pdev = adapter->pdev;
16644 + if (tx_ring->desc && tx_ring->buffer_info) {
16645 + for (i = 0; i < tx_ring->count; i++) {
16646 + if (tx_ring->buffer_info[i].dma)
16647 + pci_unmap_single(pdev,
16648 + tx_ring->buffer_info[i].dma,
16649 + tx_ring->buffer_info[i].length,
16650 + PCI_DMA_TODEVICE);
16651 + if (tx_ring->buffer_info[i].skb)
16652 + dev_kfree_skb(tx_ring->buffer_info[i].skb);
16656 + if (rx_ring->desc && rx_ring->buffer_info) {
16657 + for (i = 0; i < rx_ring->count; i++) {
16658 + if (rx_ring->buffer_info[i].dma)
16659 + pci_unmap_single(pdev,
16660 + rx_ring->buffer_info[i].dma,
16661 + 2048, PCI_DMA_FROMDEVICE);
16662 + if (rx_ring->buffer_info[i].skb)
16663 + dev_kfree_skb(rx_ring->buffer_info[i].skb);
16667 + if (tx_ring->desc) {
16668 + dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
16670 + tx_ring->desc = NULL;
16672 + if (rx_ring->desc) {
16673 + dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
16675 + rx_ring->desc = NULL;
16678 + kfree(tx_ring->buffer_info);
16679 + tx_ring->buffer_info = NULL;
16680 + kfree(rx_ring->buffer_info);
16681 + rx_ring->buffer_info = NULL;
16684 +static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
16686 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
16687 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
16688 + struct pci_dev *pdev = adapter->pdev;
16689 + struct e1000_hw *hw = &adapter->hw;
16694 + /* Setup Tx descriptor ring and Tx buffers */
16696 + if (!tx_ring->count)
16697 + tx_ring->count = E1000_DEFAULT_TXD;
16699 + tx_ring->buffer_info = kcalloc(tx_ring->count,
16700 + sizeof(struct e1000_buffer),
16702 + if (!(tx_ring->buffer_info)) {
16707 + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
16708 + tx_ring->size = ALIGN(tx_ring->size, 4096);
16709 + tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
16710 + &tx_ring->dma, GFP_KERNEL);
16711 + if (!tx_ring->desc) {
16715 + tx_ring->next_to_use = 0;
16716 + tx_ring->next_to_clean = 0;
16718 + ew32(TDBAL(0), ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
16719 + ew32(TDBAH(0), ((u64) tx_ring->dma >> 32));
16720 + ew32(TDLEN(0), tx_ring->count * sizeof(struct e1000_tx_desc));
16723 + ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | E1000_TCTL_MULR |
16724 + E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
16725 + E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
16727 + for (i = 0; i < tx_ring->count; i++) {
16728 + struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
16729 + struct sk_buff *skb;
16730 + unsigned int skb_size = 1024;
16732 + skb = alloc_skb(skb_size, GFP_KERNEL);
16737 + skb_put(skb, skb_size);
16738 + tx_ring->buffer_info[i].skb = skb;
16739 + tx_ring->buffer_info[i].length = skb->len;
16740 + tx_ring->buffer_info[i].dma =
16741 + pci_map_single(pdev, skb->data, skb->len,
16742 + PCI_DMA_TODEVICE);
16743 + if (pci_dma_mapping_error(pdev, tx_ring->buffer_info[i].dma)) {
16747 + tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
16748 + tx_desc->lower.data = cpu_to_le32(skb->len);
16749 + tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
16750 + E1000_TXD_CMD_IFCS |
16751 + E1000_TXD_CMD_RS);
16752 + tx_desc->upper.data = 0;
16755 + /* Setup Rx descriptor ring and Rx buffers */
16757 + if (!rx_ring->count)
16758 + rx_ring->count = E1000_DEFAULT_RXD;
16760 + rx_ring->buffer_info = kcalloc(rx_ring->count,
16761 + sizeof(struct e1000_buffer),
16763 + if (!(rx_ring->buffer_info)) {
16768 + rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
16769 + rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
16770 + &rx_ring->dma, GFP_KERNEL);
16771 + if (!rx_ring->desc) {
16775 + rx_ring->next_to_use = 0;
16776 + rx_ring->next_to_clean = 0;
16778 + rctl = er32(RCTL);
16779 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
16780 + ew32(RDBAL(0), ((u64) rx_ring->dma & 0xFFFFFFFF));
16781 + ew32(RDBAH(0), ((u64) rx_ring->dma >> 32));
16782 + ew32(RDLEN(0), rx_ring->size);
16785 + rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
16786 + E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE |
16787 + E1000_RCTL_SBP | E1000_RCTL_SECRC |
16788 + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
16789 + (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
16790 + ew32(RCTL, rctl);
16792 + for (i = 0; i < rx_ring->count; i++) {
16793 + struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
16794 + struct sk_buff *skb;
16796 + skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL);
16801 + skb_reserve(skb, NET_IP_ALIGN);
16802 + rx_ring->buffer_info[i].skb = skb;
16803 + rx_ring->buffer_info[i].dma =
16804 + pci_map_single(pdev, skb->data, 2048,
16805 + PCI_DMA_FROMDEVICE);
16806 + if (pci_dma_mapping_error(pdev, rx_ring->buffer_info[i].dma)) {
16810 + rx_desc->buffer_addr =
16811 + cpu_to_le64(rx_ring->buffer_info[i].dma);
16812 + memset(skb->data, 0x00, skb->len);
16818 + e1000_free_desc_rings(adapter);
16822 +static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
16824 + /* Write out to PHY registers 29 and 30 to disable the Receiver. */
16825 + e1e_wphy(&adapter->hw, 29, 0x001F);
16826 + e1e_wphy(&adapter->hw, 30, 0x8FFC);
16827 + e1e_wphy(&adapter->hw, 29, 0x001A);
16828 + e1e_wphy(&adapter->hw, 30, 0x8FF0);
16831 +static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
16833 + struct e1000_hw *hw = &adapter->hw;
16834 + u32 ctrl_reg = 0;
16835 + u32 stat_reg = 0;
16838 + hw->mac.autoneg = 0;
16840 + if (hw->phy.type == e1000_phy_m88) {
16841 + /* Auto-MDI/MDIX Off */
16842 + e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
16843 + /* reset to update Auto-MDI/MDIX */
16844 + e1e_wphy(hw, PHY_CONTROL, 0x9140);
16845 + /* autoneg off */
16846 + e1e_wphy(hw, PHY_CONTROL, 0x8140);
16847 + } else if (hw->phy.type == e1000_phy_gg82563)
16848 + e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
16850 + ctrl_reg = er32(CTRL);
16852 + switch (hw->phy.type) {
16853 + case e1000_phy_ife:
16854 + /* force 100, set loopback */
16855 + e1e_wphy(hw, PHY_CONTROL, 0x6100);
16857 + /* Now set up the MAC to the same speed/duplex as the PHY. */
16858 + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
16859 + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
16860 + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
16861 + E1000_CTRL_SPD_100 |/* Force Speed to 100 */
16862 + E1000_CTRL_FD); /* Force Duplex to FULL */
16864 + case e1000_phy_bm:
16865 + /* Set Default MAC Interface speed to 1GB */
16866 + e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);
16867 + phy_reg &= ~0x0007;
16868 + phy_reg |= 0x006;
16869 + e1e_wphy(hw, PHY_REG(2, 21), phy_reg);
16870 + /* Assert SW reset for above settings to take effect */
16871 + e1000e_commit_phy(hw);
16873 + /* Force Full Duplex */
16874 + e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
16875 + e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);
16876 + /* Set Link Up (in force link) */
16877 + e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);
16878 + e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);
16880 + e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
16881 + e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);
16882 + /* Set Early Link Enable */
16883 + e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
16884 + e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400);
16885 + /* fall through */
16887 + /* force 1000, set loopback */
16888 + e1e_wphy(hw, PHY_CONTROL, 0x4140);
16891 + /* Now set up the MAC to the same speed/duplex as the PHY. */
16892 + ctrl_reg = er32(CTRL);
16893 + ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
16894 + ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
16895 + E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
16896 + E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
16897 + E1000_CTRL_FD); /* Force Duplex to FULL */
16899 + if (adapter->flags & FLAG_IS_ICH)
16900 + ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */
16903 + if (hw->phy.media_type == e1000_media_type_copper &&
16904 + hw->phy.type == e1000_phy_m88) {
16905 + ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
16908 + * Set the ILOS bit on the fiber Nic if half duplex link is
16911 + stat_reg = er32(STATUS);
16912 + if ((stat_reg & E1000_STATUS_FD) == 0)
16913 + ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
16916 + ew32(CTRL, ctrl_reg);
16919 + * Disable the receiver on the PHY so when a cable is plugged in, the
16920 + * PHY does not begin to autoneg when a cable is reconnected to the NIC.
16922 + if (hw->phy.type == e1000_phy_m88)
16923 + e1000_phy_disable_receiver(adapter);
16930 +static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
16932 + struct e1000_hw *hw = &adapter->hw;
16933 + u32 ctrl = er32(CTRL);
16936 + /* special requirements for 82571/82572 fiber adapters */
16939 + * jump through hoops to make sure link is up because serdes
16940 + * link is hardwired up
16942 + ctrl |= E1000_CTRL_SLU;
16943 + ew32(CTRL, ctrl);
16945 + /* disable autoneg */
16946 + ctrl = er32(TXCW);
16947 + ctrl &= ~(1 << 31);
16948 + ew32(TXCW, ctrl);
16950 + link = (er32(STATUS) & E1000_STATUS_LU);
16953 + /* set invert loss of signal */
16954 + ctrl = er32(CTRL);
16955 + ctrl |= E1000_CTRL_ILOS;
16956 + ew32(CTRL, ctrl);
16960 + * special write to serdes control register to enable SerDes analog
16963 +#define E1000_SERDES_LB_ON 0x410
16964 + ew32(SCTL, E1000_SERDES_LB_ON);
16970 +/* only call this for fiber/serdes connections to es2lan */
16971 +static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
16973 + struct e1000_hw *hw = &adapter->hw;
16974 + u32 ctrlext = er32(CTRL_EXT);
16975 + u32 ctrl = er32(CTRL);
16978 + * save CTRL_EXT to restore later, reuse an empty variable (unused
16979 + * on mac_type 80003es2lan)
16981 + adapter->tx_fifo_head = ctrlext;
16983 + /* clear the serdes mode bits, putting the device into mac loopback */
16984 + ctrlext &= ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
16985 + ew32(CTRL_EXT, ctrlext);
16987 + /* force speed to 1000/FD, link up */
16988 + ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
16989 + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
16990 + E1000_CTRL_SPD_1000 | E1000_CTRL_FD);
16991 + ew32(CTRL, ctrl);
16993 + /* set mac loopback */
16994 + ctrl = er32(RCTL);
16995 + ctrl |= E1000_RCTL_LBM_MAC;
16996 + ew32(RCTL, ctrl);
16998 + /* set testing mode parameters (no need to reset later) */
16999 +#define KMRNCTRLSTA_OPMODE (0x1F << 16)
17000 +#define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582
17001 + ew32(KMRNCTRLSTA,
17002 + (KMRNCTRLSTA_OPMODE | KMRNCTRLSTA_OPMODE_1GB_FD_GMII));
17007 +static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
17009 + struct e1000_hw *hw = &adapter->hw;
17012 + if (hw->phy.media_type == e1000_media_type_fiber ||
17013 + hw->phy.media_type == e1000_media_type_internal_serdes) {
17014 + switch (hw->mac.type) {
17015 + case e1000_80003es2lan:
17016 + return e1000_set_es2lan_mac_loopback(adapter);
17018 + case e1000_82571:
17019 + case e1000_82572:
17020 + return e1000_set_82571_fiber_loopback(adapter);
17023 + rctl = er32(RCTL);
17024 + rctl |= E1000_RCTL_LBM_TCVR;
17025 + ew32(RCTL, rctl);
17028 + } else if (hw->phy.media_type == e1000_media_type_copper) {
17029 + return e1000_integrated_phy_loopback(adapter);
17035 +static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
17037 + struct e1000_hw *hw = &adapter->hw;
17041 + rctl = er32(RCTL);
17042 + rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
17043 + ew32(RCTL, rctl);
17045 + switch (hw->mac.type) {
17046 + case e1000_80003es2lan:
17047 + if (hw->phy.media_type == e1000_media_type_fiber ||
17048 + hw->phy.media_type == e1000_media_type_internal_serdes) {
17049 + /* restore CTRL_EXT, stealing space from tx_fifo_head */
17050 + ew32(CTRL_EXT, adapter->tx_fifo_head);
17051 + adapter->tx_fifo_head = 0;
17053 + /* fall through */
17054 + case e1000_82571:
17055 + case e1000_82572:
17056 + if (hw->phy.media_type == e1000_media_type_fiber ||
17057 + hw->phy.media_type == e1000_media_type_internal_serdes) {
17058 +#define E1000_SERDES_LB_OFF 0x400
17059 + ew32(SCTL, E1000_SERDES_LB_OFF);
17063 + /* Fall Through */
17065 + hw->mac.autoneg = 1;
17066 + if (hw->phy.type == e1000_phy_gg82563)
17067 + e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180);
17068 + e1e_rphy(hw, PHY_CONTROL, &phy_reg);
17069 + if (phy_reg & MII_CR_LOOPBACK) {
17070 + phy_reg &= ~MII_CR_LOOPBACK;
17071 + e1e_wphy(hw, PHY_CONTROL, phy_reg);
17072 + e1000e_commit_phy(hw);
17078 +static void e1000_create_lbtest_frame(struct sk_buff *skb,
17079 + unsigned int frame_size)
17081 + memset(skb->data, 0xFF, frame_size);
17082 + frame_size &= ~1;
17083 + memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
17084 + memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
17085 + memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
17088 +static int e1000_check_lbtest_frame(struct sk_buff *skb,
17089 + unsigned int frame_size)
17091 + frame_size &= ~1;
17092 + if (*(skb->data + 3) == 0xFF)
17093 + if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
17094 + (*(skb->data + frame_size / 2 + 12) == 0xAF))
17099 +static int e1000_run_loopback_test(struct e1000_adapter *adapter)
17101 + struct e1000_ring *tx_ring = &adapter->test_tx_ring;
17102 + struct e1000_ring *rx_ring = &adapter->test_rx_ring;
17103 + struct pci_dev *pdev = adapter->pdev;
17104 + struct e1000_hw *hw = &adapter->hw;
17109 + unsigned long time;
17111 + ew32(RDT(0), rx_ring->count - 1);
17114 + * Calculate the loop count based on the largest descriptor ring
17115 + * The idea is to wrap the largest ring a number of times using 64
17116 + * send/receive pairs during each loop
17119 + if (rx_ring->count <= tx_ring->count)
17120 + lc = ((tx_ring->count / 64) * 2) + 1;
17122 + lc = ((rx_ring->count / 64) * 2) + 1;
17126 + for (j = 0; j <= lc; j++) { /* loop count loop */
17127 + for (i = 0; i < 64; i++) { /* send the packets */
17128 + e1000_create_lbtest_frame(tx_ring->buffer_info[k].skb,
17130 + pci_dma_sync_single_for_device(pdev,
17131 + tx_ring->buffer_info[k].dma,
17132 + tx_ring->buffer_info[k].length,
17133 + PCI_DMA_TODEVICE);
17135 + if (k == tx_ring->count)
17140 + time = jiffies; /* set the start time for the receive */
17142 + do { /* receive the sent packets */
17143 + pci_dma_sync_single_for_cpu(pdev,
17144 + rx_ring->buffer_info[l].dma, 2048,
17145 + PCI_DMA_FROMDEVICE);
17147 + ret_val = e1000_check_lbtest_frame(
17148 + rx_ring->buffer_info[l].skb, 1024);
17152 + if (l == rx_ring->count)
17155 + * time + 20 msecs (200 msecs on 2.4) is more than
17156 + * enough time to complete the receives, if it's
17157 + * exceeded, break and error off
17159 + } while ((good_cnt < 64) && !time_after(jiffies, time + 20));
17160 + if (good_cnt != 64) {
17161 + ret_val = 13; /* ret_val is the same as mis-compare */
17164 + if (jiffies >= (time + 20)) {
17165 + ret_val = 14; /* error code for time out error */
17168 + } /* end loop count loop */
17172 +static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
17175 + * PHY loopback cannot be performed if SoL/IDER
17176 + * sessions are active
17178 + if (e1000_check_reset_block(&adapter->hw)) {
17179 + e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
17184 + *data = e1000_setup_desc_rings(adapter);
17188 + *data = e1000_setup_loopback_test(adapter);
17190 + goto err_loopback;
17192 + *data = e1000_run_loopback_test(adapter);
17193 + e1000_loopback_cleanup(adapter);
17196 + e1000_free_desc_rings(adapter);
17201 +static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
17203 + struct e1000_hw *hw = &adapter->hw;
17206 + if (hw->phy.media_type == e1000_media_type_internal_serdes) {
17208 + hw->mac.serdes_has_link = 0;
17211 + * On some blade server designs, link establishment
17212 + * could take as long as 2-3 minutes
17215 + hw->mac.ops.check_for_link(hw);
17216 + if (hw->mac.serdes_has_link)
17219 + } while (i++ < 3750);
17223 + hw->mac.ops.check_for_link(hw);
17224 + if (hw->mac.autoneg)
17227 + if (!(er32(STATUS) &
17228 + E1000_STATUS_LU))
17234 +static int e1000_get_self_test_count(struct net_device *netdev)
17236 + return E1000_TEST_LEN;
17239 +static int e1000_get_stats_count(struct net_device *netdev)
17241 + return E1000_STATS_LEN;
17244 +static void e1000_diag_test(struct net_device *netdev,
17245 + struct ethtool_test *eth_test, u64 *data)
17247 + struct e1000_adapter *adapter = netdev_priv(netdev);
17248 + u16 autoneg_advertised;
17249 + u8 forced_speed_duplex;
17251 + bool if_running = netif_running(netdev);
17253 + set_bit(__E1000_TESTING, &adapter->state);
17254 + if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
17255 + /* Offline tests */
17257 + /* save speed, duplex, autoneg settings */
17258 + autoneg_advertised = adapter->hw.phy.autoneg_advertised;
17259 + forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
17260 + autoneg = adapter->hw.mac.autoneg;
17262 + e_info("offline testing starting\n");
17265 + * Link test performed before hardware reset so autoneg doesn't
17266 + * interfere with test result
17268 + if (e1000_link_test(adapter, &data[4]))
17269 + eth_test->flags |= ETH_TEST_FL_FAILED;
17272 + /* indicate we're in test mode */
17273 + dev_close(netdev);
17275 + e1000e_reset(adapter);
17277 + if (e1000_reg_test(adapter, &data[0]))
17278 + eth_test->flags |= ETH_TEST_FL_FAILED;
17280 + e1000e_reset(adapter);
17281 + if (e1000_eeprom_test(adapter, &data[1]))
17282 + eth_test->flags |= ETH_TEST_FL_FAILED;
17284 + e1000e_reset(adapter);
17285 + if (e1000_intr_test(adapter, &data[2]))
17286 + eth_test->flags |= ETH_TEST_FL_FAILED;
17288 + e1000e_reset(adapter);
17289 + /* make sure the phy is powered up */
17290 + e1000e_power_up_phy(adapter);
17291 + if (e1000_loopback_test(adapter, &data[3]))
17292 + eth_test->flags |= ETH_TEST_FL_FAILED;
17294 + /* restore speed, duplex, autoneg settings */
17295 + adapter->hw.phy.autoneg_advertised = autoneg_advertised;
17296 + adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
17297 + adapter->hw.mac.autoneg = autoneg;
17299 + /* force this routine to wait until autoneg complete/timeout */
17300 + adapter->hw.phy.autoneg_wait_to_complete = 1;
17301 + e1000e_reset(adapter);
17302 + adapter->hw.phy.autoneg_wait_to_complete = 0;
17304 + clear_bit(__E1000_TESTING, &adapter->state);
17306 + dev_open(netdev);
17308 + e_info("online testing starting\n");
17309 + /* Online tests */
17310 + if (e1000_link_test(adapter, &data[4]))
17311 + eth_test->flags |= ETH_TEST_FL_FAILED;
17313 + /* Online tests aren't run; pass by default */
17319 + clear_bit(__E1000_TESTING, &adapter->state);
17321 + msleep_interruptible(4 * 1000);
17324 +static void e1000_get_wol(struct net_device *netdev,
17325 + struct ethtool_wolinfo *wol)
17327 + struct e1000_adapter *adapter = netdev_priv(netdev);
17329 + wol->supported = 0;
17330 + wol->wolopts = 0;
17332 + if (!(adapter->flags & FLAG_HAS_WOL) ||
17333 + !device_can_wakeup(&adapter->pdev->dev))
17336 + wol->supported = WAKE_UCAST | WAKE_MCAST |
17337 + WAKE_BCAST | WAKE_MAGIC |
17338 + WAKE_PHY | WAKE_ARP;
17340 + /* apply any specific unsupported masks here */
17341 + if (adapter->flags & FLAG_NO_WAKE_UCAST) {
17342 + wol->supported &= ~WAKE_UCAST;
17344 + if (adapter->wol & E1000_WUFC_EX)
17345 + e_err("Interface does not support directed (unicast) "
17346 + "frame wake-up packets\n");
17349 + if (adapter->wol & E1000_WUFC_EX)
17350 + wol->wolopts |= WAKE_UCAST;
17351 + if (adapter->wol & E1000_WUFC_MC)
17352 + wol->wolopts |= WAKE_MCAST;
17353 + if (adapter->wol & E1000_WUFC_BC)
17354 + wol->wolopts |= WAKE_BCAST;
17355 + if (adapter->wol & E1000_WUFC_MAG)
17356 + wol->wolopts |= WAKE_MAGIC;
17357 + if (adapter->wol & E1000_WUFC_LNKC)
17358 + wol->wolopts |= WAKE_PHY;
17359 + if (adapter->wol & E1000_WUFC_ARP)
17360 + wol->wolopts |= WAKE_ARP;
17363 +static int e1000_set_wol(struct net_device *netdev,
17364 + struct ethtool_wolinfo *wol)
17366 + struct e1000_adapter *adapter = netdev_priv(netdev);
17368 + if (!(adapter->flags & FLAG_HAS_WOL) ||
17369 + !device_can_wakeup(&adapter->pdev->dev) ||
17370 + (wol->wolopts & ~(WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
17371 + WAKE_MAGIC | WAKE_PHY | WAKE_ARP)))
17372 + return -EOPNOTSUPP;
17374 + /* these settings will always override what we currently have */
17375 + adapter->wol = 0;
17377 + if (wol->wolopts & WAKE_UCAST)
17378 + adapter->wol |= E1000_WUFC_EX;
17379 + if (wol->wolopts & WAKE_MCAST)
17380 + adapter->wol |= E1000_WUFC_MC;
17381 + if (wol->wolopts & WAKE_BCAST)
17382 + adapter->wol |= E1000_WUFC_BC;
17383 + if (wol->wolopts & WAKE_MAGIC)
17384 + adapter->wol |= E1000_WUFC_MAG;
17385 + if (wol->wolopts & WAKE_PHY)
17386 + adapter->wol |= E1000_WUFC_LNKC;
17387 + if (wol->wolopts & WAKE_ARP)
17388 + adapter->wol |= E1000_WUFC_ARP;
17390 + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
17395 +/* toggle LED 4 times per second = 2 "blinks" per second */
17396 +#define E1000_ID_INTERVAL (HZ/4)
17398 +/* bit defines for adapter->led_status */
17399 +#define E1000_LED_ON 0
17401 +static void e1000e_led_blink_task(struct work_struct *work)
17403 + struct e1000_adapter *adapter = container_of(work,
17404 + struct e1000_adapter, led_blink_task);
17406 + if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
17407 + adapter->hw.mac.ops.led_off(&adapter->hw);
17409 + adapter->hw.mac.ops.led_on(&adapter->hw);
17412 +static void e1000_led_blink_callback(unsigned long data)
17414 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
17416 + schedule_work(&adapter->led_blink_task);
17417 + mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
17420 +static int e1000_phys_id(struct net_device *netdev, u32 data)
17422 + struct e1000_adapter *adapter = netdev_priv(netdev);
17423 + struct e1000_hw *hw = &adapter->hw;
17428 + if ((hw->phy.type == e1000_phy_ife) ||
17429 + (hw->mac.type == e1000_pchlan) ||
17430 + (hw->mac.type == e1000_82583) ||
17431 + (hw->mac.type == e1000_82574)) {
17432 + INIT_WORK(&adapter->led_blink_task, e1000e_led_blink_task);
17433 + if (!adapter->blink_timer.function) {
17434 + init_timer(&adapter->blink_timer);
17435 + adapter->blink_timer.function =
17436 + e1000_led_blink_callback;
17437 + adapter->blink_timer.data = (unsigned long) adapter;
17439 + mod_timer(&adapter->blink_timer, jiffies);
17440 + msleep_interruptible(data * 1000);
17441 + del_timer_sync(&adapter->blink_timer);
17442 + if (hw->phy.type == e1000_phy_ife)
17443 + e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
17445 + e1000e_blink_led(hw);
17446 + msleep_interruptible(data * 1000);
17449 + hw->mac.ops.led_off(hw);
17450 + clear_bit(E1000_LED_ON, &adapter->led_status);
17451 + hw->mac.ops.cleanup_led(hw);
17456 +static int e1000_get_coalesce(struct net_device *netdev,
17457 + struct ethtool_coalesce *ec)
17459 + struct e1000_adapter *adapter = netdev_priv(netdev);
17461 + if (adapter->itr_setting <= 3)
17462 + ec->rx_coalesce_usecs = adapter->itr_setting;
17464 + ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
17469 +static int e1000_set_coalesce(struct net_device *netdev,
17470 + struct ethtool_coalesce *ec)
17472 + struct e1000_adapter *adapter = netdev_priv(netdev);
17473 + struct e1000_hw *hw = &adapter->hw;
17475 + if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) ||
17476 + ((ec->rx_coalesce_usecs > 3) &&
17477 + (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) ||
17478 + (ec->rx_coalesce_usecs == 2))
17481 + if (ec->rx_coalesce_usecs <= 3) {
17482 + adapter->itr = 20000;
17483 + adapter->itr_setting = ec->rx_coalesce_usecs;
17485 + adapter->itr = (1000000 / ec->rx_coalesce_usecs);
17486 + adapter->itr_setting = adapter->itr & ~3;
17489 + if (adapter->itr_setting != 0)
17490 + ew32(ITR, 1000000000 / (adapter->itr * 256));
17497 +static int e1000_nway_reset(struct net_device *netdev)
17499 + struct e1000_adapter *adapter = netdev_priv(netdev);
17500 + if (netif_running(netdev))
17501 + e1000e_reinit_locked(adapter);
17505 +static void e1000_get_ethtool_stats(struct net_device *netdev,
17506 + struct ethtool_stats *stats,
17509 + struct e1000_adapter *adapter = netdev_priv(netdev);
17512 + e1000e_update_stats(adapter);
17513 + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
17514 + char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
17515 + data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
17516 + sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
17520 +static void e1000_get_strings(struct net_device *netdev, u32 stringset,
17526 + switch (stringset) {
17527 + case ETH_SS_TEST:
17528 + memcpy(data, *e1000_gstrings_test, sizeof(e1000_gstrings_test));
17530 + case ETH_SS_STATS:
17531 + for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
17532 + memcpy(p, e1000_gstrings_stats[i].stat_string,
17533 + ETH_GSTRING_LEN);
17534 + p += ETH_GSTRING_LEN;
17540 +static const struct ethtool_ops e1000_ethtool_ops = {
17541 + .get_settings = e1000_get_settings,
17542 + .set_settings = e1000_set_settings,
17543 + .get_drvinfo = e1000_get_drvinfo,
17544 + .get_regs_len = e1000_get_regs_len,
17545 + .get_regs = e1000_get_regs,
17546 + .get_wol = e1000_get_wol,
17547 + .set_wol = e1000_set_wol,
17548 + .get_msglevel = e1000_get_msglevel,
17549 + .set_msglevel = e1000_set_msglevel,
17550 + .nway_reset = e1000_nway_reset,
17551 + .get_link = e1000_get_link,
17552 + .get_eeprom_len = e1000_get_eeprom_len,
17553 + .get_eeprom = e1000_get_eeprom,
17554 + .set_eeprom = e1000_set_eeprom,
17555 + .get_ringparam = e1000_get_ringparam,
17556 + .set_ringparam = e1000_set_ringparam,
17557 + .get_pauseparam = e1000_get_pauseparam,
17558 + .set_pauseparam = e1000_set_pauseparam,
17559 + .get_rx_csum = e1000_get_rx_csum,
17560 + .set_rx_csum = e1000_set_rx_csum,
17561 + .get_tx_csum = e1000_get_tx_csum,
17562 + .set_tx_csum = e1000_set_tx_csum,
17563 + .get_sg = ethtool_op_get_sg,
17564 + .set_sg = ethtool_op_set_sg,
17565 +#ifdef NETIF_F_TSO
17566 + .get_tso = ethtool_op_get_tso,
17567 + .set_tso = e1000_set_tso,
17569 + .self_test = e1000_diag_test,
17570 + .get_strings = e1000_get_strings,
17571 + .phys_id = e1000_phys_id,
17572 + .get_ethtool_stats = e1000_get_ethtool_stats,
17573 + .self_test_count = e1000_get_self_test_count,
17574 + .get_stats_count = e1000_get_stats_count,
17575 + .get_coalesce = e1000_get_coalesce,
17576 + .set_coalesce = e1000_set_coalesce,
17577 +#ifdef NETIF_F_LRO
17578 + .get_flags = ethtool_op_get_flags,
17579 + .set_flags = ethtool_op_set_flags,
17583 +void e1000e_set_ethtool_ops(struct net_device *netdev)
17585 + /* have to "undeclare" const on this struct to remove warnings */
17586 + SET_ETHTOOL_OPS(netdev, (struct ethtool_ops *)&e1000_ethtool_ops);
17588 +#endif /* SIOCETHTOOL */
17589 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/hw.h linux-2.6.22-10/drivers/net/e1000e/hw.h
17590 --- linux-2.6.22-0/drivers/net/e1000e/hw.h 1970-01-01 01:00:00.000000000 +0100
17591 +++ linux-2.6.22-10/drivers/net/e1000e/hw.h 2009-06-24 00:32:20.000000000 +0200
17593 +/*******************************************************************************
17595 + Intel PRO/1000 Linux driver
17596 + Copyright(c) 1999 - 2009 Intel Corporation.
17598 + This program is free software; you can redistribute it and/or modify it
17599 + under the terms and conditions of the GNU General Public License,
17600 + version 2, as published by the Free Software Foundation.
17602 + This program is distributed in the hope it will be useful, but WITHOUT
17603 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17604 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17607 + You should have received a copy of the GNU General Public License along with
17608 + this program; if not, write to the Free Software Foundation, Inc.,
17609 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17611 + The full GNU General Public License is included in this distribution in
17612 + the file called "COPYING".
17614 + Contact Information:
17615 + Linux NICS <linux.nics@intel.com>
17616 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
17617 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17619 +*******************************************************************************/
17621 +#ifndef _E1000_HW_H_
17622 +#define _E1000_HW_H_
17624 +#include "e1000_regs.h"
17625 +#include "e1000_defines.h"
17629 +#define E1000_DEV_ID_82571EB_COPPER 0x105E
17630 +#define E1000_DEV_ID_82571EB_FIBER 0x105F
17631 +#define E1000_DEV_ID_82571EB_SERDES 0x1060
17632 +#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
17633 +#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
17634 +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
17635 +#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17636 +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
17637 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
17638 +#define E1000_DEV_ID_82572EI_COPPER 0x107D
17639 +#define E1000_DEV_ID_82572EI_FIBER 0x107E
17640 +#define E1000_DEV_ID_82572EI_SERDES 0x107F
17641 +#define E1000_DEV_ID_82572EI 0x10B9
17642 +#define E1000_DEV_ID_82573E 0x108B
17643 +#define E1000_DEV_ID_82573E_IAMT 0x108C
17644 +#define E1000_DEV_ID_82573L 0x109A
17645 +#define E1000_DEV_ID_82574L 0x10D3
17646 +#define E1000_DEV_ID_82574LA 0x10F6
17647 +#define E1000_DEV_ID_82583V 0x150C
17648 +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
17649 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
17650 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
17651 +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
17652 +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
17653 +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
17654 +#define E1000_DEV_ID_ICH8_IGP_C 0x104B
17655 +#define E1000_DEV_ID_ICH8_IFE 0x104C
17656 +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
17657 +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
17658 +#define E1000_DEV_ID_ICH8_IGP_M 0x104D
17659 +#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
17660 +#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
17661 +#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
17662 +#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
17663 +#define E1000_DEV_ID_ICH9_BM 0x10E5
17664 +#define E1000_DEV_ID_ICH9_IGP_C 0x294C
17665 +#define E1000_DEV_ID_ICH9_IFE 0x10C0
17666 +#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
17667 +#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
17668 +#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
17669 +#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
17670 +#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
17671 +#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
17672 +#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
17673 +#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
17674 +#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
17675 +#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
17676 +#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
17677 +#define E1000_REVISION_0 0
17678 +#define E1000_REVISION_1 1
17679 +#define E1000_REVISION_2 2
17680 +#define E1000_REVISION_3 3
17681 +#define E1000_REVISION_4 4
17683 +#define E1000_FUNC_0 0
17684 +#define E1000_FUNC_1 1
17686 +#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
17687 +#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
17689 +enum e1000_mac_type {
17690 + e1000_undefined = 0,
17696 + e1000_80003es2lan,
17701 + e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
17704 +enum e1000_media_type {
17705 + e1000_media_type_unknown = 0,
17706 + e1000_media_type_copper = 1,
17707 + e1000_media_type_fiber = 2,
17708 + e1000_media_type_internal_serdes = 3,
17709 + e1000_num_media_types
17712 +enum e1000_nvm_type {
17713 + e1000_nvm_unknown = 0,
17715 + e1000_nvm_eeprom_spi,
17716 + e1000_nvm_flash_hw,
17717 + e1000_nvm_flash_sw
17720 +enum e1000_nvm_override {
17721 + e1000_nvm_override_none = 0,
17722 + e1000_nvm_override_spi_small,
17723 + e1000_nvm_override_spi_large,
17726 +enum e1000_phy_type {
17727 + e1000_phy_unknown = 0,
17732 + e1000_phy_gg82563,
17740 +enum e1000_bus_type {
17741 + e1000_bus_type_unknown = 0,
17742 + e1000_bus_type_pci,
17743 + e1000_bus_type_pcix,
17744 + e1000_bus_type_pci_express,
17745 + e1000_bus_type_reserved
17748 +enum e1000_bus_speed {
17749 + e1000_bus_speed_unknown = 0,
17750 + e1000_bus_speed_33,
17751 + e1000_bus_speed_66,
17752 + e1000_bus_speed_100,
17753 + e1000_bus_speed_120,
17754 + e1000_bus_speed_133,
17755 + e1000_bus_speed_2500,
17756 + e1000_bus_speed_5000,
17757 + e1000_bus_speed_reserved
17760 +enum e1000_bus_width {
17761 + e1000_bus_width_unknown = 0,
17762 + e1000_bus_width_pcie_x1,
17763 + e1000_bus_width_pcie_x2,
17764 + e1000_bus_width_pcie_x4 = 4,
17765 + e1000_bus_width_pcie_x8 = 8,
17766 + e1000_bus_width_32,
17767 + e1000_bus_width_64,
17768 + e1000_bus_width_reserved
17771 +enum e1000_1000t_rx_status {
17772 + e1000_1000t_rx_status_not_ok = 0,
17773 + e1000_1000t_rx_status_ok,
17774 + e1000_1000t_rx_status_undefined = 0xFF
17777 +enum e1000_rev_polarity {
17778 + e1000_rev_polarity_normal = 0,
17779 + e1000_rev_polarity_reversed,
17780 + e1000_rev_polarity_undefined = 0xFF
17783 +enum e1000_fc_mode {
17784 + e1000_fc_none = 0,
17785 + e1000_fc_rx_pause,
17786 + e1000_fc_tx_pause,
17788 + e1000_fc_default = 0xFF
17791 +enum e1000_ms_type {
17792 + e1000_ms_hw_default = 0,
17793 + e1000_ms_force_master,
17794 + e1000_ms_force_slave,
17798 +enum e1000_smart_speed {
17799 + e1000_smart_speed_default = 0,
17800 + e1000_smart_speed_on,
17801 + e1000_smart_speed_off
17804 +enum e1000_serdes_link_state {
17805 + e1000_serdes_link_down = 0,
17806 + e1000_serdes_link_autoneg_progress,
17807 + e1000_serdes_link_autoneg_complete,
17808 + e1000_serdes_link_forced_up
17811 +/* Receive Descriptor */
17812 +struct e1000_rx_desc {
17813 + __le64 buffer_addr; /* Address of the descriptor's data buffer */
17814 + __le16 length; /* Length of data DMAed into data buffer */
17815 + __le16 csum; /* Packet checksum */
17816 + u8 status; /* Descriptor status */
17817 + u8 errors; /* Descriptor Errors */
17821 +/* Receive Descriptor - Extended */
17822 +union e1000_rx_desc_extended {
17824 + __le64 buffer_addr;
17829 + __le32 mrq; /* Multiple Rx Queues */
17831 + __le32 rss; /* RSS Hash */
17833 + __le16 ip_id; /* IP id */
17834 + __le16 csum; /* Packet Checksum */
17839 + __le32 status_error; /* ext status/error */
17841 + __le16 vlan; /* VLAN tag */
17843 + } wb; /* writeback */
17846 +#define MAX_PS_BUFFERS 4
17847 +/* Receive Descriptor - Packet Split */
17848 +union e1000_rx_desc_packet_split {
17850 + /* one buffer for protocol header(s), three data buffers */
17851 + __le64 buffer_addr[MAX_PS_BUFFERS];
17855 + __le32 mrq; /* Multiple Rx Queues */
17857 + __le32 rss; /* RSS Hash */
17859 + __le16 ip_id; /* IP id */
17860 + __le16 csum; /* Packet Checksum */
17865 + __le32 status_error; /* ext status/error */
17866 + __le16 length0; /* length of buffer 0 */
17867 + __le16 vlan; /* VLAN tag */
17870 + __le16 header_status;
17871 + __le16 length[3]; /* length of buffers 1-3 */
17874 + } wb; /* writeback */
17877 +/* Transmit Descriptor */
17878 +struct e1000_tx_desc {
17879 + __le64 buffer_addr; /* Address of the descriptor's data buffer */
17883 + __le16 length; /* Data buffer length */
17884 + u8 cso; /* Checksum offset */
17885 + u8 cmd; /* Descriptor control */
17891 + u8 status; /* Descriptor status */
17892 + u8 css; /* Checksum start */
17898 +/* Offload Context Descriptor */
17899 +struct e1000_context_desc {
17901 + __le32 ip_config;
17903 + u8 ipcss; /* IP checksum start */
17904 + u8 ipcso; /* IP checksum offset */
17905 + __le16 ipcse; /* IP checksum end */
17909 + __le32 tcp_config;
17911 + u8 tucss; /* TCP checksum start */
17912 + u8 tucso; /* TCP checksum offset */
17913 + __le16 tucse; /* TCP checksum end */
17916 + __le32 cmd_and_length;
17920 + u8 status; /* Descriptor status */
17921 + u8 hdr_len; /* Header length */
17922 + __le16 mss; /* Maximum segment size */
17927 +/* Offload data descriptor */
17928 +struct e1000_data_desc {
17929 + __le64 buffer_addr; /* Address of the descriptor's buffer address */
17933 + __le16 length; /* Data buffer length */
17941 + u8 status; /* Descriptor status */
17942 + u8 popts; /* Packet Options */
17948 +/* Statistics counters collected by the MAC */
17949 +struct e1000_hw_stats {
18017 +struct e1000_phy_stats {
18019 + u32 receive_errors;
18022 +struct e1000_host_mng_dhcp_cookie {
18033 +/* Host Interface "Rev 1" */
18034 +struct e1000_host_command_header {
18036 + u8 command_length;
18037 + u8 command_options;
18041 +#define E1000_HI_MAX_DATA_LENGTH 252
18042 +struct e1000_host_command_info {
18043 + struct e1000_host_command_header command_header;
18044 + u8 command_data[E1000_HI_MAX_DATA_LENGTH];
18047 +/* Host Interface "Rev 2" */
18048 +struct e1000_host_mng_command_header {
18053 + u16 command_length;
18056 +#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
18057 +struct e1000_host_mng_command_info {
18058 + struct e1000_host_mng_command_header command_header;
18059 + u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
18062 +#include "e1000_mac.h"
18063 +#include "e1000_phy.h"
18064 +#include "e1000_nvm.h"
18065 +#include "e1000_manage.h"
18067 +struct e1000_mac_operations {
18068 + /* Function pointers for the MAC. */
18069 + s32 (*init_params)(struct e1000_hw *);
18070 + s32 (*id_led_init)(struct e1000_hw *);
18071 + s32 (*blink_led)(struct e1000_hw *);
18072 + s32 (*check_for_link)(struct e1000_hw *);
18073 + bool (*check_mng_mode)(struct e1000_hw *hw);
18074 + s32 (*cleanup_led)(struct e1000_hw *);
18075 + void (*clear_hw_cntrs)(struct e1000_hw *);
18076 + void (*clear_vfta)(struct e1000_hw *);
18077 + s32 (*get_bus_info)(struct e1000_hw *);
18078 + void (*set_lan_id)(struct e1000_hw *);
18079 + s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
18080 + s32 (*led_on)(struct e1000_hw *);
18081 + s32 (*led_off)(struct e1000_hw *);
18082 + void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
18083 + s32 (*reset_hw)(struct e1000_hw *);
18084 + s32 (*init_hw)(struct e1000_hw *);
18085 + s32 (*setup_link)(struct e1000_hw *);
18086 + s32 (*setup_physical_interface)(struct e1000_hw *);
18087 + s32 (*setup_led)(struct e1000_hw *);
18088 + void (*write_vfta)(struct e1000_hw *, u32, u32);
18089 + void (*mta_set)(struct e1000_hw *, u32);
18090 + void (*config_collision_dist)(struct e1000_hw *);
18091 + void (*rar_set)(struct e1000_hw *, u8*, u32);
18092 + s32 (*read_mac_addr)(struct e1000_hw *);
18093 + s32 (*validate_mdi_setting)(struct e1000_hw *);
18094 + s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
18095 + s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
18096 + struct e1000_host_mng_command_header*);
18097 + s32 (*mng_enable_host_if)(struct e1000_hw *);
18098 + s32 (*wait_autoneg)(struct e1000_hw *);
18101 +struct e1000_phy_operations {
18102 + s32 (*init_params)(struct e1000_hw *);
18103 + s32 (*acquire)(struct e1000_hw *);
18104 + s32 (*cfg_on_link_up)(struct e1000_hw *);
18105 + s32 (*check_polarity)(struct e1000_hw *);
18106 + s32 (*check_reset_block)(struct e1000_hw *);
18107 + s32 (*commit)(struct e1000_hw *);
18108 + s32 (*force_speed_duplex)(struct e1000_hw *);
18109 + s32 (*get_cfg_done)(struct e1000_hw *hw);
18110 + s32 (*get_cable_length)(struct e1000_hw *);
18111 + s32 (*get_info)(struct e1000_hw *);
18112 + s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
18113 + void (*release)(struct e1000_hw *);
18114 + s32 (*reset)(struct e1000_hw *);
18115 + s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
18116 + s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
18117 + s32 (*write_reg)(struct e1000_hw *, u32, u16);
18118 + void (*power_up)(struct e1000_hw *);
18119 + void (*power_down)(struct e1000_hw *);
18122 +struct e1000_nvm_operations {
18123 + s32 (*init_params)(struct e1000_hw *);
18124 + s32 (*acquire)(struct e1000_hw *);
18125 + s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
18126 + void (*release)(struct e1000_hw *);
18127 + void (*reload)(struct e1000_hw *);
18128 + s32 (*update)(struct e1000_hw *);
18129 + s32 (*valid_led_default)(struct e1000_hw *, u16 *);
18130 + s32 (*validate)(struct e1000_hw *);
18131 + s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
18134 +struct e1000_mac_info {
18135 + struct e1000_mac_operations ops;
18139 + enum e1000_mac_type type;
18141 + u32 collision_delta;
18142 + u32 ledctl_default;
18143 + u32 ledctl_mode1;
18144 + u32 ledctl_mode2;
18145 + u32 mc_filter_type;
18146 + u32 tx_packet_delta;
18149 + u16 current_ifs_val;
18153 + u16 ifs_step_size;
18154 + u16 mta_reg_count;
18156 + /* Maximum size of the MTA register table in all supported adapters */
18157 + #define MAX_MTA_REG 128
18158 + u32 mta_shadow[MAX_MTA_REG];
18159 + u16 rar_entry_count;
18161 + u8 forced_speed_duplex;
18163 + bool adaptive_ifs;
18164 + bool arc_subsystem_valid;
18165 + bool asf_firmware_present;
18167 + bool autoneg_failed;
18168 + bool get_link_status;
18169 + bool in_ifs_mode;
18170 + enum e1000_serdes_link_state serdes_link_state;
18171 + bool serdes_has_link;
18172 + bool tx_pkt_filtering;
18175 +struct e1000_phy_info {
18176 + struct e1000_phy_operations ops;
18177 + enum e1000_phy_type type;
18179 + enum e1000_1000t_rx_status local_rx;
18180 + enum e1000_1000t_rx_status remote_rx;
18181 + enum e1000_ms_type ms_type;
18182 + enum e1000_ms_type original_ms_type;
18183 + enum e1000_rev_polarity cable_polarity;
18184 + enum e1000_smart_speed smart_speed;
18188 + u32 reset_delay_us; /* in usec */
18191 + enum e1000_media_type media_type;
18193 + u16 autoneg_advertised;
18194 + u16 autoneg_mask;
18195 + u16 cable_length;
18196 + u16 max_cable_length;
18197 + u16 min_cable_length;
18201 + bool disable_polarity_correction;
18203 + bool polarity_correction;
18204 + bool reset_disable;
18205 + bool speed_downgraded;
18206 + bool autoneg_wait_to_complete;
18209 +struct e1000_nvm_info {
18210 + struct e1000_nvm_operations ops;
18211 + enum e1000_nvm_type type;
18212 + enum e1000_nvm_override override;
18214 + u32 flash_bank_size;
18215 + u32 flash_base_addr;
18219 + u16 address_bits;
18224 +struct e1000_bus_info {
18225 + enum e1000_bus_type type;
18226 + enum e1000_bus_speed speed;
18227 + enum e1000_bus_width width;
18230 + u16 pci_cmd_word;
18233 +struct e1000_fc_info {
18234 + u32 high_water; /* Flow control high-water mark */
18235 + u32 low_water; /* Flow control low-water mark */
18236 + u16 pause_time; /* Flow control pause timer */
18237 + bool send_xon; /* Flow control send XON */
18238 + bool strict_ieee; /* Strict IEEE mode */
18239 + enum e1000_fc_mode current_mode; /* FC mode in effect */
18240 + enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
18243 +struct e1000_dev_spec_82571 {
18244 + bool laa_is_present;
18248 +struct e1000_shadow_ram {
18253 +#define E1000_ICH8_SHADOW_RAM_WORDS 2048
18255 +struct e1000_dev_spec_ich8lan {
18256 + bool kmrn_lock_loss_workaround_enabled;
18257 + struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
18261 + struct e1000_adapter *adapter;
18263 + u8 __iomem *hw_addr;
18264 + u8 __iomem *flash_address;
18266 + struct e1000_mac_info mac;
18267 + struct e1000_fc_info fc;
18268 + struct e1000_phy_info phy;
18269 + struct e1000_nvm_info nvm;
18270 + struct e1000_bus_info bus;
18271 + struct e1000_host_mng_dhcp_cookie mng_cookie;
18274 + struct e1000_dev_spec_82571 _82571;
18275 + struct e1000_dev_spec_ich8lan ich8lan;
18279 + u16 subsystem_vendor_id;
18280 + u16 subsystem_device_id;
18286 +#include "e1000_82571.h"
18287 +#include "e1000_80003es2lan.h"
18288 +#include "e1000_ich8lan.h"
18290 +/* These functions must be implemented by drivers */
18291 +s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
18294 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/kcompat.c linux-2.6.22-10/drivers/net/e1000e/kcompat.c
18295 --- linux-2.6.22-0/drivers/net/e1000e/kcompat.c 1970-01-01 01:00:00.000000000 +0100
18296 +++ linux-2.6.22-10/drivers/net/e1000e/kcompat.c 2009-06-24 00:32:20.000000000 +0200
18298 +/*******************************************************************************
18300 + Intel PRO/1000 Linux driver
18301 + Copyright(c) 1999 - 2009 Intel Corporation.
18303 + This program is free software; you can redistribute it and/or modify it
18304 + under the terms and conditions of the GNU General Public License,
18305 + version 2, as published by the Free Software Foundation.
18307 + This program is distributed in the hope it will be useful, but WITHOUT
18308 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18309 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18312 + You should have received a copy of the GNU General Public License along with
18313 + this program; if not, write to the Free Software Foundation, Inc.,
18314 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18316 + The full GNU General Public License is included in this distribution in
18317 + the file called "COPYING".
18319 + Contact Information:
18320 + Linux NICS <linux.nics@intel.com>
18321 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18322 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18324 +*******************************************************************************/
18326 +#include "e1000.h"
18327 +#include "kcompat.h"
18329 +/*****************************************************************************/
18330 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) )
18332 +_kc_skb_pad(struct sk_buff *skb, int pad)
18334 + struct sk_buff *nskb;
18336 + /* If the skbuff is non linear tailroom is always zero.. */
18337 + if(skb_tailroom(skb) >= pad)
18339 + memset(skb->data+skb->len, 0, pad);
18343 + nskb = skb_copy_expand(skb, skb_headroom(skb), skb_tailroom(skb) + pad, GFP_ATOMIC);
18346 + memset(nskb->data+nskb->len, 0, pad);
18349 +#endif /* < 2.4.21 */
18351 +/*****************************************************************************/
18352 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )
18354 +/**************************************/
18355 +/* PCI DMA MAPPING */
18357 +#if defined(CONFIG_HIGHMEM)
18359 +#ifndef PCI_DRAM_OFFSET
18360 +#define PCI_DRAM_OFFSET 0
18364 +_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,
18365 + size_t size, int direction)
18367 + return (((u64) (page - mem_map) << PAGE_SHIFT) + offset +
18368 + PCI_DRAM_OFFSET);
18371 +#else /* CONFIG_HIGHMEM */
18374 +_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,
18375 + size_t size, int direction)
18377 + return pci_map_single(dev, (void *)page_address(page) + offset, size,
18381 +#endif /* CONFIG_HIGHMEM */
18384 +_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size,
18387 + return pci_unmap_single(dev, dma_addr, size, direction);
18390 +#endif /* 2.4.13 => 2.4.3 */
18392 +/*****************************************************************************/
18393 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )
18395 +/**************************************/
18396 +/* PCI DRIVER API */
18399 +_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask)
18401 + if (!pci_dma_supported(dev, mask))
18403 + dev->dma_mask = mask;
18408 +_kc_pci_request_regions(struct pci_dev *dev, char *res_name)
18412 + for (i = 0; i < 6; i++) {
18413 + if (pci_resource_len(dev, i) == 0)
18416 + if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
18417 + if (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {
18418 + pci_release_regions(dev);
18421 + } else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) {
18422 + if (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {
18423 + pci_release_regions(dev);
18432 +_kc_pci_release_regions(struct pci_dev *dev)
18436 + for (i = 0; i < 6; i++) {
18437 + if (pci_resource_len(dev, i) == 0)
18440 + if (pci_resource_flags(dev, i) & IORESOURCE_IO)
18441 + release_region(pci_resource_start(dev, i), pci_resource_len(dev, i));
18443 + else if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
18444 + release_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i));
18448 +/**************************************/
18449 +/* NETWORK DRIVER API */
18451 +struct net_device *
18452 +_kc_alloc_etherdev(int sizeof_priv)
18454 + struct net_device *dev;
18457 + alloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31;
18458 + dev = kmalloc(alloc_size, GFP_KERNEL);
18461 + memset(dev, 0, alloc_size);
18464 + dev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31);
18465 + dev->name[0] = '\0';
18466 + ether_setup(dev);
18472 +_kc_is_valid_ether_addr(u8 *addr)
18474 + const char zaddr[6] = { 0, };
18476 + return !(addr[0] & 1) && memcmp(addr, zaddr, 6);
18479 +#endif /* 2.4.3 => 2.4.0 */
18481 +/*****************************************************************************/
18482 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )
18485 +_kc_pci_set_power_state(struct pci_dev *dev, int state)
18491 +_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable)
18496 +#endif /* 2.4.6 => 2.4.3 */
18498 +/*****************************************************************************/
18499 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
18500 +void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page,
18501 + int off, int size)
18503 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
18504 + frag->page = page;
18505 + frag->page_offset = off;
18506 + frag->size = size;
18507 + skb_shinfo(skb)->nr_frags = i + 1;
18511 + * Original Copyright:
18512 + * find_next_bit.c: fallback find next bit implementation
18514 + * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
18515 + * Written by David Howells (dhowells@redhat.com)
18519 + * find_next_bit - find the next set bit in a memory region
18520 + * @addr: The address to base the search on
18521 + * @offset: The bitnumber to start searching at
18522 + * @size: The maximum size to search
18524 +unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
18525 + unsigned long offset)
18527 + const unsigned long *p = addr + BITOP_WORD(offset);
18528 + unsigned long result = offset & ~(BITS_PER_LONG-1);
18529 + unsigned long tmp;
18531 + if (offset >= size)
18534 + offset %= BITS_PER_LONG;
18537 + tmp &= (~0UL << offset);
18538 + if (size < BITS_PER_LONG)
18539 + goto found_first;
18541 + goto found_middle;
18542 + size -= BITS_PER_LONG;
18543 + result += BITS_PER_LONG;
18545 + while (size & ~(BITS_PER_LONG-1)) {
18546 + if ((tmp = *(p++)))
18547 + goto found_middle;
18548 + result += BITS_PER_LONG;
18549 + size -= BITS_PER_LONG;
18556 + tmp &= (~0UL >> (BITS_PER_LONG - size));
18557 + if (tmp == 0UL) /* Are any bits set? */
18558 + return result + size; /* Nope. */
18560 + return result + ffs(tmp);
18563 +#endif /* 2.6.0 => 2.4.6 */
18565 +/*****************************************************************************/
18566 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )
18567 +void *_kc_kzalloc(size_t size, int flags)
18569 + void *ret = kmalloc(size, flags);
18571 + memset(ret, 0, size);
18574 +#endif /* <= 2.6.13 */
18576 +/*****************************************************************************/
18577 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )
18578 +struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev,
18579 + unsigned int length)
18581 + /* 16 == NET_PAD_SKB */
18582 + struct sk_buff *skb;
18583 + skb = alloc_skb(length + 16, GFP_ATOMIC);
18584 + if (likely(skb != NULL)) {
18585 + skb_reserve(skb, 16);
18590 +#endif /* <= 2.6.17 */
18592 +/*****************************************************************************/
18593 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )
18594 +int _kc_pci_save_state(struct pci_dev *pdev)
18596 + struct net_device *netdev = pci_get_drvdata(pdev);
18597 + struct adapter_struct *adapter = netdev_priv(netdev);
18598 + int size = PCI_CONFIG_SPACE_LEN, i;
18599 + u16 pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP);
18600 + u16 pcie_link_status;
18602 + if (pcie_cap_offset) {
18603 + if (!pci_read_config_word(pdev,
18604 + pcie_cap_offset + PCIE_LINK_STATUS,
18605 + &pcie_link_status))
18606 + size = PCIE_CONFIG_SPACE_LEN;
18608 + pci_config_space_ich8lan();
18609 +#ifdef HAVE_PCI_ERS
18610 + if (adapter->config_space == NULL)
18612 + WARN_ON(adapter->config_space != NULL);
18614 + adapter->config_space = kmalloc(size, GFP_KERNEL);
18615 + if (!adapter->config_space) {
18616 + printk(KERN_ERR "Out of memory in pci_save_state\n");
18619 + for (i = 0; i < (size / 4); i++)
18620 + pci_read_config_dword(pdev, i * 4, &adapter->config_space[i]);
18624 +void _kc_pci_restore_state(struct pci_dev * pdev)
18626 + struct net_device *netdev = pci_get_drvdata(pdev);
18627 + struct adapter_struct *adapter = netdev_priv(netdev);
18628 + int size = PCI_CONFIG_SPACE_LEN, i;
18629 + u16 pcie_cap_offset;
18630 + u16 pcie_link_status;
18632 + if (adapter->config_space != NULL) {
18633 + pcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP);
18634 + if (pcie_cap_offset &&
18635 + !pci_read_config_word(pdev,
18636 + pcie_cap_offset + PCIE_LINK_STATUS,
18637 + &pcie_link_status))
18638 + size = PCIE_CONFIG_SPACE_LEN;
18640 + pci_config_space_ich8lan();
18641 + for (i = 0; i < (size / 4); i++)
18642 + pci_write_config_dword(pdev, i * 4, adapter->config_space[i]);
18643 +#ifndef HAVE_PCI_ERS
18644 + kfree(adapter->config_space);
18645 + adapter->config_space = NULL;
18650 +#ifdef HAVE_PCI_ERS
18651 +void _kc_free_netdev(struct net_device *netdev)
18653 + struct adapter_struct *adapter = netdev_priv(netdev);
18655 + if (adapter->config_space != NULL)
18656 + kfree(adapter->config_space);
18657 +#ifdef CONFIG_SYSFS
18658 + if (netdev->reg_state == NETREG_UNINITIALIZED) {
18659 + kfree((char *)netdev - netdev->padded);
18661 + BUG_ON(netdev->reg_state != NETREG_UNREGISTERED);
18662 + netdev->reg_state = NETREG_RELEASED;
18663 + class_device_put(&netdev->class_dev);
18666 + kfree((char *)netdev - netdev->padded);
18670 +#endif /* <= 2.6.18 */
18672 +/*****************************************************************************/
18673 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )
18675 +/* this function returns the true netdev of the napi struct */
18676 +struct net_device * napi_to_netdev(struct napi_struct *napi)
18678 + struct adapter_struct *adapter = container_of(napi,
18679 + struct adapter_struct,
18681 + return adapter->netdev;
18684 +int __kc_adapter_clean(struct net_device *netdev, int *budget)
18687 + int work_to_do = min(*budget, netdev->quota);
18688 + struct adapter_struct *adapter = netdev_priv(netdev);
18689 + struct napi_struct *napi = &adapter->napi;
18690 + work_done = napi->poll(napi, work_to_do);
18691 + *budget -= work_done;
18692 + netdev->quota -= work_done;
18693 + return (work_done >= work_to_do) ? 1 : 0;
18696 +#endif /* <= 2.6.24 */
18698 +/*****************************************************************************/
18699 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )
18701 +void _kc_netif_tx_stop_all_queues(struct net_device *netdev)
18703 + struct adapter_struct *adapter = netdev_priv(netdev);
18706 + netif_stop_queue(netdev);
18707 + if (netif_is_multiqueue(netdev))
18708 + for (i = 0; i < adapter->num_tx_queues; i++)
18709 + netif_stop_subqueue(netdev, i);
18711 +void _kc_netif_tx_wake_all_queues(struct net_device *netdev)
18713 + struct adapter_struct *adapter = netdev_priv(netdev);
18716 + netif_wake_queue(netdev);
18717 + if (netif_is_multiqueue(netdev))
18718 + for (i = 0; i < adapter->num_tx_queues; i++)
18719 + netif_wake_subqueue(netdev, i);
18721 +void _kc_netif_tx_start_all_queues(struct net_device *netdev)
18723 + struct adapter_struct *adapter = netdev_priv(netdev);
18726 + netif_start_queue(netdev);
18727 + if (netif_is_multiqueue(netdev))
18728 + for (i = 0; i < adapter->num_tx_queues; i++)
18729 + netif_start_subqueue(netdev, i);
18731 +#endif /* HAVE_TX_MQ */
18732 +#endif /* < 2.6.27 */
18734 +/*****************************************************************************/
18735 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )
18738 +_kc_pci_prepare_to_sleep(struct pci_dev *dev)
18740 + pci_power_t target_state;
18743 + target_state = pci_choose_state(dev, PMSG_SUSPEND);
18745 + pci_enable_wake(dev, target_state, true);
18747 + error = pci_set_power_state(dev, target_state);
18750 + pci_enable_wake(dev, target_state, false);
18756 +_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable)
18760 + err = pci_enable_wake(dev, PCI_D3cold, enable);
18764 + err = pci_enable_wake(dev, PCI_D3hot, enable);
18769 +#endif /* < 2.6.28 */
18771 +/*****************************************************************************/
18772 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) )
18773 +#endif /* < 2.6.29 */
18775 +/*****************************************************************************/
18776 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )
18777 +#endif /* < 2.6.30 */
18778 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/kcompat_ethtool.c linux-2.6.22-10/drivers/net/e1000e/kcompat_ethtool.c
18779 --- linux-2.6.22-0/drivers/net/e1000e/kcompat_ethtool.c 1970-01-01 01:00:00.000000000 +0100
18780 +++ linux-2.6.22-10/drivers/net/e1000e/kcompat_ethtool.c 2009-06-24 00:32:20.000000000 +0200
18782 +/*******************************************************************************
18784 + Intel PRO/1000 Linux driver
18785 + Copyright(c) 1999 - 2009 Intel Corporation.
18787 + This program is free software; you can redistribute it and/or modify it
18788 + under the terms and conditions of the GNU General Public License,
18789 + version 2, as published by the Free Software Foundation.
18791 + This program is distributed in the hope it will be useful, but WITHOUT
18792 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18793 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18796 + You should have received a copy of the GNU General Public License along with
18797 + this program; if not, write to the Free Software Foundation, Inc.,
18798 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18800 + The full GNU General Public License is included in this distribution in
18801 + the file called "COPYING".
18803 + Contact Information:
18804 + Linux NICS <linux.nics@intel.com>
18805 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18806 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18808 +*******************************************************************************/
18811 + * net/core/ethtool.c - Ethtool ioctl handler
18812 + * Copyright (c) 2003 Matthew Wilcox <matthew@wil.cx>
18814 + * This file is where we call all the ethtool_ops commands to get
18815 + * the information ethtool needs. We fall back to calling do_ioctl()
18816 + * for drivers which haven't been converted to ethtool_ops yet.
18818 + * It's GPL, stupid.
18820 + * Modification by sfeldma@pobox.com to work as backward compat
18821 + * solution for pre-ethtool_ops kernels.
18822 + * - copied struct ethtool_ops from ethtool.h
18823 + * - defined SET_ETHTOOL_OPS
18824 + * - put in some #ifndef NETIF_F_xxx wrappers
18825 + * - changes refs to dev->ethtool_ops to ethtool_ops
18826 + * - changed dev_ethtool to ethtool_ioctl
18827 + * - remove EXPORT_SYMBOL()s
18828 + * - added _kc_ prefix in built-in ethtool_op_xxx ops.
18831 +#include <linux/module.h>
18832 +#include <linux/types.h>
18833 +#include <linux/errno.h>
18834 +#include <linux/mii.h>
18835 +#include <linux/ethtool.h>
18836 +#include <linux/netdevice.h>
18837 +#include <asm/uaccess.h>
18839 +#include "kcompat.h"
18841 +#undef SUPPORTED_10000baseT_Full
18842 +#define SUPPORTED_10000baseT_Full (1 << 12)
18843 +#undef ADVERTISED_10000baseT_Full
18844 +#define ADVERTISED_10000baseT_Full (1 << 12)
18845 +#undef SPEED_10000
18846 +#define SPEED_10000 10000
18848 +#undef ethtool_ops
18849 +#define ethtool_ops _kc_ethtool_ops
18851 +struct _kc_ethtool_ops {
18852 + int (*get_settings)(struct net_device *, struct ethtool_cmd *);
18853 + int (*set_settings)(struct net_device *, struct ethtool_cmd *);
18854 + void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
18855 + int (*get_regs_len)(struct net_device *);
18856 + void (*get_regs)(struct net_device *, struct ethtool_regs *, void *);
18857 + void (*get_wol)(struct net_device *, struct ethtool_wolinfo *);
18858 + int (*set_wol)(struct net_device *, struct ethtool_wolinfo *);
18859 + u32 (*get_msglevel)(struct net_device *);
18860 + void (*set_msglevel)(struct net_device *, u32);
18861 + int (*nway_reset)(struct net_device *);
18862 + u32 (*get_link)(struct net_device *);
18863 + int (*get_eeprom_len)(struct net_device *);
18864 + int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);
18865 + int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);
18866 + int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *);
18867 + int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *);
18868 + void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *);
18869 + int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *);
18870 + void (*get_pauseparam)(struct net_device *,
18871 + struct ethtool_pauseparam*);
18872 + int (*set_pauseparam)(struct net_device *,
18873 + struct ethtool_pauseparam*);
18874 + u32 (*get_rx_csum)(struct net_device *);
18875 + int (*set_rx_csum)(struct net_device *, u32);
18876 + u32 (*get_tx_csum)(struct net_device *);
18877 + int (*set_tx_csum)(struct net_device *, u32);
18878 + u32 (*get_sg)(struct net_device *);
18879 + int (*set_sg)(struct net_device *, u32);
18880 + u32 (*get_tso)(struct net_device *);
18881 + int (*set_tso)(struct net_device *, u32);
18882 + int (*self_test_count)(struct net_device *);
18883 + void (*self_test)(struct net_device *, struct ethtool_test *, u64 *);
18884 + void (*get_strings)(struct net_device *, u32 stringset, u8 *);
18885 + int (*phys_id)(struct net_device *, u32);
18886 + int (*get_stats_count)(struct net_device *);
18887 + void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *,
18889 +} *ethtool_ops = NULL;
18891 +#undef SET_ETHTOOL_OPS
18892 +#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops))
18895 + * Some useful ethtool_ops methods that are device independent. If we find that
18896 + * all drivers want to do the same thing here, we can turn these into dev_()
18897 + * function calls.
18900 +#undef ethtool_op_get_link
18901 +#define ethtool_op_get_link _kc_ethtool_op_get_link
18902 +u32 _kc_ethtool_op_get_link(struct net_device *dev)
18904 + return netif_carrier_ok(dev) ? 1 : 0;
18907 +#undef ethtool_op_get_tx_csum
18908 +#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum
18909 +u32 _kc_ethtool_op_get_tx_csum(struct net_device *dev)
18911 +#ifdef NETIF_F_IP_CSUM
18912 + return (dev->features & NETIF_F_IP_CSUM) != 0;
18918 +#undef ethtool_op_set_tx_csum
18919 +#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum
18920 +int _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
18922 +#ifdef NETIF_F_IP_CSUM
18924 +#ifdef NETIF_F_IPV6_CSUM
18925 + dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
18927 + dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
18929 + dev->features |= NETIF_F_IP_CSUM;
18931 + dev->features &= ~NETIF_F_IP_CSUM;
18938 +#undef ethtool_op_get_sg
18939 +#define ethtool_op_get_sg _kc_ethtool_op_get_sg
18940 +u32 _kc_ethtool_op_get_sg(struct net_device *dev)
18943 + return (dev->features & NETIF_F_SG) != 0;
18949 +#undef ethtool_op_set_sg
18950 +#define ethtool_op_set_sg _kc_ethtool_op_set_sg
18951 +int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data)
18955 + dev->features |= NETIF_F_SG;
18957 + dev->features &= ~NETIF_F_SG;
18963 +#undef ethtool_op_get_tso
18964 +#define ethtool_op_get_tso _kc_ethtool_op_get_tso
18965 +u32 _kc_ethtool_op_get_tso(struct net_device *dev)
18967 +#ifdef NETIF_F_TSO
18968 + return (dev->features & NETIF_F_TSO) != 0;
18974 +#undef ethtool_op_set_tso
18975 +#define ethtool_op_set_tso _kc_ethtool_op_set_tso
18976 +int _kc_ethtool_op_set_tso(struct net_device *dev, u32 data)
18978 +#ifdef NETIF_F_TSO
18980 + dev->features |= NETIF_F_TSO;
18982 + dev->features &= ~NETIF_F_TSO;
18988 +/* Handlers for each ethtool command */
18990 +static int ethtool_get_settings(struct net_device *dev, void *useraddr)
18992 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
18995 + if (!ethtool_ops->get_settings)
18996 + return -EOPNOTSUPP;
18998 + err = ethtool_ops->get_settings(dev, &cmd);
19002 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
19007 +static int ethtool_set_settings(struct net_device *dev, void *useraddr)
19009 + struct ethtool_cmd cmd;
19011 + if (!ethtool_ops->set_settings)
19012 + return -EOPNOTSUPP;
19014 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
19017 + return ethtool_ops->set_settings(dev, &cmd);
19020 +static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr)
19022 + struct ethtool_drvinfo info;
19023 + struct ethtool_ops *ops = ethtool_ops;
19025 + if (!ops->get_drvinfo)
19026 + return -EOPNOTSUPP;
19028 + memset(&info, 0, sizeof(info));
19029 + info.cmd = ETHTOOL_GDRVINFO;
19030 + ops->get_drvinfo(dev, &info);
19032 + if (ops->self_test_count)
19033 + info.testinfo_len = ops->self_test_count(dev);
19034 + if (ops->get_stats_count)
19035 + info.n_stats = ops->get_stats_count(dev);
19036 + if (ops->get_regs_len)
19037 + info.regdump_len = ops->get_regs_len(dev);
19038 + if (ops->get_eeprom_len)
19039 + info.eedump_len = ops->get_eeprom_len(dev);
19041 + if (copy_to_user(useraddr, &info, sizeof(info)))
19046 +static int ethtool_get_regs(struct net_device *dev, char *useraddr)
19048 + struct ethtool_regs regs;
19049 + struct ethtool_ops *ops = ethtool_ops;
19053 + if (!ops->get_regs || !ops->get_regs_len)
19054 + return -EOPNOTSUPP;
19056 + if (copy_from_user(®s, useraddr, sizeof(regs)))
19059 + reglen = ops->get_regs_len(dev);
19060 + if (regs.len > reglen)
19061 + regs.len = reglen;
19063 + regbuf = kmalloc(reglen, GFP_USER);
19067 + ops->get_regs(dev, ®s, regbuf);
19070 + if (copy_to_user(useraddr, ®s, sizeof(regs)))
19072 + useraddr += offsetof(struct ethtool_regs, data);
19073 + if (copy_to_user(useraddr, regbuf, reglen))
19082 +static int ethtool_get_wol(struct net_device *dev, char *useraddr)
19084 + struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
19086 + if (!ethtool_ops->get_wol)
19087 + return -EOPNOTSUPP;
19089 + ethtool_ops->get_wol(dev, &wol);
19091 + if (copy_to_user(useraddr, &wol, sizeof(wol)))
19096 +static int ethtool_set_wol(struct net_device *dev, char *useraddr)
19098 + struct ethtool_wolinfo wol;
19100 + if (!ethtool_ops->set_wol)
19101 + return -EOPNOTSUPP;
19103 + if (copy_from_user(&wol, useraddr, sizeof(wol)))
19106 + return ethtool_ops->set_wol(dev, &wol);
19109 +static int ethtool_get_msglevel(struct net_device *dev, char *useraddr)
19111 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
19113 + if (!ethtool_ops->get_msglevel)
19114 + return -EOPNOTSUPP;
19116 + edata.data = ethtool_ops->get_msglevel(dev);
19118 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
19123 +static int ethtool_set_msglevel(struct net_device *dev, char *useraddr)
19125 + struct ethtool_value edata;
19127 + if (!ethtool_ops->set_msglevel)
19128 + return -EOPNOTSUPP;
19130 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
19133 + ethtool_ops->set_msglevel(dev, edata.data);
19137 +static int ethtool_nway_reset(struct net_device *dev)
19139 + if (!ethtool_ops->nway_reset)
19140 + return -EOPNOTSUPP;
19142 + return ethtool_ops->nway_reset(dev);
19145 +static int ethtool_get_link(struct net_device *dev, void *useraddr)
19147 + struct ethtool_value edata = { ETHTOOL_GLINK };
19149 + if (!ethtool_ops->get_link)
19150 + return -EOPNOTSUPP;
19152 + edata.data = ethtool_ops->get_link(dev);
19154 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
19159 +static int ethtool_get_eeprom(struct net_device *dev, void *useraddr)
19161 + struct ethtool_eeprom eeprom;
19162 + struct ethtool_ops *ops = ethtool_ops;
19166 + if (!ops->get_eeprom || !ops->get_eeprom_len)
19167 + return -EOPNOTSUPP;
19169 + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))
19172 + /* Check for wrap and zero */
19173 + if (eeprom.offset + eeprom.len <= eeprom.offset)
19176 + /* Check for exceeding total eeprom len */
19177 + if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev))
19180 + data = kmalloc(eeprom.len, GFP_USER);
19185 + if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len))
19188 + ret = ops->get_eeprom(dev, &eeprom, data);
19193 + if (copy_to_user(useraddr, &eeprom, sizeof(eeprom)))
19195 + if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len))
19204 +static int ethtool_set_eeprom(struct net_device *dev, void *useraddr)
19206 + struct ethtool_eeprom eeprom;
19207 + struct ethtool_ops *ops = ethtool_ops;
19211 + if (!ops->set_eeprom || !ops->get_eeprom_len)
19212 + return -EOPNOTSUPP;
19214 + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))
19217 + /* Check for wrap and zero */
19218 + if (eeprom.offset + eeprom.len <= eeprom.offset)
19221 + /* Check for exceeding total eeprom len */
19222 + if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev))
19225 + data = kmalloc(eeprom.len, GFP_USER);
19230 + if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len))
19233 + ret = ops->set_eeprom(dev, &eeprom, data);
19237 + if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len))
19245 +static int ethtool_get_coalesce(struct net_device *dev, void *useraddr)
19247 + struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE };
19249 + if (!ethtool_ops->get_coalesce)
19250 + return -EOPNOTSUPP;
19252 + ethtool_ops->get_coalesce(dev, &coalesce);
19254 + if (copy_to_user(useraddr, &coalesce, sizeof(coalesce)))
19259 +static int ethtool_set_coalesce(struct net_device *dev, void *useraddr)
19261 + struct ethtool_coalesce coalesce;
19263 + if (!ethtool_ops->get_coalesce)
19264 + return -EOPNOTSUPP;
19266 + if (copy_from_user(&coalesce, useraddr, sizeof(coalesce)))
19269 + return ethtool_ops->set_coalesce(dev, &coalesce);
19272 +static int ethtool_get_ringparam(struct net_device *dev, void *useraddr)
19274 + struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM };
19276 + if (!ethtool_ops->get_ringparam)
19277 + return -EOPNOTSUPP;
19279 + ethtool_ops->get_ringparam(dev, &ringparam);
19281 + if (copy_to_user(useraddr, &ringparam, sizeof(ringparam)))
19286 +static int ethtool_set_ringparam(struct net_device *dev, void *useraddr)
19288 + struct ethtool_ringparam ringparam;
19290 + if (!ethtool_ops->get_ringparam)
19291 + return -EOPNOTSUPP;
19293 + if (copy_from_user(&ringparam, useraddr, sizeof(ringparam)))
19296 + return ethtool_ops->set_ringparam(dev, &ringparam);
19299 +static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr)
19301 + struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM };
19303 + if (!ethtool_ops->get_pauseparam)
19304 + return -EOPNOTSUPP;
19306 + ethtool_ops->get_pauseparam(dev, &pauseparam);
19308 + if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam)))
19313 +static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr)
19315 + struct ethtool_pauseparam pauseparam;
19317 + if (!ethtool_ops->get_pauseparam)
19318 + return -EOPNOTSUPP;
19320 + if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam)))
19323 + return ethtool_ops->set_pauseparam(dev, &pauseparam);
19326 +static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr)
19328 + struct ethtool_value edata = { ETHTOOL_GRXCSUM };
19330 + if (!ethtool_ops->get_rx_csum)
19331 + return -EOPNOTSUPP;
19333 + edata.data = ethtool_ops->get_rx_csum(dev);
19335 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
19340 +static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr)
19342 + struct ethtool_value edata;
19344 + if (!ethtool_ops->set_rx_csum)
19345 + return -EOPNOTSUPP;
19347 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
19350 + ethtool_ops->set_rx_csum(dev, edata.data);
19354 +static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr)
19356 + struct ethtool_value edata = { ETHTOOL_GTXCSUM };
19358 + if (!ethtool_ops->get_tx_csum)
19359 + return -EOPNOTSUPP;
19361 + edata.data = ethtool_ops->get_tx_csum(dev);
19363 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
19368 +static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr)
19370 + struct ethtool_value edata;
19372 + if (!ethtool_ops->set_tx_csum)
19373 + return -EOPNOTSUPP;
19375 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
19378 + return ethtool_ops->set_tx_csum(dev, edata.data);
19381 +static int ethtool_get_sg(struct net_device *dev, char *useraddr)
19383 + struct ethtool_value edata = { ETHTOOL_GSG };
19385 + if (!ethtool_ops->get_sg)
19386 + return -EOPNOTSUPP;
19388 + edata.data = ethtool_ops->get_sg(dev);
19390 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
19395 +static int ethtool_set_sg(struct net_device *dev, char *useraddr)
19397 + struct ethtool_value edata;
19399 + if (!ethtool_ops->set_sg)
19400 + return -EOPNOTSUPP;
19402 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
19405 + return ethtool_ops->set_sg(dev, edata.data);
19408 +static int ethtool_get_tso(struct net_device *dev, char *useraddr)
19410 + struct ethtool_value edata = { ETHTOOL_GTSO };
19412 + if (!ethtool_ops->get_tso)
19413 + return -EOPNOTSUPP;
19415 + edata.data = ethtool_ops->get_tso(dev);
19417 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
19422 +static int ethtool_set_tso(struct net_device *dev, char *useraddr)
19424 + struct ethtool_value edata;
19426 + if (!ethtool_ops->set_tso)
19427 + return -EOPNOTSUPP;
19429 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
19432 + return ethtool_ops->set_tso(dev, edata.data);
19435 +static int ethtool_self_test(struct net_device *dev, char *useraddr)
19437 + struct ethtool_test test;
19438 + struct ethtool_ops *ops = ethtool_ops;
19442 + if (!ops->self_test || !ops->self_test_count)
19443 + return -EOPNOTSUPP;
19445 + if (copy_from_user(&test, useraddr, sizeof(test)))
19448 + test.len = ops->self_test_count(dev);
19449 + data = kmalloc(test.len * sizeof(u64), GFP_USER);
19453 + ops->self_test(dev, &test, data);
19456 + if (copy_to_user(useraddr, &test, sizeof(test)))
19458 + useraddr += sizeof(test);
19459 + if (copy_to_user(useraddr, data, test.len * sizeof(u64)))
19468 +static int ethtool_get_strings(struct net_device *dev, void *useraddr)
19470 + struct ethtool_gstrings gstrings;
19471 + struct ethtool_ops *ops = ethtool_ops;
19475 + if (!ops->get_strings)
19476 + return -EOPNOTSUPP;
19478 + if (copy_from_user(&gstrings, useraddr, sizeof(gstrings)))
19481 + switch (gstrings.string_set) {
19482 + case ETH_SS_TEST:
19483 + if (!ops->self_test_count)
19484 + return -EOPNOTSUPP;
19485 + gstrings.len = ops->self_test_count(dev);
19487 + case ETH_SS_STATS:
19488 + if (!ops->get_stats_count)
19489 + return -EOPNOTSUPP;
19490 + gstrings.len = ops->get_stats_count(dev);
19496 + data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER);
19500 + ops->get_strings(dev, gstrings.string_set, data);
19503 + if (copy_to_user(useraddr, &gstrings, sizeof(gstrings)))
19505 + useraddr += sizeof(gstrings);
19506 + if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN))
19515 +static int ethtool_phys_id(struct net_device *dev, void *useraddr)
19517 + struct ethtool_value id;
19519 + if (!ethtool_ops->phys_id)
19520 + return -EOPNOTSUPP;
19522 + if (copy_from_user(&id, useraddr, sizeof(id)))
19525 + return ethtool_ops->phys_id(dev, id.data);
19528 +static int ethtool_get_stats(struct net_device *dev, void *useraddr)
19530 + struct ethtool_stats stats;
19531 + struct ethtool_ops *ops = ethtool_ops;
19535 + if (!ops->get_ethtool_stats || !ops->get_stats_count)
19536 + return -EOPNOTSUPP;
19538 + if (copy_from_user(&stats, useraddr, sizeof(stats)))
19541 + stats.n_stats = ops->get_stats_count(dev);
19542 + data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER);
19546 + ops->get_ethtool_stats(dev, &stats, data);
19549 + if (copy_to_user(useraddr, &stats, sizeof(stats)))
19551 + useraddr += sizeof(stats);
19552 + if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64)))
19561 +/* The main entry point in this file. Called from net/core/dev.c */
19563 +#define ETHTOOL_OPS_COMPAT
19564 +int ethtool_ioctl(struct ifreq *ifr)
19566 + struct net_device *dev = __dev_get_by_name(ifr->ifr_name);
19567 + void *useraddr = (void *) ifr->ifr_data;
19571 + * XXX: This can be pushed down into the ethtool_* handlers that
19572 + * need it. Keep existing behavior for the moment.
19574 + if (!capable(CAP_NET_ADMIN))
19577 + if (!dev || !netif_device_present(dev))
19580 + if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
19583 + switch (ethcmd) {
19584 + case ETHTOOL_GSET:
19585 + return ethtool_get_settings(dev, useraddr);
19586 + case ETHTOOL_SSET:
19587 + return ethtool_set_settings(dev, useraddr);
19588 + case ETHTOOL_GDRVINFO:
19589 + return ethtool_get_drvinfo(dev, useraddr);
19590 + case ETHTOOL_GREGS:
19591 + return ethtool_get_regs(dev, useraddr);
19592 + case ETHTOOL_GWOL:
19593 + return ethtool_get_wol(dev, useraddr);
19594 + case ETHTOOL_SWOL:
19595 + return ethtool_set_wol(dev, useraddr);
19596 + case ETHTOOL_GMSGLVL:
19597 + return ethtool_get_msglevel(dev, useraddr);
19598 + case ETHTOOL_SMSGLVL:
19599 + return ethtool_set_msglevel(dev, useraddr);
19600 + case ETHTOOL_NWAY_RST:
19601 + return ethtool_nway_reset(dev);
19602 + case ETHTOOL_GLINK:
19603 + return ethtool_get_link(dev, useraddr);
19604 + case ETHTOOL_GEEPROM:
19605 + return ethtool_get_eeprom(dev, useraddr);
19606 + case ETHTOOL_SEEPROM:
19607 + return ethtool_set_eeprom(dev, useraddr);
19608 + case ETHTOOL_GCOALESCE:
19609 + return ethtool_get_coalesce(dev, useraddr);
19610 + case ETHTOOL_SCOALESCE:
19611 + return ethtool_set_coalesce(dev, useraddr);
19612 + case ETHTOOL_GRINGPARAM:
19613 + return ethtool_get_ringparam(dev, useraddr);
19614 + case ETHTOOL_SRINGPARAM:
19615 + return ethtool_set_ringparam(dev, useraddr);
19616 + case ETHTOOL_GPAUSEPARAM:
19617 + return ethtool_get_pauseparam(dev, useraddr);
19618 + case ETHTOOL_SPAUSEPARAM:
19619 + return ethtool_set_pauseparam(dev, useraddr);
19620 + case ETHTOOL_GRXCSUM:
19621 + return ethtool_get_rx_csum(dev, useraddr);
19622 + case ETHTOOL_SRXCSUM:
19623 + return ethtool_set_rx_csum(dev, useraddr);
19624 + case ETHTOOL_GTXCSUM:
19625 + return ethtool_get_tx_csum(dev, useraddr);
19626 + case ETHTOOL_STXCSUM:
19627 + return ethtool_set_tx_csum(dev, useraddr);
19628 + case ETHTOOL_GSG:
19629 + return ethtool_get_sg(dev, useraddr);
19630 + case ETHTOOL_SSG:
19631 + return ethtool_set_sg(dev, useraddr);
19632 + case ETHTOOL_GTSO:
19633 + return ethtool_get_tso(dev, useraddr);
19634 + case ETHTOOL_STSO:
19635 + return ethtool_set_tso(dev, useraddr);
19636 + case ETHTOOL_TEST:
19637 + return ethtool_self_test(dev, useraddr);
19638 + case ETHTOOL_GSTRINGS:
19639 + return ethtool_get_strings(dev, useraddr);
19640 + case ETHTOOL_PHYS_ID:
19641 + return ethtool_phys_id(dev, useraddr);
19642 + case ETHTOOL_GSTATS:
19643 + return ethtool_get_stats(dev, useraddr);
19645 + return -EOPNOTSUPP;
19648 + return -EOPNOTSUPP;
19651 +#define mii_if_info _kc_mii_if_info
19652 +struct _kc_mii_if_info {
19656 + int reg_num_mask;
19658 + unsigned int full_duplex : 1; /* is full duplex? */
19659 + unsigned int force_media : 1; /* is autoneg. disabled? */
19661 + struct net_device *dev;
19662 + int (*mdio_read) (struct net_device *dev, int phy_id, int location);
19663 + void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val);
19666 +struct ethtool_cmd;
19667 +struct mii_ioctl_data;
19669 +#undef mii_link_ok
19670 +#define mii_link_ok _kc_mii_link_ok
19671 +#undef mii_nway_restart
19672 +#define mii_nway_restart _kc_mii_nway_restart
19673 +#undef mii_ethtool_gset
19674 +#define mii_ethtool_gset _kc_mii_ethtool_gset
19675 +#undef mii_ethtool_sset
19676 +#define mii_ethtool_sset _kc_mii_ethtool_sset
19677 +#undef mii_check_link
19678 +#define mii_check_link _kc_mii_check_link
19679 +#undef generic_mii_ioctl
19680 +#define generic_mii_ioctl _kc_generic_mii_ioctl
19681 +extern int _kc_mii_link_ok (struct mii_if_info *mii);
19682 +extern int _kc_mii_nway_restart (struct mii_if_info *mii);
19683 +extern int _kc_mii_ethtool_gset(struct mii_if_info *mii,
19684 + struct ethtool_cmd *ecmd);
19685 +extern int _kc_mii_ethtool_sset(struct mii_if_info *mii,
19686 + struct ethtool_cmd *ecmd);
19687 +extern void _kc_mii_check_link (struct mii_if_info *mii);
19688 +extern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if,
19689 + struct mii_ioctl_data *mii_data, int cmd,
19690 + unsigned int *duplex_changed);
19693 +struct _kc_pci_dev_ext {
19694 + struct pci_dev *dev;
19695 + void *pci_drvdata;
19696 + struct pci_driver *driver;
19699 +struct _kc_net_dev_ext {
19700 + struct net_device *dev;
19701 + unsigned int carrier;
19705 +/**************************************/
19708 +int _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
19710 + struct net_device *dev = mii->dev;
19711 + u32 advert, bmcr, lpa, nego;
19713 + ecmd->supported =
19714 + (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
19715 + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
19716 + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
19718 + /* only supports twisted-pair */
19719 + ecmd->port = PORT_MII;
19721 + /* only supports internal transceiver */
19722 + ecmd->transceiver = XCVR_INTERNAL;
19724 + /* this isn't fully supported at higher layers */
19725 + ecmd->phy_address = mii->phy_id;
19727 + ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
19728 + advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
19729 + if (advert & ADVERTISE_10HALF)
19730 + ecmd->advertising |= ADVERTISED_10baseT_Half;
19731 + if (advert & ADVERTISE_10FULL)
19732 + ecmd->advertising |= ADVERTISED_10baseT_Full;
19733 + if (advert & ADVERTISE_100HALF)
19734 + ecmd->advertising |= ADVERTISED_100baseT_Half;
19735 + if (advert & ADVERTISE_100FULL)
19736 + ecmd->advertising |= ADVERTISED_100baseT_Full;
19738 + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
19739 + lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
19740 + if (bmcr & BMCR_ANENABLE) {
19741 + ecmd->advertising |= ADVERTISED_Autoneg;
19742 + ecmd->autoneg = AUTONEG_ENABLE;
19744 + nego = mii_nway_result(advert & lpa);
19745 + if (nego == LPA_100FULL || nego == LPA_100HALF)
19746 + ecmd->speed = SPEED_100;
19748 + ecmd->speed = SPEED_10;
19749 + if (nego == LPA_100FULL || nego == LPA_10FULL) {
19750 + ecmd->duplex = DUPLEX_FULL;
19751 + mii->full_duplex = 1;
19753 + ecmd->duplex = DUPLEX_HALF;
19754 + mii->full_duplex = 0;
19757 + ecmd->autoneg = AUTONEG_DISABLE;
19759 + ecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
19760 + ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
19763 + /* ignore maxtxpkt, maxrxpkt for now */
19768 +int _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
19770 + struct net_device *dev = mii->dev;
19772 + if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
19774 + if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
19776 + if (ecmd->port != PORT_MII)
19778 + if (ecmd->transceiver != XCVR_INTERNAL)
19780 + if (ecmd->phy_address != mii->phy_id)
19782 + if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
19785 + /* ignore supported, maxtxpkt, maxrxpkt */
19787 + if (ecmd->autoneg == AUTONEG_ENABLE) {
19788 + u32 bmcr, advert, tmp;
19790 + if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
19791 + ADVERTISED_10baseT_Full |
19792 + ADVERTISED_100baseT_Half |
19793 + ADVERTISED_100baseT_Full)) == 0)
19796 + /* advertise only what has been requested */
19797 + advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
19798 + tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
19799 + if (ADVERTISED_10baseT_Half)
19800 + tmp |= ADVERTISE_10HALF;
19801 + if (ADVERTISED_10baseT_Full)
19802 + tmp |= ADVERTISE_10FULL;
19803 + if (ADVERTISED_100baseT_Half)
19804 + tmp |= ADVERTISE_100HALF;
19805 + if (ADVERTISED_100baseT_Full)
19806 + tmp |= ADVERTISE_100FULL;
19807 + if (advert != tmp) {
19808 + mii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp);
19809 + mii->advertising = tmp;
19812 + /* turn on autonegotiation, and force a renegotiate */
19813 + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
19814 + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
19815 + mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);
19817 + mii->force_media = 0;
19821 + /* turn off auto negotiation, set speed and duplexity */
19822 + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
19823 + tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
19824 + if (ecmd->speed == SPEED_100)
19825 + tmp |= BMCR_SPEED100;
19826 + if (ecmd->duplex == DUPLEX_FULL) {
19827 + tmp |= BMCR_FULLDPLX;
19828 + mii->full_duplex = 1;
19830 + mii->full_duplex = 0;
19832 + mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp);
19834 + mii->force_media = 1;
19839 +int _kc_mii_link_ok (struct mii_if_info *mii)
19841 + /* first, a dummy read, needed to latch some MII phys */
19842 + mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
19843 + if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)
19848 +int _kc_mii_nway_restart (struct mii_if_info *mii)
19853 + /* if autoneg is off, it's an error */
19854 + bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR);
19856 + if (bmcr & BMCR_ANENABLE) {
19857 + bmcr |= BMCR_ANRESTART;
19858 + mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr);
19865 +void _kc_mii_check_link (struct mii_if_info *mii)
19867 + int cur_link = mii_link_ok(mii);
19868 + int prev_link = netif_carrier_ok(mii->dev);
19870 + if (cur_link && !prev_link)
19871 + netif_carrier_on(mii->dev);
19872 + else if (prev_link && !cur_link)
19873 + netif_carrier_off(mii->dev);
19876 +int _kc_generic_mii_ioctl(struct mii_if_info *mii_if,
19877 + struct mii_ioctl_data *mii_data, int cmd,
19878 + unsigned int *duplex_chg_out)
19881 + unsigned int duplex_changed = 0;
19883 + if (duplex_chg_out)
19884 + *duplex_chg_out = 0;
19886 + mii_data->phy_id &= mii_if->phy_id_mask;
19887 + mii_data->reg_num &= mii_if->reg_num_mask;
19890 + case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */
19891 + case SIOCGMIIPHY:
19892 + mii_data->phy_id = mii_if->phy_id;
19893 + /* fall through */
19895 + case SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */
19896 + case SIOCGMIIREG:
19897 + mii_data->val_out =
19898 + mii_if->mdio_read(mii_if->dev, mii_data->phy_id,
19899 + mii_data->reg_num);
19902 + case SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */
19903 + case SIOCSMIIREG: {
19904 + u16 val = mii_data->val_in;
19906 + if (!capable(CAP_NET_ADMIN))
19909 + if (mii_data->phy_id == mii_if->phy_id) {
19910 + switch(mii_data->reg_num) {
19912 + unsigned int new_duplex = 0;
19913 + if (val & (BMCR_RESET|BMCR_ANENABLE))
19914 + mii_if->force_media = 0;
19916 + mii_if->force_media = 1;
19917 + if (mii_if->force_media &&
19918 + (val & BMCR_FULLDPLX))
19920 + if (mii_if->full_duplex != new_duplex) {
19921 + duplex_changed = 1;
19922 + mii_if->full_duplex = new_duplex;
19926 + case MII_ADVERTISE:
19927 + mii_if->advertising = val;
19935 + mii_if->mdio_write(mii_if->dev, mii_data->phy_id,
19936 + mii_data->reg_num, val);
19941 + rc = -EOPNOTSUPP;
19945 + if ((rc == 0) && (duplex_chg_out) && (duplex_changed))
19946 + *duplex_chg_out = 1;
19951 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/kcompat.h linux-2.6.22-10/drivers/net/e1000e/kcompat.h
19952 --- linux-2.6.22-0/drivers/net/e1000e/kcompat.h 1970-01-01 01:00:00.000000000 +0100
19953 +++ linux-2.6.22-10/drivers/net/e1000e/kcompat.h 2009-06-24 00:32:20.000000000 +0200
19955 +/*******************************************************************************
19957 + Intel PRO/1000 Linux driver
19958 + Copyright(c) 1999 - 2009 Intel Corporation.
19960 + This program is free software; you can redistribute it and/or modify it
19961 + under the terms and conditions of the GNU General Public License,
19962 + version 2, as published by the Free Software Foundation.
19964 + This program is distributed in the hope it will be useful, but WITHOUT
19965 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19966 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19969 + You should have received a copy of the GNU General Public License along with
19970 + this program; if not, write to the Free Software Foundation, Inc.,
19971 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19973 + The full GNU General Public License is included in this distribution in
19974 + the file called "COPYING".
19976 + Contact Information:
19977 + Linux NICS <linux.nics@intel.com>
19978 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19979 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19981 +*******************************************************************************/
19983 +#ifndef _KCOMPAT_H_
19984 +#define _KCOMPAT_H_
19986 +#include <linux/version.h>
19987 +#include <linux/init.h>
19988 +#include <linux/types.h>
19989 +#include <linux/errno.h>
19990 +#include <linux/module.h>
19991 +#include <linux/pci.h>
19992 +#include <linux/netdevice.h>
19993 +#include <linux/etherdevice.h>
19994 +#include <linux/skbuff.h>
19995 +#include <linux/ioport.h>
19996 +#include <linux/slab.h>
19997 +#include <linux/list.h>
19998 +#include <linux/delay.h>
19999 +#include <linux/sched.h>
20000 +#include <linux/in.h>
20001 +#include <linux/ip.h>
20002 +#include <linux/udp.h>
20003 +#include <linux/mii.h>
20004 +#include <asm/io.h>
20006 +/* NAPI enable/disable flags here */
20008 +#ifdef E1000E_NO_NAPI
20012 +#define adapter_struct e1000_adapter
20013 +#define CONFIG_E1000E_MSIX
20015 +/* and finally set defines so that the code sees the changes */
20017 +#ifndef CONFIG_E1000E_NAPI
20018 +#define CONFIG_E1000E_NAPI
20021 +#undef CONFIG_E1000E_NAPI
20024 +/* MSI compatibility code for all kernels and drivers */
20025 +#ifdef DISABLE_PCI_MSI
20026 +#undef CONFIG_PCI_MSI
20028 +#ifndef CONFIG_PCI_MSI
20029 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )
20030 +struct msix_entry {
20031 + u16 vector; /* kernel uses to write allocated vector */
20032 + u16 entry; /* driver uses to specify entry, OS writes */
20035 +#define pci_enable_msi(a) -ENOTSUPP
20036 +#define pci_disable_msi(a) do {} while (0)
20037 +#define pci_enable_msix(a, b, c) -ENOTSUPP
20038 +#define pci_disable_msix(a) do {} while (0)
20039 +#define msi_remove_pci_irq_vectors(a) do {} while (0)
20040 +#endif /* CONFIG_PCI_MSI */
20045 +#ifdef DISABLE_NET_POLL_CONTROLLER
20046 +#undef CONFIG_NET_POLL_CONTROLLER
20049 +#ifndef PMSG_SUSPEND
20050 +#define PMSG_SUSPEND 3
20053 +/* generic boolean compatibility */
20057 +#define FALSE false
20058 +#ifdef GCC_VERSION
20059 +#if ( GCC_VERSION < 3000 )
20060 +#define _Bool char
20064 +#define bool _Bool
20070 +#ifndef module_param
20071 +#define module_param(v,t,p) MODULE_PARM(v, "i");
20074 +#ifndef DMA_64BIT_MASK
20075 +#define DMA_64BIT_MASK 0xffffffffffffffffULL
20078 +#ifndef DMA_32BIT_MASK
20079 +#define DMA_32BIT_MASK 0x00000000ffffffffULL
20082 +#ifndef PCI_CAP_ID_EXP
20083 +#define PCI_CAP_ID_EXP 0x10
20086 +#ifndef PCIE_LINK_STATE_L0S
20087 +#define PCIE_LINK_STATE_L0S 1
20091 +#ifdef CONFIG_IA64
20092 +#define mmiowb() asm volatile ("mf.a" ::: "memory")
20098 +#ifndef SET_NETDEV_DEV
20099 +#define SET_NETDEV_DEV(net, pdev)
20102 +#ifndef HAVE_FREE_NETDEV
20103 +#define free_netdev(x) kfree(x)
20106 +#ifdef HAVE_POLL_CONTROLLER
20107 +#define CONFIG_NET_POLL_CONTROLLER
20110 +#ifndef NETDEV_TX_OK
20111 +#define NETDEV_TX_OK 0
20114 +#ifndef NETDEV_TX_BUSY
20115 +#define NETDEV_TX_BUSY 1
20118 +#ifndef NETDEV_TX_LOCKED
20119 +#define NETDEV_TX_LOCKED -1
20122 +#ifndef SKB_DATAREF_SHIFT
20123 +/* if we do not have the infrastructure to detect if skb_header is cloned
20124 + just return false in all cases */
20125 +#define skb_header_cloned(x) 0
20128 +#ifndef NETIF_F_GSO
20129 +#define gso_size tso_size
20130 +#define gso_segs tso_segs
20133 +#ifndef NETIF_F_GRO
20134 +#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \
20135 + vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan)
20136 +#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb)
20139 +#ifndef CHECKSUM_PARTIAL
20140 +#define CHECKSUM_PARTIAL CHECKSUM_HW
20141 +#define CHECKSUM_COMPLETE CHECKSUM_HW
20144 +#ifndef __read_mostly
20145 +#define __read_mostly
20148 +#ifndef HAVE_NETIF_MSG
20149 +#define HAVE_NETIF_MSG 1
20151 + NETIF_MSG_DRV = 0x0001,
20152 + NETIF_MSG_PROBE = 0x0002,
20153 + NETIF_MSG_LINK = 0x0004,
20154 + NETIF_MSG_TIMER = 0x0008,
20155 + NETIF_MSG_IFDOWN = 0x0010,
20156 + NETIF_MSG_IFUP = 0x0020,
20157 + NETIF_MSG_RX_ERR = 0x0040,
20158 + NETIF_MSG_TX_ERR = 0x0080,
20159 + NETIF_MSG_TX_QUEUED = 0x0100,
20160 + NETIF_MSG_INTR = 0x0200,
20161 + NETIF_MSG_TX_DONE = 0x0400,
20162 + NETIF_MSG_RX_STATUS = 0x0800,
20163 + NETIF_MSG_PKTDATA = 0x1000,
20164 + NETIF_MSG_HW = 0x2000,
20165 + NETIF_MSG_WOL = 0x4000,
20169 +#define NETIF_MSG_HW 0x2000
20170 +#define NETIF_MSG_WOL 0x4000
20171 +#endif /* HAVE_NETIF_MSG */
20174 +#define MII_RESV1 0x17 /* Reserved... */
20178 +#define unlikely(_x) _x
20179 +#define likely(_x) _x
20183 +#define WARN_ON(x)
20186 +#ifndef PCI_DEVICE
20187 +#define PCI_DEVICE(vend,dev) \
20188 + .vendor = (vend), .device = (dev), \
20189 + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
20192 +#ifndef num_online_cpus
20193 +#define num_online_cpus() smp_num_cpus
20196 +#ifndef _LINUX_RANDOM_H
20197 +#include <linux/random.h>
20200 +#ifndef DECLARE_BITMAP
20201 +#ifndef BITS_TO_LONGS
20202 +#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG)
20204 +#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)]
20208 +#define VLAN_HLEN 4
20211 +#ifndef VLAN_ETH_HLEN
20212 +#define VLAN_ETH_HLEN 18
20215 +#ifndef VLAN_ETH_FRAME_LEN
20216 +#define VLAN_ETH_FRAME_LEN 1518
20219 +#ifndef DCA_GET_TAG_TWO_ARGS
20220 +#define dca3_get_tag(a,b) dca_get_tag(b)
20224 +/*****************************************************************************/
20225 +/* Installations with ethtool version without eeprom, adapter id, or statistics
20228 +#ifndef ETH_GSTRING_LEN
20229 +#define ETH_GSTRING_LEN 32
20232 +#ifndef ETHTOOL_GSTATS
20233 +#define ETHTOOL_GSTATS 0x1d
20234 +#undef ethtool_drvinfo
20235 +#define ethtool_drvinfo k_ethtool_drvinfo
20236 +struct k_ethtool_drvinfo {
20239 + char version[32];
20240 + char fw_version[32];
20241 + char bus_info[32];
20242 + char reserved1[32];
20243 + char reserved2[16];
20245 + u32 testinfo_len;
20250 +struct ethtool_stats {
20255 +#endif /* ETHTOOL_GSTATS */
20257 +#ifndef ETHTOOL_PHYS_ID
20258 +#define ETHTOOL_PHYS_ID 0x1c
20259 +#endif /* ETHTOOL_PHYS_ID */
20261 +#ifndef ETHTOOL_GSTRINGS
20262 +#define ETHTOOL_GSTRINGS 0x1b
20263 +enum ethtool_stringset {
20267 +struct ethtool_gstrings {
20268 + u32 cmd; /* ETHTOOL_GSTRINGS */
20269 + u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/
20270 + u32 len; /* number of strings in the string set */
20273 +#endif /* ETHTOOL_GSTRINGS */
20275 +#ifndef ETHTOOL_TEST
20276 +#define ETHTOOL_TEST 0x1a
20277 +enum ethtool_test_flags {
20278 + ETH_TEST_FL_OFFLINE = (1 << 0),
20279 + ETH_TEST_FL_FAILED = (1 << 1),
20281 +struct ethtool_test {
20288 +#endif /* ETHTOOL_TEST */
20290 +#ifndef ETHTOOL_GEEPROM
20291 +#define ETHTOOL_GEEPROM 0xb
20292 +#undef ETHTOOL_GREGS
20293 +struct ethtool_eeprom {
20301 +struct ethtool_value {
20305 +#endif /* ETHTOOL_GEEPROM */
20307 +#ifndef ETHTOOL_GLINK
20308 +#define ETHTOOL_GLINK 0xa
20309 +#endif /* ETHTOOL_GLINK */
20311 +#ifndef ETHTOOL_GREGS
20312 +#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */
20313 +#define ethtool_regs _kc_ethtool_regs
20314 +/* for passing big chunks of data */
20315 +struct _kc_ethtool_regs {
20317 + u32 version; /* driver-specific, indicates different chips/revs */
20318 + u32 len; /* bytes */
20321 +#endif /* ETHTOOL_GREGS */
20323 +#ifndef ETHTOOL_GMSGLVL
20324 +#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */
20326 +#ifndef ETHTOOL_SMSGLVL
20327 +#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */
20329 +#ifndef ETHTOOL_NWAY_RST
20330 +#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */
20332 +#ifndef ETHTOOL_GLINK
20333 +#define ETHTOOL_GLINK 0x0000000a /* Get link status */
20335 +#ifndef ETHTOOL_GEEPROM
20336 +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */
20338 +#ifndef ETHTOOL_SEEPROM
20339 +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */
20341 +#ifndef ETHTOOL_GCOALESCE
20342 +#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */
20343 +/* for configuring coalescing parameters of chip */
20344 +#define ethtool_coalesce _kc_ethtool_coalesce
20345 +struct _kc_ethtool_coalesce {
20346 + u32 cmd; /* ETHTOOL_{G,S}COALESCE */
20348 + /* How many usecs to delay an RX interrupt after
20349 + * a packet arrives. If 0, only rx_max_coalesced_frames
20352 + u32 rx_coalesce_usecs;
20354 + /* How many packets to delay an RX interrupt after
20355 + * a packet arrives. If 0, only rx_coalesce_usecs is
20356 + * used. It is illegal to set both usecs and max frames
20357 + * to zero as this would cause RX interrupts to never be
20360 + u32 rx_max_coalesced_frames;
20362 + /* Same as above two parameters, except that these values
20363 + * apply while an IRQ is being serviced by the host. Not
20364 + * all cards support this feature and the values are ignored
20367 + u32 rx_coalesce_usecs_irq;
20368 + u32 rx_max_coalesced_frames_irq;
20370 + /* How many usecs to delay a TX interrupt after
20371 + * a packet is sent. If 0, only tx_max_coalesced_frames
20374 + u32 tx_coalesce_usecs;
20376 + /* How many packets to delay a TX interrupt after
20377 + * a packet is sent. If 0, only tx_coalesce_usecs is
20378 + * used. It is illegal to set both usecs and max frames
20379 + * to zero as this would cause TX interrupts to never be
20382 + u32 tx_max_coalesced_frames;
20384 + /* Same as above two parameters, except that these values
20385 + * apply while an IRQ is being serviced by the host. Not
20386 + * all cards support this feature and the values are ignored
20389 + u32 tx_coalesce_usecs_irq;
20390 + u32 tx_max_coalesced_frames_irq;
20392 + /* How many usecs to delay in-memory statistics
20393 + * block updates. Some drivers do not have an in-memory
20394 + * statistic block, and in such cases this value is ignored.
20395 + * This value must not be zero.
20397 + u32 stats_block_coalesce_usecs;
20399 + /* Adaptive RX/TX coalescing is an algorithm implemented by
20400 + * some drivers to improve latency under low packet rates and
20401 + * improve throughput under high packet rates. Some drivers
20402 + * only implement one of RX or TX adaptive coalescing. Anything
20403 + * not implemented by the driver causes these values to be
20404 + * silently ignored.
20406 + u32 use_adaptive_rx_coalesce;
20407 + u32 use_adaptive_tx_coalesce;
20409 + /* When the packet rate (measured in packets per second)
20410 + * is below pkt_rate_low, the {rx,tx}_*_low parameters are
20413 + u32 pkt_rate_low;
20414 + u32 rx_coalesce_usecs_low;
20415 + u32 rx_max_coalesced_frames_low;
20416 + u32 tx_coalesce_usecs_low;
20417 + u32 tx_max_coalesced_frames_low;
20419 + /* When the packet rate is below pkt_rate_high but above
20420 + * pkt_rate_low (both measured in packets per second) the
20421 + * normal {rx,tx}_* coalescing parameters are used.
20424 + /* When the packet rate is (measured in packets per second)
20425 + * is above pkt_rate_high, the {rx,tx}_*_high parameters are
20428 + u32 pkt_rate_high;
20429 + u32 rx_coalesce_usecs_high;
20430 + u32 rx_max_coalesced_frames_high;
20431 + u32 tx_coalesce_usecs_high;
20432 + u32 tx_max_coalesced_frames_high;
20434 + /* How often to do adaptive coalescing packet rate sampling,
20435 + * measured in seconds. Must not be zero.
20437 + u32 rate_sample_interval;
20439 +#endif /* ETHTOOL_GCOALESCE */
20441 +#ifndef ETHTOOL_SCOALESCE
20442 +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */
20444 +#ifndef ETHTOOL_GRINGPARAM
20445 +#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */
20446 +/* for configuring RX/TX ring parameters */
20447 +#define ethtool_ringparam _kc_ethtool_ringparam
20448 +struct _kc_ethtool_ringparam {
20449 + u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */
20451 + /* Read only attributes. These indicate the maximum number
20452 + * of pending RX/TX ring entries the driver will allow the
20455 + u32 rx_max_pending;
20456 + u32 rx_mini_max_pending;
20457 + u32 rx_jumbo_max_pending;
20458 + u32 tx_max_pending;
20460 + /* Values changeable by the user. The valid values are
20461 + * in the range 1 to the "*_max_pending" counterpart above.
20464 + u32 rx_mini_pending;
20465 + u32 rx_jumbo_pending;
20468 +#endif /* ETHTOOL_GRINGPARAM */
20470 +#ifndef ETHTOOL_SRINGPARAM
20471 +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */
20473 +#ifndef ETHTOOL_GPAUSEPARAM
20474 +#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */
20475 +/* for configuring link flow control parameters */
20476 +#define ethtool_pauseparam _kc_ethtool_pauseparam
20477 +struct _kc_ethtool_pauseparam {
20478 + u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */
20480 + /* If the link is being auto-negotiated (via ethtool_cmd.autoneg
20481 + * being true) the user may set 'autoneg' here non-zero to have the
20482 + * pause parameters be auto-negotiated too. In such a case, the
20483 + * {rx,tx}_pause values below determine what capabilities are
20486 + * If 'autoneg' is zero or the link is not being auto-negotiated,
20487 + * then {rx,tx}_pause force the driver to use/not-use pause
20494 +#endif /* ETHTOOL_GPAUSEPARAM */
20496 +#ifndef ETHTOOL_SPAUSEPARAM
20497 +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */
20499 +#ifndef ETHTOOL_GRXCSUM
20500 +#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */
20502 +#ifndef ETHTOOL_SRXCSUM
20503 +#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */
20505 +#ifndef ETHTOOL_GTXCSUM
20506 +#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */
20508 +#ifndef ETHTOOL_STXCSUM
20509 +#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */
20511 +#ifndef ETHTOOL_GSG
20512 +#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable
20513 + * (ethtool_value) */
20515 +#ifndef ETHTOOL_SSG
20516 +#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable
20517 + * (ethtool_value). */
20519 +#ifndef ETHTOOL_TEST
20520 +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */
20522 +#ifndef ETHTOOL_GSTRINGS
20523 +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */
20525 +#ifndef ETHTOOL_PHYS_ID
20526 +#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */
20528 +#ifndef ETHTOOL_GSTATS
20529 +#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */
20531 +#ifndef ETHTOOL_GTSO
20532 +#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
20534 +#ifndef ETHTOOL_STSO
20535 +#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
20538 +#ifndef ETHTOOL_BUSINFO_LEN
20539 +#define ETHTOOL_BUSINFO_LEN 32
20542 +/*****************************************************************************/
20543 +/* 2.4.3 => 2.4.0 */
20544 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )
20546 +/**************************************/
20547 +/* PCI DRIVER API */
20549 +#ifndef pci_set_dma_mask
20550 +#define pci_set_dma_mask _kc_pci_set_dma_mask
20551 +extern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask);
20554 +#ifndef pci_request_regions
20555 +#define pci_request_regions _kc_pci_request_regions
20556 +extern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name);
20559 +#ifndef pci_release_regions
20560 +#define pci_release_regions _kc_pci_release_regions
20561 +extern void _kc_pci_release_regions(struct pci_dev *pdev);
20564 +/**************************************/
20565 +/* NETWORK DRIVER API */
20567 +#ifndef alloc_etherdev
20568 +#define alloc_etherdev _kc_alloc_etherdev
20569 +extern struct net_device * _kc_alloc_etherdev(int sizeof_priv);
20572 +#ifndef is_valid_ether_addr
20573 +#define is_valid_ether_addr _kc_is_valid_ether_addr
20574 +extern int _kc_is_valid_ether_addr(u8 *addr);
20577 +/**************************************/
20578 +/* MISCELLANEOUS */
20580 +#ifndef INIT_TQUEUE
20581 +#define INIT_TQUEUE(_tq, _routine, _data) \
20583 + INIT_LIST_HEAD(&(_tq)->list); \
20584 + (_tq)->sync = 0; \
20585 + (_tq)->routine = _routine; \
20586 + (_tq)->data = _data; \
20590 +#endif /* 2.4.3 => 2.4.0 */
20592 +/*****************************************************************************/
20593 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) )
20594 +/* Generic MII registers. */
20595 +#define MII_BMCR 0x00 /* Basic mode control register */
20596 +#define MII_BMSR 0x01 /* Basic mode status register */
20597 +#define MII_PHYSID1 0x02 /* PHYS ID 1 */
20598 +#define MII_PHYSID2 0x03 /* PHYS ID 2 */
20599 +#define MII_ADVERTISE 0x04 /* Advertisement control reg */
20600 +#define MII_LPA 0x05 /* Link partner ability reg */
20601 +#define MII_EXPANSION 0x06 /* Expansion register */
20602 +/* Basic mode control register. */
20603 +#define BMCR_FULLDPLX 0x0100 /* Full duplex */
20604 +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
20605 +/* Basic mode status register. */
20606 +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
20607 +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
20608 +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
20609 +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
20610 +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
20611 +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
20612 +/* Advertisement control register. */
20613 +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
20614 +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
20615 +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
20616 +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
20617 +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
20618 +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
20619 + ADVERTISE_100HALF | ADVERTISE_100FULL)
20620 +/* Expansion register for auto-negotiation. */
20621 +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
20624 +/*****************************************************************************/
20625 +/* 2.4.6 => 2.4.3 */
20626 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )
20628 +#ifndef pci_set_power_state
20629 +#define pci_set_power_state _kc_pci_set_power_state
20630 +extern int _kc_pci_set_power_state(struct pci_dev *dev, int state);
20633 +#ifndef pci_enable_wake
20634 +#define pci_enable_wake _kc_pci_enable_wake
20635 +extern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable);
20638 +#ifndef pci_disable_device
20639 +#define pci_disable_device _kc_pci_disable_device
20640 +extern void _kc_pci_disable_device(struct pci_dev *pdev);
20643 +/* PCI PM entry point syntax changed, so don't support suspend/resume */
20646 +#endif /* 2.4.6 => 2.4.3 */
20648 +#ifndef HAVE_PCI_SET_MWI
20649 +#define pci_set_mwi(X) pci_write_config_word(X, \
20650 + PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \
20651 + PCI_COMMAND_INVALIDATE);
20652 +#define pci_clear_mwi(X) pci_write_config_word(X, \
20653 + PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \
20654 + ~PCI_COMMAND_INVALIDATE);
20657 +/*****************************************************************************/
20658 +/* 2.4.10 => 2.4.9 */
20659 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) )
20661 +/**************************************/
20664 +#ifndef MODULE_LICENSE
20665 + #define MODULE_LICENSE(X)
20668 +/**************************************/
20672 +#define min(x,y) ({ \
20673 + const typeof(x) _x = (x); \
20674 + const typeof(y) _y = (y); \
20675 + (void) (&_x == &_y); \
20676 + _x < _y ? _x : _y; })
20679 +#define max(x,y) ({ \
20680 + const typeof(x) _x = (x); \
20681 + const typeof(y) _y = (y); \
20682 + (void) (&_x == &_y); \
20683 + _x > _y ? _x : _y; })
20685 +#define min_t(type,x,y) ({ \
20688 + _x < _y ? _x : _y; })
20690 +#define max_t(type,x,y) ({ \
20693 + _x > _y ? _x : _y; })
20695 +#ifndef list_for_each_safe
20696 +#define list_for_each_safe(pos, n, head) \
20697 + for (pos = (head)->next, n = pos->next; pos != (head); \
20698 + pos = n, n = pos->next)
20701 +#endif /* 2.4.10 -> 2.4.6 */
20704 +/*****************************************************************************/
20705 +/* 2.4.13 => 2.4.10 */
20706 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )
20708 +/**************************************/
20709 +/* PCI DMA MAPPING */
20711 +#ifndef virt_to_page
20712 + #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT))
20715 +#ifndef pci_map_page
20716 +#define pci_map_page _kc_pci_map_page
20717 +extern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction);
20720 +#ifndef pci_unmap_page
20721 +#define pci_unmap_page _kc_pci_unmap_page
20722 +extern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction);
20725 +/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */
20727 +#undef DMA_32BIT_MASK
20728 +#define DMA_32BIT_MASK 0xffffffff
20729 +#undef DMA_64BIT_MASK
20730 +#define DMA_64BIT_MASK 0xffffffff
20732 +/**************************************/
20736 +#define cpu_relax() rep_nop()
20739 +#endif /* 2.4.13 => 2.4.10 */
20741 +/*****************************************************************************/
20742 +/* 2.4.17 => 2.4.12 */
20743 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) )
20745 +#ifndef __devexit_p
20746 + #define __devexit_p(x) &(x)
20749 +#endif /* 2.4.17 => 2.4.13 */
20751 +/*****************************************************************************/
20752 +/* 2.4.20 => 2.4.19 */
20753 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) )
20755 +/* we won't support NAPI on less than 2.4.20 */
20757 +#undef CONFIG_E1000E_NAPI
20760 +#endif /* 2.4.20 => 2.4.19 */
20762 +/*****************************************************************************/
20764 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,21) )
20765 +#define skb_pad(x,y) _kc_skb_pad(x, y)
20766 +struct sk_buff * _kc_skb_pad(struct sk_buff *skb, int pad);
20767 +#endif /* < 2.4.21 */
20769 +/*****************************************************************************/
20770 +/* 2.4.22 => 2.4.17 */
20771 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )
20772 +#define pci_name(x) ((x)->slot_name)
20775 +/*****************************************************************************/
20776 +/*****************************************************************************/
20777 +/* 2.4.23 => 2.4.22 */
20778 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) )
20779 +/*****************************************************************************/
20781 +#ifndef netif_poll_disable
20782 +#define netif_poll_disable(x) _kc_netif_poll_disable(x)
20783 +static inline void _kc_netif_poll_disable(struct net_device *netdev)
20785 + while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) {
20787 + current->state = TASK_INTERRUPTIBLE;
20788 + schedule_timeout(1);
20793 +#ifndef netif_poll_enable
20794 +#define netif_poll_enable(x) _kc_netif_poll_enable(x)
20795 +static inline void _kc_netif_poll_enable(struct net_device *netdev)
20797 + clear_bit(__LINK_STATE_RX_SCHED, &netdev->state);
20801 +#ifndef netif_tx_disable
20802 +#define netif_tx_disable(x) _kc_netif_tx_disable(x)
20803 +static inline void _kc_netif_tx_disable(struct net_device *dev)
20805 + spin_lock_bh(&dev->xmit_lock);
20806 + netif_stop_queue(dev);
20807 + spin_unlock_bh(&dev->xmit_lock);
20810 +#endif /* 2.4.23 => 2.4.22 */
20812 +/*****************************************************************************/
20813 +/* 2.6.4 => 2.6.0 */
20814 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \
20815 + ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
20816 + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) )
20817 +#define ETHTOOL_OPS_COMPAT
20818 +#endif /* 2.6.4 => 2.6.0 */
20820 +/*****************************************************************************/
20821 +/* 2.5.71 => 2.4.x */
20822 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) )
20823 +#include <net/sock.h>
20824 +#define sk_protocol protocol
20826 +#define pci_get_device pci_find_device
20827 +#endif /* 2.5.70 => 2.4.x */
20829 +/*****************************************************************************/
20830 +/* < 2.4.27 or 2.6.0 <= 2.6.5 */
20831 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \
20832 + ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
20833 + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) )
20835 +#ifndef netif_msg_init
20836 +#define netif_msg_init _kc_netif_msg_init
20837 +static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits)
20839 + /* use default */
20840 + if (debug_value < 0 || debug_value >= (sizeof(u32) * 8))
20841 + return default_msg_enable_bits;
20842 + if (debug_value == 0) /* no output */
20844 + /* set low N bits */
20845 + return (1 << debug_value) -1;
20849 +#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */
20850 +/*****************************************************************************/
20851 +#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \
20852 + (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \
20853 + ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )))
20854 +#define netdev_priv(x) x->priv
20857 +/*****************************************************************************/
20859 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) )
20860 +#undef pci_register_driver
20861 +#define pci_register_driver pci_module_init
20863 +#define dev_err(__unused_dev, format, arg...) \
20864 + printk(KERN_ERR "%s: " format, pci_name(adapter->pdev) , ## arg)
20865 +#define dev_warn(__unused_dev, format, arg...) \
20866 + printk(KERN_WARNING "%s: " format, pci_name(pdev) , ## arg)
20868 +/* hlist_* code - double linked lists */
20869 +struct hlist_head {
20870 + struct hlist_node *first;
20873 +struct hlist_node {
20874 + struct hlist_node *next, **pprev;
20877 +static inline void __hlist_del(struct hlist_node *n)
20879 + struct hlist_node *next = n->next;
20880 + struct hlist_node **pprev = n->pprev;
20883 + next->pprev = pprev;
20886 +static inline void hlist_del(struct hlist_node *n)
20893 +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
20895 + struct hlist_node *first = h->first;
20898 + first->pprev = &n->next;
20900 + n->pprev = &h->first;
20903 +static inline int hlist_empty(const struct hlist_head *h)
20905 + return !h->first;
20907 +#define HLIST_HEAD_INIT { .first = NULL }
20908 +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL }
20909 +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
20910 +static inline void INIT_HLIST_NODE(struct hlist_node *h)
20915 +#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
20917 +#define hlist_for_each_entry(tpos, pos, head, member) \
20918 + for (pos = (head)->first; \
20919 + pos && ({ prefetch(pos->next); 1;}) && \
20920 + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
20923 +#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \
20924 + for (pos = (head)->first; \
20925 + pos && ({ n = pos->next; 1; }) && \
20926 + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
20929 +/* we ignore GFP here */
20930 +#define dma_alloc_coherent(dv, sz, dma, gfp) \
20931 + pci_alloc_consistent(pdev, (sz), (dma))
20932 +#define dma_free_coherent(dv, sz, addr, dma_addr) \
20933 + pci_free_consistent(pdev, (sz), (addr), (dma_addr))
20935 +#ifndef might_sleep
20936 +#define might_sleep()
20939 +#endif /* <= 2.5.0 */
20941 +/*****************************************************************************/
20942 +/* 2.5.28 => 2.4.23 */
20943 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )
20945 +static inline void _kc_synchronize_irq(void)
20947 + synchronize_irq();
20949 +#undef synchronize_irq
20950 +#define synchronize_irq(X) _kc_synchronize_irq()
20952 +#include <linux/tqueue.h>
20953 +#define work_struct tq_struct
20955 +#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a)
20956 +#undef container_of
20957 +#define container_of list_entry
20958 +#define schedule_work schedule_task
20959 +#define flush_scheduled_work flush_scheduled_tasks
20960 +#define cancel_work_sync(x) flush_scheduled_work()
20962 +#endif /* 2.5.28 => 2.4.17 */
20964 +/*****************************************************************************/
20965 +/* 2.6.0 => 2.5.28 */
20966 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
20967 +#define MODULE_INFO(version, _version)
20968 +#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
20969 +#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1
20971 +#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT
20972 +#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1
20975 +#define pci_set_consistent_dma_mask(dev,mask) 1
20978 +#define dev_put(dev) __dev_put(dev)
20980 +#ifndef skb_fill_page_desc
20981 +#define skb_fill_page_desc _kc_skb_fill_page_desc
20982 +extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size);
20986 +#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1))
20988 +#ifndef page_count
20989 +#define page_count(p) atomic_read(&(p)->count)
20992 +/* find_first_bit and find_next bit are not defined for most
20993 + * 2.4 kernels (except for the redhat 2.4.21 kernels
20995 +#include <linux/bitops.h>
20996 +#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
20997 +#undef find_next_bit
20998 +#define find_next_bit _kc_find_next_bit
20999 +extern unsigned long _kc_find_next_bit(const unsigned long *addr,
21000 + unsigned long size,
21001 + unsigned long offset);
21002 +#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
21004 +#endif /* 2.6.0 => 2.5.28 */
21006 +/*****************************************************************************/
21007 +/* 2.6.4 => 2.6.0 */
21008 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )
21009 +#define MODULE_VERSION(_version) MODULE_INFO(version, _version)
21010 +#endif /* 2.6.4 => 2.6.0 */
21012 +/*****************************************************************************/
21013 +/* 2.6.5 => 2.6.0 */
21014 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )
21015 +#define pci_dma_sync_single_for_cpu pci_dma_sync_single
21016 +#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu
21017 +#endif /* 2.6.5 => 2.6.0 */
21019 +/*****************************************************************************/
21020 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) )
21021 +/* taken from 2.6 include/linux/bitmap.h */
21022 +#undef bitmap_zero
21023 +#define bitmap_zero _kc_bitmap_zero
21024 +static inline void _kc_bitmap_zero(unsigned long *dst, int nbits)
21026 + if (nbits <= BITS_PER_LONG)
21029 + int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
21030 + memset(dst, 0, len);
21033 +#endif /* < 2.6.6 */
21035 +/*****************************************************************************/
21036 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) )
21038 +#define if_mii _kc_if_mii
21039 +static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)
21041 + return (struct mii_ioctl_data *) &rq->ifr_ifru;
21043 +#endif /* < 2.6.7 */
21045 +/*****************************************************************************/
21046 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )
21047 +#ifndef PCI_EXP_DEVCTL
21048 +#define PCI_EXP_DEVCTL 8
21050 +#ifndef PCI_EXP_DEVCTL_CERE
21051 +#define PCI_EXP_DEVCTL_CERE 0x0001
21053 +#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \
21054 + schedule_timeout((x * HZ)/1000 + 2); \
21057 +#endif /* < 2.6.8 */
21059 +/*****************************************************************************/
21060 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
21061 +#include <net/dsfield.h>
21065 +#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags)
21066 +extern void *_kc_kzalloc(size_t size, int flags);
21068 +#define MSEC_PER_SEC 1000L
21069 +static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j)
21071 +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
21072 + return (MSEC_PER_SEC / HZ) * j;
21073 +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
21074 + return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);
21076 + return (j * MSEC_PER_SEC) / HZ;
21079 +static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m)
21081 + if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET))
21082 + return MAX_JIFFY_OFFSET;
21083 +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
21084 + return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);
21085 +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
21086 + return m * (HZ / MSEC_PER_SEC);
21088 + return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC;
21092 +#define msleep_interruptible _kc_msleep_interruptible
21093 +static inline unsigned long _kc_msleep_interruptible(unsigned int msecs)
21095 + unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1;
21097 + while (timeout && !signal_pending(current)) {
21098 + __set_current_state(TASK_INTERRUPTIBLE);
21099 + timeout = schedule_timeout(timeout);
21101 + return _kc_jiffies_to_msecs(timeout);
21104 +/* Basic mode control register. */
21105 +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
21108 +#define __le16 u16
21111 +#define __le32 u32
21114 +#define __le64 u64
21117 +#ifdef pci_dma_mapping_error
21118 +#undef pci_dma_mapping_error
21120 +#define pci_dma_mapping_error _kc_pci_dma_mapping_error
21121 +static inline int _kc_pci_dma_mapping_error(struct pci_dev *pdev,
21122 + dma_addr_t dma_addr)
21124 + return dma_addr == 0;
21127 +#endif /* < 2.6.9 */
21129 +/*****************************************************************************/
21130 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )
21131 +#ifdef module_param_array_named
21132 +#undef module_param_array_named
21133 +#define module_param_array_named(name, array, type, nump, perm) \
21134 + static struct kparam_array __param_arr_##name \
21135 + = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \
21136 + sizeof(array[0]), array }; \
21137 + module_param_call(name, param_array_set, param_array_get, \
21138 + &__param_arr_##name, perm)
21139 +#endif /* module_param_array_named */
21140 +#endif /* < 2.6.10 */
21142 +/*****************************************************************************/
21143 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) )
21147 +#define PCI_D3hot 3
21148 +#define PCI_D3cold 4
21149 +typedef int pci_power_t;
21150 +#define pci_choose_state(pdev,state) state
21151 +#define PMSG_SUSPEND 3
21152 +#define PCI_EXP_LNKCTL 16
21154 +#undef NETIF_F_LLTX
21156 +#ifndef ARCH_HAS_PREFETCH
21157 +#define prefetch(X)
21160 +#ifndef NET_IP_ALIGN
21161 +#define NET_IP_ALIGN 2
21164 +#define KC_USEC_PER_SEC 1000000L
21165 +#define usecs_to_jiffies _kc_usecs_to_jiffies
21166 +static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j)
21168 +#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)
21169 + return (KC_USEC_PER_SEC / HZ) * j;
21170 +#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)
21171 + return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC);
21173 + return (j * KC_USEC_PER_SEC) / HZ;
21176 +static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m)
21178 + if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET))
21179 + return MAX_JIFFY_OFFSET;
21180 +#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)
21181 + return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ);
21182 +#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)
21183 + return m * (HZ / KC_USEC_PER_SEC);
21185 + return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC;
21188 +#endif /* < 2.6.11 */
21190 +/*****************************************************************************/
21191 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) )
21192 +#include <linux/reboot.h>
21193 +#define USE_REBOOT_NOTIFIER
21195 +/* Generic MII registers. */
21196 +#define MII_CTRL1000 0x09 /* 1000BASE-T control */
21197 +#define MII_STAT1000 0x0a /* 1000BASE-T status */
21198 +/* Advertisement control register. */
21199 +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
21200 +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */
21201 +/* 1000BASE-T Control register */
21202 +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
21203 +#endif /* < 2.6.12 */
21205 +/*****************************************************************************/
21206 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )
21207 +#define pm_message_t u32
21209 +#define kzalloc _kc_kzalloc
21210 +extern void *_kc_kzalloc(size_t size, int flags);
21213 +/* Generic MII registers. */
21214 +#define MII_ESTATUS 0x0f /* Extended Status */
21215 +/* Basic mode status register. */
21216 +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
21217 +/* Extended status register. */
21218 +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
21219 +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
21220 +#endif /* < 2.6.14 */
21222 +/*****************************************************************************/
21223 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) )
21224 +#ifndef device_can_wakeup
21225 +#define device_can_wakeup(dev) (1)
21227 +#ifndef device_set_wakeup_enable
21228 +#define device_set_wakeup_enable(dev, val) do{}while(0)
21230 +#ifndef device_init_wakeup
21231 +#define device_init_wakeup(dev,val) do {} while (0)
21233 +#endif /* < 2.6.15 */
21235 +/*****************************************************************************/
21236 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) )
21237 +#define DEFINE_MUTEX(x) DECLARE_MUTEX(x)
21238 +#define mutex_lock(x) down_interruptible(x)
21239 +#define mutex_unlock(x) up(x)
21241 +#undef HAVE_PCI_ERS
21242 +#else /* 2.6.16 and above */
21243 +#undef HAVE_PCI_ERS
21244 +#define HAVE_PCI_ERS
21245 +#endif /* < 2.6.16 */
21247 +/*****************************************************************************/
21248 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )
21250 +#ifndef IRQ_HANDLED
21251 +#define irqreturn_t void
21252 +#define IRQ_HANDLED
21256 +#ifndef IRQF_PROBE_SHARED
21257 +#ifdef SA_PROBEIRQ
21258 +#define IRQF_PROBE_SHARED SA_PROBEIRQ
21260 +#define IRQF_PROBE_SHARED 0
21264 +#ifndef IRQF_SHARED
21265 +#define IRQF_SHARED SA_SHIRQ
21268 +#ifndef ARRAY_SIZE
21269 +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
21272 +#ifndef netdev_alloc_skb
21273 +#define netdev_alloc_skb _kc_netdev_alloc_skb
21274 +extern struct sk_buff *_kc_netdev_alloc_skb(struct net_device *dev,
21275 + unsigned int length);
21278 +#ifndef skb_is_gso
21279 +#ifdef NETIF_F_TSO
21280 +#define skb_is_gso _kc_skb_is_gso
21281 +static inline int _kc_skb_is_gso(const struct sk_buff *skb)
21283 + return skb_shinfo(skb)->gso_size;
21286 +#define skb_is_gso(a) 0
21290 +#endif /* < 2.6.18 */
21292 +/*****************************************************************************/
21293 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )
21295 +#ifndef DIV_ROUND_UP
21296 +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
21298 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) )
21299 +#ifndef RHEL_RELEASE_CODE
21300 +#define RHEL_RELEASE_CODE 0
21302 +#ifndef RHEL_RELEASE_VERSION
21303 +#define RHEL_RELEASE_VERSION(a,b) 0
21305 +#ifndef AX_RELEASE_CODE
21306 +#define AX_RELEASE_CODE 0
21308 +#ifndef AX_RELEASE_VERSION
21309 +#define AX_RELEASE_VERSION(a,b) 0
21311 +#if (!(( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) ) && ( RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0) ) || ( RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0) ) || (AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0))))
21312 +typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *);
21314 +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))
21315 +#undef CONFIG_INET_LRO
21316 +#undef CONFIG_INET_LRO_MODULE
21318 +#undef CONFIG_FCOE
21319 +#undef CONFIG_FCOE_MODULE
21320 +#endif /* IXGBE_FCOE */
21322 +typedef irqreturn_t (*new_handler_t)(int, void*);
21323 +static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)
21325 +typedef void (*irq_handler_t)(int, void*, struct pt_regs *);
21326 +typedef void (*new_handler_t)(int, void*);
21327 +static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)
21328 +#endif /* >= 2.5.x */
21330 + irq_handler_t new_handler = (irq_handler_t) handler;
21331 + return request_irq(irq, new_handler, flags, devname, dev_id);
21334 +#undef request_irq
21335 +#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id))
21337 +#define irq_handler_t new_handler_t
21338 +/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */
21339 +#define PCIE_CONFIG_SPACE_LEN 256
21340 +#define PCI_CONFIG_SPACE_LEN 64
21341 +#define PCIE_LINK_STATUS 0x12
21342 +#define pci_config_space_ich8lan() { \
21343 + if (adapter->flags & FLAG_IS_ICH) \
21344 + size = PCIE_CONFIG_SPACE_LEN; \
21346 +#undef pci_save_state
21347 +extern int _kc_pci_save_state(struct pci_dev *);
21348 +#define pci_save_state(pdev) _kc_pci_save_state(pdev)
21349 +#undef pci_restore_state
21350 +extern void _kc_pci_restore_state(struct pci_dev *);
21351 +#define pci_restore_state(pdev) _kc_pci_restore_state(pdev)
21352 +#ifdef HAVE_PCI_ERS
21353 +#undef free_netdev
21354 +extern void _kc_free_netdev(struct net_device *);
21355 +#define free_netdev(netdev) _kc_free_netdev(netdev)
21357 +static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)
21361 +#define pci_disable_pcie_error_reporting(dev) do {} while (0)
21362 +#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0)
21363 +#else /* 2.6.19 */
21364 +#include <linux/aer.h>
21365 +#endif /* < 2.6.19 */
21367 +/*****************************************************************************/
21368 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) )
21369 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) )
21371 +#define INIT_WORK(_work, _func) \
21373 + INIT_LIST_HEAD(&(_work)->entry); \
21374 + (_work)->pending = 0; \
21375 + (_work)->func = (void (*)(void *))_func; \
21376 + (_work)->data = _work; \
21377 + init_timer(&(_work)->timer); \
21381 +#ifndef PCI_VDEVICE
21382 +#define PCI_VDEVICE(ven, dev) \
21383 + PCI_VENDOR_ID_##ven, (dev), \
21384 + PCI_ANY_ID, PCI_ANY_ID, 0, 0
21387 +#ifndef round_jiffies
21388 +#define round_jiffies(x) x
21391 +#define csum_offset csum
21393 +#endif /* < 2.6.20 */
21395 +/*****************************************************************************/
21396 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )
21397 +#define to_net_dev(class) container_of(class, struct net_device, class_dev)
21398 +#define NETDEV_CLASS_DEV
21399 +#define vlan_group_get_device(vg, id) (vg->vlan_devices[id])
21400 +#define vlan_group_set_device(vg, id, dev) if (vg) vg->vlan_devices[id] = dev;
21401 +#define pci_channel_offline(pdev) (pdev->error_state && \
21402 + pdev->error_state != pci_channel_io_normal)
21403 +#define pci_request_selected_regions(pdev, bars, name) \
21404 + pci_request_regions(pdev, name)
21405 +#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev);
21406 +#endif /* < 2.6.21 */
21408 +/*****************************************************************************/
21409 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )
21410 +#define tcp_hdr(skb) (skb->h.th)
21411 +#define tcp_hdrlen(skb) (skb->h.th->doff << 2)
21412 +#define skb_transport_offset(skb) (skb->h.raw - skb->data)
21413 +#define skb_transport_header(skb) (skb->h.raw)
21414 +#define ipv6_hdr(skb) (skb->nh.ipv6h)
21415 +#define ip_hdr(skb) (skb->nh.iph)
21416 +#define skb_network_offset(skb) (skb->nh.raw - skb->data)
21417 +#define skb_network_header(skb) (skb->nh.raw)
21418 +#define skb_tail_pointer(skb) skb->tail
21419 +#define skb_copy_to_linear_data_offset(skb, offset, from, len) \
21420 + memcpy(skb->data + offset, from, len)
21421 +#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw)
21422 +#define pci_register_driver pci_module_init
21423 +#define skb_mac_header(skb) skb->mac.raw
21425 +#ifdef NETIF_F_MULTI_QUEUE
21426 +#ifndef alloc_etherdev_mq
21427 +#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a)
21429 +#endif /* NETIF_F_MULTI_QUEUE */
21431 +#ifndef ETH_FCS_LEN
21432 +#define ETH_FCS_LEN 4
21434 +#define cancel_work_sync(x) flush_scheduled_work()
21436 +#define udp_hdr _udp_hdr
21437 +static inline struct udphdr *_udp_hdr(const struct sk_buff *skb)
21439 + return (struct udphdr *)skb_transport_header(skb);
21442 +#endif /* < 2.6.22 */
21444 +/*****************************************************************************/
21445 +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) )
21446 +#undef ETHTOOL_GPERMADDR
21447 +#undef SET_MODULE_OWNER
21448 +#define SET_MODULE_OWNER(dev) do { } while (0)
21449 +#endif /* > 2.6.22 */
21451 +/*****************************************************************************/
21452 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) )
21453 +#define netif_subqueue_stopped(_a, _b) 0
21454 +#endif /* < 2.6.23 */
21456 +/*****************************************************************************/
21457 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )
21458 +/* NAPI API changes in 2.6.24 break everything */
21459 +struct napi_struct {
21460 + /* used to look up the real NAPI polling routine */
21461 + int (*poll)(struct napi_struct *, int);
21462 + struct net_device poll_dev;
21466 +extern int __kc_adapter_clean(struct net_device *, int *);
21467 +extern struct net_device * napi_to_netdev(struct napi_struct *);
21468 +#define napi_to_poll_dev(napi) napi_to_netdev(napi)
21469 +#define napi_enable(napi) netif_poll_enable(adapter->netdev)
21470 +#define napi_disable(napi) netif_poll_disable(adapter->netdev)
21471 +#define netif_napi_add(_netdev, _napi, _poll, _weight) \
21473 + struct napi_struct *__napi = (_napi); \
21474 + _netdev->poll = &(__kc_adapter_clean); \
21475 + _netdev->weight = (_weight); \
21476 + __napi->poll = &(_poll); \
21477 + __napi->weight = (_weight); \
21478 + netif_poll_disable(_netdev); \
21480 +#define netif_napi_del(_a) do {} while (0)
21481 +#define napi_schedule_prep(napi) netif_rx_schedule_prep(napi_to_netdev(napi))
21482 +#define napi_schedule(napi) netif_rx_schedule(napi_to_poll_dev(napi))
21483 +#define __napi_schedule(napi) __netif_rx_schedule(napi_to_poll_dev(napi))
21484 +#define napi_complete(napi) netif_rx_complete(napi_to_poll_dev(napi))
21486 +#define netif_napi_add(_netdev, _napi, _poll, _weight) \
21488 + struct napi_struct *__napi = _napi; \
21489 + _netdev->poll = &(_poll); \
21490 + _netdev->weight = (_weight); \
21491 + __napi->poll = &(_poll); \
21492 + __napi->weight = (_weight); \
21494 +#define netif_napi_del(_a) do {} while (0)
21497 +#undef dev_get_by_name
21498 +#define dev_get_by_name(_a, _b) dev_get_by_name(_b)
21499 +#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b)
21500 +#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
21501 +#else /* < 2.6.24 */
21502 +#define HAVE_NETDEV_NAPI_LIST
21503 +#endif /* < 2.6.24 */
21505 +/*****************************************************************************/
21506 +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) )
21507 +#include <linux/pm_qos_params.h>
21508 +#endif /* > 2.6.24 */
21510 +/*****************************************************************************/
21511 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) )
21512 +#define PM_QOS_CPU_DMA_LATENCY 1
21514 +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) )
21515 +#include <linux/latency.h>
21516 +#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY
21517 +#define pm_qos_add_requirement(pm_qos_class, name, value) \
21518 + set_acceptable_latency(name, value)
21519 +#define pm_qos_remove_requirement(pm_qos_class, name) \
21520 + remove_acceptable_latency(name)
21521 +#define pm_qos_update_requirement(pm_qos_class, name, value) \
21522 + modify_acceptable_latency(name, value)
21524 +#define PM_QOS_DEFAULT_VALUE -1
21525 +#define pm_qos_add_requirement(pm_qos_class, name, value)
21526 +#define pm_qos_remove_requirement(pm_qos_class, name)
21527 +#define pm_qos_update_requirement(pm_qos_class, name, value) { \
21528 + if (value != PM_QOS_DEFAULT_VALUE) { \
21529 + printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \
21530 + pci_name(adapter->pdev)); \
21533 +#endif /* > 2.6.18 */
21535 +#define pci_enable_device_mem(pdev) pci_enable_device(pdev)
21537 +#endif /* < 2.6.25 */
21539 +/*****************************************************************************/
21540 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )
21541 +#else /* < 2.6.26 */
21542 +#include <linux/pci-aspm.h>
21543 +#define HAVE_NETDEV_VLAN_FEATURES
21544 +#endif /* < 2.6.26 */
21545 +/*****************************************************************************/
21546 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )
21547 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) )
21548 +#if (((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM)) || ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && defined(CONFIG_PM_SLEEP)))
21549 +#undef device_set_wakeup_enable
21550 +#define device_set_wakeup_enable(dev, val) \
21553 + int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \
21555 + pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \
21558 + (dev)->power.can_wakeup = !!(pmc >> 11); \
21559 + (dev)->power.should_wakeup = (val && (pmc >> 11)); \
21561 +#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */
21562 +#endif /* 2.6.15 through 2.6.27 */
21563 +#ifndef netif_napi_del
21564 +#define netif_napi_del(_a) do {} while (0)
21566 +#ifdef CONFIG_NETPOLL
21567 +#undef netif_napi_del
21568 +#define netif_napi_del(_a) list_del(&(_a)->dev_list);
21571 +#endif /* netif_napi_del */
21572 +#ifndef pci_dma_mapping_error
21573 +#define pci_dma_mapping_error(pdev, dma_addr) pci_dma_mapping_error(dma_addr)
21578 +extern void _kc_netif_tx_stop_all_queues(struct net_device *);
21579 +extern void _kc_netif_tx_wake_all_queues(struct net_device *);
21580 +extern void _kc_netif_tx_start_all_queues(struct net_device *);
21581 +#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a)
21582 +#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a)
21583 +#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a)
21584 +#undef netif_stop_subqueue
21585 +#define netif_stop_subqueue(_ndev,_qi) do { \
21586 + if (netif_is_multiqueue((_ndev))) \
21587 + netif_stop_subqueue((_ndev), (_qi)); \
21589 + netif_stop_queue((_ndev)); \
21591 +#undef netif_start_subqueue
21592 +#define netif_start_subqueue(_ndev,_qi) do { \
21593 + if (netif_is_multiqueue((_ndev))) \
21594 + netif_start_subqueue((_ndev), (_qi)); \
21596 + netif_start_queue((_ndev)); \
21598 +#else /* HAVE_TX_MQ */
21599 +#define netif_tx_stop_all_queues(a) netif_stop_queue(a)
21600 +#define netif_tx_wake_all_queues(a) netif_wake_queue(a)
21601 +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) )
21602 +#define netif_tx_start_all_queues(a) netif_start_queue(a)
21604 +#define netif_tx_start_all_queues(a) do {} while (0)
21606 +#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev))
21607 +#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev))
21608 +#endif /* HAVE_TX_MQ */
21609 +#ifndef NETIF_F_MULTI_QUEUE
21610 +#define NETIF_F_MULTI_QUEUE 0
21611 +#define netif_is_multiqueue(a) 0
21612 +#define netif_wake_subqueue(a, b)
21613 +#endif /* NETIF_F_MULTI_QUEUE */
21614 +#else /* < 2.6.27 */
21615 +#define HAVE_TX_MQ
21616 +#define HAVE_NETDEV_SELECT_QUEUE
21617 +#endif /* < 2.6.27 */
21619 +/*****************************************************************************/
21620 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )
21621 +#define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \
21622 + pci_resource_len(pdev, bar))
21623 +#define pci_wake_from_d3 _kc_pci_wake_from_d3
21624 +#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep
21625 +extern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable);
21626 +extern int _kc_pci_prepare_to_sleep(struct pci_dev *dev);
21627 +#endif /* < 2.6.28 */
21629 +/*****************************************************************************/
21630 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) )
21631 +#define pci_request_selected_regions_exclusive(pdev, bars, name) \
21632 + pci_request_selected_regions(pdev, bars, name)
21633 +#else /* < 2.6.29 */
21635 +#define HAVE_PFC_MODE_ENABLE
21636 +#endif /* CONFIG_DCB */
21637 +#endif /* < 2.6.29 */
21639 +/*****************************************************************************/
21640 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )
21642 +#undef CONFIG_FCOE
21643 +#undef CONFIG_FCOE_MODULE
21644 +#endif /* IXGBE_FCOE */
21645 +extern u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb);
21646 +#define skb_tx_hash(n, s) _kc_skb_tx_hash(n, s)
21648 +#define HAVE_ASPM_QUIRKS
21649 +#endif /* < 2.6.30 */
21651 +/*****************************************************************************/
21652 +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) )
21654 +#ifndef HAVE_NETDEV_STORAGE_ADDRESS
21655 +#define HAVE_NETDEV_STORAGE_ADDRESS
21657 +#endif /* < 2.6.31 */
21658 +#endif /* _KCOMPAT_H_ */
21659 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/Makefile linux-2.6.22-10/drivers/net/e1000e/Makefile
21660 --- linux-2.6.22-0/drivers/net/e1000e/Makefile 1970-01-01 01:00:00.000000000 +0100
21661 +++ linux-2.6.22-10/drivers/net/e1000e/Makefile 2009-08-27 23:56:36.000000000 +0200
21663 +################################################################################
21665 +# Intel PRO/1000 Linux driver
21666 +# Copyright(c) 1999 - 2009 Intel Corporation.
21668 +# This program is free software; you can redistribute it and/or modify it
21669 +# under the terms and conditions of the GNU General Public License,
21670 +# version 2, as published by the Free Software Foundation.
21672 +# This program is distributed in the hope it will be useful, but WITHOUT
21673 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21674 +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21677 +# You should have received a copy of the GNU General Public License along with
21678 +# this program; if not, write to the Free Software Foundation, Inc.,
21679 +# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21681 +# The full GNU General Public License is included in this distribution in
21682 +# the file called "COPYING".
21684 +# Contact Information:
21685 +# Linux NICS <linux.nics@intel.com>
21686 +# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21687 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21689 +################################################################################
21691 +obj-$(CONFIG_E1000E) := e1000e.o
21693 +e1000e-objs := e1000_82571.o e1000_ich8lan.o e1000_80003es2lan.o \
21694 + netdev.o ethtool.o param.o e1000_mac.o e1000_nvm.o \
21695 + e1000_phy.o e1000_manage.o kcompat.o
21696 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/netdev.c linux-2.6.22-10/drivers/net/e1000e/netdev.c
21697 --- linux-2.6.22-0/drivers/net/e1000e/netdev.c 1970-01-01 01:00:00.000000000 +0100
21698 +++ linux-2.6.22-10/drivers/net/e1000e/netdev.c 2009-06-24 00:32:20.000000000 +0200
21700 +/*******************************************************************************
21702 + Intel PRO/1000 Linux driver
21703 + Copyright(c) 1999 - 2009 Intel Corporation.
21705 + This program is free software; you can redistribute it and/or modify it
21706 + under the terms and conditions of the GNU General Public License,
21707 + version 2, as published by the Free Software Foundation.
21709 + This program is distributed in the hope it will be useful, but WITHOUT
21710 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21711 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21714 + You should have received a copy of the GNU General Public License along with
21715 + this program; if not, write to the Free Software Foundation, Inc.,
21716 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21718 + The full GNU General Public License is included in this distribution in
21719 + the file called "COPYING".
21721 + Contact Information:
21722 + Linux NICS <linux.nics@intel.com>
21723 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21724 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21726 +*******************************************************************************/
21728 +#include <linux/module.h>
21729 +#include <linux/types.h>
21730 +#include <linux/init.h>
21731 +#include <linux/pci.h>
21732 +#include <linux/vmalloc.h>
21733 +#include <linux/pagemap.h>
21734 +#include <linux/delay.h>
21735 +#include <linux/netdevice.h>
21736 +#include <linux/tcp.h>
21737 +#include <linux/ipv6.h>
21738 +#ifdef NETIF_F_TSO
21739 +#include <net/checksum.h>
21740 +#ifdef NETIF_F_TSO6
21741 +#include <net/ip6_checksum.h>
21744 +#include <linux/mii.h>
21745 +#include <linux/ethtool.h>
21746 +#include <linux/if_vlan.h>
21748 +#include "e1000.h"
21750 +#ifdef CONFIG_E1000E_NAPI
21751 +#define DRV_EXTRAVERSION "-NAPI"
21753 +#define DRV_EXTRAVERSION
21756 +#define DRV_VERSION "1.0.2.5" DRV_EXTRAVERSION
21757 +char e1000e_driver_name[] = "e1000e";
21758 +const char e1000e_driver_version[] = DRV_VERSION;
21760 +static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
21762 + struct e1000_hw *hw = &adapter->hw;
21763 + static int global_quad_port_a; /* global port a indication */
21764 + struct pci_dev *pdev = adapter->pdev;
21765 + u16 eeprom_data = 0;
21766 + int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
21768 + /* tag quad port adapters first, it's used below */
21769 + switch (pdev->device) {
21770 + case E1000_DEV_ID_82571EB_QUAD_COPPER:
21771 + case E1000_DEV_ID_82571EB_QUAD_FIBER:
21772 + case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
21773 + case E1000_DEV_ID_82571PT_QUAD_COPPER:
21774 + adapter->flags |= FLAG_IS_QUAD_PORT;
21775 + /* mark the first port */
21776 + if (global_quad_port_a == 0)
21777 + adapter->flags |= FLAG_IS_QUAD_PORT_A;
21778 + /* Reset for multiple quad port adapters */
21779 + global_quad_port_a++;
21780 + if (global_quad_port_a == 4)
21781 + global_quad_port_a = 0;
21787 + switch (adapter->hw.mac.type) {
21788 + case e1000_82571:
21789 + /* these dual ports don't have WoL on port B at all */
21790 + if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
21791 + (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
21792 + (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
21794 + adapter->flags &= ~FLAG_HAS_WOL;
21795 + /* quad ports only support WoL on port A */
21796 + if (adapter->flags & FLAG_IS_QUAD_PORT &&
21797 + (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
21798 + adapter->flags &= ~FLAG_HAS_WOL;
21799 + /* Does not support WoL on any port */
21800 + if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
21801 + adapter->flags &= ~FLAG_HAS_WOL;
21804 + case e1000_82573:
21805 + if (pdev->device == E1000_DEV_ID_82573L) {
21806 + if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
21807 + &eeprom_data) < 0)
21809 + if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
21810 + adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
21811 + adapter->max_hw_frame_size = DEFAULT_JUMBO;
21823 +static struct e1000_info e1000_82571_info = {
21824 + .mac = e1000_82571,
21825 + .flags = FLAG_HAS_HW_VLAN_FILTER
21826 + | FLAG_HAS_JUMBO_FRAMES
21828 + | FLAG_APME_IN_CTRL3
21829 + | FLAG_RX_CSUM_ENABLED
21830 + | FLAG_HAS_CTRLEXT_ON_LOAD
21831 + | FLAG_HAS_SMART_POWER_DOWN
21832 + | FLAG_RESET_OVERWRITES_LAA /* errata */
21833 + | FLAG_TARC_SPEED_MODE_BIT /* errata */
21834 + | FLAG_APME_CHECK_PORT_B,
21836 + .max_hw_frame_size = DEFAULT_JUMBO,
21837 + .init_ops = e1000_init_function_pointers_82571,
21838 + .get_variants = e1000_get_variants_82571,
21841 +static struct e1000_info e1000_82572_info = {
21842 + .mac = e1000_82572,
21843 + .flags = FLAG_HAS_HW_VLAN_FILTER
21844 + | FLAG_HAS_JUMBO_FRAMES
21846 + | FLAG_APME_IN_CTRL3
21847 + | FLAG_RX_CSUM_ENABLED
21848 + | FLAG_HAS_CTRLEXT_ON_LOAD
21849 + | FLAG_TARC_SPEED_MODE_BIT, /* errata */
21851 + .max_hw_frame_size = DEFAULT_JUMBO,
21852 + .init_ops = e1000_init_function_pointers_82571,
21853 + .get_variants = e1000_get_variants_82571,
21856 +static struct e1000_info e1000_82573_info = {
21857 + .mac = e1000_82573,
21858 + .flags = FLAG_HAS_HW_VLAN_FILTER
21860 + | FLAG_APME_IN_CTRL3
21861 + | FLAG_RX_CSUM_ENABLED
21862 + | FLAG_HAS_SMART_POWER_DOWN
21865 + | FLAG_HAS_SWSM_ON_LOAD,
21867 + .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
21868 + .init_ops = e1000_init_function_pointers_82571,
21869 + .get_variants = e1000_get_variants_82571,
21872 +static struct e1000_info e1000_82574_info = {
21873 + .mac = e1000_82574,
21874 + .flags = FLAG_HAS_HW_VLAN_FILTER
21875 +#ifdef CONFIG_E1000E_MSIX
21878 + | FLAG_HAS_JUMBO_FRAMES
21880 + | FLAG_APME_IN_CTRL3
21881 + | FLAG_RX_CSUM_ENABLED
21882 + | FLAG_HAS_SMART_POWER_DOWN
21884 + | FLAG_HAS_CTRLEXT_ON_LOAD,
21886 + .max_hw_frame_size = DEFAULT_JUMBO,
21887 + .init_ops = e1000_init_function_pointers_82571,
21888 + .get_variants = e1000_get_variants_82571,
21891 +static struct e1000_info e1000_82583_info = {
21892 + .mac = e1000_82583,
21893 + .flags = FLAG_HAS_HW_VLAN_FILTER
21895 + | FLAG_APME_IN_CTRL3
21896 + | FLAG_RX_CSUM_ENABLED
21897 + | FLAG_HAS_SMART_POWER_DOWN
21899 + | FLAG_HAS_CTRLEXT_ON_LOAD,
21901 + .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
21902 + .init_ops = e1000_init_function_pointers_82571,
21903 + .get_variants = e1000_get_variants_82571,
21906 +static struct e1000_info e1000_es2_info = {
21907 + .mac = e1000_80003es2lan,
21908 + .flags = FLAG_HAS_HW_VLAN_FILTER
21909 + | FLAG_HAS_JUMBO_FRAMES
21911 + | FLAG_APME_IN_CTRL3
21912 + | FLAG_RX_CSUM_ENABLED
21913 + | FLAG_HAS_CTRLEXT_ON_LOAD
21914 + | FLAG_RX_NEEDS_RESTART /* errata */
21915 + | FLAG_TARC_SET_BIT_ZERO /* errata */
21916 + | FLAG_APME_CHECK_PORT_B
21917 + | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
21918 + | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
21920 + .max_hw_frame_size = DEFAULT_JUMBO,
21921 + .init_ops = e1000_init_function_pointers_80003es2lan,
21922 + .get_variants = NULL,
21925 +static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
21927 + if (adapter->hw.phy.type == e1000_phy_ife) {
21928 + adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
21929 + adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
21932 + if ((adapter->hw.mac.type == e1000_ich8lan) &&
21933 + (adapter->hw.phy.type == e1000_phy_igp_3))
21934 + adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
21939 +static struct e1000_info e1000_ich8_info = {
21940 + .mac = e1000_ich8lan,
21941 + .flags = FLAG_HAS_WOL
21943 + | FLAG_RX_CSUM_ENABLED
21944 + | FLAG_HAS_CTRLEXT_ON_LOAD
21947 + | FLAG_APME_IN_WUC,
21949 + .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
21950 + .init_ops = e1000_init_function_pointers_ich8lan,
21951 + .get_variants = e1000_get_variants_ich8lan,
21954 +static struct e1000_info e1000_ich9_info = {
21955 + .mac = e1000_ich9lan,
21956 + .flags = FLAG_HAS_JUMBO_FRAMES
21959 + | FLAG_RX_CSUM_ENABLED
21960 + | FLAG_HAS_CTRLEXT_ON_LOAD
21964 + | FLAG_APME_IN_WUC,
21966 + .max_hw_frame_size = DEFAULT_JUMBO,
21967 + .init_ops = e1000_init_function_pointers_ich8lan,
21968 + .get_variants = e1000_get_variants_ich8lan,
21971 +static struct e1000_info e1000_ich10_info = {
21972 + .mac = e1000_ich10lan,
21973 + .flags = FLAG_HAS_JUMBO_FRAMES
21976 + | FLAG_RX_CSUM_ENABLED
21977 + | FLAG_HAS_CTRLEXT_ON_LOAD
21981 + | FLAG_APME_IN_WUC,
21983 + .max_hw_frame_size = DEFAULT_JUMBO,
21984 + .init_ops = e1000_init_function_pointers_ich8lan,
21985 + .get_variants = e1000_get_variants_ich8lan,
21988 +static struct e1000_info e1000_pch_info = {
21989 + .mac = e1000_pchlan,
21990 + .flags = FLAG_IS_ICH
21992 + | FLAG_RX_CSUM_ENABLED
21993 + | FLAG_HAS_CTRLEXT_ON_LOAD
21996 + | FLAG_HAS_JUMBO_FRAMES
21997 + | FLAG_APME_IN_WUC,
21999 + .max_hw_frame_size = 4096,
22000 + .init_ops = e1000_init_function_pointers_ich8lan,
22001 + .get_variants = e1000_get_variants_ich8lan,
22004 +static const struct e1000_info *e1000_info_tbl[] = {
22005 + [board_82571] = &e1000_82571_info,
22006 + [board_82572] = &e1000_82572_info,
22007 + [board_82573] = &e1000_82573_info,
22008 + [board_82574] = &e1000_82574_info,
22009 + [board_82583] = &e1000_82583_info,
22010 + [board_80003es2lan] = &e1000_es2_info,
22011 + [board_ich8lan] = &e1000_ich8_info,
22012 + [board_ich9lan] = &e1000_ich9_info,
22013 + [board_ich10lan] = &e1000_ich10_info,
22014 + [board_pchlan] = &e1000_pch_info,
22018 + * e1000_desc_unused - calculate if we have unused descriptors
22020 +static int e1000_desc_unused(struct e1000_ring *ring)
22022 + if (ring->next_to_clean > ring->next_to_use)
22023 + return ring->next_to_clean - ring->next_to_use - 1;
22025 + return ring->count + ring->next_to_clean - ring->next_to_use - 1;
22029 + * e1000_receive_skb - helper function to handle Rx indications
22030 + * @adapter: board private structure
22031 + * @status: descriptor status field as written by hardware
22032 + * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
22033 + * @skb: pointer to sk_buff to be indicated to stack
22035 +static void e1000_receive_skb(struct e1000_adapter *adapter,
22036 + struct net_device *netdev,
22037 + struct sk_buff *skb,
22038 + u8 status, __le16 vlan)
22040 +#ifndef CONFIG_E1000E_NAPI
22044 + skb->protocol = eth_type_trans(skb, netdev);
22046 +#ifdef CONFIG_E1000E_NAPI
22047 + if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
22048 + vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
22049 + le16_to_cpu(vlan));
22051 +#ifdef NETIF_F_GRO
22052 + napi_gro_receive(&adapter->napi, skb);
22054 + netif_receive_skb(skb);
22055 +#endif /* NETIF_F_GRO */
22057 + if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
22058 + ret = vlan_hwaccel_rx(skb, adapter->vlgrp, le16_to_cpu(vlan));
22060 + ret = netif_rx(skb);
22061 + if (unlikely(ret == NET_RX_DROP))
22062 + adapter->rx_dropped_backlog++;
22064 +#ifndef NETIF_F_GRO
22066 + netdev->last_rx = jiffies;
22071 + * e1000_rx_checksum - Receive Checksum Offload for 82543
22072 + * @adapter: board private structure
22073 + * @status_err: receive descriptor status and error fields
22074 + * @csum: receive descriptor csum field
22075 + * @sk_buff: socket buffer with received data
22077 +static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
22078 + u32 csum, struct sk_buff *skb)
22080 + u16 status = (u16)status_err;
22081 + u8 errors = (u8)(status_err >> 24);
22082 + skb->ip_summed = CHECKSUM_NONE;
22084 + /* Ignore Checksum bit is set */
22085 + if (status & E1000_RXD_STAT_IXSM)
22087 + /* TCP/UDP checksum error bit is set */
22088 + if (errors & E1000_RXD_ERR_TCPE) {
22089 + /* let the stack verify checksum errors */
22090 + adapter->hw_csum_err++;
22094 + /* TCP/UDP Checksum has not been calculated */
22095 + if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
22098 + /* It must be a TCP or UDP packet with a valid checksum */
22099 + if (status & E1000_RXD_STAT_TCPCS) {
22100 + /* TCP checksum is good */
22101 + skb->ip_summed = CHECKSUM_UNNECESSARY;
22104 + * IP fragment with UDP payload
22105 + * Hardware complements the payload checksum, so we undo it
22106 + * and then put the value in host order for further stack use.
22108 + csum = ntohl(csum ^ 0xFFFF);
22109 + skb->csum = csum;
22110 + skb->ip_summed = CHECKSUM_COMPLETE;
22112 + adapter->hw_csum_good++;
22116 + * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
22117 + * @adapter: address of board private structure
22119 +static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
22120 + int cleaned_count)
22122 + struct net_device *netdev = adapter->netdev;
22123 + struct pci_dev *pdev = adapter->pdev;
22124 + struct e1000_ring *rx_ring = adapter->rx_ring;
22125 + struct e1000_rx_desc *rx_desc;
22126 + struct e1000_buffer *buffer_info;
22127 + struct sk_buff *skb;
22129 + unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
22131 + i = rx_ring->next_to_use;
22132 + buffer_info = &rx_ring->buffer_info[i];
22134 + while (cleaned_count--) {
22135 + skb = buffer_info->skb;
22137 + skb_trim(skb, 0);
22141 + skb = netdev_alloc_skb(netdev, bufsz);
22143 + /* Better luck next round */
22144 + adapter->alloc_rx_buff_failed++;
22149 + * Make buffer alignment 2 beyond a 16 byte boundary
22150 + * this will result in a 16 byte aligned IP header after
22151 + * the 14 byte MAC header is removed
22153 + skb_reserve(skb, NET_IP_ALIGN);
22155 + buffer_info->skb = skb;
22157 + buffer_info->dma = pci_map_single(pdev, skb->data,
22158 + adapter->rx_buffer_len,
22159 + PCI_DMA_FROMDEVICE);
22160 + if (pci_dma_mapping_error(pdev, buffer_info->dma)) {
22161 + dev_err(&pdev->dev, "RX DMA map failed\n");
22162 + adapter->rx_dma_failed++;
22166 + rx_desc = E1000_RX_DESC(*rx_ring, i);
22167 + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
22170 + if (i == rx_ring->count)
22172 + buffer_info = &rx_ring->buffer_info[i];
22175 + if (rx_ring->next_to_use != i) {
22176 + rx_ring->next_to_use = i;
22178 + i = (rx_ring->count - 1);
22181 + * Force memory writes to complete before letting h/w
22182 + * know there are new descriptors to fetch. (Only
22183 + * applicable for weak-ordered memory model archs,
22184 + * such as IA-64).
22187 + writel(i, adapter->hw.hw_addr + rx_ring->tail);
22192 + * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
22193 + * @adapter: address of board private structure
22195 +static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
22196 + int cleaned_count)
22198 + struct net_device *netdev = adapter->netdev;
22199 + struct pci_dev *pdev = adapter->pdev;
22200 + union e1000_rx_desc_packet_split *rx_desc;
22201 + struct e1000_ring *rx_ring = adapter->rx_ring;
22202 + struct e1000_buffer *buffer_info;
22203 + struct e1000_ps_page *ps_page;
22204 + struct sk_buff *skb;
22205 + unsigned int i, j;
22207 + i = rx_ring->next_to_use;
22208 + buffer_info = &rx_ring->buffer_info[i];
22210 + while (cleaned_count--) {
22211 + rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
22213 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
22214 + ps_page = &buffer_info->ps_pages[j];
22215 + if (j >= adapter->rx_ps_pages) {
22216 + /* all unused desc entries get hw null ptr */
22217 + rx_desc->read.buffer_addr[j+1] = ~cpu_to_le64(0);
22220 + if (!ps_page->page) {
22221 + ps_page->page = alloc_page(GFP_ATOMIC);
22222 + if (!ps_page->page) {
22223 + adapter->alloc_rx_buff_failed++;
22226 + ps_page->dma = pci_map_page(pdev,
22229 + PCI_DMA_FROMDEVICE);
22230 + if (pci_dma_mapping_error(pdev, ps_page->dma)) {
22231 + dev_err(&adapter->pdev->dev,
22232 + "RX DMA page map failed\n");
22233 + adapter->rx_dma_failed++;
22238 + * Refresh the desc even if buffer_addrs
22239 + * didn't change because each write-back
22240 + * erases this info.
22242 + rx_desc->read.buffer_addr[j+1] =
22243 + cpu_to_le64(ps_page->dma);
22246 + skb = netdev_alloc_skb(netdev,
22247 + adapter->rx_ps_bsize0 + NET_IP_ALIGN);
22250 + adapter->alloc_rx_buff_failed++;
22255 + * Make buffer alignment 2 beyond a 16 byte boundary
22256 + * this will result in a 16 byte aligned IP header after
22257 + * the 14 byte MAC header is removed
22259 + skb_reserve(skb, NET_IP_ALIGN);
22261 + buffer_info->skb = skb;
22262 + buffer_info->dma = pci_map_single(pdev, skb->data,
22263 + adapter->rx_ps_bsize0,
22264 + PCI_DMA_FROMDEVICE);
22265 + if (pci_dma_mapping_error(pdev, buffer_info->dma)) {
22266 + dev_err(&pdev->dev, "RX DMA map failed\n");
22267 + adapter->rx_dma_failed++;
22268 + /* cleanup skb */
22269 + dev_kfree_skb_any(skb);
22270 + buffer_info->skb = NULL;
22274 + rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
22277 + if (i == rx_ring->count)
22279 + buffer_info = &rx_ring->buffer_info[i];
22283 + if (rx_ring->next_to_use != i) {
22284 + rx_ring->next_to_use = i;
22287 + i = (rx_ring->count - 1);
22290 + * Force memory writes to complete before letting h/w
22291 + * know there are new descriptors to fetch. (Only
22292 + * applicable for weak-ordered memory model archs,
22293 + * such as IA-64).
22297 + * Hardware increments by 16 bytes, but packet split
22298 + * descriptors are 32 bytes...so we increment tail
22301 + writel(i<<1, adapter->hw.hw_addr + rx_ring->tail);
22305 +#ifdef CONFIG_E1000E_NAPI
22307 + * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
22308 + * @adapter: address of board private structure
22309 + * @cleaned_count: number of buffers to allocate this pass
22312 +static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter,
22313 + int cleaned_count)
22315 + struct net_device *netdev = adapter->netdev;
22316 + struct pci_dev *pdev = adapter->pdev;
22317 + struct e1000_rx_desc *rx_desc;
22318 + struct e1000_ring *rx_ring = adapter->rx_ring;
22319 + struct e1000_buffer *buffer_info;
22320 + struct sk_buff *skb;
22322 + unsigned int bufsz = 256 -
22323 + 16 /* for skb_reserve */ -
22326 + i = rx_ring->next_to_use;
22327 + buffer_info = &rx_ring->buffer_info[i];
22329 + while (cleaned_count--) {
22330 + skb = buffer_info->skb;
22332 + skb_trim(skb, 0);
22336 + skb = netdev_alloc_skb(netdev, bufsz);
22337 + if (unlikely(!skb)) {
22338 + /* Better luck next round */
22339 + adapter->alloc_rx_buff_failed++;
22343 + /* Make buffer alignment 2 beyond a 16 byte boundary
22344 + * this will result in a 16 byte aligned IP header after
22345 + * the 14 byte MAC header is removed
22347 + skb_reserve(skb, NET_IP_ALIGN);
22349 + buffer_info->skb = skb;
22351 + /* allocate a new page if necessary */
22352 + if (!buffer_info->page) {
22353 + buffer_info->page = alloc_page(GFP_ATOMIC);
22354 + if (unlikely(!buffer_info->page)) {
22355 + adapter->alloc_rx_buff_failed++;
22360 + if (!buffer_info->dma)
22361 + buffer_info->dma = pci_map_page(pdev,
22362 + buffer_info->page, 0,
22364 + PCI_DMA_FROMDEVICE);
22366 + rx_desc = E1000_RX_DESC(*rx_ring, i);
22367 + rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
22369 + if (unlikely(++i == rx_ring->count))
22371 + buffer_info = &rx_ring->buffer_info[i];
22374 + if (likely(rx_ring->next_to_use != i)) {
22375 + rx_ring->next_to_use = i;
22376 + if (unlikely(i-- == 0))
22377 + i = (rx_ring->count - 1);
22379 + /* Force memory writes to complete before letting h/w
22380 + * know there are new descriptors to fetch. (Only
22381 + * applicable for weak-ordered memory model archs,
22382 + * such as IA-64). */
22384 + writel(i, adapter->hw.hw_addr + rx_ring->tail);
22387 +#endif /* CONFIG_E1000E_NAPI */
22390 + * e1000_clean_rx_irq - Send received data up the network stack; legacy
22391 + * @adapter: board private structure
22393 + * the return value indicates whether actual cleaning was done, there
22394 + * is no guarantee that everything was cleaned
22396 +#ifdef CONFIG_E1000E_NAPI
22397 +static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
22398 + int *work_done, int work_to_do)
22400 +static bool e1000_clean_rx_irq(struct e1000_adapter *adapter)
22403 + struct net_device *netdev = adapter->netdev;
22404 + struct pci_dev *pdev = adapter->pdev;
22405 + struct e1000_hw *hw = &adapter->hw;
22406 + struct e1000_ring *rx_ring = adapter->rx_ring;
22407 + struct e1000_rx_desc *rx_desc, *next_rxd;
22408 + struct e1000_buffer *buffer_info, *next_buffer;
22411 + int cleaned_count = 0;
22412 + bool cleaned = 0;
22413 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
22415 + i = rx_ring->next_to_clean;
22416 + rx_desc = E1000_RX_DESC(*rx_ring, i);
22417 + buffer_info = &rx_ring->buffer_info[i];
22419 + while (rx_desc->status & E1000_RXD_STAT_DD) {
22420 + struct sk_buff *skb;
22423 +#ifdef CONFIG_E1000E_NAPI
22424 + if (*work_done >= work_to_do)
22429 + status = rx_desc->status;
22430 + skb = buffer_info->skb;
22431 + buffer_info->skb = NULL;
22433 + prefetch(skb->data - NET_IP_ALIGN);
22436 + if (i == rx_ring->count)
22438 + next_rxd = E1000_RX_DESC(*rx_ring, i);
22439 + prefetch(next_rxd);
22441 + next_buffer = &rx_ring->buffer_info[i];
22445 + pci_unmap_single(pdev,
22446 + buffer_info->dma,
22447 + adapter->rx_buffer_len,
22448 + PCI_DMA_FROMDEVICE);
22449 + buffer_info->dma = 0;
22451 + length = le16_to_cpu(rx_desc->length);
22453 + /* !EOP means multiple descriptors were used to store a single
22454 + * packet, also make sure the frame isn't just CRC only */
22455 + if (!(status & E1000_RXD_STAT_EOP) || (length <= 4)) {
22456 + /* All receives must fit into a single buffer */
22457 + e_dbg("Receive packet consumed multiple buffers\n");
22459 + buffer_info->skb = skb;
22463 + if (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
22465 + buffer_info->skb = skb;
22469 + /* adjust length to remove Ethernet CRC */
22470 + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
22473 + total_rx_bytes += length;
22474 + total_rx_packets++;
22477 + * code added for copybreak, this should improve
22478 + * performance for small packets with large amounts
22479 + * of reassembly being done in the stack
22481 + if (length < copybreak) {
22482 + struct sk_buff *new_skb =
22483 + netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
22485 + skb_reserve(new_skb, NET_IP_ALIGN);
22486 + skb_copy_to_linear_data_offset(new_skb,
22492 + /* save the skb in buffer_info as good */
22493 + buffer_info->skb = skb;
22496 + /* else just continue with the old one */
22498 + /* end copybreak code */
22499 + skb_put(skb, length);
22501 + /* Receive Checksum Offload */
22502 + e1000_rx_checksum(adapter,
22504 + ((u32)(rx_desc->errors) << 24),
22505 + le16_to_cpu(rx_desc->csum), skb);
22507 + e1000_receive_skb(adapter, netdev, skb, status, rx_desc->special);
22510 + rx_desc->status = 0;
22512 + /* return some buffers to hardware, one at a time is too slow */
22513 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
22514 + adapter->alloc_rx_buf(adapter, cleaned_count);
22515 + cleaned_count = 0;
22518 + /* use prefetched values */
22519 + rx_desc = next_rxd;
22520 + buffer_info = next_buffer;
22522 + rx_ring->next_to_clean = i;
22524 + cleaned_count = e1000_desc_unused(rx_ring);
22525 + if (cleaned_count)
22526 + adapter->alloc_rx_buf(adapter, cleaned_count);
22528 + adapter->total_rx_bytes += total_rx_bytes;
22529 + adapter->total_rx_packets += total_rx_packets;
22530 + adapter->net_stats.rx_bytes += total_rx_bytes;
22531 + adapter->net_stats.rx_packets += total_rx_packets;
22535 +static void e1000_put_txbuf(struct e1000_adapter *adapter,
22536 + struct e1000_buffer *buffer_info)
22538 + if (buffer_info->dma) {
22539 + pci_unmap_page(adapter->pdev, buffer_info->dma,
22540 + buffer_info->length, PCI_DMA_TODEVICE);
22541 + buffer_info->dma = 0;
22543 + if (buffer_info->skb) {
22544 + dev_kfree_skb_any(buffer_info->skb);
22545 + buffer_info->skb = NULL;
22549 +static void e1000_print_tx_hang(struct e1000_adapter *adapter)
22551 + struct e1000_ring *tx_ring = adapter->tx_ring;
22552 + unsigned int i = tx_ring->next_to_clean;
22553 + unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
22554 + struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
22556 + /* detected Tx unit hang */
22557 + e_err("Detected Tx Unit Hang:\n"
22560 + " next_to_use <%x>\n"
22561 + " next_to_clean <%x>\n"
22562 + "buffer_info[next_to_clean]:\n"
22563 + " time_stamp <%lx>\n"
22564 + " next_to_watch <%x>\n"
22565 + " jiffies <%lx>\n"
22566 + " next_to_watch.status <%x>\n",
22567 + readl(adapter->hw.hw_addr + tx_ring->head),
22568 + readl(adapter->hw.hw_addr + tx_ring->tail),
22569 + tx_ring->next_to_use,
22570 + tx_ring->next_to_clean,
22571 + tx_ring->buffer_info[eop].time_stamp,
22574 + eop_desc->upper.fields.status);
22578 + * e1000_clean_tx_irq - Reclaim resources after transmit completes
22579 + * @adapter: board private structure
22581 + * the return value indicates if there is more work to do (later)
22583 +static bool e1000_clean_tx_irq(struct e1000_adapter *adapter)
22585 + struct net_device *netdev = adapter->netdev;
22586 + struct e1000_hw *hw = &adapter->hw;
22587 + struct e1000_ring *tx_ring = adapter->tx_ring;
22588 + struct e1000_tx_desc *tx_desc, *eop_desc;
22589 + struct e1000_buffer *buffer_info;
22590 + unsigned int i, eop;
22591 + bool cleaned = 0, retval = 1;
22592 + unsigned int total_tx_bytes = 0, total_tx_packets = 0;
22594 + i = tx_ring->next_to_clean;
22595 + eop = tx_ring->buffer_info[i].next_to_watch;
22596 + eop_desc = E1000_TX_DESC(*tx_ring, eop);
22598 + while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
22599 + for (cleaned = 0; !cleaned; ) {
22600 + tx_desc = E1000_TX_DESC(*tx_ring, i);
22601 + buffer_info = &tx_ring->buffer_info[i];
22602 + cleaned = (i == eop);
22605 + struct sk_buff *skb = buffer_info->skb;
22606 +#ifdef NETIF_F_TSO
22607 + unsigned int segs, bytecount;
22608 + segs = skb_shinfo(skb)->gso_segs ?: 1;
22609 + /* multiply data chunks by size of headers */
22610 + bytecount = ((segs - 1) * skb_headlen(skb)) +
22612 + total_tx_packets += segs;
22613 + total_tx_bytes += bytecount;
22615 + total_tx_packets++;
22616 + total_tx_bytes += skb->len;
22620 + e1000_put_txbuf(adapter, buffer_info);
22621 + tx_desc->upper.data = 0;
22624 + if (i == tx_ring->count)
22626 +#ifdef CONFIG_E1000E_NAPI
22627 + if (total_tx_packets >= tx_ring->count) {
22629 + goto done_cleaning;
22634 + eop = tx_ring->buffer_info[i].next_to_watch;
22635 + eop_desc = E1000_TX_DESC(*tx_ring, eop);
22638 +#ifdef CONFIG_E1000E_NAPI
22641 + tx_ring->next_to_clean = i;
22643 +#define TX_WAKE_THRESHOLD 32
22644 + if (cleaned && netif_carrier_ok(netdev) &&
22645 + e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
22646 + /* Make sure that anybody stopping the queue after this
22647 + * sees the new next_to_clean.
22651 + if (netif_queue_stopped(netdev) &&
22652 + !(test_bit(__E1000_DOWN, &adapter->state))) {
22653 + netif_wake_queue(netdev);
22654 + ++adapter->restart_queue;
22658 + if (adapter->detect_tx_hung) {
22660 + * Detect a transmit hang in hardware, this serializes the
22661 + * check with the clearing of time_stamp and movement of i
22663 + adapter->detect_tx_hung = 0;
22664 + if (tx_ring->buffer_info[eop].dma &&
22665 + time_after(jiffies, tx_ring->buffer_info[eop].time_stamp
22666 + + (adapter->tx_timeout_factor * HZ))
22667 + && !(er32(STATUS) & E1000_STATUS_TXOFF)) {
22668 + e1000_print_tx_hang(adapter);
22669 + netif_stop_queue(netdev);
22672 + adapter->total_tx_bytes += total_tx_bytes;
22673 + adapter->total_tx_packets += total_tx_packets;
22674 + adapter->net_stats.tx_bytes += total_tx_bytes;
22675 + adapter->net_stats.tx_packets += total_tx_packets;
22680 + * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
22681 + * @adapter: board private structure
22683 + * the return value indicates whether actual cleaning was done, there
22684 + * is no guarantee that everything was cleaned
22686 +#ifdef CONFIG_E1000E_NAPI
22687 +static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
22688 + int *work_done, int work_to_do)
22690 +static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
22693 + struct e1000_hw *hw = &adapter->hw;
22694 + union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
22695 + struct net_device *netdev = adapter->netdev;
22696 + struct pci_dev *pdev = adapter->pdev;
22697 + struct e1000_ring *rx_ring = adapter->rx_ring;
22698 + struct e1000_buffer *buffer_info, *next_buffer;
22699 + struct e1000_ps_page *ps_page;
22700 + struct sk_buff *skb;
22701 + unsigned int i, j;
22702 + u32 length, staterr;
22703 + int cleaned_count = 0;
22704 + bool cleaned = 0;
22705 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
22707 + i = rx_ring->next_to_clean;
22708 + rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
22709 + staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
22710 + buffer_info = &rx_ring->buffer_info[i];
22712 + while (staterr & E1000_RXD_STAT_DD) {
22713 +#ifdef CONFIG_E1000E_NAPI
22714 + if (*work_done >= work_to_do)
22718 + skb = buffer_info->skb;
22720 + /* in the packet split case this is header only */
22721 + prefetch(skb->data - NET_IP_ALIGN);
22724 + if (i == rx_ring->count)
22726 + next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
22727 + prefetch(next_rxd);
22729 + next_buffer = &rx_ring->buffer_info[i];
22733 + pci_unmap_single(pdev, buffer_info->dma,
22734 + adapter->rx_ps_bsize0,
22735 + PCI_DMA_FROMDEVICE);
22736 + buffer_info->dma = 0;
22738 + if (!(staterr & E1000_RXD_STAT_EOP)) {
22739 + e_dbg("Packet Split buffers didn't pick up the full "
22741 + dev_kfree_skb_irq(skb);
22745 + if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
22746 + dev_kfree_skb_irq(skb);
22750 + length = le16_to_cpu(rx_desc->wb.middle.length0);
22753 + e_dbg("Last part of the packet spanning multiple "
22754 + "descriptors\n");
22755 + dev_kfree_skb_irq(skb);
22759 + /* Good Receive */
22760 + skb_put(skb, length);
22762 +#ifdef CONFIG_E1000E_NAPI
22765 + * this looks ugly, but it seems compiler issues make it
22766 + * more efficient than reusing j
22768 + int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
22771 + * page alloc/put takes too long and effects small packet
22772 + * throughput, so unsplit small packets and save the alloc/put
22773 + * only valid in softirq (napi) context to call kmap_*
22775 + if (l1 && (l1 <= copybreak) &&
22776 + ((length + l1) <= adapter->rx_ps_bsize0)) {
22779 + ps_page = &buffer_info->ps_pages[0];
22782 + * there is no documentation about how to call
22783 + * kmap_atomic, so we can't hold the mapping
22786 + pci_dma_sync_single_for_cpu(pdev, ps_page->dma,
22787 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
22788 + vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
22789 + memcpy(skb_tail_pointer(skb), vaddr, l1);
22790 + kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
22791 + pci_dma_sync_single_for_device(pdev, ps_page->dma,
22792 + PAGE_SIZE, PCI_DMA_FROMDEVICE);
22794 + /* remove the CRC */
22795 + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
22798 + skb_put(skb, l1);
22804 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
22805 + length = le16_to_cpu(rx_desc->wb.upper.length[j]);
22809 + ps_page = &buffer_info->ps_pages[j];
22810 + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE,
22811 + PCI_DMA_FROMDEVICE);
22812 + ps_page->dma = 0;
22813 + skb_fill_page_desc(skb, j, ps_page->page, 0, length);
22814 + ps_page->page = NULL;
22815 + skb->len += length;
22816 + skb->data_len += length;
22817 + skb->truesize += length;
22820 + /* strip the ethernet crc, problem is we're using pages now so
22821 + * this whole operation can get a little cpu intensive */
22822 + if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
22823 + pskb_trim(skb, skb->len - 4);
22825 +#ifdef CONFIG_E1000E_NAPI
22828 + total_rx_bytes += skb->len;
22829 + total_rx_packets++;
22831 + e1000_rx_checksum(adapter, staterr, le16_to_cpu(
22832 + rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
22834 + if (rx_desc->wb.upper.header_status &
22835 + cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
22836 + adapter->rx_hdr_split++;
22838 + e1000_receive_skb(adapter, netdev, skb,
22839 + staterr, rx_desc->wb.middle.vlan);
22842 + rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
22843 + buffer_info->skb = NULL;
22845 + /* return some buffers to hardware, one at a time is too slow */
22846 + if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
22847 + adapter->alloc_rx_buf(adapter, cleaned_count);
22848 + cleaned_count = 0;
22851 + /* use prefetched values */
22852 + rx_desc = next_rxd;
22853 + buffer_info = next_buffer;
22855 + staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
22857 + rx_ring->next_to_clean = i;
22859 + cleaned_count = e1000_desc_unused(rx_ring);
22860 + if (cleaned_count)
22861 + adapter->alloc_rx_buf(adapter, cleaned_count);
22863 + adapter->total_rx_bytes += total_rx_bytes;
22864 + adapter->total_rx_packets += total_rx_packets;
22865 + adapter->net_stats.rx_bytes += total_rx_bytes;
22866 + adapter->net_stats.rx_packets += total_rx_packets;
22870 +#ifdef CONFIG_E1000E_NAPI
22872 + * e1000_consume_page - helper function
22874 +static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
22878 + skb->len += length;
22879 + skb->data_len += length;
22880 + skb->truesize += length;
22884 + * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
22885 + * @adapter: board private structure
22887 + * the return value indicates whether actual cleaning was done, there
22888 + * is no guarantee that everything was cleaned
22891 +static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
22892 + int *work_done, int work_to_do)
22894 + struct net_device *netdev = adapter->netdev;
22895 + struct pci_dev *pdev = adapter->pdev;
22896 + struct e1000_ring *rx_ring = adapter->rx_ring;
22897 + struct e1000_rx_desc *rx_desc, *next_rxd;
22898 + struct e1000_buffer *buffer_info, *next_buffer;
22901 + int cleaned_count = 0;
22902 + bool cleaned = false;
22903 + unsigned int total_rx_bytes = 0, total_rx_packets = 0;
22905 + i = rx_ring->next_to_clean;
22906 + rx_desc = E1000_RX_DESC(*rx_ring, i);
22907 + buffer_info = &rx_ring->buffer_info[i];
22909 + while (rx_desc->status & E1000_RXD_STAT_DD) {
22910 + struct sk_buff *skb;
22913 + if (*work_done >= work_to_do)
22917 + status = rx_desc->status;
22918 + skb = buffer_info->skb;
22919 + buffer_info->skb = NULL;
22922 + if (i == rx_ring->count)
22924 + next_rxd = E1000_RX_DESC(*rx_ring, i);
22925 + prefetch(next_rxd);
22927 + next_buffer = &rx_ring->buffer_info[i];
22931 + pci_unmap_page(pdev, buffer_info->dma, PAGE_SIZE,
22932 + PCI_DMA_FROMDEVICE);
22933 + buffer_info->dma = 0;
22935 + length = le16_to_cpu(rx_desc->length);
22937 + /* errors is only valid for DD + EOP descriptors */
22938 + if (unlikely((status & E1000_RXD_STAT_EOP) &&
22939 + (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK))) {
22940 + /* recycle both page and skb */
22941 + buffer_info->skb = skb;
22942 + /* an error means any chain goes out the window
22944 + if (rx_ring->rx_skb_top)
22945 + dev_kfree_skb(rx_ring->rx_skb_top);
22946 + rx_ring->rx_skb_top = NULL;
22950 +#define rxtop (rx_ring->rx_skb_top)
22951 + if (!(status & E1000_RXD_STAT_EOP)) {
22952 + /* this descriptor is only the beginning (or middle) */
22954 + /* this is the beginning of a chain */
22956 + skb_fill_page_desc(rxtop, 0, buffer_info->page,
22959 + /* this is the middle of a chain */
22960 + skb_fill_page_desc(rxtop,
22961 + skb_shinfo(rxtop)->nr_frags,
22962 + buffer_info->page, 0, length);
22963 + /* re-use the skb, only consumed the page */
22964 + buffer_info->skb = skb;
22966 + e1000_consume_page(buffer_info, rxtop, length);
22970 + /* end of the chain */
22971 + skb_fill_page_desc(rxtop,
22972 + skb_shinfo(rxtop)->nr_frags,
22973 + buffer_info->page, 0, length);
22974 + /* re-use the current skb, we only consumed the
22976 + buffer_info->skb = skb;
22979 + e1000_consume_page(buffer_info, skb, length);
22981 + /* no chain, got EOP, this buf is the packet
22982 + * copybreak to save the put_page/alloc_page */
22983 + if (length <= copybreak &&
22984 + skb_tailroom(skb) >= length) {
22986 + vaddr = kmap_atomic(buffer_info->page,
22987 + KM_SKB_DATA_SOFTIRQ);
22988 + memcpy(skb_tail_pointer(skb), vaddr,
22990 + kunmap_atomic(vaddr,
22991 + KM_SKB_DATA_SOFTIRQ);
22992 + /* re-use the page, so don't erase
22993 + * buffer_info->page */
22994 + skb_put(skb, length);
22996 + skb_fill_page_desc(skb, 0,
22997 + buffer_info->page, 0,
22999 + e1000_consume_page(buffer_info, skb,
23005 + /* Receive Checksum Offload XXX recompute due to CRC strip? */
23006 + e1000_rx_checksum(adapter,
23008 + ((u32)(rx_desc->errors) << 24),
23009 + le16_to_cpu(rx_desc->csum), skb);
23011 + /* probably a little skewed due to removing CRC */
23012 + total_rx_bytes += skb->len;
23013 + total_rx_packets++;
23015 + /* eth type trans needs skb->data to point to something */
23016 + if (!pskb_may_pull(skb, ETH_HLEN)) {
23017 + e_err("pskb_may_pull failed.\n");
23018 + dev_kfree_skb(skb);
23022 + e1000_receive_skb(adapter, netdev, skb, status,
23023 + rx_desc->special);
23026 + rx_desc->status = 0;
23028 + /* return some buffers to hardware, one at a time is too slow */
23029 + if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
23030 + adapter->alloc_rx_buf(adapter, cleaned_count);
23031 + cleaned_count = 0;
23034 + /* use prefetched values */
23035 + rx_desc = next_rxd;
23036 + buffer_info = next_buffer;
23038 + rx_ring->next_to_clean = i;
23040 + cleaned_count = e1000_desc_unused(rx_ring);
23041 + if (cleaned_count)
23042 + adapter->alloc_rx_buf(adapter, cleaned_count);
23044 + adapter->total_rx_bytes += total_rx_bytes;
23045 + adapter->total_rx_packets += total_rx_packets;
23046 + adapter->net_stats.rx_bytes += total_rx_bytes;
23047 + adapter->net_stats.rx_packets += total_rx_packets;
23051 +#endif /* CONFIG_E1000E_NAPI */
23053 + * e1000_clean_rx_ring - Free Rx Buffers per Queue
23054 + * @adapter: board private structure
23056 +static void e1000_clean_rx_ring(struct e1000_adapter *adapter)
23058 + struct e1000_ring *rx_ring = adapter->rx_ring;
23059 + struct e1000_buffer *buffer_info;
23060 + struct e1000_ps_page *ps_page;
23061 + struct pci_dev *pdev = adapter->pdev;
23062 + unsigned int i, j;
23064 + /* Free all the Rx ring sk_buffs */
23065 + for (i = 0; i < rx_ring->count; i++) {
23066 + buffer_info = &rx_ring->buffer_info[i];
23067 + if (buffer_info->dma) {
23068 + if (adapter->clean_rx == e1000_clean_rx_irq)
23069 + pci_unmap_single(pdev, buffer_info->dma,
23070 + adapter->rx_buffer_len,
23071 + PCI_DMA_FROMDEVICE);
23072 +#ifdef CONFIG_E1000E_NAPI
23073 + else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
23074 + pci_unmap_page(pdev, buffer_info->dma,
23076 + PCI_DMA_FROMDEVICE);
23078 + else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
23079 + pci_unmap_single(pdev, buffer_info->dma,
23080 + adapter->rx_ps_bsize0,
23081 + PCI_DMA_FROMDEVICE);
23082 + buffer_info->dma = 0;
23085 + if (buffer_info->page) {
23086 + put_page(buffer_info->page);
23087 + buffer_info->page = NULL;
23090 + if (buffer_info->skb) {
23091 + dev_kfree_skb(buffer_info->skb);
23092 + buffer_info->skb = NULL;
23095 + for (j = 0; j < PS_PAGE_BUFFERS; j++) {
23096 + ps_page = &buffer_info->ps_pages[j];
23097 + if (!ps_page->page)
23099 + pci_unmap_page(pdev, ps_page->dma, PAGE_SIZE,
23100 + PCI_DMA_FROMDEVICE);
23101 + ps_page->dma = 0;
23102 + put_page(ps_page->page);
23103 + ps_page->page = NULL;
23107 +#ifdef CONFIG_E1000E_NAPI
23108 + /* there also may be some cached data from a chained receive */
23109 + if (rx_ring->rx_skb_top) {
23110 + dev_kfree_skb(rx_ring->rx_skb_top);
23111 + rx_ring->rx_skb_top = NULL;
23115 + /* Zero out the descriptor ring */
23116 + memset(rx_ring->desc, 0, rx_ring->size);
23118 + rx_ring->next_to_clean = 0;
23119 + rx_ring->next_to_use = 0;
23121 + writel(0, adapter->hw.hw_addr + rx_ring->head);
23122 + writel(0, adapter->hw.hw_addr + rx_ring->tail);
23125 +static void e1000e_downshift_workaround(struct work_struct *work)
23127 + struct e1000_adapter *adapter = container_of(work,
23128 + struct e1000_adapter, downshift_task);
23130 + e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
23133 +#ifndef CONFIG_E1000E_NAPI
23134 +static void e1000_set_itr(struct e1000_adapter *adapter);
23137 + * e1000_intr_msi - Interrupt Handler
23138 + * @irq: interrupt number
23139 + * @data: pointer to a network interface device structure
23141 +static irqreturn_t e1000_intr_msi(int irq, void *data)
23143 + struct net_device *netdev = data;
23144 + struct e1000_adapter *adapter = netdev_priv(netdev);
23145 + struct e1000_hw *hw = &adapter->hw;
23146 +#ifndef CONFIG_E1000E_NAPI
23149 + u32 icr = er32(ICR);
23152 + * read ICR disables interrupts using IAM
23155 + if (icr & E1000_ICR_LSC) {
23156 + hw->mac.get_link_status = 1;
23158 + * ICH8 workaround-- Call gig speed drop workaround on cable
23159 + * disconnect (LSC) before accessing any PHY registers
23161 + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
23162 + (!(er32(STATUS) & E1000_STATUS_LU)))
23163 + schedule_work(&adapter->downshift_task);
23166 + * 80003ES2LAN workaround-- For packet buffer work-around on
23167 + * link down event; disable receives here in the ISR and reset
23168 + * adapter in watchdog
23170 + if (netif_carrier_ok(netdev) &&
23171 + adapter->flags & FLAG_RX_NEEDS_RESTART) {
23172 + /* disable receives */
23173 + u32 rctl = er32(RCTL);
23174 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
23175 + adapter->flags |= FLAG_RX_RESTART_NOW;
23177 + /* guard against interrupt when we're going down */
23178 + if (!test_bit(__E1000_DOWN, &adapter->state))
23179 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
23182 +#ifdef CONFIG_E1000E_NAPI
23183 + if (napi_schedule_prep(&adapter->napi)) {
23184 + adapter->total_tx_bytes = 0;
23185 + adapter->total_tx_packets = 0;
23186 + adapter->total_rx_bytes = 0;
23187 + adapter->total_rx_packets = 0;
23188 + __napi_schedule(&adapter->napi);
23191 + adapter->total_tx_bytes = 0;
23192 + adapter->total_rx_bytes = 0;
23193 + adapter->total_tx_packets = 0;
23194 + adapter->total_rx_packets = 0;
23196 + for (i = 0; i < E1000_MAX_INTR; i++) {
23197 + int rx_cleaned = adapter->clean_rx(adapter);
23198 + int tx_cleaned_complete = e1000_clean_tx_irq(adapter);
23199 + if (!rx_cleaned && tx_cleaned_complete)
23203 + if (likely(adapter->itr_setting & 3))
23204 + e1000_set_itr(adapter);
23205 +#endif /* CONFIG_E1000E_NAPI */
23207 + return IRQ_HANDLED;
23211 + * e1000_intr - Interrupt Handler
23212 + * @irq: interrupt number
23213 + * @data: pointer to a network interface device structure
23215 +static irqreturn_t e1000_intr(int irq, void *data)
23217 + struct net_device *netdev = data;
23218 + struct e1000_adapter *adapter = netdev_priv(netdev);
23219 + struct e1000_hw *hw = &adapter->hw;
23220 +#ifndef CONFIG_E1000E_NAPI
23222 + int rx_cleaned, tx_cleaned_complete;
23224 + u32 rctl, icr = er32(ICR);
23226 + if (!icr || test_bit(__E1000_DOWN, &adapter->state))
23227 + return IRQ_NONE; /* Not our interrupt */
23229 +#ifdef CONFIG_E1000E_NAPI
23231 + * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
23232 + * not set, then the adapter didn't send an interrupt
23234 + if (!(icr & E1000_ICR_INT_ASSERTED))
23237 +#endif /* CONFIG_E1000E_NAPI */
23239 + * Interrupt Auto-Mask...upon reading ICR,
23240 + * interrupts are masked. No need for the
23244 + if (icr & E1000_ICR_LSC) {
23245 + hw->mac.get_link_status = 1;
23247 + * ICH8 workaround-- Call gig speed drop workaround on cable
23248 + * disconnect (LSC) before accessing any PHY registers
23250 + if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
23251 + (!(er32(STATUS) & E1000_STATUS_LU)))
23252 + schedule_work(&adapter->downshift_task);
23255 + * 80003ES2LAN workaround--
23256 + * For packet buffer work-around on link down event;
23257 + * disable receives here in the ISR and
23258 + * reset adapter in watchdog
23260 + if (netif_carrier_ok(netdev) &&
23261 + (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
23262 + /* disable receives */
23263 + rctl = er32(RCTL);
23264 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
23265 + adapter->flags |= FLAG_RX_RESTART_NOW;
23267 + /* guard against interrupt when we're going down */
23268 + if (!test_bit(__E1000_DOWN, &adapter->state))
23269 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
23272 +#ifdef CONFIG_E1000E_NAPI
23273 + if (napi_schedule_prep(&adapter->napi)) {
23274 + adapter->total_tx_bytes = 0;
23275 + adapter->total_tx_packets = 0;
23276 + adapter->total_rx_bytes = 0;
23277 + adapter->total_rx_packets = 0;
23278 + __napi_schedule(&adapter->napi);
23281 + adapter->total_tx_bytes = 0;
23282 + adapter->total_rx_bytes = 0;
23283 + adapter->total_tx_packets = 0;
23284 + adapter->total_rx_packets = 0;
23286 + for (i = 0; i < E1000_MAX_INTR; i++) {
23287 + rx_cleaned = adapter->clean_rx(adapter);
23288 + tx_cleaned_complete = e1000_clean_tx_irq(adapter);
23289 + if (!rx_cleaned && tx_cleaned_complete)
23293 + if (likely(adapter->itr_setting & 3))
23294 + e1000_set_itr(adapter);
23295 +#endif /* CONFIG_E1000E_NAPI */
23297 + return IRQ_HANDLED;
23300 +#ifdef CONFIG_E1000E_MSIX
23301 +static irqreturn_t e1000_msix_other(int irq, void *data)
23303 + struct net_device *netdev = data;
23304 + struct e1000_adapter *adapter = netdev_priv(netdev);
23305 + struct e1000_hw *hw = &adapter->hw;
23306 + u32 icr = er32(ICR);
23308 + if (!(icr & E1000_ICR_INT_ASSERTED)) {
23309 + ew32(IMS, E1000_IMS_OTHER);
23313 + if (icr & adapter->eiac_mask)
23314 + ew32(ICS, (icr & adapter->eiac_mask));
23316 + if (icr & E1000_ICR_OTHER) {
23317 + if (!(icr & E1000_ICR_LSC))
23318 + goto no_link_interrupt;
23319 + hw->mac.get_link_status = 1;
23320 + /* guard against interrupt when we're going down */
23321 + if (!test_bit(__E1000_DOWN, &adapter->state))
23322 + mod_timer(&adapter->watchdog_timer, jiffies + 1);
23325 +no_link_interrupt:
23326 + ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
23328 + return IRQ_HANDLED;
23332 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
23333 +static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
23335 + struct net_device *netdev = data;
23336 + struct e1000_adapter *adapter = netdev_priv(netdev);
23337 + struct e1000_hw *hw = &adapter->hw;
23338 + struct e1000_ring *tx_ring = adapter->tx_ring;
23341 + adapter->total_tx_bytes = 0;
23342 + adapter->total_tx_packets = 0;
23344 + if (!e1000_clean_tx_irq(adapter))
23345 + /* Ring was not completely cleaned, so fire another interrupt */
23346 + ew32(ICS, tx_ring->ims_val);
23348 + return IRQ_HANDLED;
23351 +#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */
23352 +static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
23354 + struct net_device *netdev = data;
23355 + struct e1000_adapter *adapter = netdev_priv(netdev);
23356 +#ifndef CONFIG_E1000E_NAPI
23358 + struct e1000_hw *hw = &adapter->hw;
23361 + /* Write the ITR value calculated at the end of the
23362 + * previous interrupt.
23364 + if (adapter->rx_ring->set_itr) {
23365 + writel(1000000000 / (adapter->rx_ring->itr_val * 256),
23366 + adapter->hw.hw_addr + adapter->rx_ring->itr_register);
23367 + adapter->rx_ring->set_itr = 0;
23370 +#ifdef CONFIG_E1000E_NAPI
23371 + if (napi_schedule_prep(&adapter->napi)) {
23372 + adapter->total_rx_bytes = 0;
23373 + adapter->total_rx_packets = 0;
23374 +#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER
23375 + adapter->total_tx_bytes = 0;
23376 + adapter->total_tx_packets = 0;
23377 +#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */
23378 + __napi_schedule(&adapter->napi);
23381 + adapter->total_rx_bytes = 0;
23382 + adapter->total_rx_packets = 0;
23383 +#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER
23384 + adapter->total_tx_bytes = 0;
23385 + adapter->total_tx_packets = 0;
23388 + for (i = 0; i < E1000_MAX_INTR; i++) {
23389 + int rx_cleaned = adapter->clean_rx(adapter);
23390 +#ifndef CONFIG_E1000E_SEPARATE_TX_HANDLER
23391 + int tx_cleaned_complete = e1000_clean_tx_irq(adapter);
23392 + if (!rx_cleaned && tx_cleaned_complete)
23398 + /* If we got here, the ring was not completely cleaned,
23399 + * so fire another interrupt.
23401 + ew32(ICS, adapter->rx_ring->ims_val);
23404 +#endif /* CONFIG_E1000E_NAPI */
23405 + return IRQ_HANDLED;
23409 + * e1000_configure_msix - Configure MSI-X hardware
23411 + * e1000_configure_msix sets up the hardware to properly
23412 + * generate MSI-X interrupts.
23414 +static void e1000_configure_msix(struct e1000_adapter *adapter)
23416 + struct e1000_hw *hw = &adapter->hw;
23417 + struct e1000_ring *rx_ring = adapter->rx_ring;
23418 + struct e1000_ring *tx_ring = adapter->tx_ring;
23420 + u32 ctrl_ext, ivar = 0;
23422 + adapter->eiac_mask = 0;
23424 + /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
23425 + if (hw->mac.type == e1000_82574) {
23426 + u32 rfctl = er32(RFCTL);
23427 + rfctl |= E1000_RFCTL_ACK_DIS;
23428 + ew32(RFCTL, rfctl);
23431 +#define E1000_IVAR_INT_ALLOC_VALID 0x8
23432 + /* Configure Rx vector */
23433 + rx_ring->ims_val = E1000_IMS_RXQ0;
23434 + adapter->eiac_mask |= rx_ring->ims_val;
23435 + if (rx_ring->itr_val)
23436 + writel(1000000000 / (rx_ring->itr_val * 256),
23437 + hw->hw_addr + rx_ring->itr_register);
23439 + writel(1, hw->hw_addr + rx_ring->itr_register);
23440 + ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
23442 + /* Configure Tx vector */
23443 + tx_ring->ims_val = E1000_IMS_TXQ0;
23444 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
23446 + if (tx_ring->itr_val)
23447 + writel(1000000000 / (tx_ring->itr_val * 256),
23448 + hw->hw_addr + tx_ring->itr_register);
23450 + writel(1, hw->hw_addr + tx_ring->itr_register);
23452 + rx_ring->ims_val |= tx_ring->ims_val;
23454 + adapter->eiac_mask |= tx_ring->ims_val;
23455 + ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
23457 + /* set vector for Other Causes, e.g. link changes */
23459 + ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
23460 + if (rx_ring->itr_val)
23461 + writel(1000000000 / (rx_ring->itr_val * 256),
23462 + hw->hw_addr + E1000_EITR_82574(vector));
23464 + writel(1, hw->hw_addr + E1000_EITR_82574(vector));
23466 + /* Cause Tx interrupts on every write back */
23467 + ivar |= (1 << 31);
23469 + ew32(IVAR, ivar);
23471 + /* enable MSI-X PBA support */
23472 + ctrl_ext = er32(CTRL_EXT);
23473 + ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
23475 + /* Auto-Mask Other interrupts upon ICR read */
23476 + ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
23477 + ctrl_ext |= E1000_CTRL_EXT_EIAME;
23478 + ew32(CTRL_EXT, ctrl_ext);
23482 +void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
23484 + if (adapter->msix_entries) {
23485 + pci_disable_msix(adapter->pdev);
23486 + kfree(adapter->msix_entries);
23487 + adapter->msix_entries = NULL;
23488 + } else if (adapter->flags & FLAG_MSI_ENABLED) {
23489 + pci_disable_msi(adapter->pdev);
23490 + adapter->flags &= ~FLAG_MSI_ENABLED;
23497 + * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
23499 + * Attempt to configure interrupts using the best available
23500 + * capabilities of the hardware and kernel.
23502 +void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
23508 + switch (adapter->int_mode) {
23509 + case E1000E_INT_MODE_MSIX:
23510 + if (adapter->flags & FLAG_HAS_MSIX) {
23511 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
23512 + numvecs = 3; /* RxQ0, TxQ0 and other */
23514 + numvecs = 2; /* RxQ0/TxQ0 and other */
23516 + adapter->msix_entries = kcalloc(numvecs,
23517 + sizeof(struct msix_entry),
23519 + if (adapter->msix_entries) {
23520 + for (i = 0; i < numvecs; i++)
23521 + adapter->msix_entries[i].entry = i;
23523 + err = pci_enable_msix(adapter->pdev,
23524 + adapter->msix_entries,
23529 + /* MSI-X failed, so fall through and try MSI */
23530 + e_err("Failed to initialize MSI-X interrupts. "
23531 + "Falling back to MSI interrupts.\n");
23532 + e1000e_reset_interrupt_capability(adapter);
23534 + adapter->int_mode = E1000E_INT_MODE_MSI;
23535 + /* Fall through */
23536 + case E1000E_INT_MODE_MSI:
23537 + if (!pci_enable_msi(adapter->pdev)) {
23538 + adapter->flags |= FLAG_MSI_ENABLED;
23540 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
23541 + e_err("Failed to initialize MSI interrupts. Falling "
23542 + "back to legacy interrupts.\n");
23544 + /* Fall through */
23545 + case E1000E_INT_MODE_LEGACY:
23546 + /* Don't do anything; this is the system default */
23554 + * e1000_request_msix - Initialize MSI-X interrupts
23556 + * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
23559 +static int e1000_request_msix(struct e1000_adapter *adapter)
23561 + struct net_device *netdev = adapter->netdev;
23562 + int err = 0, vector = 0;
23564 + if (strlen(netdev->name) < (IFNAMSIZ - 5))
23565 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
23566 + sprintf(adapter->rx_ring->name, "%s-rx-0", netdev->name);
23568 + sprintf(adapter->rx_ring->name, "%s-Q0", netdev->name);
23571 + memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
23572 + err = request_irq(adapter->msix_entries[vector].vector,
23573 + &e1000_intr_msix_rx, 0, adapter->rx_ring->name,
23577 + adapter->rx_ring->itr_register = E1000_EITR_82574(vector);
23578 + adapter->rx_ring->itr_val = adapter->itr;
23581 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
23582 + if (strlen(netdev->name) < (IFNAMSIZ - 5))
23583 + sprintf(adapter->tx_ring->name, "%s-tx-0", netdev->name);
23585 + memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
23586 + err = request_irq(adapter->msix_entries[vector].vector,
23587 + &e1000_intr_msix_tx, 0, adapter->tx_ring->name,
23591 + adapter->tx_ring->itr_register = E1000_EITR_82574(vector);
23592 + adapter->tx_ring->itr_val = adapter->itr;
23595 +#endif /* CONFIG_E1000E_SEPARATE_TX_HANDLER */
23596 + err = request_irq(adapter->msix_entries[vector].vector,
23597 + &e1000_msix_other, 0, netdev->name, netdev);
23601 + e1000_configure_msix(adapter);
23607 +#endif /* CONFIG_E1000E_MSIX */
23609 + * e1000_request_irq - initialize interrupts
23611 + * Attempts to configure interrupts using the best available
23612 + * capabilities of the hardware and kernel.
23614 +static int e1000_request_irq(struct e1000_adapter *adapter)
23616 + struct net_device *netdev = adapter->netdev;
23617 +#ifndef CONFIG_E1000E_MSIX
23618 + int irq_flags = IRQF_SHARED;
23622 +#ifdef CONFIG_E1000E_MSIX
23623 + if (adapter->msix_entries) {
23624 + err = e1000_request_msix(adapter);
23627 + /* fall back to MSI */
23628 + e1000e_reset_interrupt_capability(adapter);
23629 + adapter->int_mode = E1000E_INT_MODE_MSI;
23630 + e1000e_set_interrupt_capability(adapter);
23632 + if (adapter->flags & FLAG_MSI_ENABLED) {
23633 + err = request_irq(adapter->pdev->irq, &e1000_intr_msi, 0,
23634 + netdev->name, netdev);
23638 + /* fall back to legacy interrupt */
23639 + e1000e_reset_interrupt_capability(adapter);
23640 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
23643 + err = request_irq(adapter->pdev->irq, &e1000_intr, IRQF_SHARED,
23644 + netdev->name, netdev);
23646 + e_err("Unable to allocate interrupt, Error: %d\n", err);
23648 + if (!(adapter->flags & FLAG_MSI_TEST_FAILED)) {
23649 + err = pci_enable_msi(adapter->pdev);
23651 + adapter->flags |= FLAG_MSI_ENABLED;
23656 + err = request_irq(adapter->pdev->irq,
23657 + ((adapter->flags & FLAG_MSI_ENABLED) ?
23658 + &e1000_intr_msi : &e1000_intr),
23659 + irq_flags, netdev->name, netdev);
23661 + if (adapter->flags & FLAG_MSI_ENABLED) {
23662 + pci_disable_msi(adapter->pdev);
23663 + adapter->flags &= ~FLAG_MSI_ENABLED;
23665 + e_err("Unable to allocate interrupt, Error: %d\n", err);
23667 +#endif /* CONFIG_E1000E_MSIX */
23672 +static void e1000_free_irq(struct e1000_adapter *adapter)
23674 + struct net_device *netdev = adapter->netdev;
23676 +#ifdef CONFIG_E1000E_MSIX
23677 + if (adapter->msix_entries) {
23680 + free_irq(adapter->msix_entries[vector].vector, netdev);
23683 +#ifdef CONFIG_E1000E_SEPARATE_TX_HANDLER
23684 + free_irq(adapter->msix_entries[vector].vector, netdev);
23688 + /* Other Causes interrupt vector */
23689 + free_irq(adapter->msix_entries[vector].vector, netdev);
23693 +#endif /* CONFIG_E1000E_MSIX */
23694 + free_irq(adapter->pdev->irq, netdev);
23695 +#ifndef CONFIG_E1000E_MSIX
23696 + if (adapter->flags & FLAG_MSI_ENABLED) {
23697 + pci_disable_msi(adapter->pdev);
23698 + adapter->flags &= ~FLAG_MSI_ENABLED;
23704 + * e1000_irq_disable - Mask off interrupt generation on the NIC
23706 +static void e1000_irq_disable(struct e1000_adapter *adapter)
23708 + struct e1000_hw *hw = &adapter->hw;
23711 +#ifdef CONFIG_E1000E_MSIX
23712 + if (adapter->msix_entries)
23713 + ew32(EIAC_82574, 0);
23714 +#endif /* CONFIG_E1000E_MSIX */
23716 + synchronize_irq(adapter->pdev->irq);
23720 + * e1000_irq_enable - Enable default interrupt generation settings
23722 +static void e1000_irq_enable(struct e1000_adapter *adapter)
23724 + struct e1000_hw *hw = &adapter->hw;
23726 +#ifdef CONFIG_E1000E_MSIX
23727 + if (adapter->msix_entries) {
23728 + ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
23729 + ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
23731 + ew32(IMS, IMS_ENABLE_MASK);
23734 + ew32(IMS, IMS_ENABLE_MASK);
23735 +#endif /* CONFIG_E1000E_MSIX */
23740 + * e1000_get_hw_control - get control of the h/w from f/w
23741 + * @adapter: address of board private structure
23743 + * e1000_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
23744 + * For ASF and Pass Through versions of f/w this means that
23745 + * the driver is loaded. For AMT version (only with 82573)
23746 + * of the f/w this means that the network i/f is open.
23748 +static void e1000_get_hw_control(struct e1000_adapter *adapter)
23750 + struct e1000_hw *hw = &adapter->hw;
23754 + /* Let firmware know the driver has taken over */
23755 + if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
23756 + swsm = er32(SWSM);
23757 + ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
23758 + } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
23759 + ctrl_ext = er32(CTRL_EXT);
23760 + ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
23765 + * e1000_release_hw_control - release control of the h/w to f/w
23766 + * @adapter: address of board private structure
23768 + * e1000_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
23769 + * For ASF and Pass Through versions of f/w this means that the
23770 + * driver is no longer loaded. For AMT version (only with 82573) i
23771 + * of the f/w this means that the network i/f is closed.
23774 +static void e1000_release_hw_control(struct e1000_adapter *adapter)
23776 + struct e1000_hw *hw = &adapter->hw;
23780 + /* Let firmware taken over control of h/w */
23781 + if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
23782 + swsm = er32(SWSM);
23783 + ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
23784 + } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
23785 + ctrl_ext = er32(CTRL_EXT);
23786 + ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
23791 + * @e1000_alloc_ring - allocate memory for a ring structure
23793 +static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
23794 + struct e1000_ring *ring)
23796 + struct pci_dev *pdev = adapter->pdev;
23798 + ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
23807 + * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
23808 + * @adapter: board private structure
23810 + * Return 0 on success, negative on failure
23812 +int e1000e_setup_tx_resources(struct e1000_adapter *adapter)
23814 + struct e1000_ring *tx_ring = adapter->tx_ring;
23815 + int err = -ENOMEM, size;
23817 + size = sizeof(struct e1000_buffer) * tx_ring->count;
23818 + tx_ring->buffer_info = vmalloc(size);
23819 + if (!tx_ring->buffer_info)
23821 + memset(tx_ring->buffer_info, 0, size);
23823 + /* round up to nearest 4K */
23824 + tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
23825 + tx_ring->size = ALIGN(tx_ring->size, 4096);
23827 + err = e1000_alloc_ring_dma(adapter, tx_ring);
23831 + tx_ring->next_to_use = 0;
23832 + tx_ring->next_to_clean = 0;
23836 + vfree(tx_ring->buffer_info);
23837 + e_err("Unable to allocate memory for the transmit descriptor ring\n");
23842 + * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
23843 + * @adapter: board private structure
23845 + * Returns 0 on success, negative on failure
23847 +int e1000e_setup_rx_resources(struct e1000_adapter *adapter)
23849 + struct e1000_ring *rx_ring = adapter->rx_ring;
23850 + struct e1000_buffer *buffer_info;
23851 + int i, size, desc_len, err = -ENOMEM;
23853 + size = sizeof(struct e1000_buffer) * rx_ring->count;
23854 + rx_ring->buffer_info = vmalloc(size);
23855 + if (!rx_ring->buffer_info)
23857 + memset(rx_ring->buffer_info, 0, size);
23859 + for (i = 0; i < rx_ring->count; i++) {
23860 + buffer_info = &rx_ring->buffer_info[i];
23861 + buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
23862 + sizeof(struct e1000_ps_page),
23864 + if (!buffer_info->ps_pages)
23868 + desc_len = sizeof(union e1000_rx_desc_packet_split);
23870 + /* Round up to nearest 4K */
23871 + rx_ring->size = rx_ring->count * desc_len;
23872 + rx_ring->size = ALIGN(rx_ring->size, 4096);
23874 + err = e1000_alloc_ring_dma(adapter, rx_ring);
23878 + rx_ring->next_to_clean = 0;
23879 + rx_ring->next_to_use = 0;
23880 + rx_ring->rx_skb_top = NULL;
23885 + for (i = 0; i < rx_ring->count; i++) {
23886 + buffer_info = &rx_ring->buffer_info[i];
23887 + kfree(buffer_info->ps_pages);
23890 + vfree(rx_ring->buffer_info);
23891 + e_err("Unable to allocate memory for the receive descriptor ring\n");
23896 + * e1000_clean_tx_ring - Free Tx Buffers
23897 + * @adapter: board private structure
23899 +static void e1000_clean_tx_ring(struct e1000_adapter *adapter)
23901 + struct e1000_ring *tx_ring = adapter->tx_ring;
23902 + struct e1000_buffer *buffer_info;
23903 + unsigned long size;
23906 + for (i = 0; i < tx_ring->count; i++) {
23907 + buffer_info = &tx_ring->buffer_info[i];
23908 + e1000_put_txbuf(adapter, buffer_info);
23911 + size = sizeof(struct e1000_buffer) * tx_ring->count;
23912 + memset(tx_ring->buffer_info, 0, size);
23914 + memset(tx_ring->desc, 0, tx_ring->size);
23916 + tx_ring->next_to_use = 0;
23917 + tx_ring->next_to_clean = 0;
23919 + writel(0, adapter->hw.hw_addr + tx_ring->head);
23920 + writel(0, adapter->hw.hw_addr + tx_ring->tail);
23924 + * e1000e_free_tx_resources - Free Tx Resources per Queue
23925 + * @adapter: board private structure
23927 + * Free all transmit software resources
23929 +void e1000e_free_tx_resources(struct e1000_adapter *adapter)
23931 + struct pci_dev *pdev = adapter->pdev;
23932 + struct e1000_ring *tx_ring = adapter->tx_ring;
23934 + e1000_clean_tx_ring(adapter);
23936 + vfree(tx_ring->buffer_info);
23937 + tx_ring->buffer_info = NULL;
23939 + dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
23941 + tx_ring->desc = NULL;
23945 + * e1000e_free_rx_resources - Free Rx Resources
23946 + * @adapter: board private structure
23948 + * Free all receive software resources
23951 +void e1000e_free_rx_resources(struct e1000_adapter *adapter)
23953 + struct pci_dev *pdev = adapter->pdev;
23954 + struct e1000_ring *rx_ring = adapter->rx_ring;
23957 + e1000_clean_rx_ring(adapter);
23959 + for (i = 0; i < rx_ring->count; i++) {
23960 + kfree(rx_ring->buffer_info[i].ps_pages);
23963 + vfree(rx_ring->buffer_info);
23964 + rx_ring->buffer_info = NULL;
23966 + dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
23968 + rx_ring->desc = NULL;
23972 + * e1000_update_itr - update the dynamic ITR value based on statistics
23973 + * @adapter: pointer to adapter
23974 + * @itr_setting: current adapter->itr
23975 + * @packets: the number of packets during this measurement interval
23976 + * @bytes: the number of bytes during this measurement interval
23978 + * Stores a new ITR value based on packets and byte
23979 + * counts during the last interrupt. The advantage of per interrupt
23980 + * computation is faster updates and more accurate ITR for the current
23981 + * traffic pattern. Constants in this function were computed
23982 + * based on theoretical maximum wire speed and thresholds were set based
23983 + * on testing data as well as attempting to minimize response time
23984 + * while increasing bulk throughput. This functionality is controlled
23985 + * by the InterruptThrottleRate module parameter.
23987 +static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
23988 + u16 itr_setting, int packets,
23991 + unsigned int retval = itr_setting;
23993 + if (packets == 0)
23994 + goto update_itr_done;
23996 + switch (itr_setting) {
23997 + case lowest_latency:
23998 + /* handle TSO and jumbo frames */
23999 + if (bytes/packets > 8000)
24000 + retval = bulk_latency;
24001 + else if ((packets < 5) && (bytes > 512)) {
24002 + retval = low_latency;
24005 + case low_latency: /* 50 usec aka 20000 ints/s */
24006 + if (bytes > 10000) {
24007 + /* this if handles the TSO accounting */
24008 + if (bytes/packets > 8000) {
24009 + retval = bulk_latency;
24010 + } else if ((packets < 10) || ((bytes/packets) > 1200)) {
24011 + retval = bulk_latency;
24012 + } else if ((packets > 35)) {
24013 + retval = lowest_latency;
24015 + } else if (bytes/packets > 2000) {
24016 + retval = bulk_latency;
24017 + } else if (packets <= 2 && bytes < 512) {
24018 + retval = lowest_latency;
24021 + case bulk_latency: /* 250 usec aka 4000 ints/s */
24022 + if (bytes > 25000) {
24023 + if (packets > 35) {
24024 + retval = low_latency;
24026 + } else if (bytes < 6000) {
24027 + retval = low_latency;
24036 +static void e1000_set_itr(struct e1000_adapter *adapter)
24038 + struct e1000_hw *hw = &adapter->hw;
24040 + u32 new_itr = adapter->itr;
24042 + /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
24043 + if (adapter->link_speed != SPEED_1000) {
24046 + goto set_itr_now;
24049 + adapter->tx_itr = e1000_update_itr(adapter,
24051 + adapter->total_tx_packets,
24052 + adapter->total_tx_bytes);
24053 + /* conservative mode (itr 3) eliminates the lowest_latency setting */
24054 + if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
24055 + adapter->tx_itr = low_latency;
24057 + adapter->rx_itr = e1000_update_itr(adapter,
24059 + adapter->total_rx_packets,
24060 + adapter->total_rx_bytes);
24061 + /* conservative mode (itr 3) eliminates the lowest_latency setting */
24062 + if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
24063 + adapter->rx_itr = low_latency;
24065 + current_itr = max(adapter->rx_itr, adapter->tx_itr);
24067 + switch (current_itr) {
24068 + /* counts and packets in update_itr are dependent on these numbers */
24069 + case lowest_latency:
24072 + case low_latency:
24073 + new_itr = 20000; /* aka hwitr = ~200 */
24075 + case bulk_latency:
24083 + if (new_itr != adapter->itr) {
24085 + * this attempts to bias the interrupt rate towards Bulk
24086 + * by adding intermediate steps when interrupt rate is
24089 + new_itr = new_itr > adapter->itr ?
24090 + min(adapter->itr + (new_itr >> 2), new_itr) :
24092 + adapter->itr = new_itr;
24093 +#ifdef CONFIG_E1000E_MSIX
24094 + adapter->rx_ring->itr_val = new_itr;
24095 + if (adapter->msix_entries)
24096 + adapter->rx_ring->set_itr = 1;
24098 + ew32(ITR, 1000000000 / (new_itr * 256));
24100 + ew32(ITR, 1000000000 / (new_itr * 256));
24106 + * e1000_alloc_queues - Allocate memory for all rings
24107 + * @adapter: board private structure to initialize
24109 +static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
24111 + adapter->tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
24112 + if (!adapter->tx_ring)
24115 + adapter->rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
24116 + if (!adapter->rx_ring)
24121 + e_err("Unable to allocate memory for queues\n");
24122 + kfree(adapter->rx_ring);
24123 + kfree(adapter->tx_ring);
24127 +#ifdef CONFIG_E1000E_NAPI
24129 + * e1000_poll - NAPI Rx polling callback
24130 + * @napi: struct associated with this polling callback
24131 + * @budget: amount of packets driver is allowed to process this poll
24133 +static int e1000_poll(struct napi_struct *napi, int budget)
24135 + struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
24137 + int tx_clean_complete = 1, work_done = 0;
24138 +#ifdef CONFIG_E1000E_MSIX
24139 + struct e1000_hw *hw = &adapter->hw;
24142 +#ifdef CONFIG_E1000E_MSIX
24143 + if (!adapter->msix_entries ||
24144 + (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
24146 + tx_clean_complete = e1000_clean_tx_irq(adapter);
24148 + adapter->clean_rx(adapter, &work_done, budget);
24150 + if (!tx_clean_complete)
24151 + work_done = budget;
24153 +#ifndef HAVE_NETDEV_NAPI_LIST
24154 + if (!netif_running(adapter->netdev))
24158 + /* If Tx completed and all Rx work done, exit the polling mode */
24159 + if (work_done < budget) {
24160 + napi_complete(napi);
24161 + if (adapter->itr_setting & 3)
24162 + e1000_set_itr(adapter);
24163 + if (!test_bit(__E1000_DOWN, &adapter->state)) {
24164 +#ifdef CONFIG_E1000E_MSIX
24165 + if (adapter->msix_entries)
24166 + ew32(IMS, adapter->rx_ring->ims_val);
24169 + e1000_irq_enable(adapter);
24173 + return work_done;
24176 +#endif /* CONFIG_E1000E_NAPI */
24177 +static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
24179 + struct e1000_adapter *adapter = netdev_priv(netdev);
24180 + struct e1000_hw *hw = &adapter->hw;
24182 + struct net_device *v_netdev;
24184 + /* don't update vlan cookie if already programmed */
24185 + if ((adapter->hw.mng_cookie.status &
24186 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
24187 + (vid == adapter->mng_vlan_id))
24189 + /* add VID to filter table */
24190 + index = (vid >> 5) & 0x7F;
24191 + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
24192 + vfta |= (1 << (vid & 0x1F));
24193 + e1000e_write_vfta(hw, index, vfta);
24195 + * Copy feature flags from netdev to the vlan netdev for this vid.
24196 + * This allows things like TSO to bubble down to our vlan device.
24198 + v_netdev = vlan_group_get_device(adapter->vlgrp, vid);
24199 + v_netdev->features |= adapter->netdev->features;
24200 + vlan_group_set_device(adapter->vlgrp, vid, v_netdev);
24203 +static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
24205 + struct e1000_adapter *adapter = netdev_priv(netdev);
24206 + struct e1000_hw *hw = &adapter->hw;
24209 + if (!test_bit(__E1000_DOWN, &adapter->state))
24210 + e1000_irq_disable(adapter);
24211 + vlan_group_set_device(adapter->vlgrp, vid, NULL);
24213 + if (!test_bit(__E1000_DOWN, &adapter->state))
24214 + e1000_irq_enable(adapter);
24216 + if ((adapter->hw.mng_cookie.status &
24217 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
24218 + (vid == adapter->mng_vlan_id)) {
24219 + /* release control to f/w */
24220 + e1000_release_hw_control(adapter);
24224 + /* remove VID from filter table */
24225 + index = (vid >> 5) & 0x7F;
24226 + vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
24227 + vfta &= ~(1 << (vid & 0x1F));
24228 + e1000e_write_vfta(hw, index, vfta);
24231 +static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
24233 + struct net_device *netdev = adapter->netdev;
24234 + u16 vid = adapter->hw.mng_cookie.vlan_id;
24235 + u16 old_vid = adapter->mng_vlan_id;
24237 + if (!adapter->vlgrp)
24240 + if (!vlan_group_get_device(adapter->vlgrp, vid)) {
24241 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
24242 + if (adapter->hw.mng_cookie.status &
24243 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
24244 + e1000_vlan_rx_add_vid(netdev, vid);
24245 + adapter->mng_vlan_id = vid;
24248 + if ((old_vid != (u16)E1000_MNG_VLAN_NONE) &&
24249 + (vid != old_vid) &&
24250 + !vlan_group_get_device(adapter->vlgrp, old_vid))
24251 + e1000_vlan_rx_kill_vid(netdev, old_vid);
24253 + adapter->mng_vlan_id = vid;
24258 +static void e1000_vlan_rx_register(struct net_device *netdev,
24259 + struct vlan_group *grp)
24261 + struct e1000_adapter *adapter = netdev_priv(netdev);
24262 + struct e1000_hw *hw = &adapter->hw;
24265 + if (!test_bit(__E1000_DOWN, &adapter->state))
24266 + e1000_irq_disable(adapter);
24267 + adapter->vlgrp = grp;
24270 + /* enable VLAN tag insert/strip */
24271 + ctrl = er32(CTRL);
24272 + ctrl |= E1000_CTRL_VME;
24273 + ew32(CTRL, ctrl);
24275 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
24276 + /* enable VLAN receive filtering */
24277 + rctl = er32(RCTL);
24278 + rctl &= ~E1000_RCTL_CFIEN;
24279 + ew32(RCTL, rctl);
24280 + e1000_update_mng_vlan(adapter);
24283 + /* disable VLAN tag insert/strip */
24284 + ctrl = er32(CTRL);
24285 + ctrl &= ~E1000_CTRL_VME;
24286 + ew32(CTRL, ctrl);
24288 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
24289 + if (adapter->mng_vlan_id !=
24290 + (u16)E1000_MNG_VLAN_NONE) {
24291 + e1000_vlan_rx_kill_vid(netdev,
24292 + adapter->mng_vlan_id);
24293 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
24298 + if (!test_bit(__E1000_DOWN, &adapter->state))
24299 + e1000_irq_enable(adapter);
24302 +static void e1000_restore_vlan(struct e1000_adapter *adapter)
24306 + e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
24308 + if (!adapter->vlgrp)
24311 + for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
24312 + if (!vlan_group_get_device(adapter->vlgrp, vid))
24314 + e1000_vlan_rx_add_vid(adapter->netdev, vid);
24318 +static void e1000_init_manageability(struct e1000_adapter *adapter)
24320 + struct e1000_hw *hw = &adapter->hw;
24321 + u32 manc, manc2h;
24323 + if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
24326 + manc = er32(MANC);
24329 + * enable receiving management packets to the host. this will probably
24330 + * generate destination unreachable messages from the host OS, but
24331 + * the packets will be handled on SMBUS
24333 + manc |= E1000_MANC_EN_MNG2HOST;
24334 + manc2h = er32(MANC2H);
24335 +#define E1000_MNG2HOST_PORT_623 (1 << 5)
24336 +#define E1000_MNG2HOST_PORT_664 (1 << 6)
24337 + manc2h |= E1000_MNG2HOST_PORT_623;
24338 + manc2h |= E1000_MNG2HOST_PORT_664;
24339 + ew32(MANC2H, manc2h);
24340 + ew32(MANC, manc);
24344 + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
24345 + * @adapter: board private structure
24347 + * Configure the Tx unit of the MAC after a reset.
24349 +static void e1000_configure_tx(struct e1000_adapter *adapter)
24351 + struct e1000_hw *hw = &adapter->hw;
24352 + struct e1000_ring *tx_ring = adapter->tx_ring;
24354 + u32 tdlen, tctl, tipg, tarc;
24355 + u32 ipgr1, ipgr2;
24357 + /* Setup the HW Tx Head and Tail descriptor pointers */
24358 + tdba = tx_ring->dma;
24359 + tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
24360 + ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
24361 + ew32(TDBAH(0), (tdba >> 32));
24362 + ew32(TDLEN(0), tdlen);
24365 + tx_ring->head = E1000_TDH(0);
24366 + tx_ring->tail = E1000_TDT(0);
24368 + /* Set the default values for the Tx Inter Packet Gap timer */
24369 + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */
24370 + ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */
24371 + ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */
24373 + if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
24374 + ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */
24376 + tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
24377 + tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
24378 + ew32(TIPG, tipg);
24380 + /* Set the Tx Interrupt Delay register */
24381 + ew32(TIDV, adapter->tx_int_delay);
24382 + /* Tx irq moderation */
24383 + ew32(TADV, adapter->tx_abs_int_delay);
24385 + /* Program the Transmit Control Register */
24386 + tctl = er32(TCTL);
24387 + tctl &= ~E1000_TCTL_CT;
24388 + tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
24389 + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
24391 + if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
24392 + tarc = er32(TARC(0));
24394 + * set the speed mode bit, we'll clear it if we're not at
24395 + * gigabit link later
24397 +#define SPEED_MODE_BIT (1 << 21)
24398 + tarc |= SPEED_MODE_BIT;
24399 + ew32(TARC(0), tarc);
24402 + /* errata: program both queues to unweighted RR */
24403 + if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
24404 + tarc = er32(TARC(0));
24406 + ew32(TARC(0), tarc);
24407 + tarc = er32(TARC(1));
24409 + ew32(TARC(1), tarc);
24412 + e1000e_config_collision_dist(hw);
24414 + /* Setup Transmit Descriptor Settings for eop descriptor */
24415 + adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
24417 + /* only set IDE if we are delaying interrupts using the timers */
24418 + if (adapter->tx_int_delay)
24419 + adapter->txd_cmd |= E1000_TXD_CMD_IDE;
24421 + /* enable Report Status bit */
24422 + adapter->txd_cmd |= E1000_TXD_CMD_RS;
24424 + ew32(TCTL, tctl);
24426 + adapter->tx_queue_len = adapter->netdev->tx_queue_len;
24430 + * e1000_setup_rctl - configure the receive control registers
24431 + * @adapter: Board private structure
24433 +#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
24434 + (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
24435 +static void e1000_setup_rctl(struct e1000_adapter *adapter)
24437 + struct e1000_hw *hw = &adapter->hw;
24442 + /* Program MC offset vector base */
24443 + rctl = er32(RCTL);
24444 + rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
24445 + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
24446 + E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
24447 + (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
24449 + /* Do not Store bad packets */
24450 + rctl &= ~E1000_RCTL_SBP;
24452 + /* Enable Long Packet receive */
24453 + if (adapter->netdev->mtu <= ETH_DATA_LEN)
24454 + rctl &= ~E1000_RCTL_LPE;
24456 + rctl |= E1000_RCTL_LPE;
24458 + /* Some systems expect that the CRC is included in SMBUS traffic. The
24459 + * hardware strips the CRC before sending to both SMBUS (BMC) and to
24460 + * host memory when this is enabled */
24461 + if (adapter->flags2 & FLAG2_CRC_STRIPPING)
24462 + rctl |= E1000_RCTL_SECRC;
24464 + /* Workaround Si errata on 82577 PHY */
24465 + if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
24468 + e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
24469 + phy_data &= 0xfff8;
24470 + phy_data |= (1 << 2);
24471 + e1e_wphy(hw, PHY_REG(770, 26), phy_data);
24473 + e1e_rphy(hw, 22, &phy_data);
24474 + phy_data &= 0x0fff;
24475 + phy_data |= (1 << 14);
24476 + e1e_wphy(hw, 0x10, 0x2823);
24477 + e1e_wphy(hw, 0x11, 0x0003);
24478 + e1e_wphy(hw, 22, phy_data);
24481 + /* Setup buffer sizes */
24482 + rctl &= ~E1000_RCTL_SZ_4096;
24483 + rctl |= E1000_RCTL_BSEX;
24484 + switch (adapter->rx_buffer_len) {
24486 + rctl |= E1000_RCTL_SZ_256;
24487 + rctl &= ~E1000_RCTL_BSEX;
24490 + rctl |= E1000_RCTL_SZ_512;
24491 + rctl &= ~E1000_RCTL_BSEX;
24494 + rctl |= E1000_RCTL_SZ_1024;
24495 + rctl &= ~E1000_RCTL_BSEX;
24499 + rctl |= E1000_RCTL_SZ_2048;
24500 + rctl &= ~E1000_RCTL_BSEX;
24503 + rctl |= E1000_RCTL_SZ_4096;
24506 + rctl |= E1000_RCTL_SZ_8192;
24509 + rctl |= E1000_RCTL_SZ_16384;
24514 + * 82571 and greater support packet-split where the protocol
24515 + * header is placed in skb->data and the packet data is
24516 + * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
24517 + * In the case of a non-split, skb->data is linearly filled,
24518 + * followed by the page buffers. Therefore, skb->data is
24519 + * sized to hold the largest protocol header.
24521 + * allocations using alloc_page take too long for regular MTU
24522 + * so only enable packet split for jumbo frames
24524 + * Using pages when the page size is greater than 16k wastes
24525 + * a lot of memory, since we allocate 3 pages at all times
24528 + pages = PAGE_USE_COUNT(adapter->netdev->mtu);
24529 + if (!(adapter->flags & FLAG_IS_ICH) && (pages <= 3) &&
24530 + (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
24531 + adapter->rx_ps_pages = pages;
24533 + adapter->rx_ps_pages = 0;
24535 + if (adapter->rx_ps_pages) {
24536 + /* Configure extra packet-split registers */
24537 + rfctl = er32(RFCTL);
24538 + rfctl |= E1000_RFCTL_EXTEN;
24540 + * disable packet split support for IPv6 extension headers,
24541 + * because some malformed IPv6 headers can hang the Rx
24543 + rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
24544 + E1000_RFCTL_NEW_IPV6_EXT_DIS);
24546 + ew32(RFCTL, rfctl);
24548 + /* Enable Packet split descriptors */
24549 + rctl |= E1000_RCTL_DTYP_PS;
24551 + psrctl |= adapter->rx_ps_bsize0 >>
24552 + E1000_PSRCTL_BSIZE0_SHIFT;
24554 + switch (adapter->rx_ps_pages) {
24556 + psrctl |= PAGE_SIZE <<
24557 + E1000_PSRCTL_BSIZE3_SHIFT;
24559 + psrctl |= PAGE_SIZE <<
24560 + E1000_PSRCTL_BSIZE2_SHIFT;
24562 + psrctl |= PAGE_SIZE >>
24563 + E1000_PSRCTL_BSIZE1_SHIFT;
24567 + ew32(PSRCTL, psrctl);
24570 + ew32(RCTL, rctl);
24571 + /* just started the receive unit, no need to restart */
24572 + adapter->flags &= ~FLAG_RX_RESTART_NOW;
24576 + * e1000_configure_rx - Configure Receive Unit after Reset
24577 + * @adapter: board private structure
24579 + * Configure the Rx unit of the MAC after a reset.
24581 +static void e1000_configure_rx(struct e1000_adapter *adapter)
24583 + struct e1000_hw *hw = &adapter->hw;
24584 + struct e1000_ring *rx_ring = adapter->rx_ring;
24586 + u32 rdlen, rctl, rxcsum, ctrl_ext;
24588 + if (adapter->rx_ps_pages) {
24589 + /* this is a 32 byte descriptor */
24590 + rdlen = rx_ring->count *
24591 + sizeof(union e1000_rx_desc_packet_split);
24592 + adapter->clean_rx = e1000_clean_rx_irq_ps;
24593 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
24594 +#ifdef CONFIG_E1000E_NAPI
24595 + } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
24596 + rdlen = rx_ring->count * sizeof(struct e1000_rx_desc);
24597 + adapter->clean_rx = e1000_clean_jumbo_rx_irq;
24598 + adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
24601 + rdlen = rx_ring->count * sizeof(struct e1000_rx_desc);
24602 + adapter->clean_rx = e1000_clean_rx_irq;
24603 + adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
24606 + /* disable receives while setting up the descriptors */
24607 + rctl = er32(RCTL);
24608 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
24612 + /* set the Receive Delay Timer Register */
24613 + ew32(RDTR, adapter->rx_int_delay);
24615 + /* irq moderation */
24616 + ew32(RADV, adapter->rx_abs_int_delay);
24617 + if (adapter->itr_setting != 0)
24618 + ew32(ITR, 1000000000 / (adapter->itr * 256));
24620 + ctrl_ext = er32(CTRL_EXT);
24621 +#ifdef CONFIG_E1000E_NAPI
24622 + /* Auto-Mask interrupts upon ICR access */
24623 + ctrl_ext |= E1000_CTRL_EXT_IAME;
24624 + ew32(IAM, 0xffffffff);
24626 + ew32(CTRL_EXT, ctrl_ext);
24630 + * Setup the HW Rx Head and Tail Descriptor Pointers and
24631 + * the Base and Length of the Rx Descriptor Ring
24633 + rdba = rx_ring->dma;
24634 + ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
24635 + ew32(RDBAH(0), (rdba >> 32));
24636 + ew32(RDLEN(0), rdlen);
24639 + rx_ring->head = E1000_RDH(0);
24640 + rx_ring->tail = E1000_RDT(0);
24642 + /* Enable Receive Checksum Offload for TCP and UDP */
24643 + rxcsum = er32(RXCSUM);
24644 + if (adapter->flags & FLAG_RX_CSUM_ENABLED) {
24645 + rxcsum |= E1000_RXCSUM_TUOFL;
24648 + * IPv4 payload checksum for UDP fragments must be
24649 + * used in conjunction with packet-split.
24651 + if (adapter->rx_ps_pages)
24652 + rxcsum |= E1000_RXCSUM_IPPCSE;
24654 + rxcsum &= ~E1000_RXCSUM_TUOFL;
24655 + /* no need to clear IPPCSE as it defaults to 0 */
24657 + ew32(RXCSUM, rxcsum);
24660 + * Enable early receives on supported devices, only takes effect when
24661 + * packet size is equal or larger than the specified value (in 8 byte
24662 + * units), e.g. using jumbo frames when setting to E1000_ERT_2048
24664 + if (adapter->flags & FLAG_HAS_ERT) {
24665 + if (adapter->netdev->mtu > ETH_DATA_LEN) {
24666 + u32 rxdctl = er32(RXDCTL(0));
24667 + ew32(RXDCTL(0), rxdctl | 0x3);
24668 + ew32(ERT, E1000_ERT_2048 | (1 << 13));
24670 + * With jumbo frames and early-receive enabled,
24671 + * excessive C-state transition latencies result in
24672 + * dropped transactions.
24674 + pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY,
24675 + adapter->netdev->name, 55);
24677 + pm_qos_update_requirement(PM_QOS_CPU_DMA_LATENCY,
24678 + adapter->netdev->name,
24679 + PM_QOS_DEFAULT_VALUE);
24683 + /* Enable Receives */
24684 + ew32(RCTL, rctl);
24688 + * e1000_update_mc_addr_list - Update Multicast addresses
24689 + * @hw: pointer to the HW structure
24690 + * @mc_addr_list: array of multicast addresses to program
24691 + * @mc_addr_count: number of multicast addresses to program
24693 + * Updates the Multicast Table Array.
24694 + * The caller must have a packed mc_addr_list of multicast addresses.
24696 +static void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
24697 + u32 mc_addr_count)
24699 + hw->mac.ops.update_mc_addr_list(hw, mc_addr_list, mc_addr_count);
24703 + * e1000_set_multi - Multicast and Promiscuous mode set
24704 + * @netdev: network interface device structure
24706 + * The set_multi entry point is called whenever the multicast address
24707 + * list or the network interface flags are updated. This routine is
24708 + * responsible for configuring the hardware for proper multicast,
24709 + * promiscuous mode, and all-multi behavior.
24711 +static void e1000_set_multi(struct net_device *netdev)
24713 + struct e1000_adapter *adapter = netdev_priv(netdev);
24714 + struct e1000_hw *hw = &adapter->hw;
24715 + struct dev_mc_list *mc_ptr;
24720 + /* Check for Promiscuous and All Multicast modes */
24722 + rctl = er32(RCTL);
24724 + if (netdev->flags & IFF_PROMISC) {
24725 + rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
24726 + rctl &= ~E1000_RCTL_VFE;
24728 + if (netdev->flags & IFF_ALLMULTI) {
24729 + rctl |= E1000_RCTL_MPE;
24730 + rctl &= ~E1000_RCTL_UPE;
24732 + rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
24734 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
24735 + rctl |= E1000_RCTL_VFE;
24738 + ew32(RCTL, rctl);
24740 + if (netdev->mc_count) {
24741 + mta_list = kmalloc(netdev->mc_count * 6, GFP_ATOMIC);
24745 + /* prepare a packed array of only addresses. */
24746 + mc_ptr = netdev->mc_list;
24748 + for (i = 0; i < netdev->mc_count; i++) {
24751 + memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr,
24753 + mc_ptr = mc_ptr->next;
24756 + e1000_update_mc_addr_list(hw, mta_list, i);
24760 + * if we're called from probe, we might not have
24761 + * anything to do here, so clear out the list
24763 + e1000_update_mc_addr_list(hw, NULL, 0);
24768 + * e1000_configure - configure the hardware for Rx and Tx
24769 + * @adapter: private board structure
24771 +static void e1000_configure(struct e1000_adapter *adapter)
24773 + e1000_set_multi(adapter->netdev);
24775 + e1000_restore_vlan(adapter);
24776 + e1000_init_manageability(adapter);
24778 + e1000_configure_tx(adapter);
24779 + e1000_setup_rctl(adapter);
24780 + e1000_configure_rx(adapter);
24781 + adapter->alloc_rx_buf(adapter, e1000_desc_unused(adapter->rx_ring));
24785 + * e1000e_power_up_phy - restore link in case the phy was powered down
24786 + * @adapter: address of board private structure
24788 + * The phy may be powered down to save power and turn off link when the
24789 + * driver is unloaded and wake on lan is not enabled (among others)
24790 + * *** this routine MUST be followed by a call to e1000e_reset ***
24792 +void e1000e_power_up_phy(struct e1000_adapter *adapter)
24794 + if (adapter->hw.phy.ops.power_up)
24795 + adapter->hw.phy.ops.power_up(&adapter->hw);
24797 + adapter->hw.mac.ops.setup_link(&adapter->hw);
24801 + * e1000_power_down_phy - Power down the PHY
24803 + * Power down the PHY so no link is implied when interface is down.
24804 + * The PHY cannot be powered down if management or WoL is active.
24806 +static void e1000_power_down_phy(struct e1000_adapter *adapter)
24808 + /* WoL is enabled */
24809 + if (adapter->wol)
24812 + if (adapter->hw.phy.ops.power_down)
24813 + adapter->hw.phy.ops.power_down(&adapter->hw);
24817 + * e1000e_reset - bring the hardware into a known good state
24819 + * This function boots the hardware and enables some settings that
24820 + * require a configuration cycle of the hardware - those cannot be
24821 + * set/changed during runtime. After reset the device needs to be
24822 + * properly configured for Rx, Tx etc.
24824 +void e1000e_reset(struct e1000_adapter *adapter)
24826 + struct e1000_mac_info *mac = &adapter->hw.mac;
24827 + struct e1000_fc_info *fc = &adapter->hw.fc;
24828 + struct e1000_hw *hw = &adapter->hw;
24829 + u32 tx_space, min_tx_space, min_rx_space;
24830 + u32 pba = adapter->pba;
24833 + /* reset Packet Buffer Allocation to default */
24836 + if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
24838 + * To maintain wire speed transmits, the Tx FIFO should be
24839 + * large enough to accommodate two full transmit packets,
24840 + * rounded up to the next 1KB and expressed in KB. Likewise,
24841 + * the Rx FIFO should be large enough to accommodate at least
24842 + * one full receive packet and is similarly rounded up and
24843 + * expressed in KB.
24846 + /* upper 16 bits has Tx packet buffer allocation size in KB */
24847 + tx_space = pba >> 16;
24848 + /* lower 16 bits has Rx packet buffer allocation size in KB */
24851 + * the Tx fifo also stores 16 bytes of information about the tx
24852 + * but don't include ethernet FCS because hardware appends it
24854 + min_tx_space = (adapter->max_frame_size +
24855 + sizeof(struct e1000_tx_desc) -
24856 + ETH_FCS_LEN) * 2;
24857 + min_tx_space = ALIGN(min_tx_space, 1024);
24858 + min_tx_space >>= 10;
24859 + /* software strips receive CRC, so leave room for it */
24860 + min_rx_space = adapter->max_frame_size;
24861 + min_rx_space = ALIGN(min_rx_space, 1024);
24862 + min_rx_space >>= 10;
24865 + * If current Tx allocation is less than the min Tx FIFO size,
24866 + * and the min Tx FIFO size is less than the current Rx FIFO
24867 + * allocation, take space away from current Rx allocation
24869 + if ((tx_space < min_tx_space) &&
24870 + ((min_tx_space - tx_space) < pba)) {
24871 + pba -= min_tx_space - tx_space;
24874 + * if short on Rx space, Rx wins and must trump tx
24875 + * adjustment or use Early Receive if available
24877 + if ((pba < min_rx_space) &&
24878 + (!(adapter->flags & FLAG_HAS_ERT)))
24879 + /* ERT enabled in e1000_configure_rx */
24880 + pba = min_rx_space;
24888 + * flow control settings
24890 + * The high water mark must be low enough to fit two full frames
24891 + * (or the size used for early receive) above it in the Rx FIFO.
24892 + * Set it to the lower of:
24893 + * - 90% of the Rx FIFO size, and
24894 + * - the full Rx FIFO size minus the early receive size (for parts
24895 + * with ERT support assuming ERT set to E1000_ERT_2048), or
24896 + * - the full Rx FIFO size minus two full frames
24898 + if ((adapter->flags & FLAG_HAS_ERT) &&
24899 + (adapter->netdev->mtu > ETH_DATA_LEN))
24900 + hwm = min(((pba << 10) * 9 / 10),
24901 + ((pba << 10) - (E1000_ERT_2048 << 3)));
24903 + hwm = min(((pba << 10) * 9 / 10),
24904 + ((pba << 10) - (2 * adapter->max_frame_size)));
24906 + fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
24907 + fc->low_water = (fc->high_water - (2 * adapter->max_frame_size));
24908 + fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */
24910 + if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
24911 + fc->pause_time = 0xFFFF;
24913 + fc->pause_time = E1000_FC_PAUSE_TIME;
24914 + fc->send_xon = 1;
24915 + fc->current_mode = fc->requested_mode;
24917 + /* Allow time for pending master requests to run */
24918 + mac->ops.reset_hw(hw);
24921 + * For parts with AMT enabled, let the firmware know
24922 + * that the network interface is in control
24924 + if (adapter->flags & FLAG_HAS_AMT)
24925 + e1000_get_hw_control(adapter);
24928 + if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)
24929 + e1e_wphy(&adapter->hw, BM_WUC, 0);
24931 + if (mac->ops.init_hw(hw))
24932 + e_err("Hardware Error\n");
24934 + e1000_update_mng_vlan(adapter);
24936 + /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
24937 + ew32(VET, ETH_P_8021Q);
24939 + e1000e_reset_adaptive(hw);
24940 + e1000_get_phy_info(hw);
24942 + if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
24943 + !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
24944 + u16 phy_data = 0;
24946 + * speed up time to link by disabling smart power down, ignore
24947 + * the return value of this function because there is nothing
24948 + * different we would do if it failed
24950 + e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
24951 + phy_data &= ~IGP02E1000_PM_SPD;
24952 + e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
24956 +int e1000e_up(struct e1000_adapter *adapter)
24958 + struct e1000_hw *hw = &adapter->hw;
24960 + /* DMA latency requirement to workaround early-receive/jumbo issue */
24961 + if (adapter->flags & FLAG_HAS_ERT)
24962 + pm_qos_add_requirement(PM_QOS_CPU_DMA_LATENCY,
24963 + adapter->netdev->name,
24964 + PM_QOS_DEFAULT_VALUE);
24966 + /* hardware has been reset, we need to reload some things */
24967 + e1000_configure(adapter);
24969 + clear_bit(__E1000_DOWN, &adapter->state);
24971 +#ifdef CONFIG_E1000E_NAPI
24972 + napi_enable(&adapter->napi);
24974 +#ifdef CONFIG_E1000E_MSIX
24975 + if (adapter->msix_entries)
24976 + e1000_configure_msix(adapter);
24977 +#endif /* CONFIG_E1000E_MSIX */
24978 + e1000_irq_enable(adapter);
24980 + /* fire a link change interrupt to start the watchdog */
24981 + ew32(ICS, E1000_ICS_LSC);
24985 +void e1000e_down(struct e1000_adapter *adapter)
24987 + struct net_device *netdev = adapter->netdev;
24988 + struct e1000_hw *hw = &adapter->hw;
24992 + * signal that we're down so the interrupt handler does not
24993 + * reschedule our watchdog timer
24995 + set_bit(__E1000_DOWN, &adapter->state);
24997 + /* disable receives in the hardware */
24998 + rctl = er32(RCTL);
24999 + ew32(RCTL, rctl & ~E1000_RCTL_EN);
25000 + /* flush and sleep below */
25002 + netif_tx_stop_all_queues(netdev);
25004 + /* disable transmits in the hardware */
25005 + tctl = er32(TCTL);
25006 + tctl &= ~E1000_TCTL_EN;
25007 + ew32(TCTL, tctl);
25008 + /* flush both disables and wait for them to finish */
25012 +#ifdef CONFIG_E1000E_NAPI
25013 + napi_disable(&adapter->napi);
25015 + e1000_irq_disable(adapter);
25017 + del_timer_sync(&adapter->watchdog_timer);
25018 + del_timer_sync(&adapter->phy_info_timer);
25020 + netdev->tx_queue_len = adapter->tx_queue_len;
25021 + netif_carrier_off(netdev);
25022 + adapter->link_speed = 0;
25023 + adapter->link_duplex = 0;
25025 +#ifdef HAVE_PCI_ERS
25026 + if (!pci_channel_offline(adapter->pdev))
25028 + e1000e_reset(adapter);
25029 + e1000_clean_tx_ring(adapter);
25030 + e1000_clean_rx_ring(adapter);
25032 + if (adapter->flags & FLAG_HAS_ERT)
25033 + pm_qos_remove_requirement(PM_QOS_CPU_DMA_LATENCY,
25034 + adapter->netdev->name);
25037 + * TODO: for power management, we could drop the link and
25038 + * pci_disable_device here.
25042 +void e1000e_reinit_locked(struct e1000_adapter *adapter)
25045 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
25047 + e1000e_down(adapter);
25048 + e1000e_up(adapter);
25049 + clear_bit(__E1000_RESETTING, &adapter->state);
25053 + * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
25054 + * @adapter: board private structure to initialize
25056 + * e1000_sw_init initializes the Adapter private data structure.
25057 + * Fields are initialized based on PCI device information and
25058 + * OS network device settings (MTU size).
25060 +static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
25062 + struct net_device *netdev = adapter->netdev;
25065 + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
25066 + adapter->rx_ps_bsize0 = 128;
25067 + adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
25068 + adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
25070 + /* Set various function pointers */
25071 + adapter->ei->init_ops(&adapter->hw);
25073 + rc = adapter->hw.mac.ops.init_params(&adapter->hw);
25077 + rc = adapter->hw.nvm.ops.init_params(&adapter->hw);
25081 + rc = adapter->hw.phy.ops.init_params(&adapter->hw);
25085 +#ifdef CONFIG_E1000E_MSIX
25086 + e1000e_set_interrupt_capability(adapter);
25088 +#endif /* CONFIG_E1000E_MSIX */
25089 + if (e1000_alloc_queues(adapter))
25092 + /* Explicitly disable IRQ since the NIC can be in any state. */
25093 + e1000_irq_disable(adapter);
25095 + set_bit(__E1000_DOWN, &adapter->state);
25100 + * e1000_intr_msi_test - Interrupt Handler
25101 + * @irq: interrupt number
25102 + * @data: pointer to a network interface device structure
25104 +static irqreturn_t e1000_intr_msi_test(int irq, void *data)
25106 + struct net_device *netdev = data;
25107 + struct e1000_adapter *adapter = netdev_priv(netdev);
25108 + struct e1000_hw *hw = &adapter->hw;
25109 + u32 icr = er32(ICR);
25111 + e_dbg("icr is %08X\n", icr);
25112 + if (icr & E1000_ICR_RXSEQ) {
25113 + adapter->flags &= ~FLAG_MSI_TEST_FAILED;
25117 + return IRQ_HANDLED;
25121 + * e1000_test_msi_interrupt - Returns 0 for successful test
25122 + * @adapter: board private struct
25124 + * code flow taken from tg3.c
25126 +static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
25128 + struct net_device *netdev = adapter->netdev;
25129 + struct e1000_hw *hw = &adapter->hw;
25132 + /* poll_enable hasn't been called yet, so don't need disable */
25133 + /* clear any pending events */
25136 + /* free the real vector and request a test handler */
25137 + e1000_free_irq(adapter);
25138 +#ifdef CONFIG_E1000E_MSIX
25139 + e1000e_reset_interrupt_capability(adapter);
25142 + /* Assume that the test fails, if it succeeds then the test
25143 + * MSI irq handler will unset this flag */
25144 + adapter->flags |= FLAG_MSI_TEST_FAILED;
25146 + err = pci_enable_msi(adapter->pdev);
25148 + goto msi_test_failed;
25150 + err = request_irq(adapter->pdev->irq, &e1000_intr_msi_test, 0,
25151 + netdev->name, netdev);
25153 + pci_disable_msi(adapter->pdev);
25154 + goto msi_test_failed;
25159 + e1000_irq_enable(adapter);
25161 + /* fire an unusual interrupt on the test handler */
25162 + ew32(ICS, E1000_ICS_RXSEQ);
25166 + e1000_irq_disable(adapter);
25170 + if (adapter->flags & FLAG_MSI_TEST_FAILED) {
25171 +#ifdef CONFIG_E1000E_MSIX
25172 + adapter->int_mode = E1000E_INT_MODE_LEGACY;
25175 + e_info("MSI interrupt test failed!\n");
25178 + free_irq(adapter->pdev->irq, netdev);
25179 + pci_disable_msi(adapter->pdev);
25182 + goto msi_test_failed;
25184 + /* okay so the test worked, restore settings */
25185 + e_dbg("MSI interrupt test succeeded!\n");
25187 +#ifdef CONFIG_E1000E_MSIX
25188 + e1000e_set_interrupt_capability(adapter);
25190 + /* restore the original vector, even if it failed */
25192 + e1000_request_irq(adapter);
25197 + * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
25198 + * @adapter: board private struct
25200 + * code flow taken from tg3.c, called with e1000 interrupts disabled.
25202 +static int e1000_test_msi(struct e1000_adapter *adapter)
25207 + if (!(adapter->flags & FLAG_MSI_ENABLED))
25210 + /* disable SERR in case the MSI write causes a master abort */
25211 + pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
25212 + pci_write_config_word(adapter->pdev, PCI_COMMAND,
25213 + pci_cmd & ~PCI_COMMAND_SERR);
25215 + err = e1000_test_msi_interrupt(adapter);
25217 + /* restore previous setting of command word */
25218 + pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
25224 + /* EIO means MSI test failed */
25228 + /* back to INTx mode */
25229 + e_warn("MSI interrupt test failed, using legacy interrupt.\n");
25231 + e1000_free_irq(adapter);
25233 + err = e1000_request_irq(adapter);
25239 + * e1000_open - Called when a network interface is made active
25240 + * @netdev: network interface device structure
25242 + * Returns 0 on success, negative value on failure
25244 + * The open entry point is called when a network interface is made
25245 + * active by the system (IFF_UP). At this point all resources needed
25246 + * for transmit and receive operations are allocated, the interrupt
25247 + * handler is registered with the OS, the watchdog timer is started,
25248 + * and the stack is notified that the interface is ready.
25250 +static int e1000_open(struct net_device *netdev)
25252 + struct e1000_adapter *adapter = netdev_priv(netdev);
25253 + struct e1000_hw *hw = &adapter->hw;
25256 + /* disallow open during test */
25257 + if (test_bit(__E1000_TESTING, &adapter->state))
25260 + /* allocate transmit descriptors */
25261 + err = e1000e_setup_tx_resources(adapter);
25263 + goto err_setup_tx;
25265 + /* allocate receive descriptors */
25266 + err = e1000e_setup_rx_resources(adapter);
25268 + goto err_setup_rx;
25270 + e1000e_power_up_phy(adapter);
25272 + adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
25273 + if ((adapter->hw.mng_cookie.status &
25274 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
25275 + e1000_update_mng_vlan(adapter);
25278 + * If AMT is enabled, let the firmware know that the network
25279 + * interface is now open
25281 + if (adapter->flags & FLAG_HAS_AMT)
25282 + e1000_get_hw_control(adapter);
25285 + * before we allocate an interrupt, we must be ready to handle it.
25286 + * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
25287 + * as soon as we call pci_request_irq, so we have to setup our
25288 + * clean_rx handler before we do so.
25290 + e1000_configure(adapter);
25292 + err = e1000_request_irq(adapter);
25294 + goto err_req_irq;
25297 + * Work around PCIe errata with MSI interrupts causing some chipsets to
25298 + * ignore e1000e MSI messages, which means we need to test our MSI
25301 +#ifdef CONFIG_E1000E_MSIX
25302 + if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
25306 + err = e1000_test_msi(adapter);
25308 + e_err("Interrupt allocation failed\n");
25309 + goto err_req_irq;
25313 + /* From here on the code is the same as e1000e_up() */
25314 + clear_bit(__E1000_DOWN, &adapter->state);
25316 +#ifdef CONFIG_E1000E_NAPI
25317 + napi_enable(&adapter->napi);
25320 + e1000_irq_enable(adapter);
25322 + netif_tx_start_all_queues(netdev);
25324 + /* fire a link status change interrupt to start the watchdog */
25325 + ew32(ICS, E1000_ICS_LSC);
25330 + e1000_release_hw_control(adapter);
25331 + e1000_power_down_phy(adapter);
25332 + e1000e_free_rx_resources(adapter);
25334 + e1000e_free_tx_resources(adapter);
25336 + e1000e_reset(adapter);
25342 + * e1000_close - Disables a network interface
25343 + * @netdev: network interface device structure
25345 + * Returns 0, this is not allowed to fail
25347 + * The close entry point is called when an interface is de-activated
25348 + * by the OS. The hardware is still under the drivers control, but
25349 + * needs to be disabled. A global MAC reset is issued to stop the
25350 + * hardware, and all transmit and receive resources are freed.
25352 +static int e1000_close(struct net_device *netdev)
25354 + struct e1000_adapter *adapter = netdev_priv(netdev);
25356 + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
25357 + e1000e_down(adapter);
25358 + e1000_power_down_phy(adapter);
25359 + e1000_free_irq(adapter);
25361 + e1000e_free_tx_resources(adapter);
25362 + e1000e_free_rx_resources(adapter);
25365 + * kill manageability vlan ID if supported, but not if a vlan with
25366 + * the same ID is registered on the host OS (let 8021q kill it)
25368 + if ((adapter->hw.mng_cookie.status &
25369 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
25370 + !(adapter->vlgrp &&
25371 + vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
25372 + e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
25375 + * If AMT is enabled, let the firmware know that the network
25376 + * interface is now closed
25378 + if (adapter->flags & FLAG_HAS_AMT)
25379 + e1000_release_hw_control(adapter);
25384 + * e1000_set_mac - Change the Ethernet Address of the NIC
25385 + * @netdev: network interface device structure
25386 + * @p: pointer to an address structure
25388 + * Returns 0 on success, negative on failure
25390 +static int e1000_set_mac(struct net_device *netdev, void *p)
25392 + struct e1000_adapter *adapter = netdev_priv(netdev);
25393 + struct sockaddr *addr = p;
25395 + if (!is_valid_ether_addr(addr->sa_data))
25396 + return -EADDRNOTAVAIL;
25398 + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
25399 + memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
25401 + e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
25403 + if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
25404 + /* activate the work around */
25405 + e1000e_set_laa_state_82571(&adapter->hw, 1);
25408 + * Hold a copy of the LAA in RAR[14] This is done so that
25409 + * between the time RAR[0] gets clobbered and the time it
25410 + * gets fixed (in e1000_watchdog), the actual LAA is in one
25411 + * of the RARs and no incoming packets directed to this port
25412 + * are dropped. Eventually the LAA will be in RAR[0] and
25415 + e1000e_rar_set(&adapter->hw,
25416 + adapter->hw.mac.addr,
25417 + adapter->hw.mac.rar_entry_count - 1);
25424 + * e1000e_update_phy_task - work thread to update phy
25425 + * @work: pointer to our work struct
25427 + * this worker thread exists because we must acquire a
25428 + * semaphore to read the phy, which we could msleep while
25429 + * waiting for it, and we can't msleep in a timer.
25431 +static void e1000e_update_phy_task(struct work_struct *work)
25433 + struct e1000_adapter *adapter = container_of(work,
25434 + struct e1000_adapter, update_phy_task);
25435 + e1000_get_phy_info(&adapter->hw);
25439 + * Need to wait a few seconds after link up to get diagnostic information from
25442 +static void e1000_update_phy_info(unsigned long data)
25444 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
25445 + schedule_work(&adapter->update_phy_task);
25449 + * e1000e_update_stats - Update the board statistics counters
25450 + * @adapter: board private structure
25452 +void e1000e_update_stats(struct e1000_adapter *adapter)
25454 + struct e1000_hw *hw = &adapter->hw;
25455 +#ifdef HAVE_PCI_ERS
25456 + struct pci_dev *pdev = adapter->pdev;
25461 + * Prevent stats update while adapter is being reset, or if the pci
25462 + * connection is down.
25464 + if (adapter->link_speed == 0)
25466 +#ifdef HAVE_PCI_ERS
25467 + if (pci_channel_offline(pdev))
25471 + adapter->stats.crcerrs += er32(CRCERRS);
25472 + adapter->stats.gprc += er32(GPRC);
25473 + adapter->stats.gorc += er32(GORCL);
25474 + er32(GORCH); /* Clear gorc */
25475 + adapter->stats.bprc += er32(BPRC);
25476 + adapter->stats.mprc += er32(MPRC);
25477 + adapter->stats.roc += er32(ROC);
25479 + adapter->stats.mpc += er32(MPC);
25480 + if ((hw->phy.type == e1000_phy_82578) ||
25481 + (hw->phy.type == e1000_phy_82577)) {
25482 + e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
25483 + e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
25484 + adapter->stats.scc += phy_data;
25486 + e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
25487 + e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
25488 + adapter->stats.ecol += phy_data;
25490 + e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
25491 + e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
25492 + adapter->stats.mcc += phy_data;
25494 + e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
25495 + e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
25496 + adapter->stats.latecol += phy_data;
25498 + e1e_rphy(hw, HV_DC_UPPER, &phy_data);
25499 + e1e_rphy(hw, HV_DC_LOWER, &phy_data);
25500 + adapter->stats.dc += phy_data;
25502 + adapter->stats.scc += er32(SCC);
25503 + adapter->stats.ecol += er32(ECOL);
25504 + adapter->stats.mcc += er32(MCC);
25505 + adapter->stats.latecol += er32(LATECOL);
25506 + adapter->stats.dc += er32(DC);
25508 + adapter->stats.xonrxc += er32(XONRXC);
25509 + adapter->stats.xontxc += er32(XONTXC);
25510 + adapter->stats.xoffrxc += er32(XOFFRXC);
25511 + adapter->stats.xofftxc += er32(XOFFTXC);
25512 + adapter->stats.gptc += er32(GPTC);
25513 + adapter->stats.gotc += er32(GOTCL);
25514 + er32(GOTCH); /* Clear gotc */
25515 + adapter->stats.rnbc += er32(RNBC);
25516 + adapter->stats.ruc += er32(RUC);
25518 + adapter->stats.mptc += er32(MPTC);
25519 + adapter->stats.bptc += er32(BPTC);
25521 + /* used for adaptive IFS */
25523 + hw->mac.tx_packet_delta = er32(TPT);
25524 + adapter->stats.tpt += hw->mac.tx_packet_delta;
25525 + if ((hw->phy.type == e1000_phy_82578) ||
25526 + (hw->phy.type == e1000_phy_82577)) {
25527 + e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
25528 + e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
25529 + hw->mac.collision_delta = phy_data;
25531 + hw->mac.collision_delta = er32(COLC);
25533 + adapter->stats.colc += hw->mac.collision_delta;
25535 + adapter->stats.algnerrc += er32(ALGNERRC);
25536 + adapter->stats.rxerrc += er32(RXERRC);
25537 + if ((hw->phy.type == e1000_phy_82578) ||
25538 + (hw->phy.type == e1000_phy_82577)) {
25539 + e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
25540 + e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
25541 + adapter->stats.tncrs += phy_data;
25543 + if ((hw->mac.type != e1000_82574) &&
25544 + (hw->mac.type != e1000_82583))
25545 + adapter->stats.tncrs += er32(TNCRS);
25547 + adapter->stats.cexterr += er32(CEXTERR);
25548 + adapter->stats.tsctc += er32(TSCTC);
25549 + adapter->stats.tsctfc += er32(TSCTFC);
25551 + /* Fill out the OS statistics structure */
25552 + adapter->net_stats.multicast = adapter->stats.mprc;
25553 + adapter->net_stats.collisions = adapter->stats.colc;
25558 + * RLEC on some newer hardware can be incorrect so build
25559 + * our own version based on RUC and ROC
25561 + adapter->net_stats.rx_errors = adapter->stats.rxerrc +
25562 + adapter->stats.crcerrs + adapter->stats.algnerrc +
25563 + adapter->stats.ruc + adapter->stats.roc +
25564 + adapter->stats.cexterr;
25565 + adapter->net_stats.rx_length_errors = adapter->stats.ruc +
25566 + adapter->stats.roc;
25567 + adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
25568 + adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
25569 + adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
25572 + adapter->net_stats.tx_errors = adapter->stats.ecol +
25573 + adapter->stats.latecol;
25574 + adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
25575 + adapter->net_stats.tx_window_errors = adapter->stats.latecol;
25576 + adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
25578 + /* Tx Dropped needs to be maintained elsewhere */
25580 + /* Management Stats */
25581 + adapter->stats.mgptc += er32(MGTPTC);
25582 + adapter->stats.mgprc += er32(MGTPRC);
25583 + adapter->stats.mgpdc += er32(MGTPDC);
25586 +#ifdef SIOCGMIIPHY
25588 + * e1000_phy_read_status - Update the PHY register status snapshot
25589 + * @adapter: board private structure
25591 +static void e1000_phy_read_status(struct e1000_adapter *adapter)
25593 + struct e1000_hw *hw = &adapter->hw;
25594 + struct e1000_phy_regs *phy = &adapter->phy_regs;
25597 + if ((er32(STATUS) & E1000_STATUS_LU) &&
25598 + (adapter->hw.phy.media_type == e1000_media_type_copper)) {
25599 + ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
25600 + ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
25601 + ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
25602 + ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
25603 + ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
25604 + ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
25605 + ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
25606 + ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
25608 + e_warn("Error reading PHY register\n");
25611 + * Do not read PHY registers if link is not up
25612 + * Set values to typical power-on defaults
25614 + phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
25615 + phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
25616 + BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
25618 + phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
25619 + ADVERTISE_ALL | ADVERTISE_CSMA);
25621 + phy->expansion = EXPANSION_ENABLENPAGE;
25622 + phy->ctrl1000 = ADVERTISE_1000FULL;
25623 + phy->stat1000 = 0;
25624 + phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
25628 +#endif /* SIOCGMIIPHY */
25629 +static void e1000_print_link_info(struct e1000_adapter *adapter)
25631 + struct e1000_hw *hw = &adapter->hw;
25632 + u32 ctrl = er32(CTRL);
25634 + /* Link status message must follow this format for user tools */
25635 + printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s, "
25636 + "Flow Control: %s\n",
25637 + adapter->netdev->name,
25638 + adapter->link_speed,
25639 + (adapter->link_duplex == FULL_DUPLEX) ?
25640 + "Full Duplex" : "Half Duplex",
25641 + ((ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE)) ?
25643 + ((ctrl & E1000_CTRL_RFCE) ? "RX" :
25644 + ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
25647 +bool e1000_has_link(struct e1000_adapter *adapter)
25649 + struct e1000_hw *hw = &adapter->hw;
25650 + bool link_active = 0;
25654 + * get_link_status is set on LSC (link status) interrupt or
25655 + * Rx sequence error interrupt. get_link_status will stay
25656 + * false until the check_for_link establishes link
25657 + * for copper adapters ONLY
25659 + switch (hw->phy.media_type) {
25660 + case e1000_media_type_copper:
25661 + if (hw->mac.get_link_status) {
25662 + ret_val = hw->mac.ops.check_for_link(hw);
25663 + link_active = !hw->mac.get_link_status;
25668 + case e1000_media_type_fiber:
25669 + ret_val = hw->mac.ops.check_for_link(hw);
25670 + link_active = !!(er32(STATUS) & E1000_STATUS_LU);
25672 + case e1000_media_type_internal_serdes:
25673 + ret_val = hw->mac.ops.check_for_link(hw);
25674 + link_active = adapter->hw.mac.serdes_has_link;
25677 + case e1000_media_type_unknown:
25681 + if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
25682 + (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
25683 + /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
25684 + e_info("Gigabit has been disabled, downgrading speed\n");
25687 + return link_active;
25690 +static void e1000e_enable_receives(struct e1000_adapter *adapter)
25692 + /* make sure the receive unit is started */
25693 + if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
25694 + (adapter->flags & FLAG_RX_RESTART_NOW)) {
25695 + struct e1000_hw *hw = &adapter->hw;
25696 + u32 rctl = er32(RCTL);
25697 + ew32(RCTL, rctl | E1000_RCTL_EN);
25698 + adapter->flags &= ~FLAG_RX_RESTART_NOW;
25703 + * e1000_watchdog - Timer Call-back
25704 + * @data: pointer to adapter cast into an unsigned long
25706 +static void e1000_watchdog(unsigned long data)
25708 + struct e1000_adapter *adapter = (struct e1000_adapter *) data;
25710 + /* Do the rest outside of interrupt context */
25711 + schedule_work(&adapter->watchdog_task);
25713 + /* TODO: make this use queue_delayed_work() */
25716 +static void e1000_watchdog_task(struct work_struct *work)
25718 + struct e1000_adapter *adapter = container_of(work,
25719 + struct e1000_adapter, watchdog_task);
25720 + struct net_device *netdev = adapter->netdev;
25721 + struct e1000_mac_info *mac = &adapter->hw.mac;
25722 + struct e1000_phy_info *phy = &adapter->hw.phy;
25723 + struct e1000_ring *tx_ring = adapter->tx_ring;
25724 + struct e1000_hw *hw = &adapter->hw;
25726 + int tx_pending = 0;
25728 + link = e1000_has_link(adapter);
25729 + if ((netif_carrier_ok(netdev)) && link) {
25730 + e1000e_enable_receives(adapter);
25734 + if ((e1000e_enable_tx_pkt_filtering(hw)) &&
25735 + (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
25736 + e1000_update_mng_vlan(adapter);
25739 + if (!netif_carrier_ok(netdev)) {
25741 +#ifdef SIOCGMIIPHY
25742 + /* update snapshot of PHY registers on LSC */
25743 + e1000_phy_read_status(adapter);
25745 + mac->ops.get_link_up_info(&adapter->hw,
25746 + &adapter->link_speed,
25747 + &adapter->link_duplex);
25748 + e1000_print_link_info(adapter);
25750 + * On supported PHYs, check for duplex mismatch only
25751 + * if link has autonegotiated at 10/100 half
25753 + if ((hw->phy.type == e1000_phy_igp_3 ||
25754 + hw->phy.type == e1000_phy_bm) &&
25755 + (hw->mac.autoneg == true) &&
25756 + (adapter->link_speed == SPEED_10 ||
25757 + adapter->link_speed == SPEED_100) &&
25758 + (adapter->link_duplex == HALF_DUPLEX)) {
25761 + e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
25763 + if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
25764 + e_info("Autonegotiated half duplex but"
25765 + " link partner cannot autoneg. "
25766 + " Try forcing full duplex if "
25767 + "link gets many collisions.\n");
25771 + * tweak tx_queue_len according to speed/duplex
25772 + * and adjust the timeout factor
25774 + netdev->tx_queue_len = adapter->tx_queue_len;
25775 + adapter->tx_timeout_factor = 1;
25776 + switch (adapter->link_speed) {
25779 + netdev->tx_queue_len = 10;
25780 + adapter->tx_timeout_factor = 16;
25784 + netdev->tx_queue_len = 100;
25785 + /* maybe add some timeout factor ? */
25790 + * workaround: re-program speed mode bit after
25793 + if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
25796 + tarc0 = er32(TARC(0));
25797 + tarc0 &= ~SPEED_MODE_BIT;
25798 + ew32(TARC(0), tarc0);
25801 +#ifdef NETIF_F_TSO
25803 + * disable TSO for pcie and 10/100 speeds, to avoid
25804 + * some hardware issues
25806 + if (!(adapter->flags & FLAG_TSO_FORCE)) {
25807 + switch (adapter->link_speed) {
25810 + e_info("10/100 speed: disabling TSO\n");
25811 + netdev->features &= ~NETIF_F_TSO;
25812 +#ifdef NETIF_F_TSO6
25813 + netdev->features &= ~NETIF_F_TSO6;
25817 + netdev->features |= NETIF_F_TSO;
25818 +#ifdef NETIF_F_TSO6
25819 + netdev->features |= NETIF_F_TSO6;
25830 + * enable transmits in the hardware, need to do this
25831 + * after setting TARC(0)
25833 + tctl = er32(TCTL);
25834 + tctl |= E1000_TCTL_EN;
25835 + ew32(TCTL, tctl);
25838 + * Perform any post-link-up configuration before
25839 + * reporting link up.
25841 + if (phy->ops.cfg_on_link_up)
25842 + phy->ops.cfg_on_link_up(hw);
25844 + netif_carrier_on(netdev);
25845 + netif_tx_wake_all_queues(netdev);
25847 + if (!test_bit(__E1000_DOWN, &adapter->state))
25848 + mod_timer(&adapter->phy_info_timer,
25849 + round_jiffies(jiffies + 2 * HZ));
25852 + if (netif_carrier_ok(netdev)) {
25853 + adapter->link_speed = 0;
25854 + adapter->link_duplex = 0;
25855 + /* Link status message must follow this format */
25856 + printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
25857 + adapter->netdev->name);
25858 + netif_carrier_off(netdev);
25859 + netif_tx_stop_all_queues(netdev);
25860 + if (!test_bit(__E1000_DOWN, &adapter->state))
25861 + mod_timer(&adapter->phy_info_timer,
25862 + round_jiffies(jiffies + 2 * HZ));
25864 + if (adapter->flags & FLAG_RX_NEEDS_RESTART)
25865 + schedule_work(&adapter->reset_task);
25870 + e1000e_update_stats(adapter);
25872 + mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
25873 + adapter->tpt_old = adapter->stats.tpt;
25874 + mac->collision_delta = adapter->stats.colc - adapter->colc_old;
25875 + adapter->colc_old = adapter->stats.colc;
25877 + adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
25878 + adapter->gorc_old = adapter->stats.gorc;
25879 + adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
25880 + adapter->gotc_old = adapter->stats.gotc;
25882 + e1000e_update_adaptive(&adapter->hw);
25884 + if (!netif_carrier_ok(netdev)) {
25885 + tx_pending = (e1000_desc_unused(tx_ring) + 1 <
25887 + if (tx_pending) {
25889 + * We've lost link, so the controller stops DMA,
25890 + * but we've got queued Tx work that's never going
25891 + * to get done, so reset controller to flush Tx.
25892 + * (Do the reset outside of interrupt context).
25894 + adapter->tx_timeout_count++;
25895 + schedule_work(&adapter->reset_task);
25899 + /* Cause software interrupt to ensure Rx ring is cleaned */
25900 +#ifdef CONFIG_E1000E_MSIX
25901 + if (adapter->msix_entries)
25902 + ew32(ICS, adapter->rx_ring->ims_val);
25904 + ew32(ICS, E1000_ICS_RXDMT0);
25906 + ew32(ICS, E1000_ICS_RXDMT0);
25909 + /* Force detection of hung controller every watchdog period */
25910 + adapter->detect_tx_hung = 1;
25913 + * With 82571 controllers, LAA may be overwritten due to controller
25914 + * reset from the other port. Set the appropriate LAA in RAR[0]
25916 + if (e1000e_get_laa_state_82571(hw))
25917 + e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
25919 + /* Reset the timer */
25920 + if (!test_bit(__E1000_DOWN, &adapter->state))
25921 + mod_timer(&adapter->watchdog_timer,
25922 + round_jiffies(jiffies + 2 * HZ));
25925 +#define E1000_TX_FLAGS_CSUM 0x00000001
25926 +#define E1000_TX_FLAGS_VLAN 0x00000002
25927 +#define E1000_TX_FLAGS_TSO 0x00000004
25928 +#define E1000_TX_FLAGS_IPV4 0x00000008
25929 +#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
25930 +#define E1000_TX_FLAGS_VLAN_SHIFT 16
25932 +static int e1000_tso(struct e1000_adapter *adapter,
25933 + struct sk_buff *skb)
25935 +#ifdef NETIF_F_TSO
25936 + struct e1000_ring *tx_ring = adapter->tx_ring;
25937 + struct e1000_context_desc *context_desc;
25938 + struct e1000_buffer *buffer_info;
25940 + u32 cmd_length = 0;
25941 + u16 ipcse = 0, tucse, mss;
25942 + u8 ipcss, ipcso, tucss, tucso, hdr_len;
25945 + if (!skb_is_gso(skb))
25948 + if (skb_header_cloned(skb)) {
25949 + err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
25954 + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
25955 + mss = skb_shinfo(skb)->gso_size;
25956 + if (skb->protocol == htons(ETH_P_IP)) {
25957 + struct iphdr *iph = ip_hdr(skb);
25958 + iph->tot_len = 0;
25960 + tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
25961 + 0, IPPROTO_TCP, 0);
25962 + cmd_length = E1000_TXD_CMD_IP;
25963 + ipcse = skb_transport_offset(skb) - 1;
25964 +#ifdef NETIF_F_TSO6
25965 + } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
25966 + ipv6_hdr(skb)->payload_len = 0;
25967 + tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
25968 + &ipv6_hdr(skb)->daddr,
25969 + 0, IPPROTO_TCP, 0);
25973 + ipcss = skb_network_offset(skb);
25974 + ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
25975 + tucss = skb_transport_offset(skb);
25976 + tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
25979 + cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
25980 + E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
25982 + i = tx_ring->next_to_use;
25983 + context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
25984 + buffer_info = &tx_ring->buffer_info[i];
25986 + context_desc->lower_setup.ip_fields.ipcss = ipcss;
25987 + context_desc->lower_setup.ip_fields.ipcso = ipcso;
25988 + context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
25989 + context_desc->upper_setup.tcp_fields.tucss = tucss;
25990 + context_desc->upper_setup.tcp_fields.tucso = tucso;
25991 + context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
25992 + context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
25993 + context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
25994 + context_desc->cmd_and_length = cpu_to_le32(cmd_length);
25996 + buffer_info->time_stamp = jiffies;
25997 + buffer_info->next_to_watch = i;
26000 + if (i == tx_ring->count)
26002 + tx_ring->next_to_use = i;
26010 +static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
26012 + struct e1000_ring *tx_ring = adapter->tx_ring;
26013 + struct e1000_context_desc *context_desc;
26014 + struct e1000_buffer *buffer_info;
26017 + u32 cmd_len = E1000_TXD_CMD_DEXT;
26019 + if (skb->ip_summed != CHECKSUM_PARTIAL)
26022 + switch (skb->protocol) {
26023 + case __constant_htons(ETH_P_IP):
26024 + if (ip_hdr(skb)->protocol == IPPROTO_TCP)
26025 + cmd_len |= E1000_TXD_CMD_TCP;
26027 + case __constant_htons(ETH_P_IPV6):
26028 + /* XXX not handling all IPV6 headers */
26029 + if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
26030 + cmd_len |= E1000_TXD_CMD_TCP;
26033 + if (unlikely(net_ratelimit()))
26034 + e_warn("checksum_partial proto=%x!\n", skb->protocol);
26038 + css = skb_transport_offset(skb);
26040 + i = tx_ring->next_to_use;
26041 + buffer_info = &tx_ring->buffer_info[i];
26042 + context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
26044 + context_desc->lower_setup.ip_config = 0;
26045 + context_desc->upper_setup.tcp_fields.tucss = css;
26046 + context_desc->upper_setup.tcp_fields.tucso =
26047 + css + skb->csum_offset;
26048 + context_desc->upper_setup.tcp_fields.tucse = 0;
26049 + context_desc->tcp_seg_setup.data = 0;
26050 + context_desc->cmd_and_length = cpu_to_le32(cmd_len);
26052 + buffer_info->time_stamp = jiffies;
26053 + buffer_info->next_to_watch = i;
26056 + if (i == tx_ring->count)
26058 + tx_ring->next_to_use = i;
26063 +#define E1000_MAX_PER_TXD 8192
26064 +#define E1000_MAX_TXD_PWR 12
26066 +static int e1000_tx_map(struct e1000_adapter *adapter,
26067 + struct sk_buff *skb, unsigned int first,
26068 + unsigned int max_per_txd, unsigned int nr_frags,
26069 + unsigned int mss)
26071 + struct e1000_ring *tx_ring = adapter->tx_ring;
26072 + struct e1000_buffer *buffer_info;
26073 + unsigned int len = skb->len - skb->data_len;
26074 + unsigned int offset = 0, size, count = 0, i;
26077 + i = tx_ring->next_to_use;
26080 + buffer_info = &tx_ring->buffer_info[i];
26081 + size = min(len, max_per_txd);
26083 + buffer_info->length = size;
26084 + /* set time_stamp *before* dma to help avoid a possible race */
26085 + buffer_info->time_stamp = jiffies;
26086 + buffer_info->dma =
26087 + pci_map_single(adapter->pdev,
26088 + skb->data + offset,
26090 + PCI_DMA_TODEVICE);
26091 + if (pci_dma_mapping_error(adapter->pdev, buffer_info->dma)) {
26092 + dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
26093 + adapter->tx_dma_failed++;
26096 + buffer_info->next_to_watch = i;
26102 + if (i == tx_ring->count)
26106 + for (f = 0; f < nr_frags; f++) {
26107 + struct skb_frag_struct *frag;
26109 + frag = &skb_shinfo(skb)->frags[f];
26110 + len = frag->size;
26111 + offset = frag->page_offset;
26114 + buffer_info = &tx_ring->buffer_info[i];
26115 + size = min(len, max_per_txd);
26117 + buffer_info->length = size;
26118 + buffer_info->time_stamp = jiffies;
26119 + buffer_info->dma =
26120 + pci_map_page(adapter->pdev,
26124 + PCI_DMA_TODEVICE);
26125 + if (pci_dma_mapping_error(adapter->pdev,
26126 + buffer_info->dma)) {
26127 + dev_err(&adapter->pdev->dev,
26128 + "TX DMA page map failed\n");
26129 + adapter->tx_dma_failed++;
26133 + buffer_info->next_to_watch = i;
26140 + if (i == tx_ring->count)
26146 + i = tx_ring->count - 1;
26150 + tx_ring->buffer_info[i].skb = skb;
26151 + tx_ring->buffer_info[first].next_to_watch = i;
26156 +static void e1000_tx_queue(struct e1000_adapter *adapter,
26157 + int tx_flags, int count)
26159 + struct e1000_ring *tx_ring = adapter->tx_ring;
26160 + struct e1000_tx_desc *tx_desc = NULL;
26161 + struct e1000_buffer *buffer_info;
26162 + u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
26165 + if (tx_flags & E1000_TX_FLAGS_TSO) {
26166 + txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
26167 + E1000_TXD_CMD_TSE;
26168 + txd_upper |= E1000_TXD_POPTS_TXSM << 8;
26170 + if (tx_flags & E1000_TX_FLAGS_IPV4)
26171 + txd_upper |= E1000_TXD_POPTS_IXSM << 8;
26174 + if (tx_flags & E1000_TX_FLAGS_CSUM) {
26175 + txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
26176 + txd_upper |= E1000_TXD_POPTS_TXSM << 8;
26179 + if (tx_flags & E1000_TX_FLAGS_VLAN) {
26180 + txd_lower |= E1000_TXD_CMD_VLE;
26181 + txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
26184 + i = tx_ring->next_to_use;
26186 + while (count--) {
26187 + buffer_info = &tx_ring->buffer_info[i];
26188 + tx_desc = E1000_TX_DESC(*tx_ring, i);
26189 + tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
26190 + tx_desc->lower.data =
26191 + cpu_to_le32(txd_lower | buffer_info->length);
26192 + tx_desc->upper.data = cpu_to_le32(txd_upper);
26195 + if (i == tx_ring->count)
26199 + tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
26202 + * Force memory writes to complete before letting h/w
26203 + * know there are new descriptors to fetch. (Only
26204 + * applicable for weak-ordered memory model archs,
26205 + * such as IA-64).
26209 + tx_ring->next_to_use = i;
26210 + writel(i, adapter->hw.hw_addr + tx_ring->tail);
26212 + * we need this if more than one processor can write to our tail
26213 + * at a time, it synchronizes IO on IA64/Altix systems
26218 +#define MINIMUM_DHCP_PACKET_SIZE 282
26219 +static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
26220 + struct sk_buff *skb)
26222 + struct e1000_hw *hw = &adapter->hw;
26223 + u16 length, offset;
26225 + if (vlan_tx_tag_present(skb)) {
26226 + if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id)
26227 + && (adapter->hw.mng_cookie.status &
26228 + E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
26232 + if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
26235 + if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
26239 + const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
26240 + struct udphdr *udp;
26242 + if (ip->protocol != IPPROTO_UDP)
26245 + udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
26246 + if (ntohs(udp->dest) != 67)
26249 + offset = (u8 *)udp + 8 - skb->data;
26250 + length = skb->len - offset;
26251 + return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
26257 +static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
26259 + struct e1000_adapter *adapter = netdev_priv(netdev);
26261 + netif_stop_queue(netdev);
26263 + * Herbert's original patch had:
26264 + * smp_mb__after_netif_stop_queue();
26265 + * but since that doesn't exist yet, just open code it.
26270 + * We need to check again in a case another CPU has just
26271 + * made room available.
26273 + if (e1000_desc_unused(adapter->tx_ring) < size)
26276 + /* A reprieve! */
26277 + netif_start_queue(netdev);
26278 + ++adapter->restart_queue;
26282 +static int e1000_maybe_stop_tx(struct net_device *netdev, int size)
26284 + struct e1000_adapter *adapter = netdev_priv(netdev);
26286 + if (e1000_desc_unused(adapter->tx_ring) >= size)
26288 + return __e1000_maybe_stop_tx(netdev, size);
26291 +#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
26292 +static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
26294 + struct e1000_adapter *adapter = netdev_priv(netdev);
26295 + struct e1000_ring *tx_ring = adapter->tx_ring;
26296 + unsigned int first;
26297 + unsigned int max_per_txd = E1000_MAX_PER_TXD;
26298 + unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
26299 + unsigned int tx_flags = 0;
26300 + unsigned int len = skb->len - skb->data_len;
26301 + unsigned int nr_frags;
26302 + unsigned int mss = 0;
26307 + if (test_bit(__E1000_DOWN, &adapter->state)) {
26308 + dev_kfree_skb_any(skb);
26309 + return NETDEV_TX_OK;
26312 + if (skb->len <= 0) {
26313 + dev_kfree_skb_any(skb);
26314 + return NETDEV_TX_OK;
26317 +#ifdef NETIF_F_TSO
26318 + mss = skb_shinfo(skb)->gso_size;
26320 + * The controller does a simple calculation to
26321 + * make sure there is enough room in the FIFO before
26322 + * initiating the DMA for each buffer. The calc is:
26323 + * 4 = ceil(buffer len/mss). To make sure we don't
26324 + * overrun the FIFO, adjust the max buffer len if mss
26329 + max_per_txd = min(mss << 2, max_per_txd);
26330 + max_txd_pwr = fls(max_per_txd) - 1;
26333 + * TSO Workaround for 82571/2/3 Controllers -- if skb->data
26334 + * points to just header, pull a few bytes of payload from
26335 + * frags into skb->data
26337 + hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
26339 + * we do this workaround for ES2LAN, but it is un-necessary,
26340 + * avoiding it could save a lot of cycles
26342 + if (skb->data_len && (hdr_len == len)) {
26343 + unsigned int pull_size;
26345 + pull_size = min((unsigned int)4, skb->data_len);
26346 + if (!__pskb_pull_tail(skb, pull_size)) {
26347 + e_err("__pskb_pull_tail failed.\n");
26348 + dev_kfree_skb_any(skb);
26349 + return NETDEV_TX_OK;
26351 + len = skb->len - skb->data_len;
26355 + /* reserve a descriptor for the offload context */
26356 + if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
26360 + if (skb->ip_summed == CHECKSUM_PARTIAL)
26364 + count += TXD_USE_COUNT(len, max_txd_pwr);
26366 + nr_frags = skb_shinfo(skb)->nr_frags;
26367 + for (f = 0; f < nr_frags; f++)
26368 + count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
26371 + if (adapter->hw.mac.tx_pkt_filtering)
26372 + e1000_transfer_dhcp_info(adapter, skb);
26376 + * need: count + 2 desc gap to keep tail from touching
26377 + * head, otherwise try next time
26379 + if (e1000_maybe_stop_tx(netdev, count + 2)) {
26380 + return NETDEV_TX_BUSY;
26383 + if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
26384 + tx_flags |= E1000_TX_FLAGS_VLAN;
26385 + tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
26388 + first = tx_ring->next_to_use;
26390 + tso = e1000_tso(adapter, skb);
26392 + dev_kfree_skb_any(skb);
26393 + return NETDEV_TX_OK;
26397 + tx_flags |= E1000_TX_FLAGS_TSO;
26398 + else if (e1000_tx_csum(adapter, skb))
26399 + tx_flags |= E1000_TX_FLAGS_CSUM;
26402 + * Old method was to assume IPv4 packet by default if TSO was enabled.
26403 + * 82571 hardware supports TSO capabilities for IPv6 as well...
26404 + * no longer assume, we must.
26406 + if (skb->protocol == htons(ETH_P_IP))
26407 + tx_flags |= E1000_TX_FLAGS_IPV4;
26409 + count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss);
26411 + /* handle pci_map_single() error in e1000_tx_map */
26412 + dev_kfree_skb_any(skb);
26413 + return NETDEV_TX_OK;
26416 + e1000_tx_queue(adapter, tx_flags, count);
26418 + netdev->trans_start = jiffies;
26420 + /* Make sure there is space in the ring for the next send. */
26421 + e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2);
26423 + return NETDEV_TX_OK;
26427 + * e1000_tx_timeout - Respond to a Tx Hang
26428 + * @netdev: network interface device structure
26430 +static void e1000_tx_timeout(struct net_device *netdev)
26432 + struct e1000_adapter *adapter = netdev_priv(netdev);
26434 + /* Do the reset outside of interrupt context */
26435 + adapter->tx_timeout_count++;
26436 + schedule_work(&adapter->reset_task);
26439 +static void e1000_reset_task(struct work_struct *work)
26441 + struct e1000_adapter *adapter;
26442 + adapter = container_of(work, struct e1000_adapter, reset_task);
26444 + e1000e_reinit_locked(adapter);
26448 + * e1000_get_stats - Get System Network Statistics
26449 + * @netdev: network interface device structure
26451 + * Returns the address of the device statistics structure.
26452 + * The statistics are actually updated from the timer callback.
26454 +static struct net_device_stats *e1000_get_stats(struct net_device *netdev)
26456 + struct e1000_adapter *adapter = netdev_priv(netdev);
26458 + /* only return the current stats */
26459 + return &adapter->net_stats;
26463 + * e1000_change_mtu - Change the Maximum Transfer Unit
26464 + * @netdev: network interface device structure
26465 + * @new_mtu: new value for maximum frame size
26467 + * Returns 0 on success, negative on failure
26469 +static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
26471 + struct e1000_adapter *adapter = netdev_priv(netdev);
26472 + int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
26474 + /* Jumbo frame support */
26475 + if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
26476 + !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
26477 + e_err("Jumbo Frames not supported.\n");
26481 + /* Supported frame sizes */
26482 + if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
26483 + (max_frame > adapter->max_hw_frame_size)) {
26484 + e_err("Unsupported MTU setting\n");
26488 + while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
26490 + /* e1000e_down has a dependency on max_frame_size */
26491 + adapter->max_frame_size = max_frame;
26492 + if (netif_running(netdev))
26493 + e1000e_down(adapter);
26496 + * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
26497 + * means we reserve 2 more, this pushes us to allocate from the next
26498 + * larger slab size.
26499 + * i.e. RXBUFFER_2048 --> size-4096 slab
26500 + * However with the new *_jumbo_rx* routines, jumbo receives will use
26501 + * fragmented skbs
26504 + if (max_frame <= 256)
26505 + adapter->rx_buffer_len = 256;
26506 + else if (max_frame <= 512)
26507 + adapter->rx_buffer_len = 512;
26508 + else if (max_frame <= 1024)
26509 + adapter->rx_buffer_len = 1024;
26510 + else if (max_frame <= 2048)
26511 + adapter->rx_buffer_len = 2048;
26512 +#ifdef CONFIG_E1000E_NAPI
26514 + adapter->rx_buffer_len = 4096;
26516 + else if (max_frame <= 4096)
26517 + adapter->rx_buffer_len = 4096;
26518 + else if (max_frame <= 8192)
26519 + adapter->rx_buffer_len = 8192;
26520 + else if (max_frame <= 16384)
26521 + adapter->rx_buffer_len = 16384;
26524 + /* adjust allocation if LPE protects us, and we aren't using SBP */
26525 + if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
26526 + (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
26527 + adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
26530 + e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
26531 + netdev->mtu = new_mtu;
26533 + if (netif_running(netdev))
26534 + e1000e_up(adapter);
26536 + e1000e_reset(adapter);
26538 + clear_bit(__E1000_RESETTING, &adapter->state);
26543 +static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
26546 + struct e1000_adapter *adapter = netdev_priv(netdev);
26547 + struct mii_ioctl_data *data = if_mii(ifr);
26549 + if (adapter->hw.phy.media_type != e1000_media_type_copper)
26550 + return -EOPNOTSUPP;
26553 + case SIOCGMIIPHY:
26554 + data->phy_id = adapter->hw.phy.addr;
26556 + case SIOCGMIIREG:
26557 + if (!capable(CAP_NET_ADMIN))
26559 + switch (data->reg_num & 0x1F) {
26561 + data->val_out = adapter->phy_regs.bmcr;
26564 + data->val_out = adapter->phy_regs.bmsr;
26566 + case MII_PHYSID1:
26567 + data->val_out = (adapter->hw.phy.id >> 16);
26569 + case MII_PHYSID2:
26570 + data->val_out = (adapter->hw.phy.id & 0xFFFF);
26572 + case MII_ADVERTISE:
26573 + data->val_out = adapter->phy_regs.advertise;
26576 + data->val_out = adapter->phy_regs.lpa;
26578 + case MII_EXPANSION:
26579 + data->val_out = adapter->phy_regs.expansion;
26581 + case MII_CTRL1000:
26582 + data->val_out = adapter->phy_regs.ctrl1000;
26584 + case MII_STAT1000:
26585 + data->val_out = adapter->phy_regs.stat1000;
26587 + case MII_ESTATUS:
26588 + data->val_out = adapter->phy_regs.estatus;
26594 + case SIOCSMIIREG:
26596 + return -EOPNOTSUPP;
26601 +static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
26604 + case SIOCGMIIPHY:
26605 + case SIOCGMIIREG:
26606 + case SIOCSMIIREG:
26607 + return e1000_mii_ioctl(netdev, ifr, cmd);
26608 +#ifdef ETHTOOL_OPS_COMPAT
26609 + case SIOCETHTOOL:
26610 + return ethtool_ioctl(ifr);
26613 + return -EOPNOTSUPP;
26617 +static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
26619 + struct e1000_hw *hw = &adapter->hw;
26624 + /* copy MAC RARs to PHY RARs */
26625 + for (i = 0; i < adapter->hw.mac.rar_entry_count; i++) {
26626 + mac_reg = er32(RAL(i));
26627 + e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
26628 + e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
26629 + mac_reg = er32(RAH(i));
26630 + e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
26631 + e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0xFFFF));
26634 + /* copy MAC MTA to PHY MTA */
26635 + for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
26636 + mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
26637 + e1e_wphy(hw, BM_MTA(i), (u16)(mac_reg & 0xFFFF));
26638 + e1e_wphy(hw, BM_MTA(i) + 1, (u16)((mac_reg >> 16) & 0xFFFF));
26641 + /* configure PHY Rx Control register */
26642 + e1e_rphy(&adapter->hw, BM_RCTL, &phy_reg);
26643 + mac_reg = er32(RCTL);
26644 + if (mac_reg & E1000_RCTL_UPE)
26645 + phy_reg |= BM_RCTL_UPE;
26646 + if (mac_reg & E1000_RCTL_MPE)
26647 + phy_reg |= BM_RCTL_MPE;
26648 + phy_reg &= ~(BM_RCTL_MO_MASK);
26649 + if (mac_reg & E1000_RCTL_MO_3)
26650 + phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
26651 + << BM_RCTL_MO_SHIFT);
26652 + if (mac_reg & E1000_RCTL_BAM)
26653 + phy_reg |= BM_RCTL_BAM;
26654 + if (mac_reg & E1000_RCTL_PMCF)
26655 + phy_reg |= BM_RCTL_PMCF;
26656 + mac_reg = er32(CTRL);
26657 + if (mac_reg & E1000_CTRL_RFCE)
26658 + phy_reg |= BM_RCTL_RFCE;
26659 + e1e_wphy(&adapter->hw, BM_RCTL, phy_reg);
26661 + /* enable PHY wakeup in MAC register */
26662 + ew32(WUFC, wufc);
26663 + ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
26665 + /* configure and enable PHY wakeup in PHY registers */
26666 + e1e_wphy(&adapter->hw, BM_WUFC, wufc);
26667 + e1e_wphy(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
26669 + /* activate PHY wakeup */
26670 + retval = hw->phy.ops.acquire(hw);
26672 + e_err("Could not acquire PHY\n");
26675 + e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
26676 + (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
26677 + retval = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
26679 + e_err("Could not read PHY page 769\n");
26682 + phy_reg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
26683 + retval = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
26685 + e_err("Could not set PHY Host Wakeup bit\n");
26687 + hw->phy.ops.release(hw);
26692 +static int e1000_suspend(struct pci_dev *pdev, pm_message_t state)
26694 + struct net_device *netdev = pci_get_drvdata(pdev);
26695 + struct e1000_adapter *adapter = netdev_priv(netdev);
26696 + struct e1000_hw *hw = &adapter->hw;
26697 + u32 ctrl, ctrl_ext, rctl, status;
26698 + u32 wufc = adapter->wol;
26701 + netif_device_detach(netdev);
26703 + if (netif_running(netdev)) {
26704 + WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
26705 + e1000e_down(adapter);
26706 + e1000_free_irq(adapter);
26708 +#ifdef CONFIG_E1000E_MSIX
26709 + e1000e_reset_interrupt_capability(adapter);
26712 + retval = pci_save_state(pdev);
26716 + status = er32(STATUS);
26717 + if (status & E1000_STATUS_LU)
26718 + wufc &= ~E1000_WUFC_LNKC;
26721 + e1000_setup_rctl(adapter);
26722 + e1000_set_multi(netdev);
26724 + /* turn on all-multi mode if wake on multicast is enabled */
26725 + if (wufc & E1000_WUFC_MC) {
26726 + rctl = er32(RCTL);
26727 + rctl |= E1000_RCTL_MPE;
26728 + ew32(RCTL, rctl);
26731 + ctrl = er32(CTRL);
26732 + /* advertise wake from D3Cold */
26733 + #define E1000_CTRL_ADVD3WUC 0x00100000
26734 + /* phy power management enable */
26735 + #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
26736 + ctrl |= E1000_CTRL_ADVD3WUC;
26737 + if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
26738 + ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
26739 + ew32(CTRL, ctrl);
26741 + if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
26742 + adapter->hw.phy.media_type ==
26743 + e1000_media_type_internal_serdes) {
26744 + /* keep the laser running in D3 */
26745 + ctrl_ext = er32(CTRL_EXT);
26746 + ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
26747 + ew32(CTRL_EXT, ctrl_ext);
26750 + if (adapter->flags & FLAG_IS_ICH)
26751 + e1000e_disable_gig_wol_ich8lan(&adapter->hw);
26753 + /* Allow time for pending master requests to run */
26754 + e1000e_disable_pcie_master(&adapter->hw);
26756 + if ((adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) &&
26757 + !(hw->mac.ops.check_mng_mode(hw))) {
26758 + /* enable wakeup by the PHY */
26759 + retval = e1000_init_phy_wakeup(adapter, wufc);
26763 + /* enable wakeup by the MAC */
26764 + ew32(WUFC, wufc);
26765 + ew32(WUC, E1000_WUC_PME_EN);
26767 + pci_enable_wake(pdev, PCI_D3hot, 1);
26768 + pci_enable_wake(pdev, PCI_D3cold, 1);
26772 + pci_enable_wake(pdev, PCI_D3hot, 0);
26773 + pci_enable_wake(pdev, PCI_D3cold, 0);
26776 + /* make sure adapter isn't asleep if manageability is enabled */
26777 + if (adapter->flags & FLAG_MNG_PT_ENABLED) {
26778 + pci_enable_wake(pdev, PCI_D3hot, 1);
26779 + pci_enable_wake(pdev, PCI_D3cold, 1);
26782 + if (adapter->hw.phy.type == e1000_phy_igp_3)
26783 + e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
26786 + * Release control of h/w to f/w. If f/w is AMT enabled, this
26787 + * would have already happened in close and is redundant.
26789 + e1000_release_hw_control(adapter);
26791 + pci_disable_device(pdev);
26794 + * The pci-e switch on some quad port adapters will report a
26795 + * correctable error when the MAC transitions from D0 to D3. To
26796 + * prevent this we need to mask off the correctable errors on the
26797 + * downstream port of the pci-e switch.
26799 + if (adapter->flags & FLAG_IS_QUAD_PORT) {
26800 + struct pci_dev *us_dev = pdev->bus->self;
26801 + int pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
26804 + pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
26805 + pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
26806 + (devctl & ~PCI_EXP_DEVCTL_CERE));
26808 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
26810 + pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
26812 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
26818 +static void e1000e_disable_l1aspm(struct pci_dev *pdev)
26824 + * 82573 workaround - disable L1 ASPM on mobile chipsets
26826 + * L1 ASPM on various mobile (ich7) chipsets do not behave properly
26827 + * resulting in lost data or garbage information on the pci-e link
26828 + * level. This could result in (false) bad EEPROM checksum errors,
26829 + * long ping times (up to 2s) or even a system freeze/hang.
26831 + * Unfortunately this feature saves about 1W power consumption when
26834 + pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
26835 + pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &val);
26837 + dev_warn(&pdev->dev, "Disabling L1 ASPM\n");
26839 + pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, val);
26844 +static int e1000_resume(struct pci_dev *pdev)
26846 + struct net_device *netdev = pci_get_drvdata(pdev);
26847 + struct e1000_adapter *adapter = netdev_priv(netdev);
26848 + struct e1000_hw *hw = &adapter->hw;
26851 + pci_set_power_state(pdev, PCI_D0);
26852 + pci_restore_state(pdev);
26853 + e1000e_disable_l1aspm(pdev);
26855 + err = pci_enable_device_mem(pdev);
26857 + dev_err(&pdev->dev,
26858 + "Cannot enable PCI device from suspend\n");
26862 + /* AER (Advanced Error Reporting) hooks */
26863 + err = pci_enable_pcie_error_reporting(pdev);
26865 + dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
26867 + /* non-fatal, continue */
26870 + pci_set_master(pdev);
26872 + pci_enable_wake(pdev, PCI_D3hot, 0);
26873 + pci_enable_wake(pdev, PCI_D3cold, 0);
26875 +#ifdef CONFIG_E1000E_MSIX
26876 + e1000e_set_interrupt_capability(adapter);
26878 + if (netif_running(netdev)) {
26879 + err = e1000_request_irq(adapter);
26884 + e1000e_power_up_phy(adapter);
26886 + /* report the system wakeup cause from S3/S4 */
26887 + if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
26890 + e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
26892 + e_info("PHY Wakeup cause - %s\n",
26893 + phy_data & E1000_WUS_EX ? "Unicast Packet" :
26894 + phy_data & E1000_WUS_MC ? "Multicast Packet" :
26895 + phy_data & E1000_WUS_BC ? "Broadcast Packet" :
26896 + phy_data & E1000_WUS_MAG ? "Magic Packet" :
26897 + phy_data & E1000_WUS_LNKC ? "Link Status "
26898 + " Change" : "other");
26900 + e1e_wphy(&adapter->hw, BM_WUS, ~0);
26902 + u32 wus = er32(WUS);
26904 + e_info("MAC Wakeup cause - %s\n",
26905 + wus & E1000_WUS_EX ? "Unicast Packet" :
26906 + wus & E1000_WUS_MC ? "Multicast Packet" :
26907 + wus & E1000_WUS_BC ? "Broadcast Packet" :
26908 + wus & E1000_WUS_MAG ? "Magic Packet" :
26909 + wus & E1000_WUS_LNKC ? "Link Status Change" :
26915 + e1000e_reset(adapter);
26917 + e1000_init_manageability(adapter);
26919 + if (netif_running(netdev))
26920 + e1000e_up(adapter);
26922 + netif_device_attach(netdev);
26925 + * If the controller has AMT, do not set DRV_LOAD until the interface
26926 + * is up. For all other cases, let the f/w know that the h/w is now
26927 + * under the control of the driver.
26929 + if (!(adapter->flags & FLAG_HAS_AMT))
26930 + e1000_get_hw_control(adapter);
26936 +#ifndef USE_REBOOT_NOTIFIER
26937 +static void e1000_shutdown(struct pci_dev *pdev)
26939 + e1000_suspend(pdev, PMSG_SUSPEND);
26942 +static struct pci_driver e1000_driver;
26943 +static int e1000_notify_reboot(struct notifier_block *nb, unsigned long event,
26946 + struct pci_dev *pdev = NULL;
26951 + case SYS_POWER_OFF:
26952 + while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {
26953 + if (pci_dev_driver(pdev) == &e1000_driver)
26954 + e1000_suspend(pdev, PMSG_SUSPEND);
26958 + return NOTIFY_DONE;
26961 +static struct notifier_block e1000_notifier_reboot = {
26962 + .notifier_call = e1000_notify_reboot,
26968 +#ifdef CONFIG_NET_POLL_CONTROLLER
26970 + * Polling 'interrupt' - used by things like netconsole to send skbs
26971 + * without having to re-enable interrupts. It's not called while
26972 + * the interrupt routine is executing.
26974 +static void e1000_netpoll(struct net_device *netdev)
26976 + struct e1000_adapter *adapter = netdev_priv(netdev);
26978 + disable_irq(adapter->pdev->irq);
26979 + e1000_intr(adapter->pdev->irq, netdev);
26981 +#ifndef CONFIG_E1000E_NAPI
26982 + adapter->clean_rx(adapter);
26985 + enable_irq(adapter->pdev->irq);
26989 +#ifdef HAVE_PCI_ERS
26991 + * e1000_io_error_detected - called when PCI error is detected
26992 + * @pdev: Pointer to PCI device
26993 + * @state: The current pci connection state
26995 + * This function is called after a PCI bus error affecting
26996 + * this device has been detected.
26998 +static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
26999 + pci_channel_state_t state)
27001 + struct net_device *netdev = pci_get_drvdata(pdev);
27002 + struct e1000_adapter *adapter = netdev_priv(netdev);
27004 + netif_device_detach(netdev);
27006 + if (netif_running(netdev))
27007 + e1000e_down(adapter);
27008 + pci_disable_device(pdev);
27010 + /* Request a slot slot reset. */
27011 + return PCI_ERS_RESULT_NEED_RESET;
27015 + * e1000_io_slot_reset - called after the pci bus has been reset.
27016 + * @pdev: Pointer to PCI device
27018 + * Restart the card from scratch, as if from a cold-boot. Implementation
27019 + * resembles the first-half of the e1000_resume routine.
27021 +static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
27023 + struct net_device *netdev = pci_get_drvdata(pdev);
27024 + struct e1000_adapter *adapter = netdev_priv(netdev);
27025 + struct e1000_hw *hw = &adapter->hw;
27027 + pci_ers_result_t result;
27029 + e1000e_disable_l1aspm(pdev);
27030 + err = pci_enable_device_mem(pdev);
27032 + dev_err(&pdev->dev,
27033 + "Cannot re-enable PCI device after reset.\n");
27034 + result = PCI_ERS_RESULT_DISCONNECT;
27036 + pci_set_master(pdev);
27037 + pci_restore_state(pdev);
27039 + pci_enable_wake(pdev, PCI_D3hot, 0);
27040 + pci_enable_wake(pdev, PCI_D3cold, 0);
27042 + e1000e_reset(adapter);
27044 + result = PCI_ERS_RESULT_RECOVERED;
27047 + pci_cleanup_aer_uncorrect_error_status(pdev);
27053 + * e1000_io_resume - called when traffic can start flowing again.
27054 + * @pdev: Pointer to PCI device
27056 + * This callback is called when the error recovery driver tells us that
27057 + * its OK to resume normal operation. Implementation resembles the
27058 + * second-half of the e1000_resume routine.
27060 +static void e1000_io_resume(struct pci_dev *pdev)
27062 + struct net_device *netdev = pci_get_drvdata(pdev);
27063 + struct e1000_adapter *adapter = netdev_priv(netdev);
27065 + e1000_init_manageability(adapter);
27067 + if (netif_running(netdev)) {
27068 + if (e1000e_up(adapter)) {
27069 + dev_err(&pdev->dev,
27070 + "can't bring device back up after reset\n");
27075 + netif_device_attach(netdev);
27078 + * If the controller has AMT, do not set DRV_LOAD until the interface
27079 + * is up. For all other cases, let the f/w know that the h/w is now
27080 + * under the control of the driver.
27082 + if (!(adapter->flags & FLAG_HAS_AMT))
27083 + e1000_get_hw_control(adapter);
27086 +#endif /* HAVE_PCI_ERS */
27088 +static void e1000_print_device_info(struct e1000_adapter *adapter)
27090 + struct e1000_hw *hw = &adapter->hw;
27091 + struct net_device *netdev = adapter->netdev;
27094 + /* print bus type/speed/width info */
27095 + e_info("(PCI Express:2.5GB/s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
27097 + ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
27099 + /* MAC address */
27100 + netdev->dev_addr[0], netdev->dev_addr[1],
27101 + netdev->dev_addr[2], netdev->dev_addr[3],
27102 + netdev->dev_addr[4], netdev->dev_addr[5]);
27103 + e_info("Intel(R) PRO/%s Network Connection\n",
27104 + (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
27105 + e1000e_read_pba_num(hw, &pba_num);
27106 + e_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
27107 + hw->mac.type, hw->phy.type, (pba_num >> 8), (pba_num & 0xff));
27110 +static void e1000_eeprom_checks(struct e1000_adapter *adapter)
27112 + struct e1000_hw *hw = &adapter->hw;
27115 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0))
27116 + struct pci_dev *pdev = adapter->pdev;
27119 + if (hw->mac.type != e1000_82573)
27122 + ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
27123 + if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) {
27124 + /* Deep Smart Power Down (DSPD) */
27125 + dev_warn(&adapter->pdev->dev,
27126 + "Warning: detected DSPD enabled in EEPROM\n");
27129 + ret_val = e1000_read_nvm(hw, NVM_INIT_3GIO_3, 1, &buf);
27130 + if (!ret_val && (le16_to_cpu(buf) & (3 << 2))) {
27131 + /* ASPM enable */
27132 + dev_warn(&adapter->pdev->dev,
27133 + "Warning: detected ASPM enabled in EEPROM\n");
27137 +s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
27141 + cap_offset = pci_find_capability(hw->adapter->pdev, PCI_CAP_ID_EXP);
27143 + return -E1000_ERR_CONFIG;
27145 + pci_read_config_word(hw->adapter->pdev, cap_offset + reg, value);
27147 + return E1000_SUCCESS;
27150 +#ifdef HAVE_NET_DEVICE_OPS
27151 +static const struct net_device_ops e1000e_netdev_ops = {
27152 + .ndo_open = e1000_open,
27153 + .ndo_stop = e1000_close,
27154 + .ndo_start_xmit = e1000_xmit_frame,
27155 + .ndo_get_stats = e1000_get_stats,
27156 + .ndo_set_multicast_list = e1000_set_multi,
27157 + .ndo_set_mac_address = e1000_set_mac,
27158 + .ndo_change_mtu = e1000_change_mtu,
27159 + .ndo_do_ioctl = e1000_ioctl,
27160 + .ndo_tx_timeout = e1000_tx_timeout,
27161 + .ndo_validate_addr = eth_validate_addr,
27163 + .ndo_vlan_rx_register = e1000_vlan_rx_register,
27164 + .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
27165 + .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
27166 +#ifdef CONFIG_NET_POLL_CONTROLLER
27167 + .ndo_poll_controller = e1000_netpoll,
27171 +#endif /* HAVE_NET_DEVICE_OPS */
27173 + * e1000_probe - Device Initialization Routine
27174 + * @pdev: PCI device information struct
27175 + * @ent: entry in e1000e_pci_tbl
27177 + * Returns 0 on success, negative on failure
27179 + * e1000_probe initializes an adapter identified by a pci_dev structure.
27180 + * The OS initialization, configuring of the adapter private structure,
27181 + * and a hardware reset occur.
27183 +static int __devinit e1000_probe(struct pci_dev *pdev,
27184 + const struct pci_device_id *ent)
27186 + struct net_device *netdev;
27187 + struct e1000_adapter *adapter;
27188 + struct e1000_hw *hw;
27189 + const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
27190 + static int cards_found;
27191 + int i, err, pci_using_dac;
27192 + u16 eeprom_data = 0;
27193 + u16 eeprom_apme_mask = E1000_EEPROM_APME;
27195 + e1000e_disable_l1aspm(pdev);
27197 + err = pci_enable_device_mem(pdev);
27201 + pci_using_dac = 0;
27202 + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
27204 + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
27206 + pci_using_dac = 1;
27208 + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
27210 + err = pci_set_consistent_dma_mask(pdev,
27211 + DMA_BIT_MASK(32));
27213 + printk(KERN_ERR "%s: No usable DMA "
27214 + "configuration, aborting\n",
27221 + err = pci_request_selected_regions_exclusive(pdev,
27222 + pci_select_bars(pdev, IORESOURCE_MEM),
27223 + e1000e_driver_name);
27225 + goto err_pci_reg;
27227 + pci_set_master(pdev);
27230 + netdev = alloc_etherdev(sizeof(struct e1000_adapter));
27232 + goto err_alloc_etherdev;
27234 + SET_MODULE_OWNER(netdev);
27235 + SET_NETDEV_DEV(netdev, &pdev->dev);
27237 + pci_set_drvdata(pdev, netdev);
27238 + adapter = netdev_priv(netdev);
27239 + hw = &adapter->hw;
27240 + adapter->netdev = netdev;
27241 + adapter->pdev = pdev;
27242 + adapter->ei = ei;
27243 + adapter->pba = ei->pba;
27244 + adapter->flags = ei->flags;
27245 + adapter->flags2 = ei->flags2;
27246 + adapter->hw.adapter = adapter;
27247 + adapter->hw.mac.type = ei->mac;
27248 + adapter->max_hw_frame_size = ei->max_hw_frame_size;
27249 + adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
27251 + /* PCI config space info */
27252 + hw->device_id = pdev->device;
27253 +#ifdef HAVE_PCI_ERS
27254 + err = pci_save_state(pdev);
27256 + goto err_ioremap;
27260 + adapter->hw.hw_addr = pci_ioremap_bar(pdev, 0);
27261 + if (!adapter->hw.hw_addr)
27262 + goto err_ioremap;
27264 + if ((adapter->flags & FLAG_HAS_FLASH) &&
27265 + (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
27266 + adapter->hw.flash_address = pci_ioremap_bar(pdev, 1);
27267 + if (!adapter->hw.flash_address)
27268 + goto err_flashmap;
27271 + adapter->bd_number = cards_found++;
27273 + e1000e_check_options(adapter);
27275 + /* setup adapter struct */
27276 + err = e1000_sw_init(adapter);
27278 + goto err_sw_init;
27280 + if (ei->get_variants) {
27281 + err = ei->get_variants(adapter);
27283 + goto err_hw_init;
27286 + /* construct the net_device struct */
27287 +#ifdef HAVE_NET_DEVICE_OPS
27288 + netdev->netdev_ops = &e1000e_netdev_ops;
27290 + netdev->open = &e1000_open;
27291 + netdev->stop = &e1000_close;
27292 + netdev->hard_start_xmit = &e1000_xmit_frame;
27293 + netdev->get_stats = &e1000_get_stats;
27294 + netdev->set_multicast_list = &e1000_set_multi;
27295 + netdev->set_mac_address = &e1000_set_mac;
27296 + netdev->change_mtu = &e1000_change_mtu;
27297 + netdev->do_ioctl = &e1000_ioctl;
27298 + netdev->tx_timeout = &e1000_tx_timeout;
27299 + netdev->vlan_rx_register = e1000_vlan_rx_register;
27300 + netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
27301 + netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
27302 +#ifdef CONFIG_NET_POLL_CONTROLLER
27303 + netdev->poll_controller = e1000_netpoll;
27305 +#endif /* HAVE_NET_DEVICE_OPS */
27306 + e1000e_set_ethtool_ops(netdev);
27307 + netdev->watchdog_timeo = 5 * HZ;
27308 +#ifdef CONFIG_E1000E_NAPI
27309 + netif_napi_add(netdev, &adapter->napi, e1000_poll, 64);
27311 + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
27313 + hw->mac.ops.get_bus_info(&adapter->hw);
27315 + adapter->hw.phy.autoneg_wait_to_complete = 0;
27317 + /* Copper options */
27318 + if (adapter->hw.phy.media_type == e1000_media_type_copper) {
27319 + adapter->hw.phy.mdix = AUTO_ALL_MODES;
27320 + adapter->hw.phy.disable_polarity_correction = 0;
27321 + adapter->hw.phy.ms_type = e1000_ms_hw_default;
27324 + if (e1000_check_reset_block(&adapter->hw))
27325 + e_info("PHY reset is blocked due to SOL/IDER session.\n");
27327 + netdev->features = NETIF_F_SG |
27328 + NETIF_F_HW_CSUM |
27329 + NETIF_F_HW_VLAN_TX |
27330 + NETIF_F_HW_VLAN_RX;
27332 + if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
27333 + netdev->features |= NETIF_F_HW_VLAN_FILTER;
27335 +#ifdef NETIF_F_TSO
27336 + netdev->features |= NETIF_F_TSO;
27337 +#ifdef NETIF_F_TSO6
27338 + netdev->features |= NETIF_F_TSO6;
27342 + if (pci_using_dac)
27343 + netdev->features |= NETIF_F_HIGHDMA;
27346 + if (e1000e_enable_mng_pass_thru(&adapter->hw))
27347 + adapter->flags |= FLAG_MNG_PT_ENABLED;
27350 + * before reading the NVM, reset the controller to
27351 + * put the device in a known good starting state
27353 + adapter->hw.mac.ops.reset_hw(&adapter->hw);
27356 + * systems with ASPM and others may see the checksum fail on the first
27357 + * attempt. Let's give it a few tries
27359 + for (i = 0;; i++) {
27360 + if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
27363 + e_err("The NVM Checksum Is Not Valid\n");
27369 + e1000_eeprom_checks(adapter);
27371 + /* copy the MAC address out of the NVM */
27372 + if (e1000e_read_mac_addr(&adapter->hw))
27373 + e_err("NVM Read Error while reading MAC address\n");
27375 + memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
27376 +#ifdef ETHTOOL_GPERMADDR
27377 + memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
27379 + if (!is_valid_ether_addr(netdev->perm_addr)) {
27381 + if (!is_valid_ether_addr(netdev->dev_addr)) {
27383 + e_err("Invalid MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
27384 + netdev->dev_addr[0], netdev->dev_addr[1],
27385 + netdev->dev_addr[2], netdev->dev_addr[3],
27386 + netdev->dev_addr[4], netdev->dev_addr[5]);
27391 + init_timer(&adapter->watchdog_timer);
27392 + adapter->watchdog_timer.function = &e1000_watchdog;
27393 + adapter->watchdog_timer.data = (unsigned long) adapter;
27395 + init_timer(&adapter->phy_info_timer);
27396 + adapter->phy_info_timer.function = &e1000_update_phy_info;
27397 + adapter->phy_info_timer.data = (unsigned long) adapter;
27399 + INIT_WORK(&adapter->reset_task, e1000_reset_task);
27400 + INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
27401 + INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
27402 + INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
27404 + /* Initialize link parameters. User can change them with ethtool */
27405 + adapter->hw.mac.autoneg = 1;
27406 + adapter->fc_autoneg = 1;
27407 + if (adapter->hw.mac.type == e1000_pchlan) {
27408 + /* Workaround h/w hang when Tx flow control enabled */
27409 + adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
27410 + adapter->hw.fc.current_mode = e1000_fc_rx_pause;
27412 + adapter->hw.fc.requested_mode = e1000_fc_default;
27413 + adapter->hw.fc.current_mode = e1000_fc_default;
27415 + adapter->hw.phy.autoneg_advertised = 0x2f;
27417 + /* ring size defaults */
27418 + adapter->rx_ring->count = 256;
27419 + adapter->tx_ring->count = 256;
27422 + * Initial Wake on LAN setting - If APM wake is enabled in
27423 + * the EEPROM, enable the ACPI Magic Packet filter
27425 + if (adapter->flags & FLAG_APME_IN_WUC) {
27426 + /* APME bit in EEPROM is mapped to WUC.APME */
27427 + eeprom_data = er32(WUC);
27428 + eeprom_apme_mask = E1000_WUC_APME;
27429 + if (eeprom_data & E1000_WUC_PHY_WAKE)
27430 + adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
27431 + } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
27432 + if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
27433 + (adapter->hw.bus.func == 1))
27434 + e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
27435 + 1, &eeprom_data);
27437 + e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
27438 + 1, &eeprom_data);
27441 + /* fetch WoL from EEPROM */
27442 + if (eeprom_data & eeprom_apme_mask)
27443 + adapter->eeprom_wol |= E1000_WUFC_MAG;
27446 + * now that we have the eeprom settings, apply the special cases
27447 + * where the eeprom may be wrong or the board simply won't support
27448 + * wake on lan on a particular port
27450 + if (!(adapter->flags & FLAG_HAS_WOL))
27451 + adapter->eeprom_wol = 0;
27453 + /* initialize the wol settings based on the eeprom settings */
27454 + adapter->wol = adapter->eeprom_wol;
27455 + device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
27457 + /* save off EEPROM version number */
27458 + e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
27460 + /* reset the hardware with the new settings */
27461 + e1000e_reset(adapter);
27464 + * If the controller has AMT, do not set DRV_LOAD until the interface
27465 + * is up. For all other cases, let the f/w know that the h/w is now
27466 + * under the control of the driver.
27468 + if (!(adapter->flags & FLAG_HAS_AMT))
27469 + e1000_get_hw_control(adapter);
27471 + /* tell the stack to leave us alone until e1000_open() is called */
27472 + netif_carrier_off(netdev);
27473 + netif_tx_stop_all_queues(netdev);
27475 + strcpy(netdev->name, "eth%d");
27476 + err = register_netdev(netdev);
27478 + goto err_register;
27480 + e1000_print_device_info(adapter);
27485 + if (!(adapter->flags & FLAG_HAS_AMT))
27486 + e1000_release_hw_control(adapter);
27488 + if (!e1000_check_reset_block(&adapter->hw))
27489 + e1000_phy_hw_reset(&adapter->hw);
27491 + kfree(adapter->tx_ring);
27492 + kfree(adapter->rx_ring);
27494 +#ifdef CONFIG_E1000E_MSIX
27495 + e1000e_reset_interrupt_capability(adapter);
27496 +#endif /* CONFIG_E1000E_MSIX */
27497 + if (adapter->hw.flash_address)
27498 + iounmap(adapter->hw.flash_address);
27500 + iounmap(adapter->hw.hw_addr);
27502 + free_netdev(netdev);
27503 +err_alloc_etherdev:
27504 + pci_release_selected_regions(pdev,
27505 + pci_select_bars(pdev, IORESOURCE_MEM));
27508 + pci_disable_device(pdev);
27513 + * e1000_remove - Device Removal Routine
27514 + * @pdev: PCI device information struct
27516 + * e1000_remove is called by the PCI subsystem to alert the driver
27517 + * that it should release a PCI device. The could be caused by a
27518 + * Hot-Plug event, or because the driver is going to be removed from
27521 +static void __devexit e1000_remove(struct pci_dev *pdev)
27523 + struct net_device *netdev = pci_get_drvdata(pdev);
27524 + struct e1000_adapter *adapter = netdev_priv(netdev);
27527 + * flush_scheduled work may reschedule our watchdog task, so
27528 + * explicitly disable watchdog tasks from being rescheduled
27530 + set_bit(__E1000_DOWN, &adapter->state);
27531 + del_timer_sync(&adapter->watchdog_timer);
27532 + del_timer_sync(&adapter->phy_info_timer);
27534 + flush_scheduled_work();
27537 + * Release control of h/w to f/w. If f/w is AMT enabled, this
27538 + * would have already happened in close and is redundant.
27540 + e1000_release_hw_control(adapter);
27542 + unregister_netdev(netdev);
27544 + if (!e1000_check_reset_block(&adapter->hw))
27545 + e1000_phy_hw_reset(&adapter->hw);
27547 +#ifdef CONFIG_E1000E_MSIX
27548 + e1000e_reset_interrupt_capability(adapter);
27549 +#endif /* CONFIG_E1000E_MSIX */
27550 + kfree(adapter->tx_ring);
27551 + kfree(adapter->rx_ring);
27553 + iounmap(adapter->hw.hw_addr);
27554 + if (adapter->hw.flash_address)
27555 + iounmap(adapter->hw.flash_address);
27556 + pci_release_selected_regions(pdev,
27557 + pci_select_bars(pdev, IORESOURCE_MEM));
27559 + free_netdev(netdev);
27561 + /* AER disable */
27562 + pci_disable_pcie_error_reporting(pdev);
27564 + pci_disable_device(pdev);
27567 +#ifdef HAVE_PCI_ERS
27568 +/* PCI Error Recovery (ERS) */
27569 +static struct pci_error_handlers e1000_err_handler = {
27570 + .error_detected = e1000_io_error_detected,
27571 + .slot_reset = e1000_io_slot_reset,
27572 + .resume = e1000_io_resume,
27576 +static struct pci_device_id e1000e_pci_tbl[] = {
27577 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
27578 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
27579 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
27580 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
27581 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
27582 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
27583 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
27584 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
27585 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
27587 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
27588 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
27589 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
27590 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
27592 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
27593 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
27594 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
27596 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
27597 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
27598 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
27600 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
27601 + board_80003es2lan },
27602 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
27603 + board_80003es2lan },
27604 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
27605 + board_80003es2lan },
27606 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
27607 + board_80003es2lan },
27609 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
27610 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
27611 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
27612 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
27613 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
27614 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
27615 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
27617 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
27618 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
27619 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
27620 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
27621 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
27622 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
27623 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
27624 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
27625 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
27627 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
27628 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
27629 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
27631 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
27632 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
27634 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
27635 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
27636 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
27637 + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
27639 + { } /* terminate list */
27641 +MODULE_DEVICE_TABLE(pci, e1000e_pci_tbl);
27643 +/* PCI Device API Driver */
27644 +static struct pci_driver e1000_driver = {
27645 + .name = e1000e_driver_name,
27646 + .id_table = e1000e_pci_tbl,
27647 + .probe = e1000_probe,
27648 + .remove = __devexit_p(e1000_remove),
27650 + /* Power Management Hooks */
27651 + .suspend = e1000_suspend,
27652 + .resume = e1000_resume,
27654 +#ifndef USE_REBOOT_NOTIFIER
27655 + .shutdown = e1000_shutdown,
27657 +#ifdef HAVE_PCI_ERS
27658 + .err_handler = &e1000_err_handler
27663 + * e1000_init_module - Driver Registration Routine
27665 + * e1000_init_module is the first routine called when the driver is
27666 + * loaded. All it does is register with the PCI subsystem.
27668 +static int __init e1000_init_module(void)
27671 + printk(KERN_INFO "%s: Intel(R) PRO/1000 Network Driver - %s\n",
27672 + e1000e_driver_name, e1000e_driver_version);
27673 + printk(KERN_INFO "%s: Copyright(c) 1999 - 2009 Intel Corporation.\n",
27674 + e1000e_driver_name);
27675 + ret = pci_register_driver(&e1000_driver);
27676 +#ifdef USE_REBOOT_NOTIFIER
27678 + register_reboot_notifier(&e1000_notifier_reboot);
27683 +module_init(e1000_init_module);
27686 + * e1000_exit_module - Driver Exit Cleanup Routine
27688 + * e1000_exit_module is called just before the driver is removed
27691 +static void __exit e1000_exit_module(void)
27693 +#ifdef USE_REBOOT_NOTIFIER
27694 + unregister_reboot_notifier(&e1000_notifier_reboot);
27696 + pci_unregister_driver(&e1000_driver);
27698 +module_exit(e1000_exit_module);
27701 +MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
27702 +MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
27703 +MODULE_LICENSE("GPL");
27704 +MODULE_VERSION(DRV_VERSION);
27707 diff -Nurp linux-2.6.22-0/drivers/net/e1000e/param.c linux-2.6.22-10/drivers/net/e1000e/param.c
27708 --- linux-2.6.22-0/drivers/net/e1000e/param.c 1970-01-01 01:00:00.000000000 +0100
27709 +++ linux-2.6.22-10/drivers/net/e1000e/param.c 2009-06-24 00:32:20.000000000 +0200
27711 +/*******************************************************************************
27713 + Intel PRO/1000 Linux driver
27714 + Copyright(c) 1999 - 2009 Intel Corporation.
27716 + This program is free software; you can redistribute it and/or modify it
27717 + under the terms and conditions of the GNU General Public License,
27718 + version 2, as published by the Free Software Foundation.
27720 + This program is distributed in the hope it will be useful, but WITHOUT
27721 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
27722 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27725 + You should have received a copy of the GNU General Public License along with
27726 + this program; if not, write to the Free Software Foundation, Inc.,
27727 + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
27729 + The full GNU General Public License is included in this distribution in
27730 + the file called "COPYING".
27732 + Contact Information:
27733 + Linux NICS <linux.nics@intel.com>
27734 + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
27735 + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27737 +*******************************************************************************/
27739 +#include <linux/netdevice.h>
27741 +#include "e1000.h"
27744 + * This is the only thing that needs to be changed to adjust the
27745 + * maximum number of ports that the driver can manage.
27748 +#define E1000_MAX_NIC 32
27750 +#define OPTION_UNSET -1
27751 +#define OPTION_DISABLED 0
27752 +#define OPTION_ENABLED 1
27754 +#define COPYBREAK_DEFAULT 256
27755 +unsigned int copybreak = COPYBREAK_DEFAULT;
27756 +module_param(copybreak, uint, 0644);
27757 +MODULE_PARM_DESC(copybreak,
27758 + "Maximum size of packet that is copied to a new buffer on receive");
27761 + * All parameters are treated the same, as an integer array of values.
27762 + * This macro just reduces the need to repeat the same declaration code
27763 + * over and over (plus this helps to avoid typo bugs).
27766 +#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
27767 +#ifndef module_param_array
27768 +/* Module Parameters are always initialized to -1, so that the driver
27769 + * can tell the difference between no user specified value or the
27770 + * user asking for the default value.
27771 + * The true default values are loaded in when e1000e_check_options is called.
27773 + * This is a GCC extension to ANSI C.
27774 + * See the item "Labeled Elements in Initializers" in the section
27775 + * "Extensions to the C Language Family" of the GCC documentation.
27777 +#define E1000_PARAM(X, desc) \
27778 + static const int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
27779 + static unsigned int num_##X; \
27780 + MODULE_PARM(X, "1-" __MODULE_STRING(E1000_MAX_NIC) "i"); \
27781 + MODULE_PARM_DESC(X, desc);
27783 +#define E1000_PARAM(X, desc) \
27784 + static int __devinitdata X[E1000_MAX_NIC+1] \
27785 + = E1000_PARAM_INIT; \
27786 + static unsigned int num_##X; \
27787 + module_param_array_named(X, X, int, &num_##X, 0); \
27788 + MODULE_PARM_DESC(X, desc);
27793 + * Transmit Interrupt Delay in units of 1.024 microseconds
27794 + * Tx interrupt delay needs to typically be set to something non zero
27796 + * Valid Range: 0-65535
27798 +E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
27799 +#define DEFAULT_TIDV 8
27800 +#define MAX_TXDELAY 0xFFFF
27801 +#define MIN_TXDELAY 0
27804 + * Transmit Absolute Interrupt Delay in units of 1.024 microseconds
27806 + * Valid Range: 0-65535
27808 +E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
27809 +#define DEFAULT_TADV 32
27810 +#define MAX_TXABSDELAY 0xFFFF
27811 +#define MIN_TXABSDELAY 0
27814 + * Receive Interrupt Delay in units of 1.024 microseconds
27815 + * hardware will likely hang if you set this to anything but zero.
27817 + * Valid Range: 0-65535
27819 +E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
27820 +#define DEFAULT_RDTR 0
27821 +#define MAX_RXDELAY 0xFFFF
27822 +#define MIN_RXDELAY 0
27825 + * Receive Absolute Interrupt Delay in units of 1.024 microseconds
27827 + * Valid Range: 0-65535
27829 +E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
27830 +#define DEFAULT_RADV 8
27831 +#define MAX_RXABSDELAY 0xFFFF
27832 +#define MIN_RXABSDELAY 0
27835 + * Interrupt Throttle Rate (interrupts/sec)
27837 + * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
27839 +E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
27840 +#define DEFAULT_ITR 3
27841 +#define MAX_ITR 100000
27842 +#define MIN_ITR 100
27844 +#ifdef CONFIG_E1000E_MSIX
27845 +/* IntMode (Interrupt Mode)
27847 + * Valid Range: 0 - 2
27849 + * Default Value: 2 (MSI-X)
27851 +E1000_PARAM(IntMode, "Interrupt Mode");
27852 +#define MAX_INTMODE 2
27853 +#define MIN_INTMODE 0
27855 +#endif /* CONFIG_E1000E_MSIX */
27857 + * Enable Smart Power Down of the PHY
27859 + * Valid Range: 0, 1
27861 + * Default Value: 0 (disabled)
27863 +E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
27866 + * Enable Kumeran Lock Loss workaround
27868 + * Valid Range: 0, 1
27870 + * Default Value: 1 (enabled)
27872 +E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
27875 + * Enable CRC Stripping
27877 + * Valid Range: 0, 1
27879 + * Default Value: 1 (enabled)
27881 +E1000_PARAM(CrcStripping, "Enable CRC Stripping, disable if your BMC needs " \
27884 +struct e1000_option {
27885 + enum { enable_option, range_option, list_option } type;
27886 + const char *name;
27890 + struct { /* range_option info */
27894 + struct { /* list_option info */
27896 + struct e1000_opt_list { int i; char *str; } *p;
27901 +static int __devinit e1000_validate_option(unsigned int *value,
27902 + const struct e1000_option *opt,
27903 + struct e1000_adapter *adapter)
27905 + if (*value == OPTION_UNSET) {
27906 + *value = opt->def;
27910 + switch (opt->type) {
27911 + case enable_option:
27912 + switch (*value) {
27913 + case OPTION_ENABLED:
27914 + e_info("%s Enabled\n", opt->name);
27916 + case OPTION_DISABLED:
27917 + e_info("%s Disabled\n", opt->name);
27921 + case range_option:
27922 + if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
27923 + e_info("%s set to %i\n", opt->name, *value);
27927 + case list_option: {
27929 + struct e1000_opt_list *ent;
27931 + for (i = 0; i < opt->arg.l.nr; i++) {
27932 + ent = &opt->arg.l.p[i];
27933 + if (*value == ent->i) {
27934 + if (ent->str[0] != '\0')
27935 + e_info("%s\n", ent->str);
27945 + e_info("Invalid %s value specified (%i) %s\n", opt->name, *value,
27947 + *value = opt->def;
27952 + * e1000e_check_options - Range Checking for Command Line Parameters
27953 + * @adapter: board private structure
27955 + * This routine checks all command line parameters for valid user
27956 + * input. If an invalid value is given, or if no user specified
27957 + * value exists, a default value is used. The final value is stored
27958 + * in a variable in the adapter structure.
27960 +void __devinit e1000e_check_options(struct e1000_adapter *adapter)
27962 + struct e1000_hw *hw = &adapter->hw;
27963 + int bd = adapter->bd_number;
27965 + if (bd >= E1000_MAX_NIC) {
27966 + e_notice("Warning: no configuration for board #%i\n", bd);
27967 + e_notice("Using defaults for all values\n");
27970 + { /* Transmit Interrupt Delay */
27971 + const struct e1000_option opt = {
27972 + .type = range_option,
27973 + .name = "Transmit Interrupt Delay",
27974 + .err = "using default of "
27975 + __MODULE_STRING(DEFAULT_TIDV),
27976 + .def = DEFAULT_TIDV,
27977 + .arg = { .r = { .min = MIN_TXDELAY,
27978 + .max = MAX_TXDELAY } }
27981 + if (num_TxIntDelay > bd) {
27982 + adapter->tx_int_delay = TxIntDelay[bd];
27983 + e1000_validate_option(&adapter->tx_int_delay, &opt,
27986 + adapter->tx_int_delay = opt.def;
27989 + { /* Transmit Absolute Interrupt Delay */
27990 + const struct e1000_option opt = {
27991 + .type = range_option,
27992 + .name = "Transmit Absolute Interrupt Delay",
27993 + .err = "using default of "
27994 + __MODULE_STRING(DEFAULT_TADV),
27995 + .def = DEFAULT_TADV,
27996 + .arg = { .r = { .min = MIN_TXABSDELAY,
27997 + .max = MAX_TXABSDELAY } }
28000 + if (num_TxAbsIntDelay > bd) {
28001 + adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
28002 + e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
28005 + adapter->tx_abs_int_delay = opt.def;
28008 + { /* Receive Interrupt Delay */
28009 + struct e1000_option opt = {
28010 + .type = range_option,
28011 + .name = "Receive Interrupt Delay",
28012 + .err = "using default of "
28013 + __MODULE_STRING(DEFAULT_RDTR),
28014 + .def = DEFAULT_RDTR,
28015 + .arg = { .r = { .min = MIN_RXDELAY,
28016 + .max = MAX_RXDELAY } }
28019 + if (num_RxIntDelay > bd) {
28020 + adapter->rx_int_delay = RxIntDelay[bd];
28021 + e1000_validate_option(&adapter->rx_int_delay, &opt,
28024 + adapter->rx_int_delay = opt.def;
28027 + { /* Receive Absolute Interrupt Delay */
28028 + const struct e1000_option opt = {
28029 + .type = range_option,
28030 + .name = "Receive Absolute Interrupt Delay",
28031 + .err = "using default of "
28032 + __MODULE_STRING(DEFAULT_RADV),
28033 + .def = DEFAULT_RADV,
28034 + .arg = { .r = { .min = MIN_RXABSDELAY,
28035 + .max = MAX_RXABSDELAY } }
28038 + if (num_RxAbsIntDelay > bd) {
28039 + adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
28040 + e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
28043 + adapter->rx_abs_int_delay = opt.def;
28046 + { /* Interrupt Throttling Rate */
28047 + const struct e1000_option opt = {
28048 + .type = range_option,
28049 + .name = "Interrupt Throttling Rate (ints/sec)",
28050 + .err = "using default of "
28051 + __MODULE_STRING(DEFAULT_ITR),
28052 + .def = DEFAULT_ITR,
28053 + .arg = { .r = { .min = MIN_ITR,
28054 + .max = MAX_ITR } }
28057 + if (num_InterruptThrottleRate > bd) {
28058 + adapter->itr = InterruptThrottleRate[bd];
28059 + switch (adapter->itr) {
28061 + e_info("%s turned off\n", opt.name);
28064 + e_info("%s set to dynamic mode\n", opt.name);
28065 + adapter->itr_setting = adapter->itr;
28066 + adapter->itr = 20000;
28069 + e_info("%s set to dynamic conservative mode\n",
28071 + adapter->itr_setting = adapter->itr;
28072 + adapter->itr = 20000;
28076 + * Save the setting, because the dynamic bits
28079 + if (e1000_validate_option(&adapter->itr, &opt,
28081 + (adapter->itr == 3)) {
28083 + * In case of invalid user value,
28084 + * default to conservative mode.
28086 + adapter->itr_setting = adapter->itr;
28087 + adapter->itr = 20000;
28090 + * Clear the lower two bits because
28091 + * they are used as control.
28093 + adapter->itr_setting =
28094 + adapter->itr & ~3;
28099 + adapter->itr_setting = opt.def;
28100 + adapter->itr = 20000;
28103 +#ifdef CONFIG_E1000E_MSIX
28104 + { /* Interrupt Mode */
28105 + struct e1000_option opt = {
28106 + .type = range_option,
28107 + .name = "Interrupt Mode",
28108 + .err = "defaulting to 2 (MSI-X)",
28109 + .def = E1000E_INT_MODE_MSIX,
28110 + .arg = { .r = { .min = MIN_INTMODE,
28111 + .max = MAX_INTMODE } }
28114 + if (num_IntMode > bd) {
28115 + unsigned int int_mode = IntMode[bd];
28116 + e1000_validate_option(&int_mode, &opt, adapter);
28117 + adapter->int_mode = int_mode;
28119 + adapter->int_mode = opt.def;
28122 +#endif /* CONFIG_E1000E_MSIX */
28123 + { /* Smart Power Down */
28124 + const struct e1000_option opt = {
28125 + .type = enable_option,
28126 + .name = "PHY Smart Power Down",
28127 + .err = "defaulting to Disabled",
28128 + .def = OPTION_DISABLED
28131 + if (num_SmartPowerDownEnable > bd) {
28132 + unsigned int spd = SmartPowerDownEnable[bd];
28133 + e1000_validate_option(&spd, &opt, adapter);
28134 + if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN)
28136 + adapter->flags |= FLAG_SMART_POWER_DOWN;
28139 + { /* CRC Stripping */
28140 + const struct e1000_option opt = {
28141 + .type = enable_option,
28142 + .name = "CRC Stripping",
28143 + .err = "defaulting to Enabled",
28144 + .def = OPTION_ENABLED
28147 + if (num_CrcStripping > bd) {
28148 + unsigned int crc_stripping = CrcStripping[bd];
28149 + e1000_validate_option(&crc_stripping, &opt, adapter);
28150 + if (crc_stripping == OPTION_ENABLED)
28151 + adapter->flags2 |= FLAG2_CRC_STRIPPING;
28153 + adapter->flags2 |= FLAG2_CRC_STRIPPING;
28156 + { /* Kumeran Lock Loss Workaround */
28157 + const struct e1000_option opt = {
28158 + .type = enable_option,
28159 + .name = "Kumeran Lock Loss Workaround",
28160 + .err = "defaulting to Enabled",
28161 + .def = OPTION_ENABLED
28164 + if (num_KumeranLockLoss > bd) {
28165 + unsigned int kmrn_lock_loss = KumeranLockLoss[bd];
28166 + e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
28167 + if (hw->mac.type == e1000_ich8lan)
28168 + e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw,
28171 + if (hw->mac.type == e1000_ich8lan)
28172 + e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw,
28177 diff -Nurp linux-2.6.22-0/drivers/net/Kconfig linux-2.6.22-10/drivers/net/Kconfig
28178 --- linux-2.6.22-0/drivers/net/Kconfig 2007-07-09 01:32:17.000000000 +0200
28179 +++ linux-2.6.22-10/drivers/net/Kconfig 2009-08-27 23:57:46.000000000 +0200
28180 @@ -1993,6 +1993,29 @@ config E1000_DISABLE_PACKET_SPLIT
28182 If in doubt, say N.
28185 + tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
28188 + This driver supports the PCI-Express Intel(R) PRO/1000 gigabit
28189 + ethernet family of adapters. For PCI or PCI-X e1000 adapters,
28190 + use the regular e1000 driver For more information on how to
28191 + identify your adapter, go to the Adapter & Driver ID Guide at:
28193 + <http://support.intel.com/support/network/adapter/pro100/21397.htm>
28195 + For general information and support, go to the Intel support
28198 + <http://support.intel.com>
28200 + More specific information on configuring the driver is in
28201 + <file:Documentation/networking/e1000e.txt>.
28203 + To compile this driver as a module, choose M here and read
28204 + <file:Documentation/networking/net-modules.txt>. The module
28205 + will be called e1000e.
28207 source "drivers/net/ixp2000/Kconfig"
28210 diff -Nurp linux-2.6.22-0/drivers/net/Makefile linux-2.6.22-10/drivers/net/Makefile
28211 --- linux-2.6.22-0/drivers/net/Makefile 2007-07-09 01:32:17.000000000 +0200
28212 +++ linux-2.6.22-10/drivers/net/Makefile 2009-08-27 23:57:06.000000000 +0200
28216 obj-$(CONFIG_E1000) += e1000/
28217 +obj-$(CONFIG_E1000E) += e1000e/
28218 obj-$(CONFIG_IBM_EMAC) += ibm_emac/
28219 obj-$(CONFIG_IXGB) += ixgb/
28220 obj-$(CONFIG_CHELSIO_T1) += chelsio/