Setting tag linux-2.6-22-48

[linux-2.6.git] / linux-2.6-016-bnx2x.patch

diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_compat.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_compat.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_compat.h      1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_compat.h   2010-03-10 20:22:55.202896096 -0500
@@ -0,0 +1,570 @@
+#ifndef __BNX2X_COMPAT_H__
+#define __BNX2X_COMPAT_H__
+
+#ifndef __VMKLNX__
+#define VMWARE_ESX_DDK_VERSION         0
+#endif
+
+#if (LINUX_VERSION_CODE < 0x02061e)
+#define skb_record_rx_queue(skb, index)
+#endif
+
+#if (LINUX_VERSION_CODE < 0x020618) && (VMWARE_ESX_DDK_VERSION < 40000)
+#define napi_complete(napi)            netif_rx_complete(dev)
+#define napi_schedule(napi)            netif_rx_schedule(bp->dev)
+#endif
+
+#ifndef BNX2X_MULTI_QUEUE
+#define netif_tx_wake_all_queues       netif_wake_queue
+#define netif_tx_start_all_queues      netif_start_queue
+#endif
+
+#if (LINUX_VERSION_CODE < 0x020618)
+#define skb_copy_from_linear_data_offset(skb, pad, new_skb_data, len) \
+                               memcpy(new_skb_data, skb->data + pad, len)
+#endif
+
+#if (LINUX_VERSION_CODE < 0x020616)
+/* skb_buff accessors */
+#define ip_hdr(skb)                    (skb)->nh.iph
+#define ipv6_hdr(skb)                  (skb)->nh.ipv6h
+#define ip_hdrlen(skb)                 (ip_hdr(skb)->ihl * 4)
+#define tcp_hdr(skb)                   (skb)->h.th
+#define tcp_hdrlen(skb)                        (tcp_hdr(skb)->doff * 4)
+#define udp_hdr(skb)                   (skb)->h.uh
+#define skb_mac_header(skb)            ((skb)->mac.raw)
+#define skb_network_header(skb)                ((skb)->nh.raw)
+#define skb_transport_header(skb)      ((skb)->h.raw)
+#endif
+
+
+#ifndef CHECKSUM_PARTIAL
+#define CHECKSUM_PARTIAL               CHECKSUM_HW
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020600)
+#define might_sleep()
+
+#define num_online_cpus()              1
+
+#define dev_info(dev, format, args...) \
+                               printk(KERN_INFO "bnx2x: " format, ##args)
+
+#define dev_err(dev, format, args...) \
+                               printk(KERN_ERR "bnx2x: " format, ##args)
+
+static inline int dma_mapping_error(dma_addr_t mapping)
+{
+       return 0;
+}
+
+#define synchronize_irq(X)             synchronize_irq()
+#define flush_scheduled_work()
+#endif
+
+
+#ifndef SET_MODULE_OWNER
+#define SET_MODULE_OWNER(dev)
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020604)
+#define MODULE_VERSION(version)
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020605)
+static inline void pci_dma_sync_single_for_device(struct pci_dev *dev,
+                                                 dma_addr_t map, size_t size,
+                                                 int dir)
+{
+}
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020547)
+#define pci_set_consistent_dma_mask(X, Y)      (0)
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020607)
+#define msleep(x) \
+       do { \
+               current->state = TASK_UNINTERRUPTIBLE; \
+               schedule_timeout((HZ * (x)) / 1000); \
+       } while (0)
+
+#ifndef ADVERTISE_1000XPAUSE
+static inline struct mii_ioctl_data *if_mii(struct ifreq *rq)
+{
+       return (struct mii_ioctl_data *)&rq->ifr_ifru;
+}
+#endif
+
+#define pci_enable_msix(X, Y, Z)       (-1)
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020609)
+#define msleep_interruptible(x) \
+       do{ \
+               current->state = TASK_INTERRUPTIBLE; \
+               schedule_timeout((HZ * (x)) / 1000); \
+       } while (0)
+
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x02060b)
+#define pm_message_t                   u32
+#define pci_power_t                    u32
+#define PCI_D0                         0
+#define PCI_D3hot                      3
+#define pci_choose_state(pdev, state)  state
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x02060e)
+#define touch_softlockup_watchdog()
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020612)
+static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev,
+                                              unsigned int length)
+{
+       struct sk_buff *skb = dev_alloc_skb(length);
+
+       if (skb)
+               skb->dev = dev;
+       return skb;
+}
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020614)
+#define PCI_VDEVICE(vendor, device)             \
+        PCI_VENDOR_ID_##vendor, (device),       \
+        PCI_ANY_ID, PCI_ANY_ID, 0, 0
+#endif
+
+#if (LINUX_VERSION_CODE < 0x020615)
+#define vlan_group_set_device(vg, vlan_id, dev)        vg->vlan_devices[vlan_id] = dev
+#endif
+
+
+#ifndef IRQ_RETVAL
+typedef void                           irqreturn_t;
+#define IRQ_HANDLED
+#define IRQ_NONE
+#endif
+
+
+#ifndef IRQF_SHARED
+#define IRQF_SHARED                    SA_SHIRQ
+#endif
+
+
+#ifndef NETIF_F_GSO
+static inline void netif_tx_lock(struct net_device *dev)
+{
+       spin_lock(&dev->xmit_lock);
+       dev->xmit_lock_owner = smp_processor_id();
+}
+
+static inline void netif_tx_unlock(struct net_device *dev)
+{
+       dev->xmit_lock_owner = -1;
+       spin_unlock(&dev->xmit_lock);
+}
+#endif
+
+
+#ifndef skb_shinfo
+#define skb_shinfo(SKB)        ((struct skb_shared_info *)(skb_end_pointer(SKB)))
+#endif
+
+
+#ifdef NETIF_F_TSO
+#ifndef NETIF_F_GSO
+
+static inline int skb_is_gso(const struct sk_buff *skb)
+{
+       return skb_shinfo(skb)->tso_size;
+}
+
+#define gso_size                       tso_size
+
+#endif /* NETIF_F_GSO */
+
+#ifndef NETIF_F_GSO_SOFTWARE
+#define NETIF_F_GSO_SOFTWARE           (NETIF_F_TSO)
+#endif
+
+#endif /* NETIF_F_TSO */
+
+#ifndef NETIF_F_TSO_ECN
+#define NETIF_F_TSO_ECN                        0
+#endif
+
+
+#if !defined(mmiowb)
+#define mmiowb()
+#endif
+
+#if !defined(__iomem)
+#define __iomem
+#endif
+
+#ifndef noinline
+#define noinline
+#endif
+
+#if !defined(INIT_WORK)
+#define INIT_WORK INIT_TQUEUE
+#define schedule_work                  schedule_task
+#define work_struct                    tq_struct
+#endif
+
+#if !defined(HAVE_NETDEV_PRIV) && (LINUX_VERSION_CODE != 0x020603) && (LINUX_VERSION_CODE != 0x020604) && (LINUX_VERSION_CODE != 0x020605)
+#define netdev_priv(dev)               (dev)->priv
+#endif
+
+/* Missing defines */
+#ifndef SPEED_2500
+#define SPEED_2500                     2500
+#endif
+
+#ifndef SUPPORTED_Pause
+#define SUPPORTED_Pause                        (1 << 13)
+#endif
+#ifndef SUPPORTED_Asym_Pause
+#define SUPPORTED_Asym_Pause           (1 << 14)
+#endif
+
+#ifndef ADVERTISED_Pause
+#define ADVERTISED_Pause               (1 << 13)
+#endif
+
+#ifndef ADVERTISED_Asym_Pause
+#define ADVERTISED_Asym_Pause          (1 << 14)
+#endif
+
+#ifndef NETDEV_TX_BUSY
+#define NETDEV_TX_BUSY                 1 /* driver tx path was busy */
+#endif
+
+#ifndef NETDEV_TX_OK
+#define NETDEV_TX_OK                   0 /* driver took care of packet */
+#endif
+
+#ifndef DMA_BIT_MASK
+#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
+#endif
+
+#ifndef PCI_CAP_ID_EXP
+#define PCI_CAP_ID_EXP                 0x10
+#endif
+
+#ifndef PCI_EXP_DEVCTL
+#define PCI_EXP_DEVCTL                 8       /* Device Control */
+#endif
+
+#ifndef PCI_EXP_DEVCTL_PAYLOAD
+#define PCI_EXP_DEVCTL_PAYLOAD         0x00e0  /* Max_Payload_Size */
+#endif
+
+#ifndef PCI_EXP_DEVCTL_READRQ
+#define PCI_EXP_DEVCTL_READRQ          0x7000  /* Max_Read_Request_Size */
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020618)
+
+#ifndef NETIF_F_HW_CSUM
+#define NETIF_F_HW_CSUM                        8
+#endif
+
+static inline int bnx2x_set_tx_hw_csum(struct net_device *dev, u32 data)
+{
+       if (data)
+               dev->features |= NETIF_F_HW_CSUM;
+       else
+               dev->features &= ~NETIF_F_HW_CSUM;
+       return 0;
+}
+#endif
+
+
+/* If mutex is not available, use semaphore */
+#ifndef __LINUX_MUTEX_H
+#define mutex                          semaphore
+#define mutex_lock(x)                  down(x)
+#define mutex_unlock(x)                        up(x)
+#define mutex_init(x)                  sema_init(x,1)
+#endif
+
+
+#ifndef KERN_CONT
+#define KERN_CONT                      ""
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x020619)
+#define le16_add_cpu(var, val) *var = cpu_to_le16(le16_to_cpup(var) + val)
+#define le32_add_cpu(var, val) *var = cpu_to_le32(le32_to_cpup(var) + val)
+#endif
+
+
+#if (LINUX_VERSION_CODE < 0x02061b) || defined(BNX2X_DRIVER_DISK) || defined(__VMKLNX__)
+
+/*
+ * This is the CRC-32C table
+ * Generated with:
+ * width = 32 bits
+ * poly = 0x1EDC6F41
+ * reflect input bytes = true
+ * reflect output bytes = true
+ */
+
+static u32 crc32c_table[256] = {
+       0x00000000L, 0xF26B8303L, 0xE13B70F7L, 0x1350F3F4L,
+       0xC79A971FL, 0x35F1141CL, 0x26A1E7E8L, 0xD4CA64EBL,
+       0x8AD958CFL, 0x78B2DBCCL, 0x6BE22838L, 0x9989AB3BL,
+       0x4D43CFD0L, 0xBF284CD3L, 0xAC78BF27L, 0x5E133C24L,
+       0x105EC76FL, 0xE235446CL, 0xF165B798L, 0x030E349BL,
+       0xD7C45070L, 0x25AFD373L, 0x36FF2087L, 0xC494A384L,
+       0x9A879FA0L, 0x68EC1CA3L, 0x7BBCEF57L, 0x89D76C54L,
+       0x5D1D08BFL, 0xAF768BBCL, 0xBC267848L, 0x4E4DFB4BL,
+       0x20BD8EDEL, 0xD2D60DDDL, 0xC186FE29L, 0x33ED7D2AL,
+       0xE72719C1L, 0x154C9AC2L, 0x061C6936L, 0xF477EA35L,
+       0xAA64D611L, 0x580F5512L, 0x4B5FA6E6L, 0xB93425E5L,
+       0x6DFE410EL, 0x9F95C20DL, 0x8CC531F9L, 0x7EAEB2FAL,
+       0x30E349B1L, 0xC288CAB2L, 0xD1D83946L, 0x23B3BA45L,
+       0xF779DEAEL, 0x05125DADL, 0x1642AE59L, 0xE4292D5AL,
+       0xBA3A117EL, 0x4851927DL, 0x5B016189L, 0xA96AE28AL,
+       0x7DA08661L, 0x8FCB0562L, 0x9C9BF696L, 0x6EF07595L,
+       0x417B1DBCL, 0xB3109EBFL, 0xA0406D4BL, 0x522BEE48L,
+       0x86E18AA3L, 0x748A09A0L, 0x67DAFA54L, 0x95B17957L,
+       0xCBA24573L, 0x39C9C670L, 0x2A993584L, 0xD8F2B687L,
+       0x0C38D26CL, 0xFE53516FL, 0xED03A29BL, 0x1F682198L,
+       0x5125DAD3L, 0xA34E59D0L, 0xB01EAA24L, 0x42752927L,
+       0x96BF4DCCL, 0x64D4CECFL, 0x77843D3BL, 0x85EFBE38L,
+       0xDBFC821CL, 0x2997011FL, 0x3AC7F2EBL, 0xC8AC71E8L,
+       0x1C661503L, 0xEE0D9600L, 0xFD5D65F4L, 0x0F36E6F7L,
+       0x61C69362L, 0x93AD1061L, 0x80FDE395L, 0x72966096L,
+       0xA65C047DL, 0x5437877EL, 0x4767748AL, 0xB50CF789L,
+       0xEB1FCBADL, 0x197448AEL, 0x0A24BB5AL, 0xF84F3859L,
+       0x2C855CB2L, 0xDEEEDFB1L, 0xCDBE2C45L, 0x3FD5AF46L,
+       0x7198540DL, 0x83F3D70EL, 0x90A324FAL, 0x62C8A7F9L,
+       0xB602C312L, 0x44694011L, 0x5739B3E5L, 0xA55230E6L,
+       0xFB410CC2L, 0x092A8FC1L, 0x1A7A7C35L, 0xE811FF36L,
+       0x3CDB9BDDL, 0xCEB018DEL, 0xDDE0EB2AL, 0x2F8B6829L,
+       0x82F63B78L, 0x709DB87BL, 0x63CD4B8FL, 0x91A6C88CL,
+       0x456CAC67L, 0xB7072F64L, 0xA457DC90L, 0x563C5F93L,
+       0x082F63B7L, 0xFA44E0B4L, 0xE9141340L, 0x1B7F9043L,
+       0xCFB5F4A8L, 0x3DDE77ABL, 0x2E8E845FL, 0xDCE5075CL,
+       0x92A8FC17L, 0x60C37F14L, 0x73938CE0L, 0x81F80FE3L,
+       0x55326B08L, 0xA759E80BL, 0xB4091BFFL, 0x466298FCL,
+       0x1871A4D8L, 0xEA1A27DBL, 0xF94AD42FL, 0x0B21572CL,
+       0xDFEB33C7L, 0x2D80B0C4L, 0x3ED04330L, 0xCCBBC033L,
+       0xA24BB5A6L, 0x502036A5L, 0x4370C551L, 0xB11B4652L,
+       0x65D122B9L, 0x97BAA1BAL, 0x84EA524EL, 0x7681D14DL,
+       0x2892ED69L, 0xDAF96E6AL, 0xC9A99D9EL, 0x3BC21E9DL,
+       0xEF087A76L, 0x1D63F975L, 0x0E330A81L, 0xFC588982L,
+       0xB21572C9L, 0x407EF1CAL, 0x532E023EL, 0xA145813DL,
+       0x758FE5D6L, 0x87E466D5L, 0x94B49521L, 0x66DF1622L,
+       0x38CC2A06L, 0xCAA7A905L, 0xD9F75AF1L, 0x2B9CD9F2L,
+       0xFF56BD19L, 0x0D3D3E1AL, 0x1E6DCDEEL, 0xEC064EEDL,
+       0xC38D26C4L, 0x31E6A5C7L, 0x22B65633L, 0xD0DDD530L,
+       0x0417B1DBL, 0xF67C32D8L, 0xE52CC12CL, 0x1747422FL,
+       0x49547E0BL, 0xBB3FFD08L, 0xA86F0EFCL, 0x5A048DFFL,
+       0x8ECEE914L, 0x7CA56A17L, 0x6FF599E3L, 0x9D9E1AE0L,
+       0xD3D3E1ABL, 0x21B862A8L, 0x32E8915CL, 0xC083125FL,
+       0x144976B4L, 0xE622F5B7L, 0xF5720643L, 0x07198540L,
+       0x590AB964L, 0xAB613A67L, 0xB831C993L, 0x4A5A4A90L,
+       0x9E902E7BL, 0x6CFBAD78L, 0x7FAB5E8CL, 0x8DC0DD8FL,
+       0xE330A81AL, 0x115B2B19L, 0x020BD8EDL, 0xF0605BEEL,
+       0x24AA3F05L, 0xD6C1BC06L, 0xC5914FF2L, 0x37FACCF1L,
+       0x69E9F0D5L, 0x9B8273D6L, 0x88D28022L, 0x7AB90321L,
+       0xAE7367CAL, 0x5C18E4C9L, 0x4F48173DL, 0xBD23943EL,
+       0xF36E6F75L, 0x0105EC76L, 0x12551F82L, 0xE03E9C81L,
+       0x34F4F86AL, 0xC69F7B69L, 0xD5CF889DL, 0x27A40B9EL,
+       0x79B737BAL, 0x8BDCB4B9L, 0x988C474DL, 0x6AE7C44EL,
+       0xBE2DA0A5L, 0x4C4623A6L, 0x5F16D052L, 0xAD7D5351L
+};
+
+/*
+ * Steps through buffer one byte at at time, calculates reflected
+ * crc using table.
+ */
+
+static inline u32 /*__attribute_pure__*/
+crc32c_le(u32 seed, unsigned char const *data, size_t length)
+{
+       __le32 crc = __cpu_to_le32(seed);
+
+       while (length--)
+               crc = crc32c_table[(crc ^ *data++) & 0xFFL] ^ (crc >> 8);
+
+       return __le32_to_cpu(crc);
+}
+#endif
+
+/* Taken from drivers/net/mdio.c */
+#if (LINUX_VERSION_CODE < 0x02061f)
+#include <linux/mii.h>
+
+/* MDIO Manageable Devices (MMDs). */
+#define MDIO_MMD_AN            7       /* Auto-Negotiation */
+
+/* Generic MDIO registers. */
+#define MDIO_AN_ADVERTISE      16      /* AN advertising (base page) */
+#define MDIO_AN_LPA            19      /* AN LP abilities (base page) */
+
+/* Device present registers. */
+#define MDIO_DEVS_PRESENT(devad)       (1 << (devad))
+#define MDIO_DEVS_AN                   MDIO_DEVS_PRESENT(MDIO_MMD_AN)
+
+/**
+ * struct mdio_if_info - Ethernet controller MDIO interface
+ * @prtad: PRTAD of the PHY (%MDIO_PRTAD_NONE if not present/unknown)
+ * @mmds: Mask of MMDs expected to be present in the PHY.  This must be
+ *     non-zero unless @prtad = %MDIO_PRTAD_NONE.
+ * @mode_support: MDIO modes supported.  If %MDIO_SUPPORTS_C22 is set then
+ *     MII register access will be passed through with @devad =
+ *     %MDIO_DEVAD_NONE.  If %MDIO_EMULATE_C22 is set then access to
+ *     commonly used clause 22 registers will be translated into
+ *     clause 45 registers.
+ * @dev: Net device structure
+ * @mdio_read: Register read function; returns value or negative error code
+ * @mdio_write: Register write function; returns 0 or negative error code
+ */
+struct mdio_if_info {
+       int prtad;
+       u32 __bitwise mmds;
+       unsigned mode_support;
+
+       struct net_device *dev;
+       int (*mdio_read)(struct net_device *dev, int prtad, int devad,
+                        u16 addr);
+       int (*mdio_write)(struct net_device *dev, int prtad, int devad,
+                         u16 addr, u16 val);
+};
+
+#define MDIO_PRTAD_NONE                        (-1)
+#define MDIO_DEVAD_NONE                        (-1)
+#define MDIO_EMULATE_C22               4
+
+/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
+
+#define MDIO_PHY_ID_C45                        0x8000
+#define MDIO_PHY_ID_PRTAD              0x03e0
+#define MDIO_PHY_ID_DEVAD              0x001f
+#define MDIO_PHY_ID_C45_MASK                                           \
+       (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
+
+static inline int mdio_phy_id_is_c45(int phy_id)
+{
+       return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK);
+}
+
+static inline __u16 mdio_phy_id_prtad(int phy_id)
+{
+       return (phy_id & MDIO_PHY_ID_PRTAD) >> 5;
+}
+
+static inline __u16 mdio_phy_id_devad(int phy_id)
+{
+       return phy_id & MDIO_PHY_ID_DEVAD;
+}
+
+#define MDIO_SUPPORTS_C22              1
+#define MDIO_SUPPORTS_C45              2
+
+/**
+ * mdio_mii_ioctl - MII ioctl interface for MDIO (clause 22 or 45) PHYs
+ * @mdio: MDIO interface
+ * @mii_data: MII ioctl data structure
+ * @cmd: MII ioctl command
+ *
+ * Returns 0 on success, negative on error.
+ */
+static inline int mdio_mii_ioctl(const struct mdio_if_info *mdio,
+                                struct mii_ioctl_data *mii_data, int cmd)
+{
+       int prtad, devad;
+       u16 addr = mii_data->reg_num;
+
+       /* Validate/convert cmd to one of SIOC{G,S}MIIREG */
+       switch (cmd) {
+       case SIOCGMIIPHY:
+               if (mdio->prtad == MDIO_PRTAD_NONE)
+                       return -EOPNOTSUPP;
+               mii_data->phy_id = mdio->prtad;
+               cmd = SIOCGMIIREG;
+               break;
+       case SIOCGMIIREG:
+               break;
+       case SIOCSMIIREG:
+               if (!capable(CAP_NET_ADMIN))
+                       return -EPERM;
+               break;
+       default:
+               return -EOPNOTSUPP;
+       }
+
+       /* Validate/convert phy_id */
+       if ((mdio->mode_support & MDIO_SUPPORTS_C45) &&
+           mdio_phy_id_is_c45(mii_data->phy_id)) {
+               prtad = mdio_phy_id_prtad(mii_data->phy_id);
+               devad = mdio_phy_id_devad(mii_data->phy_id);
+       } else if ((mdio->mode_support & MDIO_SUPPORTS_C22) &&
+                  mii_data->phy_id < 0x20) {
+               prtad = mii_data->phy_id;
+               devad = MDIO_DEVAD_NONE;
+               addr &= 0x1f;
+       } else if ((mdio->mode_support & MDIO_EMULATE_C22) &&
+                  mdio->prtad != MDIO_PRTAD_NONE &&
+                  mii_data->phy_id == mdio->prtad) {
+               /* Remap commonly-used MII registers. */
+               prtad = mdio->prtad;
+               switch (addr) {
+               case MII_BMCR:
+               case MII_BMSR:
+               case MII_PHYSID1:
+               case MII_PHYSID2:
+                       devad = __ffs(mdio->mmds);
+                       break;
+               case MII_ADVERTISE:
+               case MII_LPA:
+                       if (!(mdio->mmds & MDIO_DEVS_AN))
+                               return -EINVAL;
+                       devad = MDIO_MMD_AN;
+                       if (addr == MII_ADVERTISE)
+                               addr = MDIO_AN_ADVERTISE;
+                       else
+                               addr = MDIO_AN_LPA;
+                       break;
+               default:
+                       return -EINVAL;
+               }
+       } else {
+               return -EINVAL;
+       }
+
+       if (cmd == SIOCGMIIREG) {
+               int rc = mdio->mdio_read(mdio->dev, prtad, devad, addr);
+               if (rc < 0)
+                       return rc;
+               mii_data->val_out = rc;
+               return 0;
+       } else {
+               return mdio->mdio_write(mdio->dev, prtad, devad, addr,
+                                       mii_data->val_in);
+       }
+}
+#endif
+
+#endif /* __BNX2X_COMPAT_H__ */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_dump.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_dump.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_dump.h        1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_dump.h     2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,542 @@
+/* bnx2x_dump.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2009 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
+ *
+ * Written by: Yitchak Gertner
+ */
+
+
+/* This struct holds a signature to ensure the dump returned from the driver
+ * match the meta data file inserted to grc_dump.tcl
+ * The signature is time stamp, diag version and grc_dump version
+ */
+
+#ifndef BNX2X_DUMP_H
+#define BNX2X_DUMP_H
+
+
+struct dump_sign {
+       u32 time_stamp;
+       u32 diag_ver;
+       u32 grc_dump_ver;
+};
+
+#define TSTORM_WAITP_ADDR              0x1b8a80
+#define CSTORM_WAITP_ADDR              0x238a80
+#define XSTORM_WAITP_ADDR              0x2b8a80
+#define USTORM_WAITP_ADDR              0x338a80
+#define TSTORM_CAM_MODE                        0x1b1440
+
+#define RI_E1                          0x1
+#define RI_E1H                         0x2
+#define RI_ONLINE                      0x100
+
+#define RI_E1_OFFLINE                  (RI_E1)
+#define RI_E1_ONLINE                   (RI_E1 | RI_ONLINE)
+#define RI_E1H_OFFLINE                 (RI_E1H)
+#define RI_E1H_ONLINE                  (RI_E1H | RI_ONLINE)
+#define RI_ALL_OFFLINE                 (RI_E1 | RI_E1H)
+#define RI_ALL_ONLINE                  (RI_E1 | RI_E1H | RI_ONLINE)
+
+#define MAX_TIMER_PENDING              200
+#define TIMER_SCAN_DONT_CARE           0xFF
+
+
+struct dump_hdr {
+       u32              hdr_size;      /* in dwords, excluding this field */
+       struct dump_sign dump_sign;
+       u32              xstorm_waitp;
+       u32              tstorm_waitp;
+       u32              ustorm_waitp;
+       u32              cstorm_waitp;
+       u16              info;
+       u8               idle_chk;
+       u8               reserved;
+};
+
+struct reg_addr {
+       u32 addr;
+       u32 size;
+       u16 info;
+};
+
+struct wreg_addr {
+       u32 addr;
+       u32 size;
+       u32 read_regs_count;
+       const u32 *read_regs;
+       u16 info;
+};
+
+
+#define REGS_COUNT                     558
+static const struct reg_addr reg_addrs[REGS_COUNT] = {
+       { 0x2000, 341, RI_ALL_ONLINE }, { 0x2800, 103, RI_ALL_ONLINE },
+       { 0x3000, 287, RI_ALL_ONLINE }, { 0x3800, 331, RI_ALL_ONLINE },
+       { 0x8800, 6, RI_E1_ONLINE }, { 0xa000, 223, RI_ALL_ONLINE },
+       { 0xa388, 1, RI_ALL_ONLINE }, { 0xa398, 1, RI_ALL_ONLINE },
+       { 0xa39c, 7, RI_E1H_ONLINE }, { 0xa3c0, 3, RI_E1H_ONLINE },
+       { 0xa3d0, 1, RI_E1H_ONLINE }, { 0xa3d8, 1, RI_E1H_ONLINE },
+       { 0xa3e0, 1, RI_E1H_ONLINE }, { 0xa3e8, 1, RI_E1H_ONLINE },
+       { 0xa3f0, 1, RI_E1H_ONLINE }, { 0xa3f8, 1, RI_E1H_ONLINE },
+       { 0xa400, 69, RI_ALL_ONLINE }, { 0xa518, 1, RI_ALL_ONLINE },
+       { 0xa520, 1, RI_ALL_ONLINE }, { 0xa528, 1, RI_ALL_ONLINE },
+       { 0xa530, 1, RI_ALL_ONLINE }, { 0xa538, 1, RI_ALL_ONLINE },
+       { 0xa540, 1, RI_ALL_ONLINE }, { 0xa548, 1, RI_ALL_ONLINE },
+       { 0xa550, 1, RI_ALL_ONLINE }, { 0xa558, 1, RI_ALL_ONLINE },
+       { 0xa560, 1, RI_ALL_ONLINE }, { 0xa568, 1, RI_ALL_ONLINE },
+       { 0xa570, 1, RI_ALL_ONLINE }, { 0xa580, 1, RI_ALL_ONLINE },
+       { 0xa590, 1, RI_ALL_ONLINE }, { 0xa5a0, 1, RI_ALL_ONLINE },
+       { 0xa5c0, 1, RI_ALL_ONLINE }, { 0xa5e0, 1, RI_E1H_ONLINE },
+       { 0xa5e8, 1, RI_E1H_ONLINE }, { 0xa5f0, 1, RI_E1H_ONLINE },
+       { 0xa5f8, 10, RI_E1H_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE },
+       { 0x103bc, 1, RI_ALL_ONLINE }, { 0x103cc, 1, RI_ALL_ONLINE },
+       { 0x103dc, 1, RI_ALL_ONLINE }, { 0x10400, 57, RI_ALL_ONLINE },
+       { 0x104e8, 2, RI_ALL_ONLINE }, { 0x104f4, 2, RI_ALL_ONLINE },
+       { 0x10500, 146, RI_ALL_ONLINE }, { 0x10750, 2, RI_ALL_ONLINE },
+       { 0x10760, 2, RI_ALL_ONLINE }, { 0x10770, 2, RI_ALL_ONLINE },
+       { 0x10780, 2, RI_ALL_ONLINE }, { 0x10790, 2, RI_ALL_ONLINE },
+       { 0x107a0, 2, RI_ALL_ONLINE }, { 0x107b0, 2, RI_ALL_ONLINE },
+       { 0x107c0, 2, RI_ALL_ONLINE }, { 0x107d0, 2, RI_ALL_ONLINE },
+       { 0x107e0, 2, RI_ALL_ONLINE }, { 0x10880, 2, RI_ALL_ONLINE },
+       { 0x10900, 2, RI_ALL_ONLINE }, { 0x12000, 1, RI_ALL_ONLINE },
+       { 0x14000, 1, RI_ALL_ONLINE }, { 0x16000, 26, RI_E1H_ONLINE },
+       { 0x16070, 18, RI_E1H_ONLINE }, { 0x160c0, 27, RI_E1H_ONLINE },
+       { 0x16140, 1, RI_E1H_ONLINE }, { 0x16160, 1, RI_E1H_ONLINE },
+       { 0x16180, 2, RI_E1H_ONLINE }, { 0x161c0, 2, RI_E1H_ONLINE },
+       { 0x16204, 5, RI_E1H_ONLINE }, { 0x18000, 1, RI_E1H_ONLINE },
+       { 0x18008, 1, RI_E1H_ONLINE }, { 0x20000, 24, RI_ALL_ONLINE },
+       { 0x20060, 8, RI_ALL_ONLINE }, { 0x20080, 138, RI_ALL_ONLINE },
+       { 0x202b4, 1, RI_ALL_ONLINE }, { 0x202c4, 1, RI_ALL_ONLINE },
+       { 0x20400, 2, RI_ALL_ONLINE }, { 0x2040c, 8, RI_ALL_ONLINE },
+       { 0x2042c, 18, RI_E1H_ONLINE }, { 0x20480, 1, RI_ALL_ONLINE },
+       { 0x20500, 1, RI_ALL_ONLINE }, { 0x20600, 1, RI_ALL_ONLINE },
+       { 0x28000, 1, RI_ALL_ONLINE }, { 0x28004, 8191, RI_ALL_OFFLINE },
+       { 0x30000, 1, RI_ALL_ONLINE }, { 0x30004, 16383, RI_ALL_OFFLINE },
+       { 0x40000, 98, RI_ALL_ONLINE }, { 0x40194, 1, RI_ALL_ONLINE },
+       { 0x401a4, 1, RI_ALL_ONLINE }, { 0x401a8, 11, RI_E1H_ONLINE },
+       { 0x40200, 4, RI_ALL_ONLINE }, { 0x40400, 43, RI_ALL_ONLINE },
+       { 0x404b8, 1, RI_ALL_ONLINE }, { 0x404c8, 1, RI_ALL_ONLINE },
+       { 0x404cc, 3, RI_E1H_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE },
+       { 0x40510, 2, RI_ALL_ONLINE }, { 0x40520, 2, RI_ALL_ONLINE },
+       { 0x40530, 2, RI_ALL_ONLINE }, { 0x40540, 2, RI_ALL_ONLINE },
+       { 0x42000, 164, RI_ALL_ONLINE }, { 0x4229c, 1, RI_ALL_ONLINE },
+       { 0x422ac, 1, RI_ALL_ONLINE }, { 0x422bc, 1, RI_ALL_ONLINE },
+       { 0x422d4, 5, RI_E1H_ONLINE }, { 0x42400, 49, RI_ALL_ONLINE },
+       { 0x424c8, 38, RI_ALL_ONLINE }, { 0x42568, 2, RI_ALL_ONLINE },
+       { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 20, RI_ALL_ONLINE },
+       { 0x50050, 8, RI_ALL_ONLINE }, { 0x50070, 88, RI_ALL_ONLINE },
+       { 0x501dc, 1, RI_ALL_ONLINE }, { 0x501ec, 1, RI_ALL_ONLINE },
+       { 0x501f0, 4, RI_E1H_ONLINE }, { 0x50200, 2, RI_ALL_ONLINE },
+       { 0x5020c, 7, RI_ALL_ONLINE }, { 0x50228, 6, RI_E1H_ONLINE },
+       { 0x50240, 1, RI_ALL_ONLINE }, { 0x50280, 1, RI_ALL_ONLINE },
+       { 0x52000, 1, RI_ALL_ONLINE }, { 0x54000, 1, RI_ALL_ONLINE },
+       { 0x54004, 3327, RI_ALL_OFFLINE }, { 0x58000, 1, RI_ALL_ONLINE },
+       { 0x58004, 8191, RI_ALL_OFFLINE }, { 0x60000, 71, RI_ALL_ONLINE },
+       { 0x60128, 1, RI_ALL_ONLINE }, { 0x60138, 1, RI_ALL_ONLINE },
+       { 0x6013c, 24, RI_E1H_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE },
+       { 0x61000, 1, RI_ALL_ONLINE }, { 0x61004, 511, RI_ALL_OFFLINE },
+       { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 21496, RI_ALL_OFFLINE },
+       { 0x85000, 3, RI_ALL_ONLINE }, { 0x8500c, 4, RI_ALL_OFFLINE },
+       { 0x8501c, 7, RI_ALL_ONLINE }, { 0x85038, 4, RI_ALL_OFFLINE },
+       { 0x85048, 1, RI_ALL_ONLINE }, { 0x8504c, 109, RI_ALL_OFFLINE },
+       { 0x85200, 32, RI_ALL_ONLINE }, { 0x85280, 11104, RI_ALL_OFFLINE },
+       { 0xa0000, 16384, RI_ALL_ONLINE }, { 0xb0000, 16384, RI_E1H_ONLINE },
+       { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc1028, 1, RI_ALL_ONLINE },
+       { 0xc1038, 1, RI_ALL_ONLINE }, { 0xc1800, 2, RI_ALL_ONLINE },
+       { 0xc2000, 164, RI_ALL_ONLINE }, { 0xc229c, 1, RI_ALL_ONLINE },
+       { 0xc22ac, 1, RI_ALL_ONLINE }, { 0xc22bc, 1, RI_ALL_ONLINE },
+       { 0xc2400, 49, RI_ALL_ONLINE }, { 0xc24c8, 38, RI_ALL_ONLINE },
+       { 0xc2568, 2, RI_ALL_ONLINE }, { 0xc2600, 1, RI_ALL_ONLINE },
+       { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42a0, 1, RI_ALL_ONLINE },
+       { 0xc42b0, 1, RI_ALL_ONLINE }, { 0xc42c0, 1, RI_ALL_ONLINE },
+       { 0xc42e0, 7, RI_E1H_ONLINE }, { 0xc4400, 51, RI_ALL_ONLINE },
+       { 0xc44d0, 38, RI_ALL_ONLINE }, { 0xc4570, 2, RI_ALL_ONLINE },
+       { 0xc4600, 1, RI_ALL_ONLINE }, { 0xd0000, 19, RI_ALL_ONLINE },
+       { 0xd004c, 8, RI_ALL_ONLINE }, { 0xd006c, 91, RI_ALL_ONLINE },
+       { 0xd01e4, 1, RI_ALL_ONLINE }, { 0xd01f4, 1, RI_ALL_ONLINE },
+       { 0xd0200, 2, RI_ALL_ONLINE }, { 0xd020c, 7, RI_ALL_ONLINE },
+       { 0xd0228, 18, RI_E1H_ONLINE }, { 0xd0280, 1, RI_ALL_ONLINE },
+       { 0xd0300, 1, RI_ALL_ONLINE }, { 0xd0400, 1, RI_ALL_ONLINE },
+       { 0xd4000, 1, RI_ALL_ONLINE }, { 0xd4004, 2559, RI_ALL_OFFLINE },
+       { 0xd8000, 1, RI_ALL_ONLINE }, { 0xd8004, 8191, RI_ALL_OFFLINE },
+       { 0xe0000, 21, RI_ALL_ONLINE }, { 0xe0054, 8, RI_ALL_ONLINE },
+       { 0xe0074, 85, RI_ALL_ONLINE }, { 0xe01d4, 1, RI_ALL_ONLINE },
+       { 0xe01e4, 1, RI_ALL_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE },
+       { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1H_ONLINE },
+       { 0xe0280, 1, RI_ALL_ONLINE }, { 0xe0300, 1, RI_ALL_ONLINE },
+       { 0xe1000, 1, RI_ALL_ONLINE }, { 0xe2000, 1, RI_ALL_ONLINE },
+       { 0xe2004, 2047, RI_ALL_OFFLINE }, { 0xf0000, 1, RI_ALL_ONLINE },
+       { 0xf0004, 16383, RI_ALL_OFFLINE }, { 0x101000, 12, RI_ALL_ONLINE },
+       { 0x10103c, 1, RI_ALL_ONLINE }, { 0x10104c, 1, RI_ALL_ONLINE },
+       { 0x101050, 1, RI_E1H_ONLINE }, { 0x101100, 1, RI_ALL_ONLINE },
+       { 0x101800, 8, RI_ALL_ONLINE }, { 0x102000, 18, RI_ALL_ONLINE },
+       { 0x102054, 1, RI_ALL_ONLINE }, { 0x102064, 1, RI_ALL_ONLINE },
+       { 0x102080, 17, RI_ALL_ONLINE }, { 0x1020c8, 8, RI_E1H_ONLINE },
+       { 0x102400, 1, RI_ALL_ONLINE }, { 0x103000, 26, RI_ALL_ONLINE },
+       { 0x103074, 1, RI_ALL_ONLINE }, { 0x103084, 1, RI_ALL_ONLINE },
+       { 0x103094, 1, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1H_ONLINE },
+       { 0x103800, 8, RI_ALL_ONLINE }, { 0x104000, 63, RI_ALL_ONLINE },
+       { 0x104108, 1, RI_ALL_ONLINE }, { 0x104118, 1, RI_ALL_ONLINE },
+       { 0x104200, 17, RI_ALL_ONLINE }, { 0x104400, 64, RI_ALL_ONLINE },
+       { 0x104500, 192, RI_ALL_OFFLINE }, { 0x104800, 64, RI_ALL_ONLINE },
+       { 0x104900, 192, RI_ALL_OFFLINE }, { 0x105000, 7, RI_ALL_ONLINE },
+       { 0x10501c, 1, RI_ALL_OFFLINE }, { 0x105020, 3, RI_ALL_ONLINE },
+       { 0x10502c, 1, RI_ALL_OFFLINE }, { 0x105030, 3, RI_ALL_ONLINE },
+       { 0x10503c, 1, RI_ALL_OFFLINE }, { 0x105040, 3, RI_ALL_ONLINE },
+       { 0x10504c, 1, RI_ALL_OFFLINE }, { 0x105050, 3, RI_ALL_ONLINE },
+       { 0x10505c, 1, RI_ALL_OFFLINE }, { 0x105060, 3, RI_ALL_ONLINE },
+       { 0x10506c, 1, RI_ALL_OFFLINE }, { 0x105070, 3, RI_ALL_ONLINE },
+       { 0x10507c, 1, RI_ALL_OFFLINE }, { 0x105080, 3, RI_ALL_ONLINE },
+       { 0x10508c, 1, RI_ALL_OFFLINE }, { 0x105090, 3, RI_ALL_ONLINE },
+       { 0x10509c, 1, RI_ALL_OFFLINE }, { 0x1050a0, 3, RI_ALL_ONLINE },
+       { 0x1050ac, 1, RI_ALL_OFFLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
+       { 0x1050bc, 1, RI_ALL_OFFLINE }, { 0x1050c0, 3, RI_ALL_ONLINE },
+       { 0x1050cc, 1, RI_ALL_OFFLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
+       { 0x1050dc, 1, RI_ALL_OFFLINE }, { 0x1050e0, 3, RI_ALL_ONLINE },
+       { 0x1050ec, 1, RI_ALL_OFFLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
+       { 0x1050fc, 1, RI_ALL_OFFLINE }, { 0x105100, 3, RI_ALL_ONLINE },
+       { 0x10510c, 1, RI_ALL_OFFLINE }, { 0x105110, 3, RI_ALL_ONLINE },
+       { 0x10511c, 1, RI_ALL_OFFLINE }, { 0x105120, 3, RI_ALL_ONLINE },
+       { 0x10512c, 1, RI_ALL_OFFLINE }, { 0x105130, 3, RI_ALL_ONLINE },
+       { 0x10513c, 1, RI_ALL_OFFLINE }, { 0x105140, 3, RI_ALL_ONLINE },
+       { 0x10514c, 1, RI_ALL_OFFLINE }, { 0x105150, 3, RI_ALL_ONLINE },
+       { 0x10515c, 1, RI_ALL_OFFLINE }, { 0x105160, 3, RI_ALL_ONLINE },
+       { 0x10516c, 1, RI_ALL_OFFLINE }, { 0x105170, 3, RI_ALL_ONLINE },
+       { 0x10517c, 1, RI_ALL_OFFLINE }, { 0x105180, 3, RI_ALL_ONLINE },
+       { 0x10518c, 1, RI_ALL_OFFLINE }, { 0x105190, 3, RI_ALL_ONLINE },
+       { 0x10519c, 1, RI_ALL_OFFLINE }, { 0x1051a0, 3, RI_ALL_ONLINE },
+       { 0x1051ac, 1, RI_ALL_OFFLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
+       { 0x1051bc, 1, RI_ALL_OFFLINE }, { 0x1051c0, 3, RI_ALL_ONLINE },
+       { 0x1051cc, 1, RI_ALL_OFFLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
+       { 0x1051dc, 1, RI_ALL_OFFLINE }, { 0x1051e0, 3, RI_ALL_ONLINE },
+       { 0x1051ec, 1, RI_ALL_OFFLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
+       { 0x1051fc, 1, RI_ALL_OFFLINE }, { 0x105200, 3, RI_ALL_ONLINE },
+       { 0x10520c, 1, RI_ALL_OFFLINE }, { 0x105210, 3, RI_ALL_ONLINE },
+       { 0x10521c, 1, RI_ALL_OFFLINE }, { 0x105220, 3, RI_ALL_ONLINE },
+       { 0x10522c, 1, RI_ALL_OFFLINE }, { 0x105230, 3, RI_ALL_ONLINE },
+       { 0x10523c, 1, RI_ALL_OFFLINE }, { 0x105240, 3, RI_ALL_ONLINE },
+       { 0x10524c, 1, RI_ALL_OFFLINE }, { 0x105250, 3, RI_ALL_ONLINE },
+       { 0x10525c, 1, RI_ALL_OFFLINE }, { 0x105260, 3, RI_ALL_ONLINE },
+       { 0x10526c, 1, RI_ALL_OFFLINE }, { 0x105270, 3, RI_ALL_ONLINE },
+       { 0x10527c, 1, RI_ALL_OFFLINE }, { 0x105280, 3, RI_ALL_ONLINE },
+       { 0x10528c, 1, RI_ALL_OFFLINE }, { 0x105290, 3, RI_ALL_ONLINE },
+       { 0x10529c, 1, RI_ALL_OFFLINE }, { 0x1052a0, 3, RI_ALL_ONLINE },
+       { 0x1052ac, 1, RI_ALL_OFFLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
+       { 0x1052bc, 1, RI_ALL_OFFLINE }, { 0x1052c0, 3, RI_ALL_ONLINE },
+       { 0x1052cc, 1, RI_ALL_OFFLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
+       { 0x1052dc, 1, RI_ALL_OFFLINE }, { 0x1052e0, 3, RI_ALL_ONLINE },
+       { 0x1052ec, 1, RI_ALL_OFFLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
+       { 0x1052fc, 1, RI_ALL_OFFLINE }, { 0x105300, 3, RI_ALL_ONLINE },
+       { 0x10530c, 1, RI_ALL_OFFLINE }, { 0x105310, 3, RI_ALL_ONLINE },
+       { 0x10531c, 1, RI_ALL_OFFLINE }, { 0x105320, 3, RI_ALL_ONLINE },
+       { 0x10532c, 1, RI_ALL_OFFLINE }, { 0x105330, 3, RI_ALL_ONLINE },
+       { 0x10533c, 1, RI_ALL_OFFLINE }, { 0x105340, 3, RI_ALL_ONLINE },
+       { 0x10534c, 1, RI_ALL_OFFLINE }, { 0x105350, 3, RI_ALL_ONLINE },
+       { 0x10535c, 1, RI_ALL_OFFLINE }, { 0x105360, 3, RI_ALL_ONLINE },
+       { 0x10536c, 1, RI_ALL_OFFLINE }, { 0x105370, 3, RI_ALL_ONLINE },
+       { 0x10537c, 1, RI_ALL_OFFLINE }, { 0x105380, 3, RI_ALL_ONLINE },
+       { 0x10538c, 1, RI_ALL_OFFLINE }, { 0x105390, 3, RI_ALL_ONLINE },
+       { 0x10539c, 1, RI_ALL_OFFLINE }, { 0x1053a0, 3, RI_ALL_ONLINE },
+       { 0x1053ac, 1, RI_ALL_OFFLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
+       { 0x1053bc, 1, RI_ALL_OFFLINE }, { 0x1053c0, 3, RI_ALL_ONLINE },
+       { 0x1053cc, 1, RI_ALL_OFFLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
+       { 0x1053dc, 1, RI_ALL_OFFLINE }, { 0x1053e0, 3, RI_ALL_ONLINE },
+       { 0x1053ec, 1, RI_ALL_OFFLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
+       { 0x1053fc, 769, RI_ALL_OFFLINE }, { 0x108000, 33, RI_ALL_ONLINE },
+       { 0x108090, 1, RI_ALL_ONLINE }, { 0x1080a0, 1, RI_ALL_ONLINE },
+       { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_ALL_ONLINE },
+       { 0x108120, 5, RI_ALL_ONLINE }, { 0x108200, 74, RI_ALL_ONLINE },
+       { 0x108400, 74, RI_ALL_ONLINE }, { 0x108800, 152, RI_ALL_ONLINE },
+       { 0x109000, 1, RI_ALL_ONLINE }, { 0x120000, 347, RI_ALL_ONLINE },
+       { 0x120578, 1, RI_ALL_ONLINE }, { 0x120588, 1, RI_ALL_ONLINE },
+       { 0x120598, 1, RI_ALL_ONLINE }, { 0x12059c, 23, RI_E1H_ONLINE },
+       { 0x120614, 1, RI_E1H_ONLINE }, { 0x12061c, 30, RI_E1H_ONLINE },
+       { 0x12080c, 65, RI_ALL_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE },
+       { 0x122000, 2, RI_ALL_ONLINE }, { 0x128000, 2, RI_E1H_ONLINE },
+       { 0x140000, 114, RI_ALL_ONLINE }, { 0x1401d4, 1, RI_ALL_ONLINE },
+       { 0x1401e4, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
+       { 0x144000, 4, RI_ALL_ONLINE }, { 0x148000, 4, RI_ALL_ONLINE },
+       { 0x14c000, 4, RI_ALL_ONLINE }, { 0x150000, 4, RI_ALL_ONLINE },
+       { 0x154000, 4, RI_ALL_ONLINE }, { 0x158000, 4, RI_ALL_ONLINE },
+       { 0x15c000, 7, RI_E1H_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE },
+       { 0x161028, 1, RI_ALL_ONLINE }, { 0x161038, 1, RI_ALL_ONLINE },
+       { 0x161800, 2, RI_ALL_ONLINE }, { 0x164000, 60, RI_ALL_ONLINE },
+       { 0x1640fc, 1, RI_ALL_ONLINE }, { 0x16410c, 1, RI_ALL_ONLINE },
+       { 0x164110, 2, RI_E1H_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE },
+       { 0x164208, 1, RI_ALL_ONLINE }, { 0x164210, 1, RI_ALL_ONLINE },
+       { 0x164218, 1, RI_ALL_ONLINE }, { 0x164220, 1, RI_ALL_ONLINE },
+       { 0x164228, 1, RI_ALL_ONLINE }, { 0x164230, 1, RI_ALL_ONLINE },
+       { 0x164238, 1, RI_ALL_ONLINE }, { 0x164240, 1, RI_ALL_ONLINE },
+       { 0x164248, 1, RI_ALL_ONLINE }, { 0x164250, 1, RI_ALL_ONLINE },
+       { 0x164258, 1, RI_ALL_ONLINE }, { 0x164260, 1, RI_ALL_ONLINE },
+       { 0x164270, 2, RI_ALL_ONLINE }, { 0x164280, 2, RI_ALL_ONLINE },
+       { 0x164800, 2, RI_ALL_ONLINE }, { 0x165000, 2, RI_ALL_ONLINE },
+       { 0x166000, 164, RI_ALL_ONLINE }, { 0x16629c, 1, RI_ALL_ONLINE },
+       { 0x1662ac, 1, RI_ALL_ONLINE }, { 0x1662bc, 1, RI_ALL_ONLINE },
+       { 0x166400, 49, RI_ALL_ONLINE }, { 0x1664c8, 38, RI_ALL_ONLINE },
+       { 0x166568, 2, RI_ALL_ONLINE }, { 0x166800, 1, RI_ALL_ONLINE },
+       { 0x168000, 270, RI_ALL_ONLINE }, { 0x168444, 1, RI_ALL_ONLINE },
+       { 0x168454, 1, RI_ALL_ONLINE }, { 0x168800, 19, RI_ALL_ONLINE },
+       { 0x168900, 1, RI_ALL_ONLINE }, { 0x168a00, 128, RI_ALL_ONLINE },
+       { 0x16a000, 1, RI_ALL_ONLINE }, { 0x16a004, 1535, RI_ALL_OFFLINE },
+       { 0x16c000, 1, RI_ALL_ONLINE }, { 0x16c004, 1535, RI_ALL_OFFLINE },
+       { 0x16e000, 16, RI_E1H_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE },
+       { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 183, RI_E1H_ONLINE },
+       { 0x170000, 93, RI_ALL_ONLINE }, { 0x170180, 1, RI_ALL_ONLINE },
+       { 0x170190, 1, RI_ALL_ONLINE }, { 0x170200, 4, RI_ALL_ONLINE },
+       { 0x170214, 1, RI_ALL_ONLINE }, { 0x178000, 1, RI_ALL_ONLINE },
+       { 0x180000, 61, RI_ALL_ONLINE }, { 0x180100, 1, RI_ALL_ONLINE },
+       { 0x180110, 1, RI_ALL_ONLINE }, { 0x180120, 1, RI_ALL_ONLINE },
+       { 0x180130, 1, RI_ALL_ONLINE }, { 0x18013c, 2, RI_E1H_ONLINE },
+       { 0x180200, 58, RI_ALL_ONLINE }, { 0x180340, 4, RI_ALL_ONLINE },
+       { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_ALL_OFFLINE },
+       { 0x181000, 4, RI_ALL_ONLINE }, { 0x181010, 1020, RI_ALL_OFFLINE },
+       { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 1023, RI_ALL_OFFLINE },
+       { 0x1a1000, 1, RI_ALL_ONLINE }, { 0x1a1004, 4607, RI_ALL_OFFLINE },
+       { 0x1a5800, 2560, RI_E1H_OFFLINE }, { 0x1a8000, 64, RI_ALL_OFFLINE },
+       { 0x1a8100, 1984, RI_E1H_OFFLINE }, { 0x1aa000, 1, RI_E1H_ONLINE },
+       { 0x1aa004, 6655, RI_E1H_OFFLINE }, { 0x1b1800, 128, RI_ALL_OFFLINE },
+       { 0x1b1c00, 128, RI_ALL_OFFLINE }, { 0x1b2000, 1, RI_ALL_OFFLINE },
+       { 0x1b2400, 64, RI_E1H_OFFLINE }, { 0x1b8200, 1, RI_ALL_ONLINE },
+       { 0x1b8240, 1, RI_ALL_ONLINE }, { 0x1b8280, 1, RI_ALL_ONLINE },
+       { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE },
+       { 0x1b8a80, 1, RI_ALL_ONLINE }, { 0x1c0000, 2, RI_ALL_ONLINE },
+       { 0x200000, 65, RI_ALL_ONLINE }, { 0x200110, 1, RI_ALL_ONLINE },
+       { 0x200120, 1, RI_ALL_ONLINE }, { 0x200130, 1, RI_ALL_ONLINE },
+       { 0x200140, 1, RI_ALL_ONLINE }, { 0x20014c, 2, RI_E1H_ONLINE },
+       { 0x200200, 58, RI_ALL_ONLINE }, { 0x200340, 4, RI_ALL_ONLINE },
+       { 0x200400, 1, RI_ALL_ONLINE }, { 0x200404, 255, RI_ALL_OFFLINE },
+       { 0x202000, 4, RI_ALL_ONLINE }, { 0x202010, 2044, RI_ALL_OFFLINE },
+       { 0x220000, 1, RI_ALL_ONLINE }, { 0x220004, 1023, RI_ALL_OFFLINE },
+       { 0x221000, 1, RI_ALL_ONLINE }, { 0x221004, 4607, RI_ALL_OFFLINE },
+       { 0x225800, 1536, RI_E1H_OFFLINE }, { 0x227000, 1, RI_E1H_ONLINE },
+       { 0x227004, 1023, RI_E1H_OFFLINE }, { 0x228000, 64, RI_ALL_OFFLINE },
+       { 0x228100, 8640, RI_E1H_OFFLINE }, { 0x231800, 128, RI_ALL_OFFLINE },
+       { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_OFFLINE },
+       { 0x232400, 64, RI_E1H_OFFLINE }, { 0x238200, 1, RI_ALL_ONLINE },
+       { 0x238240, 1, RI_ALL_ONLINE }, { 0x238280, 1, RI_ALL_ONLINE },
+       { 0x2382c0, 1, RI_ALL_ONLINE }, { 0x238a00, 1, RI_ALL_ONLINE },
+       { 0x238a80, 1, RI_ALL_ONLINE }, { 0x240000, 2, RI_ALL_ONLINE },
+       { 0x280000, 65, RI_ALL_ONLINE }, { 0x280110, 1, RI_ALL_ONLINE },
+       { 0x280120, 1, RI_ALL_ONLINE }, { 0x280130, 1, RI_ALL_ONLINE },
+       { 0x280140, 1, RI_ALL_ONLINE }, { 0x28014c, 2, RI_E1H_ONLINE },
+       { 0x280200, 58, RI_ALL_ONLINE }, { 0x280340, 4, RI_ALL_ONLINE },
+       { 0x280400, 1, RI_ALL_ONLINE }, { 0x280404, 255, RI_ALL_OFFLINE },
+       { 0x282000, 4, RI_ALL_ONLINE }, { 0x282010, 2044, RI_ALL_OFFLINE },
+       { 0x2a0000, 1, RI_ALL_ONLINE }, { 0x2a0004, 1023, RI_ALL_OFFLINE },
+       { 0x2a1000, 1, RI_ALL_ONLINE }, { 0x2a1004, 4607, RI_ALL_OFFLINE },
+       { 0x2a5800, 2560, RI_E1H_OFFLINE }, { 0x2a8000, 64, RI_ALL_OFFLINE },
+       { 0x2a8100, 960, RI_E1H_OFFLINE }, { 0x2a9000, 1, RI_E1H_ONLINE },
+       { 0x2a9004, 7679, RI_E1H_OFFLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE },
+       { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_OFFLINE },
+       { 0x2b2400, 64, RI_E1H_OFFLINE }, { 0x2b8200, 1, RI_ALL_ONLINE },
+       { 0x2b8240, 1, RI_ALL_ONLINE }, { 0x2b8280, 1, RI_ALL_ONLINE },
+       { 0x2b82c0, 1, RI_ALL_ONLINE }, { 0x2b8a00, 1, RI_ALL_ONLINE },
+       { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE },
+       { 0x300000, 65, RI_ALL_ONLINE }, { 0x300110, 1, RI_ALL_ONLINE },
+       { 0x300120, 1, RI_ALL_ONLINE }, { 0x300130, 1, RI_ALL_ONLINE },
+       { 0x300140, 1, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1H_ONLINE },
+       { 0x300200, 58, RI_ALL_ONLINE }, { 0x300340, 4, RI_ALL_ONLINE },
+       { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_ALL_OFFLINE },
+       { 0x302000, 4, RI_ALL_ONLINE }, { 0x302010, 2044, RI_ALL_OFFLINE },
+       { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 1023, RI_ALL_OFFLINE },
+       { 0x321000, 1, RI_ALL_ONLINE }, { 0x321004, 4607, RI_ALL_OFFLINE },
+       { 0x325800, 2560, RI_E1H_OFFLINE }, { 0x328000, 64, RI_ALL_OFFLINE },
+       { 0x328100, 536, RI_E1H_OFFLINE }, { 0x328960, 1, RI_E1H_ONLINE },
+       { 0x328964, 8103, RI_E1H_OFFLINE }, { 0x331800, 128, RI_ALL_OFFLINE },
+       { 0x331c00, 128, RI_ALL_OFFLINE }, { 0x332000, 1, RI_ALL_OFFLINE },
+       { 0x332400, 64, RI_E1H_OFFLINE }, { 0x338200, 1, RI_ALL_ONLINE },
+       { 0x338240, 1, RI_ALL_ONLINE }, { 0x338280, 1, RI_ALL_ONLINE },
+       { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE },
+       { 0x338a80, 1, RI_ALL_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE }
+};
+
+
+#define IDLE_REGS_COUNT                        277
+static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = {
+       { 0x2114, 1, RI_ALL_ONLINE }, { 0x2120, 1, RI_ALL_ONLINE },
+       { 0x212c, 4, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE },
+       { 0x281c, 2, RI_ALL_ONLINE }, { 0xa38c, 1, RI_ALL_ONLINE },
+       { 0xa408, 1, RI_ALL_ONLINE }, { 0xa42c, 12, RI_ALL_ONLINE },
+       { 0xa600, 5, RI_E1H_ONLINE }, { 0xa618, 1, RI_E1H_ONLINE },
+       { 0xc09c, 1, RI_ALL_ONLINE }, { 0x103b0, 1, RI_ALL_ONLINE },
+       { 0x103c0, 1, RI_ALL_ONLINE }, { 0x103d0, 1, RI_E1H_ONLINE },
+       { 0x2021c, 11, RI_ALL_ONLINE }, { 0x202a8, 1, RI_ALL_ONLINE },
+       { 0x202b8, 1, RI_ALL_ONLINE }, { 0x20404, 1, RI_ALL_ONLINE },
+       { 0x2040c, 2, RI_ALL_ONLINE }, { 0x2041c, 2, RI_ALL_ONLINE },
+       { 0x40154, 14, RI_ALL_ONLINE }, { 0x40198, 1, RI_ALL_ONLINE },
+       { 0x404ac, 1, RI_ALL_ONLINE }, { 0x404bc, 1, RI_ALL_ONLINE },
+       { 0x42290, 1, RI_ALL_ONLINE }, { 0x422a0, 1, RI_ALL_ONLINE },
+       { 0x422b0, 1, RI_ALL_ONLINE }, { 0x42548, 1, RI_ALL_ONLINE },
+       { 0x42550, 1, RI_ALL_ONLINE }, { 0x42558, 1, RI_ALL_ONLINE },
+       { 0x50160, 8, RI_ALL_ONLINE }, { 0x501d0, 1, RI_ALL_ONLINE },
+       { 0x501e0, 1, RI_ALL_ONLINE }, { 0x50204, 1, RI_ALL_ONLINE },
+       { 0x5020c, 2, RI_ALL_ONLINE }, { 0x5021c, 1, RI_ALL_ONLINE },
+       { 0x60090, 1, RI_ALL_ONLINE }, { 0x6011c, 1, RI_ALL_ONLINE },
+       { 0x6012c, 1, RI_ALL_ONLINE }, { 0xc101c, 1, RI_ALL_ONLINE },
+       { 0xc102c, 1, RI_ALL_ONLINE }, { 0xc2290, 1, RI_ALL_ONLINE },
+       { 0xc22a0, 1, RI_ALL_ONLINE }, { 0xc22b0, 1, RI_ALL_ONLINE },
+       { 0xc2548, 1, RI_ALL_ONLINE }, { 0xc2550, 1, RI_ALL_ONLINE },
+       { 0xc2558, 1, RI_ALL_ONLINE }, { 0xc4294, 1, RI_ALL_ONLINE },
+       { 0xc42a4, 1, RI_ALL_ONLINE }, { 0xc42b4, 1, RI_ALL_ONLINE },
+       { 0xc4550, 1, RI_ALL_ONLINE }, { 0xc4558, 1, RI_ALL_ONLINE },
+       { 0xc4560, 1, RI_ALL_ONLINE }, { 0xd016c, 8, RI_ALL_ONLINE },
+       { 0xd01d8, 1, RI_ALL_ONLINE }, { 0xd01e8, 1, RI_ALL_ONLINE },
+       { 0xd0204, 1, RI_ALL_ONLINE }, { 0xd020c, 3, RI_ALL_ONLINE },
+       { 0xe0154, 8, RI_ALL_ONLINE }, { 0xe01c8, 1, RI_ALL_ONLINE },
+       { 0xe01d8, 1, RI_ALL_ONLINE }, { 0xe0204, 1, RI_ALL_ONLINE },
+       { 0xe020c, 2, RI_ALL_ONLINE }, { 0xe021c, 2, RI_ALL_ONLINE },
+       { 0x101014, 1, RI_ALL_ONLINE }, { 0x101030, 1, RI_ALL_ONLINE },
+       { 0x101040, 1, RI_ALL_ONLINE }, { 0x102058, 1, RI_ALL_ONLINE },
+       { 0x102080, 16, RI_ALL_ONLINE }, { 0x103004, 2, RI_ALL_ONLINE },
+       { 0x103068, 1, RI_ALL_ONLINE }, { 0x103078, 1, RI_ALL_ONLINE },
+       { 0x103088, 1, RI_ALL_ONLINE }, { 0x10309c, 2, RI_E1H_ONLINE },
+       { 0x104004, 1, RI_ALL_ONLINE }, { 0x104018, 1, RI_ALL_ONLINE },
+       { 0x104020, 1, RI_ALL_ONLINE }, { 0x10403c, 1, RI_ALL_ONLINE },
+       { 0x1040fc, 1, RI_ALL_ONLINE }, { 0x10410c, 1, RI_ALL_ONLINE },
+       { 0x104400, 64, RI_ALL_ONLINE }, { 0x104800, 64, RI_ALL_ONLINE },
+       { 0x105000, 3, RI_ALL_ONLINE }, { 0x105010, 3, RI_ALL_ONLINE },
+       { 0x105020, 3, RI_ALL_ONLINE }, { 0x105030, 3, RI_ALL_ONLINE },
+       { 0x105040, 3, RI_ALL_ONLINE }, { 0x105050, 3, RI_ALL_ONLINE },
+       { 0x105060, 3, RI_ALL_ONLINE }, { 0x105070, 3, RI_ALL_ONLINE },
+       { 0x105080, 3, RI_ALL_ONLINE }, { 0x105090, 3, RI_ALL_ONLINE },
+       { 0x1050a0, 3, RI_ALL_ONLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
+       { 0x1050c0, 3, RI_ALL_ONLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
+       { 0x1050e0, 3, RI_ALL_ONLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
+       { 0x105100, 3, RI_ALL_ONLINE }, { 0x105110, 3, RI_ALL_ONLINE },
+       { 0x105120, 3, RI_ALL_ONLINE }, { 0x105130, 3, RI_ALL_ONLINE },
+       { 0x105140, 3, RI_ALL_ONLINE }, { 0x105150, 3, RI_ALL_ONLINE },
+       { 0x105160, 3, RI_ALL_ONLINE }, { 0x105170, 3, RI_ALL_ONLINE },
+       { 0x105180, 3, RI_ALL_ONLINE }, { 0x105190, 3, RI_ALL_ONLINE },
+       { 0x1051a0, 3, RI_ALL_ONLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
+       { 0x1051c0, 3, RI_ALL_ONLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
+       { 0x1051e0, 3, RI_ALL_ONLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
+       { 0x105200, 3, RI_ALL_ONLINE }, { 0x105210, 3, RI_ALL_ONLINE },
+       { 0x105220, 3, RI_ALL_ONLINE }, { 0x105230, 3, RI_ALL_ONLINE },
+       { 0x105240, 3, RI_ALL_ONLINE }, { 0x105250, 3, RI_ALL_ONLINE },
+       { 0x105260, 3, RI_ALL_ONLINE }, { 0x105270, 3, RI_ALL_ONLINE },
+       { 0x105280, 3, RI_ALL_ONLINE }, { 0x105290, 3, RI_ALL_ONLINE },
+       { 0x1052a0, 3, RI_ALL_ONLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
+       { 0x1052c0, 3, RI_ALL_ONLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
+       { 0x1052e0, 3, RI_ALL_ONLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
+       { 0x105300, 3, RI_ALL_ONLINE }, { 0x105310, 3, RI_ALL_ONLINE },
+       { 0x105320, 3, RI_ALL_ONLINE }, { 0x105330, 3, RI_ALL_ONLINE },
+       { 0x105340, 3, RI_ALL_ONLINE }, { 0x105350, 3, RI_ALL_ONLINE },
+       { 0x105360, 3, RI_ALL_ONLINE }, { 0x105370, 3, RI_ALL_ONLINE },
+       { 0x105380, 3, RI_ALL_ONLINE }, { 0x105390, 3, RI_ALL_ONLINE },
+       { 0x1053a0, 3, RI_ALL_ONLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
+       { 0x1053c0, 3, RI_ALL_ONLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
+       { 0x1053e0, 3, RI_ALL_ONLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
+       { 0x108094, 1, RI_ALL_ONLINE }, { 0x1201b0, 2, RI_ALL_ONLINE },
+       { 0x12032c, 1, RI_ALL_ONLINE }, { 0x12036c, 3, RI_ALL_ONLINE },
+       { 0x120408, 2, RI_ALL_ONLINE }, { 0x120414, 15, RI_ALL_ONLINE },
+       { 0x120478, 2, RI_ALL_ONLINE }, { 0x12052c, 1, RI_ALL_ONLINE },
+       { 0x120564, 3, RI_ALL_ONLINE }, { 0x12057c, 1, RI_ALL_ONLINE },
+       { 0x12058c, 1, RI_ALL_ONLINE }, { 0x120608, 1, RI_E1H_ONLINE },
+       { 0x120808, 1, RI_E1_ONLINE }, { 0x12080c, 2, RI_ALL_ONLINE },
+       { 0x120818, 1, RI_ALL_ONLINE }, { 0x120820, 1, RI_ALL_ONLINE },
+       { 0x120828, 1, RI_ALL_ONLINE }, { 0x120830, 1, RI_ALL_ONLINE },
+       { 0x120838, 1, RI_ALL_ONLINE }, { 0x120840, 1, RI_ALL_ONLINE },
+       { 0x120848, 1, RI_ALL_ONLINE }, { 0x120850, 1, RI_ALL_ONLINE },
+       { 0x120858, 1, RI_ALL_ONLINE }, { 0x120860, 1, RI_ALL_ONLINE },
+       { 0x120868, 1, RI_ALL_ONLINE }, { 0x120870, 1, RI_ALL_ONLINE },
+       { 0x120878, 1, RI_ALL_ONLINE }, { 0x120880, 1, RI_ALL_ONLINE },
+       { 0x120888, 1, RI_ALL_ONLINE }, { 0x120890, 1, RI_ALL_ONLINE },
+       { 0x120898, 1, RI_ALL_ONLINE }, { 0x1208a0, 1, RI_ALL_ONLINE },
+       { 0x1208a8, 1, RI_ALL_ONLINE }, { 0x1208b0, 1, RI_ALL_ONLINE },
+       { 0x1208b8, 1, RI_ALL_ONLINE }, { 0x1208c0, 1, RI_ALL_ONLINE },
+       { 0x1208c8, 1, RI_ALL_ONLINE }, { 0x1208d0, 1, RI_ALL_ONLINE },
+       { 0x1208d8, 1, RI_ALL_ONLINE }, { 0x1208e0, 1, RI_ALL_ONLINE },
+       { 0x1208e8, 1, RI_ALL_ONLINE }, { 0x1208f0, 1, RI_ALL_ONLINE },
+       { 0x1208f8, 1, RI_ALL_ONLINE }, { 0x120900, 1, RI_ALL_ONLINE },
+       { 0x120908, 1, RI_ALL_ONLINE }, { 0x14005c, 2, RI_ALL_ONLINE },
+       { 0x1400d0, 2, RI_ALL_ONLINE }, { 0x1400e0, 1, RI_ALL_ONLINE },
+       { 0x1401c8, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
+       { 0x16101c, 1, RI_ALL_ONLINE }, { 0x16102c, 1, RI_ALL_ONLINE },
+       { 0x164014, 2, RI_ALL_ONLINE }, { 0x1640f0, 1, RI_ALL_ONLINE },
+       { 0x166290, 1, RI_ALL_ONLINE }, { 0x1662a0, 1, RI_ALL_ONLINE },
+       { 0x1662b0, 1, RI_ALL_ONLINE }, { 0x166548, 1, RI_ALL_ONLINE },
+       { 0x166550, 1, RI_ALL_ONLINE }, { 0x166558, 1, RI_ALL_ONLINE },
+       { 0x168000, 1, RI_ALL_ONLINE }, { 0x168008, 1, RI_ALL_ONLINE },
+       { 0x168010, 1, RI_ALL_ONLINE }, { 0x168018, 1, RI_ALL_ONLINE },
+       { 0x168028, 2, RI_ALL_ONLINE }, { 0x168058, 4, RI_ALL_ONLINE },
+       { 0x168070, 1, RI_ALL_ONLINE }, { 0x168238, 1, RI_ALL_ONLINE },
+       { 0x1682d0, 2, RI_ALL_ONLINE }, { 0x1682e0, 1, RI_ALL_ONLINE },
+       { 0x168300, 67, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE },
+       { 0x168438, 1, RI_ALL_ONLINE }, { 0x168448, 1, RI_ALL_ONLINE },
+       { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16e200, 128, RI_E1H_ONLINE },
+       { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 70, RI_E1H_ONLINE },
+       { 0x1700a4, 1, RI_ALL_ONLINE }, { 0x1700ac, 2, RI_ALL_ONLINE },
+       { 0x1700c0, 1, RI_ALL_ONLINE }, { 0x170174, 1, RI_ALL_ONLINE },
+       { 0x170184, 1, RI_ALL_ONLINE }, { 0x1800f4, 1, RI_ALL_ONLINE },
+       { 0x180104, 1, RI_ALL_ONLINE }, { 0x180114, 1, RI_ALL_ONLINE },
+       { 0x180124, 1, RI_ALL_ONLINE }, { 0x18026c, 1, RI_ALL_ONLINE },
+       { 0x1802a0, 1, RI_ALL_ONLINE }, { 0x1a1000, 1, RI_ALL_ONLINE },
+       { 0x1aa000, 1, RI_E1H_ONLINE }, { 0x1b8000, 1, RI_ALL_ONLINE },
+       { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE },
+       { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x200104, 1, RI_ALL_ONLINE },
+       { 0x200114, 1, RI_ALL_ONLINE }, { 0x200124, 1, RI_ALL_ONLINE },
+       { 0x200134, 1, RI_ALL_ONLINE }, { 0x20026c, 1, RI_ALL_ONLINE },
+       { 0x2002a0, 1, RI_ALL_ONLINE }, { 0x221000, 1, RI_ALL_ONLINE },
+       { 0x227000, 1, RI_E1H_ONLINE }, { 0x238000, 1, RI_ALL_ONLINE },
+       { 0x238040, 1, RI_ALL_ONLINE }, { 0x238080, 1, RI_ALL_ONLINE },
+       { 0x2380c0, 1, RI_ALL_ONLINE }, { 0x280104, 1, RI_ALL_ONLINE },
+       { 0x280114, 1, RI_ALL_ONLINE }, { 0x280124, 1, RI_ALL_ONLINE },
+       { 0x280134, 1, RI_ALL_ONLINE }, { 0x28026c, 1, RI_ALL_ONLINE },
+       { 0x2802a0, 1, RI_ALL_ONLINE }, { 0x2a1000, 1, RI_ALL_ONLINE },
+       { 0x2a9000, 1, RI_E1H_ONLINE }, { 0x2b8000, 1, RI_ALL_ONLINE },
+       { 0x2b8040, 1, RI_ALL_ONLINE }, { 0x2b8080, 1, RI_ALL_ONLINE },
+       { 0x2b80c0, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE },
+       { 0x300114, 1, RI_ALL_ONLINE }, { 0x300124, 1, RI_ALL_ONLINE },
+       { 0x300134, 1, RI_ALL_ONLINE }, { 0x30026c, 1, RI_ALL_ONLINE },
+       { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x321000, 1, RI_ALL_ONLINE },
+       { 0x328960, 1, RI_E1H_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE },
+       { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE },
+       { 0x3380c0, 1, RI_ALL_ONLINE }
+};
+
+#define WREGS_COUNT_E1                 1
+static const u32 read_reg_e1_0[] = { 0x1b1000 };
+
+static const struct wreg_addr wreg_addrs_e1[WREGS_COUNT_E1] = {
+       { 0x1b0c00, 192, 1, read_reg_e1_0, RI_E1_OFFLINE }
+};
+
+
+#define WREGS_COUNT_E1H                        1
+static const u32 read_reg_e1h_0[] = { 0x1b1040, 0x1b1000 };
+
+static const struct wreg_addr wreg_addrs_e1h[WREGS_COUNT_E1H] = {
+       { 0x1b0c00, 256, 2, read_reg_e1h_0, RI_E1H_OFFLINE }
+};
+
+
+static const struct dump_sign dump_sign_all = { 0x49aa93ee, 0x40835, 0x22 };
+
+
+#define TIMER_REGS_COUNT_E1            2
+static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] =
+       { 0x164014, 0x164018 };
+static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] =
+       { 0x1640d0, 0x1640d4 };
+
+
+#define TIMER_REGS_COUNT_E1H           2
+static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] =
+       { 0x164014, 0x164018 };
+static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] =
+       { 0x1640d0, 0x1640d4 };
+
+
+#endif /* BNX2X_DUMP_H */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_fw_defs.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_fw_defs.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_fw_defs.h     1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_fw_defs.h  2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,589 @@
+/* bnx2x_fw_defs.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
+       (IS_E1H_OFFSET ? 0x7000 : 0x1000)
+#define CSTORM_ASSERT_LIST_OFFSET(idx) \
+       (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
+       (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
+       ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
+       0x40) + (index * 0x4)))
+#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
+       (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
+       ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
+       0x80) + (index * 0x4)))
+#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
+       ((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
+#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
+       ((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
+       ((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
+       ((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
+#define CSTORM_FUNCTION_MODE_OFFSET \
+       (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
+#define CSTORM_HC_BTR_C_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
+#define CSTORM_HC_BTR_U_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
+#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
+       (function * 0x8)))
+#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
+       (function * 0x8)))
+#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x241c + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
+       (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
+       (0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
+       (function * 0x8)))
+#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
+       (function * 0x8)))
+#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
+       (function * 0x8)))
+#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
+       (function * 0x8)))
+#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
+       (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
+       (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
+       (index * 0x4)))
+#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
+       (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
+       (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
+       (index * 0x4)))
+#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
+       (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
+       (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
+       (index * 0x4)))
+#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
+       (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
+       (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
+       (index * 0x4)))
+#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
+       (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
+       (0x3040 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
+       (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
+       (0x4000 + (port * 0x800) + (cpu_id * 0x80)))
+#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
+       (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
+       (0x3048 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
+       (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
+       (0x4008 + (port * 0x800) + (cpu_id * 0x80)))
+#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
+#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
+#define CSTORM_STATS_FLAGS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
+       (function * 0x8)))
+#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
+#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
+       (IS_E1H_OFFSET ? 0xa000 : 0x1000)
+#define TSTORM_ASSERT_LIST_OFFSET(idx) \
+       (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
+       (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
+       : (0x9c0 + (port * 0x120) + (client_id * 0x10)))
+#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
+       (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
+#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
+       (IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
+#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
+       (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
+       0x28) + (index * 0x4)))
+#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
+#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
+#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
+       (function * 0x8)))
+#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
+       (function * 0x40)))
+#define TSTORM_FUNCTION_MODE_OFFSET \
+       (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
+#define TSTORM_HC_BTR_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
+       (function * 0x80)))
+#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
+#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
+       (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
+       : (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
+#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
+       (function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
+       (function * 0x8)))
+#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
+       (function * 0x40)))
+#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+       (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
+       0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
+#define TSTORM_STATS_FLAGS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
+       (function * 0x8)))
+#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
+       (function * 0x8)))
+#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
+#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET \
+       (IS_E1H_OFFSET ? 0x8000 : 0x1000)
+#define USTORM_ASSERT_LIST_OFFSET(idx) \
+       (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
+       (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
+       (0x4010 + (port * 0x360) + (clientId * 0x30)))
+#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
+       (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
+       (0x4028 + (port * 0x360) + (clientId * 0x30)))
+#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
+#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
+       (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
+       0xffffffff)
+#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
+       (function * 0x8)))
+#define USTORM_FUNCTION_MODE_OFFSET \
+       (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
+#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
+       (function * 0x8)))
+#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
+       (function * 0x8)))
+#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
+       (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
+       (0x4018 + (port * 0x360) + (clientId * 0x30)))
+#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
+       (function * 0x8)))
+#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+       (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
+       0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
+#define USTORM_RX_PRODS_OFFSET(port, client_id) \
+       (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
+       : (0x4000 + (port * 0x360) + (client_id * 0x30)))
+#define USTORM_STATS_FLAGS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
+       (function * 0x8)))
+#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
+#define USTORM_TPA_BTR_SIZE 0x1
+#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
+       (IS_E1H_OFFSET ? 0x9000 : 0x1000)
+#define XSTORM_ASSERT_LIST_OFFSET(idx) \
+       (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
+#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
+       (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
+       0x28) + (index * 0x4)))
+#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
+#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
+#define XSTORM_E1HOV_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
+#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
+       (function * 0x8)))
+#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
+       (function * 0x90)))
+#define XSTORM_FUNCTION_MODE_OFFSET \
+       (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
+#define XSTORM_HC_BTR_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
+       (function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
+       (function * 0x8)))
+#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+       (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
+       0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
+#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
+       (function * 0x90)))
+#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
+       (function * 0x10)))
+#define XSTORM_SPQ_PROD_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
+       (function * 0x10)))
+#define XSTORM_STATS_FLAGS_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
+       (function * 0x8)))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
+       (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
+#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
+       (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
+       * 0x4)) : (0x1978 + (function * 0x4)))
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+
+/**
+* This file defines HSI constants for the ETH flow
+*/
+#ifdef _EVEREST_MICROCODE
+#include "microcode_constants.h"
+#include "eth_rx_bd.h"
+#include "eth_tx_bd.h"
+#include "eth_rx_cqe.h"
+#include "eth_rx_sge.h"
+#include "eth_rx_cqe_next_page.h"
+#endif
+
+/* RSS hash types */
+#define DEFAULT_HASH_TYPE 0
+#define IPV4_HASH_TYPE 1
+#define TCP_IPV4_HASH_TYPE 2
+#define IPV6_HASH_TYPE 3
+#define TCP_IPV6_HASH_TYPE 4
+#define VLAN_PRI_HASH_TYPE 5
+#define E1HOV_PRI_HASH_TYPE 6
+#define DSCP_HASH_TYPE 7
+
+
+/* Ethernet Ring parameters */
+#define X_ETH_LOCAL_RING_SIZE 13
+#define FIRST_BD_IN_PKT 0
+#define PARSE_BD_INDEX 1
+#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
+#define U_ETH_NUM_OF_SGES_TO_FETCH 8
+#define U_ETH_MAX_SGES_FOR_PACKET 3
+
+/* Rx ring params */
+#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_LOCAL_SGE_RING_SIZE 10
+#define U_ETH_SGL_SIZE 8
+
+
+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
+       (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
+
+#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
+#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
+
+#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
+#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
+
+#define U_ETH_UNDEFINED_Q 0xFF
+
+/* values of command IDs in the ramrod message */
+#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
+#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
+#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
+#define RAMROD_CMD_ID_ETH_UPDATE 100
+#define RAMROD_CMD_ID_ETH_HALT 105
+#define RAMROD_CMD_ID_ETH_SET_MAC 110
+#define RAMROD_CMD_ID_ETH_CFC_DEL 115
+#define RAMROD_CMD_ID_ETH_PORT_DEL 120
+#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
+
+
+/* command values for set mac command */
+#define T_ETH_MAC_COMMAND_SET 0
+#define T_ETH_MAC_COMMAND_INVALIDATE 1
+
+#define T_ETH_INDIRECTION_TABLE_SIZE 128
+
+/*The CRC32 seed, that is used for the hash(reduction) multicast address */
+#define T_ETH_CRC32_HASH_SEED 0x00000000
+
+/* Maximal L2 clients supported */
+#define ETH_MAX_RX_CLIENTS_E1 18
+#define ETH_MAX_RX_CLIENTS_E1H 26
+
+/* Maximal aggregation queues supported */
+#define ETH_MAX_AGGREGATION_QUEUES_E1 32
+#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
+
+/* ETH RSS modes */
+#define ETH_RSS_MODE_DISABLED 0
+#define ETH_RSS_MODE_REGULAR 1
+#define ETH_RSS_MODE_VLAN_PRI 2
+#define ETH_RSS_MODE_E1HOV_PRI 3
+#define ETH_RSS_MODE_IP_DSCP 4
+
+
+/**
+* This file defines HSI constants common to all microcode flows
+*/
+
+/* Connection types */
+#define ETH_CONNECTION_TYPE 0
+#define TOE_CONNECTION_TYPE 1
+#define RDMA_CONNECTION_TYPE 2
+#define ISCSI_CONNECTION_TYPE 3
+#define FCOE_CONNECTION_TYPE 4
+#define RESERVED_CONNECTION_TYPE_0 5
+#define RESERVED_CONNECTION_TYPE_1 6
+#define RESERVED_CONNECTION_TYPE_2 7
+
+
+#define PROTOCOL_STATE_BIT_OFFSET 6
+
+#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+
+/* microcode fixed page page size 4K (chains and ring segments) */
+#define MC_PAGE_SIZE 4096
+
+
+/* Host coalescing constants */
+
+/* index numbers */
+#define HC_USTORM_DEF_SB_NUM_INDICES 8
+#define HC_CSTORM_DEF_SB_NUM_INDICES 8
+#define HC_XSTORM_DEF_SB_NUM_INDICES 4
+#define HC_TSTORM_DEF_SB_NUM_INDICES 4
+#define HC_USTORM_SB_NUM_INDICES 4
+#define HC_CSTORM_SB_NUM_INDICES 4
+
+/* index values - which counter to update */
+
+#define HC_INDEX_U_TOE_RX_CQ_CONS 0
+#define HC_INDEX_U_ETH_RX_CQ_CONS 1
+#define HC_INDEX_U_ETH_RX_BD_CONS 2
+#define HC_INDEX_U_FCOE_EQ_CONS 3
+
+#define HC_INDEX_C_TOE_TX_CQ_CONS 0
+#define HC_INDEX_C_ETH_TX_CQ_CONS 1
+#define HC_INDEX_C_ISCSI_EQ_CONS 2
+
+#define HC_INDEX_DEF_X_SPQ_CONS 0
+
+#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
+#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
+#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
+#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
+#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
+#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
+#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
+
+#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
+#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
+#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
+#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
+
+/* used by the driver to get the SB offset */
+#define USTORM_ID 0
+#define CSTORM_ID 1
+#define XSTORM_ID 2
+#define TSTORM_ID 3
+#define ATTENTION_ID 4
+
+/* max number of slow path commands per port */
+#define MAX_RAMRODS_PER_PORT 8
+
+/* values for RX ETH CQE type field */
+#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
+#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
+
+
+/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+#define EMULATION_FREQUENCY_FACTOR 1600
+#define FPGA_FREQUENCY_FACTOR 100
+
+#define TIMERS_TICK_SIZE_CHIP (1e-3)
+#define TIMERS_TICK_SIZE_EMUL \
+ ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
+#define TIMERS_TICK_SIZE_FPGA \
+ ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
+
+#define TSEMI_CLK1_RESUL_CHIP (1e-3)
+#define TSEMI_CLK1_RESUL_EMUL \
+ ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define TSEMI_CLK1_RESUL_FPGA \
+ ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
+#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
+#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
+
+#define XSEMI_CLK1_RESUL_CHIP (1e-3)
+#define XSEMI_CLK1_RESUL_EMUL \
+ ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK1_RESUL_FPGA \
+ ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+#define XSEMI_CLK2_RESUL_CHIP (1e-6)
+#define XSEMI_CLK2_RESUL_EMUL \
+ ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK2_RESUL_FPGA \
+ ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
+#define SDM_TIMER_TICK_RESUL_EMUL \
+ ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define SDM_TIMER_TICK_RESUL_FPGA \
+ ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+#define XSTORM_IP_ID_ROLL_HALF 0x8000
+#define XSTORM_IP_ID_ROLL_ALL 0
+
+#define FW_LOG_LIST_SIZE 50
+
+#define NUM_OF_PROTOCOLS 4
+#define NUM_OF_SAFC_BITS 16
+#define MAX_COS_NUMBER 4
+#define MAX_T_STAT_COUNTER_ID 18
+#define MAX_X_STAT_COUNTER_ID 18
+#define MAX_U_STAT_COUNTER_ID 18
+
+
+#define UNKNOWN_ADDRESS 0
+#define UNICAST_ADDRESS 1
+#define MULTICAST_ADDRESS 2
+#define BROADCAST_ADDRESS 3
+
+#define SINGLE_FUNCTION 0
+#define MULTI_FUNCTION 1
+
+#define IP_V4 0
+#define IP_V6 1
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_fw_file_hdr.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_fw_file_hdr.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_fw_file_hdr.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_fw_file_hdr.h      2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,37 @@
+/* bnx2x_fw_file_hdr.h: FW binary file header structure.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Vladislav Zolotarov <vladz@broadcom.com>
+ * Based on the original idea of John Wright <john.wright@hp.com>.
+ */
+
+#ifndef BNX2X_INIT_FILE_HDR_H
+#define BNX2X_INIT_FILE_HDR_H
+
+struct bnx2x_fw_file_section {
+       __be32 len;
+       __be32 offset;
+};
+
+struct bnx2x_fw_file_hdr {
+       struct bnx2x_fw_file_section init_ops;
+       struct bnx2x_fw_file_section init_ops_offsets;
+       struct bnx2x_fw_file_section init_data;
+       struct bnx2x_fw_file_section tsem_int_table_data;
+       struct bnx2x_fw_file_section tsem_pram_data;
+       struct bnx2x_fw_file_section usem_int_table_data;
+       struct bnx2x_fw_file_section usem_pram_data;
+       struct bnx2x_fw_file_section csem_int_table_data;
+       struct bnx2x_fw_file_section csem_pram_data;
+       struct bnx2x_fw_file_section xsem_int_table_data;
+       struct bnx2x_fw_file_section xsem_pram_data;
+       struct bnx2x_fw_file_section fw_version;
+};
+
+#endif /* BNX2X_INIT_FILE_HDR_H */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x.h     1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x.h  2010-03-10 20:21:34.659214293 -0500
@@ -0,0 +1,1446 @@
+/* bnx2x.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Eliezer Tamir
+ * Based on code from Michael Chan's bnx2 driver
+ */
+
+#ifndef BNX2X_H
+#define BNX2X_H
+
+/* compilation time flags */
+
+/* define this to make the driver freeze on error to allow getting debug info
+ * (you will need to reboot afterwards) */
+/* #define BNX2X_STOP_ON_ERROR */
+
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#define BCM_VLAN                       1
+#endif
+
+#if (LINUX_VERSION_CODE >= 0x020610) /* ! BNX2X_UPSTREAM */
+#define BCM_CNIC
+#endif
+
+#if ((LINUX_VERSION_CODE >= 0x020617) && !defined(NETIF_F_MULTI_QUEUE)) /* BNX2X_UPSTREAM */
+#define BNX2X_MULTI_QUEUE
+#endif
+
+#if (LINUX_VERSION_CODE >= 0x020618) || defined(__VMKLNX__) /* BNX2X_UPSTREAM */
+#define BNX2X_NEW_NAPI
+#endif
+
+#if defined(BNX2X_MULTI_QUEUE) && !defined(__VMKLNX__) /* ! BNX2X_UPSTREAM */
+#define BNX2X_SAFC
+#endif
+
+#ifdef __VMKLNX__ /* ! BNX2X_UPSTREAM */
+#if (VMWARE_ESX_DDK_VERSION < 40000)
+#define __NO_TPA__             1
+#else
+#define BCM_CNIC
+#define BNX2X_MULTI_QUEUE
+#endif
+#define KERN_CONT              KERN_INFO
+#endif
+
+#if (LINUX_VERSION_CODE > 0x02061e) /* BNX2X_UPSTREAM */
+#include <linux/mdio.h>
+#endif
+#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
+#include "bnx2x_compat.h"
+#endif
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+#include "cnic_drv.h"
+#endif
+#include "bnx2x_reg.h"
+#include "bnx2x_fw_defs.h"
+#include "bnx2x_hsi.h"
+#include "bnx2x_link.h"
+
+/* error/debug prints */
+
+#define DRV_MODULE_NAME                "bnx2x"
+#define PFX DRV_MODULE_NAME    ": "
+
+/* for messages that are currently off */
+#define BNX2X_MSG_OFF                  0
+#define BNX2X_MSG_MCP                  0x010000 /* was: NETIF_MSG_HW */
+#define BNX2X_MSG_STATS                        0x020000 /* was: NETIF_MSG_TIMER */
+#define BNX2X_MSG_NVM                  0x040000 /* was: NETIF_MSG_HW */
+#define BNX2X_MSG_DMAE                 0x080000 /* was: NETIF_MSG_HW */
+#define BNX2X_MSG_SP                   0x100000 /* was: NETIF_MSG_INTR */
+#define BNX2X_MSG_FP                   0x200000 /* was: NETIF_MSG_INTR */
+
+#define DP_LEVEL                       KERN_NOTICE     /* was: KERN_DEBUG */
+
+/* regular debug print */
+#define DP(__mask, __fmt, __args...) do { \
+       if (bp->msglevel & (__mask)) \
+               printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
+                       bp->dev ? (bp->dev->name) : "?", ##__args); \
+       } while (0)
+
+/* errors debug print */
+#define BNX2X_DBG_ERR(__fmt, __args...) do { \
+       if (bp->msglevel & NETIF_MSG_PROBE) \
+               printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
+                       bp->dev ? (bp->dev->name) : "?", ##__args); \
+       } while (0)
+
+/* for errors (never masked) */
+#define BNX2X_ERR(__fmt, __args...) do { \
+       printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
+               bp->dev ? (bp->dev->name) : "?", ##__args); \
+       } while (0)
+
+#define BNX2X_ERROR(__fmt, __args...) do { \
+       printk(KERN_ERR "[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
+       } while (0)
+
+/* before we have a dev->name use dev_info() */
+#define BNX2X_DEV_INFO(__fmt, __args...) do { \
+       if (bp->msglevel & NETIF_MSG_PROBE) \
+               dev_info(&bp->pdev->dev, __fmt, ##__args); \
+       } while (0)
+
+
+#ifdef BNX2X_STOP_ON_ERROR
+#define bnx2x_panic() do { \
+               bp->panic = 1; \
+               BNX2X_ERR("driver assert\n"); \
+               bnx2x_int_disable(bp); \
+               bnx2x_panic_dump(bp); \
+       } while (0)
+#else
+#define bnx2x_panic() do { \
+               bp->panic = 1; \
+               BNX2X_ERR("driver assert\n"); \
+               bnx2x_panic_dump(bp); \
+       } while (0)
+#endif
+
+
+#define U64_LO(x)                      (u32)(((u64)(x)) & 0xffffffff)
+#define U64_HI(x)                      (u32)(((u64)(x)) >> 32)
+#define HILO_U64(hi, lo)               ((((u64)(hi)) << 32) + (lo))
+
+
+#define REG_ADDR(bp, offset)           (bp->regview + offset)
+
+#define REG_RD(bp, offset)             readl(REG_ADDR(bp, offset))
+#define REG_RD8(bp, offset)            readb(REG_ADDR(bp, offset))
+
+#define REG_WR(bp, offset, val)                writel((u32)val, REG_ADDR(bp, offset))
+#define REG_WR8(bp, offset, val)       writeb((u8)val, REG_ADDR(bp, offset))
+#define REG_WR16(bp, offset, val)      writew((u16)val, REG_ADDR(bp, offset))
+
+#define REG_RD_IND(bp, offset)         bnx2x_reg_rd_ind(bp, offset)
+#define REG_WR_IND(bp, offset, val)    bnx2x_reg_wr_ind(bp, offset, val)
+
+#define REG_RD_DMAE(bp, offset, valp, len32) \
+       do { \
+               bnx2x_read_dmae(bp, offset, len32);\
+               memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
+       } while (0)
+
+#define REG_WR_DMAE(bp, offset, valp, len32) \
+       do { \
+               memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
+               bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
+                                offset, len32); \
+       } while (0)
+
+#define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \
+       do { \
+               memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
+               bnx2x_write_big_buf_wb(bp, addr, len32); \
+       } while (0)
+
+#define SHMEM_ADDR(bp, field)          (bp->common.shmem_base + \
+                                        offsetof(struct shmem_region, field))
+#define SHMEM_RD(bp, field)            REG_RD(bp, SHMEM_ADDR(bp, field))
+#define SHMEM_WR(bp, field, val)       REG_WR(bp, SHMEM_ADDR(bp, field), val)
+
+#define SHMEM2_ADDR(bp, field)         (bp->common.shmem2_base + \
+                                        offsetof(struct shmem2_region, field))
+#define SHMEM2_RD(bp, field)           REG_RD(bp, SHMEM2_ADDR(bp, field))
+#define SHMEM2_WR(bp, field, val)      REG_WR(bp, SHMEM2_ADDR(bp, field), val)
+
+#define EMAC_RD(bp, reg)               REG_RD(bp, emac_base + reg)
+#define EMAC_WR(bp, reg, val)          REG_WR(bp, emac_base + reg, val)
+
+
+/* fast path */
+
+struct sw_rx_bd {
+       struct sk_buff  *skb;
+       DECLARE_PCI_UNMAP_ADDR(mapping)
+};
+
+struct sw_tx_bd {
+       struct sk_buff  *skb;
+       u16             first_bd;
+       u8              flags;
+/* Set on the first BD descriptor when there is a split BD */
+#define BNX2X_TSO_SPLIT_BD             (1<<0)
+};
+
+struct sw_rx_page {
+       struct page     *page;
+       DECLARE_PCI_UNMAP_ADDR(mapping)
+};
+
+union db_prod {
+       struct doorbell_set_prod data;
+       u32             raw;
+};
+
+
+/* MC hsi */
+#define BCM_PAGE_SHIFT                 12
+#define BCM_PAGE_SIZE                  (1 << BCM_PAGE_SHIFT)
+#define BCM_PAGE_MASK                  (~(BCM_PAGE_SIZE - 1))
+#define BCM_PAGE_ALIGN(addr)   (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
+
+#define PAGES_PER_SGE_SHIFT            0
+#define PAGES_PER_SGE                  (1 << PAGES_PER_SGE_SHIFT)
+#define SGE_PAGE_SIZE                  PAGE_SIZE
+#define SGE_PAGE_SHIFT                 PAGE_SHIFT
+#define SGE_PAGE_ALIGN(addr)           PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
+
+/* SGE ring related macros */
+#define NUM_RX_SGE_PAGES               2
+#define RX_SGE_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
+#define MAX_RX_SGE_CNT                 (RX_SGE_CNT - 2)
+/* RX_SGE_CNT is promised to be a power of 2 */
+#define RX_SGE_MASK                    (RX_SGE_CNT - 1)
+#define NUM_RX_SGE                     (RX_SGE_CNT * NUM_RX_SGE_PAGES)
+#define MAX_RX_SGE                     (NUM_RX_SGE - 1)
+#define NEXT_SGE_IDX(x)                ((((x) & RX_SGE_MASK) == \
+                                 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
+#define RX_SGE(x)                      ((x) & MAX_RX_SGE)
+
+/* SGE producer mask related macros */
+/* Number of bits in one sge_mask array element */
+#define RX_SGE_MASK_ELEM_SZ            64
+#define RX_SGE_MASK_ELEM_SHIFT         6
+#define RX_SGE_MASK_ELEM_MASK          ((u64)RX_SGE_MASK_ELEM_SZ - 1)
+
+/* Creates a bitmask of all ones in less significant bits.
+   idx - index of the most significant bit in the created mask */
+#define RX_SGE_ONES_MASK(idx) \
+               (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
+#define RX_SGE_MASK_ELEM_ONE_MASK      ((u64)(~0))
+
+/* Number of u64 elements in SGE mask array */
+#define RX_SGE_MASK_LEN                        ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
+                                        RX_SGE_MASK_ELEM_SZ)
+#define RX_SGE_MASK_LEN_MASK           (RX_SGE_MASK_LEN - 1)
+#define NEXT_SGE_MASK_ELEM(el)         (((el) + 1) & RX_SGE_MASK_LEN_MASK)
+
+
+struct bnx2x_eth_q_stats {
+       u32 total_bytes_received_hi;
+       u32 total_bytes_received_lo;
+       u32 total_bytes_transmitted_hi;
+       u32 total_bytes_transmitted_lo;
+       u32 total_unicast_packets_received_hi;
+       u32 total_unicast_packets_received_lo;
+       u32 total_multicast_packets_received_hi;
+       u32 total_multicast_packets_received_lo;
+       u32 total_broadcast_packets_received_hi;
+       u32 total_broadcast_packets_received_lo;
+       u32 total_unicast_packets_transmitted_hi;
+       u32 total_unicast_packets_transmitted_lo;
+       u32 total_multicast_packets_transmitted_hi;
+       u32 total_multicast_packets_transmitted_lo;
+       u32 total_broadcast_packets_transmitted_hi;
+       u32 total_broadcast_packets_transmitted_lo;
+       u32 valid_bytes_received_hi;
+       u32 valid_bytes_received_lo;
+
+       u32 error_bytes_received_hi;
+       u32 error_bytes_received_lo;
+       u32 etherstatsoverrsizepkts_hi;
+       u32 etherstatsoverrsizepkts_lo;
+       u32 no_buff_discard_hi;
+       u32 no_buff_discard_lo;
+
+       u32 driver_xoff;
+       u32 rx_err_discard_pkt;
+       u32 rx_skb_alloc_failed;
+       u32 hw_csum_err;
+};
+
+#define BNX2X_NUM_Q_STATS              11
+#define Q_STATS_OFFSET32(stat_name) \
+                       (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
+
+struct bnx2x_fastpath {
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       struct napi_struct      napi;
+#endif
+
+       u8                      is_rx_queue;
+
+       struct host_status_block *status_blk;
+       dma_addr_t              status_blk_mapping;
+
+       struct sw_tx_bd         *tx_buf_ring;
+
+       union eth_tx_bd_types   *tx_desc_ring;
+       dma_addr_t              tx_desc_mapping;
+
+       struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
+       struct sw_rx_page       *rx_page_ring;  /* SGE pages mappings ring */
+
+       struct eth_rx_bd        *rx_desc_ring;
+       dma_addr_t              rx_desc_mapping;
+
+       union eth_rx_cqe        *rx_comp_ring;
+       dma_addr_t              rx_comp_mapping;
+
+       /* SGE ring */
+       struct eth_rx_sge       *rx_sge_ring;
+       dma_addr_t              rx_sge_mapping;
+
+       u64                     sge_mask[RX_SGE_MASK_LEN];
+
+       int                     state;
+#define BNX2X_FP_STATE_CLOSED          0
+#define BNX2X_FP_STATE_IRQ             0x80000
+#define BNX2X_FP_STATE_OPENING         0x90000
+#define BNX2X_FP_STATE_OPEN            0xa0000
+#define BNX2X_FP_STATE_HALTING         0xb0000
+#define BNX2X_FP_STATE_HALTED          0xc0000
+
+       u8                      index;  /* number in fp array */
+       u8                      cl_id;  /* eth client id */
+       u8                      sb_id;  /* status block number in HW */
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       u8                      cos;
+#endif
+
+       union db_prod           tx_db;
+
+       u16                     tx_pkt_prod;
+       u16                     tx_pkt_cons;
+       u16                     tx_bd_prod;
+       u16                     tx_bd_cons;
+       __le16                  *tx_cons_sb;
+
+       __le16                  fp_c_idx;
+       __le16                  fp_u_idx;
+
+       u16                     rx_bd_prod;
+       u16                     rx_bd_cons;
+       u16                     rx_comp_prod;
+       u16                     rx_comp_cons;
+       u16                     rx_sge_prod;
+       /* The last maximal completed SGE */
+       u16                     last_max_sge;
+       __le16                  *rx_cons_sb;
+       __le16                  *rx_bd_cons_sb;
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+       u16                     netq_flags;
+#define BNX2X_NETQ_RX_QUEUE_ALLOCATED  0x0001
+#define BNX2X_NETQ_TX_QUEUE_ALLOCATED  0x0002
+#define BNX2X_NETQ_RX_QUEUE_ACTIVE     0x0004
+#define BNX2X_NETQ_TX_QUEUE_ACTIVE     0x0008
+
+#define BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp) \
+                       ((fp->netq_flags & BNX2X_NETQ_RX_QUEUE_ALLOCATED) == \
+                         BNX2X_NETQ_RX_QUEUE_ALLOCATED)
+#define BNX2X_IS_NETQ_TX_QUEUE_ALLOCATED(fp) \
+                       ((fp->netq_flags & BNX2X_NETQ_TX_QUEUE_ALLOCATED) == \
+                         BNX2X_NETQ_TX_QUEUE_ALLOCATED)
+#define BNX2X_IS_NETQ_RX_QUEUE_ACTIVE(fp) \
+                       ((fp->netq_flags & BNX2X_NETQ_RX_QUEUE_ACTIVE) == \
+                         BNX2X_NETQ_RX_QUEUE_ACTIVE)
+#define BNX2X_IS_NETQ_TX_QUEUE_ACTIVE(fp) \
+                       ((fp->netq_flags & BNX2X_NETQ_TX_QUEUE_ACTIVE) == \
+                         BNX2X_NETQ_TX_QUEUE_ACTIVE)
+
+       u8                      mac_filter_addr[6];
+#endif
+
+       unsigned long           tx_pkt,
+                               rx_pkt,
+                               rx_calls;
+
+       /* TPA related */
+       struct sw_rx_bd         tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
+       u8                      tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
+#define BNX2X_TPA_START                        1
+#define BNX2X_TPA_STOP                 2
+       u8                      disable_tpa;
+#ifdef BNX2X_STOP_ON_ERROR
+       u64                     tpa_queue_used;
+#endif
+
+       struct tstorm_per_client_stats old_tclient;
+       struct ustorm_per_client_stats old_uclient;
+       struct xstorm_per_client_stats old_xclient;
+       struct bnx2x_eth_q_stats eth_q_stats;
+
+       /* The size is calculated using the following:
+            sizeof name field from netdev structure +
+            4 ('-Xx-' string) +
+            4 (for the digits and to make it DWORD aligned) */
+#define FP_NAME_SIZE           (sizeof(((struct net_device *)0)->name) + 8)
+       char                    name[FP_NAME_SIZE];
+       struct bnx2x            *bp; /* parent */
+};
+
+#define bnx2x_fp(bp, nr, var)          (bp->fp[nr].var)
+
+
+/* MC hsi */
+#define MAX_FETCH_BD                   13      /* HW max BDs per packet */
+#define RX_COPY_THRESH                 92
+
+#define NUM_TX_RINGS                   16
+#define TX_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
+#define MAX_TX_DESC_CNT                        (TX_DESC_CNT - 1)
+#define NUM_TX_BD                      (TX_DESC_CNT * NUM_TX_RINGS)
+#define MAX_TX_BD                      (NUM_TX_BD - 1)
+#define MAX_TX_AVAIL                   (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
+#define NEXT_TX_IDX(x)         ((((x) & MAX_TX_DESC_CNT) == \
+                                 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
+#define TX_BD(x)                       ((x) & MAX_TX_BD)
+#define TX_BD_POFF(x)                  ((x) & MAX_TX_DESC_CNT)
+
+/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
+#if !defined(__VMKLNX__) /* BNX2X_UPSTREAM */
+#define NUM_RX_RINGS                   8
+#else
+#define NUM_RX_RINGS                   1
+#endif
+#define RX_DESC_CNT            (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
+#define MAX_RX_DESC_CNT                        (RX_DESC_CNT - 2)
+#define RX_DESC_MASK                   (RX_DESC_CNT - 1)
+#define NUM_RX_BD                      (RX_DESC_CNT * NUM_RX_RINGS)
+#define MAX_RX_BD                      (NUM_RX_BD - 1)
+#define MAX_RX_AVAIL                   (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
+#define NEXT_RX_IDX(x)         ((((x) & RX_DESC_MASK) == \
+                                 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
+#define RX_BD(x)                       ((x) & MAX_RX_BD)
+
+/* As long as CQE is 4 times bigger than BD entry we have to allocate
+   4 times more pages for CQ ring in order to keep it balanced with
+   BD ring */
+#define NUM_RCQ_RINGS                  (NUM_RX_RINGS * 4)
+#define RCQ_DESC_CNT           (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
+#define MAX_RCQ_DESC_CNT               (RCQ_DESC_CNT - 1)
+#define NUM_RCQ_BD                     (RCQ_DESC_CNT * NUM_RCQ_RINGS)
+#define MAX_RCQ_BD                     (NUM_RCQ_BD - 1)
+#define MAX_RCQ_AVAIL                  (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
+#define NEXT_RCQ_IDX(x)                ((((x) & MAX_RCQ_DESC_CNT) == \
+                                 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
+#define RCQ_BD(x)                      ((x) & MAX_RCQ_BD)
+
+
+/* This is needed for determining of last_max */
+#define SUB_S16(a, b)                  (s16)((s16)(a) - (s16)(b))
+
+#define __SGE_MASK_SET_BIT(el, bit) \
+       do { \
+               el = ((el) | ((u64)0x1 << (bit))); \
+       } while (0)
+
+#define __SGE_MASK_CLEAR_BIT(el, bit) \
+       do { \
+               el = ((el) & (~((u64)0x1 << (bit)))); \
+       } while (0)
+
+#define SGE_MASK_SET_BIT(fp, idx) \
+       __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
+                          ((idx) & RX_SGE_MASK_ELEM_MASK))
+
+#define SGE_MASK_CLEAR_BIT(fp, idx) \
+       __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
+                            ((idx) & RX_SGE_MASK_ELEM_MASK))
+
+
+/* used on a CID received from the HW */
+#define SW_CID(x)                      (le32_to_cpu(x) & \
+                                        (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
+#define CQE_CMD(x)                     (le32_to_cpu(x) >> \
+                                       COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
+
+#define BD_UNMAP_ADDR(bd)              HILO_U64(le32_to_cpu((bd)->addr_hi), \
+                                                le32_to_cpu((bd)->addr_lo))
+#define BD_UNMAP_LEN(bd)               (le16_to_cpu((bd)->nbytes))
+
+
+#define DPM_TRIGER_TYPE                        0x40
+#define DOORBELL(bp, cid, val) \
+       do { \
+               writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
+                      DPM_TRIGER_TYPE); \
+       } while (0)
+
+
+/* TX CSUM helpers */
+#if (LINUX_VERSION_CODE >= 0x020616) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */
+#define SKB_CS_OFF(skb)                (offsetof(struct tcphdr, check) - \
+                                skb->csum_offset)
+#define SKB_CS(skb)            (*(u16 *)(skb_transport_header(skb) + \
+                                         skb->csum_offset))
+#else
+#define SKB_CS_OFF(skb)                (offsetof(struct tcphdr, check) - skb->csum)
+#define SKB_CS(skb)            (*(u16 *)(skb->h.raw + skb->csum))
+#endif
+
+#define pbd_tcp_flags(skb)     (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
+
+#define XMIT_PLAIN                     0
+#define XMIT_CSUM_V4                   0x1
+#define XMIT_CSUM_V6                   0x2
+#define XMIT_CSUM_TCP                  0x4
+#define XMIT_GSO_V4                    0x8
+#define XMIT_GSO_V6                    0x10
+
+#define XMIT_CSUM                      (XMIT_CSUM_V4 | XMIT_CSUM_V6)
+#define XMIT_GSO                       (XMIT_GSO_V4 | XMIT_GSO_V6)
+
+
+/* stuff added to make the code fit 80Col */
+
+#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
+
+#define TPA_TYPE_START                 ETH_FAST_PATH_RX_CQE_START_FLG
+#define TPA_TYPE_END                   ETH_FAST_PATH_RX_CQE_END_FLG
+#define TPA_TYPE(cqe_fp_flags)         ((cqe_fp_flags) & \
+                                        (TPA_TYPE_START | TPA_TYPE_END))
+
+#define ETH_RX_ERROR_FALGS             ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
+
+#define BNX2X_IP_CSUM_ERR(cqe) \
+                       (!((cqe)->fast_path_cqe.status_flags & \
+                          ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
+                        ((cqe)->fast_path_cqe.type_error_flags & \
+                         ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
+
+#define BNX2X_L4_CSUM_ERR(cqe) \
+                       (!((cqe)->fast_path_cqe.status_flags & \
+                          ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
+                        ((cqe)->fast_path_cqe.type_error_flags & \
+                         ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
+
+#define BNX2X_RX_CSUM_OK(cqe) \
+                       (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
+
+#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
+                               (((le16_to_cpu(flags) & \
+                                  PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
+                                 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
+                                == PRS_FLAG_OVERETH_IPV4)
+#define BNX2X_RX_SUM_FIX(cqe) \
+       BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
+
+
+#define FP_USB_FUNC_OFF                        (2 + 2*HC_USTORM_SB_NUM_INDICES)
+#define FP_CSB_FUNC_OFF                        (2 + 2*HC_CSTORM_SB_NUM_INDICES)
+
+#define U_SB_ETH_RX_CQ_INDEX           HC_INDEX_U_ETH_RX_CQ_CONS
+#define U_SB_ETH_RX_BD_INDEX           HC_INDEX_U_ETH_RX_BD_CONS
+#define C_SB_ETH_TX_CQ_INDEX           HC_INDEX_C_ETH_TX_CQ_CONS
+
+#define BNX2X_RX_SB_INDEX \
+       (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
+
+#define BNX2X_RX_SB_BD_INDEX \
+       (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
+
+#define BNX2X_RX_SB_INDEX_NUM \
+               (((U_SB_ETH_RX_CQ_INDEX << \
+                  USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
+                 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
+                ((U_SB_ETH_RX_BD_INDEX << \
+                  USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
+                 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
+
+#define BNX2X_TX_SB_INDEX \
+       (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
+
+
+/* end of fast path */
+
+/* common */
+
+struct bnx2x_common {
+
+       u32                     chip_id;
+/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+#define CHIP_ID(bp)                    (bp->common.chip_id & 0xfffffff0)
+
+#define CHIP_NUM(bp)                   (bp->common.chip_id >> 16)
+#define CHIP_NUM_57710                 0x164e
+#define CHIP_NUM_57711                 0x164f
+#define CHIP_NUM_57711E                        0x1650
+#define CHIP_NUM_57712                 0x1662
+#define CHIP_NUM_57712E                        0x1663
+#define CHIP_NUM_57713                 0x1651
+#define CHIP_NUM_57713E                        0x1652
+#define CHIP_IS_E1(bp)                 (CHIP_NUM(bp) == CHIP_NUM_57710)
+#define CHIP_IS_57711(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711)
+#define CHIP_IS_57711E(bp)             (CHIP_NUM(bp) == CHIP_NUM_57711E)
+#define CHIP_IS_57712(bp)              (CHIP_NUM(bp) == CHIP_NUM_57712)
+#define CHIP_IS_57712E(bp)             (CHIP_NUM(bp) == CHIP_NUM_57712E)
+#define CHIP_IS_57713(bp)              (CHIP_NUM(bp) == CHIP_NUM_57713)
+#define CHIP_IS_57713E(bp)             (CHIP_NUM(bp) == CHIP_NUM_57713E)
+#define CHIP_IS_E1H(bp)                        (CHIP_IS_57711(bp) || \
+                                        CHIP_IS_57711E(bp))
+#define IS_E1H_OFFSET                  CHIP_IS_E1H(bp)
+#define CHIP_IS_E2(bp)                 (CHIP_IS_57712(bp) || \
+                                        CHIP_IS_57712E(bp) || \
+                                        CHIP_IS_57713(bp) || \
+                                        CHIP_IS_57713E(bp))
+
+#define CHIP_REV(bp)                   (bp->common.chip_id & 0x0000f000)
+#define CHIP_REV_Ax                    0x00000000
+/* assume maximum 5 revisions */
+#define CHIP_REV_IS_SLOW(bp)           (CHIP_REV(bp) > 0x00005000)
+/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
+#define CHIP_REV_IS_EMUL(bp)           ((CHIP_REV_IS_SLOW(bp)) && \
+                                        !(CHIP_REV(bp) & 0x00001000))
+/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
+#define CHIP_REV_IS_FPGA(bp)           ((CHIP_REV_IS_SLOW(bp)) && \
+                                        (CHIP_REV(bp) & 0x00001000))
+
+#define CHIP_TIME(bp)                  ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
+                                       ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
+
+#define CHIP_METAL(bp)                 (bp->common.chip_id & 0x00000ff0)
+#define CHIP_BOND_ID(bp)               (bp->common.chip_id & 0x0000000f)
+
+       int                     flash_size;
+#define NVRAM_1MB_SIZE                 0x20000 /* 1M bit in bytes */
+#define NVRAM_TIMEOUT_COUNT            30000
+#define NVRAM_PAGE_SIZE                        256
+
+       u32                     shmem_base;
+       u32                     shmem2_base;
+
+       u32                     hw_config;
+
+       u32                     bc_ver;
+};
+
+
+/* end of common */
+
+/* port */
+
+struct nig_stats {
+       u32 brb_discard;
+       u32 brb_packet;
+       u32 brb_truncate;
+       u32 flow_ctrl_discard;
+       u32 flow_ctrl_octets;
+       u32 flow_ctrl_packet;
+       u32 mng_discard;
+       u32 mng_octet_inp;
+       u32 mng_octet_out;
+       u32 mng_packet_inp;
+       u32 mng_packet_out;
+       u32 pbf_octets;
+       u32 pbf_packet;
+       u32 safc_inp;
+       u32 egress_mac_pkt0_lo;
+       u32 egress_mac_pkt0_hi;
+       u32 egress_mac_pkt1_lo;
+       u32 egress_mac_pkt1_hi;
+};
+
+struct bnx2x_port {
+       u32                     pmf;
+
+       u32                     link_config;
+
+       u32                     supported;
+/* link settings - missing defines */
+#define SUPPORTED_2500baseX_Full       (1 << 15)
+
+       u32                     advertising;
+/* link settings - missing defines */
+#define ADVERTISED_2500baseX_Full      (1 << 15)
+
+       u32                     phy_addr;
+
+       /* used to synchronize phy accesses */
+       struct mutex            phy_mutex;
+       int                     need_hw_lock;
+
+       u32                     port_stx;
+
+       struct nig_stats        old_nig_stats;
+};
+
+/* end of port */
+
+
+enum bnx2x_stats_event {
+       STATS_EVENT_PMF = 0,
+       STATS_EVENT_LINK_UP,
+       STATS_EVENT_UPDATE,
+       STATS_EVENT_STOP,
+       STATS_EVENT_MAX
+};
+
+enum bnx2x_stats_state {
+       STATS_STATE_DISABLED = 0,
+       STATS_STATE_ENABLED,
+       STATS_STATE_MAX
+};
+
+struct bnx2x_eth_stats {
+       u32 total_bytes_received_hi;
+       u32 total_bytes_received_lo;
+       u32 total_bytes_transmitted_hi;
+       u32 total_bytes_transmitted_lo;
+       u32 total_unicast_packets_received_hi;
+       u32 total_unicast_packets_received_lo;
+       u32 total_multicast_packets_received_hi;
+       u32 total_multicast_packets_received_lo;
+       u32 total_broadcast_packets_received_hi;
+       u32 total_broadcast_packets_received_lo;
+       u32 total_unicast_packets_transmitted_hi;
+       u32 total_unicast_packets_transmitted_lo;
+       u32 total_multicast_packets_transmitted_hi;
+       u32 total_multicast_packets_transmitted_lo;
+       u32 total_broadcast_packets_transmitted_hi;
+       u32 total_broadcast_packets_transmitted_lo;
+       u32 valid_bytes_received_hi;
+       u32 valid_bytes_received_lo;
+
+       u32 error_bytes_received_hi;
+       u32 error_bytes_received_lo;
+       u32 etherstatsoverrsizepkts_hi;
+       u32 etherstatsoverrsizepkts_lo;
+       u32 no_buff_discard_hi;
+       u32 no_buff_discard_lo;
+
+       u32 rx_stat_ifhcinbadoctets_hi;
+       u32 rx_stat_ifhcinbadoctets_lo;
+       u32 tx_stat_ifhcoutbadoctets_hi;
+       u32 tx_stat_ifhcoutbadoctets_lo;
+       u32 rx_stat_dot3statsfcserrors_hi;
+       u32 rx_stat_dot3statsfcserrors_lo;
+       u32 rx_stat_dot3statsalignmenterrors_hi;
+       u32 rx_stat_dot3statsalignmenterrors_lo;
+       u32 rx_stat_dot3statscarriersenseerrors_hi;
+       u32 rx_stat_dot3statscarriersenseerrors_lo;
+       u32 rx_stat_falsecarriererrors_hi;
+       u32 rx_stat_falsecarriererrors_lo;
+       u32 rx_stat_etherstatsundersizepkts_hi;
+       u32 rx_stat_etherstatsundersizepkts_lo;
+       u32 rx_stat_dot3statsframestoolong_hi;
+       u32 rx_stat_dot3statsframestoolong_lo;
+       u32 rx_stat_etherstatsfragments_hi;
+       u32 rx_stat_etherstatsfragments_lo;
+       u32 rx_stat_etherstatsjabbers_hi;
+       u32 rx_stat_etherstatsjabbers_lo;
+       u32 rx_stat_maccontrolframesreceived_hi;
+       u32 rx_stat_maccontrolframesreceived_lo;
+       u32 rx_stat_bmac_xpf_hi;
+       u32 rx_stat_bmac_xpf_lo;
+       u32 rx_stat_bmac_xcf_hi;
+       u32 rx_stat_bmac_xcf_lo;
+       u32 rx_stat_xoffstateentered_hi;
+       u32 rx_stat_xoffstateentered_lo;
+       u32 rx_stat_xonpauseframesreceived_hi;
+       u32 rx_stat_xonpauseframesreceived_lo;
+       u32 rx_stat_xoffpauseframesreceived_hi;
+       u32 rx_stat_xoffpauseframesreceived_lo;
+       u32 tx_stat_outxonsent_hi;
+       u32 tx_stat_outxonsent_lo;
+       u32 tx_stat_outxoffsent_hi;
+       u32 tx_stat_outxoffsent_lo;
+       u32 tx_stat_flowcontroldone_hi;
+       u32 tx_stat_flowcontroldone_lo;
+       u32 tx_stat_etherstatscollisions_hi;
+       u32 tx_stat_etherstatscollisions_lo;
+       u32 tx_stat_dot3statssinglecollisionframes_hi;
+       u32 tx_stat_dot3statssinglecollisionframes_lo;
+       u32 tx_stat_dot3statsmultiplecollisionframes_hi;
+       u32 tx_stat_dot3statsmultiplecollisionframes_lo;
+       u32 tx_stat_dot3statsdeferredtransmissions_hi;
+       u32 tx_stat_dot3statsdeferredtransmissions_lo;
+       u32 tx_stat_dot3statsexcessivecollisions_hi;
+       u32 tx_stat_dot3statsexcessivecollisions_lo;
+       u32 tx_stat_dot3statslatecollisions_hi;
+       u32 tx_stat_dot3statslatecollisions_lo;
+       u32 tx_stat_etherstatspkts64octets_hi;
+       u32 tx_stat_etherstatspkts64octets_lo;
+       u32 tx_stat_etherstatspkts65octetsto127octets_hi;
+       u32 tx_stat_etherstatspkts65octetsto127octets_lo;
+       u32 tx_stat_etherstatspkts128octetsto255octets_hi;
+       u32 tx_stat_etherstatspkts128octetsto255octets_lo;
+       u32 tx_stat_etherstatspkts256octetsto511octets_hi;
+       u32 tx_stat_etherstatspkts256octetsto511octets_lo;
+       u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
+       u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
+       u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
+       u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
+       u32 tx_stat_etherstatspktsover1522octets_hi;
+       u32 tx_stat_etherstatspktsover1522octets_lo;
+       u32 tx_stat_bmac_2047_hi;
+       u32 tx_stat_bmac_2047_lo;
+       u32 tx_stat_bmac_4095_hi;
+       u32 tx_stat_bmac_4095_lo;
+       u32 tx_stat_bmac_9216_hi;
+       u32 tx_stat_bmac_9216_lo;
+       u32 tx_stat_bmac_16383_hi;
+       u32 tx_stat_bmac_16383_lo;
+       u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
+       u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
+       u32 tx_stat_bmac_ufl_hi;
+       u32 tx_stat_bmac_ufl_lo;
+
+       u32 pause_frames_received_hi;
+       u32 pause_frames_received_lo;
+       u32 pause_frames_sent_hi;
+       u32 pause_frames_sent_lo;
+
+       u32 etherstatspkts1024octetsto1522octets_hi;
+       u32 etherstatspkts1024octetsto1522octets_lo;
+       u32 etherstatspktsover1522octets_hi;
+       u32 etherstatspktsover1522octets_lo;
+
+       u32 brb_drop_hi;
+       u32 brb_drop_lo;
+       u32 brb_truncate_hi;
+       u32 brb_truncate_lo;
+
+       u32 mac_filter_discard;
+       u32 xxoverflow_discard;
+       u32 brb_truncate_discard;
+       u32 mac_discard;
+
+       u32 driver_xoff;
+       u32 rx_err_discard_pkt;
+       u32 rx_skb_alloc_failed;
+       u32 hw_csum_err;
+
+       u32 nig_timer_max;
+};
+
+#define BNX2X_NUM_STATS                        41
+#define STATS_OFFSET32(stat_name) \
+                       (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
+
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+#ifdef BCM_CNIC
+#define MAX_CONTEXT                    15
+#else /* BNX2X_UPSTREAM */
+#define MAX_CONTEXT                    16
+#endif
+#else
+#define MAX_CONTEXT                    2
+#endif
+
+union cdu_context {
+       struct eth_context eth;
+       char pad[1024];
+};
+
+#define MAX_DMAE_C                     8
+
+/* DMA memory not used in fastpath */
+struct bnx2x_slowpath {
+       union cdu_context               context[MAX_CONTEXT];
+       struct eth_stats_query          fw_stats;
+       struct mac_configuration_cmd    mac_config;
+       struct mac_configuration_cmd    mcast_config;
+
+       /* used by dmae command executer */
+       struct dmae_command             dmae[MAX_DMAE_C];
+
+       u32                             stats_comp;
+       union mac_stats                 mac_stats;
+       struct nig_stats                nig_stats;
+       struct host_port_stats          port_stats;
+       struct host_func_stats          func_stats;
+       struct host_func_stats          func_stats_base;
+
+       u32                             wb_comp;
+       u32                             wb_data[4];
+};
+
+#define bnx2x_sp(bp, var)              (&bp->slowpath->var)
+#define bnx2x_sp_mapping(bp, var) \
+               (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
+
+
+/* attn group wiring */
+#define MAX_DYNAMIC_ATTN_GRPS          8
+
+struct attn_route {
+       u32     sig[4];
+};
+
+struct bnx2x {
+       /* Fields used in the tx and intr/napi performance paths
+        * are grouped together in the beginning of the structure
+        */
+       struct bnx2x_fastpath   fp[MAX_CONTEXT];
+       void __iomem            *regview;
+       void __iomem            *doorbells;
+#define BNX2X_DB_SIZE          (16*BCM_PAGE_SIZE)
+
+       struct net_device       *dev;
+       struct pci_dev          *pdev;
+
+       atomic_t                intr_sem;
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+#ifdef BCM_CNIC
+       struct msix_entry       msix_table[MAX_CONTEXT+2];
+#else /* BNX2X_UPSTREAM */
+       struct msix_entry       msix_table[MAX_CONTEXT+1];
+#endif
+#endif
+#define INT_MODE_INTx                  1
+#define INT_MODE_MSI                   2
+#define INT_MODE_MSIX                  3
+
+       int                     tx_ring_size;
+
+#ifdef BCM_VLAN
+       struct vlan_group       *vlgrp;
+#endif
+
+       u32                     rx_csum;
+       u32                     rx_buf_size;
+#define ETH_OVREHEAD                   (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
+#define ETH_MIN_PACKET_SIZE            60
+#define ETH_MAX_PACKET_SIZE            1500
+#define ETH_MAX_JUMBO_PACKET_SIZE      9600
+
+       /* Max supported alignment is 256 (8 shift) */
+#define BNX2X_RX_ALIGN_SHIFT           ((L1_CACHE_SHIFT < 8) ? \
+                                        L1_CACHE_SHIFT : 8)
+#define BNX2X_RX_ALIGN                 (1 << BNX2X_RX_ALIGN_SHIFT)
+
+       struct host_def_status_block *def_status_blk;
+#define DEF_SB_ID                      16
+       __le16                  def_c_idx;
+       __le16                  def_u_idx;
+       __le16                  def_x_idx;
+       __le16                  def_t_idx;
+       __le16                  def_att_idx;
+       u32                     attn_state;
+       struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
+
+       /* slow path ring */
+       struct eth_spe          *spq;
+       dma_addr_t              spq_mapping;
+       u16                     spq_prod_idx;
+       struct eth_spe          *spq_prod_bd;
+       struct eth_spe          *spq_last_bd;
+       __le16                  *dsb_sp_prod;
+       u16                     spq_left; /* serialize spq */
+       /* used to synchronize spq accesses */
+       spinlock_t              spq_lock;
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+       /* n queues allocated */
+       u16                     n_rx_queues_allocated;
+       u16                     n_tx_queues_allocated;
+       u8                      netq_enabled;
+#endif
+
+       /* Flags for marking that there is a STAT_QUERY or
+          SET_MAC ramrod pending */
+       u8                      stats_pending;
+       u8                      set_mac_pending;
+
+       /* End of fields used in the performance code paths */
+
+       int                     panic;
+       int                     msglevel;
+
+       u32                     flags;
+#define PCIX_FLAG                      1
+#define PCI_32BIT_FLAG                 2
+#define ONE_PORT_FLAG                  4
+#define NO_WOL_FLAG                    8
+#define USING_DAC_FLAG                 0x10
+#define USING_MSIX_FLAG                        0x20
+#define USING_MSI_FLAG                 0x40
+#define TPA_ENABLE_FLAG                        0x80
+#define NO_MCP_FLAG                    0x100
+#define BP_NOMCP(bp)                   (bp->flags & NO_MCP_FLAG)
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+#define SAFC_TX_FLAG                   0x200
+#endif
+#define HW_VLAN_TX_FLAG                        0x400
+#define HW_VLAN_RX_FLAG                        0x800
+
+       int                     func;
+#define BP_PORT(bp)                    (bp->func % PORT_MAX)
+#define BP_FUNC(bp)                    (bp->func)
+#define BP_E1HVN(bp)                   (bp->func >> 1)
+#define BP_L_ID(bp)                    (BP_E1HVN(bp) << 2)
+
+       int                     pm_cap;
+       int                     pcie_cap;
+       int                     mrrs;
+
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       struct delayed_work     sp_task;
+#else
+       struct work_struct      sp_task;
+#endif
+       struct work_struct      reset_task;
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       u16                     sp_running;
+#endif
+
+       struct timer_list       timer;
+       int                     current_interval;
+
+       u16                     fw_seq;
+       u16                     fw_drv_pulse_wr_seq;
+       u32                     func_stx;
+
+       struct link_params      link_params;
+       struct link_vars        link_vars;
+       struct mdio_if_info     mdio;
+
+       struct bnx2x_common     common;
+       struct bnx2x_port       port;
+
+       struct cmng_struct_per_port cmng;
+       u32                     vn_weight_sum;
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       u32                     cos_weight_sum;
+#endif
+
+       u32                     mf_config;
+       u16                     e1hov;
+       u8                      e1hmf;
+#define IS_E1HMF(bp)                   (bp->e1hmf != 0)
+
+       u8                      wol;
+
+       int                     rx_ring_size;
+
+       u16                     tx_quick_cons_trip_int;
+       u16                     tx_quick_cons_trip;
+       u16                     tx_ticks_int;
+       u16                     tx_ticks;
+
+       u16                     rx_quick_cons_trip_int;
+       u16                     rx_quick_cons_trip;
+       u16                     rx_ticks_int;
+       u16                     rx_ticks;
+
+       u32                     lin_cnt;
+
+       int                     state;
+#define BNX2X_STATE_CLOSED             0
+#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
+#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
+#define BNX2X_STATE_OPEN               0x3000
+#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
+#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
+#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
+#define BNX2X_STATE_DISABLED           0xd000
+#define BNX2X_STATE_DIAG               0xe000
+#define BNX2X_STATE_ERROR              0xf000
+
+       int                     multi_mode;
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+#define BNX2X_MAX_PRIORITY             8
+#define BNX2X_MAX_ENTRIES_PER_PRI      16
+#define BNX2X_MAX_COS                  3
+#define BNX2X_MAX_TX_COS               2
+       /* priority to cos mapping */
+       u8                      pri_map[BNX2X_MAX_PRIORITY];
+       /* number of queues per cos */
+       u8                      qs_per_cos[BNX2X_MAX_COS];
+       /* min rate per cos */
+       u16                     cos_min_rate[BNX2X_MAX_COS];
+       /* cos to queue mapping */
+       u8                      cos_map[BNX2X_MAX_COS];
+#endif
+       int                     num_rx_queues;
+       int                     num_tx_queues;
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+#define BNX2X_COS_QUEUES(cos)  ((qs_per_cos & (0xff << cos*8)) >> cos*8)
+#define BNX2X_COS_RATE(cos)    ((cos_min_rate & (0xff << cos*8)) >> cos*8)
+#endif
+
+       u32                     rx_mode;
+#define BNX2X_RX_MODE_NONE             0
+#define BNX2X_RX_MODE_NORMAL           1
+#define BNX2X_RX_MODE_ALLMULTI         2
+#define BNX2X_RX_MODE_PROMISC          3
+#define BNX2X_MAX_MULTICAST            64
+#define BNX2X_MAX_EMUL_MULTI           16
+
+       dma_addr_t              def_status_blk_mapping;
+
+       struct bnx2x_slowpath   *slowpath;
+       dma_addr_t              slowpath_mapping;
+
+       int                     dropless_fc;
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       void                    *t1;
+       dma_addr_t              t1_mapping;
+       void                    *t2;
+       dma_addr_t              t2_mapping;
+       void                    *timers;
+       dma_addr_t              timers_mapping;
+       void                    *qm;
+       dma_addr_t              qm_mapping;
+       struct cnic_ops         *cnic_ops;
+       void                    *cnic_data;
+       u32                     cnic_tag;
+       struct cnic_eth_dev     cnic_eth_dev;
+       struct host_status_block *cnic_sb;
+       dma_addr_t              cnic_sb_mapping;
+#define CNIC_SB_ID(bp)                 BP_L_ID(bp)
+       struct eth_spe          *cnic_kwq;
+       struct eth_spe          *cnic_kwq_prod;
+       struct eth_spe          *cnic_kwq_cons;
+       struct eth_spe          *cnic_kwq_last;
+       u16                     cnic_kwq_pending;
+       u16                     cnic_spq_pending;
+#endif
+
+       int                     dmae_ready;
+       /* used to synchronize dmae accesses */
+       struct mutex            dmae_mutex;
+
+       /* used to synchronize stats collecting */
+       int                     stats_state;
+       /* used by dmae command loader */
+       struct dmae_command     stats_dmae;
+       int                     executer_idx;
+
+       u16                     stats_counter;
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       struct net_device_stats net_stats;
+#endif
+       struct bnx2x_eth_stats  eth_stats;
+
+       struct z_stream_s       *strm;
+       void                    *gunzip_buf;
+       dma_addr_t              gunzip_mapping;
+       int                     gunzip_outlen;
+#define FW_BUF_SIZE                    0x8000
+#define GUNZIP_BUF(bp)                 bp->gunzip_buf
+#define GUNZIP_PHYS(bp)                        bp->gunzip_mapping
+#define GUNZIP_OUTLEN(bp)              bp->gunzip_outlen
+
+#if (LINUX_VERSION_CODE < 0x02060b) /* ! BNX2X_UPSTREAM */
+       u32                     pci_state[16];
+#endif
+       struct raw_op           *init_ops;
+       /* Init blocks offsets inside init_ops */
+       u16                     *init_ops_offsets;
+       /* Data blob - has 32 bit granularity */
+       u32                     *init_data;
+       /* Zipped PRAM blobs - raw data */
+       const u8                *tsem_int_table_data;
+       const u8                *tsem_pram_data;
+       const u8                *usem_int_table_data;
+       const u8                *usem_pram_data;
+       const u8                *xsem_int_table_data;
+       const u8                *xsem_pram_data;
+       const u8                *csem_int_table_data;
+       const u8                *csem_pram_data;
+#define INIT_OPS(bp)                   bp->init_ops
+#define INIT_OPS_OFFSETS(bp)           bp->init_ops_offsets
+#define INIT_DATA(bp)                  bp->init_data
+#define INIT_TSEM_INT_TABLE_DATA(bp)   bp->tsem_int_table_data
+#define INIT_TSEM_PRAM_DATA(bp)                bp->tsem_pram_data
+#define INIT_USEM_INT_TABLE_DATA(bp)   bp->usem_int_table_data
+#define INIT_USEM_PRAM_DATA(bp)                bp->usem_pram_data
+#define INIT_XSEM_INT_TABLE_DATA(bp)   bp->xsem_int_table_data
+#define INIT_XSEM_PRAM_DATA(bp)                bp->xsem_pram_data
+#define INIT_CSEM_INT_TABLE_DATA(bp)   bp->csem_int_table_data
+#define INIT_CSEM_PRAM_DATA(bp)                bp->csem_pram_data
+
+#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */
+       const struct firmware   *firmware;
+#endif
+};
+
+
+#define BNX2X_MAX_QUEUES(bp)   (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
+                                             : (MAX_CONTEXT/2))
+#define BNX2X_NUM_QUEUES(bp)   (bp->num_rx_queues + bp->num_tx_queues)
+#define is_multi(bp)           (BNX2X_NUM_QUEUES(bp) > 2)
+
+#define for_each_rx_queue(bp, var) \
+                       for (var = 0; var < bp->num_rx_queues; var++)
+#define for_each_tx_queue(bp, var) \
+                       for (var = bp->num_rx_queues; \
+                            var < BNX2X_NUM_QUEUES(bp); var++)
+#define for_each_queue(bp, var) \
+                       for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
+#define for_each_nondefault_queue(bp, var) \
+                       for (var = 1; var < bp->num_rx_queues; var++)
+
+
+void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
+void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
+                     u32 len32);
+int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
+int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
+u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
+void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
+void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
+                              u32 addr, u32 len);
+
+static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
+                          int wait)
+{
+       u32 val;
+
+       do {
+               val = REG_RD(bp, reg);
+               if (val == expected)
+                       break;
+               ms -= wait;
+               msleep(wait);
+
+       } while (ms > 0);
+
+       return val;
+}
+
+
+/* load/unload mode */
+#define LOAD_NORMAL                    0
+#define LOAD_OPEN                      1
+#define LOAD_DIAG                      2
+#define UNLOAD_NORMAL                  0
+#define UNLOAD_CLOSE                   1
+
+
+/* DMAE command defines */
+#define DMAE_CMD_SRC_PCI               0
+#define DMAE_CMD_SRC_GRC               DMAE_COMMAND_SRC
+
+#define DMAE_CMD_DST_PCI               (1 << DMAE_COMMAND_DST_SHIFT)
+#define DMAE_CMD_DST_GRC               (2 << DMAE_COMMAND_DST_SHIFT)
+
+#define DMAE_CMD_C_DST_PCI             0
+#define DMAE_CMD_C_DST_GRC             (1 << DMAE_COMMAND_C_DST_SHIFT)
+
+#define DMAE_CMD_C_ENABLE              DMAE_COMMAND_C_TYPE_ENABLE
+
+#define DMAE_CMD_ENDIANITY_NO_SWAP     (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_B_SWAP      (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_DW_SWAP     (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_B_DW_SWAP   (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
+
+#define DMAE_CMD_PORT_0                        0
+#define DMAE_CMD_PORT_1                        DMAE_COMMAND_PORT
+
+#define DMAE_CMD_SRC_RESET             DMAE_COMMAND_SRC_RESET
+#define DMAE_CMD_DST_RESET             DMAE_COMMAND_DST_RESET
+#define DMAE_CMD_E1HVN_SHIFT           DMAE_COMMAND_E1HVN_SHIFT
+
+#define DMAE_LEN32_RD_MAX              0x80
+#define DMAE_LEN32_WR_MAX              0x400
+
+#define DMAE_COMP_VAL                  0xe0d0d0ae
+
+#define MAX_DMAE_C_PER_PORT            8
+#define INIT_DMAE_C(bp)                        (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
+                                        BP_E1HVN(bp))
+#define PMF_DMAE_C(bp)                 (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
+                                        E1HVN_MAX)
+
+
+/* PCIE link and speed */
+#define PCICFG_LINK_WIDTH              0x1f00000
+#define PCICFG_LINK_WIDTH_SHIFT                20
+#define PCICFG_LINK_SPEED              0xf0000
+#define PCICFG_LINK_SPEED_SHIFT                16
+
+
+#define BNX2X_NUM_TESTS                        7
+
+#define BNX2X_PHY_LOOPBACK             0
+#define BNX2X_MAC_LOOPBACK             1
+#define BNX2X_PHY_LOOPBACK_FAILED      1
+#define BNX2X_MAC_LOOPBACK_FAILED      2
+#define BNX2X_LOOPBACK_FAILED          (BNX2X_MAC_LOOPBACK_FAILED | \
+                                        BNX2X_PHY_LOOPBACK_FAILED)
+
+
+#define STROM_ASSERT_ARRAY_SIZE                50
+
+
+/* must be used on a CID before placing it on a HW ring */
+#define HW_CID(bp, x)                  ((BP_PORT(bp) << 23) | \
+                                        (BP_E1HVN(bp) << 17) | (x))
+
+#define SP_DESC_CNT            (BCM_PAGE_SIZE / sizeof(struct eth_spe))
+#define MAX_SP_DESC_CNT                        (SP_DESC_CNT - 1)
+
+
+#define BNX2X_BTR                      3
+#define MAX_SPQ_PENDING                        8
+
+
+/* CMNG constants
+   derived from lab experiments, and not from system spec calculations !!! */
+#define DEF_MIN_RATE                   100
+/* resolution of the rate shaping timer - 100 usec */
+#define RS_PERIODIC_TIMEOUT_USEC       100
+/* resolution of fairness algorithm in usecs -
+   coefficient for calculating the actual t fair */
+#define T_FAIR_COEF                    10000000
+/* number of bytes in single QM arbitration cycle -
+   coefficient for calculating the fairness timer */
+#define QM_ARB_BYTES                   40000
+#define FAIR_MEM                       2
+
+
+#define ATTN_NIG_FOR_FUNC              (1L << 8)
+#define ATTN_SW_TIMER_4_FUNC           (1L << 9)
+#define GPIO_2_FUNC                    (1L << 10)
+#define GPIO_3_FUNC                    (1L << 11)
+#define GPIO_4_FUNC                    (1L << 12)
+#define ATTN_GENERAL_ATTN_1            (1L << 13)
+#define ATTN_GENERAL_ATTN_2            (1L << 14)
+#define ATTN_GENERAL_ATTN_3            (1L << 15)
+#define ATTN_GENERAL_ATTN_4            (1L << 13)
+#define ATTN_GENERAL_ATTN_5            (1L << 14)
+#define ATTN_GENERAL_ATTN_6            (1L << 15)
+
+#define ATTN_HARD_WIRED_MASK           0xff00
+#define ATTENTION_ID                   4
+
+
+/* stuff added to make the code fit 80Col */
+
+#define BNX2X_PMF_LINK_ASSERT \
+       GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
+
+#define BNX2X_MC_ASSERT_BITS \
+       (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+        GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+        GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+        GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
+
+#define BNX2X_MCP_ASSERT \
+       GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
+
+#define BNX2X_GRC_TIMEOUT      GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
+#define BNX2X_GRC_RSV          (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
+                                GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
+                                GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
+                                GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
+                                GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
+                                GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+
+#define HW_INTERRUT_ASSERT_SET_0 \
+                               (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_0   (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
+                                AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_1 \
+                               (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_1   (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
+                                AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
+                            AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+                                AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_2 \
+                               (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
+                                AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
+                       AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
+                                AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_2   (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
+                       AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
+                                AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
+                                AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+
+
+#define MULTI_FLAGS(bp) \
+               (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
+                TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
+                TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
+                TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
+                (bp->multi_mode << \
+                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
+#define MULTI_MASK                     0x7f
+
+
+#define DEF_USB_FUNC_OFF               (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
+#define DEF_CSB_FUNC_OFF               (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
+#define DEF_XSB_FUNC_OFF               (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
+#define DEF_TSB_FUNC_OFF               (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
+
+#define C_DEF_SB_SP_INDEX              HC_INDEX_DEF_C_ETH_SLOW_PATH
+
+#define BNX2X_SP_DSB_INDEX \
+(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
+
+
+#define CAM_IS_INVALID(x) \
+(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
+
+#define CAM_INVALIDATE(x) \
+       (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
+
+
+/* Number of u32 elements in MC hash array */
+#define MC_HASH_SIZE                   8
+#define MC_HASH_OFFSET(bp, i)          (BAR_TSTRORM_INTMEM + \
+       TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
+
+
+#ifndef PXP2_REG_PXP2_INT_STS
+#define PXP2_REG_PXP2_INT_STS          PXP2_REG_PXP2_INT_STS_0
+#endif
+
+/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
+
+#endif /* bnx2x.h */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_hsi.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_hsi.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_hsi.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_hsi.h      2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,3190 @@
+/* bnx2x_hsi.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+struct license_key {
+       u32 reserved[6];
+
+#if defined(__BIG_ENDIAN)
+       u16 max_iscsi_init_conn;
+       u16 max_iscsi_trgt_conn;
+#elif defined(__LITTLE_ENDIAN)
+       u16 max_iscsi_trgt_conn;
+       u16 max_iscsi_init_conn;
+#endif
+
+       u32 reserved_a[6];
+};
+
+
+#define PORT_0                         0
+#define PORT_1                         1
+#define PORT_MAX                       2
+
+/****************************************************************************
+ * Shared HW configuration                                                 *
+ ****************************************************************************/
+struct shared_hw_cfg {                                  /* NVRAM Offset */
+       /* Up to 16 bytes of NULL-terminated string */
+       u8  part_num[16];                                       /* 0x104 */
+
+       u32 config;                                             /* 0x114 */
+#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK            0x00000001
+#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT           0
+#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V            0x00000000
+#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V            0x00000001
+#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN       0x00000002
+
+#define SHARED_HW_CFG_PORT_SWAP                    0x00000004
+
+#define SHARED_HW_CFG_BEACON_WOL_EN                0x00000008
+
+#define SHARED_HW_CFG_MFW_SELECT_MASK              0x00000700
+#define SHARED_HW_CFG_MFW_SELECT_SHIFT             8
+       /* Whatever MFW found in NVM
+          (if multiple found, priority order is: NC-SI, UMP, IPMI) */
+#define SHARED_HW_CFG_MFW_SELECT_DEFAULT           0x00000000
+#define SHARED_HW_CFG_MFW_SELECT_NC_SI             0x00000100
+#define SHARED_HW_CFG_MFW_SELECT_UMP               0x00000200
+#define SHARED_HW_CFG_MFW_SELECT_IPMI              0x00000300
+       /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
+         (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
+       /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
+         (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
+       /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
+         (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
+
+#define SHARED_HW_CFG_LED_MODE_MASK                0x000f0000
+#define SHARED_HW_CFG_LED_MODE_SHIFT               16
+#define SHARED_HW_CFG_LED_MAC1                     0x00000000
+#define SHARED_HW_CFG_LED_PHY1                     0x00010000
+#define SHARED_HW_CFG_LED_PHY2                     0x00020000
+#define SHARED_HW_CFG_LED_PHY3                     0x00030000
+#define SHARED_HW_CFG_LED_MAC2                     0x00040000
+#define SHARED_HW_CFG_LED_PHY4                     0x00050000
+#define SHARED_HW_CFG_LED_PHY5                     0x00060000
+#define SHARED_HW_CFG_LED_PHY6                     0x00070000
+#define SHARED_HW_CFG_LED_MAC3                     0x00080000
+#define SHARED_HW_CFG_LED_PHY7                     0x00090000
+#define SHARED_HW_CFG_LED_PHY9                     0x000a0000
+#define SHARED_HW_CFG_LED_PHY11                    0x000b0000
+#define SHARED_HW_CFG_LED_MAC4                     0x000c0000
+#define SHARED_HW_CFG_LED_PHY8                     0x000d0000
+
+#define SHARED_HW_CFG_AN_ENABLE_MASK               0x3f000000
+#define SHARED_HW_CFG_AN_ENABLE_SHIFT              24
+#define SHARED_HW_CFG_AN_ENABLE_CL37               0x01000000
+#define SHARED_HW_CFG_AN_ENABLE_CL73               0x02000000
+#define SHARED_HW_CFG_AN_ENABLE_BAM                0x04000000
+#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
+#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
+#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY         0x20000000
+
+       u32 config2;                                            /* 0x118 */
+       /* one time auto detect grace period (in sec) */
+#define SHARED_HW_CFG_GRACE_PERIOD_MASK            0x000000ff
+#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT           0
+
+#define SHARED_HW_CFG_PCIE_GEN2_ENABLED            0x00000100
+
+       /* The default value for the core clock is 250MHz and it is
+          achieved by setting the clock change to 4 */
+#define SHARED_HW_CFG_CLOCK_CHANGE_MASK            0x00000e00
+#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT           9
+
+#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ          0x00000000
+#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ          0x00001000
+
+#define SHARED_HW_CFG_HIDE_PORT1                   0x00002000
+
+#define SHARED_HW_CFG_WOL_CAPABLE_DISABLED         0x00000000
+#define SHARED_HW_CFG_WOL_CAPABLE_ENABLED          0x00004000
+
+       /* Output low when PERST is asserted */
+#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED   0x00000000
+#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED    0x00008000
+
+#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
+#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT   16
+#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW     0x00000000
+#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB     0x00010000 /*    0dB */
+#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB   0x00020000 /* -3.5dB */
+#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB   0x00030000 /* -6.0dB */
+
+       /*  The fan failure mechanism is usually related to the PHY type
+         since the power consumption of the board is determined by the PHY.
+         Currently, fan is required for most designs with SFX7101, BCM8727
+         and BCM8481. If a fan is not required for a board which uses one
+         of those PHYs, this field should be set to "Disabled". If a fan is
+         required for a different PHY type, this option should be set to
+         "Enabled".
+         The fan failure indication is expected on
+         SPIO5 */
+#define SHARED_HW_CFG_FAN_FAILURE_MASK                       0x00180000
+#define SHARED_HW_CFG_FAN_FAILURE_SHIFT                      19
+#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE                   0x00000000
+#define SHARED_HW_CFG_FAN_FAILURE_DISABLED                   0x00080000
+#define SHARED_HW_CFG_FAN_FAILURE_ENABLED                    0x00100000
+
+       /*  ASPM Power Management support */
+#define SHARED_HW_CFG_ASPM_SUPPORT_MASK                      0x00600000
+#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT                     21
+#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED            0x00000000
+#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED              0x00200000
+#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED               0x00400000
+#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED           0x00600000
+
+       /*  The value of PM_TL_IGNORE_REQS (bit0) in PCI register
+         tl_control_0 (register 0x2800) */
+#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED              0x00000000
+#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED               0x00800000
+
+
+       u32 power_dissipated;                                   /* 0x11c */
+#define SHARED_HW_CFG_POWER_DIS_CMN_MASK           0xff000000
+#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT          24
+
+#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK        0x00ff0000
+#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT       16
+#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE     0x00000000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT        0x00010000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT       0x00020000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT      0x00030000
+
+       u32 ump_nc_si_config;                                   /* 0x120 */
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK      0x00000003
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT     0
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC       0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY       0x00000001
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII       0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII      0x00000002
+
+#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK      0x00000f00
+#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT     8
+
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
+
+       u32 board;                                              /* 0x124 */
+#define SHARED_HW_CFG_BOARD_REV_MASK               0x00ff0000
+#define SHARED_HW_CFG_BOARD_REV_SHIFT              16
+
+#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK         0x0f000000
+#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT        24
+
+#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK         0xf0000000
+#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT        28
+
+       u32 reserved;                                           /* 0x128 */
+
+};
+
+
+/****************************************************************************
+ * Port HW configuration                                                   *
+ ****************************************************************************/
+struct port_hw_cfg {                       /* port 0: 0x12c  port 1: 0x2bc */
+
+       u32 pci_id;
+#define PORT_HW_CFG_PCI_VENDOR_ID_MASK             0xffff0000
+#define PORT_HW_CFG_PCI_DEVICE_ID_MASK             0x0000ffff
+
+       u32 pci_sub_id;
+#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK      0xffff0000
+#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK      0x0000ffff
+
+       u32 power_dissipated;
+#define PORT_HW_CFG_POWER_DIS_D3_MASK              0xff000000
+#define PORT_HW_CFG_POWER_DIS_D3_SHIFT             24
+#define PORT_HW_CFG_POWER_DIS_D2_MASK              0x00ff0000
+#define PORT_HW_CFG_POWER_DIS_D2_SHIFT             16
+#define PORT_HW_CFG_POWER_DIS_D1_MASK              0x0000ff00
+#define PORT_HW_CFG_POWER_DIS_D1_SHIFT             8
+#define PORT_HW_CFG_POWER_DIS_D0_MASK              0x000000ff
+#define PORT_HW_CFG_POWER_DIS_D0_SHIFT             0
+
+       u32 power_consumed;
+#define PORT_HW_CFG_POWER_CONS_D3_MASK             0xff000000
+#define PORT_HW_CFG_POWER_CONS_D3_SHIFT            24
+#define PORT_HW_CFG_POWER_CONS_D2_MASK             0x00ff0000
+#define PORT_HW_CFG_POWER_CONS_D2_SHIFT            16
+#define PORT_HW_CFG_POWER_CONS_D1_MASK             0x0000ff00
+#define PORT_HW_CFG_POWER_CONS_D1_SHIFT            8
+#define PORT_HW_CFG_POWER_CONS_D0_MASK             0x000000ff
+#define PORT_HW_CFG_POWER_CONS_D0_SHIFT            0
+
+       u32 mac_upper;
+#define PORT_HW_CFG_UPPERMAC_MASK                  0x0000ffff
+#define PORT_HW_CFG_UPPERMAC_SHIFT                 0
+       u32 mac_lower;
+
+       u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
+       u32 iscsi_mac_lower;
+
+       u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
+       u32 rdma_mac_lower;
+
+       u32 serdes_config;
+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT  0
+
+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT   16
+
+
+       u32 reserved0[16];                                      /* 0x158 */
+
+       /*  4 times 16 bits for all 4 lanes. In case external PHY is present
+         (not direct mode), those values will not take effect on the 4 XGXS
+         lanes. For some external PHYs (such as 8706 and 8726) the values
+         will be used to configure the external PHY \96 in those cases, not
+         all 4 values are needed. */
+       u16 xgxs_config_rx[4];                                  /* 0x198 */
+       u16 xgxs_config_tx[4];                                  /* 0x1A0 */
+
+       u32 reserved1[64];                                      /* 0x1A8 */
+
+       u32 lane_config;
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASK             0x0000ffff
+#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT            0
+#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK          0x000000ff
+#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT         0
+#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK          0x0000ff00
+#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT         8
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK      0x0000c000
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT     14
+       /* AN and forced */
+#define PORT_HW_CFG_LANE_SWAP_CFG_01230123         0x00001b1b
+       /* forced only */
+#define PORT_HW_CFG_LANE_SWAP_CFG_01233210         0x00001be4
+       /* forced only */
+#define PORT_HW_CFG_LANE_SWAP_CFG_31203120         0x0000d8d8
+       /* forced only */
+#define PORT_HW_CFG_LANE_SWAP_CFG_32103210         0x0000e4e4
+
+       u32 external_phy_config;
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK       0xff000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT      24
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT     0x00000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
+
+#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK       0x00ff0000
+#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT      16
+
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK         0x0000ff00
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT        8
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT       0x00000000
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071      0x00000100
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072      0x00000200
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073      0x00000300
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705      0x00000400
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706      0x00000500
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726      0x00000600
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481      0x00000700
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101      0x00000800
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727      0x00000900
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC   0x00000a00
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE      0x0000fd00
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN     0x0000ff00
+
+#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK         0x000000ff
+#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT        0
+
+       u32 speed_capability_mask;
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK       0xffff0000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT      16
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G         0x00100000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G       0x00200000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G        0x00400000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G        0x00800000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G      0x01000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G        0x02000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G        0x04000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G        0x08000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
+
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK       0x0000ffff
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT      0
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G         0x00000010
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G       0x00000020
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G        0x00000040
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G        0x00000080
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G      0x00000100
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G        0x00000200
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G        0x00000400
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G        0x00000800
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
+
+       /*  A place to hold the original MAC address as a backup */
+       u32 backup_mac_upper;                                   /* 0x2B4 */
+       u32 backup_mac_lower;                                   /* 0x2B8 */
+
+};
+
+
+/****************************************************************************
+ * Shared Feature configuration                                            *
+ ****************************************************************************/
+struct shared_feat_cfg {                                /* NVRAM Offset */
+
+       u32 config;                                             /* 0x450 */
+#define SHARED_FEATURE_BMC_ECHO_MODE_EN            0x00000001
+
+       /* Use NVRAM values instead of HW default values */
+#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
+#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED  0x00000002
+
+#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO        0x00000000
+#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM       0x00000008
+
+#define SHARED_FEAT_CFG_NCSI_ID_MASK               0x00000030
+#define SHARED_FEAT_CFG_NCSI_ID_SHIFT              4
+
+       /* Override the OTP back to single function mode. When using GPIO,
+          high means only SF, 0 is according to CLP configuration */
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK         0x00000700
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT        8
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED    0x00000000
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF     0x00000100
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4        0x00000200
+
+};
+
+
+/****************************************************************************
+ * Port Feature configuration                                              *
+ ****************************************************************************/
+struct port_feat_cfg {                     /* port 0: 0x454  port 1: 0x4c8 */
+
+       u32 config;
+#define PORT_FEATURE_BAR1_SIZE_MASK                0x0000000f
+#define PORT_FEATURE_BAR1_SIZE_SHIFT               0
+#define PORT_FEATURE_BAR1_SIZE_DISABLED            0x00000000
+#define PORT_FEATURE_BAR1_SIZE_64K                 0x00000001
+#define PORT_FEATURE_BAR1_SIZE_128K                0x00000002
+#define PORT_FEATURE_BAR1_SIZE_256K                0x00000003
+#define PORT_FEATURE_BAR1_SIZE_512K                0x00000004
+#define PORT_FEATURE_BAR1_SIZE_1M                  0x00000005
+#define PORT_FEATURE_BAR1_SIZE_2M                  0x00000006
+#define PORT_FEATURE_BAR1_SIZE_4M                  0x00000007
+#define PORT_FEATURE_BAR1_SIZE_8M                  0x00000008
+#define PORT_FEATURE_BAR1_SIZE_16M                 0x00000009
+#define PORT_FEATURE_BAR1_SIZE_32M                 0x0000000a
+#define PORT_FEATURE_BAR1_SIZE_64M                 0x0000000b
+#define PORT_FEATURE_BAR1_SIZE_128M                0x0000000c
+#define PORT_FEATURE_BAR1_SIZE_256M                0x0000000d
+#define PORT_FEATURE_BAR1_SIZE_512M                0x0000000e
+#define PORT_FEATURE_BAR1_SIZE_1G                  0x0000000f
+#define PORT_FEATURE_BAR2_SIZE_MASK                0x000000f0
+#define PORT_FEATURE_BAR2_SIZE_SHIFT               4
+#define PORT_FEATURE_BAR2_SIZE_DISABLED            0x00000000
+#define PORT_FEATURE_BAR2_SIZE_64K                 0x00000010
+#define PORT_FEATURE_BAR2_SIZE_128K                0x00000020
+#define PORT_FEATURE_BAR2_SIZE_256K                0x00000030
+#define PORT_FEATURE_BAR2_SIZE_512K                0x00000040
+#define PORT_FEATURE_BAR2_SIZE_1M                  0x00000050
+#define PORT_FEATURE_BAR2_SIZE_2M                  0x00000060
+#define PORT_FEATURE_BAR2_SIZE_4M                  0x00000070
+#define PORT_FEATURE_BAR2_SIZE_8M                  0x00000080
+#define PORT_FEATURE_BAR2_SIZE_16M                 0x00000090
+#define PORT_FEATURE_BAR2_SIZE_32M                 0x000000a0
+#define PORT_FEATURE_BAR2_SIZE_64M                 0x000000b0
+#define PORT_FEATURE_BAR2_SIZE_128M                0x000000c0
+#define PORT_FEATURE_BAR2_SIZE_256M                0x000000d0
+#define PORT_FEATURE_BAR2_SIZE_512M                0x000000e0
+#define PORT_FEATURE_BAR2_SIZE_1G                  0x000000f0
+#define PORT_FEATURE_EN_SIZE_MASK                  0x07000000
+#define PORT_FEATURE_EN_SIZE_SHIFT                 24
+#define PORT_FEATURE_WOL_ENABLED                   0x01000000
+#define PORT_FEATURE_MBA_ENABLED                   0x02000000
+#define PORT_FEATURE_MFW_ENABLED                   0x04000000
+
+       /*  Advertise expansion ROM even if MBA is disabled */
+#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED             0x00000000
+#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED              0x08000000
+
+       /* Reserved bits: 28-29 */
+       /*  Check the optic vendor via i2c against a list of approved modules
+         in a separate nvram image */
+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK                  0xE0000000
+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT                 29
+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT        0x00000000
+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER       0x20000000
+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG           0x40000000
+#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN            0x60000000
+
+
+       u32 wol_config;
+       /* Default is used when driver sets to "auto" mode */
+#define PORT_FEATURE_WOL_DEFAULT_MASK              0x00000003
+#define PORT_FEATURE_WOL_DEFAULT_SHIFT             0
+#define PORT_FEATURE_WOL_DEFAULT_DISABLE           0x00000000
+#define PORT_FEATURE_WOL_DEFAULT_MAGIC             0x00000001
+#define PORT_FEATURE_WOL_DEFAULT_ACPI              0x00000002
+#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
+#define PORT_FEATURE_WOL_RES_PAUSE_CAP             0x00000004
+#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP        0x00000008
+#define PORT_FEATURE_WOL_ACPI_UPON_MGMT            0x00000010
+
+       u32 mba_config;
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK      0x00000007
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT     0
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE       0x00000000
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL       0x00000001
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP     0x00000002
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE      0x00000007
+#define PORT_FEATURE_MBA_RES_PAUSE_CAP             0x00000100
+#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP        0x00000200
+#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE       0x00000400
+#define PORT_FEATURE_MBA_HOTKEY_CTRL_S             0x00000000
+#define PORT_FEATURE_MBA_HOTKEY_CTRL_B             0x00000800
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK         0x000ff000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT        12
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED     0x00000000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K           0x00001000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K           0x00002000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K           0x00003000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K          0x00004000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K          0x00005000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K          0x00006000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K         0x00007000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K         0x00008000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K         0x00009000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M           0x0000a000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M           0x0000b000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M           0x0000c000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M           0x0000d000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M          0x0000e000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M          0x0000f000
+#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK          0x00f00000
+#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT         20
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK       0x03000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT      24
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO       0x00000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS        0x01000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H     0x02000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H     0x03000000
+#define PORT_FEATURE_MBA_LINK_SPEED_MASK           0x3c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT          26
+#define PORT_FEATURE_MBA_LINK_SPEED_AUTO           0x00000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10HD           0x04000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10FD           0x08000000
+#define PORT_FEATURE_MBA_LINK_SPEED_100HD          0x0c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_100FD          0x10000000
+#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS          0x14000000
+#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS        0x18000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4     0x1c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4     0x20000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR      0x24000000
+#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS         0x28000000
+#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS       0x2c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS         0x30000000
+#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS         0x34000000
+#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS         0x38000000
+
+       u32 bmc_config;
+#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT     0x00000000
+#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN          0x00000001
+
+       u32 mba_vlan_cfg;
+#define PORT_FEATURE_MBA_VLAN_TAG_MASK             0x0000ffff
+#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT            0
+#define PORT_FEATURE_MBA_VLAN_EN                   0x00010000
+
+       u32 resource_cfg;
+#define PORT_FEATURE_RESOURCE_CFG_VALID            0x00000001
+#define PORT_FEATURE_RESOURCE_CFG_DIAG             0x00000002
+#define PORT_FEATURE_RESOURCE_CFG_L2               0x00000004
+#define PORT_FEATURE_RESOURCE_CFG_ISCSI            0x00000008
+#define PORT_FEATURE_RESOURCE_CFG_RDMA             0x00000010
+
+       u32 smbus_config;
+       /* Obsolete */
+#define PORT_FEATURE_SMBUS_EN                      0x00000001
+#define PORT_FEATURE_SMBUS_ADDR_MASK               0x000000fe
+#define PORT_FEATURE_SMBUS_ADDR_SHIFT              1
+
+       u32 reserved1;
+
+       u32 link_config;    /* Used as HW defaults for the driver */
+#define PORT_FEATURE_CONNECTED_SWITCH_MASK         0x03000000
+#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT        24
+       /* (forced) low speed switch (< 10G) */
+#define PORT_FEATURE_CON_SWITCH_1G_SWITCH          0x00000000
+       /* (forced) high speed switch (>= 10G) */
+#define PORT_FEATURE_CON_SWITCH_10G_SWITCH         0x01000000
+#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT        0x02000000
+#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
+
+#define PORT_FEATURE_LINK_SPEED_MASK               0x000f0000
+#define PORT_FEATURE_LINK_SPEED_SHIFT              16
+#define PORT_FEATURE_LINK_SPEED_AUTO               0x00000000
+#define PORT_FEATURE_LINK_SPEED_10M_FULL           0x00010000
+#define PORT_FEATURE_LINK_SPEED_10M_HALF           0x00020000
+#define PORT_FEATURE_LINK_SPEED_100M_HALF          0x00030000
+#define PORT_FEATURE_LINK_SPEED_100M_FULL          0x00040000
+#define PORT_FEATURE_LINK_SPEED_1G                 0x00050000
+#define PORT_FEATURE_LINK_SPEED_2_5G               0x00060000
+#define PORT_FEATURE_LINK_SPEED_10G_CX4            0x00070000
+#define PORT_FEATURE_LINK_SPEED_10G_KX4            0x00080000
+#define PORT_FEATURE_LINK_SPEED_10G_KR             0x00090000
+#define PORT_FEATURE_LINK_SPEED_12G                0x000a0000
+#define PORT_FEATURE_LINK_SPEED_12_5G              0x000b0000
+#define PORT_FEATURE_LINK_SPEED_13G                0x000c0000
+#define PORT_FEATURE_LINK_SPEED_15G                0x000d0000
+#define PORT_FEATURE_LINK_SPEED_16G                0x000e0000
+
+#define PORT_FEATURE_FLOW_CONTROL_MASK             0x00000700
+#define PORT_FEATURE_FLOW_CONTROL_SHIFT            8
+#define PORT_FEATURE_FLOW_CONTROL_AUTO             0x00000000
+#define PORT_FEATURE_FLOW_CONTROL_TX               0x00000100
+#define PORT_FEATURE_FLOW_CONTROL_RX               0x00000200
+#define PORT_FEATURE_FLOW_CONTROL_BOTH             0x00000300
+#define PORT_FEATURE_FLOW_CONTROL_NONE             0x00000400
+
+       /* The default for MCP link configuration,
+          uses the same defines as link_config */
+       u32 mfw_wol_link_cfg;
+
+       u32 reserved[19];
+
+};
+
+
+/****************************************************************************
+ * Device Information                                                      *
+ ****************************************************************************/
+struct shm_dev_info {                                              /* size */
+
+       u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
+
+       struct shared_hw_cfg     shared_hw_config;                    /* 40 */
+
+       struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
+
+       struct shared_feat_cfg   shared_feature_config;                /* 4 */
+
+       struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
+
+};
+
+
+#define FUNC_0                         0
+#define FUNC_1                         1
+#define FUNC_2                         2
+#define FUNC_3                         3
+#define FUNC_4                         4
+#define FUNC_5                         5
+#define FUNC_6                         6
+#define FUNC_7                         7
+#define E1_FUNC_MAX                    2
+#define E1H_FUNC_MAX                   8
+
+#define VN_0                           0
+#define VN_1                           1
+#define VN_2                           2
+#define VN_3                           3
+#define E1VN_MAX                       1
+#define E1HVN_MAX                      4
+
+
+/* This value (in milliseconds) determines the frequency of the driver
+ * issuing the PULSE message code.  The firmware monitors this periodic
+ * pulse to determine when to switch to an OS-absent mode. */
+#define DRV_PULSE_PERIOD_MS            250
+
+/* This value (in milliseconds) determines how long the driver should
+ * wait for an acknowledgement from the firmware before timing out.  Once
+ * the firmware has timed out, the driver will assume there is no firmware
+ * running and there won't be any firmware-driver synchronization during a
+ * driver reset. */
+#define FW_ACK_TIME_OUT_MS             5000
+
+#define FW_ACK_POLL_TIME_MS            1
+
+#define FW_ACK_NUM_OF_POLL     (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
+
+/* LED Blink rate that will achieve ~15.9Hz */
+#define LED_BLINK_RATE_VAL             480
+
+/****************************************************************************
+ * Driver <-> FW Mailbox                                                   *
+ ****************************************************************************/
+struct drv_port_mb {
+
+       u32 link_status;
+       /* Driver should update this field on any link change event */
+
+#define LINK_STATUS_LINK_FLAG_MASK                     0x00000001
+#define LINK_STATUS_LINK_UP                            0x00000001
+#define LINK_STATUS_SPEED_AND_DUPLEX_MASK              0x0000001E
+#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE   (0<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10THD             (1<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD             (2<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD           (3<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100T4             (4<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD           (5<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD           (6<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD           (7<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD           (7<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD           (8<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD           (9<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD           (9<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD            (10<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD            (10<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD            (11<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD            (11<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD          (12<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD          (12<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD            (13<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD            (13<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD            (14<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD            (14<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD            (15<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD            (15<<1)
+
+#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK           0x00000020
+#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED             0x00000020
+
+#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE            0x00000040
+#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK       0x00000080
+#define LINK_STATUS_PARALLEL_DETECTION_USED            0x00000080
+
+#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE       0x00000200
+#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE       0x00000400
+#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE         0x00000800
+#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE       0x00001000
+#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE       0x00002000
+#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE         0x00004000
+#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE         0x00008000
+
+#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK          0x00010000
+#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED            0x00010000
+
+#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK          0x00020000
+#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED            0x00020000
+
+#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK     0x000C0000
+#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE     (0<<18)
+#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE       (1<<18)
+#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE      (2<<18)
+#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE            (3<<18)
+
+#define LINK_STATUS_SERDES_LINK                        0x00100000
+
+#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE       0x00200000
+#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE       0x00400000
+#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE        0x00800000
+#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE        0x01000000
+#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE      0x02000000
+#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE        0x04000000
+#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE        0x08000000
+#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE        0x10000000
+
+       u32 port_stx;
+
+       u32 stat_nig_timer;
+
+       /* MCP firmware does not use this field */
+       u32 ext_phy_fw_version;
+
+};
+
+
+struct drv_func_mb {
+
+       u32 drv_mb_header;
+#define DRV_MSG_CODE_MASK                              0xffff0000
+#define DRV_MSG_CODE_LOAD_REQ                          0x10000000
+#define DRV_MSG_CODE_LOAD_DONE                         0x11000000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                 0x20000000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                0x20010000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                0x20020000
+#define DRV_MSG_CODE_UNLOAD_DONE                       0x21000000
+#define DRV_MSG_CODE_DCC_OK                            0x30000000
+#define DRV_MSG_CODE_DCC_FAILURE                       0x31000000
+#define DRV_MSG_CODE_DIAG_ENTER_REQ                    0x50000000
+#define DRV_MSG_CODE_DIAG_EXIT_REQ                     0x60000000
+#define DRV_MSG_CODE_VALIDATE_KEY                      0x70000000
+#define DRV_MSG_CODE_GET_CURR_KEY                      0x80000000
+#define DRV_MSG_CODE_GET_UPGRADE_KEY                   0x81000000
+#define DRV_MSG_CODE_GET_MANUF_KEY                     0x82000000
+#define DRV_MSG_CODE_LOAD_L2B_PRAM                     0x90000000
+       /*
+        * The optic module verification commands requris bootcode
+        * v5.0.6 or later
+        */
+#define DRV_MSG_CODE_VRFY_OPT_MDL                      0xa0000000
+#define REQ_BC_VER_4_VRFY_OPT_MDL                      0x00050006
+
+#define BIOS_MSG_CODE_LIC_CHALLENGE                    0xff010000
+#define BIOS_MSG_CODE_LIC_RESPONSE                     0xff020000
+#define BIOS_MSG_CODE_VIRT_MAC_PRIM                    0xff030000
+#define BIOS_MSG_CODE_VIRT_MAC_ISCSI                   0xff040000
+
+#define DRV_MSG_SEQ_NUMBER_MASK                        0x0000ffff
+
+       u32 drv_mb_param;
+
+       u32 fw_mb_header;
+#define FW_MSG_CODE_MASK                               0xffff0000
+#define FW_MSG_CODE_DRV_LOAD_COMMON                    0x10100000
+#define FW_MSG_CODE_DRV_LOAD_PORT                      0x10110000
+#define FW_MSG_CODE_DRV_LOAD_FUNCTION                  0x10120000
+#define FW_MSG_CODE_DRV_LOAD_REFUSED                   0x10200000
+#define FW_MSG_CODE_DRV_LOAD_DONE                      0x11100000
+#define FW_MSG_CODE_DRV_UNLOAD_COMMON                  0x20100000
+#define FW_MSG_CODE_DRV_UNLOAD_PORT                    0x20110000
+#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                0x20120000
+#define FW_MSG_CODE_DRV_UNLOAD_DONE                    0x21100000
+#define FW_MSG_CODE_DCC_DONE                           0x30100000
+#define FW_MSG_CODE_DIAG_ENTER_DONE                    0x50100000
+#define FW_MSG_CODE_DIAG_REFUSE                        0x50200000
+#define FW_MSG_CODE_DIAG_EXIT_DONE                     0x60100000
+#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS               0x70100000
+#define FW_MSG_CODE_VALIDATE_KEY_FAILURE               0x70200000
+#define FW_MSG_CODE_GET_KEY_DONE                       0x80100000
+#define FW_MSG_CODE_NO_KEY                             0x80f00000
+#define FW_MSG_CODE_LIC_INFO_NOT_READY                 0x80f80000
+#define FW_MSG_CODE_L2B_PRAM_LOADED                    0x90100000
+#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE            0x90210000
+#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE            0x90220000
+#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE            0x90230000
+#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE            0x90240000
+#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS               0xa0100000
+#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG             0xa0200000
+#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED            0xa0300000
+
+#define FW_MSG_CODE_LIC_CHALLENGE                      0xff010000
+#define FW_MSG_CODE_LIC_RESPONSE                       0xff020000
+#define FW_MSG_CODE_VIRT_MAC_PRIM                      0xff030000
+#define FW_MSG_CODE_VIRT_MAC_ISCSI                     0xff040000
+
+#define FW_MSG_SEQ_NUMBER_MASK                         0x0000ffff
+
+       u32 fw_mb_param;
+
+       u32 drv_pulse_mb;
+#define DRV_PULSE_SEQ_MASK                             0x00007fff
+#define DRV_PULSE_SYSTEM_TIME_MASK                     0xffff0000
+       /* The system time is in the format of
+        * (year-2001)*12*32 + month*32 + day. */
+#define DRV_PULSE_ALWAYS_ALIVE                         0x00008000
+       /* Indicate to the firmware not to go into the
+        * OS-absent when it is not getting driver pulse.
+        * This is used for debugging as well for PXE(MBA). */
+
+       u32 mcp_pulse_mb;
+#define MCP_PULSE_SEQ_MASK                             0x00007fff
+#define MCP_PULSE_ALWAYS_ALIVE                         0x00008000
+       /* Indicates to the driver not to assert due to lack
+        * of MCP response */
+#define MCP_EVENT_MASK                                 0xffff0000
+#define MCP_EVENT_OTHER_DRIVER_RESET_REQ               0x00010000
+
+       u32 iscsi_boot_signature;
+       u32 iscsi_boot_block_offset;
+
+       u32 drv_status;
+#define DRV_STATUS_PMF                                 0x00000001
+
+#define DRV_STATUS_DCC_EVENT_MASK                      0x0000ff00
+#define DRV_STATUS_DCC_DISABLE_ENABLE_PF               0x00000100
+#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION            0x00000200
+#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS              0x00000400
+#define DRV_STATUS_DCC_RESERVED1                       0x00000800
+#define DRV_STATUS_DCC_SET_PROTOCOL                    0x00001000
+#define DRV_STATUS_DCC_SET_PRIORITY                    0x00002000
+
+       u32 virt_mac_upper;
+#define VIRT_MAC_SIGN_MASK                             0xffff0000
+#define VIRT_MAC_SIGNATURE                             0x564d0000
+       u32 virt_mac_lower;
+
+};
+
+
+/****************************************************************************
+ * Management firmware state                                               *
+ ****************************************************************************/
+/* Allocate 440 bytes for management firmware */
+#define MGMTFW_STATE_WORD_SIZE                             110
+
+struct mgmtfw_state {
+       u32 opaque[MGMTFW_STATE_WORD_SIZE];
+};
+
+
+/****************************************************************************
+ * Multi-Function configuration                                            *
+ ****************************************************************************/
+struct shared_mf_cfg {
+
+       u32 clp_mb;
+#define SHARED_MF_CLP_SET_DEFAULT                  0x00000000
+       /* set by CLP */
+#define SHARED_MF_CLP_EXIT                         0x00000001
+       /* set by MCP */
+#define SHARED_MF_CLP_EXIT_DONE                    0x00010000
+
+};
+
+struct port_mf_cfg {
+
+       u32 dynamic_cfg;        /* device control channel */
+#define PORT_MF_CFG_E1HOV_TAG_MASK                 0x0000ffff
+#define PORT_MF_CFG_E1HOV_TAG_SHIFT                0
+#define PORT_MF_CFG_E1HOV_TAG_DEFAULT              PORT_MF_CFG_E1HOV_TAG_MASK
+
+       u32 reserved[3];
+
+};
+
+struct func_mf_cfg {
+
+       u32 config;
+       /* E/R/I/D */
+       /* function 0 of each port cannot be hidden */
+#define FUNC_MF_CFG_FUNC_HIDE                      0x00000001
+
+#define FUNC_MF_CFG_PROTOCOL_MASK                  0x00000007
+#define FUNC_MF_CFG_PROTOCOL_ETHERNET              0x00000002
+#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
+#define FUNC_MF_CFG_PROTOCOL_ISCSI                 0x00000006
+#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
+       FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
+
+#define FUNC_MF_CFG_FUNC_DISABLED                  0x00000008
+
+       /* PRI */
+       /* 0 - low priority, 3 - high priority */
+#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK         0x00000300
+#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT        8
+#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT      0x00000000
+
+       /* MINBW, MAXBW */
+       /* value range - 0..100, increments in 100Mbps */
+#define FUNC_MF_CFG_MIN_BW_MASK                    0x00ff0000
+#define FUNC_MF_CFG_MIN_BW_SHIFT                   16
+#define FUNC_MF_CFG_MIN_BW_DEFAULT                 0x00000000
+#define FUNC_MF_CFG_MAX_BW_MASK                    0xff000000
+#define FUNC_MF_CFG_MAX_BW_SHIFT                   24
+#define FUNC_MF_CFG_MAX_BW_DEFAULT                 0x64000000
+
+       u32 mac_upper;          /* MAC */
+#define FUNC_MF_CFG_UPPERMAC_MASK                  0x0000ffff
+#define FUNC_MF_CFG_UPPERMAC_SHIFT                 0
+#define FUNC_MF_CFG_UPPERMAC_DEFAULT               FUNC_MF_CFG_UPPERMAC_MASK
+       u32 mac_lower;
+#define FUNC_MF_CFG_LOWERMAC_DEFAULT               0xffffffff
+
+       u32 e1hov_tag;  /* VNI */
+#define FUNC_MF_CFG_E1HOV_TAG_MASK                 0x0000ffff
+#define FUNC_MF_CFG_E1HOV_TAG_SHIFT                0
+#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT              FUNC_MF_CFG_E1HOV_TAG_MASK
+
+       u32 reserved[2];
+
+};
+
+struct mf_cfg {
+
+       struct shared_mf_cfg    shared_mf_config;
+       struct port_mf_cfg      port_mf_config[PORT_MAX];
+       struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
+
+};
+
+
+/****************************************************************************
+ * Shared Memory Region                                                    *
+ ****************************************************************************/
+struct shmem_region {                         /*   SharedMem Offset (size) */
+
+       u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
+#define SHR_MEM_FORMAT_REV_ID                      ('A'<<24)
+#define SHR_MEM_FORMAT_REV_MASK                    0xff000000
+       /* validity bits */
+#define SHR_MEM_VALIDITY_PCI_CFG                   0x00100000
+#define SHR_MEM_VALIDITY_MB                        0x00200000
+#define SHR_MEM_VALIDITY_DEV_INFO                  0x00400000
+#define SHR_MEM_VALIDITY_RESERVED                  0x00000007
+       /* One licensing bit should be set */
+#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
+#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
+#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
+#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT      0x00000020
+       /* Active MFW */
+#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN        0x00000000
+#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI           0x00000040
+#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP            0x00000080
+#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI           0x000000c0
+#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE           0x000001c0
+#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK           0x000001c0
+
+       struct shm_dev_info     dev_info;                /* 0x8     (0x438) */
+
+struct license_key             drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
+
+       /* FW information (for internal FW use) */
+       u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
+       struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
+
+       struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
+#if !defined(b710) /* BNX2X_UPSTREAM */
+       struct drv_func_mb      func_mb[E1H_FUNC_MAX];
+#else
+       struct drv_func_mb      func_mb[E1_FUNC_MAX];  /* 0x684 (44*2=0x58) */
+#endif
+
+#if !defined(b710) /* BNX2X_UPSTREAM */
+       struct mf_cfg           mf_cfg;
+#endif
+
+};                                                    /* 0x6dc */
+
+
+struct shmem2_region {
+
+       u32                     size;
+
+       u32                     dcc_support;
+#define SHMEM_DCC_SUPPORT_NONE                     0x00000000
+#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
+#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
+#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
+#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV         0x00000040
+#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV         0x00000080
+#define SHMEM_DCC_SUPPORT_DEFAULT                  SHMEM_DCC_SUPPORT_NONE
+
+};
+
+
+struct emac_stats {
+    u32     rx_stat_ifhcinoctets;
+    u32     rx_stat_ifhcinbadoctets;
+    u32     rx_stat_etherstatsfragments;
+    u32     rx_stat_ifhcinucastpkts;
+    u32     rx_stat_ifhcinmulticastpkts;
+    u32     rx_stat_ifhcinbroadcastpkts;
+    u32     rx_stat_dot3statsfcserrors;
+    u32     rx_stat_dot3statsalignmenterrors;
+    u32     rx_stat_dot3statscarriersenseerrors;
+    u32     rx_stat_xonpauseframesreceived;
+    u32     rx_stat_xoffpauseframesreceived;
+    u32     rx_stat_maccontrolframesreceived;
+    u32     rx_stat_xoffstateentered;
+    u32     rx_stat_dot3statsframestoolong;
+    u32     rx_stat_etherstatsjabbers;
+    u32     rx_stat_etherstatsundersizepkts;
+    u32     rx_stat_etherstatspkts64octets;
+    u32     rx_stat_etherstatspkts65octetsto127octets;
+    u32     rx_stat_etherstatspkts128octetsto255octets;
+    u32     rx_stat_etherstatspkts256octetsto511octets;
+    u32     rx_stat_etherstatspkts512octetsto1023octets;
+    u32     rx_stat_etherstatspkts1024octetsto1522octets;
+    u32     rx_stat_etherstatspktsover1522octets;
+
+    u32     rx_stat_falsecarriererrors;
+
+    u32     tx_stat_ifhcoutoctets;
+    u32     tx_stat_ifhcoutbadoctets;
+    u32     tx_stat_etherstatscollisions;
+    u32     tx_stat_outxonsent;
+    u32     tx_stat_outxoffsent;
+    u32     tx_stat_flowcontroldone;
+    u32     tx_stat_dot3statssinglecollisionframes;
+    u32     tx_stat_dot3statsmultiplecollisionframes;
+    u32     tx_stat_dot3statsdeferredtransmissions;
+    u32     tx_stat_dot3statsexcessivecollisions;
+    u32     tx_stat_dot3statslatecollisions;
+    u32     tx_stat_ifhcoutucastpkts;
+    u32     tx_stat_ifhcoutmulticastpkts;
+    u32     tx_stat_ifhcoutbroadcastpkts;
+    u32     tx_stat_etherstatspkts64octets;
+    u32     tx_stat_etherstatspkts65octetsto127octets;
+    u32     tx_stat_etherstatspkts128octetsto255octets;
+    u32     tx_stat_etherstatspkts256octetsto511octets;
+    u32     tx_stat_etherstatspkts512octetsto1023octets;
+    u32     tx_stat_etherstatspkts1024octetsto1522octets;
+    u32     tx_stat_etherstatspktsover1522octets;
+    u32     tx_stat_dot3statsinternalmactransmiterrors;
+};
+
+
+struct bmac_stats {
+    u32     tx_stat_gtpkt_lo;
+    u32     tx_stat_gtpkt_hi;
+    u32     tx_stat_gtxpf_lo;
+    u32     tx_stat_gtxpf_hi;
+    u32     tx_stat_gtfcs_lo;
+    u32     tx_stat_gtfcs_hi;
+    u32     tx_stat_gtmca_lo;
+    u32     tx_stat_gtmca_hi;
+    u32     tx_stat_gtbca_lo;
+    u32     tx_stat_gtbca_hi;
+    u32     tx_stat_gtfrg_lo;
+    u32     tx_stat_gtfrg_hi;
+    u32     tx_stat_gtovr_lo;
+    u32     tx_stat_gtovr_hi;
+    u32     tx_stat_gt64_lo;
+    u32     tx_stat_gt64_hi;
+    u32     tx_stat_gt127_lo;
+    u32     tx_stat_gt127_hi;
+    u32     tx_stat_gt255_lo;
+    u32     tx_stat_gt255_hi;
+    u32     tx_stat_gt511_lo;
+    u32     tx_stat_gt511_hi;
+    u32     tx_stat_gt1023_lo;
+    u32     tx_stat_gt1023_hi;
+    u32     tx_stat_gt1518_lo;
+    u32     tx_stat_gt1518_hi;
+    u32     tx_stat_gt2047_lo;
+    u32     tx_stat_gt2047_hi;
+    u32     tx_stat_gt4095_lo;
+    u32     tx_stat_gt4095_hi;
+    u32     tx_stat_gt9216_lo;
+    u32     tx_stat_gt9216_hi;
+    u32     tx_stat_gt16383_lo;
+    u32     tx_stat_gt16383_hi;
+    u32     tx_stat_gtmax_lo;
+    u32     tx_stat_gtmax_hi;
+    u32     tx_stat_gtufl_lo;
+    u32     tx_stat_gtufl_hi;
+    u32     tx_stat_gterr_lo;
+    u32     tx_stat_gterr_hi;
+    u32     tx_stat_gtbyt_lo;
+    u32     tx_stat_gtbyt_hi;
+
+    u32     rx_stat_gr64_lo;
+    u32     rx_stat_gr64_hi;
+    u32     rx_stat_gr127_lo;
+    u32     rx_stat_gr127_hi;
+    u32     rx_stat_gr255_lo;
+    u32     rx_stat_gr255_hi;
+    u32     rx_stat_gr511_lo;
+    u32     rx_stat_gr511_hi;
+    u32     rx_stat_gr1023_lo;
+    u32     rx_stat_gr1023_hi;
+    u32     rx_stat_gr1518_lo;
+    u32     rx_stat_gr1518_hi;
+    u32     rx_stat_gr2047_lo;
+    u32     rx_stat_gr2047_hi;
+    u32     rx_stat_gr4095_lo;
+    u32     rx_stat_gr4095_hi;
+    u32     rx_stat_gr9216_lo;
+    u32     rx_stat_gr9216_hi;
+    u32     rx_stat_gr16383_lo;
+    u32     rx_stat_gr16383_hi;
+    u32     rx_stat_grmax_lo;
+    u32     rx_stat_grmax_hi;
+    u32     rx_stat_grpkt_lo;
+    u32     rx_stat_grpkt_hi;
+    u32     rx_stat_grfcs_lo;
+    u32     rx_stat_grfcs_hi;
+    u32     rx_stat_grmca_lo;
+    u32     rx_stat_grmca_hi;
+    u32     rx_stat_grbca_lo;
+    u32     rx_stat_grbca_hi;
+    u32     rx_stat_grxcf_lo;
+    u32     rx_stat_grxcf_hi;
+    u32     rx_stat_grxpf_lo;
+    u32     rx_stat_grxpf_hi;
+    u32     rx_stat_grxuo_lo;
+    u32     rx_stat_grxuo_hi;
+    u32     rx_stat_grjbr_lo;
+    u32     rx_stat_grjbr_hi;
+    u32     rx_stat_grovr_lo;
+    u32     rx_stat_grovr_hi;
+    u32     rx_stat_grflr_lo;
+    u32     rx_stat_grflr_hi;
+    u32     rx_stat_grmeg_lo;
+    u32     rx_stat_grmeg_hi;
+    u32     rx_stat_grmeb_lo;
+    u32     rx_stat_grmeb_hi;
+    u32     rx_stat_grbyt_lo;
+    u32     rx_stat_grbyt_hi;
+    u32     rx_stat_grund_lo;
+    u32     rx_stat_grund_hi;
+    u32     rx_stat_grfrg_lo;
+    u32     rx_stat_grfrg_hi;
+    u32     rx_stat_grerb_lo;
+    u32     rx_stat_grerb_hi;
+    u32     rx_stat_grfre_lo;
+    u32     rx_stat_grfre_hi;
+    u32     rx_stat_gripj_lo;
+    u32     rx_stat_gripj_hi;
+};
+
+
+union mac_stats {
+    struct emac_stats  emac_stats;
+    struct bmac_stats  bmac_stats;
+};
+
+
+struct mac_stx {
+    /* in_bad_octets */
+    u32     rx_stat_ifhcinbadoctets_hi;
+    u32     rx_stat_ifhcinbadoctets_lo;
+
+    /* out_bad_octets */
+    u32     tx_stat_ifhcoutbadoctets_hi;
+    u32     tx_stat_ifhcoutbadoctets_lo;
+
+    /* crc_receive_errors */
+    u32     rx_stat_dot3statsfcserrors_hi;
+    u32     rx_stat_dot3statsfcserrors_lo;
+    /* alignment_errors */
+    u32     rx_stat_dot3statsalignmenterrors_hi;
+    u32     rx_stat_dot3statsalignmenterrors_lo;
+    /* carrier_sense_errors */
+    u32     rx_stat_dot3statscarriersenseerrors_hi;
+    u32     rx_stat_dot3statscarriersenseerrors_lo;
+    /* false_carrier_detections */
+    u32     rx_stat_falsecarriererrors_hi;
+    u32     rx_stat_falsecarriererrors_lo;
+
+    /* runt_packets_received */
+    u32     rx_stat_etherstatsundersizepkts_hi;
+    u32     rx_stat_etherstatsundersizepkts_lo;
+    /* jabber_packets_received */
+    u32     rx_stat_dot3statsframestoolong_hi;
+    u32     rx_stat_dot3statsframestoolong_lo;
+
+    /* error_runt_packets_received */
+    u32     rx_stat_etherstatsfragments_hi;
+    u32     rx_stat_etherstatsfragments_lo;
+    /* error_jabber_packets_received */
+    u32     rx_stat_etherstatsjabbers_hi;
+    u32     rx_stat_etherstatsjabbers_lo;
+
+    /* control_frames_received */
+    u32     rx_stat_maccontrolframesreceived_hi;
+    u32     rx_stat_maccontrolframesreceived_lo;
+    u32     rx_stat_bmac_xpf_hi;
+    u32     rx_stat_bmac_xpf_lo;
+    u32     rx_stat_bmac_xcf_hi;
+    u32     rx_stat_bmac_xcf_lo;
+
+    /* xoff_state_entered */
+    u32     rx_stat_xoffstateentered_hi;
+    u32     rx_stat_xoffstateentered_lo;
+    /* pause_xon_frames_received */
+    u32     rx_stat_xonpauseframesreceived_hi;
+    u32     rx_stat_xonpauseframesreceived_lo;
+    /* pause_xoff_frames_received */
+    u32     rx_stat_xoffpauseframesreceived_hi;
+    u32     rx_stat_xoffpauseframesreceived_lo;
+    /* pause_xon_frames_transmitted */
+    u32     tx_stat_outxonsent_hi;
+    u32     tx_stat_outxonsent_lo;
+    /* pause_xoff_frames_transmitted */
+    u32     tx_stat_outxoffsent_hi;
+    u32     tx_stat_outxoffsent_lo;
+    /* flow_control_done */
+    u32     tx_stat_flowcontroldone_hi;
+    u32     tx_stat_flowcontroldone_lo;
+
+    /* ether_stats_collisions */
+    u32     tx_stat_etherstatscollisions_hi;
+    u32     tx_stat_etherstatscollisions_lo;
+    /* single_collision_transmit_frames */
+    u32     tx_stat_dot3statssinglecollisionframes_hi;
+    u32     tx_stat_dot3statssinglecollisionframes_lo;
+    /* multiple_collision_transmit_frames */
+    u32     tx_stat_dot3statsmultiplecollisionframes_hi;
+    u32     tx_stat_dot3statsmultiplecollisionframes_lo;
+    /* deferred_transmissions */
+    u32     tx_stat_dot3statsdeferredtransmissions_hi;
+    u32     tx_stat_dot3statsdeferredtransmissions_lo;
+    /* excessive_collision_frames */
+    u32     tx_stat_dot3statsexcessivecollisions_hi;
+    u32     tx_stat_dot3statsexcessivecollisions_lo;
+    /* late_collision_frames */
+    u32     tx_stat_dot3statslatecollisions_hi;
+    u32     tx_stat_dot3statslatecollisions_lo;
+
+    /* frames_transmitted_64_bytes */
+    u32     tx_stat_etherstatspkts64octets_hi;
+    u32     tx_stat_etherstatspkts64octets_lo;
+    /* frames_transmitted_65_127_bytes */
+    u32     tx_stat_etherstatspkts65octetsto127octets_hi;
+    u32     tx_stat_etherstatspkts65octetsto127octets_lo;
+    /* frames_transmitted_128_255_bytes */
+    u32     tx_stat_etherstatspkts128octetsto255octets_hi;
+    u32     tx_stat_etherstatspkts128octetsto255octets_lo;
+    /* frames_transmitted_256_511_bytes */
+    u32     tx_stat_etherstatspkts256octetsto511octets_hi;
+    u32     tx_stat_etherstatspkts256octetsto511octets_lo;
+    /* frames_transmitted_512_1023_bytes */
+    u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
+    u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
+    /* frames_transmitted_1024_1522_bytes */
+    u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
+    u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
+    /* frames_transmitted_1523_9022_bytes */
+    u32     tx_stat_etherstatspktsover1522octets_hi;
+    u32     tx_stat_etherstatspktsover1522octets_lo;
+    u32     tx_stat_bmac_2047_hi;
+    u32     tx_stat_bmac_2047_lo;
+    u32     tx_stat_bmac_4095_hi;
+    u32     tx_stat_bmac_4095_lo;
+    u32     tx_stat_bmac_9216_hi;
+    u32     tx_stat_bmac_9216_lo;
+    u32     tx_stat_bmac_16383_hi;
+    u32     tx_stat_bmac_16383_lo;
+
+    /* internal_mac_transmit_errors */
+    u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
+    u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
+
+    /* if_out_discards */
+    u32     tx_stat_bmac_ufl_hi;
+    u32     tx_stat_bmac_ufl_lo;
+};
+
+
+#define MAC_STX_IDX_MAX                    2
+
+struct host_port_stats {
+    u32           host_port_stats_start;
+
+    struct mac_stx mac_stx[MAC_STX_IDX_MAX];
+
+    u32           brb_drop_hi;
+    u32           brb_drop_lo;
+
+    u32           host_port_stats_end;
+};
+
+
+struct host_func_stats {
+    u32     host_func_stats_start;
+
+    u32     total_bytes_received_hi;
+    u32     total_bytes_received_lo;
+
+    u32     total_bytes_transmitted_hi;
+    u32     total_bytes_transmitted_lo;
+
+    u32     total_unicast_packets_received_hi;
+    u32     total_unicast_packets_received_lo;
+
+    u32     total_multicast_packets_received_hi;
+    u32     total_multicast_packets_received_lo;
+
+    u32     total_broadcast_packets_received_hi;
+    u32     total_broadcast_packets_received_lo;
+
+    u32     total_unicast_packets_transmitted_hi;
+    u32     total_unicast_packets_transmitted_lo;
+
+    u32     total_multicast_packets_transmitted_hi;
+    u32     total_multicast_packets_transmitted_lo;
+
+    u32     total_broadcast_packets_transmitted_hi;
+    u32     total_broadcast_packets_transmitted_lo;
+
+    u32     valid_bytes_received_hi;
+    u32     valid_bytes_received_lo;
+
+    u32     host_func_stats_end;
+};
+
+
+#define BCM_5710_FW_MAJOR_VERSION                      5
+#define BCM_5710_FW_MINOR_VERSION                      0
+#define BCM_5710_FW_REVISION_VERSION                   21
+#define BCM_5710_FW_ENGINEERING_VERSION                0
+#define BCM_5710_FW_COMPILE_FLAGS                      1
+
+
+/*
+ * attention bits
+ */
+struct atten_def_status_block {
+       __le32 attn_bits;
+       __le32 attn_bits_ack;
+       u8 status_block_id;
+       u8 reserved0;
+       __le16 attn_bits_index;
+       __le32 reserved1;
+};
+
+
+/*
+ * common data for all protocols
+ */
+struct doorbell_hdr {
+       u8 header;
+#define DOORBELL_HDR_RX (0x1<<0)
+#define DOORBELL_HDR_RX_SHIFT 0
+#define DOORBELL_HDR_DB_TYPE (0x1<<1)
+#define DOORBELL_HDR_DB_TYPE_SHIFT 1
+#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
+#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
+#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
+#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
+};
+
+/*
+ * doorbell message sent to the chip
+ */
+struct doorbell {
+#if defined(__BIG_ENDIAN)
+       u16 zero_fill2;
+       u8 zero_fill1;
+       struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+       struct doorbell_hdr header;
+       u8 zero_fill1;
+       u16 zero_fill2;
+#endif
+};
+
+
+/*
+ * doorbell message sent to the chip
+ */
+struct doorbell_set_prod {
+#if defined(__BIG_ENDIAN)
+       u16 prod;
+       u8 zero_fill1;
+       struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+       struct doorbell_hdr header;
+       u8 zero_fill1;
+       u16 prod;
+#endif
+};
+
+
+/*
+ * IGU driver acknowledgement register
+ */
+struct igu_ack_register {
+#if defined(__BIG_ENDIAN)
+       u16 sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+       u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+       u16 status_block_index;
+       u16 sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+#endif
+};
+
+
+/*
+ * IGU driver acknowledgement register
+ */
+struct igu_backward_compatible {
+       u32 sb_id_and_flags;
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
+       u32 reserved_2;
+};
+
+
+/*
+ * IGU driver acknowledgement register
+ */
+struct igu_regular {
+       u32 sb_id_and_flags;
+#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
+#define IGU_REGULAR_SB_INDEX_SHIFT 0
+#define IGU_REGULAR_RESERVED0 (0x1<<20)
+#define IGU_REGULAR_RESERVED0_SHIFT 20
+#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
+#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
+#define IGU_REGULAR_BUPDATE (0x1<<24)
+#define IGU_REGULAR_BUPDATE_SHIFT 24
+#define IGU_REGULAR_ENABLE_INT (0x3<<25)
+#define IGU_REGULAR_ENABLE_INT_SHIFT 25
+#define IGU_REGULAR_RESERVED_1 (0x1<<27)
+#define IGU_REGULAR_RESERVED_1_SHIFT 27
+#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
+#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
+#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
+#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
+#define IGU_REGULAR_BCLEANUP (0x1<<31)
+#define IGU_REGULAR_BCLEANUP_SHIFT 31
+       u32 reserved_2;
+};
+
+/*
+ * IGU driver acknowledgement register
+ */
+union igu_consprod_reg {
+       struct igu_regular regular;
+       struct igu_backward_compatible backward_compatible;
+};
+
+
+/*
+ * Parser parsing flags field
+ */
+struct parsing_flags {
+       __le16 flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
+#define PARSING_FLAGS_VLAN (0x1<<1)
+#define PARSING_FLAGS_VLAN_SHIFT 1
+#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
+#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
+#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
+#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
+#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
+#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
+#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
+#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
+#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
+#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
+#define PARSING_FLAGS_RESERVED0 (0x3<<14)
+#define PARSING_FLAGS_RESERVED0_SHIFT 14
+};
+
+
+struct regpair {
+       __le32 lo;
+       __le32 hi;
+};
+
+
+/*
+ * dmae command structure
+ */
+struct dmae_command {
+       u32 opcode;
+#define DMAE_COMMAND_SRC (0x1<<0)
+#define DMAE_COMMAND_SRC_SHIFT 0
+#define DMAE_COMMAND_DST (0x3<<1)
+#define DMAE_COMMAND_DST_SHIFT 1
+#define DMAE_COMMAND_C_DST (0x1<<3)
+#define DMAE_COMMAND_C_DST_SHIFT 3
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
+#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
+#define DMAE_COMMAND_ENDIANITY (0x3<<9)
+#define DMAE_COMMAND_ENDIANITY_SHIFT 9
+#define DMAE_COMMAND_PORT (0x1<<11)
+#define DMAE_COMMAND_PORT_SHIFT 11
+#define DMAE_COMMAND_CRC_RESET (0x1<<12)
+#define DMAE_COMMAND_CRC_RESET_SHIFT 12
+#define DMAE_COMMAND_SRC_RESET (0x1<<13)
+#define DMAE_COMMAND_SRC_RESET_SHIFT 13
+#define DMAE_COMMAND_DST_RESET (0x1<<14)
+#define DMAE_COMMAND_DST_RESET_SHIFT 14
+#define DMAE_COMMAND_E1HVN (0x3<<15)
+#define DMAE_COMMAND_E1HVN_SHIFT 15
+#define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
+#define DMAE_COMMAND_RESERVED0_SHIFT 17
+       u32 src_addr_lo;
+       u32 src_addr_hi;
+       u32 dst_addr_lo;
+       u32 dst_addr_hi;
+#if defined(__BIG_ENDIAN)
+       u16 reserved1;
+       u16 len;
+#elif defined(__LITTLE_ENDIAN)
+       u16 len;
+       u16 reserved1;
+#endif
+       u32 comp_addr_lo;
+       u32 comp_addr_hi;
+       u32 comp_val;
+       u32 crc32;
+       u32 crc32_c;
+#if defined(__BIG_ENDIAN)
+       u16 crc16_c;
+       u16 crc16;
+#elif defined(__LITTLE_ENDIAN)
+       u16 crc16;
+       u16 crc16_c;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 reserved2;
+       u16 crc_t10;
+#elif defined(__LITTLE_ENDIAN)
+       u16 crc_t10;
+       u16 reserved2;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 xsum8;
+       u16 xsum16;
+#elif defined(__LITTLE_ENDIAN)
+       u16 xsum16;
+       u16 xsum8;
+#endif
+};
+
+
+struct double_regpair {
+       u32 regpair0_lo;
+       u32 regpair0_hi;
+       u32 regpair1_lo;
+       u32 regpair1_hi;
+};
+
+
+/*
+ * The eth storm context of Ustorm (configuration part)
+ */
+struct ustorm_eth_st_context_config {
+#if defined(__BIG_ENDIAN)
+       u8 flags;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
+       u8 status_block_id;
+       u8 clientId;
+       u8 sb_index_numbers;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
+#elif defined(__LITTLE_ENDIAN)
+       u8 sb_index_numbers;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
+       u8 clientId;
+       u8 status_block_id;
+       u8 flags;
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
+#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
+#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 bd_buff_size;
+       u8 statistics_counter_id;
+       u8 mc_alignment_log_size;
+#elif defined(__LITTLE_ENDIAN)
+       u8 mc_alignment_log_size;
+       u8 statistics_counter_id;
+       u16 bd_buff_size;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 __local_sge_prod;
+       u8 __local_bd_prod;
+       u16 sge_buff_size;
+#elif defined(__LITTLE_ENDIAN)
+       u16 sge_buff_size;
+       u8 __local_bd_prod;
+       u8 __local_sge_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __sdm_bd_expected_counter;
+       u8 cstorm_agg_int;
+       u8 __expected_bds_on_ram;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __expected_bds_on_ram;
+       u8 cstorm_agg_int;
+       u16 __sdm_bd_expected_counter;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __ring_data_ram_addr;
+       u16 __hc_cstorm_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __hc_cstorm_ram_addr;
+       u16 __ring_data_ram_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 reserved1;
+       u8 max_sges_for_packet;
+       u16 __bd_ring_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __bd_ring_ram_addr;
+       u8 max_sges_for_packet;
+       u8 reserved1;
+#endif
+       u32 bd_page_base_lo;
+       u32 bd_page_base_hi;
+       u32 sge_page_base_lo;
+       u32 sge_page_base_hi;
+       struct regpair reserved2;
+};
+
+/*
+ * The eth Rx Buffer Descriptor
+ */
+struct eth_rx_bd {
+       __le32 addr_lo;
+       __le32 addr_hi;
+};
+
+/*
+ * The eth Rx SGE Descriptor
+ */
+struct eth_rx_sge {
+       __le32 addr_lo;
+       __le32 addr_hi;
+};
+
+/*
+ * Local BDs and SGEs rings (in ETH)
+ */
+struct eth_local_rx_rings {
+       struct eth_rx_bd __local_bd_ring[8];
+       struct eth_rx_sge __local_sge_ring[10];
+};
+
+/*
+ * The eth storm context of Ustorm
+ */
+struct ustorm_eth_st_context {
+       struct ustorm_eth_st_context_config common;
+       struct eth_local_rx_rings __rings;
+};
+
+/*
+ * The eth storm context of Tstorm
+ */
+struct tstorm_eth_st_context {
+       u32 __reserved0[28];
+};
+
+/*
+ * The eth aggregative context section of Xstorm
+ */
+struct xstorm_eth_extra_ag_context_section {
+#if defined(__BIG_ENDIAN)
+       u8 __tcp_agg_vars1;
+       u8 __reserved50;
+       u16 __mss;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __mss;
+       u8 __reserved50;
+       u8 __tcp_agg_vars1;
+#endif
+       u32 __snd_nxt;
+       u32 __tx_wnd;
+       u32 __snd_una;
+       u32 __reserved53;
+#if defined(__BIG_ENDIAN)
+       u8 __agg_val8_th;
+       u8 __agg_val8;
+       u16 __tcp_agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __tcp_agg_vars2;
+       u8 __agg_val8;
+       u8 __agg_val8_th;
+#endif
+       u32 __reserved58;
+       u32 __reserved59;
+       u32 __reserved60;
+       u32 __reserved61;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_val7_th;
+       u16 __agg_val7;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val7;
+       u16 __agg_val7_th;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 __tcp_agg_vars5;
+       u8 __tcp_agg_vars4;
+       u8 __tcp_agg_vars3;
+       u8 __reserved62;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __reserved62;
+       u8 __tcp_agg_vars3;
+       u8 __tcp_agg_vars4;
+       u8 __tcp_agg_vars5;
+#endif
+       u32 __tcp_agg_vars6;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_misc6;
+       u16 __tcp_agg_vars7;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __tcp_agg_vars7;
+       u16 __agg_misc6;
+#endif
+       u32 __agg_val10;
+       u32 __agg_val10_th;
+#if defined(__BIG_ENDIAN)
+       u16 __reserved3;
+       u8 __reserved2;
+       u8 __da_only_cnt;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __da_only_cnt;
+       u8 __reserved2;
+       u16 __reserved3;
+#endif
+};
+
+/*
+ * The eth aggregative context of Xstorm
+ */
+struct xstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+       u16 agg_val1;
+       u8 __agg_vars1;
+       u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __state;
+       u8 __agg_vars1;
+       u16 agg_val1;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 cdu_reserved;
+       u8 __agg_vars4;
+       u8 __agg_vars3;
+       u8 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __agg_vars2;
+       u8 __agg_vars3;
+       u8 __agg_vars4;
+       u8 cdu_reserved;
+#endif
+       u32 __bd_prod;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_vars5;
+       u16 __agg_val4_th;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val4_th;
+       u16 __agg_vars5;
+#endif
+       struct xstorm_eth_extra_ag_context_section __extra_section;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_vars7;
+       u8 __agg_val3_th;
+       u8 __agg_vars6;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __agg_vars6;
+       u8 __agg_val3_th;
+       u16 __agg_vars7;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __agg_val11_th;
+       u16 __agg_val11;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val11;
+       u16 __agg_val11_th;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 __reserved1;
+       u8 __agg_val6_th;
+       u16 __agg_val9;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val9;
+       u8 __agg_val6_th;
+       u8 __reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __agg_val2_th;
+       u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val2;
+       u16 __agg_val2_th;
+#endif
+       u32 __agg_vars8;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_misc0;
+       u16 __agg_val4;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val4;
+       u16 __agg_misc0;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 __agg_val3;
+       u8 __agg_val6;
+       u8 __agg_val5_th;
+       u8 __agg_val5;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __agg_val5;
+       u8 __agg_val5_th;
+       u8 __agg_val6;
+       u8 __agg_val3;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __agg_misc1;
+       u16 __bd_ind_max_val;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __bd_ind_max_val;
+       u16 __agg_misc1;
+#endif
+       u32 __reserved57;
+       u32 __agg_misc4;
+       u32 __agg_misc5;
+};
+
+/*
+ * The eth extra aggregative context section of Tstorm
+ */
+struct tstorm_eth_extra_ag_context_section {
+       u32 __agg_val1;
+#if defined(__BIG_ENDIAN)
+       u8 __tcp_agg_vars2;
+       u8 __agg_val3;
+       u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val2;
+       u8 __agg_val3;
+       u8 __tcp_agg_vars2;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __agg_val5;
+       u8 __agg_val6;
+       u8 __tcp_agg_vars3;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __tcp_agg_vars3;
+       u8 __agg_val6;
+       u16 __agg_val5;
+#endif
+       u32 __reserved63;
+       u32 __reserved64;
+       u32 __reserved65;
+       u32 __reserved66;
+       u32 __reserved67;
+       u32 __tcp_agg_vars1;
+       u32 __reserved61;
+       u32 __reserved62;
+       u32 __reserved2;
+};
+
+/*
+ * The eth aggregative context of Tstorm
+ */
+struct tstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+       u16 __reserved54;
+       u8 __agg_vars1;
+       u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __state;
+       u8 __agg_vars1;
+       u16 __reserved54;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __agg_val4;
+       u16 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_vars2;
+       u16 __agg_val4;
+#endif
+       struct tstorm_eth_extra_ag_context_section __extra_section;
+};
+
+/*
+ * The eth aggregative context of Cstorm
+ */
+struct cstorm_eth_ag_context {
+       u32 __agg_vars1;
+#if defined(__BIG_ENDIAN)
+       u8 __aux1_th;
+       u8 __aux1_val;
+       u16 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_vars2;
+       u8 __aux1_val;
+       u8 __aux1_th;
+#endif
+       u32 __num_of_treated_packet;
+       u32 __last_packet_treated;
+#if defined(__BIG_ENDIAN)
+       u16 __reserved58;
+       u16 __reserved57;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __reserved57;
+       u16 __reserved58;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 __reserved62;
+       u8 __reserved61;
+       u8 __reserved60;
+       u8 __reserved59;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __reserved59;
+       u8 __reserved60;
+       u8 __reserved61;
+       u8 __reserved62;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __reserved64;
+       u16 __reserved63;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __reserved63;
+       u16 __reserved64;
+#endif
+       u32 __reserved65;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_vars3;
+       u16 __rq_inv_cnt;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __rq_inv_cnt;
+       u16 __agg_vars3;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __packet_index_th;
+       u16 __packet_index;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __packet_index;
+       u16 __packet_index_th;
+#endif
+};
+
+/*
+ * The eth aggregative context of Ustorm
+ */
+struct ustorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+       u8 __aux_counter_flags;
+       u8 __agg_vars2;
+       u8 __agg_vars1;
+       u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __state;
+       u8 __agg_vars1;
+       u8 __agg_vars2;
+       u8 __aux_counter_flags;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 cdu_usage;
+       u8 __agg_misc2;
+       u16 __agg_misc1;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_misc1;
+       u8 __agg_misc2;
+       u8 cdu_usage;
+#endif
+       u32 __agg_misc4;
+#if defined(__BIG_ENDIAN)
+       u8 __agg_val3_th;
+       u8 __agg_val3;
+       u16 __agg_misc3;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_misc3;
+       u8 __agg_val3;
+       u8 __agg_val3_th;
+#endif
+       u32 __agg_val1;
+       u32 __agg_misc4_th;
+#if defined(__BIG_ENDIAN)
+       u16 __agg_val2_th;
+       u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __agg_val2;
+       u16 __agg_val2_th;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __reserved2;
+       u8 __decision_rules;
+       u8 __decision_rule_enable_bits;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __decision_rule_enable_bits;
+       u8 __decision_rules;
+       u16 __reserved2;
+#endif
+};
+
+/*
+ * Timers connection context
+ */
+struct timers_block_context {
+       u32 __reserved_0;
+       u32 __reserved_1;
+       u32 __reserved_2;
+       u32 flags;
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
+};
+
+/*
+ * structure for easy accessibility to assembler
+ */
+struct eth_tx_bd_flags {
+       u8 as_bitfield;
+#define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
+#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
+#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2)
+#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2
+#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
+#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
+#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
+#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
+#define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
+#define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
+#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
+#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
+#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
+};
+
+/*
+ * The eth Tx Buffer Descriptor
+ */
+struct eth_tx_start_bd {
+       __le32 addr_lo;
+       __le32 addr_hi;
+       __le16 nbd;
+       __le16 nbytes;
+       __le16 vlan;
+       struct eth_tx_bd_flags bd_flags;
+       u8 general_data;
+#define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
+#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
+#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
+};
+
+/*
+ * Tx regular BD structure
+ */
+struct eth_tx_bd {
+       u32 addr_lo;
+       u32 addr_hi;
+       u16 total_pkt_bytes;
+       u16 nbytes;
+       u8 reserved[4];
+};
+
+/*
+ * Tx parsing BD structure for ETH,Relevant in START
+ */
+struct eth_tx_parse_bd {
+       u8 global_data;
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
+#define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
+#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
+       u8 tcp_flags;
+#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
+#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
+#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
+#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
+#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
+#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
+#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
+       u8 ip_hlen;
+       s8 reserved;
+       __le16 total_hlen;
+       __le16 tcp_pseudo_csum;
+       __le16 lso_mss;
+       __le16 ip_id;
+       __le32 tcp_send_seq;
+};
+
+/*
+ * The last BD in the BD memory will hold a pointer to the next BD memory
+ */
+struct eth_tx_next_bd {
+       __le32 addr_lo;
+       __le32 addr_hi;
+       u8 reserved[8];
+};
+
+/*
+ * union for 4 Bd types
+ */
+union eth_tx_bd_types {
+       struct eth_tx_start_bd start_bd;
+       struct eth_tx_bd reg_bd;
+       struct eth_tx_parse_bd parse_bd;
+       struct eth_tx_next_bd next_bd;
+};
+
+/*
+ * The eth storm context of Xstorm
+ */
+struct xstorm_eth_st_context {
+       u32 tx_bd_page_base_lo;
+       u32 tx_bd_page_base_hi;
+#if defined(__BIG_ENDIAN)
+       u16 tx_bd_cons;
+       u8 statistics_data;
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
+       u8 __local_tx_bd_prod;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __local_tx_bd_prod;
+       u8 statistics_data;
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
+#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
+       u16 tx_bd_cons;
+#endif
+       u32 __reserved1;
+       u32 __reserved2;
+#if defined(__BIG_ENDIAN)
+       u8 __ram_cache_index;
+       u8 __double_buffer_client;
+       u16 __pkt_cons;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __pkt_cons;
+       u8 __double_buffer_client;
+       u8 __ram_cache_index;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 __statistics_address;
+       u16 __gso_next;
+#elif defined(__LITTLE_ENDIAN)
+       u16 __gso_next;
+       u16 __statistics_address;
+#endif
+#if defined(__BIG_ENDIAN)
+       u8 __local_tx_bd_cons;
+       u8 safc_group_num;
+       u8 safc_group_en;
+       u8 __is_eth_conn;
+#elif defined(__LITTLE_ENDIAN)
+       u8 __is_eth_conn;
+       u8 safc_group_en;
+       u8 safc_group_num;
+       u8 __local_tx_bd_cons;
+#endif
+       union eth_tx_bd_types __bds[13];
+};
+
+/*
+ * The eth storm context of Cstorm
+ */
+struct cstorm_eth_st_context {
+#if defined(__BIG_ENDIAN)
+       u16 __reserved0;
+       u8 sb_index_number;
+       u8 status_block_id;
+#elif defined(__LITTLE_ENDIAN)
+       u8 status_block_id;
+       u8 sb_index_number;
+       u16 __reserved0;
+#endif
+       u32 __reserved1[3];
+};
+
+/*
+ * Ethernet connection context
+ */
+struct eth_context {
+       struct ustorm_eth_st_context ustorm_st_context;
+       struct tstorm_eth_st_context tstorm_st_context;
+       struct xstorm_eth_ag_context xstorm_ag_context;
+       struct tstorm_eth_ag_context tstorm_ag_context;
+       struct cstorm_eth_ag_context cstorm_ag_context;
+       struct ustorm_eth_ag_context ustorm_ag_context;
+       struct timers_block_context timers_context;
+       struct xstorm_eth_st_context xstorm_st_context;
+       struct cstorm_eth_st_context cstorm_st_context;
+};
+
+
+/*
+ * Ethernet doorbell
+ */
+struct eth_tx_doorbell {
+#if defined(__BIG_ENDIAN)
+       u16 npackets;
+       u8 params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+       struct doorbell_hdr hdr;
+#elif defined(__LITTLE_ENDIAN)
+       struct doorbell_hdr hdr;
+       u8 params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+       u16 npackets;
+#endif
+};
+
+
+/*
+ * cstorm default status block, generated by ustorm
+ */
+struct cstorm_def_status_block_u {
+       __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
+       __le16 status_block_index;
+       u8 func;
+       u8 status_block_id;
+       __le32 __flags;
+};
+
+/*
+ * cstorm default status block, generated by cstorm
+ */
+struct cstorm_def_status_block_c {
+       __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
+       __le16 status_block_index;
+       u8 func;
+       u8 status_block_id;
+       __le32 __flags;
+};
+
+/*
+ * xstorm status block
+ */
+struct xstorm_def_status_block {
+       __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
+       __le16 status_block_index;
+       u8 func;
+       u8 status_block_id;
+       __le32 __flags;
+};
+
+/*
+ * tstorm status block
+ */
+struct tstorm_def_status_block {
+       __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
+       __le16 status_block_index;
+       u8 func;
+       u8 status_block_id;
+       __le32 __flags;
+};
+
+/*
+ * host status block
+ */
+struct host_def_status_block {
+       struct atten_def_status_block atten_status_block;
+       struct cstorm_def_status_block_u u_def_status_block;
+       struct cstorm_def_status_block_c c_def_status_block;
+       struct xstorm_def_status_block x_def_status_block;
+       struct tstorm_def_status_block t_def_status_block;
+};
+
+
+/*
+ * cstorm status block, generated by ustorm
+ */
+struct cstorm_status_block_u {
+       __le16 index_values[HC_USTORM_SB_NUM_INDICES];
+       __le16 status_block_index;
+       u8 func;
+       u8 status_block_id;
+       __le32 __flags;
+};
+
+/*
+ * cstorm status block, generated by cstorm
+ */
+struct cstorm_status_block_c {
+       __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
+       __le16 status_block_index;
+       u8 func;
+       u8 status_block_id;
+       __le32 __flags;
+};
+
+/*
+ * host status block
+ */
+struct host_status_block {
+       struct cstorm_status_block_u u_status_block;
+       struct cstorm_status_block_c c_status_block;
+};
+
+
+/*
+ * The data for RSS setup ramrod
+ */
+struct eth_client_setup_ramrod_data {
+       u32 client_id;
+       u8 is_rdma;
+       u8 is_fcoe;
+       u16 reserved1;
+};
+
+
+/*
+ * regular eth FP CQE parameters struct
+ */
+struct eth_fast_path_rx_cqe {
+       u8 type_error_flags;
+#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
+#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
+#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
+#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
+       u8 status_flags;
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
+       u8 placement_offset;
+       u8 queue_index;
+       __le32 rss_hash_result;
+       __le16 vlan_tag;
+       __le16 pkt_len;
+       __le16 len_on_bd;
+       struct parsing_flags pars_flags;
+       __le16 sgl[8];
+};
+
+
+/*
+ * The data for RSS setup ramrod
+ */
+struct eth_halt_ramrod_data {
+       u32 client_id;
+       u32 reserved0;
+};
+
+
+/*
+ * The data for statistics query ramrod
+ */
+struct eth_query_ramrod_data {
+#if defined(__BIG_ENDIAN)
+       u8 reserved0;
+       u8 collect_port;
+       u16 drv_counter;
+#elif defined(__LITTLE_ENDIAN)
+       u16 drv_counter;
+       u8 collect_port;
+       u8 reserved0;
+#endif
+       u32 ctr_id_vector;
+};
+
+
+/*
+ * Place holder for ramrods protocol specific data
+ */
+struct ramrod_data {
+       __le32 data_lo;
+       __le32 data_hi;
+};
+
+/*
+ * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
+ */
+union eth_ramrod_data {
+       struct ramrod_data general;
+};
+
+
+/*
+ * Eth Rx Cqe structure- general structure for ramrods
+ */
+struct common_ramrod_eth_rx_cqe {
+       u8 ramrod_type;
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
+       u8 conn_type;
+       __le16 reserved1;
+       __le32 conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
+#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
+       struct ramrod_data protocol_data;
+       __le32 reserved2[4];
+};
+
+/*
+ * Rx Last CQE in page (in ETH)
+ */
+struct eth_rx_cqe_next_page {
+       __le32 addr_lo;
+       __le32 addr_hi;
+       __le32 reserved[6];
+};
+
+/*
+ * union for all eth rx cqe types (fix their sizes)
+ */
+union eth_rx_cqe {
+       struct eth_fast_path_rx_cqe fast_path_cqe;
+       struct common_ramrod_eth_rx_cqe ramrod_cqe;
+       struct eth_rx_cqe_next_page next_page_cqe;
+};
+
+
+/*
+ * common data for all protocols
+ */
+struct spe_hdr {
+       __le32 conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF<<0)
+#define SPE_HDR_CID_SHIFT 0
+#define SPE_HDR_CMD_ID (0xFF<<24)
+#define SPE_HDR_CMD_ID_SHIFT 24
+       __le16 type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0)
+#define SPE_HDR_CONN_TYPE_SHIFT 0
+#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
+#define SPE_HDR_COMMON_RAMROD_SHIFT 8
+       __le16 reserved;
+};
+
+/*
+ * Ethernet slow path element
+ */
+union eth_specific_data {
+       u8 protocol_data[8];
+       struct regpair mac_config_addr;
+       struct eth_client_setup_ramrod_data client_setup_ramrod_data;
+       struct eth_halt_ramrod_data halt_ramrod_data;
+       struct regpair leading_cqe_addr;
+       struct regpair update_data_addr;
+       struct eth_query_ramrod_data query_ramrod_data;
+};
+
+/*
+ * Ethernet slow path element
+ */
+struct eth_spe {
+       struct spe_hdr hdr;
+       union eth_specific_data data;
+};
+
+
+/*
+ * array of 13 bds as appears in the eth xstorm context
+ */
+struct eth_tx_bds_array {
+       union eth_tx_bd_types bds[13];
+};
+
+
+/*
+ * Common configuration parameters per function in Tstorm
+ */
+struct tstorm_eth_function_common_config {
+#if defined(__BIG_ENDIAN)
+       u8 leading_client_id;
+       u8 rss_result_mask;
+       u16 config_flags;
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
+#elif defined(__LITTLE_ENDIAN)
+       u16 config_flags;
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
+       u8 rss_result_mask;
+       u8 leading_client_id;
+#endif
+       u16 vlan_id[2];
+};
+
+/*
+ * RSS idirection table update configuration
+ */
+struct rss_update_config {
+#if defined(__BIG_ENDIAN)
+       u16 toe_rss_bitmap;
+       u16 flags;
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
+#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
+#elif defined(__LITTLE_ENDIAN)
+       u16 flags;
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
+#define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
+#define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
+#define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
+       u16 toe_rss_bitmap;
+#endif
+       u32 reserved1;
+};
+
+/*
+ * parameters for eth update ramrod
+ */
+struct eth_update_ramrod_data {
+       struct tstorm_eth_function_common_config func_config;
+       u8 indirectionTable[128];
+       struct rss_update_config rss_config;
+};
+
+
+/*
+ * MAC filtering configuration command header
+ */
+struct mac_configuration_hdr {
+       u8 length;
+       u8 offset;
+       u16 client_id;
+       u32 reserved1;
+};
+
+/*
+ * MAC address in list for ramrod
+ */
+struct tstorm_cam_entry {
+       __le16 lsb_mac_addr;
+       __le16 middle_mac_addr;
+       __le16 msb_mac_addr;
+       __le16 flags;
+#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
+#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
+#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
+#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
+#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
+#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
+};
+
+/*
+ * MAC filtering: CAM target table entry
+ */
+struct tstorm_cam_target_table_entry {
+       u8 flags;
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
+       u8 reserved1;
+       u16 vlan_id;
+       u32 clients_bit_vector;
+};
+
+/*
+ * MAC address in list for ramrod
+ */
+struct mac_configuration_entry {
+       struct tstorm_cam_entry cam_entry;
+       struct tstorm_cam_target_table_entry target_table_entry;
+};
+
+/*
+ * MAC filtering configuration command
+ */
+struct mac_configuration_cmd {
+       struct mac_configuration_hdr hdr;
+       struct mac_configuration_entry config_table[64];
+};
+
+
+/*
+ * MAC address in list for ramrod
+ */
+struct mac_configuration_entry_e1h {
+       __le16 lsb_mac_addr;
+       __le16 middle_mac_addr;
+       __le16 msb_mac_addr;
+       __le16 vlan_id;
+       __le16 e1hov_id;
+       u8 reserved0;
+       u8 flags;
+#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
+#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
+#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
+#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
+#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
+#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
+#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3)
+#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3
+       u32 clients_bit_vector;
+};
+
+/*
+ * MAC filtering configuration command
+ */
+struct mac_configuration_cmd_e1h {
+       struct mac_configuration_hdr hdr;
+       struct mac_configuration_entry_e1h config_table[32];
+};
+
+
+/*
+ * approximate-match multicast filtering for E1H per function in Tstorm
+ */
+struct tstorm_eth_approximate_match_multicast_filtering {
+       u32 mcast_add_hash_bit_array[8];
+};
+
+
+/*
+ * Configuration parameters per client in Tstorm
+ */
+struct tstorm_eth_client_config {
+#if defined(__BIG_ENDIAN)
+       u8 reserved0;
+       u8 statistics_counter_id;
+       u16 mtu;
+#elif defined(__LITTLE_ENDIAN)
+       u16 mtu;
+       u8 statistics_counter_id;
+       u8 reserved0;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 drop_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
+       u16 config_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
+#elif defined(__LITTLE_ENDIAN)
+       u16 config_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
+       u16 drop_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
+#endif
+};
+
+
+/*
+ * MAC filtering configuration parameters per port in Tstorm
+ */
+struct tstorm_eth_mac_filter_config {
+       u32 ucast_drop_all;
+       u32 ucast_accept_all;
+       u32 mcast_drop_all;
+       u32 mcast_accept_all;
+       u32 bcast_drop_all;
+       u32 bcast_accept_all;
+       u32 strict_vlan;
+       u32 vlan_filter[2];
+       u32 reserved;
+};
+
+
+/*
+ * common flag to indicate existance of TPA.
+ */
+struct tstorm_eth_tpa_exist {
+#if defined(__BIG_ENDIAN)
+       u16 reserved1;
+       u8 reserved0;
+       u8 tpa_exist;
+#elif defined(__LITTLE_ENDIAN)
+       u8 tpa_exist;
+       u8 reserved0;
+       u16 reserved1;
+#endif
+       u32 reserved2;
+};
+
+
+/*
+ * rx rings pause data for E1h only
+ */
+struct ustorm_eth_rx_pause_data_e1h {
+#if defined(__BIG_ENDIAN)
+       u16 bd_thr_low;
+       u16 cqe_thr_low;
+#elif defined(__LITTLE_ENDIAN)
+       u16 cqe_thr_low;
+       u16 bd_thr_low;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 cos;
+       u16 sge_thr_low;
+#elif defined(__LITTLE_ENDIAN)
+       u16 sge_thr_low;
+       u16 cos;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 bd_thr_high;
+       u16 cqe_thr_high;
+#elif defined(__LITTLE_ENDIAN)
+       u16 cqe_thr_high;
+       u16 bd_thr_high;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 reserved0;
+       u16 sge_thr_high;
+#elif defined(__LITTLE_ENDIAN)
+       u16 sge_thr_high;
+       u16 reserved0;
+#endif
+};
+
+
+/*
+ * Three RX producers for ETH
+ */
+struct ustorm_eth_rx_producers {
+#if defined(__BIG_ENDIAN)
+       u16 bd_prod;
+       u16 cqe_prod;
+#elif defined(__LITTLE_ENDIAN)
+       u16 cqe_prod;
+       u16 bd_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+       u16 reserved;
+       u16 sge_prod;
+#elif defined(__LITTLE_ENDIAN)
+       u16 sge_prod;
+       u16 reserved;
+#endif
+};
+
+
+/*
+ * per-port SAFC demo variables
+ */
+struct cmng_flags_per_port {
+       u8 con_number[NUM_OF_PROTOCOLS];
+       u32 cmng_enables;
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
+#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
+};
+
+
+/*
+ * per-port rate shaping variables
+ */
+struct rate_shaping_vars_per_port {
+       u32 rs_periodic_timeout;
+       u32 rs_threshold;
+};
+
+/*
+ * per-port fairness variables
+ */
+struct fairness_vars_per_port {
+       u32 upper_bound;
+       u32 fair_threshold;
+       u32 fairness_timeout;
+};
+
+/*
+ * per-port SAFC variables
+ */
+struct safc_struct_per_port {
+#if defined(__BIG_ENDIAN)
+       u16 __reserved1;
+       u8 __reserved0;
+       u8 safc_timeout_usec;
+#elif defined(__LITTLE_ENDIAN)
+       u8 safc_timeout_usec;
+       u8 __reserved0;
+       u16 __reserved1;
+#endif
+       u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
+};
+
+/*
+ * Per-port congestion management variables
+ */
+struct cmng_struct_per_port {
+       struct rate_shaping_vars_per_port rs_vars;
+       struct fairness_vars_per_port fair_vars;
+       struct safc_struct_per_port safc_vars;
+       struct cmng_flags_per_port flags;
+};
+
+
+/*
+ * Dynamic host coalescing init parameters
+ */
+struct dynamic_hc_config {
+       u32 threshold[3];
+       u8 shift_per_protocol[HC_USTORM_SB_NUM_INDICES];
+       u8 hc_timeout0[HC_USTORM_SB_NUM_INDICES];
+       u8 hc_timeout1[HC_USTORM_SB_NUM_INDICES];
+       u8 hc_timeout2[HC_USTORM_SB_NUM_INDICES];
+       u8 hc_timeout3[HC_USTORM_SB_NUM_INDICES];
+};
+
+
+/*
+ * Protocol-common statistics collected by the Xstorm (per client)
+ */
+struct xstorm_per_client_stats {
+       __le32 reserved0;
+       __le32 unicast_pkts_sent;
+       struct regpair unicast_bytes_sent;
+       struct regpair multicast_bytes_sent;
+       __le32 multicast_pkts_sent;
+       __le32 broadcast_pkts_sent;
+       struct regpair broadcast_bytes_sent;
+       __le16 stats_counter;
+       __le16 reserved1;
+       __le32 reserved2;
+};
+
+/*
+ * Common statistics collected by the Xstorm (per port)
+ */
+struct xstorm_common_stats {
+ struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
+};
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per port)
+ */
+struct tstorm_per_port_stats {
+       __le32 mac_filter_discard;
+       __le32 xxoverflow_discard;
+       __le32 brb_truncate_discard;
+       __le32 mac_discard;
+};
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per client)
+ */
+struct tstorm_per_client_stats {
+       struct regpair rcv_unicast_bytes;
+       struct regpair rcv_broadcast_bytes;
+       struct regpair rcv_multicast_bytes;
+       struct regpair rcv_error_bytes;
+       __le32 checksum_discard;
+       __le32 packets_too_big_discard;
+       __le32 rcv_unicast_pkts;
+       __le32 rcv_broadcast_pkts;
+       __le32 rcv_multicast_pkts;
+       __le32 no_buff_discard;
+       __le32 ttl0_discard;
+       __le16 stats_counter;
+       __le16 reserved0;
+};
+
+/*
+ * Protocol-common statistics collected by the Tstorm
+ */
+struct tstorm_common_stats {
+       struct tstorm_per_port_stats port_statistics;
+ struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
+};
+
+/*
+ * Protocol-common statistics collected by the Ustorm (per client)
+ */
+struct ustorm_per_client_stats {
+       struct regpair ucast_no_buff_bytes;
+       struct regpair mcast_no_buff_bytes;
+       struct regpair bcast_no_buff_bytes;
+       __le32 ucast_no_buff_pkts;
+       __le32 mcast_no_buff_pkts;
+       __le32 bcast_no_buff_pkts;
+       __le16 stats_counter;
+       __le16 reserved0;
+};
+
+/*
+ * Protocol-common statistics collected by the Ustorm
+ */
+struct ustorm_common_stats {
+ struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
+};
+
+/*
+ * Eth statistics query structure for the eth_stats_query ramrod
+ */
+struct eth_stats_query {
+       struct xstorm_common_stats xstorm_common;
+       struct tstorm_common_stats tstorm_common;
+       struct ustorm_common_stats ustorm_common;
+};
+
+
+/*
+ * per-vnic fairness variables
+ */
+struct fairness_vars_per_vn {
+       u32 cos_credit_delta[MAX_COS_NUMBER];
+       u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
+       u32 vn_credit_delta;
+       u32 __reserved0;
+};
+
+
+/*
+ * FW version stored in the Xstorm RAM
+ */
+struct fw_version {
+#if defined(__BIG_ENDIAN)
+       u8 engineering;
+       u8 revision;
+       u8 minor;
+       u8 major;
+#elif defined(__LITTLE_ENDIAN)
+       u8 major;
+       u8 minor;
+       u8 revision;
+       u8 engineering;
+#endif
+       u32 flags;
+#define FW_VERSION_OPTIMIZED (0x1<<0)
+#define FW_VERSION_OPTIMIZED_SHIFT 0
+#define FW_VERSION_BIG_ENDIEN (0x1<<1)
+#define FW_VERSION_BIG_ENDIEN_SHIFT 1
+#define FW_VERSION_CHIP_VERSION (0x3<<2)
+#define FW_VERSION_CHIP_VERSION_SHIFT 2
+#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
+#define __FW_VERSION_RESERVED_SHIFT 4
+};
+
+
+/*
+ * FW version stored in first line of pram
+ */
+struct pram_fw_version {
+       u8 major;
+       u8 minor;
+       u8 revision;
+       u8 engineering;
+       u8 flags;
+#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
+#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
+#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
+#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
+#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
+#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
+#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
+#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
+#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
+#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
+};
+
+
+/*
+ * The send queue element
+ */
+struct protocol_common_spe {
+       struct spe_hdr hdr;
+       struct regpair phy_address;
+};
+
+
+/*
+ * a single rate shaping counter. can be used as protocol or vnic counter
+ */
+struct rate_shaping_counter {
+       u32 quota;
+#if defined(__BIG_ENDIAN)
+       u16 __reserved0;
+       u16 rate;
+#elif defined(__LITTLE_ENDIAN)
+       u16 rate;
+       u16 __reserved0;
+#endif
+};
+
+
+/*
+ * per-vnic rate shaping variables
+ */
+struct rate_shaping_vars_per_vn {
+       struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
+       struct rate_shaping_counter vn_counter;
+};
+
+
+/*
+ * The send queue element
+ */
+struct slow_path_element {
+       struct spe_hdr hdr;
+       u8 protocol_data[8];
+};
+
+
+/*
+ * eth/toe flags that indicate if to query
+ */
+struct stats_indication_flags {
+       u32 collect_eth;
+       u32 collect_toe;
+};
+
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init.h        1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init.h     2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,152 @@
+/* bnx2x_init.h: Broadcom Everest network driver.
+ *               Structures and macroes needed during the initialization.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Eliezer Tamir
+ * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
+ */
+
+#ifndef BNX2X_INIT_H
+#define BNX2X_INIT_H
+
+/* RAM0 size in bytes */
+#define STORM_INTMEM_SIZE_E1           0x5800
+#define STORM_INTMEM_SIZE_E1H          0x10000
+#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
+                                                   STORM_INTMEM_SIZE_E1H) / 4)
+
+
+/* Init operation types and structures */
+/* Common for both E1 and E1H */
+#define OP_RD                  0x1 /* read single register */
+#define OP_WR                  0x2 /* write single register */
+#define OP_IW                  0x3 /* write single register using mailbox */
+#define OP_SW                  0x4 /* copy a string to the device */
+#define OP_SI                  0x5 /* copy a string using mailbox */
+#define OP_ZR                  0x6 /* clear memory */
+#define OP_ZP                  0x7 /* unzip then copy with DMAE */
+#define OP_WR_64               0x8 /* write 64 bit pattern */
+#define OP_WB                  0x9 /* copy a string using DMAE */
+
+/* FPGA and EMUL specific operations */
+#define OP_WR_EMUL             0xa /* write single register on Emulation */
+#define OP_WR_FPGA             0xb /* write single register on FPGA */
+#define OP_WR_ASIC             0xc /* write single register on ASIC */
+
+/* Init stages */
+/* Never reorder stages !!! */
+#define COMMON_STAGE           0
+#define PORT0_STAGE            1
+#define PORT1_STAGE            2
+#define FUNC0_STAGE            3
+#define FUNC1_STAGE            4
+#define FUNC2_STAGE            5
+#define FUNC3_STAGE            6
+#define FUNC4_STAGE            7
+#define FUNC5_STAGE            8
+#define FUNC6_STAGE            9
+#define FUNC7_STAGE            10
+#define STAGE_IDX_MAX          11
+
+#define STAGE_START            0
+#define STAGE_END              1
+
+
+/* Indices of blocks */
+#define PRS_BLOCK              0
+#define SRCH_BLOCK             1
+#define TSDM_BLOCK             2
+#define TCM_BLOCK              3
+#define BRB1_BLOCK             4
+#define TSEM_BLOCK             5
+#define PXPCS_BLOCK            6
+#define EMAC0_BLOCK            7
+#define EMAC1_BLOCK            8
+#define DBU_BLOCK              9
+#define MISC_BLOCK             10
+#define DBG_BLOCK              11
+#define NIG_BLOCK              12
+#define MCP_BLOCK              13
+#define UPB_BLOCK              14
+#define CSDM_BLOCK             15
+#define USDM_BLOCK             16
+#define CCM_BLOCK              17
+#define UCM_BLOCK              18
+#define USEM_BLOCK             19
+#define CSEM_BLOCK             20
+#define XPB_BLOCK              21
+#define DQ_BLOCK               22
+#define TIMERS_BLOCK           23
+#define XSDM_BLOCK             24
+#define QM_BLOCK               25
+#define PBF_BLOCK              26
+#define XCM_BLOCK              27
+#define XSEM_BLOCK             28
+#define CDU_BLOCK              29
+#define DMAE_BLOCK             30
+#define PXP_BLOCK              31
+#define CFC_BLOCK              32
+#define HC_BLOCK               33
+#define PXP2_BLOCK             34
+#define MISC_AEU_BLOCK         35
+#define PGLUE_B_BLOCK          36
+#define IGU_BLOCK              37
+
+
+/* Returns the index of start or end of a specific block stage in ops array*/
+#define BLOCK_OPS_IDX(block, stage, end) \
+                       (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
+
+
+struct raw_op {
+       u32 op:8;
+       u32 offset:24;
+       u32 raw_data;
+};
+
+struct op_read {
+       u32 op:8;
+       u32 offset:24;
+       u32 pad;
+};
+
+struct op_write {
+       u32 op:8;
+       u32 offset:24;
+       u32 val;
+};
+
+struct op_string_write {
+       u32 op:8;
+       u32 offset:24;
+#ifdef __LITTLE_ENDIAN
+       u16 data_off;
+       u16 data_len;
+#else /* __BIG_ENDIAN */
+       u16 data_len;
+       u16 data_off;
+#endif
+};
+
+struct op_zero {
+       u32 op:8;
+       u32 offset:24;
+       u32 len;
+};
+
+union init_op {
+       struct op_read          read;
+       struct op_write         write;
+       struct op_string_write  str_wr;
+       struct op_zero          zero;
+       struct raw_op           raw;
+};
+
+#endif /* BNX2X_INIT_H */
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init_ops.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init_ops.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init_ops.h    1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init_ops.h 2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,501 @@
+/* bnx2x_init_ops.h: Broadcom Everest network driver.
+ *               Static functions needed during the initialization.
+ *               This file is "included" in bnx2x_main.c.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Vladislav Zolotarov <vladz@broadcom.com>
+ */
+
+#ifndef BNX2X_INIT_OPS_H
+#define BNX2X_INIT_OPS_H
+
+static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
+
+
+static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
+                             u32 len)
+{
+       u32 i;
+
+       for (i = 0; i < len; i++)
+               REG_WR(bp, addr + i*4, data[i]);
+}
+
+static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
+                             u32 len)
+{
+       u32 i;
+
+       for (i = 0; i < len; i++)
+               REG_WR_IND(bp, addr + i*4, data[i]);
+}
+
+static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
+{
+       if (bp->dmae_ready)
+               bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
+       else
+               bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
+}
+
+static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
+{
+       u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
+       u32 buf_len32 = buf_len/4;
+       u32 i;
+
+       memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
+
+       for (i = 0; i < len; i += buf_len32) {
+               u32 cur_len = min(buf_len32, len - i);
+
+               bnx2x_write_big_buf(bp, addr + i*4, cur_len);
+       }
+}
+
+static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
+                            u32 len64)
+{
+       u32 buf_len32 = FW_BUF_SIZE/4;
+       u32 len = len64*2;
+       u64 data64 = 0;
+       u32 i;
+
+       /* 64 bit value is in a blob: first low DWORD, then high DWORD */
+       data64 = HILO_U64((*(data + 1)), (*data));
+
+       len64 = min((u32)(FW_BUF_SIZE/8), len64);
+       for (i = 0; i < len64; i++) {
+               u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
+
+               *pdata = data64;
+       }
+
+       for (i = 0; i < len; i += buf_len32) {
+               u32 cur_len = min(buf_len32, len - i);
+
+               bnx2x_write_big_buf(bp, addr + i*4, cur_len);
+       }
+}
+
+/*********************************************************
+   There are different blobs for each PRAM section.
+   In addition, each blob write operation is divided into a few operations
+   in order to decrease the amount of phys. contiguous buffer needed.
+   Thus, when we select a blob the address may be with some offset
+   from the beginning of PRAM section.
+   The same holds for the INT_TABLE sections.
+**********************************************************/
+#define IF_IS_INT_TABLE_ADDR(base, addr) \
+                       if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
+
+#define IF_IS_PRAM_ADDR(base, addr) \
+                       if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
+
+static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data)
+{
+       IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
+               data = INIT_TSEM_INT_TABLE_DATA(bp);
+       else
+               IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
+                       data = INIT_CSEM_INT_TABLE_DATA(bp);
+       else
+               IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
+                       data = INIT_USEM_INT_TABLE_DATA(bp);
+       else
+               IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
+                       data = INIT_XSEM_INT_TABLE_DATA(bp);
+       else
+               IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
+                       data = INIT_TSEM_PRAM_DATA(bp);
+       else
+               IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
+                       data = INIT_CSEM_PRAM_DATA(bp);
+       else
+               IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
+                       data = INIT_USEM_PRAM_DATA(bp);
+       else
+               IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
+                       data = INIT_XSEM_PRAM_DATA(bp);
+
+       return data;
+}
+
+static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
+{
+       if (bp->dmae_ready)
+               bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
+       else
+               bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
+}
+
+static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
+                            u32 len)
+{
+       data = (const u32 *)bnx2x_sel_blob(bp, addr, (const u8 *)data);
+
+       if (bp->dmae_ready)
+               VIRT_WR_DMAE_LEN(bp, data, addr, len);
+       else
+               bnx2x_init_ind_wr(bp, addr, data, len);
+}
+
+static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off)
+{
+       const u8 *data = NULL;
+       int rc;
+       u32 i;
+
+       data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
+
+       rc = bnx2x_gunzip(bp, data, len);
+       if (rc)
+               return;
+
+       /* gunzip_outlen is in dwords */
+       len = GUNZIP_OUTLEN(bp);
+       for (i = 0; i < len; i++)
+               ((u32 *)GUNZIP_BUF(bp))[i] =
+                               cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
+
+       bnx2x_write_big_buf_wb(bp, addr, len);
+}
+
+static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
+{
+       u16 op_start =
+               INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block,stage,STAGE_START)];
+       u16 op_end =
+               INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block,stage,STAGE_END)];
+       union init_op *op;
+       int hw_wr;
+       u32 i, op_type, addr, len;
+       const u32 *data, *data_base;
+
+       /* If empty block */
+       if (op_start == op_end)
+               return;
+
+       if (CHIP_REV_IS_FPGA(bp))
+               hw_wr = OP_WR_FPGA;
+       else if (CHIP_REV_IS_EMUL(bp))
+               hw_wr = OP_WR_EMUL;
+       else
+               hw_wr = OP_WR_ASIC;
+
+       data_base = INIT_DATA(bp);
+
+       for (i = op_start; i < op_end; i++) {
+
+               op = (union init_op *)&(INIT_OPS(bp)[i]);
+
+               op_type = op->str_wr.op;
+               addr = op->str_wr.offset;
+               len = op->str_wr.data_len;
+               data = data_base + op->str_wr.data_off;
+
+               /* HW/EMUL specific */
+               if ((op_type > OP_WB) && (op_type == hw_wr))
+                       op_type = OP_WR;
+
+               switch (op_type) {
+               case OP_RD:
+                       REG_RD(bp, addr);
+                       break;
+               case OP_WR:
+                       REG_WR(bp, addr, op->write.val);
+                       break;
+               case OP_SW:
+                       bnx2x_init_str_wr(bp, addr, data, len);
+                       break;
+               case OP_WB:
+                       bnx2x_init_wr_wb(bp, addr, data, len);
+                       break;
+               case OP_SI:
+                       bnx2x_init_ind_wr(bp, addr, data, len);
+                       break;
+               case OP_ZR:
+                       bnx2x_init_fill(bp, addr, 0, op->zero.len);
+                       break;
+               case OP_ZP:
+                       bnx2x_init_wr_zp(bp, addr, len,
+                                        op->str_wr.data_off);
+                       break;
+               case OP_WR_64:
+                       bnx2x_init_wr_64(bp, addr, data, len);
+                       break;
+               default:
+                       /* happens whenever an op is of a diff HW */
+                       break;
+               }
+       }
+}
+
+
+/****************************************************************************
+* PXP Arbiter
+****************************************************************************/
+/*
+ * This code configures the PCI read/write arbiter
+ * which implements a weighted round robin
+ * between the virtual queues in the chip.
+ *
+ * The values were derived for each PCI max payload and max request size.
+ * since max payload and max request size are only known at run time,
+ * this is done as a separate init stage.
+ */
+
+#define NUM_WR_Q                       13
+#define NUM_RD_Q                       29
+#define MAX_RD_ORD                     3
+#define MAX_WR_ORD                     2
+
+/* configuration for one arbiter queue */
+struct arb_line {
+       int l;
+       int add;
+       int ubound;
+};
+
+/* derived configuration for each read queue for each max request size */
+static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
+/* 1 */        { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+       { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
+       { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
+       { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
+       { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+/* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+/* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+       { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
+};
+
+/* derived configuration for each write queue for each max request size */
+static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
+/* 1 */        { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
+       { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
+       { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+       { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+       { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+       { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+       { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
+       { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+       { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+/* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
+       { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
+       { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
+       { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
+};
+
+/* register addresses for read queues */
+static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
+/* 1 */        {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
+               PXP2_REG_RQ_BW_RD_UBOUND0},
+       {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+               PXP2_REG_PSWRQ_BW_UB1},
+       {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+               PXP2_REG_PSWRQ_BW_UB2},
+       {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+               PXP2_REG_PSWRQ_BW_UB3},
+       {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
+               PXP2_REG_RQ_BW_RD_UBOUND4},
+       {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
+               PXP2_REG_RQ_BW_RD_UBOUND5},
+       {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+               PXP2_REG_PSWRQ_BW_UB6},
+       {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+               PXP2_REG_PSWRQ_BW_UB7},
+       {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+               PXP2_REG_PSWRQ_BW_UB8},
+/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+               PXP2_REG_PSWRQ_BW_UB9},
+       {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+               PXP2_REG_PSWRQ_BW_UB10},
+       {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+               PXP2_REG_PSWRQ_BW_UB11},
+       {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
+               PXP2_REG_RQ_BW_RD_UBOUND12},
+       {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
+               PXP2_REG_RQ_BW_RD_UBOUND13},
+       {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
+               PXP2_REG_RQ_BW_RD_UBOUND14},
+       {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
+               PXP2_REG_RQ_BW_RD_UBOUND15},
+       {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
+               PXP2_REG_RQ_BW_RD_UBOUND16},
+       {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
+               PXP2_REG_RQ_BW_RD_UBOUND17},
+       {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
+               PXP2_REG_RQ_BW_RD_UBOUND18},
+/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
+               PXP2_REG_RQ_BW_RD_UBOUND19},
+       {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
+               PXP2_REG_RQ_BW_RD_UBOUND20},
+       {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
+               PXP2_REG_RQ_BW_RD_UBOUND22},
+       {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
+               PXP2_REG_RQ_BW_RD_UBOUND23},
+       {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
+               PXP2_REG_RQ_BW_RD_UBOUND24},
+       {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
+               PXP2_REG_RQ_BW_RD_UBOUND25},
+       {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
+               PXP2_REG_RQ_BW_RD_UBOUND26},
+       {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
+               PXP2_REG_RQ_BW_RD_UBOUND27},
+       {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+               PXP2_REG_PSWRQ_BW_UB28}
+};
+
+/* register addresses for write queues */
+static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
+/* 1 */        {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+               PXP2_REG_PSWRQ_BW_UB1},
+       {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+               PXP2_REG_PSWRQ_BW_UB2},
+       {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+               PXP2_REG_PSWRQ_BW_UB3},
+       {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+               PXP2_REG_PSWRQ_BW_UB6},
+       {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+               PXP2_REG_PSWRQ_BW_UB7},
+       {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+               PXP2_REG_PSWRQ_BW_UB8},
+       {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+               PXP2_REG_PSWRQ_BW_UB9},
+       {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+               PXP2_REG_PSWRQ_BW_UB10},
+       {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+               PXP2_REG_PSWRQ_BW_UB11},
+/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+               PXP2_REG_PSWRQ_BW_UB28},
+       {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
+               PXP2_REG_RQ_BW_WR_UBOUND29},
+       {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
+               PXP2_REG_RQ_BW_WR_UBOUND30}
+};
+
+static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order)
+{
+       u32 val, i;
+
+       if (r_order > MAX_RD_ORD) {
+               DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",
+                  r_order, MAX_RD_ORD);
+               r_order = MAX_RD_ORD;
+       }
+       if (w_order > MAX_WR_ORD) {
+               DP(NETIF_MSG_HW, "write order of %d  order adjusted to %d\n",
+                  w_order, MAX_WR_ORD);
+               w_order = MAX_WR_ORD;
+       }
+       if (CHIP_REV_IS_FPGA(bp)) {
+               DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
+               w_order = 0;
+       }
+       DP(NETIF_MSG_HW, "read order %d  write order %d\n", r_order, w_order);
+
+       for (i = 0; i < NUM_RD_Q-1; i++) {
+               REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
+               REG_WR(bp, read_arb_addr[i].add,
+                      read_arb_data[i][r_order].add);
+               REG_WR(bp, read_arb_addr[i].ubound,
+                      read_arb_data[i][r_order].ubound);
+       }
+
+       for (i = 0; i < NUM_WR_Q-1; i++) {
+               if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
+                   (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
+
+                       REG_WR(bp, write_arb_addr[i].l,
+                              write_arb_data[i][w_order].l);
+
+                       REG_WR(bp, write_arb_addr[i].add,
+                              write_arb_data[i][w_order].add);
+
+                       REG_WR(bp, write_arb_addr[i].ubound,
+                              write_arb_data[i][w_order].ubound);
+               } else {
+
+                       val = REG_RD(bp, write_arb_addr[i].l);
+                       REG_WR(bp, write_arb_addr[i].l,
+                              val | (write_arb_data[i][w_order].l << 10));
+
+                       val = REG_RD(bp, write_arb_addr[i].add);
+                       REG_WR(bp, write_arb_addr[i].add,
+                              val | (write_arb_data[i][w_order].add << 10));
+
+                       val = REG_RD(bp, write_arb_addr[i].ubound);
+                       REG_WR(bp, write_arb_addr[i].ubound,
+                              val | (write_arb_data[i][w_order].ubound << 7));
+               }
+       }
+
+       val =  write_arb_data[NUM_WR_Q-1][w_order].add;
+       val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
+       val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
+       REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
+
+       val =  read_arb_data[NUM_RD_Q-1][r_order].add;
+       val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
+       val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
+       REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
+
+       REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
+       REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
+       REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
+       REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
+
+       if (r_order == MAX_RD_ORD)
+               REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
+
+       REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
+
+       if (CHIP_IS_E1H(bp)) {
+       /*    MPS      w_order     optimal TH      presently TH
+        *    128         0             0               2
+        *    256         1             1               3
+        *    >=512       2             2               3
+        */
+               val = ((w_order == 0) ? 2 : 3);
+               REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
+               REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
+               REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
+       }
+}
+
+#endif /* BNX2X_INIT_OPS_H */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init_values_e1.c linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init_values_e1.c
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init_values_e1.c      1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init_values_e1.c   2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,13901 @@
+/* init_ops array contains the list of operations needed to initialize the chip.
+ *
+ * For each block in the chip there are three init stages:
+ * common - HW used by both ports,
+ * port1 and port2 - initialization for a specific Ethernet port.
+ * When a port is opened or closed, the management CPU tells the driver
+ * whether to init/disable common HW in addition to the port HW.
+ * This way the first port going up will first initializes the common HW,
+ * and the last port going down also resets the common HW
+ *
+ * For each init stage/block there is a list of actions needed in a format:
+ * {operation, register, data}
+ * where:
+ * OP_WR - write a value to the chip.
+ * OP_RD - read a register (usually a clear on read register).
+ * OP_SW - string write, write a section of consecutive addresses to the chip.
+ * OP_SI - copy a string using indirect writes.
+ * OP_ZR - clear a range of memory.
+ * OP_ZP - unzip and copy using DMAE.
+ * OP_WB - string copy using DMAE.
+ *
+ * The #defines mark the stages.
+ *
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include "bnx2x_compat.h"
+#include "bnx2x_init.h"
+#include "bnx2x.h"
+
+
+static const struct raw_op init_ops_e1[] = {
+/* #define PRS_COMMON_START        0 */
+       {OP_WR, PRS_REG_INC_VALUE, 0xf},
+       {OP_WR, PRS_REG_EVENT_ID_1, 0x45},
+       {OP_WR, PRS_REG_EVENT_ID_2, 0x84},
+       {OP_WR, PRS_REG_EVENT_ID_3, 0x6},
+       {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
+       {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
+       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
+       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
+       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
+       {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
+       {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
+       {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
+       {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
+       {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
+       {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
+       {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
+       {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
+       {OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
+/* #define PRS_COMMON_END          1 */
+/* #define TSDM_COMMON_START       44 */
+       {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
+       {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
+       {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
+       {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2},
+       {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
+       {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
+       {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
+       {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+       {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
+/* #define TSDM_COMMON_END         45 */
+/* #define TCM_COMMON_START        66 */
+       {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
+       {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
+       {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
+       {OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
+       {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
+       {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
+       {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
+       {OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
+       {OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
+       {OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_CP_WEIGHT, 0x0},
+       {OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
+       {OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_TM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
+       {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, TCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, TCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
+       {OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
+       {OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
+       {OP_ZR, TCM_REG_XX_TABLE, 0xa},
+       {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
+       {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4},
+       {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
+       {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd},
+       {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7},
+       {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27},
+       {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7},
+       {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27},
+       {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7},
+       {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27},
+       {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
+       {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
+       {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
+       {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
+       {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
+       {OP_WR, TCM_REG_TSDM_IFEN, 0x1},
+       {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
+       {OP_WR, TCM_REG_PRS_IFEN, 0x1},
+       {OP_WR, TCM_REG_PBF_IFEN, 0x1},
+       {OP_WR, TCM_REG_USEM_IFEN, 0x1},
+       {OP_WR, TCM_REG_CSEM_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
+/* #define TCM_COMMON_END          67 */
+/* #define BRB1_COMMON_START       88 */
+       {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
+       {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
+       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
+       {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
+       {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
+/* #define BRB1_COMMON_END         89 */
+/* #define BRB1_PORT0_START        90 */
+       {OP_WR, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
+       {OP_WR, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
+       {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
+       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
+/* #define BRB1_PORT0_END          91 */
+/* #define BRB1_PORT1_START        92 */
+       {OP_WR, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
+       {OP_WR, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
+       {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
+       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
+/* #define BRB1_PORT1_END          93 */
+/* #define TSEM_COMMON_START       110 */
+       {OP_ZP, TSEM_REG_INT_TABLE, 0x960000},
+       {OP_WR_64, TSEM_REG_INT_TABLE + 0x360, 0x140223},
+       {OP_ZP, TSEM_REG_PRAM, 0x34b80000},
+       {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x34e90d2f},
+       {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x9dd1a6a},
+       {OP_WR_64, TSEM_REG_PRAM + 0x11400, 0x5d800225},
+       {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, TSEM_REG_TS_0_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_1_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_2_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_3_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_4_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_5_AS, 0x3},
+       {OP_WR, TSEM_REG_TS_6_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_7_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_8_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_9_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_10_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_11_AS, 0x3},
+       {OP_WR, TSEM_REG_TS_12_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_13_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_14_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_15_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_16_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, TSEM_REG_TS_18_AS, 0x2},
+       {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, TSEM_REG_THREADS_LIST, 0xff},
+       {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+       {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+       {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+       {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x23c8, 0x181},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x604, 0x10227},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1e38, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1e30, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x50228},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x8022d},
+/* #define TSEM_COMMON_END         111 */
+/* #define TSEM_PORT0_START        112 */
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x124},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x4920, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1500, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50235},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1580, 0x14},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x9c0, 0x48},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x2023a},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2c28, 0x2},
+/* #define TSEM_PORT0_END          113 */
+/* #define TSEM_PORT1_START        114 */
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4490, 0x124},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x4924, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1540, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x1540 + 0x8, 0x5023c},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1540 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x15d0, 0x14},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xae0, 0x48},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20241},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2c30, 0x2},
+/* #define TSEM_PORT1_END          115 */
+/* #define MISC_COMMON_START       220 */
+       {OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
+       {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
+       {OP_WR, MISC_REG_SPIO, 0xff000000},
+/* #define MISC_COMMON_END         221 */
+/* #define NIG_COMMON_START        264 */
+       {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
+       {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
+       {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
+       {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
+       {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
+/* #define NIG_COMMON_END          265 */
+/* #define NIG_PORT0_START         266 */
+       {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
+       {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
+       {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
+       {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
+       {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
+       {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
+       {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
+       {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
+       {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
+       {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
+       {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
+/* #define NIG_PORT0_END           267 */
+/* #define NIG_PORT1_START         268 */
+       {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
+       {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
+       {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
+       {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
+       {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
+       {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
+       {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
+       {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
+       {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
+       {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
+       {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
+/* #define NIG_PORT1_END           269 */
+/* #define UPB_COMMON_START        308 */
+       {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
+/* #define UPB_COMMON_END          309 */
+/* #define CSDM_COMMON_START       330 */
+       {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
+       {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
+       {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b},
+       {OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1},
+       {OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10},
+       {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+       {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
+/* #define CSDM_COMMON_END         331 */
+/* #define USDM_COMMON_START       352 */
+       {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x365},
+       {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x354},
+       {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x358},
+       {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x375},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
+       {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
+       {OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x5e},
+       {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
+       {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f},
+       {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+       {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
+/* #define USDM_COMMON_END         353 */
+/* #define CCM_COMMON_START        374 */
+       {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
+       {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
+       {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
+       {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
+       {OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
+       {OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
+       {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
+       {OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
+       {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
+       {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
+       {OP_WR, CCM_REG_INV_DONE_Q, 0x1},
+       {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, CCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, CCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
+       {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
+       {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
+       {OP_ZR, CCM_REG_XX_TABLE, 0x12},
+       {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x240243},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
+       {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
+       {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
+       {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc},
+       {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xc},
+       {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2c},
+       {OP_WR, CCM_REG_PHYS_QNUM3_0, 0xc},
+       {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x2c},
+       {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
+       {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
+       {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
+       {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
+       {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
+       {OP_WR, CCM_REG_CSDM_IFEN, 0x1},
+       {OP_WR, CCM_REG_TSEM_IFEN, 0x1},
+       {OP_WR, CCM_REG_XSEM_IFEN, 0x1},
+       {OP_WR, CCM_REG_USEM_IFEN, 0x1},
+       {OP_WR, CCM_REG_PBF_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
+/* #define CCM_COMMON_END          375 */
+/* #define UCM_COMMON_START        396 */
+       {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
+       {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
+       {OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
+       {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
+       {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
+       {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
+       {OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
+       {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
+       {OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_CP_WEIGHT, 0x0},
+       {OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
+       {OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_TM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
+       {OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
+       {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, UCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, UCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
+       {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
+       {OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
+       {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
+       {OP_ZR, UCM_REG_XX_TABLE, 0x12},
+       {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b0267},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
+       {OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4},
+       {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
+       {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf},
+       {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe},
+       {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e},
+       {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
+       {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
+       {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
+       {OP_WR, UCM_REG_USDM_IFEN, 0x1},
+       {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
+       {OP_WR, UCM_REG_TSEM_IFEN, 0x1},
+       {OP_WR, UCM_REG_CSEM_IFEN, 0x1},
+       {OP_WR, UCM_REG_XSEM_IFEN, 0x1},
+       {OP_WR, UCM_REG_DORQ_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
+/* #define UCM_COMMON_END          397 */
+/* #define USEM_COMMON_START       418 */
+       {OP_ZP, USEM_REG_INT_TABLE, 0xc90000},
+       {OP_WR_64, USEM_REG_INT_TABLE + 0x368, 0x130282},
+       {OP_ZP, USEM_REG_PRAM, 0x34120000},
+       {OP_ZP, USEM_REG_PRAM + 0x8000, 0x37b70d05},
+       {OP_ZP, USEM_REG_PRAM + 0x10000, 0x2e7d1af3},
+       {OP_WR_64, USEM_REG_PRAM + 0x16f40, 0x52180284},
+       {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, USEM_REG_TS_0_AS, 0x0},
+       {OP_WR, USEM_REG_TS_1_AS, 0x1},
+       {OP_WR, USEM_REG_TS_2_AS, 0x4},
+       {OP_WR, USEM_REG_TS_3_AS, 0x0},
+       {OP_WR, USEM_REG_TS_4_AS, 0x1},
+       {OP_WR, USEM_REG_TS_5_AS, 0x3},
+       {OP_WR, USEM_REG_TS_6_AS, 0x0},
+       {OP_WR, USEM_REG_TS_7_AS, 0x1},
+       {OP_WR, USEM_REG_TS_8_AS, 0x4},
+       {OP_WR, USEM_REG_TS_9_AS, 0x0},
+       {OP_WR, USEM_REG_TS_10_AS, 0x1},
+       {OP_WR, USEM_REG_TS_11_AS, 0x3},
+       {OP_WR, USEM_REG_TS_12_AS, 0x0},
+       {OP_WR, USEM_REG_TS_13_AS, 0x1},
+       {OP_WR, USEM_REG_TS_14_AS, 0x4},
+       {OP_WR, USEM_REG_TS_15_AS, 0x0},
+       {OP_WR, USEM_REG_TS_16_AS, 0x4},
+       {OP_WR, USEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, USEM_REG_TS_18_AS, 0x2},
+       {OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, USEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, USEM_REG_THREADS_LIST, 0xffff},
+       {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+       {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
+       {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+       {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1aa0, 0xc2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0x40},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5098, 0x4},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x5},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x5080 + 0x14, 0x10286},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x2830, 0x20287},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x100289},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x100299},
+/* #define USEM_COMMON_END         419 */
+/* #define USEM_PORT0_START        420 */
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1500, 0xb4},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x1dc8, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0xd8},
+/* #define USEM_PORT0_END          421 */
+/* #define USEM_PORT1_START        422 */
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x17d0, 0xb4},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x1dcc, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4360, 0xd8},
+/* #define USEM_PORT1_END          423 */
+/* #define CSEM_COMMON_START       440 */
+       {OP_ZP, CSEM_REG_INT_TABLE, 0x920000},
+       {OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002a9},
+       {OP_ZP, CSEM_REG_PRAM, 0x2ccf0000},
+       {OP_ZP, CSEM_REG_PRAM + 0x8000, 0x2ae50b34},
+       {OP_WR_64, CSEM_REG_PRAM + 0xdc60, 0x62da02ab},
+       {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, CSEM_REG_TS_0_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_1_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_2_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_3_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_4_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_5_AS, 0x3},
+       {OP_WR, CSEM_REG_TS_6_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_7_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_8_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_9_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_10_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_11_AS, 0x3},
+       {OP_WR, CSEM_REG_TS_12_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_13_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_14_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_15_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_16_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, CSEM_REG_TS_18_AS, 0x2},
+       {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
+       {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
+       {OP_SW, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802ad},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
+       {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002b5},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+       {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002c5},
+/* #define CSEM_COMMON_END         441 */
+/* #define CSEM_PORT0_START        442 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3040, 0xa0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3540, 0x10},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x36c0, 0x30},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4000, 0x200},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x35c0, 0x20},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3840, 0x30},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x5118, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2300, 0xe},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
+/* #define CSEM_PORT0_END          443 */
+/* #define CSEM_PORT1_START        444 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x32c0, 0xa0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3580, 0x10},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3780, 0x30},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4800, 0x200},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3640, 0x20},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3900, 0x30},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3020, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x511c, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2338, 0xe},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
+/* #define CSEM_PORT1_END          445 */
+/* #define XPB_COMMON_START        462 */
+       {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28},
+/* #define XPB_COMMON_END          463 */
+/* #define DQ_COMMON_START         484 */
+       {OP_WR, DORQ_REG_MODE_ACT, 0x2},
+       {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
+       {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
+       {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
+       {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
+       {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
+       {OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
+       {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
+       {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
+       {OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
+       {OP_WR, DORQ_REG_AGG_CMD1, 0x80},
+       {OP_WR, DORQ_REG_AGG_CMD2, 0x81},
+       {OP_WR, DORQ_REG_AGG_CMD3, 0x80},
+       {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
+       {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
+       {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
+       {OP_WR, DORQ_REG_REGN, 0x7c1004},
+       {OP_WR, DORQ_REG_IF_EN, 0xf},
+/* #define DQ_COMMON_END           485 */
+/* #define TIMERS_COMMON_START     506 */
+       {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
+       {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
+       {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
+       {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
+       {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
+       {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
+       {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
+       {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
+       {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x1},
+       {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
+       {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
+       {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
+       {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
+       {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
+       {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
+       {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
+       {OP_WR, TM_REG_EN_TIMERS, 0x1},
+       {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
+       {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
+       {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
+       {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
+/* #define TIMERS_COMMON_END       507 */
+/* #define TIMERS_PORT0_START      508 */
+       {OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0},
+       {OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0},
+       {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT0_END        509 */
+/* #define TIMERS_PORT1_START      510 */
+       {OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0},
+       {OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0},
+       {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT1_END        511 */
+/* #define XSDM_COMMON_START       528 */
+       {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
+       {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
+       {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x604},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d},
+       {OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52},
+       {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
+       {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
+       {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+       {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
+/* #define XSDM_COMMON_END         529 */
+/* #define QM_COMMON_START         550 */
+       {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
+       {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
+       {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
+       {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
+       {OP_WR, QM_REG_PCIREQAT, 0x2},
+       {OP_WR, QM_REG_CMINITCRD_0, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_1, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_2, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_3, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_4, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_5, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_6, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_7, 0x4},
+       {OP_WR, QM_REG_OUTLDREQ, 0x4},
+       {OP_WR, QM_REG_CTXREG_0, 0x7c},
+       {OP_WR, QM_REG_CTXREG_1, 0x3d},
+       {OP_WR, QM_REG_CTXREG_2, 0x3f},
+       {OP_WR, QM_REG_CTXREG_3, 0x9c},
+       {OP_WR, QM_REG_ENSEC, 0x7},
+       {OP_ZR, QM_REG_QVOQIDX_0, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_5, 0x0},
+       {OP_WR, QM_REG_QVOQIDX_6, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_7, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_8, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_9, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_10, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_11, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_12, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_13, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_14, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_15, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_16, 0x0},
+       {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
+       {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
+       {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
+       {OP_ZR, QM_REG_QVOQIDX_21, 0x4},
+       {OP_WR, QM_REG_WRRWEIGHTS_5, 0x1010101},
+       {OP_ZR, QM_REG_QVOQIDX_25, 0x4},
+       {OP_WR, QM_REG_WRRWEIGHTS_6, 0x1010101},
+       {OP_ZR, QM_REG_QVOQIDX_29, 0x3},
+       {OP_WR, QM_REG_QVOQIDX_32, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_33, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_34, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_35, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_36, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_37, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_38, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_39, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_40, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_41, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_42, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_43, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_44, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_45, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_46, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_47, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_48, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
+       {OP_WR, QM_REG_QVOQIDX_49, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_50, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_51, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_52, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_53, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_54, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_55, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_56, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_13, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_57, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_58, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_59, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_60, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_14, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_61, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_62, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_63, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010101},
+       {OP_WR, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
+       {OP_ZR, QM_REG_VOQQMASK_0_MSB, 0x2},
+       {OP_WR, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
+       {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x100},
+       {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x100},
+       {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
+       {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc0},
+       {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc0},
+       {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e00},
+       {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e00},
+       {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x4000},
+       {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x4000},
+       {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x8000},
+       {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x8000},
+       {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x2000},
+       {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x2000},
+       {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x7},
+       {OP_WR, QM_REG_VOQPORT_1, 0x1},
+       {OP_ZR, QM_REG_VOQPORT_2, 0xa},
+       {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
+       {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
+       {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
+       {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
+       {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
+       {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
+       {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
+       {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
+       {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
+       {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
+       {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
+       {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
+       {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
+       {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
+       {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
+       {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
+       {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
+       {OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
+       {OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
+       {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
+       {OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
+       {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
+       {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
+       {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
+       {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
+       {OP_WR, QM_REG_ENBYTECRD_LSB, 0x7},
+       {OP_WR, QM_REG_ENBYTECRD_MSB, 0x7},
+       {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
+       {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
+       {OP_WR, QM_REG_FUNCNUMSEL_LSB, 0x0},
+       {OP_WR, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
+       {OP_WR, QM_REG_CMINTEN, 0xff},
+/* #define QM_COMMON_END           551 */
+/* #define PBF_COMMON_START        572 */
+       {OP_WR, PBF_REG_INIT, 0x1},
+       {OP_WR, PBF_REG_INIT_P4, 0x1},
+       {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
+       {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
+       {OP_WR, PBF_REG_INIT_P4, 0x0},
+       {OP_WR, PBF_REG_INIT, 0x0},
+       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
+/* #define PBF_COMMON_END          573 */
+/* #define PBF_PORT0_START         574 */
+       {OP_WR, PBF_REG_INIT_P0, 0x1},
+       {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
+       {OP_WR, PBF_REG_INIT_P0, 0x0},
+       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
+/* #define PBF_PORT0_END           575 */
+/* #define PBF_PORT1_START         576 */
+       {OP_WR, PBF_REG_INIT_P1, 0x1},
+       {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
+       {OP_WR, PBF_REG_INIT_P1, 0x0},
+       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
+/* #define PBF_PORT1_END           577 */
+/* #define XCM_COMMON_START        594 */
+       {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
+       {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
+       {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
+       {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
+       {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
+       {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
+       {OP_WR, XCM_REG_STORM_WEIGHT, 0x3},
+       {OP_WR, XCM_REG_TSEM_WEIGHT, 0x6},
+       {OP_WR, XCM_REG_CSEM_WEIGHT, 0x3},
+       {OP_WR, XCM_REG_USEM_WEIGHT, 0x3},
+       {OP_WR, XCM_REG_DORQ_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_PBF_WEIGHT, 0x0},
+       {OP_WR, XCM_REG_NIG0_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_CP_WEIGHT, 0x0},
+       {OP_WR, XCM_REG_XSDM_WEIGHT, 0x6},
+       {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4},
+       {OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_TM_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
+       {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
+       {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
+       {OP_WR, XCM_REG_AUX1_Q, 0x2},
+       {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
+       {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, XCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, XCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
+       {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
+       {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
+       {OP_WR, XCM_REG_XX_MSG_NUM, 0x1f},
+       {OP_ZR, XCM_REG_XX_TABLE, 0x12},
+       {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f02d5},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
+       {OP_ZR, XCM_REG_N_SM_CTX_LD_4, 0x4},
+       {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
+       {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
+       {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
+       {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
+       {OP_WR, XCM_REG_XSDM_IFEN, 0x1},
+       {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
+       {OP_WR, XCM_REG_TSEM_IFEN, 0x1},
+       {OP_WR, XCM_REG_CSEM_IFEN, 0x1},
+       {OP_WR, XCM_REG_USEM_IFEN, 0x1},
+       {OP_WR, XCM_REG_DORQ_IFEN, 0x1},
+       {OP_WR, XCM_REG_PBF_IFEN, 0x1},
+       {OP_WR, XCM_REG_NIG0_IFEN, 0x1},
+       {OP_WR, XCM_REG_NIG1_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
+/* #define XCM_COMMON_END          595 */
+/* #define XCM_PORT0_START         596 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+/* #define XCM_PORT0_END           597 */
+/* #define XCM_PORT1_START         598 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+/* #define XCM_PORT1_END           599 */
+/* #define XSEM_COMMON_START       616 */
+       {OP_ZP, XSEM_REG_INT_TABLE, 0xb40000},
+       {OP_WR_64, XSEM_REG_INT_TABLE + 0x368, 0x1302f4},
+       {OP_ZP, XSEM_REG_PRAM, 0x35d70000},
+       {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x3a590d76},
+       {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x3b741c0d},
+       {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x226c2aeb},
+       {OP_WR_64, XSEM_REG_PRAM + 0x1c6f0, 0x472202f6},
+       {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, XSEM_REG_TS_0_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_1_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_2_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_3_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_4_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_5_AS, 0x3},
+       {OP_WR, XSEM_REG_TS_6_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_7_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_8_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_9_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_10_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_11_AS, 0x3},
+       {OP_WR, XSEM_REG_TS_12_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_13_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_14_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_15_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_16_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, XSEM_REG_TS_18_AS, 0x2},
+       {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
+       {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
+       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
+       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3c40, 0x4},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c40 + 0x10, 0x202f8},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000, 0x48},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3370, 0x202fa},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3a70, 0x402fc},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3d00, 0x20300},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x1500, 0x20302},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x100},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x1970, 0x0},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x1978, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x1960, 0x20304},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x1f48, 0x20306},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100308},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80318},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80320},
+/* #define XSEM_COMMON_END         617 */
+/* #define XSEM_PORT0_START        618 */
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3a80, 0x14},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3b20, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3378, 0xd8},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x3a38, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c58, 0x20328},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c68, 0x10032a},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x5040, 0x0},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2033a},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
+/* #define XSEM_PORT0_END          619 */
+/* #define XSEM_PORT1_START        620 */
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3ad0, 0x14},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3bb0, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x36d8, 0xd8},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x3a3c, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3c60, 0x2033c},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3ca8, 0x10033e},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x5044, 0x0},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2034e},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
+/* #define XSEM_PORT1_END          621 */
+/* #define CDU_COMMON_START        638 */
+       {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
+       {OP_WR, CDU_REG_CDU_DEBUG, 0x264},
+       {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
+       {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
+       {OP_WB, CDU_REG_L1TT, 0x2000350},
+       {OP_WB, CDU_REG_MATT, 0x200550},
+       {OP_ZR, CDU_REG_MATT + 0x80, 0x2},
+       {OP_WB, CDU_REG_MATT + 0x88, 0x60570},
+       {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
+       {OP_WR, CDU_REG_CDU_DEBUG, 0x0},
+/* #define CDU_COMMON_END          639 */
+/* #define DMAE_COMMON_START       660 */
+       {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
+       {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
+       {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
+       {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x1},
+       {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
+       {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
+/* #define DMAE_COMMON_END         661 */
+/* #define PXP_COMMON_START        682 */
+       {OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x50576},
+       {OP_WB, PXP_REG_HST_INBOUND_INT + 0x420, 0x5057b},
+       {OP_WB, PXP_REG_HST_INBOUND_INT, 0x50580},
+/* #define PXP_COMMON_END          683 */
+/* #define CFC_COMMON_START        704 */
+       {OP_WR, CFC_REG_CONTROL0, 0x10},
+       {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
+       {OP_WR, CFC_REG_INTERFACES, 0x280000},
+       {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
+       {OP_WR, CFC_REG_INTERFACES, 0x0},
+/* #define CFC_COMMON_END          705 */
+/* #define HC_COMMON_START         726 */
+       {OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
+/* #define HC_COMMON_END           727 */
+/* #define HC_PORT0_START          728 */
+       {OP_WR, HC_REG_CONFIG_0, 0x1080},
+       {OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2},
+       {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+       {OP_WR, HC_REG_LEADING_EDGE_0, 0xffff},
+       {OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff},
+       {OP_WR, HC_REG_AGG_INT_0, 0x0},
+       {OP_WR, HC_REG_ATTN_IDX, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT, 0x2},
+       {OP_WR, HC_REG_VQID_0, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+       {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+       {OP_WR, HC_REG_CONFIG_0, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_PORT0_END            729 */
+/* #define HC_PORT1_START          730 */
+       {OP_WR, HC_REG_CONFIG_1, 0x1080},
+       {OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2},
+       {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+       {OP_WR, HC_REG_LEADING_EDGE_1, 0xffff},
+       {OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff},
+       {OP_WR, HC_REG_AGG_INT_1, 0x0},
+       {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+       {OP_WR, HC_REG_VQID_1, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+       {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+       {OP_WR, HC_REG_CONFIG_1, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_PORT1_END            731 */
+/* #define PXP2_COMMON_START       748 */
+       {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340},
+       {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
+       {OP_WR, PXP2_REG_PGL_DEBUG, 0x2},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
+       {OP_ZR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x2},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ25, 0x0},
+       {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
+       {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
+       {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
+       {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
+       {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
+       {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
+       {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
+       {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
+       {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
+       {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
+       {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
+/* #define PXP2_COMMON_END         749 */
+/* #define MISC_AEU_COMMON_START   770 */
+       {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
+/* #define MISC_AEU_COMMON_END     771 */
+/* #define MISC_AEU_PORT0_START    772 */
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
+       {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
+       {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
+       {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
+       {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
+       {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
+       {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
+/* #define MISC_AEU_PORT0_END      773 */
+/* #define MISC_AEU_PORT1_START    774 */
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
+       {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
+       {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
+       {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
+       {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
+       {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
+       {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
+/* #define MISC_AEU_PORT1_END      775 */
+
+};
+
+static const u16 init_ops_offsets_e1[] = {
+       0x0000, 0x002e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x002e,
+       0x0050, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0050, 0x008d, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x008d, 0x0092,
+       0x0092, 0x0096, 0x0096, 0x009a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x009a, 0x00db, 0x00db, 0x00e9, 0x00e9, 0x00f7, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x00f7, 0x00fe, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x00fe, 0x0103, 0x0103, 0x010e, 0x010e, 0x0119,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0119, 0x011a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x011a, 0x0152, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0152, 0x0176, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0176, 0x01b5, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x01b5, 0x01f0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x01f0, 0x0235, 0x0235, 0x0238, 0x0238,
+       0x023b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x023b,
+       0x0276, 0x0276, 0x0280, 0x0280, 0x028a, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x028a, 0x028b, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x028b, 0x029d,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x029d, 0x02b2, 0x02b2, 0x02b5, 0x02b5, 0x02b8, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x02b8, 0x02e6, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x02e6, 0x036d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x036d, 0x0374, 0x0374, 0x0378,
+       0x0378, 0x037c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x037c, 0x03bb, 0x03bb, 0x03c3, 0x03c3, 0x03cb, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x03cb, 0x041f, 0x041f, 0x0431, 0x0431,
+       0x0443, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0443,
+       0x044d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x044d, 0x0453, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0453, 0x0456,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0456, 0x045b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x045b, 0x045c, 0x045c,
+       0x046e, 0x046e, 0x0480, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0480, 0x04ed, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x04ed, 0x04ee, 0x04ee, 0x0502,
+       0x0502, 0x0516, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+static const u32 init_data_e1[] = {
+       0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
+       0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
+       0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
+       0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
+       0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
+       0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
+       0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
+       0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
+       0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
+       0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
+       0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
+       0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
+       0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
+       0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
+       0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
+       0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
+       0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
+       0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
+       0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
+       0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
+       0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
+       0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
+       0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
+       0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
+       0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
+       0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
+       0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
+       0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
+       0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
+       0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
+       0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
+       0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
+       0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
+       0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
+       0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
+       0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
+       0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
+       0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
+       0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
+       0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
+       0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
+       0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
+       0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
+       0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
+       0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
+       0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
+       0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
+       0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
+       0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
+       0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
+       0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
+       0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
+       0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
+       0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
+       0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
+       0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
+       0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
+       0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
+       0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
+       0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
+       0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
+       0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
+       0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
+       0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
+       0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
+       0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
+       0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
+       0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
+       0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
+       0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
+       0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
+       0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
+       0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
+       0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
+       0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
+       0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
+       0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
+       0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
+       0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
+       0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
+       0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
+       0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
+       0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
+       0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
+       0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
+       0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
+       0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
+       0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
+       0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
+       0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
+       0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
+       0x00000200, 0x00007ff8, 0x00007ff8, 0x0000026f, 0x00001500, 0x00000001,
+       0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00000001, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+       0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+       0xffffffff, 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180,
+       0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600,
+       0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80,
+       0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00,
+       0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380,
+       0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800,
+       0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700,
+       0x00020a80, 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00,
+       0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100,
+       0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600,
+       0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00,
+       0x00007ff8, 0x00007ff8, 0x00000174, 0x00001500, 0x00001900, 0x00000000,
+       0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x00007ff8, 0x00007ff8, 0x00000509,
+       0x00003500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00001000,
+       0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300,
+       0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600,
+       0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900,
+       0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00,
+       0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00,
+       0x00007ff8, 0x00007ff8, 0x00000448, 0x00001500, 0x10000000, 0x000028ad,
+       0x00000000, 0x00010001, 0x00150005, 0xccccccc1, 0xffffffff, 0xffffffff,
+       0x7058103c, 0x00000000, 0x00000000, 0x00000001, 0xcccc0201, 0xcccccccc,
+       0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x000e01b7, 0x011600d6,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000,
+       0x007201bb, 0x012300f3, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x00100000, 0x00000000, 0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+       0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
+       0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+       0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+       0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+       0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
+       0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+       0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+       0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff,
+       0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+       0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+       0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+       0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
+       0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+       0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
+       0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+       0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+       0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
+       0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+       0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
+       0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x000c0000, 0x000700c0,
+       0x00028130, 0x000b8158, 0x00020210, 0x00010230, 0x000f0240, 0x00010330,
+       0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200,
+       0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198,
+       0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100,
+       0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380,
+       0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118,
+       0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc,
+       0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc,
+       0xcccccccc, 0xcccccccc, 0x00002000
+};
+
+static const u8 tsem_int_table_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51,
+       0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0x7b, 0xd8, 0x18, 0x18, 0x36, 0x70, 0x20,
+       0xf8, 0x43, 0x01, 0x5f, 0x64, 0x62, 0x60, 0xb8, 0x0c, 0xc4, 0x57, 0x81,
+       0x58, 0x80, 0x99, 0x81, 0x21, 0x98, 0x91, 0x81, 0x21, 0x84, 0x91, 0x78,
+       0xfd, 0x49, 0xa2, 0x08, 0xf6, 0x2b, 0x21, 0x06, 0x06, 0x31, 0x61, 0x06,
+       0x86, 0x68, 0x41, 0xa0, 0xb9, 0xc2, 0x08, 0xf1, 0xa3, 0x40, 0x35, 0x56,
+       0x22, 0x0c, 0x0c, 0x7f, 0xa1, 0x62, 0x8d, 0x40, 0x36, 0x9b, 0x28, 0x75,
+       0xdc, 0x3f, 0xd0, 0x78, 0x93, 0x14, 0xa6, 0xd8, 0x7a, 0x09, 0x04, 0x7b,
+       0x33, 0x16, 0x79, 0x64, 0xbc, 0x05, 0x4d, 0x9e, 0x4f, 0x12, 0x95, 0xbf,
+       0x95, 0x80, 0xfe, 0x81, 0xc6, 0x8f, 0x15, 0x51, 0xf9, 0x62, 0x0a, 0x10,
+       0x3a, 0x1f, 0x2a, 0xfe, 0x04, 0x4d, 0x5e, 0x1c, 0x2a, 0x7f, 0x19, 0xea,
+       0xaf, 0xa7, 0x8a, 0xd8, 0xcd, 0xbd, 0x02, 0x95, 0x07, 0x00, 0xc8, 0xe9,
+       0x67, 0x44, 0x60, 0x03, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 tsem_pram_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
+       0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x9c, 0x99, 0x49,
+       0x66, 0x26, 0x27, 0x21, 0x4f, 0x1e, 0x61, 0x12, 0x20, 0x82, 0x86, 0x38,
+       0xbc, 0x02, 0x28, 0xbd, 0x4e, 0x08, 0x44, 0xac, 0x5c, 0x0d, 0xf8, 0x42,
+       0x8b, 0x3a, 0xbc, 0x43, 0xde, 0x50, 0xb4, 0xb4, 0xb5, 0x5f, 0x26, 0x10,
+       0x22, 0x4f, 0x6f, 0xf0, 0x47, 0x45, 0x2f, 0xd8, 0xe1, 0x61, 0x45, 0x8b,
+       0x36, 0x60, 0xa4, 0xd1, 0x02, 0x1d, 0x40, 0x10, 0x7b, 0xbd, 0xb7, 0xc1,
+       0x52, 0x8b, 0xd5, 0xfa, 0x45, 0x54, 0x50, 0x0c, 0x24, 0x72, 0x8b, 0xd2,
+       0x5b, 0x7b, 0xfd, 0xd7, 0x5a, 0x7b, 0xef, 0xcc, 0x39, 0x93, 0x09, 0x60,
+       0xff, 0xf6, 0xfe, 0xf7, 0xbf, 0xdf, 0x1f, 0x3f, 0xbf, 0xc3, 0x3e, 0x67,
+       0x3f, 0xd6, 0x5e, 0xaf, 0xbd, 0xd6, 0xda, 0x6b, 0xef, 0xb1, 0xb3, 0x34,
+       0xa6, 0x0f, 0x64, 0xec, 0x6b, 0xfc, 0xbb, 0x81, 0xb1, 0x1a, 0x1b, 0x63,
+       0xf0, 0xaa, 0xfb, 0xf9, 0x94, 0x9d, 0xdd, 0x5f, 0xea, 0x66, 0x2c, 0x6f,
+       0xa3, 0x6f, 0xb9, 0x3b, 0x15, 0xde, 0xb7, 0xe6, 0xec, 0x4a, 0xf4, 0x31,
+       0x96, 0xb5, 0x77, 0xbd, 0x32, 0x11, 0xde, 0x67, 0x6d, 0x6a, 0x52, 0x66,
+       0xe7, 0x47, 0xdb, 0x8f, 0x76, 0xc1, 0xc7, 0x31, 0xf0, 0xbe, 0x75, 0xbd,
+       0x52, 0x04, 0xef, 0xb3, 0xde, 0x6c, 0x52, 0x66, 0xe1, 0xd3, 0x61, 0x63,
+       0x6d, 0x50, 0x9f, 0x69, 0xbe, 0x24, 0x86, 0x4f, 0x16, 0x60, 0x2c, 0x9d,
+       0xb1, 0x41, 0xe3, 0x98, 0xf8, 0x0b, 0xb8, 0xb3, 0x0a, 0x19, 0xeb, 0x8f,
+       0xff, 0x84, 0x2e, 0xce, 0x1b, 0x89, 0xd0, 0x19, 0x63, 0x39, 0x2b, 0x6c,
+       0xe1, 0x90, 0x02, 0xef, 0x83, 0x65, 0x53, 0x99, 0x97, 0xb1, 0x6d, 0x00,
+       0x57, 0x56, 0x0a, 0xb4, 0x53, 0xbf, 0x3a, 0x60, 0xc7, 0xba, 0xb5, 0xda,
+       0xc9, 0x76, 0x27, 0x63, 0x4e, 0xcd, 0xa9, 0x7d, 0x9d, 0xcb, 0x58, 0xf6,
+       0x0c, 0x66, 0x63, 0xf0, 0x1c, 0xb8, 0x94, 0xbf, 0xc7, 0xbf, 0xaf, 0xe1,
+       0xff, 0x9c, 0x90, 0xb5, 0x3c, 0x88, 0x99, 0xca, 0x39, 0x58, 0xf6, 0xa4,
+       0x9e, 0x82, 0x21, 0x99, 0x87, 0x79, 0xbe, 0x56, 0xe3, 0xc1, 0xdb, 0xa5,
+       0x97, 0x0e, 0x8f, 0xce, 0x53, 0x3e, 0x37, 0xd5, 0xf9, 0xd2, 0xdd, 0x5a,
+       0xcf, 0xf7, 0xf2, 0xb9, 0x78, 0xd1, 0x27, 0xfa, 0xc3, 0xd0, 0xfa, 0x69,
+       0xac, 0x37, 0x98, 0xb1, 0x70, 0x4c, 0xfd, 0xaa, 0x90, 0xae, 0xb1, 0x6b,
+       0xe1, 0x09, 0x08, 0x68, 0xce, 0xef, 0xd9, 0x7e, 0x2a, 0x2b, 0x2a, 0x44,
+       0x3a, 0xdc, 0xc7, 0x26, 0xd2, 0xb3, 0x46, 0xf3, 0xdd, 0x85, 0x78, 0xa9,
+       0x39, 0x6a, 0x67, 0x21, 0x80, 0xbb, 0xa6, 0xf6, 0x54, 0x09, 0x96, 0x59,
+       0xab, 0xc2, 0x86, 0xe4, 0xf4, 0x6c, 0x3f, 0x9c, 0xd9, 0x89, 0x1e, 0x45,
+       0x4c, 0xd1, 0x4e, 0xe1, 0x7c, 0xbd, 0xcc, 0x8b, 0xf3, 0x53, 0x2b, 0x7d,
+       0x4f, 0x94, 0x00, 0x9e, 0xe7, 0x26, 0x06, 0x26, 0x61, 0xbf, 0xeb, 0x12,
+       0x83, 0xf4, 0x94, 0xef, 0x33, 0x67, 0x4f, 0xc9, 0x0c, 0x02, 0x3c, 0xc5,
+       0x0b, 0xf2, 0x43, 0x0c, 0xe8, 0x7e, 0x7e, 0xa3, 0xe2, 0x77, 0x40, 0xf3,
+       0xd3, 0x4a, 0x58, 0xb7, 0x03, 0x3d, 0x2a, 0x6e, 0xaf, 0x2d, 0xb8, 0x11,
+       0xea, 0xfd, 0x56, 0x0f, 0xde, 0x8c, 0xed, 0x2a, 0x67, 0xb4, 0x1d, 0x21,
+       0x7a, 0xb0, 0xda, 0x3c, 0xc4, 0x53, 0x9b, 0xce, 0xf9, 0x67, 0x60, 0x6b,
+       0xd1, 0xa7, 0x1a, 0xd0, 0x0d, 0x58, 0x2c, 0x94, 0x94, 0x82, 0x74, 0x61,
+       0xec, 0xa4, 0x89, 0x0e, 0xf8, 0x77, 0x72, 0xa8, 0x28, 0xab, 0xbd, 0xe3,
+       0xf1, 0x72, 0xcf, 0xb9, 0xd8, 0x8f, 0x86, 0xbd, 0x84, 0x69, 0xbe, 0xf2,
+       0x7d, 0x4e, 0xe8, 0xe8, 0xa0, 0xc1, 0x31, 0xe3, 0xb1, 0x42, 0x82, 0x87,
+       0x31, 0xe4, 0x71, 0xd6, 0xae, 0xc4, 0xa3, 0xeb, 0xc0, 0x57, 0x8a, 0x8e,
+       0x6a, 0x05, 0xbd, 0x8f, 0xf7, 0xf7, 0x9f, 0x47, 0x88, 0xcb, 0x21, 0xe0,
+       0x0e, 0xe9, 0x5b, 0xe5, 0xd1, 0xc3, 0xcb, 0x80, 0xbe, 0xc5, 0x2f, 0xdb,
+       0x23, 0x37, 0x00, 0x3d, 0xaa, 0xb6, 0x28, 0x61, 0x07, 0x94, 0x6d, 0xfb,
+       0x5d, 0x01, 0xa4, 0xcf, 0xb9, 0xed, 0x50, 0x06, 0xba, 0x44, 0x3c, 0x3a,
+       0xd5, 0x3f, 0x6b, 0x38, 0xa9, 0x5c, 0xe3, 0x68, 0x7b, 0xe4, 0x7a, 0x28,
+       0x77, 0xbd, 0xac, 0xb2, 0xad, 0xd8, 0xed, 0xd0, 0x04, 0x1b, 0xca, 0xdd,
+       0x29, 0x01, 0x3b, 0x1b, 0x0d, 0x65, 0xc0, 0xc7, 0x7c, 0x17, 0x2f, 0x56,
+       0x6d, 0x39, 0x70, 0x1f, 0xf6, 0x57, 0xd6, 0xea, 0x60, 0x2e, 0xe8, 0xbf,
+       0xea, 0x95, 0x05, 0xb7, 0x5c, 0x0f, 0xe5, 0x05, 0xc0, 0x6f, 0x58, 0xa5,
+       0xea, 0x99, 0x7a, 0xbd, 0x2f, 0x94, 0x17, 0x86, 0x95, 0x66, 0x2c, 0x77,
+       0x4e, 0x64, 0xc4, 0x1f, 0xa1, 0x14, 0x3d, 0xfc, 0x0c, 0x8c, 0xd7, 0xe9,
+       0x6d, 0x4b, 0xbf, 0x03, 0xe4, 0xe5, 0x4c, 0x9d, 0x93, 0xf9, 0x00, 0x94,
+       0xe5, 0x9e, 0xb6, 0xf4, 0xdb, 0x81, 0x8f, 0xca, 0xc3, 0xbb, 0x4a, 0xb0,
+       0x5d, 0xf9, 0x4e, 0xc5, 0x8f, 0x68, 0x2f, 0x7e, 0xf9, 0x99, 0x23, 0x59,
+       0x38, 0xaf, 0xe7, 0x80, 0xaf, 0x80, 0x8f, 0x2a, 0x76, 0x24, 0x32, 0x9f,
+       0xc4, 0x1f, 0xfc, 0x7f, 0x0a, 0xa6, 0x72, 0x03, 0x7c, 0x5f, 0x0c, 0xf3,
+       0x44, 0xf9, 0x5f, 0xc0, 0x9a, 0x4a, 0x98, 0x8a, 0xe3, 0xaf, 0xd7, 0x7d,
+       0x9e, 0x28, 0xbe, 0xce, 0xd4, 0x19, 0x34, 0x4e, 0xb7, 0x3c, 0x3d, 0x07,
+       0xe3, 0x40, 0xbb, 0xea, 0x17, 0x15, 0x3f, 0x4e, 0xb1, 0xda, 0xc6, 0x82,
+       0x28, 0x57, 0xe7, 0x5e, 0x71, 0xcd, 0xd8, 0xe6, 0xc6, 0xf9, 0xd5, 0xeb,
+       0x79, 0x1e, 0x9c, 0xd7, 0xc3, 0x3a, 0xd6, 0x5b, 0x10, 0x9e, 0xb5, 0x07,
+       0x55, 0x56, 0x79, 0x78, 0x8b, 0x5e, 0x02, 0xdf, 0xcb, 0x37, 0x6d, 0xd1,
+       0xe7, 0xe7, 0x23, 0xde, 0x40, 0xef, 0xe5, 0x23, 0x5c, 0x7d, 0xac, 0x70,
+       0x6d, 0x54, 0x03, 0x88, 0xdf, 0xc5, 0xc9, 0xce, 0xad, 0x2a, 0xe0, 0x87,
+       0xb9, 0x03, 0x99, 0xd3, 0xe3, 0xf0, 0xcf, 0x99, 0x3a, 0x50, 0x63, 0x79,
+       0xd1, 0x72, 0x39, 0xca, 0x37, 0xe9, 0x93, 0xb0, 0x3e, 0xcd, 0x54, 0xbf,
+       0x44, 0x49, 0x26, 0x7e, 0xad, 0xd8, 0xa1, 0x32, 0x9f, 0x85, 0x9f, 0x38,
+       0xfd, 0x43, 0xc7, 0x38, 0xfd, 0x43, 0xfb, 0x3c, 0xe1, 0x67, 0x72, 0xa2,
+       0xf4, 0x5b, 0x6c, 0x70, 0x3d, 0x29, 0xe9, 0xb7, 0x38, 0x59, 0xd0, 0x53,
+       0xeb, 0x2a, 0x8c, 0x07, 0xcf, 0x23, 0x48, 0x0f, 0x80, 0xa7, 0x09, 0xf1,
+       0x05, 0xcf, 0xb5, 0x02, 0x3e, 0xef, 0x04, 0x56, 0xa4, 0x01, 0x5d, 0xbc,
+       0x01, 0x66, 0x28, 0xec, 0xf2, 0xfc, 0xd9, 0x64, 0x67, 0xb3, 0x18, 0x8c,
+       0xfd, 0x16, 0x9b, 0x17, 0xd0, 0xc6, 0x43, 0x59, 0x67, 0x8b, 0x98, 0x9f,
+       0x31, 0x43, 0xab, 0x0a, 0x4c, 0x82, 0xf2, 0x57, 0xac, 0xf4, 0x4d, 0x9c,
+       0x0f, 0x63, 0x7e, 0x5f, 0x29, 0xe0, 0xb9, 0x51, 0x61, 0x33, 0x70, 0xde,
+       0x87, 0x11, 0x58, 0x98, 0x4f, 0x63, 0x96, 0x4e, 0xf8, 0x6b, 0x9a, 0x5c,
+       0xb8, 0x4d, 0x55, 0x04, 0xcc, 0xa9, 0x58, 0x9e, 0xff, 0x93, 0xd5, 0x39,
+       0xd4, 0xfe, 0x38, 0xb5, 0xd7, 0xa0, 0xfd, 0xf0, 0xde, 0xdb, 0x1b, 0x25,
+       0xe3, 0x2c, 0xed, 0x8d, 0x92, 0x32, 0xd9, 0xfe, 0x3d, 0xac, 0xc7, 0x9c,
+       0x97, 0x6e, 0xdf, 0x54, 0x72, 0x9d, 0x75, 0xfc, 0x92, 0x72, 0xd9, 0xfe,
+       0x23, 0x1a, 0xdf, 0x7d, 0x69, 0xf8, 0x8d, 0x1b, 0x27, 0x58, 0xc7, 0xbf,
+       0xb1, 0x92, 0xda, 0xd7, 0x38, 0x38, 0xbd, 0xba, 0x92, 0x9d, 0xe1, 0xad,
+       0x50, 0x6e, 0x70, 0xf9, 0x03, 0x1a, 0xd2, 0x4d, 0x63, 0x11, 0x7c, 0xaf,
+       0xa5, 0xe4, 0x6d, 0xc5, 0x7a, 0xaa, 0xe4, 0x07, 0xd6, 0x16, 0x50, 0xa1,
+       0xbd, 0x7b, 0x67, 0xf2, 0xc8, 0xd5, 0xcc, 0xcc, 0x17, 0x13, 0xff, 0x88,
+       0xe3, 0x79, 0x40, 0x5a, 0xcc, 0x7c, 0x91, 0x34, 0x2e, 0xc1, 0xc2, 0x8f,
+       0xc9, 0x81, 0x14, 0x4b, 0x19, 0x7a, 0x32, 0x4e, 0x5d, 0x13, 0xd5, 0x43,
+       0x01, 0xaf, 0x93, 0xe0, 0xd1, 0xfb, 0xea, 0xa4, 0x2f, 0x8a, 0xfa, 0x3a,
+       0x09, 0xde, 0x07, 0xf7, 0xbb, 0xa8, 0xfc, 0xe0, 0x75, 0x1c, 0xde, 0x07,
+       0xfb, 0xba, 0x49, 0xce, 0x10, 0x06, 0x96, 0x05, 0x65, 0x3d, 0x78, 0xad,
+       0x61, 0x5a, 0x8f, 0x00, 0x4e, 0x85, 0x65, 0x32, 0x76, 0x41, 0x09, 0xba,
+       0x94, 0x31, 0xe6, 0xf7, 0x3e, 0x1b, 0xbe, 0x4f, 0x50, 0x59, 0x2d, 0xce,
+       0x27, 0xc1, 0xc1, 0x48, 0x1f, 0x3d, 0x9c, 0x53, 0xb8, 0x2d, 0x64, 0xc2,
+       0xcf, 0xca, 0x01, 0x40, 0x5f, 0x28, 0xa7, 0x2a, 0x3a, 0xc7, 0xa3, 0xc0,
+       0xeb, 0xc3, 0x03, 0xe6, 0x67, 0xce, 0x32, 0x8d, 0xd3, 0x38, 0x40, 0x9f,
+       0xb1, 0x35, 0x9f, 0xbf, 0x9f, 0xe3, 0xc6, 0xf1, 0x4a, 0xd3, 0x15, 0xd4,
+       0x83, 0x7a, 0x57, 0x9e, 0xe1, 0xee, 0x39, 0x8e, 0x23, 0x77, 0x9c, 0x65,
+       0x1c, 0x67, 0x76, 0x19, 0x8d, 0x93, 0x13, 0x33, 0x8e, 0x23, 0xbb, 0x2c,
+       0x66, 0x1c, 0xe7, 0x8c, 0xad, 0xe2, 0xbd, 0x18, 0x67, 0xd0, 0xa5, 0xc6,
+       0x79, 0x38, 0xf7, 0x3a, 0xeb, 0x7c, 0xb2, 0xcb, 0x69, 0x9c, 0x82, 0xd8,
+       0xf9, 0x64, 0x97, 0xc7, 0x8c, 0x93, 0xc0, 0xe7, 0x03, 0xef, 0xc5, 0x38,
+       0x7e, 0xc4, 0x5f, 0xaf, 0xf3, 0x19, 0x34, 0xc1, 0x3a, 0x9f, 0x81, 0x95,
+       0x34, 0xce, 0xf5, 0x38, 0xce, 0x18, 0xd3, 0x7c, 0x06, 0x56, 0xc6, 0x8c,
+       0xe3, 0xa6, 0x71, 0xf0, 0x3d, 0x8e, 0x03, 0x86, 0x94, 0x8f, 0x65, 0x00,
+       0xdd, 0x1d, 0x5d, 0xf3, 0x89, 0xfe, 0xbf, 0x74, 0x91, 0xbd, 0xa0, 0x3b,
+       0x82, 0xcf, 0x62, 0xbf, 0xec, 0x5d, 0x17, 0x23, 0x7d, 0xe2, 0x83, 0x71,
+       0x33, 0x50, 0xaf, 0xc0, 0xe2, 0x0c, 0xf2, 0xab, 0x29, 0x29, 0x34, 0xce,
+       0x17, 0x09, 0x40, 0x7f, 0xb7, 0x99, 0xce, 0x5c, 0x1f, 0xd1, 0x13, 0xf4,
+       0xcf, 0x3c, 0x01, 0x22, 0x0b, 0x03, 0x44, 0xa0, 0x7f, 0xaa, 0x05, 0x8f,
+       0xce, 0xdd, 0x39, 0x2d, 0xbb, 0x1e, 0x9f, 0xad, 0xc5, 0x99, 0xb3, 0xd0,
+       0x2e, 0xd9, 0xe0, 0xf1, 0x0f, 0x01, 0xd1, 0x39, 0xd7, 0x5a, 0xac, 0xcf,
+       0x89, 0x63, 0xdf, 0xcc, 0x6b, 0xb2, 0x9f, 0x6a, 0xb7, 0xf0, 0xaf, 0xd0,
+       0x7b, 0x13, 0xd9, 0xd0, 0x5a, 0x18, 0xbf, 0x05, 0x95, 0x8d, 0xa9, 0x7c,
+       0x0a, 0xf4, 0x17, 0x03, 0xbd, 0x75, 0x12, 0xf4, 0x17, 0x3e, 0x4f, 0x0b,
+       0xfb, 0xf4, 0x23, 0xd0, 0x6f, 0x4c, 0x37, 0xc3, 0x5b, 0x4f, 0xf3, 0x38,
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+       0xb5, 0xc3, 0xf7, 0x51, 0xbd, 0x7f, 0x57, 0x37, 0x6a, 0x71, 0xbf, 0x6b,
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+       0x57, 0xee, 0xce, 0x9a, 0x88, 0xfe, 0x60, 0xa5, 0x1e, 0xc9, 0xab, 0x75,
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+       0x0c, 0xf7, 0x8b, 0xca, 0x2f, 0xd1, 0x6f, 0x90, 0x45, 0xee, 0x97, 0xb0,
+       0xe0, 0xc7, 0xa8, 0x9f, 0x3b, 0x0e, 0xa8, 0xa4, 0x67, 0x59, 0xe4, 0x50,
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+       0x19, 0x54, 0x7e, 0xbf, 0x2e, 0x48, 0xcf, 0xf6, 0xba, 0x32, 0x7a, 0x9e,
+       0xac, 0xab, 0xa5, 0xef, 0x1f, 0xd5, 0x2d, 0xa5, 0xf2, 0xa9, 0xba, 0x10,
+       0x3d, 0x3f, 0xa9, 0x5b, 0x49, 0xcf, 0x33, 0x75, 0x4d, 0xf4, 0xbd, 0xa3,
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+       0x94, 0xa5, 0x0a, 0xfb, 0x4f, 0xd8, 0xeb, 0xb0, 0x72, 0x50, 0xf9, 0xbc,
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+       0x28, 0x9f, 0xb1, 0xfc, 0xd6, 0x3b, 0xfd, 0x02, 0xb4, 0xde, 0xcf, 0x0f,
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+       0x5b, 0xd3, 0xac, 0x86, 0x1c, 0xd7, 0xe2, 0xfb, 0x9d, 0x96, 0xf1, 0xa0,
+       0x9d, 0x4f, 0xfa, 0xd0, 0xb8, 0x5e, 0xf5, 0x4e, 0x77, 0x8d, 0x9d, 0x32,
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+       0x2c, 0x8d, 0xd3, 0x7e, 0xa5, 0x4d, 0xe1, 0xf0, 0x84, 0xed, 0x5d, 0xed,
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+       0xfb, 0xe1, 0x25, 0xf4, 0x54, 0x4f, 0x38, 0xdd, 0x99, 0x14, 0xb7, 0x93,
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+       0xde, 0x05, 0xd1, 0xfc, 0xf4, 0x5f, 0xec, 0x6c, 0x35, 0xc0, 0xc1, 0xbe,
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+       0xcf, 0x67, 0xd3, 0xd3, 0x51, 0x6f, 0xcc, 0xdf, 0x60, 0x67, 0x61, 0x40,
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+       0xbb, 0x80, 0xd5, 0x36, 0xa2, 0x3d, 0xa7, 0x39, 0xb8, 0x7f, 0x30, 0xdb,
+       0x60, 0x5a, 0x3f, 0x80, 0xab, 0xea, 0xe7, 0x9b, 0x0b, 0xd1, 0xee, 0xff,
+       0x85, 0xcd, 0x46, 0xf4, 0x91, 0x71, 0x86, 0x85, 0x29, 0x1c, 0xee, 0xf2,
+       0xd4, 0xb0, 0x1e, 0x80, 0xef, 0x1f, 0xb6, 0x8c, 0xba, 0xf3, 0x7a, 0xe4,
+       0x3e, 0x47, 0xb8, 0x11, 0xd7, 0x65, 0x96, 0xc4, 0xfc, 0xcf, 0xb0, 0x9e,
+       0xf8, 0x9c, 0xb3, 0xd2, 0x0a, 0xdf, 0xe5, 0xe0, 0x8f, 0x85, 0x97, 0xb1,
+       0x65, 0x16, 0x38, 0x64, 0xbf, 0x12, 0x0e, 0x75, 0x87, 0x12, 0x08, 0xc7,
+       0xe1, 0xbb, 0x37, 0x24, 0xdf, 0x09, 0x3d, 0x92, 0xa2, 0x5a, 0xed, 0xfc,
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+       0x6b, 0x38, 0x43, 0xb6, 0x24, 0xfa, 0xee, 0x8f, 0x60, 0x7c, 0x64, 0xb7,
+       0xc3, 0xbf, 0x1c, 0xe8, 0xfb, 0x80, 0xad, 0xb4, 0x1d, 0xf5, 0x33, 0xd8,
+       0x05, 0x05, 0xcc, 0x54, 0xef, 0x01, 0x5b, 0x90, 0xde, 0x77, 0x28, 0x6f,
+       0xce, 0x47, 0xfb, 0x94, 0x69, 0x91, 0x02, 0xf4, 0xef, 0x61, 0x4d, 0xd1,
+       0x90, 0x1f, 0x74, 0xc1, 0x0f, 0x6a, 0x82, 0xb7, 0x00, 0xe3, 0xb1, 0x1e,
+       0x06, 0xeb, 0x27, 0xc8, 0xa5, 0x03, 0xe1, 0x83, 0x7e, 0x1a, 0x3d, 0x65,
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+       0xa3, 0x0a, 0x94, 0x5d, 0xee, 0x16, 0x86, 0xfd, 0x39, 0x32, 0xad, 0xf1,
+       0x65, 0x97, 0xcf, 0x5a, 0xae, 0xc1, 0x7f, 0x20, 0x1d, 0x86, 0x32, 0x8a,
+       0xe3, 0x24, 0x0e, 0xb5, 0x7e, 0x87, 0x05, 0x8b, 0x21, 0xbf, 0x79, 0xfc,
+       0xd6, 0xf7, 0xff, 0xd1, 0x8d, 0xa7, 0x08, 0xf1, 0xad, 0x97, 0x58, 0x1a,
+       0x9e, 0x4e, 0x77, 0x44, 0x85, 0xf1, 0xd9, 0x38, 0xad, 0xc3, 0x6c, 0x37,
+       0x57, 0x3b, 0x39, 0xfc, 0xe4, 0x97, 0x43, 0xfd, 0x25, 0xc2, 0x9e, 0xaf,
+       0x66, 0xbe, 0x10, 0xc5, 0x89, 0x33, 0x39, 0x1f, 0x2c, 0xb9, 0xc9, 0x46,
+       0xf0, 0x2c, 0xf1, 0xf8, 0xfc, 0x21, 0xf8, 0xae, 0x68, 0x01, 0x86, 0xf2,
+       0x87, 0xb1, 0x6a, 0xf3, 0x3a, 0x56, 0x73, 0x11, 0x44, 0xae, 0x8f, 0xa9,
+       0xac, 0x75, 0xe9, 0xc8, 0x97, 0x35, 0x17, 0x35, 0x16, 0x06, 0x7d, 0x5f,
+       0x60, 0x0b, 0x7a, 0xd4, 0x31, 0x88, 0xbf, 0x00, 0xd9, 0xb9, 0x4e, 0x40,
+       0xd6, 0xd7, 0x00, 0xb2, 0xe6, 0x9e, 0x62, 0xb1, 0x7b, 0x59, 0xff, 0x14,
+       0xb1, 0xbe, 0xf6, 0x37, 0xcc, 0xf2, 0xda, 0x1f, 0xe9, 0x3c, 0x26, 0x4a,
+       0x67, 0xa9, 0x17, 0xec, 0x42, 0x2f, 0x82, 0xbe, 0xc8, 0x50, 0xd3, 0x50,
+       0x0f, 0x76, 0x95, 0x90, 0x5f, 0xc2, 0xda, 0x49, 0x4f, 0xc8, 0x7a, 0x7a,
+       0xb4, 0x5e, 0x7f, 0x84, 0xa3, 0xb7, 0x7a, 0xae, 0x68, 0xbd, 0x9c, 0x78,
+       0xfd, 0x55, 0xfd, 0xfc, 0x85, 0x3d, 0x21, 0xc0, 0x7f, 0xf9, 0xcf, 0x1e,
+       0xf3, 0x02, 0xf1, 0xd9, 0xa7, 0x5a, 0x53, 0xba, 0x1f, 0xde, 0x57, 0x3e,
+       0xb3, 0xc2, 0x8b, 0x7c, 0xfc, 0x89, 0x16, 0xf2, 0xe2, 0xbc, 0x3f, 0x0d,
+       0xab, 0x53, 0xe2, 0xf1, 0xf3, 0x9d, 0xaa, 0x22, 0xfc, 0xb1, 0x80, 0x5b,
+       0x41, 0x7f, 0x58, 0xd0, 0xe9, 0xcc, 0xf3, 0x6b, 0x6e, 0x41, 0xbc, 0x7f,
+       0xf1, 0x8c, 0xdd, 0xc0, 0x2a, 0x35, 0x3b, 0x1c, 0x11, 0x07, 0x10, 0xb1,
+       0xba, 0x65, 0x21, 0xe7, 0xa7, 0x1d, 0x8e, 0x0f, 0x78, 0xf9, 0xe1, 0xcf,
+       0x91, 0x9e, 0x35, 0xad, 0x56, 0x79, 0x2b, 0x7f, 0xf6, 0xb1, 0x74, 0x8c,
+       0x77, 0x02, 0x86, 0xb8, 0xdf, 0xc8, 0x22, 0x64, 0x3f, 0x57, 0x6f, 0xff,
+       0xb8, 0x04, 0xed, 0x91, 0x1a, 0xd6, 0x45, 0x7a, 0x22, 0xb6, 0x1d, 0x8e,
+       0x7f, 0x31, 0x85, 0xd6, 0xaf, 0x59, 0x7a, 0x52, 0xcf, 0xef, 0x72, 0xff,
+       0xa5, 0x46, 0xf0, 0x7d, 0x4d, 0xcb, 0x9a, 0xcf, 0x55, 0x2f, 0x96, 0xad,
+       0xf2, 0x5d, 0x26, 0xfc, 0x91, 0x1b, 0x55, 0x4f, 0x2a, 0xc5, 0x95, 0xc6,
+       0xb2, 0xb1, 0x48, 0x37, 0x89, 0x07, 0x16, 0xe6, 0xf6, 0xf0, 0xf2, 0xe7,
+       0x9e, 0x28, 0xf8, 0x00, 0xe0, 0xe8, 0xd8, 0xfe, 0x2f, 0x5e, 0xc5, 0x12,
+       0x37, 0xe2, 0xfa, 0xe1, 0x7c, 0xf3, 0x9c, 0x1f, 0xbf, 0xea, 0xeb, 0x5d,
+       0xaf, 0x9f, 0x13, 0xfe, 0x7c, 0xb4, 0x5d, 0x98, 0xda, 0xf9, 0x5a, 0xb9,
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+       0x8b, 0xdd, 0x0f, 0x92, 0xc9, 0x2a, 0x5f, 0xd8, 0xf6, 0x93, 0xa7, 0x90,
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+       0xe5, 0x8a, 0x5d, 0xf6, 0xd4, 0xa9, 0x7c, 0x1a, 0x6e, 0x25, 0x3d, 0x4a,
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+       0xd3, 0xd5, 0xb8, 0xf6, 0xa5, 0x11, 0x1f, 0xbf, 0xf8, 0x2a, 0xc6, 0xef,
+       0x7f, 0xef, 0xf0, 0xe3, 0xfc, 0xcb, 0x5e, 0xfc, 0xae, 0x17, 0xe7, 0x71,
+       0x5a, 0xab, 0xe5, 0xfc, 0xbc, 0x79, 0x45, 0x7a, 0x00, 0xc6, 0x2d, 0xb3,
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+       0xc6, 0x07, 0xb8, 0x13, 0xd0, 0x1e, 0x3b, 0x9d, 0x0e, 0xf6, 0x4d, 0x9c,
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+       0xe0, 0xf7, 0x3f, 0x1e, 0xe7, 0xf2, 0x83, 0xed, 0x70, 0x5d, 0x07, 0xb8,
+       0x22, 0x19, 0xf4, 0xfd, 0xc0, 0xed, 0x0a, 0xe9, 0x01, 0x07, 0x8b, 0xc4,
+       0x93, 0xe7, 0xed, 0x76, 0x21, 0xcf, 0xd6, 0xef, 0x72, 0x7f, 0x12, 0xe0,
+       0xd6, 0x70, 0x7d, 0x8a, 0xf2, 0x09, 0xf4, 0x9f, 0x42, 0xf8, 0x27, 0x3b,
+       0x6d, 0xfe, 0x06, 0x68, 0x67, 0xd2, 0xcb, 0x35, 0x38, 0x1e, 0xd5, 0xd3,
+       0xa3, 0xef, 0x4d, 0xeb, 0xfa, 0x02, 0x21, 0xff, 0xaf, 0xab, 0x62, 0x7f,
+       0x54, 0xc8, 0x3f, 0xdb, 0xc4, 0xe5, 0xbe, 0x77, 0xbb, 0x37, 0xc4, 0xfd,
+       0x03, 0x7b, 0xf8, 0x27, 0x4f, 0xa1, 0xbc, 0x82, 0x7c, 0xe2, 0x3a, 0x53,
+       0xf9, 0x82, 0xbd, 0x14, 0xe7, 0xfd, 0xd9, 0xce, 0x43, 0x6f, 0xdf, 0x03,
+       0x7c, 0xfd, 0x59, 0xb3, 0x94, 0x53, 0xab, 0xde, 0x8c, 0x95, 0xd3, 0xb2,
+       0xdd, 0x63, 0x58, 0x3c, 0x39, 0xfd, 0xcc, 0xed, 0x67, 0x71, 0xe5, 0x14,
+       0xde, 0xc7, 0x95, 0x53, 0x77, 0x3b, 0xf1, 0xf1, 0xdf, 0x5b, 0x6f, 0x4a,
+       0xbc, 0x9d, 0x8b, 0xd1, 0x9b, 0x52, 0x0f, 0xf6, 0x86, 0xbf, 0x58, 0x3d,
+       0xb8, 0x56, 0xf5, 0xc5, 0xd5, 0x83, 0xf0, 0x77, 0x9c, 0x15, 0xf6, 0xe4,
+       0x3b, 0xc9, 0x6f, 0x92, 0xcf, 0xca, 0x7f, 0x5a, 0x35, 0x90, 0xe2, 0x46,
+       0x92, 0x1f, 0x25, 0xbf, 0x75, 0xf3, 0xa3, 0xe4, 0xb7, 0xd8, 0x79, 0x5a,
+       0xf1, 0x16, 0xfb, 0xfd, 0x15, 0xa1, 0x6f, 0x24, 0x9d, 0xed, 0xcb, 0x58,
+       0xc8, 0x83, 0xf1, 0xd2, 0x7d, 0x2a, 0xf9, 0xd7, 0x9d, 0x00, 0x53, 0x23,
+       0xd0, 0xb7, 0x73, 0x67, 0x4e, 0x18, 0xe3, 0xce, 0x2b, 0x5c, 0x3c, 0x7e,
+       0xd1, 0x69, 0x74, 0x79, 0x53, 0xe0, 0xb9, 0x22, 0x99, 0x97, 0xbb, 0xd2,
+       0xf4, 0x46, 0xd4, 0x0f, 0xf2, 0x7d, 0x97, 0x8b, 0xc7, 0xb7, 0x3b, 0x4b,
+       0xbb, 0xbc, 0xc9, 0x26, 0xbf, 0xe2, 0x83, 0xbd, 0xaa, 0xd7, 0x07, 0xdf,
+       0xdb, 0xc3, 0x6c, 0x4a, 0x3c, 0x7f, 0x03, 0x34, 0x2f, 0xc1, 0xd1, 0xce,
+       0x7a, 0xfb, 0xce, 0xe3, 0xc1, 0x93, 0x55, 0x77, 0xf6, 0x52, 0xf4, 0xdb,
+       0x9b, 0x54, 0xda, 0xcf, 0x9e, 0x5b, 0x7f, 0x97, 0x17, 0xf7, 0x81, 0x3b,
+       0xf7, 0x0e, 0xfa, 0x27, 0xd4, 0x4f, 0xf3, 0xde, 0x00, 0x03, 0x13, 0xe0,
+       0xed, 0x44, 0x3b, 0x30, 0x09, 0xa7, 0x17, 0xd0, 0x30, 0x2f, 0x61, 0x8e,
+       0xa0, 0xf7, 0x27, 0x2c, 0xf4, 0xf8, 0x04, 0x98, 0xdf, 0x9c, 0xbd, 0xdc,
+       0x5f, 0x98, 0xbb, 0x36, 0xc6, 0xbe, 0x77, 0x2f, 0xd1, 0x51, 0xdf, 0x80,
+       0x7d, 0x7f, 0xd2, 0x1a, 0xd7, 0xe6, 0x7c, 0x53, 0x2e, 0xfa, 0x29, 0xdb,
+       0x64, 0xfd, 0x5e, 0xce, 0xd6, 0x12, 0xdd, 0xca, 0x63, 0xf8, 0x28, 0x28,
+       0xfc, 0xc0, 0xb1, 0x9a, 0xe0, 0xa3, 0x11, 0x6c, 0x84, 0xf0, 0xc3, 0x78,
+       0xfc, 0x42, 0xe8, 0xab, 0xc9, 0x6a, 0xfe, 0x3f, 0xa1, 0x9d, 0xd1, 0x79,
+       0x94, 0xc7, 0x15, 0xcf, 0xef, 0x55, 0x09, 0xff, 0xe7, 0x77, 0x2a, 0x61,
+       0x8c, 0xfb, 0x50, 0x7c, 0x77, 0x3c, 0xd2, 0xbf, 0x4b, 0x67, 0x26, 0x7f,
+       0xb9, 0x03, 0xf9, 0x4d, 0xef, 0x5d, 0x8e, 0x3b, 0x5e, 0xfe, 0x43, 0xe1,
+       0x0f, 0xa1, 0x4a, 0xe5, 0x9e, 0x77, 0x0b, 0xfe, 0x19, 0x9e, 0x1d, 0x7b,
+       0xde, 0xc9, 0xfb, 0x05, 0x96, 0x7f, 0xfe, 0xbb, 0xec, 0x77, 0x59, 0xcf,
+       0xfa, 0xc5, 0xfb, 0xff, 0x44, 0xfb, 0xc7, 0x9d, 0xfb, 0x1d, 0x04, 0x47,
+       0xe7, 0xfe, 0xd7, 0xb3, 0x7f, 0x88, 0xe5, 0x57, 0x1d, 0x7e, 0x84, 0xb3,
+       0x73, 0x99, 0x83, 0xf6, 0xcf, 0x42, 0xfb, 0x3d, 0xe1, 0x21, 0xf8, 0x7d,
+       0x00, 0xd0, 0x1b, 0xd7, 0xcd, 0x7d, 0x5f, 0x16, 0xb4, 0xd3, 0xba, 0xd3,
+       0x40, 0x74, 0x9a, 0xad, 0xf1, 0xfd, 0x8e, 0xf3, 0x7b, 0xff, 0xfc, 0xbe,
+       0x82, 0xf9, 0x07, 0x7b, 0x1d, 0x3e, 0x9c, 0x47, 0xcd, 0x7e, 0x9e, 0x17,
+       0x52, 0xf3, 0xaa, 0x8b, 0xe2, 0x2e, 0x9d, 0xfb, 0xbe, 0x2c, 0x0c, 0xba,
+       0xff, 0x76, 0xf3, 0xa9, 0xd6, 0x59, 0x90, 0xf8, 0xcf, 0xc3, 0x66, 0xec,
+       0x46, 0x7e, 0x4d, 0xe6, 0xfb, 0x00, 0x35, 0xbf, 0x18, 0xbf, 0xad, 0x1e,
+       0xf7, 0xc3, 0x5b, 0x0e, 0xe8, 0xb8, 0xbf, 0x52, 0xfc, 0xcb, 0xbf, 0x14,
+       0xa0, 0x7e, 0xe9, 0xdc, 0xcd, 0xed, 0x84, 0x73, 0xf6, 0xf6, 0xa7, 0x71,
+       0x1f, 0xb4, 0x4a, 0x1b, 0xbc, 0xcc, 0x8e, 0x72, 0x8f, 0x36, 0x5b, 0x5f,
+       0xb0, 0x3b, 0xed, 0xf3, 0x26, 0x86, 0xf2, 0xe3, 0xe1, 0x85, 0xe3, 0xa1,
+       0x13, 0xf0, 0x80, 0xf3, 0x02, 0xbc, 0x94, 0xa1, 0x5e, 0xec, 0x0d, 0x1f,
+       0x0d, 0x1a, 0xf7, 0x37, 0xff, 0xfb, 0xe1, 0xe3, 0xf3, 0xfb, 0x70, 0xfc,
+       0xca, 0xbd, 0x63, 0x49, 0x6e, 0xa2, 0x78, 0x51, 0x02, 0xfc, 0xbd, 0x27,
+       0xec, 0x54, 0x68, 0xfe, 0xfc, 0xfd, 0xfe, 0x2f, 0x0b, 0xd0, 0xee, 0xf9,
+       0xac, 0xb9, 0x9e, 0xd6, 0xf1, 0xcb, 0xcd, 0x7b, 0xdb, 0xff, 0xb8, 0x79,
+       0x2b, 0x91, 0x2b, 0x99, 0xf7, 0xc1, 0xff, 0xe6, 0xfc, 0x3f, 0x45, 0xe3,
+       0xeb, 0x52, 0xac, 0x1c, 0xf4, 0xe4, 0xf3, 0x9f, 0x3f, 0x48, 0xe5, 0x17,
+       0x3d, 0x7e, 0x82, 0xf7, 0x0a, 0xe5, 0xff, 0xe4, 0xff, 0x34, 0xba, 0xef,
+       0x06, 0xba, 0x7b, 0x2f, 0x4f, 0x77, 0xc5, 0xfe, 0xdf, 0x75, 0xde, 0x97,
+       0xa3, 0xfb, 0x1b, 0x82, 0xee, 0x1e, 0x03, 0xf3, 0x0a, 0x3a, 0xf7, 0xfd,
+       0x85, 0xe2, 0xe5, 0x72, 0xfe, 0x97, 0x9b, 0xb7, 0xef, 0xff, 0xd1, 0x79,
+       0x4b, 0xfb, 0x67, 0xb5, 0xcd, 0xdf, 0x94, 0x0b, 0xf5, 0xd7, 0xb2, 0x48,
+       0x9b, 0x0f, 0xe0, 0x5c, 0x31, 0x74, 0x7a, 0x13, 0x86, 0x99, 0xc0, 0x4d,
+       0x28, 0x8d, 0x67, 0x8f, 0x94, 0xda, 0xb9, 0x7f, 0xa4, 0x2a, 0x3c, 0x0e,
+       0xc3, 0x06, 0xf0, 0xb8, 0x10, 0x13, 0xfe, 0x04, 0xa5, 0x80, 0xf9, 0x30,
+       0x8e, 0x32, 0x9f, 0xec, 0x3a, 0xcd, 0xdd, 0x48, 0x76, 0x26, 0xd3, 0xfc,
+       0x6d, 0x01, 0xc0, 0xc7, 0xea, 0xab, 0x67, 0xfb, 0x29, 0x57, 0x83, 0x8d,
+       0x3c, 0x11, 0xc4, 0x72, 0xff, 0x09, 0x7e, 0x8a, 0x6f, 0xc6, 0xf8, 0x55,
+       0x0d, 0x0a, 0x0b, 0x28, 0x60, 0xef, 0x69, 0x57, 0x7f, 0xfb, 0x28, 0xda,
+       0xf9, 0xf6, 0xa1, 0xb6, 0x88, 0xa3, 0x80, 0x9e, 0x1f, 0xe0, 0xf3, 0x61,
+       0x11, 0xc7, 0xb2, 0x1b, 0xba, 0xc5, 0x9f, 0x70, 0xc7, 0xf8, 0x03, 0x2e,
+       0x9f, 0xf5, 0xbb, 0x43, 0xf4, 0xe7, 0x64, 0x23, 0x9b, 0x72, 0x31, 0x4f,
+       0xc1, 0xad, 0x19, 0x61, 0x18, 0xdf, 0x5d, 0xd4, 0x44, 0xf3, 0x71, 0x0f,
+       0x61, 0xac, 0xc9, 0xb4, 0x0f, 0xe8, 0x60, 0xa6, 0xf6, 0xd0, 0x5f, 0x3e,
+       0x06, 0x60, 0x4d, 0xf6, 0xe3, 0x37, 0xc5, 0x5f, 0x7d, 0x37, 0xfe, 0x46,
+       0xb6, 0x05, 0x10, 0x7f, 0xc3, 0x6c, 0x14, 0xd7, 0xa2, 0xa4, 0x3e, 0xc2,
+       0x87, 0x3f, 0xbc, 0x9a, 0xfc, 0x4c, 0xee, 0x3f, 0x46, 0xf1, 0xd9, 0xd8,
+       0x86, 0x78, 0xd4, 0x18, 0xf8, 0x7f, 0x7c, 0x7e, 0xe4, 0x37, 0x32, 0xe1,
+       0x2f, 0x6a, 0xa2, 0x0b, 0x6d, 0xa8, 0x2d, 0xe0, 0xb2, 0xd6, 0x13, 0x7e,
+       0xd1, 0x65, 0xe9, 0xc3, 0xe9, 0x91, 0x5d, 0x29, 0xe8, 0xb3, 0xd8, 0x42,
+       0x0f, 0x89, 0xff, 0x38, 0x74, 0xb1, 0xd0, 0x43, 0xe2, 0xf7, 0x9b, 0xd2,
+       0x25, 0x96, 0x1e, 0xb1, 0x78, 0xbf, 0xdd, 0xce, 0xe3, 0x6d, 0xb1, 0x74,
+       0xb2, 0xe4, 0x77, 0xa4, 0x71, 0x3f, 0x24, 0x02, 0x7e, 0xc8, 0xeb, 0x3b,
+       0xb7, 0x51, 0xbc, 0xe3, 0xec, 0xf3, 0x1f, 0xdc, 0x82, 0xf5, 0x2b, 0x7e,
+       0xa1, 0x32, 0x27, 0xf4, 0x73, 0x6e, 0xa7, 0x87, 0x45, 0x50, 0x7e, 0xb5,
+       0xb0, 0x8e, 0xfe, 0x54, 0x79, 0x8b, 0x1a, 0x37, 0xce, 0x2b, 0xed, 0xf2,
+       0x8a, 0x9f, 0x79, 0x68, 0xbc, 0xf2, 0xdd, 0x8e, 0xf0, 0x54, 0x68, 0x5f,
+       0xbe, 0xe7, 0xc3, 0x02, 0xb2, 0x9b, 0x96, 0x75, 0x1d, 0xe9, 0x87, 0x71,
+       0x81, 0xe7, 0x15, 0x4e, 0xbf, 0x50, 0x7b, 0x01, 0xee, 0xdb, 0x95, 0x6b,
+       0xdc, 0x3f, 0x88, 0xed, 0x6f, 0x93, 0x9d, 0xc7, 0x05, 0x3a, 0x5e, 0x49,
+       0x9c, 0x81, 0xf1, 0x07, 0x65, 0x07, 0xcf, 0x57, 0x2c, 0x6f, 0xbe, 0xcb,
+       0xee, 0x30, 0xf1, 0xdb, 0xff, 0xb2, 0xf3, 0xbc, 0x57, 0xa8, 0x47, 0xf2,
+       0x1c, 0x7a, 0x4e, 0xa1, 0xf5, 0xa6, 0x27, 0x7c, 0xdc, 0x2f, 0xe8, 0x78,
+       0x4e, 0xe1, 0xf0, 0xb5, 0xda, 0xc3, 0x98, 0xf7, 0x58, 0xbe, 0x63, 0x8b,
+       0x1e, 0x44, 0xbf, 0x72, 0xc7, 0xe7, 0x14, 0xc7, 0x2e, 0xfe, 0xd9, 0x0b,
+       0xde, 0x76, 0xf2, 0x17, 0x55, 0xab, 0xff, 0xbc, 0x43, 0x25, 0x7a, 0xc2,
+       0x93, 0xe8, 0x17, 0xeb, 0xc7, 0x56, 0xb7, 0x54, 0x91, 0x9f, 0x50, 0xdd,
+       0x2c, 0xfc, 0xc4, 0x18, 0x3f, 0xaa, 0xe2, 0x67, 0xfb, 0xf6, 0x84, 0x00,
+       0x35, 0x15, 0x2f, 0x3d, 0xeb, 0xc5, 0xf8, 0xcb, 0x99, 0xb6, 0x67, 0xbc,
+       0xe4, 0x9f, 0xee, 0xe0, 0xfe, 0xa7, 0xe6, 0xd6, 0xe2, 0xfb, 0xa7, 0x97,
+       0xf3, 0x4b, 0x9b, 0x57, 0xc5, 0xf5, 0x4b, 0xcf, 0xe0, 0x3f, 0xc0, 0x9f,
+       0x38, 0x60, 0x8f, 0xf1, 0xe7, 0x77, 0xf4, 0xb9, 0xb2, 0xfd, 0xcb, 0x17,
+       0x2e, 0x3c, 0x8d, 0x71, 0xd2, 0x8e, 0xdd, 0x9f, 0x3d, 0x8d, 0x70, 0x57,
+       0xfe, 0xe7, 0xbf, 0x3f, 0x8d, 0xf6, 0x3d, 0xdb, 0xef, 0x32, 0x9e, 0x81,
+       0xf9, 0xd6, 0x3c, 0xff, 0x5b, 0x8a, 0x37, 0xc9, 0x76, 0xef, 0x0a, 0x39,
+       0x3d, 0x37, 0x80, 0x85, 0xb2, 0xa0, 0xde, 0xb9, 0x77, 0x1c, 0x94, 0x3f,
+       0x72, 0x6e, 0xdf, 0xe9, 0x6c, 0xf4, 0xe7, 0xce, 0xed, 0xfa, 0x53, 0x3a,
+       0xfa, 0xf5, 0x4b, 0xf6, 0x4d, 0xce, 0xc0, 0x79, 0x2f, 0x79, 0xb9, 0x38,
+       0x83, 0xc5, 0x91, 0x77, 0xf9, 0x44, 0xbe, 0x0c, 0x5f, 0x41, 0x9c, 0x30,
+       0x96, 0x0e, 0x87, 0x5a, 0x0e, 0x91, 0x1f, 0x72, 0xf6, 0x84, 0x83, 0xfc,
+       0xbe, 0xee, 0xf8, 0x42, 0x73, 0x15, 0x8f, 0xd7, 0xf8, 0x44, 0x5c, 0x61,
+       0x67, 0xfc, 0x38, 0xac, 0xf4, 0x87, 0xab, 0x5b, 0x3e, 0x2c, 0xe1, 0xf1,
+       0x31, 0xe1, 0x17, 0x5f, 0x2e, 0x8e, 0x70, 0x1c, 0xe8, 0x78, 0xed, 0x15,
+       0xd0, 0x6b, 0xa7, 0x88, 0x13, 0xc5, 0xd0, 0xeb, 0x2c, 0xfe, 0x03, 0xe8,
+       0xf2, 0x65, 0x0c, 0xbd, 0x2e, 0xb0, 0xe0, 0x8f, 0xb3, 0x70, 0x1f, 0xb2,
+       0xa5, 0x4f, 0xaf, 0x71, 0x84, 0xc8, 0x15, 0xe0, 0x49, 0xc6, 0x77, 0x8f,
+       0xd8, 0x03, 0x36, 0x1d, 0xe5, 0x60, 0x77, 0x62, 0x37, 0x9d, 0xa6, 0x22,
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+       0x74, 0xed, 0x73, 0x18, 0xe8, 0xdf, 0x97, 0xef, 0xfb, 0x1d, 0xc9, 0xc5,
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+       0x6d, 0xe2, 0x45, 0xe8, 0x1f, 0xf3, 0x60, 0x6c, 0xe1, 0xf5, 0x33, 0xa1,
+       0x5d, 0xa2, 0xd6, 0xac, 0xe0, 0x3e, 0x00, 0x3c, 0x19, 0xd2, 0xe5, 0x01,
+       0x5b, 0x70, 0xab, 0x9e, 0x86, 0xf5, 0x74, 0xe6, 0x03, 0xd5, 0xf8, 0xb4,
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+       0xc6, 0x27, 0x84, 0x76, 0x85, 0xa0, 0x5f, 0x26, 0xd2, 0x14, 0xe5, 0xec,
+       0x41, 0xc6, 0xcf, 0xe7, 0x38, 0x94, 0x00, 0xfa, 0x8f, 0x9d, 0xdf, 0x35,
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+       0x18, 0xb0, 0x37, 0x29, 0x82, 0x7e, 0x10, 0xf0, 0xf3, 0x17, 0x31, 0xfc,
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+       0xfa, 0x33, 0x44, 0x7f, 0x60, 0xf0, 0xa4, 0xa3, 0xfc, 0xf0, 0xbf, 0x4e,
+       0x95, 0xdb, 0xdb, 0x9d, 0x75, 0x3e, 0x82, 0x03, 0xcc, 0xc3, 0x03, 0xb8,
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+       0xf3, 0x8f, 0x34, 0xda, 0xa1, 0x5e, 0xd5, 0xcc, 0xda, 0x3c, 0x64, 0xf6,
+       0x9e, 0x74, 0xe5, 0xe7, 0xb1, 0xd2, 0xf7, 0xce, 0xaa, 0xb7, 0x63, 0xbc,
+       0x02, 0xe9, 0xe2, 0xeb, 0x49, 0xbf, 0x6b, 0x97, 0xfa, 0xd3, 0xb4, 0x3e,
+       0x16, 0x7a, 0x8e, 0x72, 0x40, 0x3f, 0xd7, 0xee, 0xfd, 0xdc, 0x86, 0x70,
+       0x4b, 0x3a, 0x3e, 0x21, 0xf2, 0xfc, 0x63, 0xdb, 0xff, 0x83, 0x43, 0x11,
+       0xe3, 0x56, 0xd6, 0xdb, 0x31, 0x4e, 0xd2, 0xaa, 0x93, 0x3d, 0x1b, 0x5b,
+       0x6f, 0x0a, 0x1e, 0xaa, 0x1a, 0x13, 0x2d, 0x17, 0x38, 0x0b, 0x69, 0xdc,
+       0x0c, 0x1b, 0x8f, 0x77, 0xf4, 0xac, 0xcf, 0xd7, 0xbf, 0x68, 0xbf, 0x4e,
+       0x3a, 0x97, 0xd5, 0x1b, 0x1f, 0x16, 0x18, 0xbc, 0x3f, 0xc0, 0xfb, 0xb7,
+       0x11, 0x7e, 0x89, 0xf7, 0x5b, 0x1c, 0x42, 0xdf, 0xf6, 0xc4, 0xfb, 0x34,
+       0xac, 0x07, 0x78, 0xa7, 0xe7, 0x15, 0xe0, 0xfd, 0xce, 0x4b, 0xe1, 0x5d,
+       0xda, 0xcf, 0x15, 0x42, 0x1f, 0x54, 0xe0, 0xfe, 0x09, 0xf0, 0xcd, 0xc7,
+       0x81, 0xe9, 0xe9, 0x83, 0x61, 0xdc, 0x12, 0xd5, 0x4d, 0x7c, 0xbf, 0xf0,
+       0x19, 0x95, 0xe4, 0x0d, 0xea, 0x4f, 0xcd, 0x4a, 0x8f, 0xea, 0x8f, 0x85,
+       0xe3, 0x6b, 0x0f, 0xe0, 0x3c, 0x17, 0x6e, 0x56, 0x88, 0x3f, 0xe7, 0x8a,
+       0xf3, 0xa5, 0x9f, 0x89, 0x7c, 0xfe, 0xd8, 0x3c, 0xa8, 0xf9, 0x33, 0x42,
+       0xb4, 0xaf, 0xd3, 0x23, 0x1f, 0x2a, 0x1c, 0xe3, 0xcf, 0xc5, 0xe4, 0xb9,
+       0x57, 0x47, 0xf9, 0x74, 0x20, 0xcf, 0x4f, 0xe3, 0xe7, 0xb5, 0x54, 0x21,
+       0x07, 0xc5, 0x0b, 0xf2, 0x93, 0xd0, 0x0e, 0xda, 0x6f, 0xf7, 0xfd, 0x9a,
+       0xec, 0xeb, 0x37, 0x54, 0xb6, 0x35, 0x0e, 0xde, 0x89, 0xb9, 0xd2, 0xa2,
+       0xe5, 0x01, 0xb5, 0x36, 0x4b, 0x7e, 0x2c, 0x9b, 0x9b, 0x6c, 0xe9, 0x77,
+       0xd2, 0x82, 0x7c, 0xda, 0xef, 0x5e, 0xec, 0xf1, 0x5d, 0xd2, 0x9f, 0x1a,
+       0xb8, 0xd4, 0xba, 0x5e, 0xe7, 0x84, 0xac, 0xe7, 0x8b, 0x06, 0xad, 0xb4,
+       0x9e, 0x2f, 0x1a, 0xd2, 0xd4, 0xd7, 0x52, 0xff, 0xaa, 0x8d, 0xb9, 0x96,
+       0xef, 0xc3, 0xc2, 0x57, 0x5b, 0xbe, 0x5f, 0xb3, 0x63, 0xa4, 0xa5, 0x3c,
+       0xbc, 0xf9, 0x3a, 0x4b, 0xfd, 0x6b, 0x5b, 0x27, 0x5a, 0xca, 0x23, 0x22,
+       0xdf, 0xb6, 0xd4, 0x1f, 0x75, 0x74, 0xba, 0xa5, 0x3c, 0xa6, 0xed, 0x1e,
+       0x4b, 0xfd, 0xb1, 0x27, 0x66, 0x5b, 0xbe, 0x8f, 0x6f, 0x2f, 0xb7, 0x7c,
+       0xbf, 0xfe, 0x93, 0xc5, 0x96, 0xf2, 0xb7, 0xba, 0x7e, 0x60, 0xb5, 0x4f,
+       0x6c, 0x8c, 0xf4, 0x21, 0x4b, 0x50, 0x48, 0x3f, 0xbe, 0x56, 0x37, 0x2e,
+       0x1b, 0xf3, 0xb0, 0xd9, 0x68, 0x65, 0x12, 0xe2, 0xb3, 0x58, 0xe4, 0x11,
+       0xbe, 0xb6, 0x48, 0xb7, 0x19, 0x5e, 0x7c, 0xe6, 0xd9, 0x0c, 0xd0, 0x53,
+       0x07, 0xe7, 0x4d, 0xa5, 0xf5, 0xfe, 0xb5, 0x45, 0xe9, 0x01, 0x1f, 0x3d,
+       0x0b, 0x03, 0xe8, 0xcf, 0x30, 0x75, 0xc2, 0xe8, 0x78, 0x79, 0x9a, 0x93,
+       0x8d, 0xf1, 0xd9, 0xe6, 0x7c, 0xa8, 0x62, 0xa7, 0xdd, 0xa2, 0xcf, 0x26,
+       0x1b, 0xd6, 0xf2, 0xcb, 0x92, 0x6f, 0x06, 0x72, 0xbe, 0x79, 0x35, 0x46,
+       0x9f, 0xd9, 0x6b, 0x27, 0x44, 0xc0, 0x22, 0x64, 0x7d, 0x17, 0x0e, 0xce,
+       0xc0, 0xf1, 0x40, 0xbe, 0xf6, 0x09, 0xbd, 0xb6, 0xef, 0x0a, 0xf5, 0xda,
+       0x41, 0x94, 0xc3, 0xd3, 0xe9, 0x91, 0x46, 0x2c, 0x4b, 0xf9, 0x62, 0x62,
+       0x5d, 0x2d, 0x12, 0x7c, 0x04, 0xcf, 0x80, 0x8e, 0xf9, 0x90, 0x93, 0x3c,
+       0xb4, 0xfe, 0x06, 0xf0, 0xa5, 0x8f, 0xde, 0x87, 0x34, 0x90, 0x93, 0x89,
+       0x4e, 0x7f, 0xff, 0xc3, 0x38, 0x1f, 0x9b, 0x3f, 0x15, 0x99, 0x6f, 0xd2,
+       0x8c, 0xd2, 0xd7, 0x78, 0x6e, 0xa5, 0x58, 0x7f, 0xd9, 0x50, 0xdb, 0x37,
+       0x59, 0x7f, 0xa5, 0x7c, 0x67, 0xda, 0x44, 0xbe, 0x5a, 0x0a, 0xcf, 0x57,
+       0x7b, 0x72, 0x5e, 0x5e, 0x12, 0x33, 0xe1, 0xf5, 0x5d, 0x87, 0x4d, 0xd8,
+       0xcd, 0x4d, 0xfc, 0x69, 0x1c, 0x75, 0x75, 0xe7, 0xa9, 0xe6, 0x9a, 0xdf,
+       0x7f, 0x92, 0xa0, 0x99, 0xf2, 0xe3, 0x94, 0x05, 0x53, 0x29, 0x3f, 0x24,
+       0xb3, 0x17, 0x3d, 0xa8, 0x67, 0xe6, 0xde, 0xb4, 0x1d, 0xf4, 0xaf, 0x9e,
+       0xe5, 0xa3, 0xa7, 0x7c, 0xdf, 0x38, 0xc3, 0x16, 0x37, 0xef, 0xeb, 0x9c,
+       0xd0, 0x9b, 0xd2, 0xbe, 0x1a, 0x16, 0xb5, 0xaf, 0xce, 0x21, 0x1d, 0xce,
+       0x66, 0xbe, 0xf5, 0x38, 0xe6, 0x25, 0x55, 0xcf, 0xec, 0x22, 0xfb, 0x2a,
+       0xd3, 0xd6, 0xb4, 0xe8, 0x08, 0xce, 0xeb, 0x57, 0xaa, 0x88, 0x57, 0xfa,
+       0xf8, 0x79, 0x2a, 0x61, 0x17, 0xcf, 0xbb, 0xe9, 0xd1, 0x45, 0x47, 0x70,
+       0x1f, 0xfa, 0x5f, 0x87, 0x90, 0x5e, 0x92, 0xe3, 0x6c, 0xaa, 0x9b, 0x72,
+       0x93, 0x66, 0x3a, 0x37, 0xde, 0xbf, 0x17, 0x3f, 0x69, 0x98, 0x93, 0xaf,
+       0x0f, 0x4f, 0xd7, 0x0d, 0xbd, 0x69, 0x2e, 0xe5, 0x69, 0x1b, 0xfc, 0x7c,
+       0xa8, 0xe8, 0x3f, 0x3b, 0x54, 0x55, 0x82, 0x76, 0xf2, 0x40, 0x91, 0x5f,
+       0xfa, 0xb8, 0x2d, 0x7e, 0x7e, 0x4b, 0x82, 0x93, 0xcf, 0x2b, 0x03, 0x49,
+       0x8e, 0xf0, 0x1a, 0x6e, 0x92, 0x8f, 0xb3, 0xf3, 0xdf, 0xf3, 0x6a, 0x30,
+       0x8f, 0xa7, 0x6c, 0xc1, 0x04, 0x27, 0xee, 0xd3, 0x5e, 0xdb, 0x56, 0xc8,
+       0xfd, 0xbc, 0x80, 0x1f, 0xcf, 0x9d, 0x66, 0x47, 0xee, 0x7d, 0x1c, 0xeb,
+       0x67, 0x67, 0x6a, 0x94, 0xdf, 0x1a, 0x3b, 0x7e, 0xc6, 0xcc, 0xe0, 0xca,
+       0x1c, 0x98, 0x5f, 0x43, 0x8a, 0xcd, 0xef, 0xa6, 0x72, 0x97, 0x82, 0xf5,
+       0x1d, 0x0f, 0x31, 0xd6, 0x07, 0xea, 0x37, 0xfc, 0xa7, 0x4a, 0xf0, 0x34,
+       0x1c, 0x1c, 0x4f, 0xf9, 0x1e, 0x0e, 0x77, 0x2d, 0x43, 0xfb, 0x55, 0xce,
+       0xeb, 0x50, 0xca, 0x53, 0x84, 0x1f, 0xb5, 0x25, 0x91, 0xd6, 0x3d, 0x26,
+       0xf6, 0xc1, 0x65, 0x7c, 0xf5, 0x42, 0xe6, 0xdc, 0x36, 0xb4, 0x2b, 0x2e,
+       0x6c, 0xb0, 0xd3, 0x78, 0x17, 0x60, 0x8e, 0x06, 0xf4, 0x7f, 0xa1, 0x45,
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+       0x5e, 0x6b, 0xa2, 0xe3, 0xa0, 0x09, 0x6d, 0xc6, 0x01, 0x34, 0x63, 0x64,
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+       0x13, 0x9a, 0xe8, 0xde, 0xa5, 0x6d, 0xce, 0xe0, 0x75, 0x2e, 0x80, 0xef,
+       0x8f, 0xc6, 0x89, 0xbc, 0x15, 0x00, 0x8e, 0x2b, 0xff, 0xf7, 0xd9, 0xd8,
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+       0xcf, 0xe1, 0xd8, 0xda, 0x75, 0xcc, 0x4f, 0xfb, 0xce, 0xaa, 0x17, 0x28,
+       0x3e, 0xa8, 0xea, 0xa5, 0x39, 0xbc, 0x5c, 0xb7, 0x02, 0xe3, 0x87, 0x69,
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+       0xf4, 0x7c, 0x43, 0x00, 0xf8, 0x64, 0x8d, 0x9d, 0x97, 0xbf, 0xb3, 0xea,
+       0xb9, 0x06, 0x3c, 0x77, 0xbc, 0xc6, 0x5e, 0xba, 0x10, 0xcf, 0x25, 0x63,
+       0xb9, 0x01, 0xfa, 0x5f, 0x93, 0xdc, 0x9c, 0x69, 0x83, 0xb2, 0xbb, 0xfe,
+       0xd9, 0x86, 0xa3, 0x03, 0xb0, 0x2c, 0xeb, 0x3f, 0x4b, 0x7c, 0x76, 0xa7,
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+       0x43, 0x7f, 0x3a, 0xd2, 0x0f, 0xf8, 0xa5, 0x7a, 0x2f, 0xbf, 0x87, 0xa6,
+       0x1b, 0x6f, 0xad, 0xeb, 0x15, 0x5c, 0x4f, 0x7e, 0x52, 0x77, 0xd4, 0xd7,
+       0xa0, 0x09, 0x39, 0x91, 0xfa, 0x03, 0xd6, 0xe5, 0xab, 0x32, 0x19, 0xf9,
+       0x15, 0x7a, 0x58, 0x09, 0xe7, 0x2a, 0x78, 0x1f, 0xc7, 0xca, 0x74, 0x73,
+       0x3e, 0xc9, 0xad, 0x89, 0x8a, 0x58, 0x5f, 0xa0, 0xbd, 0x39, 0x2e, 0x18,
+       0x73, 0xee, 0x8c, 0x8e, 0xb2, 0xe0, 0xfa, 0xda, 0xc0, 0xf3, 0x36, 0x62,
+       0xe9, 0xfa, 0x46, 0x42, 0x51, 0x43, 0xc2, 0x18, 0x3c, 0x2f, 0x1a, 0x5c,
+       0xad, 0xa2, 0x1e, 0x7c, 0xc1, 0x6e, 0x50, 0xde, 0x7b, 0xbb, 0x46, 0x7a,
+       0xbb, 0x43, 0xe6, 0xbd, 0xd7, 0xda, 0xc9, 0x7e, 0xab, 0x14, 0xe7, 0x50,
+       0xed, 0xcb, 0x82, 0xab, 0x87, 0xa1, 0x5c, 0xdc, 0xab, 0xf9, 0x31, 0x0e,
+       0x50, 0x91, 0xd3, 0x54, 0x84, 0xf6, 0x4b, 0xc5, 0x2b, 0x39, 0xfe, 0x7a,
+       0x16, 0xcd, 0xa3, 0xad, 0x48, 0x6e, 0x4e, 0x1f, 0xe9, 0x8e, 0xe6, 0xd1,
+       0xca, 0xf2, 0x72, 0x11, 0x37, 0xca, 0x48, 0xae, 0x4d, 0x4e, 0xce, 0xc7,
+       0xfd, 0x92, 0xf5, 0xd9, 0xb8, 0x9f, 0x51, 0xcd, 0x9a, 0xee, 0xfb, 0x01,
+       0xc2, 0xfb, 0xa6, 0xca, 0x90, 0xdf, 0x3f, 0x3d, 0x30, 0x3e, 0x09, 0xef,
+       0x05, 0xaa, 0x82, 0x32, 0xc6, 0xa9, 0xaa, 0x5a, 0x8e, 0xe9, 0x41, 0xa8,
+       0x57, 0x90, 0xc0, 0xef, 0xa3, 0xa9, 0x6e, 0x01, 0xbe, 0x71, 0xf3, 0x7b,
+       0x62, 0x02, 0x79, 0x8c, 0x6d, 0xd1, 0x8c, 0x04, 0xd4, 0xf3, 0x3f, 0x09,
+       0xd4, 0x5e, 0x8d, 0x26, 0xec, 0x13, 0xae, 0xa3, 0x93, 0x5c, 0x40, 0xd7,
+       0x67, 0x73, 0x03, 0x06, 0xd2, 0xf9, 0xa5, 0x55, 0x6f, 0x35, 0x38, 0xbf,
+       0x05, 0x65, 0xdd, 0x18, 0xc6, 0x46, 0x60, 0xf9, 0x9d, 0x06, 0xe4, 0xb3,
+       0x8a, 0x11, 0x36, 0xca, 0x83, 0x64, 0xa1, 0x77, 0x5e, 0x0b, 0x0c, 0x16,
+       0xfb, 0xb1, 0x50, 0x7e, 0xc8, 0x95, 0x31, 0xd9, 0x1c, 0x97, 0xce, 0x12,
+       0xeb, 0x78, 0xcd, 0x26, 0x37, 0x9d, 0xd7, 0x82, 0x75, 0xf9, 0x71, 0xe4,
+       0xef, 0xea, 0x8d, 0xb6, 0x10, 0xee, 0x6f, 0xd9, 0x9c, 0x6d, 0x74, 0x4e,
+       0xe7, 0x25, 0x97, 0x5c, 0xff, 0xad, 0xe7, 0x9b, 0x36, 0x28, 0x5c, 0x1f,
+       0x86, 0xe6, 0xf1, 0x38, 0xe7, 0x92, 0x9b, 0x52, 0xbe, 0x4d, 0xe7, 0x9b,
+       0x56, 0xe4, 0x1a, 0xa1, 0x4b, 0xc4, 0x5b, 0xcb, 0x2e, 0x26, 0xd0, 0x39,
+       0x26, 0x59, 0x2e, 0x48, 0xf0, 0x51, 0xff, 0x65, 0x5a, 0x88, 0xf6, 0x79,
+       0xca, 0x2e, 0x7a, 0xe9, 0xfc, 0xd3, 0xdf, 0x6e, 0x3c, 0xa7, 0xe5, 0x3c,
+       0x55, 0xcf, 0xf1, 0xdc, 0x04, 0x8f, 0x1c, 0xaf, 0x32, 0x3a, 0x1e, 0xd1,
+       0xf5, 0xd0, 0xc8, 0x5f, 0x3d, 0x3e, 0x18, 0xe8, 0xb6, 0x64, 0x97, 0xdd,
+       0xe6, 0x30, 0xf1, 0xdd, 0x92, 0x5d, 0x62, 0xff, 0xdc, 0x15, 0xc8, 0xc0,
+       0x7e, 0xd2, 0x74, 0x8e, 0x67, 0x86, 0xfe, 0x1b, 0xf0, 0x1a, 0xdd, 0x41,
+       0xc3, 0xcb, 0x21, 0x0d, 0xd6, 0x81, 0x75, 0x52, 0xbe, 0x43, 0x1d, 0x0d,
+       0x93, 0x26, 0x20, 0xdd, 0xa2, 0xdf, 0x99, 0x55, 0xfe, 0x03, 0xe8, 0x3f,
+       0xaf, 0x4b, 0x90, 0xe5, 0x0b, 0xf1, 0xeb, 0x27, 0xc4, 0xd4, 0xcf, 0x95,
+       0xfd, 0xff, 0x85, 0xea, 0xc7, 0xc2, 0x93, 0x96, 0x10, 0x2d, 0x3b, 0xa1,
+       0xbe, 0xf6, 0x17, 0x47, 0x77, 0x19, 0xe1, 0x5b, 0x6f, 0x8b, 0xe9, 0x2f,
+       0x45, 0x96, 0xf5, 0x15, 0x93, 0xfa, 0x47, 0xf9, 0xea, 0xa1, 0x55, 0xde,
+       0xc3, 0x21, 0xe0, 0xab, 0x75, 0xc9, 0x4d, 0x45, 0xa8, 0xff, 0xbb, 0xe6,
+       0x31, 0x1f, 0xde, 0x73, 0x85, 0xfc, 0xea, 0x37, 0xe9, 0xdb, 0x87, 0x5c,
+       0x5c, 0xcf, 0x96, 0x5d, 0xcc, 0xb5, 0xd0, 0x3b, 0x8a, 0xf7, 0x3c, 0x0b,
+       0x5d, 0x4e, 0xd7, 0x65, 0x5a, 0xf6, 0x25, 0x17, 0xcc, 0x5c, 0x42, 0xfb,
+       0xa7, 0x0f, 0xa1, 0xb0, 0x60, 0x3f, 0x2c, 0xc4, 0xcf, 0xc1, 0x6c, 0xea,
+       0xc7, 0xc2, 0xa6, 0xb8, 0xcd, 0xff, 0x87, 0xe3, 0xaf, 0x85, 0xe3, 0xba,
+       0x5e, 0xe0, 0xf8, 0x87, 0xff, 0x62, 0x38, 0x7c, 0x96, 0xf1, 0xa2, 0x70,
+       0x0c, 0xb6, 0xc0, 0xf7, 0xd7, 0xc2, 0xb1, 0xf5, 0xce, 0xbc, 0x6f, 0xe7,
+       0x40, 0x95, 0xc7, 0x94, 0x90, 0x33, 0x17, 0xd7, 0x85, 0x1f, 0xf1, 0xbc,
+       0x35, 0x35, 0x79, 0x92, 0xaf, 0x1e, 0xf7, 0x4b, 0x7e, 0xa4, 0x51, 0xdc,
+       0x7d, 0x08, 0xe3, 0xf9, 0x28, 0xb9, 0x1a, 0x3b, 0xaa, 0x8d, 0x44, 0xf9,
+       0x69, 0x0a, 0x60, 0xdc, 0x82, 0x2d, 0xe3, 0xf6, 0x0a, 0xbc, 0x5f, 0x69,
+       0x1f, 0x49, 0xeb, 0x10, 0xf9, 0x0b, 0x83, 0xf6, 0x3a, 0x66, 0x61, 0x5e,
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+       0x23, 0x07, 0x78, 0x5c, 0x57, 0x1b, 0xe7, 0x0c, 0xa3, 0x8b, 0x15, 0x3b,
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+       0x34, 0x0e, 0x87, 0x99, 0x9e, 0xab, 0x06, 0xe7, 0x66, 0xc4, 0xa3, 0x4f,
+       0x54, 0x2f, 0x72, 0xbe, 0xba, 0x1c, 0x5f, 0x14, 0x4e, 0xe0, 0xfc, 0x9e,
+       0x01, 0xcf, 0x2d, 0x30, 0x8f, 0x16, 0x71, 0x9f, 0x46, 0x15, 0xe2, 0x0a,
+       0xfc, 0x9d, 0xca, 0xbb, 0xdc, 0xcc, 0x80, 0x75, 0xed, 0x2b, 0x4f, 0xd1,
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+       0x7c, 0x0a, 0x7c, 0x6a, 0x49, 0x89, 0xaf, 0xa7, 0x0b, 0xdc, 0x52, 0xce,
+       0x44, 0xfe, 0x84, 0xd6, 0x5e, 0x80, 0xf6, 0x88, 0xac, 0x5f, 0x38, 0xd3,
+       0x3a, 0x9e, 0xcf, 0xcd, 0xd7, 0xbf, 0x01, 0xb2, 0x5d, 0xe8, 0xd6, 0x14,
+       0xb4, 0xcb, 0xa6, 0x62, 0x17, 0x80, 0xc7, 0x41, 0x7e, 0x85, 0xe7, 0x71,
+       0xb4, 0x26, 0x86, 0xf1, 0x7e, 0x7a, 0xb0, 0x6a, 0xb5, 0xdb, 0x00, 0xaf,
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+       0x0b, 0xe2, 0xbc, 0xd3, 0xfa, 0x40, 0x39, 0x9f, 0xda, 0x07, 0x76, 0xb9,
+       0xa3, 0xfd, 0xbd, 0xc9, 0x51, 0xc6, 0x26, 0x0f, 0x2a, 0xdd, 0x8e, 0xfd,
+       0x4d, 0xce, 0xc8, 0x1a, 0xb1, 0x3c, 0x87, 0xb7, 0xc7, 0x7e, 0x0e, 0x27,
+       0xb0, 0x06, 0xe7, 0xc8, 0x28, 0xde, 0x6f, 0x75, 0x00, 0xcb, 0xa5, 0xe0,
+       0xf7, 0x50, 0xdf, 0x45, 0xf9, 0xd1, 0xf7, 0x87, 0x51, 0x76, 0xa1, 0x5e,
+       0x7a, 0x7a, 0x7b, 0x81, 0x82, 0xfb, 0x92, 0xb6, 0x40, 0x3a, 0xae, 0x23,
+       0x1f, 0x1d, 0xfb, 0x01, 0xe5, 0xc1, 0x2e, 0xc0, 0x7b, 0x8c, 0x9c, 0x78,
+       0xa5, 0x84, 0x4a, 0x7e, 0x52, 0xe1, 0x89, 0x52, 0xba, 0xb7, 0xec, 0x53,
+       0xfc, 0x98, 0x85, 0xf7, 0x1d, 0x95, 0x0e, 0x73, 0x8f, 0xc1, 0xfc, 0x30,
+       0xeb, 0x3d, 0xa4, 0x6c, 0x3b, 0x3f, 0x3f, 0x23, 0xf1, 0xd5, 0x93, 0x1f,
+       0xb8, 0xfe, 0x01, 0x38, 0x43, 0xce, 0x14, 0x0b, 0x9c, 0x6c, 0x1c, 0xc2,
+       0xed, 0xe4, 0xed, 0x62, 0xf1, 0xdb, 0xfd, 0x14, 0x7c, 0x2c, 0xe9, 0x09,
+       0xe8, 0xb9, 0xc6, 0x23, 0xe8, 0x89, 0x72, 0xda, 0x22, 0xee, 0xc5, 0xec,
+       0xe6, 0x1b, 0x71, 0xaf, 0x42, 0x87, 0xb8, 0x0f, 0x6a, 0x76, 0xa2, 0xb8,
+       0x17, 0xca, 0xe0, 0xfe, 0x95, 0xbc, 0xe7, 0xa4, 0x45, 0x0b, 0x24, 0xa2,
+       0x7d, 0x3e, 0xbb, 0x3b, 0x3f, 0x21, 0x40, 0xe7, 0x8f, 0x2a, 0x5d, 0x81,
+       0xa4, 0xf1, 0x48, 0xb7, 0x63, 0xdc, 0x7f, 0x3a, 0x5d, 0xc4, 0xef, 0xa7,
+       0x3b, 0x6d, 0x0f, 0x24, 0xa1, 0xbc, 0x9e, 0x3e, 0xa6, 0x2a, 0xf5, 0x94,
+       0xdf, 0xc1, 0xf3, 0x3e, 0x65, 0x5e, 0xdd, 0x69, 0xbb, 0x6f, 0xcd, 0xd5,
+       0xf0, 0x7d, 0xce, 0x3f, 0xab, 0x81, 0x7a, 0xfa, 0x6c, 0xf5, 0x0b, 0x3a,
+       0x58, 0x60, 0xd4, 0xbf, 0xa2, 0x9f, 0xd4, 0xaa, 0xd2, 0x3e, 0x64, 0xce,
+       0xa3, 0xb3, 0xd4, 0xe1, 0x50, 0x7f, 0x2e, 0x38, 0x0c, 0xa8, 0x8f, 0x66,
+       0x17, 0xbb, 0x43, 0x68, 0xc7, 0xb5, 0xfc, 0xbe, 0xf6, 0x7d, 0x5c, 0xcf,
+       0xe6, 0x3c, 0xed, 0xf0, 0x2d, 0x83, 0x71, 0x5e, 0xdb, 0x38, 0xea, 0x0b,
+       0x2c, 0x9f, 0x5a, 0xeb, 0xf1, 0x39, 0x28, 0xde, 0x9a, 0xab, 0xe0, 0xfd,
+       0xf1, 0x4b, 0xd6, 0xe7, 0x18, 0xb4, 0x0f, 0xb9, 0x94, 0x89, 0x38, 0xf3,
+       0xc4, 0x92, 0x62, 0x58, 0x83, 0x9f, 0xc7, 0xa1, 0xe5, 0xfe, 0x85, 0x93,
+       0xee, 0x93, 0x17, 0xdf, 0xab, 0x1b, 0x27, 0xc1, 0xfc, 0xae, 0x4e, 0x6b,
+       0xb1, 0x21, 0x2a, 0xff, 0xb0, 0xb6, 0xba, 0x11, 0xcf, 0xb3, 0xad, 0xa8,
+       0x2f, 0xcd, 0xc4, 0x38, 0xc2, 0x5a, 0xf7, 0xe4, 0x46, 0x8c, 0x23, 0xa4,
+       0xa7, 0x07, 0xda, 0x6e, 0x80, 0x75, 0x3d, 0xe2, 0xbe, 0xb1, 0x04, 0xcb,
+       0x2d, 0x4f, 0xc9, 0xfe, 0xa6, 0x34, 0x62, 0xdc, 0xe0, 0x17, 0xb6, 0x60,
+       0x8e, 0x02, 0xdf, 0x4f, 0xbb, 0x67, 0x95, 0x50, 0xfe, 0xf5, 0x20, 0xd9,
+       0xff, 0x92, 0xc6, 0x00, 0xac, 0x09, 0xb3, 0x7f, 0x7c, 0xd5, 0x17, 0x27,
+       0x30, 0x5f, 0x7b, 0x5d, 0x63, 0x09, 0xda, 0x05, 0x40, 0x57, 0x61, 0x5f,
+       0xaf, 0x21, 0xf8, 0xe6, 0x4d, 0x90, 0xe5, 0x26, 0xbd, 0x78, 0x30, 0xb4,
+       0x4f, 0x64, 0x96, 0x78, 0xaa, 0x3d, 0x1a, 0x97, 0xa0, 0x78, 0x6d, 0x4b,
+       0xb7, 0x7d, 0xbe, 0xa1, 0x04, 0xe3, 0x10, 0x73, 0x26, 0xd6, 0x16, 0x6b,
+       0xd0, 0x7f, 0xe1, 0xba, 0xa7, 0x1a, 0xf3, 0x41, 0xc5, 0x8e, 0x6d, 0x2a,
+       0x32, 0x02, 0x50, 0xbe, 0x7e, 0xdd, 0xa6, 0x12, 0x5c, 0xff, 0x5a, 0x58,
+       0xa0, 0x02, 0xed, 0x92, 0x1b, 0xd6, 0x3d, 0x5d, 0x82, 0x71, 0xf9, 0xd4,
+       0x3e, 0xd6, 0xfe, 0x53, 0x55, 0x11, 0x97, 0x67, 0xdb, 0x1a, 0xb1, 0xbf,
+       0xc2, 0x99, 0x81, 0x11, 0x0a, 0xb4, 0xff, 0x97, 0x75, 0x2f, 0x35, 0xa2,
+       0x1f, 0x92, 0x86, 0xf9, 0xb9, 0x30, 0xde, 0x05, 0xcf, 0x9f, 0x1a, 0x43,
+       0xfd, 0xa3, 0xfa, 0xf3, 0x96, 0xe8, 0x3d, 0x5a, 0xab, 0x51, 0x0e, 0xaa,
+       0x9c, 0xed, 0x47, 0x30, 0x54, 0x9b, 0xbd, 0xb4, 0x4b, 0xe7, 0x79, 0xdb,
+       0x42, 0x6f, 0xf4, 0xe7, 0xfc, 0xdc, 0x5d, 0x1e, 0xda, 0xce, 0xf3, 0xeb,
+       0x65, 0x39, 0x93, 0x97, 0x5b, 0x96, 0xc5, 0xd7, 0x43, 0x8f, 0x7a, 0xb9,
+       0xbf, 0xd9, 0x92, 0x10, 0xff, 0xfb, 0xab, 0x42, 0xef, 0x48, 0x79, 0x49,
+       0x3a, 0xc1, 0x02, 0x3b, 0xe3, 0xc8, 0xcd, 0x16, 0xb7, 0xfb, 0xff, 0x48,
+       0xee, 0x5a, 0xff, 0x6f, 0xe9, 0xb5, 0xe4, 0xcb, 0xe8, 0xb5, 0x64, 0xa9,
+       0xd7, 0x04, 0x3e, 0xf3, 0xad, 0x7a, 0x1a, 0x86, 0x11, 0xfa, 0xfe, 0xea,
+       0x5c, 0xd4, 0x0f, 0x0b, 0x30, 0xd9, 0xca, 0x64, 0x2f, 0x14, 0xb6, 0x4d,
+       0xa7, 0x75, 0xe4, 0x7b, 0x5e, 0x6e, 0x3f, 0x33, 0x1f, 0x6f, 0x9f, 0x56,
+       0xcc, 0xf3, 0x9d, 0xba, 0x5e, 0x49, 0xe4, 0xf7, 0xa4, 0x3a, 0xdb, 0xf2,
+       0xcc, 0xfb, 0xa2, 0xc7, 0x05, 0x3e, 0x8a, 0x1f, 0x9e, 0xfa, 0x04, 0x9d,
+       0x77, 0x6f, 0xb3, 0x33, 0x3a, 0xa7, 0xb2, 0xab, 0xe8, 0x92, 0x79, 0xa6,
+       0x95, 0x18, 0xdf, 0x35, 0xf9, 0x1f, 0x95, 0x5a, 0x84, 0xfc, 0xfa, 0x4a,
+       0x8c, 0xef, 0x8e, 0xc2, 0xfe, 0xde, 0xa4, 0x73, 0xa6, 0xd8, 0x0f, 0x9e,
+       0x43, 0xc1, 0x7d, 0x0c, 0x8c, 0xcf, 0xa6, 0x2d, 0x8f, 0x4f, 0x7f, 0x69,
+       0x4f, 0x55, 0x5e, 0x34, 0x58, 0xa8, 0x4f, 0xcf, 0x75, 0x37, 0xda, 0x7f,
+       0x2a, 0x0b, 0x8d, 0xba, 0xfc, 0xbc, 0xa2, 0xfd, 0x59, 0xe3, 0x0f, 0x3d,
+       0xfb, 0xd3, 0xc5, 0x7e, 0x50, 0xcc, 0xfa, 0xa8, 0xc7, 0x87, 0xf3, 0xcf,
+       0x92, 0x4f, 0x01, 0xdf, 0x36, 0x13, 0x7f, 0xcd, 0x13, 0xfc, 0x26, 0xf7,
+       0x95, 0xcf, 0xed, 0x19, 0xb6, 0xd5, 0xbc, 0x8f, 0x2f, 0xcf, 0x87, 0x81,
+       0x7e, 0xfe, 0x29, 0xfe, 0x0e, 0x46, 0x08, 0xf4, 0x3c, 0xda, 0x99, 0x85,
+       0x5a, 0xe0, 0x66, 0xac, 0x5f, 0xd8, 0x96, 0x42, 0xfb, 0x4c, 0x92, 0x3f,
+       0x24, 0x5f, 0x48, 0xba, 0xb6, 0xa4, 0xd4, 0x52, 0xdc, 0xae, 0xeb, 0x49,
+       0x85, 0xce, 0xeb, 0xc5, 0xc2, 0x65, 0xf3, 0x70, 0x3a, 0x16, 0x6e, 0xe4,
+       0xf7, 0x33, 0x66, 0xcc, 0x0c, 0xaa, 0xe6, 0xfb, 0xe4, 0xa5, 0x3c, 0x40,
+       0xff, 0x2d, 0xa2, 0xff, 0xd1, 0xe3, 0x48, 0x7e, 0x36, 0x73, 0x79, 0x00,
+       0xb9, 0xb9, 0x17, 0xe5, 0x17, 0xef, 0xdb, 0xc1, 0x79, 0xf8, 0xdb, 0x0b,
+       0xcc, 0xbf, 0x3b, 0x21, 0xe1, 0xaf, 0x40, 0x5e, 0x4c, 0x23, 0x3a, 0x72,
+       0xfc, 0xbf, 0xec, 0xa2, 0xfd, 0xfe, 0xd8, 0x75, 0x32, 0x8a, 0xff, 0xbe,
+       0x97, 0xa1, 0x67, 0x36, 0xd1, 0x53, 0xda, 0x41, 0x95, 0xbd, 0xae, 0x97,
+       0x5e, 0x9e, 0xbf, 0x78, 0x22, 0xe2, 0xf5, 0x61, 0xfc, 0x08, 0xf9, 0x1f,
+       0xf5, 0x49, 0xf3, 0x87, 0x74, 0x7f, 0x5c, 0x4b, 0xab, 0xca, 0x14, 0x1f,
+       0x9f, 0x37, 0xea, 0xad, 0xc2, 0x6e, 0x7d, 0xfc, 0xf5, 0xe1, 0x89, 0x1a,
+       0xd9, 0x63, 0xd1, 0xf5, 0xc3, 0x47, 0x76, 0x99, 0xd4, 0x9f, 0x11, 0xa7,
+       0x33, 0x5a, 0xbf, 0x6b, 0xcd, 0xd7, 0x93, 0x71, 0x9f, 0x39, 0x55, 0xdc,
+       0xcf, 0x9c, 0xaa, 0xe2, 0x11, 0xec, 0x28, 0x1c, 0x23, 0x3c, 0x5c, 0x8f,
+       0x8d, 0x0b, 0xc6, 0x8f, 0x87, 0x16, 0xb8, 0x3d, 0x9c, 0x0e, 0x62, 0x1e,
+       0x4f, 0x2e, 0x9d, 0xc8, 0x3e, 0x84, 0xf9, 0x7f, 0x4f, 0xac, 0xf3, 0xe3,
+       0xda, 0x43, 0xf4, 0xfb, 0x49, 0x76, 0xc4, 0xe3, 0x98, 0x28, 0x3e, 0xa4,
+       0x3e, 0xbb, 0xd5, 0xd1, 0xfe, 0xa2, 0x38, 0xf7, 0x62, 0xe1, 0x47, 0x59,
+       0x06, 0x3b, 0xa7, 0xda, 0x36, 0xc8, 0xf4, 0xdd, 0xcd, 0xf5, 0xae, 0x1c,
+       0x0f, 0xe0, 0x6d, 0xc0, 0xfb, 0x98, 0xd3, 0xe0, 0x89, 0x57, 0xff, 0x5f,
+       0xf0, 0xe4, 0x88, 0x7d, 0x77, 0xce, 0x97, 0x27, 0xf7, 0x64, 0x6c, 0xa1,
+       0xdf, 0x6d, 0x18, 0x14, 0x18, 0x81, 0xfa, 0x46, 0xf2, 0x17, 0xac, 0x27,
+       0x62, 0xbe, 0xb6, 0xfb, 0xa7, 0xbb, 0x39, 0xff, 0x4f, 0x8f, 0x43, 0x87,
+       0xe9, 0x82, 0xcf, 0xe6, 0x6d, 0xe4, 0xf3, 0x6f, 0xf9, 0x8f, 0xe2, 0x9b,
+       0x91, 0x0f, 0x5a, 0xde, 0x4a, 0x49, 0x5e, 0x66, 0xe2, 0xf7, 0x7a, 0xa1,
+       0x57, 0x64, 0xbf, 0x52, 0x9e, 0x64, 0x3b, 0xf9, 0x7d, 0x86, 0xe8, 0xef,
+       0x5e, 0x8f, 0x97, 0x9e, 0xf5, 0x02, 0x7f, 0x08, 0x47, 0xbc, 0xfc, 0x0a,
+       0xd9, 0x0e, 0xe7, 0x4b, 0xfa, 0x7a, 0x25, 0xd7, 0xd7, 0x30, 0xef, 0x10,
+       0xd2, 0x09, 0xe6, 0x1d, 0xc2, 0x73, 0xf8, 0x17, 0x3c, 0x4a, 0x0c, 0x5e,
+       0xc5, 0xfa, 0x20, 0xf0, 0x5d, 0xa5, 0x03, 0x9e, 0x01, 0x8f, 0x3b, 0xec,
+       0xa1, 0xbe, 0x98, 0xaf, 0x95, 0xa6, 0xf2, 0x7c, 0x98, 0xcb, 0xc9, 0x2f,
+       0xcc, 0x47, 0xfc, 0x8e, 0x80, 0x87, 0xf4, 0x4e, 0x6c, 0xff, 0x6b, 0x05,
+       0x7f, 0x6c, 0x11, 0xf7, 0xe8, 0x1e, 0xb6, 0x81, 0x3c, 0xa3, 0x9c, 0xb9,
+       0x39, 0xbc, 0xe7, 0xf6, 0x64, 0x51, 0xbf, 0x75, 0xa2, 0xde, 0xe5, 0xf5,
+       0xe1, 0x95, 0xc9, 0xcf, 0x16, 0x91, 0xaf, 0x02, 0xf0, 0x53, 0x3e, 0x66,
+       0xd5, 0xab, 0xfd, 0xb6, 0x58, 0xe1, 0xaf, 0x17, 0xf0, 0x07, 0x97, 0xe3,
+       0x39, 0xc2, 0xd4, 0x27, 0x98, 0x7f, 0x39, 0x23, 0xbc, 0x45, 0x10, 0x5f,
+       0x29, 0x5e, 0xbe, 0x9e, 0xb4, 0xe8, 0x41, 0xb2, 0xdf, 0xba, 0x9e, 0x64,
+       0xe4, 0xb7, 0x0e, 0x01, 0x3b, 0xc2, 0x07, 0xe5, 0x9a, 0x52, 0xf7, 0x48,
+       0x25, 0x27, 0x2a, 0xa7, 0x79, 0xcd, 0x0a, 0xd1, 0xb1, 0x70, 0x03, 0xac,
+       0xd3, 0x88, 0x37, 0xa7, 0xc4, 0xdb, 0x1b, 0x3b, 0xcd, 0xe3, 0x6e, 0xf0,
+       0x78, 0x2c, 0xf7, 0x10, 0x54, 0x0a, 0xfa, 0x0f, 0x81, 0xf5, 0xfd, 0xa7,
+       0x00, 0xef, 0x10, 0xe8, 0xe7, 0x45, 0x82, 0x9b, 0xc3, 0x75, 0xf2, 0xf1,
+       0xe6, 0xeb, 0x31, 0x3e, 0xd7, 0xbd, 0xde, 0x0b, 0xbe, 0xe8, 0x09, 0x67,
+       0x44, 0xef, 0xc7, 0xe1, 0xa4, 0xbc, 0x0a, 0xb4, 0x77, 0x7c, 0xa3, 0xa3,
+       0x70, 0x62, 0xff, 0x94, 0xe7, 0xe3, 0x2e, 0x5d, 0x86, 0xfd, 0x56, 0xff,
+       0x66, 0x77, 0x3f, 0x73, 0xbf, 0x2f, 0x76, 0xf7, 0x3b, 0x7b, 0xa2, 0x0b,
+       0xf5, 0xd8, 0x7a, 0xd0, 0xab, 0xa4, 0x0e, 0x82, 0x87, 0xf0, 0x1c, 0xc9,
+       0xdc, 0xbd, 0xc9, 0x06, 0xde, 0xf7, 0x00, 0xfe, 0x82, 0x0d, 0xfd, 0x42,
+       0x39, 0xee, 0x5c, 0x4d, 0xfe, 0xee, 0x4f, 0x7b, 0x21, 0xde, 0x77, 0x9e,
+       0xd7, 0x3d, 0x0e, 0xe8, 0x4f, 0x93, 0xfe, 0x3b, 0xe0, 0x71, 0xf3, 0xfa,
+       0xce, 0x83, 0x03, 0xf1, 0x1e, 0x6d, 0xa6, 0xf1, 0xf5, 0x29, 0xad, 0xe9,
+       0xf4, 0x8f, 0x70, 0x1f, 0xa2, 0xb7, 0x75, 0xf5, 0x6f, 0xc5, 0x0f, 0x40,
+       0x47, 0x9a, 0x77, 0xd7, 0x2e, 0x98, 0x97, 0x2f, 0x8a, 0xbf, 0x96, 0xe6,
+       0x59, 0xcb, 0x5c, 0xa8, 0x2f, 0x4f, 0x30, 0x3f, 0xea, 0x4b, 0x39, 0xaf,
+       0x21, 0x33, 0xdb, 0xbd, 0x98, 0x7f, 0x53, 0x23, 0xf4, 0x28, 0xe0, 0xc5,
+       0x86, 0x7c, 0x90, 0xfa, 0xcf, 0x3e, 0xb6, 0xdc, 0x67, 0xd2, 0xcf, 0x82,
+       0x7e, 0x43, 0x19, 0x97, 0x37, 0xe9, 0x9f, 0x0c, 0xc5, 0x0d, 0x12, 0x28,
+       0xbf, 0xe3, 0x29, 0x10, 0x7a, 0x8b, 0x51, 0x9c, 0xe0, 0xe4, 0xab, 0xfb,
+       0x7e, 0xca, 0xef, 0xed, 0xe0, 0xf4, 0xaa, 0x99, 0xc9, 0xe9, 0x2b, 0xe5,
+       0xf5, 0x2b, 0x4f, 0x30, 0xc5, 0x8b, 0xf6, 0xe9, 0x5d, 0x0f, 0x4d, 0xe4,
+       0x97, 0xe1, 0x46, 0xe8, 0x9e, 0xe6, 0xca, 0x0d, 0x7c, 0x1c, 0xa8, 0xd7,
+       0xcc, 0x48, 0x6e, 0xdb, 0xb2, 0x67, 0x62, 0xfe, 0x25, 0xf2, 0xd3, 0x98,
+       0x9e, 0x74, 0x4b, 0x2d, 0x6d, 0x76, 0x51, 0x7b, 0xc1, 0xff, 0x67, 0x5f,
+       0x19, 0x1e, 0x46, 0x3e, 0x4c, 0xbb, 0xbd, 0xab, 0x18, 0xdf, 0x03, 0x3f,
+       0x10, 0x3c, 0x2d, 0xcd, 0x9e, 0x30, 0xfa, 0xcb, 0x64, 0x2f, 0x63, 0xfb,
+       0x7d, 0x0a, 0x5f, 0xbf, 0x58, 0x90, 0xf0, 0x32, 0x77, 0xa6, 0xe1, 0x37,
+       0xf3, 0x89, 0x84, 0xaf, 0x9b, 0xee, 0x0c, 0xe8, 0x3e, 0x3c, 0xfa, 0x7e,
+       0xc8, 0x4c, 0xde, 0x6f, 0x4d, 0x2b, 0xf4, 0xcb, 0xfb, 0x21, 0xf9, 0xa9,
+       0xbc, 0x9f, 0xf1, 0xfb, 0xa9, 0x05, 0x7d, 0x80, 0xd5, 0x42, 0x8e, 0x91,
+       0x51, 0xbd, 0x03, 0xe5, 0x88, 0x23, 0x25, 0x8a, 0x47, 0x89, 0x3f, 0xd9,
+       0xbe, 0xfa, 0x7e, 0xfe, 0xdb, 0x3d, 0x18, 0x2f, 0x40, 0x3f, 0xaf, 0x86,
+       0xb5, 0x53, 0xdc, 0xb4, 0x52, 0x2d, 0xed, 0x8f, 0xfe, 0x1a, 0xcb, 0x70,
+       0xd0, 0x39, 0x5b, 0xf0, 0x7f, 0x49, 0xff, 0x1c, 0x76, 0x31, 0xcd, 0x05,
+       0xed, 0x5f, 0x87, 0x27, 0xae, 0xef, 0x93, 0xd5, 0x45, 0x74, 0x1e, 0x6a,
+       0xf2, 0x20, 0x85, 0xe4, 0x1c, 0x24, 0x49, 0xc6, 0xcb, 0xe8, 0xf7, 0xc6,
+       0x6e, 0xbd, 0x21, 0x91, 0xe7, 0xbd, 0x7d, 0xf5, 0xdd, 0xc1, 0x38, 0x9f,
+       0xb4, 0x44, 0xce, 0x77, 0xd0, 0x8f, 0x53, 0xf4, 0xe3, 0x24, 0x3b, 0x55,
+       0xe8, 0xc3, 0x5f, 0x67, 0x83, 0x3e, 0x34, 0xf9, 0xa5, 0x87, 0x15, 0x85,
+       0xfa, 0x39, 0xfc, 0xad, 0x6b, 0xb6, 0x2e, 0x57, 0xa2, 0xf3, 0xc4, 0xfe,
+       0xd0, 0x6e, 0x38, 0xac, 0x4c, 0xeb, 0x4f, 0xf6, 0xac, 0x88, 0x6b, 0x00,
+       0xde, 0x2c, 0xf9, 0x78, 0x51, 0xfe, 0x0d, 0x09, 0xb8, 0xda, 0xb3, 0xf1,
+       0xbb, 0xd9, 0x4f, 0x42, 0xbf, 0xa6, 0xdb, 0xcf, 0x62, 0x49, 0x0f, 0xdf,
+       0x08, 0x7e, 0xd5, 0xd8, 0x29, 0xcd, 0x11, 0xbc, 0x52, 0xbb, 0x3e, 0x94,
+       0x7c, 0xe3, 0xf7, 0x60, 0xdc, 0xc9, 0xe0, 0x67, 0xb9, 0x60, 0xfe, 0xfd,
+       0x91, 0x8f, 0xd1, 0x2f, 0xc8, 0x09, 0xa9, 0x5e, 0x84, 0x6b, 0x88, 0x42,
+       0xf7, 0x47, 0x1f, 0x49, 0x08, 0xe6, 0xf3, 0x7b, 0x88, 0xf9, 0x38, 0xe9,
+       0x22, 0xee, 0x95, 0x2e, 0xf2, 0xb4, 0xd1, 0x9e, 0xc7, 0xe7, 0x36, 0x2f,
+       0x5f, 0x2f, 0x86, 0x27, 0xf1, 0xf5, 0xe5, 0xa1, 0x24, 0x5e, 0x4e, 0xf7,
+       0xc6, 0x8f, 0x93, 0x3d, 0x21, 0xbe, 0xd7, 0x88, 0x7b, 0xbb, 0x57, 0x17,
+       0xc5, 0xcf, 0x07, 0x1c, 0xe7, 0xb5, 0xc6, 0x39, 0x6f, 0x15, 0xfb, 0x3e,
+       0xe0, 0x6f, 0x8d, 0xf3, 0xa6, 0xf1, 0xfb, 0xe0, 0x79, 0x9e, 0x32, 0xdf,
+       0x27, 0x02, 0xbb, 0x96, 0xf0, 0x5b, 0xfc, 0xf0, 0x4c, 0xda, 0xf7, 0xbc,
+       0xd0, 0x76, 0x47, 0x12, 0xbf, 0x9f, 0x82, 0xcb, 0xff, 0xc7, 0x4a, 0xe0,
+       0xdf, 0xee, 0x52, 0xf0, 0x59, 0x4a, 0xf7, 0x03, 0x86, 0x7e, 0xab, 0x52,
+       0xbe, 0xff, 0x47, 0x46, 0xc0, 0x8b, 0xf9, 0x61, 0x55, 0x09, 0xf1, 0xf3,
+       0xcf, 0xef, 0x15, 0x70, 0x54, 0x89, 0xf9, 0x9f, 0xae, 0xe3, 0xf7, 0x49,
+       0xcc, 0xc3, 0xfd, 0x48, 0xd0, 0x17, 0xb7, 0x0a, 0xff, 0x6c, 0x41, 0xd3,
+       0x6d, 0x25, 0x48, 0xef, 0x05, 0xe0, 0xbf, 0xe3, 0x7e, 0xa4, 0xcc, 0x7b,
+       0x90, 0xf4, 0x2d, 0xdb, 0xa4, 0x5a, 0xf6, 0x23, 0xe6, 0xe1, 0x7e, 0x64,
+       0x9f, 0xbf, 0xc6, 0x7f, 0xf0, 0xf7, 0xe2, 0x3f, 0x8c, 0xb6, 0xf8, 0x0f,
+       0x72, 0xdc, 0x58, 0x3f, 0xe2, 0x64, 0x5d, 0xa6, 0x65, 0xdf, 0x64, 0x76,
+       0xd3, 0x20, 0x71, 0x8f, 0x07, 0xaf, 0x3f, 0x87, 0xf9, 0x09, 0xee, 0x39,
+       0x2b, 0xfb, 0x59, 0xf6, 0x4f, 0xd9, 0xca, 0xb4, 0x2b, 0xbb, 0xe7, 0x14,
+       0xfc, 0x86, 0x50, 0x5c, 0xf8, 0x74, 0xd2, 0xaf, 0xf2, 0xfd, 0xc9, 0x3a,
+       0x27, 0x0b, 0x99, 0xe1, 0xf8, 0x64, 0x30, 0xe5, 0x8d, 0x8c, 0xf3, 0x06,
+       0x1f, 0xf0, 0x5a, 0xe0, 0x48, 0x64, 0x21, 0x33, 0x1c, 0x6c, 0x02, 0xff,
+       0x5d, 0x2f, 0x17, 0x8f, 0x5b, 0x03, 0xdd, 0x43, 0x66, 0x7b, 0x3a, 0x16,
+       0xae, 0x55, 0xde, 0xbf, 0xd6, 0x4f, 0xcb, 0xed, 0x05, 0xcf, 0x79, 0xff,
+       0x25, 0x7e, 0x5a, 0xe1, 0x04, 0xae, 0xcf, 0xf0, 0x52, 0x22, 0xcc, 0x81,
+       0x19, 0x3b, 0xc9, 0x6a, 0x37, 0x6f, 0xf6, 0xf2, 0x75, 0x72, 0xb3, 0x37,
+       0xd1, 0x62, 0x37, 0xcf, 0x9d, 0x69, 0xad, 0xb7, 0x45, 0xd4, 0xdb, 0x22,
+       0xea, 0x5d, 0xce, 0xff, 0x37, 0xdb, 0xcb, 0xca, 0x20, 0xd4, 0x1b, 0xbc,
+       0x3f, 0xf9, 0x7b, 0x3c, 0x39, 0x67, 0xde, 0xa2, 0xbc, 0xd3, 0xf7, 0xbc,
+       0xdc, 0x0e, 0x38, 0x9e, 0x14, 0xd8, 0x81, 0xf2, 0xb8, 0x56, 0xe4, 0xe9,
+       0x6f, 0xf9, 0xcb, 0xa1, 0xcc, 0x39, 0x68, 0x5f, 0xfc, 0xab, 0x9d, 0xf2,
+       0x04, 0x8a, 0x36, 0x2f, 0x59, 0x8e, 0x79, 0xd4, 0xee, 0x66, 0xc5, 0xa0,
+       0x73, 0x4a, 0xad, 0x56, 0x3e, 0xfa, 0xc7, 0xa5, 0xcd, 0x03, 0xe7, 0x02,
+       0x3e, 0x5e, 0x12, 0x74, 0xaa, 0xf4, 0xf3, 0x79, 0x54, 0xfa, 0x23, 0xfa,
+       0x60, 0x37, 0xe6, 0x75, 0xf3, 0xf1, 0xfb, 0x37, 0x1f, 0x50, 0x34, 0x93,
+       0x9e, 0xe8, 0x5f, 0xc6, 0xeb, 0xed, 0xf3, 0xda, 0x2d, 0x71, 0xf7, 0x03,
+       0x5e, 0x7e, 0x8f, 0xc4, 0x2f, 0xbd, 0x32, 0x3e, 0x18, 0x3e, 0x70, 0x53,
+       0x2a, 0xd6, 0x0f, 0x68, 0xb8, 0xae, 0xf4, 0xc5, 0xdf, 0xc1, 0x01, 0x78,
+       0xfa, 0xd6, 0x32, 0x3a, 0x07, 0xd5, 0x77, 0x34, 0xb7, 0xc7, 0xfe, 0x71,
+       0xf4, 0x16, 0x05, 0x7f, 0x97, 0x4b, 0xce, 0x73, 0xa5, 0x6d, 0x5a, 0xbe,
+       0x01, 0xed, 0x56, 0xa6, 0x27, 0xfa, 0x51, 0x4f, 0x67, 0x1b, 0xc1, 0xd7,
+       0x71, 0x9e, 0x95, 0xef, 0x45, 0x22, 0x18, 0xbe, 0x19, 0xfb, 0x5e, 0x9b,
+       0x86, 0xfe, 0x92, 0xdf, 0x08, 0x1c, 0x45, 0x7e, 0x95, 0xf3, 0xf2, 0xa9,
+       0x46, 0x5f, 0x5c, 0x6f, 0x12, 0xdf, 0xe3, 0xf0, 0x35, 0x75, 0xc7, 0x21,
+       0xb8, 0x9e, 0x66, 0x6c, 0x8d, 0xf0, 0x5f, 0xb6, 0x72, 0x3b, 0x56, 0x65,
+       0x47, 0x19, 0xb7, 0x73, 0x69, 0xbf, 0x36, 0x7d, 0xd9, 0x50, 0x5a, 0x2f,
+       0xe4, 0x7c, 0xd2, 0x53, 0x84, 0xbe, 0x4d, 0x67, 0xc1, 0xdd, 0x64, 0x6f,
+       0xb3, 0x95, 0xb4, 0xde, 0x39, 0xf9, 0xfa, 0x99, 0xbe, 0x8c, 0xff, 0x8e,
+       0x9e, 0xa4, 0x67, 0x34, 0x7e, 0x32, 0x6c, 0x24, 0xc6, 0x4f, 0x06, 0xad,
+       0x8d, 0x68, 0xb3, 0xa1, 0xdd, 0xab, 0x9b, 0x6c, 0x71, 0xef, 0xdd, 0x38,
+       0x25, 0xf0, 0x0e, 0xf3, 0xf8, 0x00, 0xe7, 0x17, 0x4b, 0x9f, 0x5e, 0xd7,
+       0x1d, 0x51, 0xcf, 0xde, 0x4b, 0x5c, 0x4a, 0xf2, 0x7b, 0xe2, 0x94, 0xf8,
+       0xfe, 0x1e, 0x63, 0x8f, 0xd0, 0xf7, 0xa2, 0xcd, 0xa9, 0xf7, 0x90, 0x5c,
+       0x36, 0xe8, 0x74, 0x4f, 0xa2, 0xc4, 0xbf, 0xdf, 0x28, 0xfd, 0x23, 0xc2,
+       0xd3, 0xb7, 0x79, 0x8b, 0x82, 0xb8, 0x39, 0x29, 0xf2, 0x19, 0x4e, 0xae,
+       0xfe, 0xa9, 0x82, 0xf6, 0xd6, 0x77, 0x17, 0x32, 0x43, 0x8d, 0xc3, 0x4f,
+       0xdd, 0xf2, 0xba, 0x74, 0xf7, 0xc0, 0xb9, 0x26, 0x7d, 0x03, 0xfd, 0x13,
+       0x3d, 0xb6, 0xc4, 0xe4, 0xa7, 0x4b, 0xff, 0xc4, 0x9d, 0xc4, 0xf5, 0xf8,
+       0x3c, 0xa3, 0x54, 0x4d, 0x4a, 0xa3, 0x7c, 0x61, 0x8a, 0xe3, 0x2d, 0xdc,
+       0xce, 0x7f, 0x8f, 0xa3, 0x57, 0x7c, 0x5c, 0x21, 0xbe, 0x94, 0x32, 0xee,
+       0xc7, 0x54, 0xce, 0xe0, 0xbf, 0x47, 0x5a, 0xb4, 0x59, 0x23, 0x7a, 0x57,
+       0x34, 0xf0, 0xdf, 0x23, 0xac, 0xdc, 0xb9, 0x8b, 0xce, 0xe3, 0xb1, 0x87,
+       0x98, 0x1f, 0xe5, 0xbd, 0xb2, 0x79, 0x97, 0x32, 0x17, 0xc6, 0xad, 0xd8,
+       0xb9, 0x4b, 0x99, 0x67, 0xc2, 0x5f, 0xbf, 0xca, 0x30, 0xe5, 0x75, 0x5f,
+       0xe5, 0x91, 0x71, 0xea, 0x08, 0xdd, 0x3b, 0x16, 0xcb, 0xd7, 0x18, 0xdf,
+       0xc7, 0xf5, 0xfd, 0x88, 0x8b, 0xcb, 0x7b, 0x47, 0x91, 0x3b, 0x84, 0x71,
+       0xeb, 0x0e, 0x7b, 0xb0, 0x12, 0xeb, 0x75, 0x64, 0x25, 0xfa, 0x71, 0x7f,
+       0x54, 0xe2, 0xfb, 0xf5, 0x5d, 0x37, 0xd2, 0xfd, 0x07, 0x9e, 0xdd, 0x8e,
+       0x08, 0x3e, 0x57, 0xda, 0xb6, 0x66, 0x3a, 0xa1, 0xde, 0xca, 0xab, 0x75,
+       0x3f, 0xf2, 0x91, 0xdf, 0x08, 0x0e, 0x45, 0xbc, 0xa4, 0x68, 0xa5, 0x2d,
+       0xd8, 0x3e, 0x39, 0xd5, 0xe3, 0xc7, 0xb8, 0xb7, 0xcf, 0xc1, 0x46, 0xd2,
+       0x3a, 0x77, 0x85, 0x78, 0x18, 0x1b, 0xc3, 0x0f, 0x63, 0x1f, 0xe2, 0x72,
+       0x72, 0x4f, 0x92, 0x57, 0xda, 0x59, 0x94, 0x6f, 0x35, 0x31, 0xc9, 0x23,
+       0xed, 0x0e, 0xd2, 0x4f, 0x47, 0xec, 0x7c, 0x1e, 0xbb, 0x19, 0x87, 0x77,
+       0x9b, 0x37, 0x30, 0x16, 0xe1, 0x61, 0x47, 0xf9, 0xef, 0x29, 0xf4, 0xad,
+       0x8c, 0x28, 0x98, 0xa7, 0x12, 0x3b, 0x6e, 0x94, 0x9f, 0x02, 0xdf, 0x4a,
+       0xfa, 0x06, 0xfc, 0x0d, 0xf6, 0x92, 0x8e, 0x7a, 0xbd, 0x42, 0xe8, 0x99,
+       0xa2, 0xcd, 0xdb, 0x95, 0x0f, 0x4d, 0x70, 0x4f, 0x45, 0x63, 0x04, 0xf9,
+       0x73, 0xe7, 0x16, 0x05, 0xe3, 0x2a, 0xf0, 0x9d, 0xf4, 0x0c, 0xd4, 0x67,
+       0x98, 0x0f, 0xd5, 0x77, 0x27, 0x8f, 0x27, 0x55, 0xc0, 0xf7, 0x79, 0x26,
+       0xbd, 0x22, 0xe7, 0x11, 0x47, 0xbf, 0xdc, 0x86, 0xf0, 0xb9, 0xdf, 0x6b,
+       0x7b, 0x8d, 0xeb, 0x97, 0x08, 0x8f, 0x23, 0x0b, 0x78, 0x63, 0xe9, 0x79,
+       0x7f, 0x12, 0xb7, 0xdb, 0x4a, 0x60, 0x59, 0xa5, 0xf7, 0x7a, 0x68, 0x28,
+       0xfa, 0x9b, 0x47, 0x72, 0x13, 0xa8, 0x3f, 0x29, 0xef, 0xb1, 0xf2, 0x79,
+       0xbf, 0xe0, 0xf3, 0xbe, 0x9b, 0xb6, 0x2b, 0x36, 0x37, 0xc5, 0xdb, 0xc9,
+       0xfe, 0x92, 0xf0, 0xc9, 0x7a, 0xc7, 0x93, 0x26, 0xce, 0x49, 0x1a, 0x83,
+       0x78, 0x68, 0x23, 0x3c, 0x54, 0x6d, 0xd2, 0x68, 0x3e, 0x93, 0xf5, 0xd2,
+       0xc1, 0x8b, 0x4c, 0xf2, 0xb0, 0x48, 0xf4, 0x77, 0xf0, 0xae, 0xf7, 0xe9,
+       0x5e, 0xa0, 0x0d, 0x3f, 0x3f, 0x46, 0xfc, 0x58, 0xd5, 0xa4, 0x70, 0xbb,
+       0xbf, 0xe9, 0x98, 0x7e, 0x07, 0xae, 0x2b, 0xa1, 0xe7, 0x54, 0xdc, 0x1f,
+       0xb9, 0x99, 0x2f, 0xe5, 0xec, 0x71, 0x71, 0x5f, 0xd6, 0xcd, 0x2d, 0x5c,
+       0xff, 0x56, 0xb5, 0xec, 0xd2, 0xf0, 0x7e, 0x49, 0xc9, 0xa7, 0x39, 0x67,
+       0x0e, 0xd2, 0x3d, 0x5b, 0x55, 0xcd, 0x0e, 0x86, 0xfb, 0xa5, 0xc0, 0x7f,
+       0xdf, 0x43, 0xfc, 0xc4, 0xf2, 0xa9, 0xc4, 0x8f, 0xd4, 0xaf, 0xbd, 0xd1,
+       0x13, 0xf4, 0x10, 0x3f, 0xa7, 0x10, 0xd2, 0x45, 0x9c, 0x3a, 0x98, 0x33,
+       0xdd, 0x13, 0xd5, 0xcf, 0xdb, 0xbc, 0x62, 0x7f, 0xd4, 0xcd, 0xdf, 0x6f,
+       0x48, 0xe2, 0xe5, 0x28, 0xff, 0x04, 0x57, 0x25, 0x59, 0xf4, 0xab, 0x8b,
+       0xe4, 0x22, 0xe7, 0xcc, 0xc8, 0x83, 0x98, 0x0f, 0x5a, 0xe5, 0x57, 0xe8,
+       0x5c, 0x65, 0x6a, 0xb1, 0xf8, 0x7d, 0x32, 0x13, 0x5c, 0xe6, 0xf3, 0x31,
+       0xb1, 0xfa, 0x11, 0xe3, 0xe1, 0x3c, 0x7e, 0xd2, 0x9e, 0x3d, 0xdd, 0x74,
+       0x3e, 0xae, 0x5b, 0xcf, 0x8b, 0xf6, 0x4f, 0x20, 0xbd, 0xf9, 0xfb, 0x08,
+       0x7f, 0xcf, 0x72, 0x71, 0xbd, 0x96, 0xf0, 0xc7, 0xd2, 0xef, 0x90, 0xb0,
+       0xc7, 0xe3, 0xf0, 0x59, 0x38, 0x29, 0xce, 0x3a, 0x26, 0xd7, 0xf5, 0x9c,
+       0xa7, 0x77, 0x6b, 0x78, 0x8f, 0x92, 0xe4, 0x9f, 0x9b, 0x91, 0xee, 0x26,
+       0xfe, 0xf9, 0x59, 0x12, 0xbf, 0x8f, 0xf7, 0x67, 0x49, 0x1a, 0xf5, 0xff,
+       0x78, 0x11, 0xdf, 0xa7, 0x7a, 0xdc, 0xce, 0xd7, 0xaf, 0xc7, 0xeb, 0x9d,
+       0x94, 0xbf, 0xf9, 0xfa, 0xdd, 0x3c, 0x9f, 0xcc, 0x73, 0x8f, 0x1e, 0xc1,
+       0xe7, 0x61, 0xdb, 0xec, 0x4a, 0xfc, 0x7e, 0xb8, 0x2f, 0x87, 0x63, 0xa5,
+       0x6d, 0x19, 0x9d, 0xf7, 0x03, 0xb9, 0x6c, 0x4e, 0x22, 0xfe, 0xf1, 0x32,
+       0xae, 0x1f, 0xb9, 0x3e, 0xdc, 0xf0, 0x12, 0xd7, 0x67, 0x95, 0x21, 0x37,
+       0xdd, 0x77, 0x5a, 0x19, 0xbc, 0x7d, 0x2e, 0xe5, 0xd9, 0xa6, 0xba, 0xfc,
+       0x74, 0x3f, 0x68, 0xf0, 0x35, 0xfd, 0x0e, 0x4f, 0x4f, 0xbe, 0xf2, 0xed,
+       0x3e, 0x40, 0xbf, 0x8b, 0x7c, 0x73, 0x33, 0x97, 0x3f, 0x49, 0x07, 0xd0,
+       0xa7, 0xc4, 0x5f, 0x52, 0x1e, 0x24, 0x5e, 0xa3, 0xf8, 0xe4, 0x78, 0x97,
+       0xf2, 0x24, 0xe9, 0xb1, 0x4d, 0xee, 0x0b, 0x00, 0xbf, 0x70, 0xfb, 0x88,
+       0xfb, 0x23, 0xf9, 0x4c, 0xa5, 0xfd, 0x9f, 0x32, 0x67, 0xe0, 0x08, 0x9e,
+       0xcb, 0x2c, 0x13, 0xfb, 0xa5, 0xf9, 0xe2, 0x77, 0x5f, 0xe4, 0x7e, 0xe9,
+       0x6c, 0x41, 0x97, 0x02, 0x5b, 0xe9, 0xaf, 0x71, 0x9e, 0x3d, 0xf6, 0x4b,
+       0xaf, 0xd0, 0xae, 0xae, 0x58, 0xfa, 0xab, 0x61, 0x18, 0x0f, 0x29, 0xcf,
+       0x3c, 0x4a, 0x4f, 0x29, 0xb7, 0xe0, 0xf7, 0x59, 0xe4, 0xfb, 0x7d, 0x41,
+       0xf7, 0xc3, 0xe2, 0xf9, 0xb1, 0xe0, 0x9b, 0x8a, 0xd1, 0xcd, 0x24, 0x97,
+       0x15, 0x1f, 0xd5, 0x92, 0x3c, 0xbb, 0xa7, 0x70, 0xbd, 0xe6, 0x7e, 0xcf,
+       0xaa, 0x8f, 0x19, 0x5b, 0x27, 0xe6, 0xbb, 0x96, 0xda, 0x4f, 0x4e, 0x6c,
+       0x2e, 0xc1, 0xfd, 0xc6, 0xc9, 0x3f, 0x56, 0x0c, 0xf4, 0x87, 0x7b, 0x83,
+       0x73, 0x01, 0x9e, 0x53, 0x43, 0xff, 0x68, 0xd3, 0x21, 0xef, 0x2c, 0xc4,
+       0xaf, 0xf8, 0x7d, 0x29, 0x79, 0x9e, 0xe7, 0x0b, 0xa1, 0x27, 0x3a, 0x76,
+       0xa8, 0xe2, 0xf7, 0x36, 0x6b, 0xf5, 0x4b, 0xd9, 0xdf, 0x97, 0xeb, 0x8f,
+       0x45, 0x8e, 0x2b, 0x74, 0xef, 0x89, 0xf0, 0xa9, 0x3a, 0x76, 0x16, 0x8f,
+       0xff, 0x18, 0xfd, 0xba, 0x1d, 0x49, 0xf4, 0xfb, 0x27, 0x9f, 0xed, 0xbc,
+       0xed, 0xfb, 0x1f, 0xa7, 0xe2, 0xef, 0x8b, 0xdc, 0xe0, 0x47, 0x3b, 0x21,
+       0x75, 0x79, 0x29, 0xf1, 0x4f, 0x57, 0x9a, 0xcb, 0xbf, 0x95, 0xc7, 0x3d,
+       0xa7, 0x60, 0x5c, 0xa7, 0xbe, 0xf9, 0x90, 0x17, 0xcf, 0xff, 0xfc, 0x6f,
+       0x59, 0x68, 0xc8, 0xa8, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd5, 0x7d,
+       0x09, 0x78, 0x54, 0xd5, 0xd9, 0xf0, 0xb9, 0x73, 0x67, 0x0b, 0x99, 0x49,
+       0x66, 0x26, 0x7b, 0xc8, 0x32, 0x09, 0x10, 0x50, 0x49, 0x98, 0x84, 0x84,
+       0x7d, 0x99, 0x24, 0x84, 0x45, 0x16, 0x27, 0x08, 0x05, 0x64, 0x1b, 0xf6,
+       0x00, 0xd9, 0x58, 0xda, 0x62, 0xa5, 0x7f, 0x06, 0x83, 0x88, 0x88, 0x6d,
+       0x68, 0xad, 0x22, 0x5a, 0xbf, 0x01, 0xc1, 0x62, 0xb5, 0x35, 0x60, 0xa4,
+       0x41, 0x02, 0x0e, 0xb2, 0x08, 0x55, 0x3f, 0x47, 0x0a, 0x16, 0x5b, 0xb4,
+       0x23, 0x22, 0xb2, 0x84, 0x64, 0x8a, 0xad, 0xa5, 0x5f, 0xf9, 0x3e, 0xfe,
+       0xf3, 0xbe, 0xe7, 0x9c, 0xcc, 0xdc, 0x9b, 0x09, 0xa8, 0x5f, 0xdb, 0xe7,
+       0xff, 0xc3, 0xe3, 0x73, 0x3c, 0xf7, 0xdc, 0x7b, 0x96, 0xf7, 0xbc, 0xfb,
+       0xfb, 0x9e, 0x33, 0x97, 0x5f, 0xee, 0x57, 0x60, 0xb0, 0x13, 0x62, 0xb6,
+       0x68, 0x08, 0x49, 0x20, 0xe4, 0xca, 0x6b, 0xf2, 0x1a, 0xaf, 0x89, 0x90,
+       0x87, 0x7f, 0xf1, 0xea, 0x88, 0xa1, 0x85, 0x84, 0x2c, 0xf7, 0x4a, 0x71,
+       0x06, 0x42, 0x48, 0xeb, 0xee, 0xff, 0xf8, 0x9f, 0xd4, 0x78, 0x42, 0x2a,
+       0x76, 0xd6, 0x58, 0x24, 0x5a, 0xaf, 0x7f, 0xf9, 0x4d, 0x7d, 0x80, 0xbe,
+       0xa7, 0xf1, 0x6e, 0x67, 0xcf, 0x77, 0xc7, 0x5a, 0xe0, 0xbd, 0xcb, 0x2f,
+       0x6c, 0x19, 0x41, 0xfa, 0xd2, 0xf6, 0xc6, 0x7a, 0x6c, 0xbf, 0xf2, 0xc2,
+       0x76, 0xac, 0xbf, 0xf5, 0x8b, 0x57, 0x0f, 0xfd, 0x17, 0x7d, 0xaf, 0xd2,
+       0x15, 0xe3, 0x80, 0xf7, 0xae, 0xbc, 0x76, 0x58, 0x0f, 0xcf, 0x2b, 0xdd,
+       0x5a, 0x67, 0x23, 0x2d, 0x89, 0xfb, 0xa8, 0x7e, 0xaa, 0x99, 0x96, 0x9e,
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+       0x6f, 0xcf, 0xa5, 0xf5, 0x46, 0x3a, 0x2a, 0xfd, 0x9e, 0x4c, 0xd7, 0x7b,
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+       0x3c, 0x71, 0xe1, 0xcf, 0x19, 0x1f, 0xad, 0xd1, 0x06, 0xf5, 0xa0, 0x42,
+       0xd6, 0xdc, 0xc8, 0x20, 0x1e, 0x3a, 0xee, 0xc7, 0x1a, 0x52, 0xd1, 0x18,
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+       0x73, 0x8e, 0x67, 0xbb, 0x75, 0x24, 0x67, 0x2b, 0xcc, 0x67, 0x3b, 0xe5,
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+       0x55, 0xb4, 0xd7, 0x13, 0xc6, 0xff, 0xa6, 0x71, 0xf8, 0xa8, 0xf1, 0x6c,
+       0x37, 0xe0, 0x28, 0x9d, 0xef, 0x27, 0x12, 0x93, 0x2b, 0xea, 0x71, 0x5e,
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+       0x71, 0xd0, 0x60, 0x01, 0x3e, 0x21, 0xf0, 0x49, 0xe0, 0x91, 0x1a, 0x7f,
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+       0x1c, 0xdb, 0x6f, 0xfa, 0xde, 0x60, 0x58, 0xcf, 0x2c, 0x43, 0x70, 0x4e,
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+       0xbf, 0x99, 0x14, 0xf2, 0x98, 0xa8, 0xe4, 0xf5, 0x82, 0xe6, 0x93, 0xa8,
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+       0x12, 0x2d, 0xa5, 0xb7, 0xc9, 0x7c, 0x3e, 0xf7, 0xb7, 0x30, 0xfd, 0x50,
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+       0xf3, 0xa5, 0xcc, 0x52, 0x4b, 0xeb, 0xc3, 0x3b, 0xe6, 0x0f, 0xce, 0x43,
+       0x42, 0x86, 0xf1, 0xf9, 0x4b, 0xf0, 0x3d, 0x85, 0xef, 0x70, 0x5e, 0x92,
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+       0x5b, 0x27, 0x9d, 0x41, 0x22, 0x7c, 0xdf, 0x01, 0x2f, 0xac, 0x9b, 0x79,
+       0x7d, 0xfd, 0x94, 0xeb, 0x73, 0x16, 0xc1, 0x73, 0x93, 0x19, 0xf9, 0x86,
+       0x9e, 0xcf, 0xe3, 0x16, 0xf0, 0x3f, 0x23, 0xf2, 0x13, 0x23, 0xac, 0xdb,
+       0x60, 0xf2, 0x5d, 0x86, 0x75, 0x99, 0x79, 0xe9, 0x29, 0x61, 0xfa, 0xb6,
+       0x27, 0x9b, 0x38, 0xea, 0xe9, 0x6b, 0xdd, 0x48, 0x23, 0x81, 0x71, 0x4d,
+       0xa6, 0x6b, 0x1e, 0x58, 0xac, 0x85, 0x58, 0x24, 0xa8, 0x47, 0x59, 0xae,
+       0xfb, 0xc0, 0xee, 0xb8, 0x66, 0x31, 0x79, 0x34, 0xfd, 0x90, 0x2f, 0xca,
+       0x71, 0x14, 0x7e, 0xad, 0xd2, 0xbb, 0x8b, 0x61, 0x5f, 0x28, 0x1f, 0x66,
+       0x7e, 0xa8, 0xae, 0xda, 0xb5, 0x3e, 0xb4, 0x77, 0x04, 0x5f, 0xb3, 0xf1,
+       0xf9, 0xd5, 0x73, 0xbe, 0x96, 0x42, 0x18, 0x1c, 0xe2, 0x89, 0xeb, 0xb0,
+       0x93, 0xf2, 0x85, 0x9f, 0x98, 0x17, 0x4f, 0x20, 0x31, 0x20, 0x8e, 0xdd,
+       0x38, 0xfe, 0x33, 0x31, 0x63, 0x4f, 0xc0, 0x7c, 0x01, 0xf0, 0x28, 0xaf,
+       0xc7, 0x6a, 0xcf, 0x87, 0xcb, 0x8b, 0x04, 0x97, 0x56, 0xc1, 0xb7, 0x92,
+       0xa6, 0x2b, 0xeb, 0x29, 0x6e, 0x65, 0xdd, 0x48, 0xce, 0x59, 0x00, 0x7f,
+       0x25, 0x9f, 0x2b, 0xf9, 0x56, 0x1c, 0xda, 0x71, 0x7d, 0xc0, 0x2f, 0xa3,
+       0xe3, 0xfc, 0x62, 0x4a, 0x37, 0x36, 0x2f, 0x81, 0x3f, 0xd9, 0x71, 0x1a,
+       0x85, 0x3e, 0xe1, 0xe2, 0x76, 0x7d, 0xb5, 0x4d, 0x4f, 0xd0, 0x1f, 0x98,
+       0x68, 0x34, 0x92, 0x7e, 0xa8, 0x5f, 0x64, 0xc7, 0x31, 0xfd, 0xe2, 0x13,
+       0xba, 0xd3, 0xd4, 0xfe, 0x0b, 0x22, 0x1f, 0xce, 0x1f, 0xe9, 0xec, 0xf5,
+       0x33, 0x0a, 0xe7, 0x0d, 0x1f, 0xc8, 0x8e, 0x87, 0xe9, 0x3e, 0x6d, 0x30,
+       0xdb, 0xd7, 0x69, 0x41, 0x6f, 0x9b, 0x21, 0x31, 0x3d, 0x5d, 0xdb, 0xe8,
+       0x03, 0x3f, 0xcf, 0xf6, 0x39, 0x56, 0xc7, 0x26, 0x68, 0x8f, 0x72, 0xfe,
+       0xf8, 0xbf, 0xa1, 0xfd, 0x03, 0x99, 0x80, 0xde, 0x54, 0x03, 0xfe, 0x75,
+       0xa4, 0x77, 0x4b, 0x31, 0x7c, 0xb7, 0x3d, 0xc3, 0x82, 0xef, 0xc5, 0x97,
+       0x06, 0xd1, 0x2f, 0x1a, 0x7c, 0x8c, 0xa0, 0x5e, 0xd4, 0x09, 0x4f, 0x6f,
+       0xd2, 0xf9, 0x53, 0x78, 0xbf, 0x00, 0x75, 0x0a, 0xdf, 0x9a, 0x85, 0x96,
+       0xe5, 0xaf, 0xd0, 0xf7, 0x53, 0x5c, 0xd1, 0x0e, 0x29, 0xac, 0x7d, 0x27,
+       0xb4, 0xd3, 0x79, 0x4a, 0x1c, 0x2f, 0xe0, 0xf9, 0xc8, 0x01, 0x60, 0xc7,
+       0xb2, 0xbf, 0x1e, 0x2d, 0xf9, 0x7e, 0x27, 0xf8, 0x29, 0x9c, 0x32, 0xca,
+       0xb5, 0x9a, 0x96, 0xfc, 0x23, 0x26, 0x3a, 0x8f, 0x1e, 0xee, 0x7c, 0x07,
+       0xa0, 0x6d, 0xcf, 0x16, 0x1e, 0x47, 0x89, 0x37, 0x78, 0x59, 0x1c, 0x81,
+       0x52, 0x2d, 0x9d, 0xc7, 0x54, 0x23, 0x9b, 0x47, 0x4d, 0x4b, 0xf1, 0x7d,
+       0x45, 0xb4, 0xbd, 0xa7, 0xbf, 0x3f, 0x81, 0x78, 0x42, 0xf4, 0x09, 0xfb,
+       0xcc, 0x4a, 0x68, 0xd2, 0x50, 0xfb, 0x19, 0xbe, 0x2b, 0x89, 0x46, 0xff,
+       0xd5, 0x69, 0xee, 0x47, 0x22, 0x9c, 0x1f, 0x0c, 0x54, 0xd1, 0xdb, 0xd0,
+       0x10, 0xfe, 0x63, 0x7b, 0xbe, 0xa8, 0x53, 0xf1, 0xef, 0x1c, 0xc0, 0xdc,
+       0x13, 0x58, 0x8f, 0x67, 0x74, 0xe0, 0x20, 0xe2, 0x8f, 0xd1, 0xe7, 0x10,
+       0x12, 0xfa, 0x83, 0xef, 0x4b, 0x43, 0xfd, 0x21, 0x3f, 0x1a, 0x15, 0x6a,
+       0x0e, 0xd1, 0x1b, 0x5d, 0x5a, 0x81, 0xd1, 0x51, 0x5f, 0x49, 0xdf, 0x3b,
+       0x56, 0x3e, 0x06, 0xf1, 0xb0, 0x06, 0xec, 0x27, 0xba, 0x1f, 0x03, 0xb5,
+       0xbe, 0xc3, 0x40, 0xdf, 0x43, 0x79, 0x99, 0xcf, 0x4b, 0x32, 0xbf, 0x01,
+       0xe1, 0xb9, 0x69, 0x9d, 0x53, 0x06, 0xb8, 0x17, 0x11, 0xb7, 0xbc, 0x85,
+       0xd6, 0x07, 0x19, 0xfd, 0x71, 0x40, 0x0f, 0xc3, 0x8c, 0x81, 0x75, 0x09,
+       0xb4, 0xbf, 0xc1, 0xd3, 0xe7, 0x25, 0x43, 0xfd, 0x20, 0x28, 0x59, 0x45,
+       0xa8, 0x67, 0x79, 0xc0, 0x3f, 0x6f, 0x35, 0x69, 0xbc, 0xeb, 0x70, 0x13,
+       0xf3, 0x1d, 0x40, 0x37, 0xd3, 0xa6, 0x33, 0x3f, 0xeb, 0xd4, 0xe9, 0x46,
+       0x2f, 0xf8, 0xed, 0xa7, 0x6a, 0x09, 0x8b, 0x6f, 0x69, 0xdd, 0x59, 0xdf,
+       0xa1, 0xed, 0xdf, 0x99, 0xc5, 0xfc, 0xbb, 0x50, 0x9f, 0x15, 0xe6, 0x3f,
+       0x11, 0xf1, 0x8c, 0xd3, 0xd4, 0x1e, 0xd9, 0x13, 0xc1, 0x9e, 0x3c, 0x18,
+       0xc7, 0xe4, 0x93, 0xf8, 0xbe, 0x66, 0xbd, 0x5e, 0x11, 0x37, 0xda, 0x1f,
+       0x67, 0xc2, 0xf6, 0xff, 0x88, 0x1b, 0xbd, 0x36, 0x0e, 0xf1, 0xdf, 0x9d,
+       0x05, 0xf4, 0xf7, 0x70, 0x1c, 0xd7, 0xab, 0xfa, 0x90, 0x3e, 0xc0, 0x57,
+       0xc2, 0xe8, 0x7e, 0x03, 0xbc, 0xd7, 0x5a, 0xfc, 0x4e, 0x57, 0x7c, 0x41,
+       0xd9, 0xce, 0xf9, 0xc2, 0x54, 0xe7, 0x4f, 0x75, 0xa8, 0x8f, 0x73, 0xfe,
+       0x20, 0xf8, 0xb0, 0x0b, 0xe8, 0x90, 0x7e, 0xe7, 0x97, 0x9c, 0x3a, 0x80,
+       0xe7, 0x47, 0x25, 0x0c, 0xfe, 0xa7, 0x8a, 0x97, 0x22, 0x7f, 0x98, 0x46,
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+       0xc7, 0xd0, 0x71, 0xa6, 0xba, 0x94, 0x7a, 0xcd, 0xb4, 0xe9, 0x6a, 0x3d,
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+       0x79, 0x44, 0xcf, 0xe2, 0x8f, 0x47, 0xa3, 0x88, 0x07, 0xfc, 0xcf, 0x02,
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+       0x33, 0x3a, 0x67, 0xfc, 0xb8, 0x88, 0xf7, 0xa7, 0x96, 0x43, 0x45, 0x5c,
+       0x9f, 0x1a, 0x41, 0xf9, 0x16, 0xd8, 0x91, 0x42, 0x3f, 0xa2, 0xef, 0x63,
+       0xfd, 0xa8, 0xa6, 0x45, 0x4e, 0xd6, 0x84, 0xe6, 0x55, 0xc8, 0xbf, 0x13,
+       0x7a, 0x99, 0xe0, 0xdb, 0x62, 0x5f, 0x8a, 0x07, 0x81, 0x2d, 0x4c, 0x48,
+       0x46, 0x3c, 0xd7, 0x6f, 0xb2, 0x49, 0x36, 0xec, 0x2b, 0xed, 0x1f, 0xe9,
+       0x81, 0x8e, 0xeb, 0xd1, 0xdb, 0xb0, 0x7f, 0x0f, 0xd8, 0x5f, 0x43, 0xf9,
+       0x78, 0x74, 0xdf, 0x3d, 0x20, 0x67, 0x3d, 0x1a, 0xa3, 0x17, 0xf0, 0x68,
+       0x83, 0x54, 0x8b, 0x7c, 0xda, 0x48, 0x38, 0xbf, 0x96, 0xdc, 0xf5, 0xf0,
+       0xf1, 0x6f, 0x3c, 0x1e, 0xe4, 0xdb, 0x83, 0x49, 0xed, 0xfd, 0x13, 0xb2,
+       0x80, 0x5f, 0xfb, 0xa3, 0x01, 0x1e, 0x14, 0x1f, 0xb2, 0xe3, 0xc3, 0xf0,
+       0xa4, 0x9e, 0xf8, 0x32, 0xf6, 0x48, 0x0a, 0x7c, 0xc1, 0xf6, 0x56, 0xeb,
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+       0x8d, 0x31, 0x3d, 0xa9, 0x85, 0xef, 0xdf, 0xd1, 0x8c, 0x43, 0x7c, 0x18,
+       0x4b, 0xbc, 0x5a, 0x98, 0x5f, 0x99, 0x45, 0xb9, 0xcf, 0x63, 0x92, 0x95,
+       0xf5, 0x71, 0xf6, 0x4e, 0x78, 0x20, 0xc3, 0xb8, 0x4e, 0x0e, 0xcf, 0xf1,
+       0x7d, 0x94, 0xed, 0x4e, 0xc1, 0xd7, 0x88, 0x92, 0xaf, 0x65, 0x91, 0x9b,
+       0xb8, 0xcf, 0xe4, 0xb1, 0xe3, 0xdf, 0x05, 0xfb, 0x3e, 0x7a, 0x0d, 0xe9,
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+       0x49, 0xa1, 0x1f, 0x85, 0xc5, 0x3d, 0x46, 0xc5, 0x27, 0x74, 0x8e, 0x7b,
+       0xb4, 0x73, 0x3f, 0xee, 0x10, 0x12, 0x58, 0xfc, 0x8a, 0xd4, 0x19, 0x5f,
+       0xda, 0x8e, 0xad, 0x91, 0x93, 0xc3, 0xf0, 0x4a, 0xe0, 0xf1, 0x1b, 0x3c,
+       0x4f, 0x42, 0x7a, 0x93, 0xc7, 0x57, 0x0b, 0x99, 0x5f, 0x2f, 0x24, 0xe7,
+       0x19, 0xbe, 0x0c, 0xe0, 0xb5, 0x21, 0x80, 0x6f, 0xf4, 0xfd, 0x45, 0x02,
+       0x4f, 0x32, 0x49, 0x26, 0xe0, 0xc9, 0xf0, 0xe6, 0x28, 0x9f, 0x4c, 0xe1,
+       0x9a, 0xcf, 0xfb, 0x19, 0x02, 0x78, 0x53, 0x10, 0x92, 0xe7, 0x3e, 0x8d,
+       0xc9, 0xae, 0xcf, 0x06, 0xfc, 0x70, 0x6c, 0x94, 0xe5, 0xce, 0x7a, 0x7b,
+       0xa2, 0xcd, 0x8e, 0x78, 0xd2, 0x5f, 0x23, 0xe4, 0xbb, 0x23, 0x8e, 0xa0,
+       0x7c, 0x6f, 0xac, 0xd7, 0xc2, 0xfc, 0xf7, 0x0f, 0xec, 0xee, 0x36, 0x29,
+       0xf0, 0x62, 0x29, 0xe2, 0x85, 0x44, 0xf1, 0x02, 0xe9, 0xaa, 0x93, 0x5c,
+       0x54, 0xb6, 0xab, 0xf0, 0x46, 0xec, 0xdf, 0x09, 0xae, 0x2f, 0x8f, 0x21,
+       0x9e, 0x9e, 0x30, 0x1e, 0x65, 0x63, 0x47, 0x41, 0x5f, 0xf6, 0x65, 0x31,
+       0xbc, 0x29, 0x23, 0x4e, 0xc4, 0x93, 0xb7, 0xb3, 0xc7, 0xf1, 0xf8, 0xb3,
+       0x5b, 0x8b, 0xfd, 0x10, 0xa5, 0x3c, 0x2c, 0x35, 0x2a, 0xf1, 0x40, 0x8d,
+       0x57, 0x74, 0x44, 0x4d, 0xf8, 0xb8, 0x6a, 0x3c, 0xeb, 0x0a, 0x6f, 0x32,
+       0x01, 0x6f, 0x84, 0x3c, 0x8c, 0xbb, 0x33, 0xde, 0x3c, 0xde, 0x35, 0xde,
+       0x3c, 0x7e, 0x3b, 0xbc, 0x51, 0xe3, 0x8b, 0xe0, 0x27, 0x7b, 0xa2, 0x2c,
+       0xa5, 0xa0, 0x97, 0xd6, 0x54, 0x48, 0xc8, 0x87, 0xfb, 0xbf, 0xd7, 0xb3,
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+       0x9a, 0xb7, 0x67, 0xb9, 0x4a, 0xa1, 0x5e, 0xb3, 0x86, 0xc5, 0x1b, 0x8a,
+       0x4e, 0xb3, 0x3c, 0x98, 0x9e, 0x6b, 0x59, 0x7b, 0xfe, 0xc3, 0xb5, 0x47,
+       0xcc, 0x20, 0xdf, 0x3d, 0xec, 0xfb, 0x37, 0x2e, 0x6f, 0x90, 0x63, 0x68,
+       0xbb, 0x77, 0x03, 0xff, 0xbe, 0xb8, 0xa1, 0x14, 0xea, 0x35, 0x1b, 0xd9,
+       0xf7, 0x5f, 0x40, 0xbc, 0x88, 0xee, 0xef, 0x80, 0xb3, 0xde, 0x7a, 0x78,
+       0x7e, 0xd7, 0xe6, 0x2c, 0x07, 0x33, 0x3f, 0x99, 0x3e, 0x3b, 0x92, 0xe3,
+       0xe9, 0x1e, 0x69, 0xef, 0x11, 0xfc, 0xae, 0x81, 0x7d, 0xb7, 0xe4, 0xb8,
+       0xb1, 0x1b, 0x41, 0x3d, 0x98, 0xe9, 0xad, 0x23, 0xf8, 0x3a, 0x47, 0x3e,
+       0xc7, 0xd6, 0x19, 0xff, 0xd9, 0xbd, 0x63, 0xed, 0x14, 0x7f, 0x17, 0x05,
+       0x3d, 0xa8, 0x37, 0x5d, 0xd4, 0x54, 0x0e, 0x40, 0x7e, 0xd3, 0x85, 0x9d,
+       0x59, 0x2c, 0x35, 0xa4, 0x41, 0x49, 0xf1, 0x06, 0xf9, 0x8c, 0xd3, 0x48,
+       0xf1, 0x3a, 0x9b, 0xc5, 0x13, 0x77, 0xd0, 0x21, 0xde, 0x8e, 0x67, 0x7a,
+       0xa0, 0x88, 0xc3, 0x41, 0x5e, 0x40, 0x78, 0x1e, 0xc0, 0xdb, 0xf1, 0x4c,
+       0xde, 0x8b, 0xf7, 0x12, 0x6d, 0x84, 0xc5, 0x8d, 0xb7, 0x99, 0xd1, 0xaf,
+       0x2b, 0xe2, 0x84, 0xbe, 0xa7, 0x89, 0x04, 0x74, 0x06, 0x6b, 0xe4, 0xf2,
+       0x3f, 0x62, 0xdc, 0x70, 0x4c, 0x8f, 0x5a, 0x8c, 0x17, 0x8e, 0xc9, 0x14,
+       0xf1, 0xc2, 0x80, 0x76, 0x3e, 0x1d, 0x37, 0xff, 0xd6, 0x97, 0xa3, 0x23,
+       0xf9, 0x51, 0xfe, 0x93, 0x8f, 0x7b, 0x89, 0xe7, 0x39, 0x88, 0xe7, 0x15,
+       0xde, 0x2c, 0x0d, 0xe0, 0xc5, 0x1e, 0x40, 0x92, 0x54, 0x00, 0x52, 0xf5,
+       0x6f, 0x41, 0x6f, 0xda, 0x03, 0x7e, 0x54, 0x26, 0x34, 0x3c, 0x64, 0x10,
+       0xec, 0x2b, 0xab, 0x9f, 0x8b, 0x5f, 0xb6, 0x69, 0x23, 0x35, 0xd2, 0x97,
+       0x68, 0x6a, 0xb5, 0x1e, 0x10, 0x32, 0x19, 0xd4, 0xfe, 0xa2, 0x5d, 0x4f,
+       0xf2, 0x13, 0x5f, 0x6c, 0x4c, 0xe7, 0xf9, 0x8f, 0xd1, 0x12, 0x1f, 0xc8,
+       0x27, 0xa2, 0x65, 0xf3, 0x5f, 0x5c, 0x4f, 0xe5, 0xa0, 0x14, 0xe2, 0x4b,
+       0x53, 0x05, 0xdb, 0x19, 0xd6, 0x0b, 0xe9, 0x74, 0x0a, 0xdf, 0xa7, 0xcb,
+       0xf1, 0x5c, 0xdf, 0xe8, 0x4f, 0xfa, 0x03, 0xbf, 0x99, 0xca, 0xf7, 0xed,
+       0x3b, 0xc6, 0x5a, 0x1d, 0x93, 0x97, 0x0d, 0x3a, 0x15, 0xfd, 0x5f, 0x43,
+       0xfa, 0x7f, 0xa6, 0x4b, 0xbd, 0x59, 0xd9, 0xae, 0xe2, 0x0f, 0x15, 0x7c,
+       0xdc, 0xc5, 0x5c, 0x5f, 0x5e, 0x4a, 0x82, 0xa8, 0x17, 0x5c, 0x94, 0xbc,
+       0x58, 0x5e, 0x7a, 0x86, 0xe9, 0xcb, 0xcb, 0x4d, 0xa7, 0x51, 0xaf, 0x68,
+       0xdf, 0xc6, 0xf4, 0xc4, 0x4a, 0x12, 0x40, 0xbd, 0x43, 0xed, 0xf7, 0x5b,
+       0xbe, 0x5b, 0x59, 0xaf, 0x6a, 0x54, 0xd6, 0x6b, 0x9a, 0x95, 0xf5, 0xf6,
+       0x5c, 0x0f, 0x8e, 0xd3, 0xfe, 0x4c, 0xd5, 0x00, 0xf0, 0xbf, 0x55, 0x6c,
+       0x7d, 0x0f, 0xfd, 0xbb, 0x15, 0x82, 0x4f, 0x78, 0x95, 0x7c, 0x82, 0x2a,
+       0x48, 0x8c, 0x4f, 0x3c, 0x7d, 0x37, 0xfa, 0x6d, 0x34, 0x46, 0xca, 0x27,
+       0x0a, 0x01, 0x5c, 0xdd, 0x30, 0x6f, 0xa4, 0x3f, 0x71, 0xc6, 0x01, 0x3f,
+       0x00, 0x21, 0x7b, 0x8b, 0xd6, 0x1f, 0x83, 0x4f, 0x52, 0x68, 0x5d, 0xe3,
+       0x8a, 0x49, 0x40, 0x3f, 0xd6, 0xd8, 0xb8, 0x0b, 0x62, 0x7c, 0x19, 0xe3,
+       0xb2, 0xef, 0x39, 0xed, 0xa1, 0x7d, 0xe9, 0xb0, 0x0b, 0x55, 0x7c, 0x22,
+       0x5f, 0xf8, 0x63, 0x7a, 0xda, 0xd0, 0x5f, 0x25, 0xf8, 0x46, 0x3e, 0x61,
+       0x72, 0x42, 0xad, 0x17, 0xf5, 0x49, 0x50, 0xda, 0x39, 0x42, 0xaf, 0xc8,
+       0x07, 0xbd, 0x82, 0xe2, 0x85, 0x5f, 0x63, 0xf2, 0x6a, 0x34, 0xe1, 0x7a,
+       0x84, 0x17, 0xe9, 0x8f, 0xda, 0x8b, 0xe3, 0xa3, 0xb2, 0x01, 0x65, 0x5c,
+       0x32, 0xd4, 0xfb, 0xcf, 0x28, 0x34, 0xf2, 0x7d, 0x27, 0xaa, 0x7d, 0xed,
+       0x9b, 0x70, 0x7b, 0x7b, 0x49, 0xd9, 0xae, 0xda, 0x77, 0x61, 0xaf, 0x0c,
+       0xe0, 0xfb, 0x3e, 0x83, 0xb8, 0xbb, 0xc3, 0x3e, 0x4c, 0x21, 0xae, 0x63,
+       0x20, 0x17, 0x4e, 0x7d, 0x54, 0xa1, 0xb0, 0x93, 0x3e, 0xfa, 0xc3, 0x68,
+       0xe1, 0x47, 0x41, 0x7b, 0xe9, 0x9b, 0xdb, 0x49, 0x4e, 0xf9, 0xdb, 0xd8,
+       0x49, 0x1d, 0xfb, 0x1d, 0x45, 0xf5, 0x46, 0x5a, 0x96, 0x4e, 0x1e, 0xd7,
+       0xeb, 0x67, 0x10, 0xdf, 0x6e, 0x8a, 0xc2, 0xbc, 0xcd, 0x1a, 0x89, 0xed,
+       0x6f, 0xe2, 0x8c, 0xd3, 0x19, 0xe1, 0x7e, 0xc3, 0x53, 0x75, 0x24, 0x41,
+       0x1b, 0x46, 0xef, 0xf5, 0xe3, 0x0c, 0x46, 0x88, 0xef, 0xd5, 0xeb, 0x98,
+       0x1d, 0x31, 0x79, 0xfc, 0xc7, 0x03, 0xe6, 0x87, 0xf1, 0x8b, 0x17, 0x8c,
+       0xc5, 0x2e, 0x80, 0xd7, 0x06, 0xc9, 0xff, 0xbd, 0x3f, 0x82, 0x5d, 0x71,
+       0x52, 0x26, 0x98, 0x17, 0xd3, 0x92, 0x80, 0xfb, 0x7d, 0xbd, 0x81, 0x3e,
+       0xa7, 0x78, 0x76, 0xfd, 0xb9, 0x7b, 0x1c, 0x1e, 0xfa, 0xf8, 0xaa, 0x8e,
+       0xc5, 0x0b, 0xbf, 0x90, 0x6a, 0x17, 0x43, 0x2a, 0x93, 0x98, 0xc7, 0xe2,
+       0x35, 0xbf, 0x8d, 0xd2, 0x52, 0xf9, 0x75, 0x25, 0xfa, 0x10, 0xc6, 0x83,
+       0xcf, 0xe8, 0xdd, 0xb3, 0x01, 0xef, 0x96, 0xbd, 0xb3, 0x0f, 0xfd, 0x91,
+       0x95, 0xa0, 0x77, 0xf7, 0x08, 0xf5, 0xdb, 0xb5, 0xdf, 0xd1, 0x83, 0x76,
+       0x89, 0xfe, 0x2d, 0x26, 0x07, 0x83, 0x52, 0x37, 0x07, 0xe6, 0x25, 0x10,
+       0x4f, 0x4e, 0x78, 0x9c, 0x68, 0x56, 0x22, 0xe3, 0xaf, 0x67, 0x6c, 0xae,
+       0xa5, 0x30, 0x7f, 0x21, 0xe7, 0x84, 0xdf, 0xff, 0xdc, 0x8a, 0x31, 0xb1,
+       0x20, 0x0a, 0xfe, 0x42, 0x9c, 0xb1, 0x10, 0x9f, 0x94, 0x28, 0x4c, 0xba,
+       0xdb, 0x3a, 0x8f, 0x07, 0xf9, 0x00, 0xeb, 0xc3, 0xfc, 0xcc, 0xe7, 0xa2,
+       0x94, 0xf1, 0x05, 0x51, 0x7e, 0x2f, 0x81, 0xf9, 0xbf, 0xf7, 0x01, 0x2d,
+       0xd1, 0xf1, 0xd2, 0xac, 0xce, 0xef, 0xc3, 0xfa, 0x2e, 0x71, 0x7b, 0xef,
+       0x12, 0x8f, 0x53, 0x5d, 0x8a, 0x61, 0x71, 0xab, 0x87, 0x13, 0x18, 0xff,
+       0xdd, 0xc7, 0xbf, 0xdb, 0xca, 0xcb, 0x4b, 0x3c, 0xae, 0x75, 0xc9, 0xa6,
+       0xb4, 0x13, 0xc5, 0x7b, 0xdb, 0xf8, 0x77, 0x17, 0xea, 0x8c, 0xc6, 0xf5,
+       0x61, 0xfb, 0x68, 0x7f, 0xda, 0x50, 0xeb, 0xc5, 0x3c, 0x28, 0x9e, 0xf7,
+       0xb1, 0x9a, 0x30, 0xbb, 0x68, 0xbf, 0x75, 0xfb, 0xa6, 0xb0, 0xf8, 0xc1,
+       0xae, 0x84, 0xe2, 0x7d, 0x30, 0xaf, 0x84, 0x1e, 0x4e, 0x7d, 0x0a, 0xc0,
+       0x6f, 0x3f, 0x93, 0xbb, 0x10, 0x47, 0x86, 0x78, 0xef, 0x30, 0x8b, 0xbb,
+       0x01, 0xe0, 0x55, 0x6d, 0x27, 0x4e, 0x88, 0x97, 0x12, 0x7b, 0x40, 0x7f,
+       0x3f, 0xc4, 0x0d, 0xc1, 0xce, 0x44, 0x7d, 0x81, 0xe1, 0x49, 0x7b, 0x14,
+       0x2b, 0xc5, 0xbc, 0x76, 0x25, 0x94, 0xef, 0x43, 0x38, 0xaf, 0x08, 0x20,
+       0xdf, 0xea, 0xa8, 0x97, 0x33, 0x7e, 0xb8, 0x2b, 0xc1, 0x85, 0xe3, 0xb6,
+       0x4f, 0x15, 0xed, 0xbc, 0xfe, 0x04, 0xab, 0x13, 0xee, 0x2f, 0x10, 0xfe,
+       0xeb, 0xae, 0xe2, 0x58, 0xea, 0xb8, 0x15, 0xcc, 0x18, 0xf5, 0xea, 0x28,
+       0xc6, 0xb7, 0xd4, 0xf1, 0xea, 0xd9, 0x82, 0x6f, 0xf1, 0x78, 0xf5, 0x2c,
+       0xce, 0x87, 0x66, 0xb7, 0x30, 0x7f, 0xf8, 0x1c, 0x23, 0xd9, 0xd0, 0x9d,
+       0xb6, 0xcf, 0x6d, 0x49, 0x62, 0xf6, 0x61, 0x8c, 0x27, 0x47, 0x11, 0xaf,
+       0xf6, 0x44, 0x7f, 0xa3, 0x3c, 0x05, 0x81, 0x9f, 0xed, 0xe9, 0xfe, 0x8e,
+       0x38, 0xeb, 0xb6, 0xb0, 0x38, 0x6b, 0x15, 0x8f, 0xd3, 0x55, 0x89, 0xf5,
+       0x35, 0x29, 0xd7, 0x77, 0x24, 0xa1, 0xcb, 0x38, 0xeb, 0x91, 0x84, 0x08,
+       0x71, 0x56, 0x75, 0x3c, 0x7f, 0x1f, 0xc8, 0xf3, 0x9e, 0x21, 0x78, 0xae,
+       0xb4, 0xb0, 0xf5, 0x97, 0xc9, 0x95, 0xa5, 0x7a, 0xe0, 0x0f, 0x0b, 0x09,
+       0xe6, 0x7f, 0xaf, 0x3c, 0xb9, 0xa0, 0xde, 0x48, 0xeb, 0x2b, 0x1f, 0x03,
+       0x4f, 0x1f, 0xf2, 0x21, 0xd4, 0x4f, 0xab, 0x38, 0xbc, 0xba, 0x9a, 0x5f,
+       0x82, 0x4b, 0x43, 0xec, 0x0a, 0xbf, 0x70, 0x37, 0x62, 0x0f, 0xb3, 0x83,
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+       0xa9, 0x8a, 0xef, 0xd3, 0x6b, 0xb3, 0x15, 0xef, 0x67, 0xae, 0xb9, 0x5b,
+       0xd1, 0x9e, 0xe5, 0x29, 0x50, 0xd4, 0x7b, 0x6c, 0x1c, 0xa2, 0x78, 0xbf,
+       0x57, 0x43, 0x89, 0xa2, 0xde, 0x7b, 0xeb, 0xbd, 0x8a, 0xf7, 0xf3, 0x49,
+       0x76, 0x2c, 0xfa, 0x8f, 0x4e, 0xc8, 0xe0, 0x1b, 0x21, 0x77, 0x79, 0x27,
+       0x2b, 0xda, 0xef, 0xd9, 0xfd, 0x80, 0xe2, 0xfb, 0x2f, 0x48, 0xed, 0x53,
+       0xc3, 0xe8, 0x7b, 0x4d, 0x51, 0x8c, 0xff, 0x13, 0x8f, 0xd3, 0xdf, 0x77,
+       0x40, 0x28, 0x5f, 0x38, 0xb7, 0x71, 0xbe, 0xe2, 0xfb, 0x7a, 0xa9, 0x71,
+       0x80, 0x8f, 0xbe, 0xbf, 0xd0, 0xcf, 0xfc, 0xeb, 0xfd, 0x9a, 0x97, 0x29,
+       0xfa, 0xbb, 0x1a, 0x33, 0x9a, 0xd9, 0x0d, 0x3c, 0x4e, 0x58, 0x4b, 0xff,
+       0x31, 0xfe, 0x6d, 0x97, 0x51, 0xff, 0x69, 0x96, 0xc8, 0x36, 0xa9, 0x73,
+       0xdc, 0xb0, 0xa2, 0x65, 0xcb, 0x86, 0xee, 0x24, 0x52, 0xfc, 0x90, 0xc9,
+       0xf5, 0x65, 0x54, 0xae, 0x83, 0xde, 0xa4, 0xd6, 0x2b, 0x0c, 0x89, 0x3c,
+       0x8e, 0x94, 0x4a, 0x52, 0x6f, 0x85, 0xd1, 0x55, 0x08, 0x0f, 0x4c, 0xa8,
+       0x77, 0x5d, 0x7f, 0x4e, 0x46, 0xff, 0x59, 0x3e, 0xc9, 0x79, 0x7a, 0x18,
+       0xc2, 0x47, 0x47, 0xbc, 0xf6, 0xce, 0xfb, 0x75, 0x9d, 0x30, 0xbf, 0xce,
+       0xf5, 0x57, 0xcc, 0x0e, 0xf0, 0x8f, 0x2d, 0x39, 0xb9, 0x00, 0xf1, 0xcf,
+       0x90, 0xac, 0xc4, 0x83, 0x28, 0xbb, 0x12, 0x0f, 0xa2, 0xfb, 0x28, 0xf1,
+       0xc0, 0xec, 0x50, 0xee, 0x7b, 0xec, 0x20, 0xe5, 0xbe, 0xab, 0xe1, 0x6c,
+       0x75, 0x2a, 0xf1, 0x40, 0xc0, 0x51, 0xc0, 0x39, 0x6e, 0xac, 0x12, 0x2f,
+       0x04, 0x7c, 0x07, 0xd1, 0x7f, 0x00, 0xdf, 0x02, 0x12, 0x3c, 0x8e, 0xf9,
+       0xd1, 0x5e, 0xc9, 0xe1, 0x23, 0x11, 0xe2, 0xb2, 0xcd, 0xdb, 0x71, 0x1d,
+       0x77, 0xd2, 0xd3, 0xf2, 0x55, 0xf0, 0xec, 0x7f, 0xd4, 0x59, 0x6f, 0x42,
+       0x38, 0xb1, 0x7c, 0x29, 0xa1, 0x17, 0x19, 0xb8, 0x5e, 0xa2, 0xf6, 0x93,
+       0x77, 0xf8, 0x57, 0x12, 0xb9, 0xde, 0xc3, 0xfb, 0x11, 0x7e, 0xed, 0x0d,
+       0x92, 0x07, 0xf5, 0x9c, 0x8e, 0xf8, 0xd5, 0x20, 0x5f, 0x86, 0x2f, 0x0b,
+       0xf4, 0x9d, 0x5a, 0xc2, 0xfc, 0x23, 0xae, 0xb2, 0xc4, 0xc8, 0x7e, 0x34,
+       0x7c, 0xde, 0x95, 0x1f, 0x4d, 0xc0, 0x51, 0xe8, 0x31, 0xcb, 0x41, 0x8f,
+       0xa1, 0xe3, 0x2c, 0x22, 0x6e, 0xe4, 0x4b, 0x17, 0xb8, 0x1e, 0xb3, 0xc4,
+       0xf4, 0x24, 0xc6, 0x01, 0xaf, 0xfe, 0x81, 0xc1, 0xb7, 0x82, 0x78, 0x91,
+       0x5f, 0x7f, 0xe3, 0xb8, 0x36, 0xd5, 0x0b, 0x49, 0x98, 0x7f, 0x51, 0x0d,
+       0x47, 0xa9, 0x45, 0xf2, 0x99, 0x81, 0x0e, 0x38, 0xdf, 0x4e, 0x25, 0x2d,
+       0x82, 0x6f, 0xbb, 0x31, 0xdf, 0x81, 0xa2, 0x9d, 0x71, 0x80, 0x22, 0x9e,
+       0xa0, 0xd4, 0x3b, 0x89, 0x53, 0x0a, 0xe7, 0x4f, 0x42, 0x0f, 0x15, 0xe3,
+       0x09, 0x78, 0x0a, 0xbe, 0x25, 0xc6, 0x33, 0x90, 0x5a, 0x39, 0x19, 0xe8,
+       0x40, 0xc5, 0xc7, 0x48, 0x1f, 0x75, 0x3c, 0x43, 0xe9, 0xe7, 0x10, 0x7e,
+       0x11, 0x1c, 0x2c, 0x2c, 0x6e, 0x31, 0xb0, 0x23, 0x1e, 0xc1, 0xec, 0xc2,
+       0x90, 0x9f, 0x8b, 0xf9, 0x35, 0xe4, 0xcc, 0xac, 0x7a, 0x02, 0xfa, 0xb6,
+       0x45, 0xf8, 0x31, 0xfc, 0x33, 0xe1, 0xb9, 0xf0, 0x63, 0xa8, 0xed, 0xf9,
+       0x3b, 0xc5, 0x41, 0xef, 0xf7, 0x48, 0x81, 0x67, 0xb3, 0x3a, 0xc7, 0x3f,
+       0x45, 0x3c, 0x95, 0x2e, 0xf3, 0xb3, 0x3f, 0xd2, 0x8f, 0x87, 0x49, 0xf6,
+       0x74, 0x18, 0x6f, 0xf2, 0x1b, 0xbd, 0x13, 0x88, 0x26, 0x92, 0x1f, 0xce,
+       0x71, 0xf6, 0x00, 0xed, 0x47, 0xd6, 0x04, 0xe3, 0xc2, 0xfd, 0x63, 0xc2,
+       0x5f, 0xfd, 0xb6, 0x14, 0xc0, 0x79, 0x7f, 0x87, 0x38, 0x1f, 0x21, 0x61,
+       0xfa, 0x42, 0x35, 0x69, 0x1c, 0x3d, 0x33, 0x0b, 0xfc, 0x9d, 0x54, 0x6e,
+       0xc5, 0x40, 0xc9, 0xfc, 0x3c, 0xa4, 0x59, 0xad, 0x8f, 0xb2, 0xf8, 0xa1,
+       0x86, 0xae, 0x04, 0xf0, 0x7b, 0x39, 0x09, 0x8b, 0x0f, 0x66, 0x85, 0xda,
+       0xb1, 0x2e, 0x77, 0xae, 0x8b, 0xfc, 0x94, 0x3b, 0xc9, 0xf7, 0x5e, 0x49,
+       0x16, 0x71, 0x2e, 0x25, 0x87, 0xb5, 0x33, 0xfe, 0x26, 0xec, 0xb5, 0xae,
+       0xec, 0x23, 0x11, 0xbf, 0x3f, 0xa6, 0xa7, 0x30, 0x29, 0x08, 0xe5, 0xa3,
+       0x34, 0x26, 0x72, 0x3f, 0x56, 0x1e, 0xc9, 0x83, 0xfe, 0x29, 0x5d, 0x35,
+       0x25, 0x26, 0x80, 0x3d, 0x4e, 0xe9, 0x50, 0x0a, 0xa7, 0xbb, 0x8e, 0xfc,
+       0x15, 0x6c, 0xef, 0x44, 0x77, 0xaa, 0xf5, 0x8b, 0xf8, 0xbd, 0x6c, 0x2e,
+       0x44, 0x3f, 0xcb, 0x82, 0xf0, 0xf5, 0x7e, 0x0d, 0x78, 0x08, 0x3d, 0xe2,
+       0x06, 0x5d, 0x1b, 0xac, 0xf7, 0x47, 0x89, 0x76, 0x2c, 0xab, 0xba, 0x9d,
+       0xfb, 0xd0, 0x09, 0xcd, 0x85, 0x7e, 0x45, 0x1e, 0x62, 0x8d, 0x9e, 0xe5,
+       0xfd, 0x92, 0x46, 0xa5, 0xfe, 0x7c, 0x36, 0x51, 0xc4, 0x59, 0x99, 0x9d,
+       0x71, 0x27, 0x38, 0x75, 0xbd, 0x0f, 0x3c, 0x9f, 0x8b, 0xef, 0xc3, 0xd7,
+       0xd5, 0x87, 0x44, 0x3e, 0x97, 0x80, 0xdf, 0x27, 0x82, 0x0f, 0x86, 0xe0,
+       0x7d, 0x5e, 0x01, 0xcf, 0x0e, 0x7b, 0xad, 0x03, 0xde, 0xe7, 0x23, 0xc1,
+       0x5b, 0xc0, 0xe3, 0x5a, 0x91, 0xff, 0x45, 0xd8, 0x27, 0xd9, 0x7c, 0x3a,
+       0x11, 0xe0, 0x9c, 0x14, 0xe3, 0xfa, 0x02, 0xf8, 0x62, 0xfa, 0xd9, 0xc0,
+       0x45, 0x49, 0x13, 0x9a, 0x57, 0x99, 0xdc, 0x8a, 0x79, 0x9c, 0xd7, 0x9b,
+       0x65, 0xb4, 0x8f, 0xaa, 0x87, 0xb3, 0x7c, 0x9e, 0xea, 0xfd, 0x18, 0x24,
+       0x27, 0x6d, 0x2d, 0x06, 0x8c, 0x03, 0x56, 0x34, 0x1f, 0x41, 0xfd, 0xac,
+       0xb5, 0x8e, 0x32, 0xd2, 0x9e, 0x5d, 0xc3, 0xa9, 0x63, 0xbd, 0x2a, 0x78,
+       0x77, 0x65, 0xaf, 0x88, 0xf5, 0xdc, 0x52, 0xad, 0x5f, 0xe4, 0x87, 0x40,
+       0x7c, 0x3f, 0xa9, 0xe8, 0xb6, 0x70, 0x50, 0xb6, 0x73, 0x38, 0x88, 0x7c,
+       0x96, 0x32, 0xb9, 0x6f, 0x6c, 0x20, 0xcc, 0x2e, 0xf1, 0xf1, 0x7d, 0x8f,
+       0xd2, 0xba, 0xa2, 0x92, 0xe8, 0xf8, 0x85, 0xbf, 0x4b, 0x8b, 0x01, 0xf8,
+       0x94, 0xc9, 0x2d, 0xc7, 0x53, 0x01, 0x0e, 0xab, 0x25, 0x3c, 0x67, 0x34,
+       0xd2, 0x40, 0x3c, 0xe0, 0xdf, 0x4f, 0xe1, 0xe7, 0xcd, 0x06, 0x05, 0x6a,
+       0x1d, 0x16, 0x0a, 0x8f, 0xe4, 0x34, 0x13, 0x9e, 0x1b, 0xea, 0xfd, 0x5d,
+       0xd9, 0x05, 0xf1, 0xcb, 0x8f, 0x57, 0xaf, 0xb2, 0xc1, 0xb9, 0xa8, 0x2b,
+       0x75, 0x74, 0x68, 0x6a, 0x77, 0xf4, 0x96, 0x34, 0x2e, 0xc4, 0x37, 0xb2,
+       0xf7, 0x93, 0x1f, 0x14, 0x42, 0x5c, 0x6d, 0x16, 0xe6, 0x17, 0xcf, 0x36,
+       0xb0, 0x78, 0x7f, 0xd6, 0xf7, 0xa2, 0x7d, 0x3d, 0x28, 0x9f, 0x78, 0x53,
+       0x4f, 0x8c, 0x40, 0x6f, 0xba, 0xec, 0x5a, 0x3c, 0x57, 0x11, 0xb4, 0xca,
+       0x68, 0x6f, 0xc4, 0xcb, 0x64, 0x14, 0xe0, 0x97, 0x80, 0x73, 0x7c, 0x34,
+       0x5b, 0x87, 0x78, 0x5e, 0xfc, 0xf3, 0x9d, 0x12, 0xe4, 0x21, 0x89, 0xe7,
+       0x23, 0xeb, 0x83, 0xfd, 0x57, 0xd2, 0xf2, 0x73, 0xd8, 0xf7, 0x84, 0xd0,
+       0x3a, 0x47, 0x96, 0x06, 0xfb, 0xd7, 0x9a, 0x42, 0x70, 0x16, 0xf9, 0x7d,
+       0x44, 0x1b, 0xcc, 0x98, 0x1c, 0x46, 0x1f, 0x47, 0x38, 0x3c, 0xaa, 0x13,
+       0xf4, 0x1b, 0x40, 0x1e, 0xb6, 0x19, 0xb9, 0x1d, 0xc8, 0xed, 0x41, 0x62,
+       0xd1, 0x22, 0x1f, 0x59, 0xcd, 0xe3, 0xeb, 0xe7, 0x7a, 0x11, 0xe2, 0xc7,
+       0x7e, 0x7c, 0x66, 0xc8, 0xa7, 0xaa, 0x8e, 0x72, 0xc6, 0x0e, 0x04, 0xff,
+       0x16, 0xe4, 0x0f, 0xd0, 0xe2, 0x2f, 0x16, 0x67, 0xac, 0x15, 0xd7, 0x6f,
+       0x47, 0xbd, 0x79, 0x35, 0xd7, 0xaf, 0xda, 0x78, 0x7e, 0xf6, 0xea, 0x71,
+       0x25, 0x49, 0x60, 0x4f, 0x25, 0xd4, 0x47, 0xce, 0x63, 0x1a, 0x9d, 0xc4,
+       0xf4, 0xfc, 0x4a, 0x1e, 0xf7, 0x16, 0xcf, 0x2b, 0xb5, 0x3e, 0xcc, 0x47,
+       0xaa, 0x84, 0x7c, 0xe1, 0xb0, 0xfc, 0xa8, 0x6f, 0x9a, 0x2f, 0x2c, 0xf2,
+       0xc4, 0xbb, 0x84, 0x83, 0x55, 0x4b, 0xb4, 0x14, 0x0e, 0xd5, 0x12, 0x71,
+       0xdd, 0xee, 0xbd, 0x03, 0xff, 0x23, 0x47, 0xb4, 0x77, 0xab, 0x92, 0x34,
+       0xb7, 0xcd, 0x63, 0x5b, 0xc8, 0xd7, 0x27, 0xf2, 0xd3, 0xaa, 0x21, 0x3f,
+       0x8d, 0x3e, 0x5a, 0xbd, 0xbf, 0x38, 0x89, 0x44, 0xe8, 0xaf, 0x43, 0xde,
+       0xdc, 0x18, 0xa2, 0xc8, 0x0b, 0x13, 0xf9, 0xcd, 0xd5, 0x37, 0x46, 0x60,
+       0x5e, 0x58, 0xe9, 0xa3, 0xad, 0x78, 0xbe, 0x0f, 0xfa, 0xb1, 0x9b, 0x42,
+       0x79, 0x69, 0x5d, 0xc1, 0xf9, 0x48, 0x22, 0x9b, 0x47, 0x35, 0xe4, 0x8b,
+       0xf5, 0x0f, 0x7f, 0xce, 0xf8, 0x47, 0xa8, 0xff, 0x78, 0xdc, 0x87, 0x5f,
+       0x02, 0x00, 0xc1, 0xcf, 0xd1, 0x2c, 0xa3, 0x1f, 0xf6, 0x97, 0x27, 0x34,
+       0x63, 0x77, 0x44, 0x98, 0xef, 0x16, 0xbe, 0xfe, 0xbb, 0x13, 0xb4, 0x48,
+       0x1f, 0xf7, 0xf8, 0x88, 0x73, 0x7b, 0x84, 0xf1, 0xc5, 0x7b, 0xe2, 0xfc,
+       0x07, 0xc0, 0xb9, 0x3c, 0xb7, 0xf3, 0xfc, 0x9a, 0x4a, 0x02, 0x73, 0x60,
+       0xfe, 0x90, 0x77, 0x1a, 0x69, 0xbc, 0xf5, 0x49, 0xcc, 0xce, 0x16, 0xf3,
+       0x6e, 0xb2, 0x05, 0x16, 0x73, 0x3c, 0xc7, 0xf3, 0x17, 0x1d, 0x75, 0x8b,
+       0x72, 0x1f, 0x5f, 0xe0, 0xfb, 0xd8, 0x74, 0x6f, 0x20, 0x03, 0xcf, 0x11,
+       0x8d, 0x8b, 0x9c, 0x07, 0x2f, 0xf6, 0xfb, 0xa6, 0xd9, 0xfd, 0x26, 0xf0,
+       0xdb, 0xca, 0x69, 0xf4, 0x65, 0xf0, 0xb3, 0x6b, 0x6b, 0x25, 0x4b, 0x18,
+       0x7d, 0x75, 0xb5, 0xdf, 0x21, 0x38, 0x6b, 0x14, 0xf9, 0x7f, 0x9d, 0xe1,
+       0xac, 0xc7, 0xfd, 0x15, 0xfd, 0x09, 0x7b, 0xe4, 0xf2, 0x56, 0x19, 0xe3,
+       0xfb, 0x97, 0x4f, 0x71, 0x7a, 0x24, 0x4e, 0x93, 0x44, 0xe9, 0x6a, 0x1e,
+       0x97, 0x57, 0x97, 0x09, 0x8b, 0x13, 0x5c, 0x6e, 0x90, 0xd0, 0x0e, 0x99,
+       0xef, 0x26, 0x64, 0x0d, 0xe5, 0x2b, 0xf3, 0x76, 0x2e, 0xc7, 0x38, 0xcd,
+       0xe2, 0x5d, 0xfd, 0x37, 0x80, 0x98, 0x82, 0xe7, 0x6b, 0x29, 0xff, 0x98,
+       0x97, 0x4c, 0xc8, 0x08, 0x5a, 0xce, 0x5f, 0xaf, 0x8c, 0xd3, 0x2e, 0xdc,
+       0xdc, 0xc9, 0xff, 0x46, 0xc2, 0xe5, 0x22, 0x55, 0x3b, 0xd1, 0xae, 0x5e,
+       0xfc, 0xa4, 0xf2, 0xbb, 0x0a, 0xb2, 0xf9, 0xcf, 0xa0, 0xf7, 0x54, 0xa8,
+       0xf4, 0x9a, 0xde, 0xdc, 0xbf, 0xb5, 0x2f, 0x89, 0xda, 0x09, 0xa0, 0xd7,
+       0x0d, 0x20, 0x03, 0x80, 0xaf, 0xaf, 0xdc, 0xf5, 0xa5, 0x1e, 0x52, 0x6d,
+       0xbb, 0xc2, 0xf3, 0x2b, 0x94, 0x9e, 0x7b, 0x6a, 0x81, 0xff, 0x59, 0xb0,
+       0x3c, 0x91, 0xe4, 0x3c, 0x08, 0xfc, 0xfd, 0xf7, 0x49, 0x6e, 0x1f, 0x94,
+       0xed, 0x1f, 0x30, 0x38, 0x5c, 0xaf, 0xbc, 0xce, 0xf8, 0xfd, 0x73, 0xf1,
+       0x28, 0x67, 0x0c, 0xc0, 0x94, 0xe9, 0xff, 0x1a, 0x66, 0xb2, 0x78, 0xeb,
+       0xa3, 0x94, 0x4d, 0x40, 0x9c, 0xcd, 0x60, 0x60, 0x7a, 0x8d, 0xd0, 0xe7,
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+       0xbf, 0xf8, 0x97, 0xc7, 0x8c, 0x05, 0x7d, 0x3f, 0xe1, 0xe5, 0x68, 0x27,
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+       0xaa, 0x7d, 0x5a, 0xa1, 0xa8, 0x97, 0x59, 0x1e, 0x54, 0xbc, 0x3f, 0x26,
+       0x79, 0x9d, 0xa2, 0x7d, 0x9c, 0xfd, 0x31, 0xd5, 0x3e, 0x6d, 0x51, 0xd4,
+       0x27, 0x3a, 0x9e, 0x51, 0xed, 0xd3, 0x76, 0xd5, 0x3e, 0xbd, 0xa4, 0x68,
+       0x1f, 0x7e, 0x21, 0x50, 0x0f, 0x64, 0x34, 0xb2, 0xd5, 0x23, 0x9b, 0xe9,
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+       0xe8, 0xa5, 0xd0, 0xe7, 0xae, 0x07, 0x76, 0x58, 0x74, 0xb4, 0xf6, 0x08,
+       0x94, 0x3e, 0x6a, 0x4f, 0x81, 0x7f, 0xea, 0xad, 0xba, 0x64, 0x2c, 0x8f,
+       0xd6, 0xd9, 0xd1, 0xbf, 0x74, 0xbc, 0xae, 0x0f, 0x96, 0x27, 0xea, 0x1c,
+       0xf8, 0xfc, 0xb7, 0x75, 0x83, 0xb0, 0x7c, 0xb7, 0xce, 0x89, 0xe5, 0x7f,
+       0xd6, 0x8d, 0xc5, 0xd2, 0x5f, 0xe7, 0xc2, 0xb2, 0xb1, 0xae, 0x11, 0xdf,
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+       0xfa, 0xfd, 0x67, 0x0e, 0x22, 0x5f, 0x6c, 0xeb, 0x16, 0x68, 0x83, 0xfa,
+       0xc3, 0xa4, 0x65, 0xc2, 0x28, 0x5a, 0x9f, 0x0f, 0xc6, 0x14, 0xe8, 0x57,
+       0x50, 0xd2, 0xfd, 0xf4, 0xa4, 0x3a, 0xff, 0x2b, 0x05, 0xf2, 0x29, 0x52,
+       0xd8, 0x73, 0x91, 0x97, 0xd0, 0xa8, 0x71, 0xe6, 0x83, 0x7e, 0xfd, 0xf8,
+       0x33, 0xc7, 0x36, 0x6b, 0xd3, 0x09, 0x79, 0x64, 0x9d, 0x2b, 0xd9, 0x62,
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+       0x69, 0x84, 0xfc, 0x0a, 0x44, 0xc6, 0x10, 0xac, 0x4f, 0x80, 0x7a, 0x7b,
+       0x14, 0x6b, 0xdf, 0xf0, 0xcc, 0xb1, 0x09, 0x1e, 0x9c, 0x1f, 0x8b, 0x1f,
+       0x4f, 0x09, 0xc5, 0x8f, 0x1f, 0x4f, 0x89, 0x10, 0x3f, 0xfe, 0xd5, 0x25,
+       0xbb, 0x19, 0xfc, 0x28, 0xa7, 0x6e, 0xf6, 0x36, 0xc3, 0xba, 0x4e, 0x71,
+       0xbf, 0x91, 0x93, 0xe4, 0xeb, 0xe6, 0xd1, 0xb2, 0x58, 0x9b, 0xaf, 0x03,
+       0xb9, 0x78, 0x56, 0xa5, 0x47, 0x88, 0xb2, 0x46, 0x53, 0xfc, 0x24, 0xe0,
+       0x69, 0xa3, 0xc6, 0x31, 0x15, 0xf3, 0x80, 0xef, 0xd5, 0x11, 0xc8, 0x3b,
+       0x9f, 0x2c, 0x31, 0x7b, 0xb4, 0x43, 0x0f, 0x4c, 0x65, 0xf2, 0xa8, 0x7d,
+       0xa2, 0x01, 0xed, 0x9d, 0xd3, 0x1a, 0xe7, 0x22, 0xcc, 0x6f, 0x92, 0x82,
+       0xcf, 0x03, 0xbc, 0x5e, 0x49, 0xf9, 0x10, 0xe1, 0xd7, 0x6e, 0x0e, 0x66,
+       0x00, 0x1c, 0x7e, 0x99, 0x72, 0x86, 0xd5, 0x13, 0x82, 0xcf, 0x4b, 0x8e,
+       0xb0, 0xba, 0x8e, 0xad, 0xf3, 0x85, 0x94, 0xd3, 0x5d, 0xad, 0x73, 0x37,
+       0xcc, 0xa7, 0xd3, 0x3a, 0x53, 0xd8, 0x7d, 0x31, 0xc4, 0xe7, 0x4c, 0x07,
+       0xf9, 0x2b, 0xea, 0xa7, 0xcb, 0x9d, 0x55, 0x20, 0x27, 0x4e, 0x17, 0x3b,
+       0x7b, 0xc1, 0x7c, 0x4e, 0xb9, 0x0c, 0x48, 0x3f, 0x1e, 0x97, 0xd9, 0x0b,
+       0xf9, 0x95, 0x44, 0xeb, 0x2c, 0x9a, 0x1a, 0xe6, 0x4f, 0xe9, 0x9d, 0xaa,
+       0xc3, 0xef, 0xa6, 0xe8, 0x19, 0x9d, 0x91, 0x07, 0xe4, 0x88, 0xe7, 0xc4,
+       0xcb, 0x52, 0x99, 0x9e, 0x85, 0xfb, 0x06, 0xf6, 0xdc, 0x8c, 0x68, 0xd4,
+       0xc3, 0x4f, 0x6b, 0x22, 0x9f, 0xf3, 0x9e, 0xcd, 0xe1, 0x73, 0xb5, 0x5b,
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+       0x1d, 0x85, 0xf1, 0xdb, 0x76, 0x57, 0x6f, 0xd4, 0x83, 0xda, 0x6b, 0x29,
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+       0x4d, 0x92, 0x7d, 0x89, 0x79, 0x52, 0x67, 0x3b, 0xb3, 0xf5, 0xe4, 0xac,
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+       0x0e, 0xde, 0x57, 0x79, 0xbf, 0xc2, 0xa0, 0x77, 0x98, 0xbd, 0xca, 0xcb,
+       0x4e, 0xf7, 0xb0, 0x2d, 0xf3, 0x28, 0xf3, 0xd4, 0x8a, 0x7d, 0x45, 0x98,
+       0x3f, 0x21, 0x07, 0x62, 0xa0, 0xbc, 0x26, 0x05, 0xd0, 0xef, 0x25, 0x6b,
+       0xd8, 0xbd, 0x0b, 0xe2, 0xbe, 0x05, 0x6a, 0xc7, 0xa6, 0x76, 0x4f, 0x00,
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+       0x7c, 0x34, 0xe7, 0x21, 0xa4, 0xfb, 0x28, 0xd4, 0x7f, 0x3a, 0xec, 0xd8,
+       0xd7, 0x35, 0x98, 0x1f, 0xd0, 0xa4, 0x75, 0xc6, 0x0e, 0x07, 0x3b, 0x76,
+       0x4d, 0x2f, 0xc7, 0x3a, 0x5a, 0xff, 0x93, 0x3f, 0xe1, 0x67, 0x07, 0x68,
+       0x59, 0x63, 0xf9, 0x8a, 0x84, 0xdf, 0xcf, 0x56, 0xb9, 0xe6, 0xba, 0xa2,
+       0xde, 0xba, 0x2e, 0x74, 0xbf, 0x0f, 0xe4, 0x41, 0x57, 0xfe, 0x8f, 0x8c,
+       0x72, 0xa7, 0x92, 0x90, 0x8d, 0xb0, 0x5f, 0x95, 0xe4, 0x2d, 0xfd, 0xca,
+       0x30, 0x39, 0x48, 0x1a, 0xff, 0xdc, 0x01, 0xf7, 0x7e, 0x94, 0xcf, 0x95,
+       0x03, 0xe0, 0xd0, 0xae, 0xd2, 0x4e, 0x72, 0xd2, 0xf7, 0xca, 0xb9, 0xbd,
+       0x41, 0x3c, 0x8f, 0xb0, 0x3a, 0xb7, 0xb3, 0x08, 0xf9, 0x7c, 0xa2, 0x93,
+       0xf6, 0x5b, 0x9e, 0xc0, 0xdf, 0x27, 0x33, 0x58, 0x7b, 0xba, 0x68, 0x7f,
+       0x80, 0xd5, 0x7b, 0x89, 0xfe, 0xf6, 0x4f, 0xc4, 0x7a, 0x8a, 0xa8, 0xf3,
+       0xfe, 0xee, 0x12, 0xf5, 0x2d, 0xac, 0x9e, 0x25, 0xbe, 0xdf, 0xcb, 0xea,
+       0xb9, 0x62, 0xfc, 0xf7, 0xd9, 0x78, 0x66, 0xf6, 0x7e, 0x69, 0xf7, 0xef,
+       0x4d, 0x02, 0xfd, 0x43, 0xf0, 0xf7, 0x71, 0xdd, 0x95, 0xf7, 0xf2, 0x50,
+       0x7e, 0x3f, 0xb1, 0xfb, 0xed, 0xf3, 0x49, 0x94, 0xed, 0x5c, 0x1e, 0x88,
+       0x7b, 0x78, 0xca, 0x7e, 0x30, 0x2e, 0xfa, 0x3d, 0xa0, 0xe7, 0x46, 0x09,
+       0x73, 0xdf, 0x2a, 0xd7, 0xea, 0xd0, 0xbf, 0x7d, 0xd5, 0xd6, 0x98, 0x17,
+       0x7e, 0x1e, 0x59, 0xe4, 0x9f, 0xb8, 0x4a, 0xcd, 0x4e, 0xd0, 0xf7, 0xaa,
+       0xf6, 0xf5, 0xde, 0x21, 0xf3, 0x7c, 0x1c, 0xd0, 0x37, 0x7e, 0xc4, 0xe3,
+       0xca, 0x65, 0xb2, 0x09, 0xe3, 0x11, 0xd7, 0x37, 0x33, 0x3e, 0xdf, 0x95,
+       0xbe, 0xb6, 0x78, 0xcd, 0x1b, 0x8a, 0xfd, 0xec, 0xd4, 0xce, 0xef, 0x49,
+       0xc6, 0x40, 0x1d, 0x1d, 0xef, 0xda, 0x13, 0x49, 0x98, 0xdf, 0x4e, 0x7a,
+       0xfa, 0x31, 0x0e, 0xbe, 0xbc, 0xbb, 0x24, 0xe2, 0xed, 0x78, 0x9e, 0x55,
+       0xe4, 0x7b, 0xc5, 0xf7, 0x20, 0x4e, 0xb0, 0x4f, 0xe3, 0x7f, 0x13, 0xc5,
+       0xee, 0xa1, 0xbc, 0xe0, 0x47, 0xfe, 0xbb, 0xf8, 0x37, 0xcc, 0xdf, 0x5b,
+       0xf5, 0xcc, 0x11, 0x94, 0x73, 0xf3, 0x65, 0x3b, 0xe2, 0xf1, 0xf1, 0x2c,
+       0xf7, 0x0a, 0x80, 0x4f, 0x9b, 0x99, 0xdd, 0x37, 0xb8, 0x78, 0xcd, 0x21,
+       0xa4, 0xd7, 0xb5, 0x99, 0x5c, 0x4f, 0xb0, 0x04, 0xfb, 0x86, 0xc3, 0xf3,
+       0xc1, 0xce, 0xf0, 0xff, 0xe1, 0x1d, 0xe0, 0xff, 0xc3, 0x7f, 0x27, 0xfc,
+       0xd5, 0x7e, 0x66, 0x71, 0x1e, 0x7a, 0xd9, 0x37, 0xcc, 0x4b, 0x6b, 0x33,
+       0xb3, 0x38, 0xa8, 0x83, 0xef, 0xd3, 0x79, 0x8d, 0x7d, 0x00, 0x87, 0xd7,
+       0xd3, 0x40, 0xe7, 0xd7, 0x16, 0xf9, 0x73, 0xac, 0x32, 0x24, 0x0d, 0xfb,
+       0x13, 0x59, 0xbe, 0xd1, 0xbb, 0x45, 0x60, 0x07, 0x5d, 0xaf, 0x35, 0xe3,
+       0xfd, 0x44, 0xb3, 0x56, 0x7d, 0x9c, 0x17, 0x7e, 0x1e, 0x45, 0x94, 0x6a,
+       0xfd, 0xff, 0x73, 0xa0, 0xa3, 0x84, 0x10, 0xbc, 0x76, 0x75, 0xe7, 0xfa,
+       0x5e, 0x08, 0xbe, 0x2f, 0xdd, 0x01, 0xbe, 0x2f, 0xfd, 0x3b, 0xe1, 0x9b,
+       0xa4, 0x0d, 0xe8, 0x1d, 0x10, 0x37, 0x3d, 0xcb, 0xee, 0x0b, 0x1b, 0xe0,
+       0x3f, 0xaf, 0x0f, 0xcf, 0x73, 0x39, 0xd9, 0x9d, 0xc9, 0xdd, 0xd8, 0x66,
+       0x16, 0x27, 0x52, 0xe7, 0x6b, 0x9d, 0xec, 0x6e, 0x66, 0x78, 0xc5, 0xe3,
+       0x31, 0x55, 0x93, 0xdf, 0x1d, 0x06, 0xf1, 0x18, 0x41, 0x0f, 0x23, 0xa3,
+       0x49, 0x23, 0xf8, 0xd7, 0x29, 0x5e, 0x3b, 0x38, 0x5e, 0x3b, 0x00, 0xaf,
+       0x05, 0xfe, 0x86, 0xe2, 0x32, 0xf4, 0xbb, 0x08, 0xf4, 0x15, 0xc2, 0x5f,
+       0xc2, 0xec, 0x62, 0x0e, 0x27, 0x7f, 0x67, 0xbc, 0x3d, 0x7d, 0x07, 0xb8,
+       0x9e, 0xfe, 0x77, 0xc2, 0xb5, 0x89, 0xea, 0xbf, 0x18, 0xc7, 0x7c, 0x3d,
+       0x0a, 0xfd, 0x27, 0x6a, 0x38, 0xff, 0x8d, 0xd3, 0xbb, 0x80, 0xb7, 0x31,
+       0xed, 0xf6, 0x70, 0x36, 0xa6, 0xfd, 0x6b, 0xe0, 0x6c, 0x4c, 0xb3, 0x2b,
+       0xf2, 0xd2, 0x04, 0xbc, 0xbb, 0x92, 0x4f, 0xea, 0xfd, 0x11, 0xf3, 0x8e,
+       0x40, 0xa7, 0x45, 0xdf, 0x86, 0x4e, 0x1f, 0x4d, 0xe7, 0x7c, 0x4a, 0x1b,
+       0xc0, 0x3c, 0x51, 0xf5, 0xbe, 0xc7, 0xa6, 0x75, 0xda, 0xf7, 0xb8, 0xb4,
+       0xdb, 0xef, 0xbb, 0xb2, 0xfd, 0x5f, 0xbc, 0xef, 0x6a, 0xb8, 0xa9, 0xcb,
+       0x4a, 0x1e, 0xdf, 0x54, 0x3f, 0xcf, 0x4f, 0xd3, 0xfc, 0x4b, 0xe1, 0xf8,
+       0xff, 0x9b, 0xff, 0x7c, 0x76, 0xed, 0x61, 0x45, 0xfb, 0xdc, 0x35, 0x27,
+       0x15, 0xed, 0xf3, 0x3c, 0x1f, 0x28, 0xea, 0xc3, 0x02, 0xfe, 0x52, 0x40,
+       0x73, 0xe1, 0x0f, 0x1f, 0x71, 0x29, 0x88, 0xfa, 0xe5, 0xb7, 0xf5, 0xab,
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+       0x99, 0x3f, 0xbf, 0x2d, 0xdd, 0xbd, 0x01, 0xf0, 0xeb, 0x7d, 0x8d, 0xb7,
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+       0x2f, 0x8f, 0xbf, 0xa3, 0xf2, 0xc5, 0xe0, 0x07, 0x31, 0x7e, 0x28, 0xbe,
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+       0xe8, 0x05, 0x1f, 0x51, 0xb1, 0x0a, 0xe7, 0x4a, 0xfe, 0x58, 0x67, 0xc4,
+       0xf2, 0x63, 0x6a, 0xe7, 0x42, 0xf9, 0x27, 0x6a, 0xe7, 0x42, 0xf9, 0x29,
+       0xb5, 0x73, 0xa1, 0xfc, 0x8c, 0xda, 0xb9, 0x50, 0x2e, 0xba, 0xe1, 0x20,
+       0x84, 0xf2, 0x8f, 0xf7, 0x32, 0x9c, 0xa3, 0x32, 0x8a, 0x42, 0xf1, 0x36,
+       0xf5, 0x7c, 0x87, 0x73, 0x78, 0x76, 0x8c, 0x7f, 0x50, 0x8f, 0xe3, 0x57,
+       0x65, 0xba, 0x11, 0xbe, 0x1d, 0xfb, 0xbd, 0x9f, 0x78, 0x21, 0x1e, 0xf2,
+       0xaa, 0x35, 0x98, 0x6a, 0xbb, 0x0d, 0xbe, 0x75, 0xcd, 0x67, 0x3c, 0xdc,
+       0xde, 0x8b, 0x9c, 0x9f, 0xd5, 0x9f, 0xef, 0x7b, 0x5e, 0x93, 0x16, 0xe5,
+       0x78, 0x5e, 0x73, 0x20, 0x66, 0x71, 0xd8, 0x7b, 0x93, 0x33, 0xf4, 0xd8,
+       0x9e, 0xfb, 0xfa, 0x05, 0x3c, 0x1f, 0xda, 0x66, 0xe9, 0x80, 0xaf, 0x53,
+       0xa2, 0x4b, 0x9e, 0xa4, 0x61, 0xf5, 0xc9, 0xcf, 0xf7, 0x41, 0xf8, 0x56,
+       0x65, 0x3a, 0x97, 0xc2, 0x3e, 0x52, 0xfa, 0xfe, 0x0e, 0x94, 0x79, 0xcd,
+       0xbf, 0xfb, 0x09, 0x9c, 0xe7, 0xa1, 0xfd, 0x63, 0x1e, 0x41, 0xbb, 0x14,
+       0x7c, 0x0a, 0xf5, 0x7c, 0xd5, 0x3a, 0xd4, 0x70, 0x10, 0xeb, 0x7a, 0xd5,
+       0xea, 0xdf, 0x04, 0xdf, 0xbf, 0xfa, 0x7a, 0x36, 0xac, 0x84, 0xf2, 0x1b,
+       0xc2, 0xe8, 0x06, 0xf0, 0x48, 0x8a, 0xb4, 0xde, 0x75, 0x08, 0xd7, 0xfb,
+       0x0c, 0xc1, 0x42, 0x38, 0xa7, 0x72, 0xdf, 0x2d, 0x39, 0x62, 0xde, 0x70,
+       0x55, 0x66, 0x31, 0xc2, 0x59, 0x27, 0xf0, 0x4d, 0xc0, 0x89, 0xef, 0xd7,
+       0xb7, 0xa5, 0xeb, 0x8e, 0x78, 0x36, 0xc7, 0x53, 0x22, 0xee, 0xd7, 0x00,
+       0xde, 0x69, 0x07, 0x39, 0x74, 0x33, 0x06, 0xf4, 0xba, 0x72, 0x1e, 0xaf,
+       0x6f, 0x6e, 0xea, 0xf9, 0x3e, 0xac, 0xcf, 0x73, 0x42, 0x26, 0xbd, 0xec,
+       0x88, 0xbf, 0x0a, 0xba, 0x7b, 0x8e, 0xef, 0x8f, 0x28, 0x73, 0x0f, 0xea,
+       0x5d, 0xb0, 0x4f, 0xaf, 0x1e, 0xbc, 0xd8, 0x13, 0xee, 0x5b, 0xa5, 0xfb,
+       0xd2, 0x13, 0xee, 0x5f, 0xdd, 0x9c, 0xd1, 0x4b, 0x91, 0xdf, 0x94, 0x3b,
+       0xf8, 0xef, 0xdb, 0x7e, 0x1a, 0x8f, 0xef, 0xe3, 0xef, 0x7c, 0xce, 0x20,
+       0xdb, 0xcb, 0x20, 0x9f, 0x64, 0xa6, 0xf1, 0xf0, 0x31, 0x58, 0xd2, 0x6c,
+       0xcb, 0xa7, 0x65, 0x90, 0x4f, 0x32, 0x37, 0x59, 0x3a, 0x0e, 0xe5, 0x3c,
+       0x7b, 0xd6, 0x68, 0xc8, 0x23, 0x11, 0xf9, 0xee, 0x0b, 0xfa, 0x14, 0x1f,
+       0x07, 0x52, 0x9a, 0xe0, 0x28, 0x47, 0x7d, 0xac, 0x18, 0x98, 0x4b, 0x98,
+       0x3c, 0x28, 0x35, 0x46, 0xf3, 0xcb, 0x9f, 0x85, 0xfc, 0x89, 0x53, 0xd4,
+       0xc7, 0x24, 0x77, 0x57, 0xbc, 0x3f, 0xce, 0xde, 0x43, 0xd1, 0x3e, 0xbe,
+       0xcf, 0x3d, 0x8a, 0x76, 0x31, 0xee, 0x04, 0x47, 0x7f, 0xc5, 0x7b, 0xfd,
+       0x6c, 0xc1, 0x6c, 0xb0, 0xbf, 0xe8, 0x3a, 0xd8, 0x7d, 0xd7, 0xbb, 0x64,
+       0xcc, 0xbb, 0xcb, 0x7d, 0xfd, 0xf4, 0xbd, 0xf7, 0xd0, 0xfa, 0xa4, 0x17,
+       0xa7, 0xe2, 0xfd, 0x7e, 0xaf, 0xf2, 0xf6, 0x49, 0x7b, 0x4b, 0xf1, 0xf7,
+       0x03, 0xdb, 0x29, 0x3c, 0xf5, 0x54, 0x91, 0xba, 0x34, 0xe8, 0xb1, 0xa7,
+       0x7e, 0x0a, 0x9d, 0xa9, 0xf4, 0xfb, 0xca, 0x83, 0x2f, 0x1c, 0x77, 0xda,
+       0x6f, 0xa3, 0xdf, 0xdf, 0x41, 0xaf, 0x17, 0xfc, 0x75, 0x79, 0x8b, 0xb1,
+       0x08, 0xf8, 0xeb, 0xd7, 0xd5, 0xf3, 0xd5, 0xfb, 0xb2, 0x3f, 0x83, 0x9f,
+       0x0b, 0xe4, 0x7a, 0x7f, 0x57, 0xf8, 0xd2, 0x41, 0x0f, 0x92, 0x9d, 0xe1,
+       0x0b, 0xbf, 0x67, 0x4b, 0x8d, 0x2f, 0x90, 0x59, 0xca, 0xf0, 0x8f, 0x95,
+       0x93, 0x4e, 0xb1, 0x73, 0x60, 0xdf, 0x94, 0x8f, 0x7d, 0x0e, 0x7c, 0x2c,
+       0xec, 0x1c, 0x66, 0x47, 0xa9, 0xf2, 0xb7, 0xf5, 0xd3, 0x3b, 0xde, 0x5f,
+       0x05, 0xfe, 0xf7, 0xf7, 0x64, 0x82, 0xe7, 0xea, 0xf8, 0xf9, 0xbc, 0xc5,
+       0xf0, 0xff, 0x72, 0x08, 0xcf, 0xc9, 0xc2, 0xed, 0x8f, 0xc0, 0x7d, 0x52,
+       0xf4, 0xb9, 0x07, 0xf4, 0x4f, 0x38, 0x07, 0xea, 0xa4, 0xfd, 0xff, 0x39,
+       0x83, 0xeb, 0x4d, 0x95, 0x87, 0x1f, 0x49, 0x29, 0x0c, 0xb5, 0x93, 0xd5,
+       0x9f, 0x2a, 0xde, 0x27, 0x6b, 0xa5, 0x0d, 0x8a, 0xfa, 0xfa, 0x2c, 0x65,
+       0x7d, 0x73, 0xf1, 0x86, 0xf0, 0xef, 0xbb, 0xe2, 0x87, 0x8b, 0xb7, 0xce,
+       0xd3, 0xbb, 0xf1, 0xfc, 0xa6, 0x14, 0xf1, 0xf7, 0x5a, 0xc5, 0x7c, 0xca,
+       0xde, 0x8a, 0xc2, 0xfc, 0xbc, 0x89, 0x90, 0x77, 0x42, 0x1f, 0x55, 0x17,
+       0x7e, 0xa0, 0x85, 0xf8, 0xea, 0xc4, 0x2e, 0xe4, 0xa7, 0xe0, 0x3b, 0x33,
+       0x64, 0x52, 0x1b, 0xa9, 0xfd, 0x66, 0x06, 0xf3, 0xdf, 0x4f, 0x78, 0x2b,
+       0x0a, 0xf3, 0x59, 0xbe, 0x69, 0xbf, 0x1f, 0x51, 0x58, 0x62, 0xbe, 0xe0,
+       0x6f, 0x98, 0xfc, 0xfc, 0x28, 0xd6, 0xaf, 0x0d, 0xdf, 0x77, 0x43, 0x26,
+       0xeb, 0xff, 0x5a, 0xd1, 0x96, 0x1f, 0x7e, 0x05, 0x71, 0xcf, 0xfd, 0x04,
+       0xf3, 0x37, 0xaf, 0x59, 0x19, 0xdf, 0xcf, 0x6b, 0xfa, 0x42, 0xa3, 0xa1,
+       0x65, 0xbf, 0x6e, 0x0c, 0x5f, 0xf2, 0x2c, 0x01, 0x0d, 0xc8, 0x93, 0xf6,
+       0x8a, 0x68, 0x0f, 0xe4, 0xe7, 0xd7, 0x2c, 0x35, 0x63, 0x5e, 0x67, 0xbf,
+       0xec, 0xe0, 0x87, 0xc6, 0x7c, 0x42, 0x62, 0x33, 0x37, 0xff, 0xd8, 0x48,
+       0xf7, 0xed, 0x0f, 0x70, 0x98, 0x31, 0x4c, 0x9e, 0xb6, 0x83, 0x8d, 0x43,
+       0xeb, 0xc9, 0xff, 0xf1, 0x38, 0xf2, 0xfb, 0xf1, 0x6f, 0x45, 0xf9, 0x34,
+       0xdf, 0x62, 0x3d, 0xc9, 0x54, 0x87, 0x42, 0x79, 0x5d, 0xc2, 0xe8, 0x7b,
+       0x0e, 0xe0, 0x0d, 0x97, 0x2b, 0xe0, 0x3b, 0xaf, 0x79, 0x84, 0x74, 0xc8,
+       0x19, 0xe0, 0x07, 0xb0, 0x7e, 0xa8, 0x4f, 0xca, 0xfc, 0xf1, 0xfb, 0x4f,
+       0xd2, 0x71, 0x6b, 0x4e, 0x32, 0xfa, 0x86, 0x4c, 0x39, 0xb5, 0xdd, 0x3e,
+       0x33, 0xcc, 0x6e, 0x27, 0xcf, 0x31, 0xba, 0x34, 0xd2, 0x7f, 0xa0, 0xcf,
+       0x2d, 0x3b, 0xda, 0xa0, 0x07, 0x7b, 0xee, 0xce, 0xf4, 0xdd, 0x88, 0x79,
+       0x33, 0x5f, 0x97, 0xae, 0x0b, 0x32, 0x95, 0xf6, 0x7b, 0x04, 0x3a, 0x3e,
+       0x35, 0x9e, 0xee, 0x4b, 0xcd, 0x7e, 0x76, 0xbf, 0xc4, 0xf5, 0x96, 0x5e,
+       0x78, 0xae, 0xb5, 0x2b, 0xf9, 0x5d, 0xb3, 0x55, 0x83, 0xf4, 0x27, 0xea,
+       0x6d, 0x2d, 0xf2, 0x58, 0xc0, 0x57, 0xf5, 0xf9, 0x70, 0x01, 0x4f, 0x62,
+       0xc9, 0x51, 0xdc, 0xe3, 0xb4, 0x72, 0xf8, 0xdf, 0x26, 0x83, 0x9c, 0x5c,
+       0x79, 0x50, 0xcb, 0x92, 0x3d, 0xba, 0x1a, 0x67, 0xa3, 0x86, 0xd8, 0xc3,
+       0xc6, 0x79, 0xf5, 0x90, 0xa1, 0x82, 0xfd, 0x0e, 0x25, 0x9b, 0x7f, 0xbb,
+       0x90, 0xcf, 0x07, 0xff, 0x6a, 0x2b, 0xee, 0xcb, 0xca, 0x75, 0x11, 0xe4,
+       0x1c, 0x95, 0xcb, 0xba, 0x78, 0x90, 0xcb, 0xe5, 0xec, 0xf7, 0x15, 0xce,
+       0x1c, 0x4c, 0x2a, 0x01, 0xf8, 0x9f, 0x91, 0x88, 0xcf, 0x8e, 0xe7, 0xae,
+       0x58, 0x9e, 0xf1, 0xfd, 0xac, 0x3b, 0x78, 0x6e, 0xc2, 0xfb, 0x43, 0x92,
+       0xfb, 0x68, 0xc3, 0xef, 0x37, 0x14, 0x76, 0xe4, 0xd4, 0x83, 0x53, 0x7b,
+       0x81, 0x1e, 0xf9, 0x61, 0xd3, 0xfc, 0x33, 0x74, 0x67, 0xc8, 0xa2, 0xcc,
+       0x1e, 0x38, 0xde, 0x34, 0xe2, 0x41, 0xbd, 0xf7, 0x8c, 0xd5, 0x95, 0x0e,
+       0xfe, 0x86, 0x49, 0x3c, 0xde, 0x7f, 0xc6, 0x1a, 0x6c, 0x05, 0x7e, 0x7c,
+       0x66, 0x78, 0xb4, 0x04, 0xf1, 0x7b, 0xda, 0xff, 0x7a, 0x12, 0x76, 0x5f,
+       0xdf, 0x19, 0x9d, 0x2b, 0x9d, 0xdd, 0x03, 0x21, 0xf2, 0x8a, 0xef, 0xfe,
+       0x56, 0xf7, 0xb6, 0x95, 0xc9, 0x6b, 0x8b, 0xc7, 0x43, 0xbc, 0x7a, 0x16,
+       0xb1, 0x80, 0x1d, 0x79, 0x9f, 0xcc, 0xf4, 0x5a, 0xf2, 0x26, 0xa3, 0x4b,
+       0xc1, 0xef, 0x6a, 0x24, 0xbf, 0x0d, 0xe6, 0xe9, 0xca, 0x9c, 0xfc, 0xfd,
+       0x4c, 0xfa, 0x5d, 0xd2, 0x9a, 0x1f, 0xa1, 0x5d, 0xd9, 0x01, 0x37, 0x2d,
+       0xff, 0x9d, 0xa6, 0xaf, 0xa9, 0xd7, 0x76, 0xd8, 0xaf, 0xbb, 0x25, 0x76,
+       0x3f, 0x89, 0x83, 0xe9, 0xfb, 0xd5, 0xc3, 0xae, 0xfe, 0x6c, 0x1a, 0x9c,
+       0x73, 0xa3, 0x76, 0xb6, 0x44, 0xe7, 0x33, 0xbf, 0xf9, 0x30, 0xde, 0xc3,
+       0xa3, 0xb6, 0xab, 0x3b, 0xec, 0x9b, 0xff, 0xa5, 0x7f, 0xb4, 0xb3, 0x7d,
+       0xe4, 0xda, 0x92, 0x59, 0x14, 0xf2, 0x7b, 0xab, 0xed, 0xa4, 0x0e, 0xbd,
+       0x5c, 0xe8, 0x77, 0xbb, 0x58, 0x9e, 0xfb, 0x91, 0xe1, 0x4f, 0xb7, 0x2d,
+       0xa7, 0xf5, 0xd5, 0xbb, 0xa2, 0x11, 0x8e, 0x97, 0x9f, 0x37, 0x78, 0x80,
+       0x7f, 0x5f, 0xde, 0x61, 0x40, 0x7b, 0xe7, 0xb2, 0x2d, 0x78, 0x6e, 0x15,
+       0xd4, 0xf7, 0xe6, 0x3a, 0x3c, 0x38, 0x5a, 0x0e, 0x9e, 0xef, 0x12, 0xf8,
+       0xbd, 0x44, 0x63, 0xff, 0x3d, 0xc8, 0x1d, 0xf2, 0x5b, 0x1d, 0xde, 0xb7,
+       0xf1, 0xc5, 0xcf, 0x0d, 0xf8, 0x7b, 0x1e, 0x4b, 0x5f, 0xb8, 0x6b, 0x07,
+       0xd8, 0x4f, 0x5f, 0xa4, 0xdb, 0x5f, 0x7e, 0x05, 0xfc, 0x7b, 0x2f, 0x27,
+       0xe0, 0x7d, 0x00, 0x24, 0x99, 0x7d, 0x3f, 0x91, 0xd3, 0x23, 0xd0, 0x97,
+       0x9d, 0xee, 0x87, 0xfc, 0x0b, 0x33, 0xea, 0x0d, 0x4b, 0x5f, 0x4b, 0x41,
+       0xfe, 0x25, 0xf6, 0xef, 0xd2, 0xcf, 0xa3, 0xf0, 0x1c, 0xfc, 0xe5, 0x13,
+       0xf7, 0xc7, 0x82, 0x1f, 0xac, 0x55, 0xb3, 0x87, 0xfd, 0x8e, 0xa4, 0x6c,
+       0xf2, 0x00, 0x1f, 0x5e, 0xbe, 0x23, 0x0a, 0xf5, 0x3e, 0xa2, 0x77, 0xbf,
+       0x06, 0xeb, 0x2f, 0xfd, 0xc5, 0xc4, 0x69, 0xfd, 0x61, 0xfc, 0xdf, 0x25,
+       0x10, 0x58, 0x4f, 0x7b, 0xcb, 0x6b, 0xe8, 0x7f, 0x0c, 0xed, 0x6f, 0x64,
+       0xb9, 0x7e, 0xbd, 0xa5, 0x07, 0xe3, 0x03, 0x1d, 0x72, 0x96, 0xe5, 0xcd,
+       0xce, 0x0d, 0xdd, 0xcb, 0xbc, 0x1f, 0xf0, 0xa7, 0x8a, 0x88, 0x7b, 0x10,
+       0x59, 0xde, 0x6c, 0x81, 0x2c, 0xb1, 0xdf, 0x95, 0x7c, 0x22, 0xf2, 0x39,
+       0xf0, 0xdf, 0x66, 0xf2, 0x38, 0xa9, 0xf0, 0x97, 0xc4, 0x11, 0x63, 0x32,
+       0xd0, 0xa1, 0x9b, 0xb0, 0x7b, 0x1f, 0x9f, 0xe8, 0x8d, 0xf7, 0xea, 0x9e,
+       0xcf, 0xe4, 0xe7, 0x97, 0x49, 0x90, 0x9f, 0x77, 0x14, 0xf8, 0x76, 0xae,
+       0xfa, 0x00, 0xfa, 0x4b, 0x0c, 0x2c, 0x5f, 0xaf, 0x8b, 0x7b, 0x2d, 0x3f,
+       0xcc, 0x64, 0xe7, 0x82, 0x17, 0x1b, 0xff, 0xa2, 0xf0, 0x9b, 0x54, 0xaf,
+       0xb9, 0xa1, 0xac, 0xf7, 0x65, 0xbf, 0xb3, 0x5c, 0x50, 0x6f, 0xef, 0xbf,
+       0x82, 0x96, 0xab, 0x38, 0x9c, 0xff, 0x91, 0xe4, 0xfa, 0x08, 0xd6, 0xb7,
+       0xac, 0x71, 0xcb, 0xbe, 0x77, 0x11, 0x2e, 0xcf, 0x7d, 0xef, 0x0f, 0x30,
+       0xee, 0x09, 0x13, 0xfa, 0x69, 0xc8, 0xbb, 0x0c, 0x7e, 0x6a, 0xfb, 0x65,
+       0xb1, 0x31, 0xc8, 0xe3, 0x0e, 0xdb, 0x15, 0x71, 0xf5, 0x8b, 0xcf, 0xfc,
+       0x1e, 0xf3, 0x47, 0x2e, 0xbe, 0x7e, 0x0f, 0xfe, 0xbe, 0xd8, 0x7c, 0xd9,
+       0x7f, 0x11, 0xee, 0xc7, 0x6a, 0x33, 0xfb, 0x3f, 0x79, 0x88, 0x96, 0x7b,
+       0x4f, 0x9c, 0xc2, 0x7d, 0x51, 0xcf, 0xb7, 0x53, 0x1c, 0x5e, 0x62, 0x7c,
+       0xa5, 0x12, 0xd6, 0xd1, 0x1f, 0xf2, 0x57, 0x5c, 0xed, 0x99, 0x48, 0xb7,
+       0x8c, 0xde, 0xcf, 0x6f, 0xca, 0x45, 0xf8, 0x09, 0x3f, 0x6d, 0xfb, 0xe5,
+       0xc8, 0xf6, 0x95, 0x98, 0xa7, 0xe8, 0x5f, 0xcc, 0x4f, 0xf4, 0x2f, 0xde,
+       0xfb, 0xef, 0x4c, 0xa6, 0xdf, 0x5f, 0xd3, 0xfb, 0xf3, 0x40, 0x2e, 0xef,
+       0x84, 0x38, 0x44, 0x98, 0x3e, 0x7f, 0x2d, 0xc6, 0x9f, 0x07, 0x3f, 0x75,
+       0xbb, 0x33, 0x9d, 0xe5, 0x73, 0x5f, 0xb3, 0xd1, 0x7a, 0x18, 0xde, 0xfc,
+       0x5f, 0x8a, 0x9c, 0x0c, 0xc3, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xad, 0x58,
+       0x0d, 0x6c, 0x14, 0xd7, 0x11, 0x9e, 0xb7, 0x7b, 0xb7, 0x77, 0xc6, 0x77,
+       0xf6, 0x81, 0x8d, 0x7f, 0xe2, 0x1f, 0xf6, 0xce, 0xc4, 0x18, 0x7c, 0xf8,
+       0x16, 0xff, 0xd5, 0xb1, 0x4d, 0x39, 0xfc, 0x83, 0x28, 0x42, 0xcd, 0xf1,
+       0x93, 0xd4, 0x4a, 0x21, 0x6c, 0x9a, 0x40, 0x28, 0xc4, 0xf8, 0x64, 0x43,
+       0x8b, 0x92, 0xaa, 0xac, 0x7b, 0x95, 0xf9, 0x11, 0x51, 0x5c, 0x35, 0x8a,
+       0xa0, 0x4d, 0xab, 0x83, 0x08, 0x14, 0x55, 0x54, 0x18, 0x17, 0x22, 0x8a,
+       0x30, 0xbd, 0x04, 0x15, 0x70, 0x1b, 0xd1, 0x43, 0x89, 0x14, 0x92, 0x5a,
+       0x68, 0xeb, 0x36, 0xd4, 0x6d, 0x0c, 0xe7, 0xd2, 0xa4, 0x2d, 0x6a, 0x24,
+       0x77, 0xe6, 0xed, 0x1e, 0x77, 0xeb, 0x9f, 0xb4, 0x89, 0x7a, 0x96, 0x6f,
+       0x3c, 0xef, 0xcd, 0x9b, 0x37, 0xf3, 0xcd, 0xbc, 0x99, 0xf7, 0xdc, 0x01,
+       0xf8, 0xa9, 0x06, 0xe8, 0x70, 0x82, 0x3d, 0x37, 0x17, 0x69, 0x07, 0x53,
+       0x22, 0x38, 0xd4, 0x01, 0xa0, 0xc1, 0x3c, 0x4e, 0x63, 0x2a, 0xce, 0x3f,
+       0x57, 0x70, 0x01, 0x6c, 0x35, 0x24, 0x0c, 0x21, 0x67, 0x1e, 0xc0, 0x63,
+       0x60, 0x7e, 0x72, 0x73, 0x6c, 0x50, 0x0f, 0xb0, 0x91, 0xfe, 0x96, 0x71,
+       0xbc, 0xe1, 0xb7, 0xf7, 0x59, 0x16, 0xc0, 0x13, 0x30, 0x60, 0x87, 0x32,
+       0x80, 0x9b, 0x42, 0xef, 0x1e, 0x49, 0x04, 0x18, 0x1f, 0xf8, 0xa1, 0x5d,
+       0x75, 0x91, 0x50, 0x9b, 0xe7, 0x76, 0x05, 0x00, 0xd3, 0x3e, 0x10, 0x26,
+       0x2b, 0x01, 0x26, 0xe9, 0xb3, 0x62, 0x3a, 0x05, 0xb0, 0x01, 0xc9, 0xd1,
+       0x67, 0x52, 0xa4, 0x6f, 0x0d, 0x60, 0x3e, 0x7e, 0xb7, 0x40, 0x45, 0x18,
+       0xf5, 0xdc, 0xf1, 0xb8, 0x34, 0x21, 0x00, 0x50, 0x2a, 0x33, 0x1b, 0x97,
+       0x2b, 0x81, 0x12, 0x92, 0xc3, 0x79, 0x25, 0x56, 0x8b, 0x74, 0xd0, 0xa1,
+       0x44, 0xd0, 0x9e, 0x3d, 0x42, 0xc8, 0x27, 0xe3, 0xba, 0xe7, 0xa4, 0x58,
+       0x15, 0x88, 0xa9, 0x75, 0x7b, 0x04, 0x95, 0x8f, 0x8f, 0xb3, 0xb7, 0xb7,
+       0x81, 0x8f, 0xb6, 0x8b, 0x55, 0x85, 0xdc, 0x00, 0x89, 0xb9, 0x12, 0xb0,
+       0x6c, 0xa4, 0xf3, 0x95, 0x78, 0x10, 0xf1, 0xd0, 0x3e, 0x01, 0xe5, 0x04,
+       0xea, 0x49, 0xd8, 0xa1, 0x63, 0x10, 0xf7, 0xad, 0x6d, 0x15, 0xc2, 0x83,
+       0xdc, 0x0f, 0xdb, 0xa8, 0x8e, 0xfb, 0x0a, 0xc0, 0xb8, 0x7d, 0xb5, 0x95,
+       0x38, 0xee, 0x07, 0x58, 0x4e, 0xe3, 0x4e, 0xd3, 0x6e, 0x2f, 0x8e, 0x07,
+       0xac, 0xf2, 0x29, 0x7f, 0xac, 0xfc, 0x05, 0x59, 0xe0, 0xfe, 0xd5, 0xe6,
+       0x08, 0xe1, 0x01, 0xff, 0x74, 0x3c, 0x36, 0xd0, 0x7c, 0x1d, 0x40, 0x04,
+       0x62, 0x22, 0xe1, 0x8a, 0x9f, 0x8d, 0x4e, 0xc4, 0xbd, 0xc9, 0xc4, 0x1d,
+       0x20, 0x28, 0x02, 0xc6, 0x65, 0x97, 0xc9, 0xef, 0x72, 0xba, 0x62, 0x62,
+       0x15, 0xda, 0x9d, 0xe5, 0xd4, 0x44, 0xf4, 0xa7, 0xe9, 0x22, 0xc6, 0x05,
+       0xf9, 0x26, 0x5b, 0xec, 0x4d, 0xa2, 0x2c, 0x08, 0xb0, 0x17, 0xe3, 0x0b,
+       0xe7, 0xed, 0xe3, 0x0f, 0xec, 0x20, 0x1c, 0x0a, 0x2a, 0x6d, 0xa4, 0xa7,
+       0xd1, 0x0c, 0x2f, 0x43, 0x5d, 0x9b, 0x50, 0xae, 0x8f, 0x85, 0x81, 0xf6,
+       0x75, 0x42, 0x3f, 0xa7, 0x87, 0x58, 0x9c, 0xdb, 0xf1, 0x65, 0x98, 0xe0,
+       0x34, 0x08, 0x1e, 0x1b, 0x51, 0x84, 0x9f, 0xd3, 0x36, 0x08, 0x71, 0xba,
+       0x0a, 0xc2, 0x9c, 0xae, 0x86, 0x7e, 0x4e, 0xd7, 0xc0, 0x00, 0xa7, 0x6b,
+       0x21, 0xce, 0x29, 0x2c, 0x89, 0x45, 0xc0, 0x4b, 0x3b, 0x7d, 0xc7, 0x73,
+       0x3b, 0x13, 0xc9, 0x57, 0x9e, 0x15, 0x26, 0x91, 0xd6, 0x7e, 0x0d, 0xc2,
+       0x03, 0xae, 0xe9, 0x38, 0xec, 0x31, 0x71, 0x9a, 0x1d, 0x07, 0x8d, 0x51,
+       0x3e, 0x7e, 0x5e, 0x1c, 0x56, 0x81, 0x5a, 0xc0, 0xf5, 0x4d, 0xc5, 0xa3,
+       0xb8, 0x82, 0xe7, 0xf7, 0x54, 0x3c, 0x1c, 0x94, 0x8f, 0x18, 0xb7, 0x0c,
+       0x88, 0x16, 0x10, 0x5d, 0x0e, 0xba, 0x48, 0x74, 0x05, 0x25, 0x2e, 0xea,
+       0x59, 0x09, 0xb2, 0x8d, 0xf8, 0x56, 0x08, 0x72, 0xbe, 0xfd, 0x7f, 0xc4,
+       0xa1, 0x41, 0x57, 0x6d, 0xaa, 0x7f, 0x06, 0x3c, 0x5a, 0x67, 0xce, 0x8b,
+       0xef, 0x9a, 0x79, 0x21, 0x12, 0x86, 0x75, 0xa9, 0x38, 0x9d, 0x91, 0x65,
+       0xce, 0x27, 0xe3, 0x05, 0x68, 0x67, 0x68, 0xe9, 0xf4, 0x38, 0x26, 0xc7,
+       0x6b, 0x33, 0x5b, 0xfe, 0x2e, 0x7b, 0x00, 0x8e, 0x46, 0xdb, 0x42, 0xb6,
+       0x42, 0xe4, 0x6b, 0x5a, 0x7a, 0xca, 0x90, 0xff, 0x99, 0xbc, 0xd1, 0xe0,
+       0x9b, 0x5a, 0x7e, 0xe1, 0x43, 0xfe, 0x54, 0xf4, 0x31, 0x83, 0x0f, 0xb4,
+       0xd4, 0xd8, 0x15, 0x80, 0xde, 0xde, 0xc7, 0x43, 0x6d, 0x8f, 0x00, 0xa8,
+       0x19, 0x59, 0x55, 0x10, 0xa0, 0xc2, 0x51, 0x2e, 0x50, 0xfe, 0xec, 0xf6,
+       0x18, 0xf8, 0xab, 0xbd, 0x7b, 0x14, 0x0f, 0x9e, 0x23, 0xb5, 0xc4, 0xa5,
+       0x90, 0x7f, 0x4e, 0x07, 0x62, 0x86, 0xf8, 0x89, 0x65, 0x22, 0x34, 0x20,
+       0x6d, 0x93, 0xd4, 0x97, 0x65, 0xb4, 0xb3, 0x74, 0x75, 0xbc, 0xcf, 0x40,
+       0xb8, 0x25, 0xbf, 0x03, 0xcf, 0xef, 0x78, 0xdc, 0x0e, 0x87, 0x70, 0xfd,
+       0x7e, 0xc9, 0x90, 0x77, 0xe0, 0x3a, 0x67, 0x75, 0xca, 0x2f, 0x1c, 0xd7,
+       0x32, 0x90, 0x1f, 0x1c, 0xac, 0xec, 0x61, 0xbe, 0xd9, 0xf7, 0x47, 0xfd,
+       0xc7, 0x48, 0xbf, 0xda, 0xfb, 0xb0, 0x06, 0x64, 0xc7, 0x39, 0xa6, 0x7c,
+       0xd6, 0x3e, 0x3f, 0xce, 0x57, 0x4f, 0x92, 0x3c, 0x38, 0xcb, 0x81, 0xe2,
+       0x5e, 0xe4, 0x34, 0xf4, 0x8c, 0x0f, 0x56, 0x56, 0x52, 0x5c, 0xce, 0x10,
+       0x48, 0x34, 0x9f, 0xeb, 0xad, 0x21, 0xdc, 0xfe, 0x92, 0x1f, 0x3a, 0x43,
+       0xf2, 0x09, 0xb7, 0x91, 0x5f, 0x67, 0x28, 0x07, 0xe7, 0xcf, 0x4e, 0xdf,
+       0x97, 0x83, 0xa7, 0x49, 0x7e, 0xea, 0x78, 0xe2, 0x43, 0x34, 0x00, 0xd7,
+       0xbf, 0x25, 0xab, 0xe7, 0x68, 0xbe, 0x2b, 0xf3, 0xd3, 0x72, 0xaa, 0x4b,
+       0x77, 0x97, 0xbd, 0xd3, 0xa7, 0x7b, 0x53, 0x79, 0xca, 0x70, 0xff, 0x4d,
+       0xe8, 0x77, 0x24, 0x08, 0x51, 0x89, 0xd7, 0x91, 0x66, 0xcf, 0x6d, 0xac,
+       0xa3, 0x80, 0x31, 0x99, 0xc4, 0x78, 0x26, 0xb6, 0xa2, 0x1e, 0xc4, 0xa1,
+       0x36, 0xa4, 0x46, 0xec, 0x38, 0xfc, 0xa5, 0x4d, 0x13, 0xf5, 0x58, 0xa4,
+       0x48, 0x6f, 0x8c, 0xea, 0x5d, 0x97, 0xa4, 0x97, 0x2e, 0xc3, 0x75, 0x2f,
+       0x6f, 0xb8, 0x25, 0x19, 0x79, 0x56, 0x6c, 0xe4, 0x99, 0x59, 0x87, 0x86,
+       0x2e, 0x0d, 0xbf, 0x50, 0x64, 0xb0, 0x21, 0x48, 0x3b, 0x57, 0x5d, 0x97,
+       0xee, 0xff, 0xe3, 0xf7, 0x88, 0x5f, 0xd7, 0x3d, 0x97, 0x42, 0xe2, 0xa9,
+       0xf3, 0x74, 0xb4, 0x07, 0xb2, 0x48, 0xc8, 0x65, 0xa9, 0x1b, 0xc9, 0x73,
+       0xd6, 0x78, 0xde, 0x11, 0x13, 0xb3, 0x88, 0x5f, 0xbc, 0x95, 0xe4, 0x96,
+       0xbf, 0x33, 0x52, 0x46, 0x7e, 0xad, 0x18, 0xd1, 0x23, 0x6e, 0xd2, 0x33,
+       0xf4, 0x5e, 0x91, 0x61, 0x87, 0xd9, 0x17, 0x82, 0xff, 0x64, 0x5f, 0xa4,
+       0x2f, 0xb4, 0x8b, 0x54, 0x9c, 0x01, 0xba, 0xcf, 0x89, 0x51, 0x07, 0xe2,
+       0xd5, 0xcd, 0xc2, 0x97, 0xdd, 0xc4, 0xff, 0x9c, 0x29, 0x1a, 0xda, 0xff,
+       0x67, 0x27, 0xe6, 0x47, 0x36, 0xc9, 0x07, 0x5d, 0x85, 0xe8, 0xd7, 0x76,
+       0xd3, 0xaf, 0xce, 0xe1, 0x13, 0x7d, 0x6e, 0xa4, 0xdb, 0x5f, 0x7d, 0x7a,
+       0x2d, 0x54, 0xd1, 0x71, 0xb0, 0xf3, 0xfa, 0x2d, 0xe3, 0x0f, 0x9d, 0xff,
+       0x9d, 0xaf, 0xdb, 0x53, 0xf5, 0x9c, 0x7f, 0x63, 0x20, 0xd0, 0xcf, 0x2e,
+       0x48, 0x7e, 0x62, 0x12, 0xe5, 0x41, 0xe7, 0x80, 0x55, 0xae, 0x0b, 0x0e,
+       0xff, 0x8d, 0xea, 0x4e, 0x57, 0x7a, 0x9d, 0x47, 0xbb, 0x26, 0x64, 0x77,
+       0x2e, 0xc7, 0xdb, 0xec, 0x57, 0x40, 0x2d, 0x04, 0xf5, 0x3d, 0x6b, 0xae,
+       0x25, 0x3f, 0x5c, 0x64, 0xf7, 0x90, 0x14, 0x75, 0x30, 0xa4, 0x3f, 0xe9,
+       0x51, 0x3c, 0xc4, 0x9b, 0xe7, 0x07, 0x2e, 0x7e, 0x0f, 0xd2, 0xe5, 0xe1,
+       0xd5, 0x1c, 0x1e, 0xfb, 0xe4, 0x79, 0xfa, 0xe6, 0x01, 0xb4, 0x3d, 0x27,
+       0x85, 0x57, 0xe0, 0xa4, 0x23, 0x48, 0xb8, 0x07, 0x4e, 0xe6, 0x07, 0xc9,
+       0xbf, 0x80, 0x04, 0x5b, 0x42, 0x1c, 0xef, 0x28, 0xcf, 0xe3, 0x00, 0xe6,
+       0x06, 0xc3, 0x7c, 0x3a, 0x3d, 0x77, 0xc2, 0x27, 0xe0, 0x3e, 0xa7, 0x87,
+       0x2a, 0x14, 0xac, 0xa0, 0x70, 0x61, 0x5f, 0x10, 0xfe, 0xb8, 0x30, 0x65,
+       0x5f, 0xb7, 0x79, 0x9e, 0xda, 0xc5, 0x53, 0xad, 0x12, 0xe6, 0xc1, 0xbd,
+       0x67, 0xc0, 0x83, 0x47, 0x12, 0xba, 0x87, 0x5f, 0x8b, 0x38, 0x91, 0xef,
+       0x3e, 0x08, 0x24, 0x01, 0xf7, 0xe8, 0x0b, 0xf5, 0xdc, 0x1b, 0x13, 0xa2,
+       0xa4, 0xa7, 0x71, 0xb8, 0xa6, 0x80, 0xe2, 0x7d, 0xd6, 0x3c, 0x9f, 0x8e,
+       0x02, 0x01, 0xe4, 0x34, 0x9c, 0x32, 0xe4, 0x39, 0x20, 0x57, 0xa4, 0xf8,
+       0x24, 0xbe, 0x0e, 0x33, 0x3e, 0x99, 0x15, 0xf3, 0x2c, 0xf3, 0x6e, 0xe5,
+       0x21, 0xcb, 0xfa, 0xec, 0x06, 0x9f, 0x75, 0xbd, 0x16, 0x8c, 0xfb, 0xeb,
+       0xa9, 0x1e, 0x1b, 0xeb, 0xe7, 0x06, 0x97, 0x58, 0xe4, 0xf7, 0x67, 0xad,
+       0xba, 0x46, 0x79, 0xb9, 0x3c, 0xbe, 0x6d, 0x2d, 0xe1, 0x92, 0xb3, 0xba,
+       0xda, 0x32, 0x5f, 0x0f, 0x4e, 0x7e, 0x7f, 0xa8, 0x2b, 0x76, 0x29, 0x51,
+       0x5c, 0x0f, 0x1f, 0x1b, 0xfd, 0xbc, 0x01, 0x7f, 0x78, 0x3f, 0x80, 0xb0,
+       0x48, 0xfe, 0x35, 0xe9, 0x00, 0x3f, 0xc2, 0x78, 0x34, 0x8e, 0xdb, 0x2c,
+       0x71, 0xcf, 0xd0, 0x31, 0x1f, 0x51, 0x2e, 0xe3, 0xdd, 0xb4, 0xb8, 0xe3,
+       0xaf, 0x43, 0xb6, 0xf2, 0xcb, 0xbc, 0x66, 0x1e, 0x14, 0x43, 0x71, 0x7a,
+       0x1e, 0xa4, 0x70, 0x76, 0x3d, 0xc0, 0x91, 0xe7, 0xc1, 0x30, 0x0a, 0x11,
+       0xce, 0x6e, 0x29, 0x8a, 0x57, 0x8e, 0x69, 0x38, 0xd5, 0xc3, 0xc2, 0x6c,
+       0x9a, 0xaf, 0xbb, 0x26, 0x42, 0x94, 0xe3, 0xde, 0xa3, 0xc4, 0x70, 0x7c,
+       0x7e, 0xc8, 0x8a, 0x77, 0x7e, 0x87, 0x15, 0xef, 0x42, 0xd5, 0x8a, 0x6f,
+       0xd1, 0x76, 0x2b, 0xbe, 0x25, 0x61, 0x2b, 0xbe, 0x0b, 0xf6, 0x5a, 0xf1,
+       0xf4, 0x6a, 0x56, 0xfc, 0xca, 0x0e, 0x34, 0x5a, 0xe4, 0x1f, 0xee, 0x6f,
+       0xb1, 0xf0, 0x8b, 0x8e, 0xac, 0xb1, 0xc8, 0x2f, 0x8e, 0xae, 0xb7, 0xf0,
+       0x95, 0xaf, 0x3f, 0x61, 0x91, 0x5f, 0x3a, 0xf0, 0x0d, 0xcb, 0x7c, 0xe0,
+       0xfc, 0x0e, 0xcb, 0x7c, 0x32, 0xaf, 0xa6, 0xc6, 0x7d, 0x59, 0xac, 0xdb,
+       0x22, 0x37, 0x35, 0xee, 0x35, 0xd7, 0x9e, 0xb7, 0xe8, 0x4d, 0xc6, 0x59,
+       0xc3, 0x9f, 0xff, 0x67, 0x9c, 0x77, 0x4d, 0x89, 0xf3, 0xf3, 0x68, 0x1b,
+       0x9d, 0xbb, 0xeb, 0x59, 0x63, 0x87, 0xe9, 0x18, 0x7e, 0x35, 0xd3, 0xa8,
+       0x4b, 0xed, 0x62, 0x73, 0x3c, 0x48, 0xf1, 0x6e, 0xb6, 0x2b, 0x14, 0xd3,
+       0xdf, 0xc9, 0x39, 0xad, 0x6e, 0x3a, 0xef, 0x66, 0x1f, 0x0a, 0x99, 0x7d,
+       0x08, 0xd4, 0x3e, 0x1e, 0xf7, 0x90, 0x99, 0x27, 0x4a, 0x5c, 0xb9, 0x4c,
+       0x75, 0xb4, 0xfa, 0x66, 0xa8, 0x35, 0x0b, 0xf9, 0x5a, 0x3d, 0x7c, 0x99,
+       0xca, 0x71, 0xfd, 0x58, 0x7f, 0x6b, 0xb6, 0xcc, 0xd3, 0x44, 0xf6, 0xa0,
+       0x3c, 0x33, 0x71, 0x79, 0xb4, 0x81, 0x81, 0xcd, 0x72, 0x5e, 0x90, 0xcf,
+       0x4b, 0xe1, 0xb6, 0x41, 0xeb, 0x15, 0xb3, 0x51, 0xb8, 0xe9, 0xd3, 0x68,
+       0x84, 0x97, 0x4b, 0x4a, 0x2a, 0xdc, 0x7f, 0xbd, 0x39, 0xcf, 0x1a, 0x8c,
+       0xba, 0xbe, 0x2e, 0x98, 0x01, 0xb6, 0x34, 0x3c, 0x96, 0x9b, 0xe3, 0x00,
+       0x7e, 0x6e, 0x5f, 0xb3, 0x31, 0x05, 0x1b, 0xcc, 0xf7, 0x00, 0xde, 0xcb,
+       0x41, 0xa2, 0x7b, 0xb9, 0xe0, 0x8c, 0x46, 0xbc, 0x33, 0xdd, 0x27, 0x95,
+       0x23, 0x22, 0xbf, 0x27, 0xa9, 0xfc, 0xde, 0x74, 0x95, 0xa9, 0x76, 0xa2,
+       0x1b, 0x9d, 0xf1, 0x52, 0xea, 0x5f, 0xc7, 0xf2, 0xd4, 0x23, 0x5e, 0xac,
+       0xf3, 0x77, 0x05, 0x45, 0xe6, 0xf7, 0x2c, 0xa6, 0x47, 0xc8, 0xa9, 0x04,
+       0x39, 0xc6, 0x9b, 0xce, 0x8d, 0x50, 0xd0, 0x4f, 0xf7, 0x77, 0xfc, 0xf3,
+       0x21, 0xac, 0xbb, 0xc2, 0xf5, 0x90, 0xe6, 0xe7, 0xe6, 0x7b, 0x74, 0xb4,
+       0x5f, 0x35, 0xed, 0x39, 0xe1, 0x55, 0x8f, 0x91, 0x9e, 0x51, 0xe6, 0xe9,
+       0xab, 0xc1, 0xb5, 0xd7, 0x1b, 0x3f, 0x2a, 0xa5, 0xfe, 0xe3, 0x10, 0x11,
+       0x09, 0xac, 0x83, 0x81, 0xac, 0xe0, 0x6b, 0x34, 0xaf, 0xed, 0x6f, 0x9e,
+       0xcb, 0xfb, 0x6a, 0x3e, 0xfa, 0x87, 0x75, 0x54, 0x17, 0x64, 0x7e, 0x7f,
+       0xd0, 0x9e, 0x67, 0xfc, 0x3d, 0xf0, 0x11, 0x29, 0x7b, 0x24, 0xed, 0x9c,
+       0x1e, 0xb0, 0xf3, 0xbe, 0x03, 0xe6, 0xfb, 0x68, 0xb3, 0x89, 0x57, 0xf2,
+       0x7d, 0xb4, 0xc9, 0xdc, 0x7f, 0x14, 0x55, 0x6c, 0xc7, 0x3a, 0xbd, 0xf9,
+       0xfc, 0x55, 0x8e, 0xcb, 0xce, 0x82, 0x71, 0xb0, 0xe5, 0xf0, 0x7c, 0xe3,
+       0xf7, 0xa4, 0xa7, 0x8b, 0x5d, 0xd5, 0x87, 0xc8, 0xa7, 0x60, 0x8d, 0xb2,
+       0x7e, 0x29, 0x8d, 0x27, 0xdf, 0x4b, 0x45, 0xe2, 0xe7, 0xe9, 0x8b, 0xed,
+       0xa2, 0x3f, 0x5b, 0x9f, 0xe1, 0xbe, 0x98, 0xa4, 0x3b, 0x0b, 0xc6, 0xf8,
+       0x7b, 0xee, 0xc1, 0xfa, 0x53, 0x46, 0x1f, 0x99, 0x5d, 0xbf, 0xc6, 0xfb,
+       0x6c, 0xca, 0x6f, 0x43, 0xff, 0xe8, 0xc1, 0x4c, 0xde, 0x5f, 0x46, 0x0f,
+       0x96, 0xb4, 0x10, 0x4d, 0xe9, 0xbf, 0xcb, 0xf5, 0x6f, 0x0e, 0xdf, 0xb0,
+       0xe4, 0xc9, 0x96, 0xbd, 0xef, 0x5b, 0xf2, 0xef, 0x29, 0xed, 0x0f, 0x96,
+       0x79, 0x3d, 0x77, 0xc2, 0x5e, 0x84, 0xfe, 0xeb, 0x6f, 0x14, 0xae, 0xfa,
+       0x3a, 0xe2, 0x77, 0xe7, 0x9c, 0xa3, 0x9e, 0xde, 0x8d, 0x18, 0xb7, 0x9b,
+       0xde, 0xba, 0x94, 0x7e, 0xfd, 0xc5, 0x45, 0x6d, 0xb4, 0xdf, 0x7f, 0xf7,
+       0xf3, 0xaf, 0x1c, 0xdf, 0x91, 0x7d, 0x71, 0xb0, 0x2d, 0x4c, 0xf9, 0x79,
+       0x6b, 0xdf, 0x4d, 0xce, 0xeb, 0xfb, 0x74, 0x4e, 0xa7, 0xfa, 0x99, 0x7c,
+       0x67, 0x26, 0xa9, 0xf4, 0x16, 0x54, 0xd8, 0x30, 0x3e, 0x13, 0x6c, 0x8e,
+       0x72, 0xdc, 0x3b, 0x7d, 0x9f, 0x2d, 0x3e, 0xe3, 0x5d, 0x32, 0xb2, 0x32,
+       0xaf, 0x85, 0xfa, 0xec, 0x48, 0x89, 0x64, 0x33, 0x68, 0xb9, 0xc1, 0x17,
+       0x36, 0x38, 0x0d, 0x7e, 0xd5, 0x6a, 0xa2, 0x09, 0xbb, 0xeb, 0x00, 0xbd,
+       0x33, 0x47, 0x18, 0x04, 0x19, 0xe6, 0xc3, 0x26, 0x16, 0xfa, 0xe9, 0x53,
+       0xe8, 0xf7, 0x0b, 0x79, 0xea, 0x27, 0x94, 0x7f, 0x5d, 0x3b, 0x26, 0xaa,
+       0x6c, 0x78, 0x1e, 0xba, 0x02, 0xfa, 0x93, 0x0c, 0xe3, 0x59, 0x3c, 0x57,
+       0xfd, 0x17, 0xf9, 0xcf, 0xf0, 0x7a, 0x57, 0x38, 0x8f, 0xdb, 0x59, 0x4e,
+       0xf7, 0x8e, 0x31, 0x41, 0xab, 0x62, 0x58, 0x0b, 0xaa, 0x7d, 0x85, 0xeb,
+       0x6c, 0x18, 0x97, 0xb1, 0x39, 0xda, 0x5d, 0xea, 0xc4, 0x4b, 0x8e, 0xe7,
+       0x1a, 0xbc, 0x64, 0x9c, 0x8f, 0x46, 0xdf, 0x24, 0x3f, 0x0f, 0xcd, 0x1e,
+       0x55, 0xf0, 0xa1, 0x9e, 0x0f, 0x99, 0x18, 0xe3, 0xf9, 0xfc, 0x4b, 0x16,
+       0x3d, 0xc1, 0xf3, 0x4d, 0x97, 0xd6, 0xbb, 0xf9, 0x79, 0xea, 0xa0, 0x77,
+       0x17, 0xbd, 0x77, 0xe9, 0xbd, 0x91, 0xc8, 0x30, 0x68, 0x86, 0x8f, 0x71,
+       0xff, 0xe6, 0x4c, 0xa1, 0x0b, 0x7d, 0x46, 0x3d, 0x6b, 0x34, 0x69, 0xbb,
+       0x78, 0xb8, 0x9c, 0xd1, 0xfd, 0xe0, 0x88, 0x03, 0xe8, 0x3c, 0xe0, 0x3e,
+       0x41, 0x81, 0xf6, 0x19, 0x72, 0x44, 0x4f, 0x20, 0x9f, 0x87, 0xb6, 0xd3,
+       0x3d, 0xe5, 0xd7, 0x92, 0x71, 0x9f, 0xaf, 0xfe, 0x95, 0x23, 0x46, 0x75,
+       0x63, 0x9b, 0xf3, 0x63, 0x1e, 0xa7, 0x12, 0x9f, 0x97, 0xeb, 0xc9, 0x2d,
+       0xc3, 0xca, 0x85, 0xeb, 0x72, 0x5f, 0x72, 0x44, 0x23, 0x64, 0x9f, 0x1e,
+       0x2f, 0x5d, 0x87, 0xf6, 0xf5, 0xdb, 0xf1, 0xfe, 0x42, 0xef, 0xe9, 0x77,
+       0x71, 0x1e, 0xcf, 0xdd, 0x9d, 0x17, 0x17, 0x1d, 0x3f, 0x94, 0x16, 0x8f,
+       0x12, 0x33, 0x0e, 0xf0, 0x0c, 0x80, 0x31, 0x9f, 0x7f, 0x8c, 0xe6, 0x3b,
+       0x87, 0x47, 0x6f, 0x51, 0x1d, 0xb9, 0xe2, 0x55, 0xbd, 0xe4, 0xff, 0xa8,
+       0x20, 0xd7, 0x53, 0x1d, 0xe9, 0xcc, 0x7a, 0x53, 0xa2, 0xfa, 0x53, 0xe3,
+       0x93, 0xf9, 0x3a, 0xb4, 0x97, 0xfb, 0x8f, 0xf5, 0xe0, 0xfb, 0x8c, 0xe3,
+       0xec, 0xf4, 0xfc, 0x09, 0xf3, 0x75, 0x0b, 0x16, 0x9b, 0x6c, 0x7a, 0xbf,
+       0x09, 0xea, 0x62, 0x5a, 0xdf, 0xe9, 0xd4, 0x25, 0xd2, 0x87, 0x19, 0xc1,
+       0xef, 0x7f, 0xb3, 0xf9, 0x7f, 0x67, 0x6b, 0xfc, 0x15, 0x3f, 0xd2, 0xbb,
+       0x6e, 0xa5, 0x94, 0xf6, 0x49, 0xee, 0x8b, 0x76, 0xd4, 0x90, 0x9e, 0xa4,
+       0xdf, 0x49, 0x3b, 0x52, 0x7a, 0x3e, 0x3b, 0xaf, 0xb7, 0x39, 0x27, 0x2c,
+       0xe7, 0xf7, 0xf6, 0xd1, 0xfd, 0xe5, 0x74, 0x4e, 0x10, 0x5f, 0x95, 0xec,
+       0xaf, 0x16, 0xd9, 0x96, 0xf5, 0x33, 0xac, 0x7f, 0xdc, 0x8c, 0xdb, 0xbf,
+       0xf3, 0x43, 0x2b, 0x7d, 0x48, 0x77, 0x84, 0x7f, 0xf0, 0xc6, 0xdb, 0x72,
+       0x6a, 0x3e, 0xc1, 0xfa, 0xbf, 0xf5, 0x01, 0xc5, 0x6b, 0xd8, 0xc5, 0xeb,
+       0xdc, 0x6c, 0xeb, 0xa7, 0xfa, 0xd9, 0x79, 0x69, 0x98, 0xe3, 0x81, 0x7e,
+       0x3e, 0x49, 0xfe, 0xa5, 0xf9, 0xf9, 0x28, 0xed, 0x93, 0xf4, 0xf3, 0xce,
+       0xd0, 0x7b, 0xaf, 0xf8, 0xe5, 0x2f, 0xee, 0x5f, 0xa2, 0x24, 0x2e, 0x91,
+       0xde, 0xc4, 0xb1, 0xfb, 0xa5, 0x32, 0xae, 0xef, 0xbc, 0x78, 0xf5, 0x26,
+       0xe5, 0x4f, 0xa7, 0xf9, 0xce, 0x87, 0xb3, 0xd6, 0xf7, 0xbb, 0x63, 0x0e,
+       0xbe, 0x13, 0xe7, 0xa5, 0xd5, 0x73, 0xaa, 0x71, 0x0b, 0xf8, 0x34, 0x4b,
+       0xbf, 0x3f, 0x39, 0x92, 0xeb, 0x8b, 0x6d, 0xd6, 0xf5, 0x78, 0x51, 0x16,
+       0x70, 0xbf, 0xb3, 0xe6, 0xfb, 0xe1, 0x3c, 0x9d, 0xdb, 0x19, 0xde, 0x99,
+       0x67, 0xe3, 0x02, 0x6f, 0x95, 0x67, 0x0b, 0xf0, 0x7e, 0x46, 0x7d, 0x00,
+       0xfb, 0x2e, 0xd5, 0xfd, 0x64, 0xdf, 0xdd, 0x7d, 0x43, 0xe0, 0xf9, 0xb8,
+       0xdb, 0x0b, 0x7c, 0x9e, 0xec, 0xa2, 0xfc, 0x67, 0xfa, 0x15, 0xde, 0x07,
+       0x92, 0xff, 0x47, 0x88, 0x30, 0xec, 0x6f, 0x98, 0x07, 0xdd, 0x92, 0xfa,
+       0x6d, 0xca, 0x0f, 0x50, 0x7b, 0x78, 0x5f, 0x10, 0x17, 0xb8, 0x14, 0xca,
+       0xe3, 0xc1, 0xdf, 0xac, 0x31, 0xdf, 0x4b, 0x46, 0x9f, 0xa9, 0x33, 0xfb,
+       0x4a, 0x1d, 0xe9, 0x21, 0xfb, 0xfd, 0xd9, 0xbc, 0xdf, 0xd4, 0x9a, 0xfb,
+       0xd6, 0x3b, 0xf1, 0x1e, 0xe3, 0xa3, 0x92, 0xad, 0x99, 0xff, 0x2f, 0x31,
+       0xff, 0xaf, 0x70, 0xf0, 0x0a, 0x7f, 0x67, 0xfd, 0x07, 0x74, 0x15, 0x3e,
+       0xc9, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 usem_int_table_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51,
+       0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0xb7, 0xc9, 0x33, 0x30, 0x98, 0x29, 0x31,
+       0x30, 0x24, 0x2a, 0x33, 0x30, 0x9c, 0x01, 0xe2, 0x24, 0x79, 0x84, 0x1c,
+       0xad, 0xb0, 0x2a, 0x07, 0x65, 0xfa, 0x5f, 0x30, 0x32, 0x30, 0xbc, 0x02,
+       0xe2, 0x37, 0x40, 0xfc, 0x8e, 0x91, 0x74, 0xfd, 0x3f, 0x85, 0x10, 0xec,
+       0x87, 0xbc, 0x0c, 0x0c, 0xbf, 0x80, 0xfc, 0x8d, 0x40, 0x5a, 0x4c, 0x80,
+       0x81, 0xe1, 0x26, 0x90, 0xfd, 0x1b, 0x88, 0xbf, 0x03, 0xf9, 0xe2, 0x7c,
+       0x0c, 0x0c, 0xca, 0x40, 0x6c, 0x06, 0xe4, 0xbb, 0x00, 0xe9, 0x3c, 0x20,
+       0xf6, 0x07, 0xe2, 0x3f, 0x40, 0x7e, 0x1b, 0x1f, 0x6e, 0xf3, 0xff, 0x0a,
+       0xe1, 0xb7, 0xff, 0xaa, 0x00, 0x2a, 0x9f, 0x57, 0x10, 0x95, 0xff, 0x91,
+       0x1f, 0xbf, 0xfe, 0x0e, 0x41, 0xfc, 0xf2, 0xbc, 0x04, 0xec, 0xc7, 0x86,
+       0x4f, 0xa8, 0x91, 0x1f, 0x1f, 0x3c, 0xea, 0xb4, 0x4f, 0x33, 0xd4, 0xc4,
+       0x37, 0x19, 0x50, 0xf9, 0xa7, 0x65, 0x18, 0x18, 0xee, 0xca, 0x32, 0x30,
+       0x28, 0xc8, 0x43, 0xf8, 0xd7, 0x90, 0xe4, 0x8d, 0x80, 0x62, 0x67, 0x64,
+       0x20, 0xec, 0xad, 0x62, 0x0c, 0x0c, 0x7b, 0xe5, 0x18, 0x18, 0x2e, 0x33,
+       0x60, 0x37, 0x77, 0x1b, 0x50, 0x7e, 0x1f, 0x50, 0xde, 0x0e, 0x6a, 0x0e,
+       0x00, 0xb5, 0xbc, 0x7b, 0x1e, 0x68, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 usem_pram_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d,
+       0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x99, 0x57, 0x66,
+       0x26, 0x93, 0x84, 0x84, 0x84, 0xf0, 0x98, 0x24, 0x80, 0x3c, 0x02, 0x0e,
+       0x01, 0x02, 0x48, 0xa8, 0x93, 0x07, 0x14, 0x25, 0xc0, 0x08, 0xa8, 0x68,
+       0x11, 0x06, 0x51, 0x08, 0x8f, 0x3c, 0x44, 0xed, 0x97, 0x6b, 0xdb, 0xcb,
+       0xf0, 0x4a, 0xd1, 0xd2, 0x36, 0xd6, 0xb6, 0xd2, 0x5e, 0xd4, 0x01, 0xe1,
+       0x5e, 0xa4, 0x58, 0x03, 0x44, 0x8d, 0x1a, 0x60, 0x80, 0x60, 0x51, 0xc1,
+       0x06, 0xeb, 0x03, 0xab, 0xd6, 0x00, 0xb6, 0x08, 0x02, 0x19, 0xa0, 0xea,
+       0x48, 0xf1, 0xf7, 0x5f, 0x6b, 0xed, 0x7d, 0x92, 0x73, 0x26, 0x33, 0x40,
+       0x7b, 0xfb, 0xdf, 0xbf, 0xdf, 0xff, 0x8f, 0xb5, 0xdb, 0x7d, 0xce, 0xde,
+       0xfb, 0xec, 0xbd, 0xde, 0x6b, 0xed, 0xb5, 0x77, 0x54, 0x96, 0xce, 0x58,
+       0x1f, 0xc6, 0xbe, 0xc1, 0xdf, 0x8d, 0x8c, 0x3d, 0x20, 0x31, 0x86, 0x8f,
+       0xb4, 0x12, 0x7e, 0xff, 0xeb, 0x9b, 0x0c, 0xc6, 0xa6, 0x5a, 0xe1, 0xbf,
+       0x64, 0xc6, 0xc6, 0xcb, 0x0e, 0xc6, 0x46, 0x30, 0x36, 0xc5, 0xc1, 0x42,
+       0x16, 0x68, 0x33, 0xa5, 0x08, 0x1e, 0x76, 0x63, 0xec, 0xcd, 0x4d, 0x52,
+       0x48, 0xc6, 0x3e, 0xd0, 0x2e, 0x58, 0xc8, 0xd8, 0x22, 0xc6, 0x7f, 0x53,
+       0x15, 0xd6, 0x24, 0x5d, 0xcf, 0xd8, 0x85, 0xd1, 0x3b, 0xeb, 0x86, 0x79,
+       0x18, 0x93, 0x7c, 0x3e, 0x56, 0x5b, 0x00, 0xa5, 0xc7, 0xcd, 0x66, 0x61,
+       0x59, 0xb4, 0xf7, 0x2b, 0xc9, 0xc5, 0x58, 0xf2, 0x68, 0x13, 0x63, 0x03,
+       0x78, 0x9f, 0x6f, 0xe0, 0xdf, 0x14, 0x9f, 0x9d, 0xc6, 0xd2, 0xea, 0x69,
+       0x13, 0x53, 0x0d, 0xf5, 0x74, 0x7f, 0x0f, 0x43, 0xfb, 0xee, 0x33, 0x73,
+       0x0d, 0xef, 0xb3, 0x02, 0x83, 0x0c, 0xef, 0xb3, 0x2b, 0x0a, 0x0c, 0xf5,
+       0x5e, 0x35, 0x37, 0x18, 0xda, 0xf7, 0xa9, 0x2d, 0x31, 0xd4, 0x73, 0x82,
+       0x37, 0x1b, 0xda, 0xe7, 0xad, 0x99, 0x66, 0xa8, 0xf7, 0xab, 0xbf, 0xd3,
+       0xd0, 0xfe, 0xba, 0x75, 0x77, 0x1b, 0xde, 0x0f, 0x0c, 0x2d, 0x32, 0xbc,
+       0x1f, 0xbc, 0x65, 0xa9, 0xa1, 0x3e, 0xa4, 0xe1, 0x21, 0x43, 0xfb, 0xeb,
+       0x9b, 0x56, 0x18, 0xde, 0x0f, 0x0b, 0x3f, 0x62, 0x78, 0x3f, 0xfc, 0xe0,
+       0xcf, 0x0c, 0xf5, 0x91, 0xad, 0xbf, 0x36, 0xb4, 0x1f, 0x75, 0x74, 0xa3,
+       0xe1, 0xfd, 0x98, 0xb6, 0xad, 0x86, 0xf7, 0x63, 0x3f, 0xdd, 0x61, 0xa8,
+       0x8f, 0x8b, 0xbc, 0x6c, 0x68, 0x7f, 0x63, 0x74, 0x9f, 0xa1, 0x5e, 0xcc,
+       0xde, 0x30, 0xb4, 0x2f, 0xb5, 0xfe, 0xc1, 0x50, 0x1f, 0xef, 0xfe, 0xc0,
+       0xd0, 0xfe, 0xdb, 0x99, 0x27, 0x0c, 0xef, 0x6f, 0xf2, 0x7c, 0x66, 0x78,
+       0xaf, 0xd1, 0xc1, 0xa4, 0x01, 0x17, 0x0d, 0xcf, 0x27, 0x7b, 0xff, 0x66,
+       0xe8, 0xa7, 0x30, 0x3f, 0x00, 0x9b, 0x31, 0x33, 0xab, 0xa1, 0xd2, 0xca,
+       0xea, 0xa9, 0xb4, 0xb3, 0x06, 0x2a, 0x1d, 0xac, 0x95, 0xca, 0xef, 0xf6,
+       0x0e, 0xdc, 0x49, 0xf4, 0xf9, 0x64, 0xb0, 0x8e, 0x01, 0xdd, 0xad, 0x0c,
+       0x46, 0xfe, 0x94, 0x06, 0xe5, 0x9b, 0xa3, 0xf3, 0x92, 0x03, 0xf9, 0x38,
+       0x9a, 0x8f, 0x31, 0xa0, 0xdb, 0x29, 0x7c, 0x68, 0x36, 0xc5, 0xea, 0x08,
+       0xcb, 0x40, 0x67, 0x16, 0x2b, 0x0b, 0xda, 0x80, 0x14, 0x5c, 0x51, 0xa0,
+       0xb7, 0x34, 0xa0, 0xbb, 0x28, 0xa3, 0xd2, 0x1d, 0x05, 0x7a, 0x1b, 0x0e,
+       0x74, 0x17, 0xb5, 0x52, 0x99, 0x1a, 0x4d, 0xa5, 0xe7, 0x69, 0x51, 0x37,
+       0x95, 0xdd, 0xa2, 0x3d, 0xe8, 0x79, 0x7a, 0x34, 0x93, 0xca, 0x8c, 0x68,
+       0x2e, 0x95, 0xdd, 0xa3, 0x1e, 0x2a, 0x33, 0xa3, 0x83, 0xa8, 0xcc, 0x8a,
+       0x0e, 0xa0, 0xb2, 0x47, 0xb4, 0x80, 0xfa, 0x65, 0x47, 0xbd, 0x54, 0xf6,
+       0x8c, 0xde, 0x40, 0xcf, 0x7b, 0x45, 0x47, 0x53, 0xd9, 0x3b, 0x5a, 0x42,
+       0xcf, 0xfb, 0x44, 0x7d, 0x54, 0x7a, 0xa2, 0x37, 0x53, 0x99, 0x13, 0x9d,
+       0x48, 0x65, 0x6e, 0x74, 0x1a, 0xb5, 0xcb, 0x8b, 0xfa, 0xa9, 0xec, 0x1b,
+       0xbd, 0x93, 0x9e, 0xf7, 0x8b, 0xce, 0xa4, 0xb2, 0x7f, 0xf4, 0x6e, 0x2a,
+       0xaf, 0x8b, 0x06, 0xa8, 0x1c, 0x10, 0x5d, 0x44, 0xe5, 0xc0, 0x68, 0x05,
+       0x95, 0x83, 0xa2, 0x4b, 0xa9, 0xdf, 0xe0, 0x68, 0x0d, 0x95, 0xf9, 0xd1,
+       0x87, 0xe8, 0xf9, 0x90, 0x68, 0x2d, 0x95, 0x43, 0xa3, 0x2b, 0xa8, 0xbc,
+       0x3e, 0x1a, 0xa4, 0xd2, 0x1b, 0x7d, 0x84, 0xda, 0x0d, 0x8b, 0xae, 0xa1,
+       0xb2, 0x20, 0xfa, 0x33, 0x7a, 0x3e, 0x3c, 0x5a, 0x4f, 0xe5, 0x88, 0xe8,
+       0xaf, 0xe9, 0xf9, 0xc8, 0xe8, 0x3a, 0x2a, 0x0b, 0xa3, 0x1b, 0xa9, 0x1c,
+       0x15, 0x0d, 0x51, 0x39, 0x3a, 0xba, 0x95, 0xca, 0x31, 0xd1, 0x2d, 0x54,
+       0xde, 0x10, 0xdd, 0x41, 0xfd, 0xc6, 0x46, 0x1b, 0xa8, 0x2c, 0x8a, 0xbe,
+       0x4c, 0xcf, 0xc7, 0x45, 0x9b, 0xa8, 0xfc, 0x16, 0xd2, 0x5b, 0x1a, 0xd2,
+       0x5d, 0x98, 0x4a, 0x5f, 0xf4, 0x75, 0x7a, 0x5e, 0x1c, 0x3d, 0x48, 0x65,
+       0x49, 0xf4, 0x2d, 0x7a, 0x5e, 0x1a, 0x6d, 0xa5, 0xb2, 0x2c, 0xfa, 0x47,
+       0x7a, 0x3e, 0x3e, 0x7a, 0x94, 0xca, 0x09, 0xd1, 0xe3, 0x54, 0x7e, 0x3b,
+       0xda, 0x46, 0xe5, 0xc4, 0xe8, 0x69, 0x2a, 0x6f, 0x8a, 0x7e, 0x4a, 0xe5,
+       0xcd, 0xd1, 0x0b, 0xd4, 0x6f, 0x52, 0x34, 0x42, 0x65, 0x79, 0xf4, 0x12,
+       0x3d, 0x9f, 0x1c, 0x8d, 0x52, 0xa9, 0xc9, 0x3b, 0x36, 0x5a, 0x3d, 0xd3,
+       0xa6, 0xd1, 0x5f, 0x2e, 0xfe, 0xff, 0x2c, 0xf7, 0x5f, 0x06, 0x83, 0x5c,
+       0x62, 0x01, 0xd3, 0x37, 0x50, 0x32, 0x07, 0xd0, 0xc1, 0x98, 0xce, 0xf6,
+       0xb1, 0x25, 0x48, 0x3b, 0x92, 0x93, 0x2a, 0xd0, 0x55, 0x12, 0xd0, 0x77,
+       0x0a, 0xc8, 0x42, 0x94, 0x87, 0x53, 0x6a, 0xa4, 0xd0, 0xb7, 0x73, 0x80,
+       0x3e, 0xba, 0xb5, 0xb5, 0x60, 0x5d, 0x1d, 0x6d, 0xf1, 0x58, 0xa0, 0x7e,
+       0x17, 0x8b, 0xa8, 0x48, 0xbf, 0x1f, 0xb1, 0x36, 0x27, 0xca, 0xd3, 0xbd,
+       0x63, 0x4e, 0xf6, 0x6c, 0x03, 0x7a, 0x7d, 0x33, 0x3d, 0xdc, 0x0b, 0x88,
+       0x1b, 0x7f, 0x24, 0x6f, 0x55, 0x9c, 0x53, 0x1e, 0xca, 0xdb, 0x33, 0x4a,
+       0x1b, 0x3c, 0x9f, 0xd2, 0x6d, 0x5f, 0x7a, 0xc0, 0x81, 0xfd, 0x81, 0x37,
+       0x0a, 0x90, 0xbc, 0xe1, 0xfb, 0x48, 0xdf, 0x40, 0x8e, 0x38, 0xce, 0x5d,
+       0x0a, 0x0b, 0xba, 0x60, 0xaa, 0x47, 0x70, 0x84, 0x31, 0xd4, 0x2e, 0x6c,
+       0x81, 0xfa, 0xac, 0x72, 0xe6, 0x2b, 0x80, 0xf6, 0x75, 0x63, 0x2c, 0x33,
+       0x43, 0xf0, 0x9d, 0xba, 0x02, 0x7f, 0x85, 0x1f, 0xca, 0x1f, 0xe7, 0xf8,
+       0x67, 0x62, 0xf9, 0x3a, 0x32, 0x0f, 0xcc, 0x7f, 0xbf, 0x28, 0x8f, 0x30,
+       0x13, 0x95, 0x3f, 0xee, 0xed, 0xa6, 0x72, 0xd6, 0x7d, 0xfd, 0x38, 0x3f,
+       0x95, 0x01, 0x10, 0xb3, 0xae, 0x0e, 0x87, 0xf4, 0x0c, 0xde, 0x8f, 0x39,
+       0x22, 0xbd, 0xfd, 0x43, 0xae, 0xbd, 0x9f, 0xc2, 0xa0, 0xdf, 0xc8, 0xce,
+       0xf6, 0xcf, 0x30, 0xff, 0x3b, 0xf8, 0x3c, 0x58, 0xc2, 0x06, 0xd4, 0x38,
+       0x3a, 0xdb, 0xc1, 0xf3, 0xa3, 0xd8, 0x2e, 0xce, 0xf3, 0x0f, 0xe2, 0x3d,
+       0x6f, 0x30, 0x81, 0x20, 0x00, 0x7d, 0x15, 0x4c, 0x35, 0x87, 0x36, 0xa3,
+       0x7e, 0x62, 0x9e, 0xe4, 0x5b, 0x70, 0x5e, 0x56, 0x4f, 0xf2, 0x34, 0x67,
+       0xe2, 0x79, 0x3d, 0xbc, 0x2c, 0x33, 0x5f, 0xe9, 0xab, 0x9f, 0x67, 0x88,
+       0xe6, 0xf7, 0xb0, 0xc4, 0x66, 0x36, 0xd0, 0xf8, 0xbe, 0xcc, 0x69, 0x43,
+       0x68, 0x7c, 0xc2, 0x77, 0x30, 0xd5, 0x1a, 0xda, 0x9c, 0x43, 0xa8, 0x30,
+       0xd0, 0xcb, 0x5f, 0x11, 0x9e, 0xd0, 0x2f, 0xdf, 0xee, 0x6f, 0xa7, 0xf5,
+       0x41, 0x3f, 0xbf, 0x13, 0xe1, 0xe3, 0xbe, 0x26, 0xb8, 0x40, 0xbf, 0x2f,
+       0x08, 0x9e, 0x0a, 0xf4, 0x1b, 0x72, 0xed, 0xfd, 0x12, 0x97, 0xf5, 0x4c,
+       0xcc, 0xc3, 0x43, 0xe3, 0x89, 0xe7, 0xd5, 0x16, 0x16, 0x94, 0x00, 0x4e,
+       0x91, 0xcd, 0xce, 0xd0, 0xc6, 0x1c, 0x5c, 0x93, 0x87, 0xe4, 0x67, 0x85,
+       0x5b, 0x08, 0xd0, 0x6e, 0x00, 0x0c, 0xd0, 0xeb, 0x15, 0x29, 0x08, 0x42,
+       0xc6, 0x5a, 0x76, 0x27, 0x85, 0x4d, 0xd0, 0xbe, 0x68, 0xb3, 0x73, 0x23,
+       0xda, 0x01, 0xed, 0x25, 0xc1, 0x8c, 0xa9, 0x08, 0x87, 0x8d, 0x2a, 0xdb,
+       0x0c, 0x4d, 0x56, 0xec, 0xfe, 0xd1, 0xbb, 0xff, 0x01, 0xf5, 0xa2, 0x0d,
+       0x2a, 0xb3, 0x40, 0x7d, 0xe1, 0xc5, 0x9f, 0x17, 0x32, 0xa0, 0xa3, 0xeb,
+       0x24, 0x89, 0x7f, 0x3f, 0xe8, 0xdb, 0xdb, 0x17, 0xc6, 0x0f, 0x30, 0xed,
+       0xe7, 0x93, 0x70, 0xfc, 0x05, 0x8c, 0x8f, 0xdf, 0x2e, 0x09, 0xb8, 0x6e,
+       0x4e, 0x26, 0xbc, 0x7d, 0x5a, 0xb6, 0xa9, 0x6e, 0x2c, 0x94, 0x6d, 0xbb,
+       0x2a, 0xcb, 0x19, 0xc8, 0xf1, 0x93, 0x00, 0xd6, 0x2c, 0xa0, 0xef, 0x85,
+       0x76, 0xa6, 0x60, 0x39, 0xab, 0x66, 0xbb, 0x99, 0xe8, 0x34, 0xa8, 0x7e,
+       0xd2, 0xa6, 0xe9, 0x17, 0xe2, 0x67, 0xa5, 0xb3, 0x2e, 0x77, 0xad, 0x2f,
+       0xc0, 0xba, 0xc6, 0xff, 0xb0, 0xee, 0x85, 0x21, 0xb5, 0xb3, 0x0e, 0xff,
+       0x2e, 0xde, 0x62, 0xac, 0xeb, 0xe0, 0x45, 0x76, 0x50, 0xe4, 0xbc, 0x12,
+       0xda, 0x48, 0x74, 0x95, 0xcd, 0xe1, 0xa3, 0xc1, 0xcb, 0x97, 0xcd, 0xe1,
+       0x27, 0xe0, 0x55, 0x76, 0x5e, 0x09, 0x9a, 0xba, 0x11, 0xbc, 0x42, 0x28,
+       0x07, 0x92, 0x25, 0x0f, 0xc1, 0xa1, 0xe2, 0xbc, 0x12, 0x96, 0x61, 0x9c,
+       0x0a, 0x80, 0x23, 0xb2, 0x60, 0xc5, 0xae, 0x87, 0x33, 0x10, 0x4e, 0x8b,
+       0xb7, 0xd8, 0xdc, 0x9f, 0xe8, 0xbe, 0x5b, 0xd9, 0x90, 0x62, 0xa8, 0x57,
+       0x37, 0x65, 0xb9, 0x3f, 0xd1, 0xe9, 0xd1, 0x0b, 0x07, 0x9f, 0x76, 0xe1,
+       0xfa, 0x97, 0x66, 0x9a, 0xdc, 0x9f, 0x80, 0x7c, 0x3b, 0xb3, 0xcc, 0x97,
+       0xf6, 0x09, 0xa0, 0xec, 0xdc, 0xb2, 0x89, 0x54, 0x6a, 0xf4, 0x51, 0xd9,
+       0x90, 0xe3, 0x76, 0x18, 0xc6, 0x31, 0xd6, 0x2f, 0xd4, 0x4b, 0x13, 0x1b,
+       0x48, 0x7f, 0x7a, 0x92, 0x67, 0x0c, 0x49, 0x4c, 0x67, 0x4b, 0x33, 0xcd,
+       0xee, 0x4f, 0x80, 0x55, 0x4f, 0x6f, 0xe1, 0xfa, 0xf6, 0xf4, 0x32, 0xab,
+       0x1b, 0xbf, 0x73, 0x66, 0x99, 0xdb, 0xcd, 0xbf, 0x9b, 0x49, 0xa5, 0x06,
+       0xaf, 0x25, 0xb5, 0x76, 0x6a, 0xaf, 0xcd, 0x2f, 0xd1, 0xb8, 0xff, 0xec,
+       0xf9, 0x31, 0xd6, 0xc8, 0x4e, 0x58, 0x51, 0x9e, 0xc3, 0xbb, 0xbc, 0xc4,
+       0xed, 0x13, 0xf2, 0x93, 0xf2, 0x57, 0x33, 0xf1, 0x49, 0xb3, 0xfa, 0x05,
+       0xd2, 0x8d, 0x15, 0xfe, 0xfd, 0xc6, 0x44, 0x74, 0x44, 0x75, 0x6d, 0xdc,
+       0xea, 0x06, 0x39, 0x68, 0xb9, 0x1e, 0x9f, 0x6f, 0x33, 0x7c, 0x0f, 0xfa,
+       0x79, 0xfe, 0xa2, 0xd3, 0x2f, 0x89, 0xf9, 0x56, 0x61, 0x7f, 0xd1, 0xd1,
+       0xe5, 0xfd, 0x38, 0x00, 0xf1, 0xa9, 0x95, 0xf0, 0x1c, 0x80, 0x11, 0x93,
+       0x61, 0xbc, 0x76, 0xc5, 0xb1, 0x06, 0xed, 0xa8, 0xc9, 0x82, 0x7e, 0xaa,
+       0xb1, 0x1d, 0xc8, 0x83, 0x4a, 0x6b, 0x9b, 0x39, 0x00, 0x8f, 0xce, 0x36,
+       0x72, 0x7c, 0x24, 0xfa, 0xce, 0xe9, 0x65, 0x5b, 0xb2, 0x51, 0xae, 0x55,
+       0x58, 0xeb, 0xcd, 0x28, 0xac, 0x2a, 0x1a, 0x06, 0x96, 0x21, 0x3f, 0x9d,
+       0x6d, 0x5c, 0x99, 0x81, 0xfa, 0x65, 0xb1, 0x7c, 0xe1, 0xbb, 0xfe, 0x38,
+       0xfd, 0x7f, 0xac, 0xf1, 0x6d, 0x48, 0x8d, 0x18, 0xf5, 0x65, 0x48, 0xcc,
+       0x13, 0xc6, 0x35, 0xf0, 0x19, 0x73, 0x74, 0xac, 0x1b, 0xea, 0x67, 0x4c,
+       0xf0, 0x29, 0x47, 0xd7, 0x71, 0x1f, 0x97, 0xb8, 0xde, 0xa9, 0xda, 0x76,
+       0x64, 0xc2, 0x58, 0x98, 0x7f, 0x55, 0xd3, 0x79, 0x33, 0xce, 0x63, 0xb2,
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+       0x05, 0xf0, 0x5d, 0xd5, 0xb8, 0xb0, 0x9c, 0x0d, 0xa5, 0xfa, 0x31, 0x5e,
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+       0xfe, 0xeb, 0x17, 0x19, 0x1e, 0x27, 0xe1, 0x21, 0xdb, 0x84, 0x36, 0x30,
+       0x0b, 0x67, 0x33, 0x28, 0xab, 0x36, 0xfd, 0x79, 0x02, 0xda, 0xd1, 0xd5,
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+       0x28, 0x36, 0x0a, 0xe5, 0x8a, 0x06, 0x07, 0x16, 0x4a, 0x27, 0xb9, 0xbc,
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+       0x90, 0xfd, 0x21, 0x94, 0x03, 0x0a, 0x9b, 0xb8, 0x3d, 0x0e, 0x3f, 0x3c,
+       0x27, 0xf8, 0xe1, 0xe4, 0x46, 0x90, 0x94, 0xb0, 0xbe, 0x93, 0x28, 0x1f,
+       0xd1, 0xce, 0x7d, 0x4b, 0x16, 0xf2, 0xf1, 0x3e, 0xb2, 0x23, 0x1f, 0x14,
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+       0x3e, 0x0f, 0xdd, 0x32, 0x11, 0xdf, 0xff, 0xf5, 0x6d, 0xce, 0x3f, 0xd8,
+       0x0f, 0xf5, 0x0f, 0xcc, 0x2b, 0xdc, 0x9d, 0xde, 0xef, 0x9d, 0x21, 0x91,
+       0x1c, 0xb0, 0xb0, 0x70, 0x3c, 0x7e, 0xde, 0xa4, 0x0a, 0x7e, 0x36, 0xbe,
+       0x07, 0x09, 0x4d, 0xf6, 0x1b, 0xcc, 0x5b, 0x91, 0x92, 0xf5, 0x74, 0x02,
+       0xe3, 0xa7, 0x12, 0xfc, 0xc9, 0x2e, 0x99, 0xff, 0x73, 0xe8, 0xa7, 0xb3,
+       0xa7, 0xab, 0xf1, 0x7b, 0xd4, 0xce, 0xdc, 0xf9, 0x3c, 0xa7, 0x93, 0x6f,
+       0x17, 0x08, 0xfe, 0xdf, 0x8a, 0xfc, 0x9f, 0xd4, 0xc9, 0xff, 0x6c, 0x7d,
+       0xfa, 0x35, 0xf9, 0x67, 0x4b, 0xd4, 0xd0, 0x7f, 0xfe, 0x1a, 0xf9, 0x15,
+       0xf8, 0x33, 0xe8, 0x41, 0x7e, 0x55, 0xfd, 0xb8, 0xee, 0xcf, 0xb6, 0xed,
+       0x7f, 0xf7, 0x4e, 0xa0, 0xeb, 0xcf, 0x1a, 0x34, 0x3e, 0x35, 0xca, 0xcd,
+       0x58, 0x3e, 0xad, 0xd8, 0xf1, 0x20, 0x43, 0xfa, 0x8c, 0xe5, 0xd3, 0xcf,
+       0x7a, 0xd6, 0xb0, 0xb8, 0x7c, 0x0a, 0xcf, 0xe3, 0xf2, 0x69, 0xcf, 0xb6,
+       0xff, 0x11, 0xb9, 0xa9, 0xc1, 0xed, 0x48, 0x0c, 0xdc, 0x40, 0x0e, 0x3e,
+       0xf5, 0xb2, 0x27, 0x31, 0xfc, 0x62, 0xe5, 0x60, 0xb5, 0xc9, 0x13, 0x57,
+       0x0e, 0xc2, 0xef, 0x6d, 0x56, 0xd8, 0x95, 0xee, 0x34, 0x7a, 0xd3, 0xe8,
+       0x6c, 0xd1, 0x6f, 0x2a, 0xfb, 0xa0, 0xbc, 0xe9, 0xa0, 0x47, 0x8d, 0xde,
+       0x3a, 0xe8, 0x51, 0xa3, 0xb7, 0xd8, 0x75, 0x1a, 0xe1, 0x16, 0xfb, 0x7e,
+       0x3d, 0xca, 0x1b, 0x9d, 0x7d, 0xa0, 0xae, 0x60, 0x41, 0x27, 0xe0, 0x39,
+       0xb2, 0x4b, 0x26, 0x3f, 0xb1, 0xdd, 0x13, 0x71, 0xa5, 0xc2, 0x77, 0x57,
+       0xdb, 0xd8, 0x1c, 0xb4, 0xb3, 0xdb, 0xdd, 0xa2, 0x9e, 0xc2, 0xeb, 0x91,
+       0x74, 0x73, 0x1d, 0xca, 0x05, 0xed, 0x79, 0xc4, 0xc6, 0xe3, 0x0d, 0xed,
+       0xfe, 0x88, 0x2b, 0x45, 0x67, 0x3f, 0x1f, 0x6b, 0x96, 0x5d, 0x1e, 0x78,
+       0xdf, 0x16, 0x62, 0x13, 0xe3, 0xd9, 0xd5, 0x20, 0x71, 0xe9, 0xfb, 0x6d,
+       0x2c, 0xd1, 0xfb, 0xe5, 0x04, 0xbf, 0xf1, 0xb2, 0xa3, 0x77, 0xed, 0x08,
+       0xf4, 0xab, 0x64, 0x2f, 0xda, 0x6e, 0xf7, 0x2c, 0xbf, 0xdd, 0x85, 0x21,
+       0x8b, 0xf6, 0xe6, 0xbc, 0xa9, 0x33, 0xe1, 0xf9, 0xbd, 0xaf, 0xc9, 0x14,
+       0xd3, 0x68, 0xb7, 0xbb, 0x86, 0xe2, 0xbc, 0xc0, 0x6f, 0x57, 0xb2, 0x00,
+       0xbe, 0xf3, 0x04, 0x9e, 0x3f, 0x65, 0xc1, 0x5f, 0x16, 0xc1, 0xba, 0xe6,
+       0x35, 0x73, 0xbb, 0xf8, 0x9e, 0xb5, 0x46, 0x78, 0xcc, 0x77, 0x3c, 0x60,
+       0x46, 0x39, 0x03, 0xf6, 0x67, 0x27, 0x1d, 0xe8, 0xe8, 0x45, 0xdb, 0x27,
+       0xa8, 0x58, 0x6f, 0x7c, 0xbf, 0x88, 0xad, 0x25, 0x7c, 0x2d, 0x8a, 0xa1,
+       0x9f, 0x80, 0xf0, 0x77, 0xb2, 0x64, 0x41, 0x3f, 0xc3, 0xd8, 0x30, 0xe1,
+       0x6f, 0x98, 0x70, 0xbc, 0xa5, 0x42, 0x4e, 0x8d, 0x97, 0xf3, 0xa7, 0xce,
+       0x04, 0xb8, 0xb7, 0x1f, 0x94, 0x99, 0x05, 0xea, 0x17, 0x9a, 0x65, 0x56,
+       0x87, 0xeb, 0xdc, 0x26, 0x85, 0x18, 0xf2, 0x71, 0x30, 0x9d, 0xe8, 0xb0,
+       0x0a, 0xe4, 0x03, 0xd3, 0xf9, 0x85, 0x67, 0x90, 0xce, 0xcc, 0x89, 0xf9,
+       0xf7, 0xcc, 0xf3, 0x1f, 0x15, 0x7e, 0x0f, 0x9a, 0x2c, 0x79, 0xe1, 0x83,
+       0xa1, 0xff, 0x01, 0xe5, 0x99, 0x17, 0xde, 0xef, 0xff, 0x0a, 0xd6, 0x5f,
+       0x7c, 0xaf, 0xf7, 0x07, 0xac, 0x6b, 0xfb, 0xd2, 0xdd, 0x5f, 0xcd, 0x46,
+       0xf9, 0xde, 0xbe, 0xdb, 0xc2, 0x28, 0x4e, 0xb2, 0xfb, 0x77, 0xbd, 0xbf,
+       0x87, 0xf5, 0x97, 0x2d, 0x5e, 0x8a, 0x73, 0xac, 0xb0, 0xf0, 0xf8, 0xd4,
+       0x6e, 0x67, 0xa8, 0x1f, 0xbe, 0xef, 0x05, 0xf8, 0x46, 0x7d, 0xb9, 0xeb,
+       0xcb, 0xa1, 0x6d, 0xa4, 0x6f, 0x56, 0x11, 0x9e, 0xca, 0x64, 0xee, 0x47,
+       0x5c, 0x68, 0xfe, 0xdb, 0x9f, 0xa4, 0x6e, 0x58, 0xc2, 0xaa, 0x50, 0x8f,
+       0xee, 0x4e, 0x22, 0xfb, 0xba, 0xfa, 0x65, 0x5b, 0x08, 0x9d, 0xce, 0xf6,
+       0x5d, 0x5f, 0x16, 0x06, 0x1c, 0xff, 0xbc, 0xf5, 0x54, 0x99, 0x59, 0x80,
+       0xe8, 0xcf, 0xc9, 0x66, 0xee, 0x40, 0x7a, 0x4d, 0x01, 0xc4, 0xc1, 0xf7,
+       0xab, 0x5f, 0x19, 0xf3, 0xf4, 0x72, 0xf8, 0x7e, 0x65, 0xe3, 0x5e, 0xf3,
+       0x3c, 0x78, 0x5f, 0xba, 0xe7, 0xeb, 0xa1, 0x28, 0x57, 0xda, 0x77, 0x70,
+       0xfb, 0xe0, 0x9c, 0xda, 0xf6, 0x24, 0xf3, 0x32, 0x36, 0x55, 0xfe, 0xc5,
+       0x72, 0x15, 0xf0, 0x75, 0x0e, 0x6d, 0xb5, 0x1e, 0x20, 0x97, 0xe4, 0x77,
+       0x8b, 0x83, 0x8e, 0x78, 0x70, 0xe1, 0x70, 0x68, 0x07, 0x38, 0xe0, 0xba,
+       0x00, 0x2e, 0x15, 0x28, 0x0f, 0x13, 0xc1, 0x63, 0xfe, 0xbf, 0x2c, 0x3c,
+       0xce, 0xcf, 0xc6, 0xef, 0x2f, 0x69, 0x1e, 0xc5, 0xe4, 0x1c, 0x3d, 0x5c,
+       0x24, 0x1f, 0x7f, 0xee, 0x0c, 0x59, 0x25, 0x5a, 0x3f, 0x7f, 0xbe, 0xfb,
+       0xcb, 0xa1, 0x28, 0x77, 0x3f, 0x6b, 0x58, 0x4e, 0xfa, 0xfb, 0x6a, 0xeb,
+       0x5e, 0x8d, 0xeb, 0x4e, 0xff, 0x7f, 0x69, 0xdd, 0x52, 0xf8, 0x5a, 0xd6,
+       0xbd, 0xe9, 0x5f, 0x76, 0xdd, 0x9c, 0xfe, 0x07, 0xc9, 0x5c, 0x1f, 0xc5,
+       0xf2, 0x41, 0x57, 0x3a, 0x7f, 0xf1, 0xbb, 0x54, 0xff, 0xad, 0xd3, 0x4b,
+       0xf3, 0xbd, 0x46, 0xfe, 0x6f, 0xf9, 0x97, 0x5d, 0xff, 0x3f, 0x88, 0xf7,
+       0x1d, 0x12, 0xed, 0xc7, 0x5d, 0x0d, 0xef, 0x27, 0xfe, 0x65, 0xd7, 0x7d,
+       0x35, 0xbc, 0xbf, 0x26, 0xf0, 0xee, 0x74, 0x63, 0xbc, 0xb7, 0x7d, 0xd7,
+       0xd7, 0xbd, 0x99, 0x6e, 0xfd, 0x57, 0x5b, 0xb7, 0x49, 0xf9, 0x57, 0x95,
+       0x6f, 0x57, 0x5e, 0xb7, 0x66, 0xf7, 0xb4, 0x9a, 0x6a, 0xdc, 0x23, 0x60,
+       0x7e, 0xef, 0xb3, 0xfa, 0x5b, 0x73, 0xa0, 0xfc, 0xbd, 0xef, 0x62, 0x37,
+       0x74, 0x47, 0x81, 0x07, 0xfc, 0xf1, 0xfc, 0x86, 0x02, 0x85, 0xfb, 0x0d,
+       0x16, 0x8c, 0x33, 0x61, 0xc3, 0x5b, 0x25, 0x2d, 0x5e, 0xd4, 0x6a, 0xd8,
+       0xc7, 0xed, 0x59, 0x41, 0x76, 0xc6, 0x14, 0xdf, 0x8f, 0xc9, 0x3e, 0x60,
+       0x4a, 0x4d, 0x6b, 0x31, 0xb4, 0x6f, 0x2d, 0x99, 0xe7, 0x7d, 0x84, 0x5a,
+       0x14, 0x1c, 0x0d, 0x60, 0x7d, 0xc6, 0x38, 0x51, 0x37, 0xfa, 0x53, 0x6f,
+       0x4a, 0xcc, 0x27, 0x81, 0x1d, 0x3b, 0xa5, 0x64, 0xd2, 0x41, 0xb4, 0xef,
+       0xa6, 0xfa, 0x64, 0xb2, 0xff, 0xa0, 0x24, 0xbb, 0xef, 0x9d, 0xde, 0x13,
+       0xf8, 0xf3, 0xd1, 0x46, 0x3f, 0xe2, 0x8e, 0x18, 0x3f, 0xe0, 0xf6, 0x99,
+       0xc6, 0xf7, 0xb7, 0x8a, 0xf1, 0x6e, 0x63, 0x4b, 0xdd, 0x23, 0x00, 0x5e,
+       0xb7, 0xf5, 0x54, 0xdc, 0x21, 0x00, 0xd1, 0x1d, 0xc5, 0x35, 0x2a, 0xae,
+       0xe7, 0x8e, 0xbb, 0x24, 0x56, 0xaf, 0x8b, 0x57, 0xde, 0x1a, 0x33, 0x9e,
+       0x4b, 0x61, 0x22, 0x4e, 0xf2, 0x8f, 0xc1, 0xef, 0x9e, 0x0e, 0xf8, 0x2d,
+       0x25, 0x78, 0xb0, 0x62, 0xd9, 0xbb, 0x99, 0x5d, 0x03, 0xfc, 0x18, 0x87,
+       0x77, 0xeb, 0x8c, 0x61, 0x21, 0x8c, 0xc3, 0x30, 0xc5, 0xcb, 0xe1, 0x77,
+       0x5b, 0xa5, 0x97, 0xe2, 0xa0, 0xc2, 0xcf, 0x54, 0x45, 0x7f, 0xd5, 0xb1,
+       0xa6, 0x15, 0xf9, 0x56, 0x65, 0x46, 0xff, 0x52, 0xf3, 0x13, 0x13, 0xc1,
+       0x99, 0x09, 0xbf, 0x93, 0xc6, 0xc9, 0xed, 0x84, 0xbb, 0xea, 0x93, 0xc9,
+       0xef, 0xd4, 0x8d, 0x47, 0xf0, 0xd0, 0xf0, 0xf1, 0xf7, 0xe2, 0x41, 0xc3,
+       0xdf, 0x7f, 0x17, 0x1f, 0x85, 0x88, 0x8f, 0x38, 0xfb, 0x67, 0x0b, 0xad,
+       0xd6, 0x5b, 0x71, 0xff, 0xc2, 0x3a, 0x40, 0x22, 0xbf, 0x7d, 0xea, 0x5a,
+       0x99, 0xf2, 0x60, 0xac, 0xf9, 0x12, 0xc1, 0xd1, 0x3f, 0x5a, 0xa5, 0xfd,
+       0x9d, 0x3f, 0x9b, 0xfc, 0x85, 0x68, 0x38, 0x97, 0x0f, 0x1f, 0x55, 0xf5,
+       0x10, 0x1f, 0xd6, 0x8b, 0xf0, 0x59, 0x28, 0xe0, 0x38, 0x9f, 0xd5, 0x90,
+       0xdd, 0xc9, 0x2e, 0x7f, 0xf3, 0x4d, 0x11, 0xee, 0x1b, 0x11, 0x84, 0xe0,
+       0xbd, 0x8f, 0xb1, 0xc9, 0xe0, 0x87, 0xcc, 0x2f, 0x92, 0xc2, 0x76, 0x58,
+       0xff, 0x02, 0x85, 0x05, 0x93, 0x0b, 0x30, 0xae, 0x29, 0xb1, 0xe3, 0xfa,
+       0xb8, 0x66, 0xc8, 0x58, 0xc7, 0xdf, 0xb7, 0x32, 0x3a, 0xc7, 0xb9, 0x5a,
+       0xfb, 0x44, 0xf2, 0xe1, 0x9f, 0x5d, 0x7e, 0x0c, 0xf2, 0xe8, 0x78, 0x5f,
+       0xf0, 0x57, 0xb0, 0x54, 0xe8, 0xf3, 0x8a, 0xde, 0x4f, 0x9c, 0xd3, 0xcc,
+       0xe1, 0x58, 0xbd, 0x44, 0x0a, 0xe5, 0x12, 0x1d, 0x85, 0x55, 0xbf, 0x6e,
+       0x5f, 0xe7, 0x7d, 0x41, 0xd7, 0x1f, 0x7f, 0x7f, 0x38, 0xc9, 0xb9, 0xe2,
+       0x9f, 0x0e, 0x49, 0x26, 0xff, 0xd5, 0x37, 0x88, 0xec, 0xfd, 0x6a, 0x61,
+       0xef, 0x5f, 0x08, 0x7a, 0x92, 0x31, 0x5e, 0x73, 0xa1, 0x39, 0x2f, 0x19,
+       0xe3, 0x31, 0x17, 0x0e, 0x96, 0xba, 0xf4, 0x72, 0x51, 0x2b, 0x8f, 0x08,
+       0x3f, 0xf2, 0x0f, 0xcb, 0xac, 0x54, 0xb6, 0x97, 0x49, 0xf5, 0x32, 0xfa,
+       0x5b, 0x2c, 0x32, 0x85, 0xf4, 0x70, 0x99, 0x8d, 0xa1, 0xdc, 0x89, 0xed,
+       0xf7, 0x92, 0xa2, 0xc5, 0x5d, 0x6a, 0xcc, 0x14, 0x97, 0x87, 0x9f, 0x5c,
+       0x88, 0x78, 0xe4, 0xbf, 0x05, 0xd0, 0x35, 0x39, 0x55, 0x87, 0xb7, 0xb5,
+       0x93, 0x4f, 0x29, 0x43, 0xbb, 0xe2, 0x01, 0x7f, 0xc7, 0x75, 0xfb, 0x24,
+       0xff, 0x5d, 0xf8, 0xa2, 0xdf, 0x8a, 0x70, 0x3d, 0x62, 0x6b, 0x9b, 0xe0,
+       0x8f, 0xb3, 0xde, 0x37, 0x04, 0xfc, 0xca, 0xf7, 0x7d, 0x65, 0xc6, 0x38,
+       0xc1, 0xb4, 0xe6, 0x1c, 0x15, 0xe1, 0x32, 0xad, 0x4c, 0x36, 0xe4, 0xdd,
+       0xec, 0x57, 0x84, 0x3f, 0x35, 0x9c, 0x0d, 0xc7, 0x79, 0x95, 0xef, 0xbb,
+       0xc9, 0x35, 0x06, 0xf1, 0x72, 0x50, 0xf6, 0xda, 0x00, 0xbe, 0xd5, 0xcd,
+       0xe7, 0xcd, 0x81, 0x38, 0xfb, 0x6d, 0xb1, 0xf0, 0xc4, 0xf1, 0x31, 0x2e,
+       0x7c, 0x42, 0xf5, 0xce, 0x47, 0x78, 0x9e, 0xf8, 0xb1, 0x8d, 0x05, 0x81,
+       0x1f, 0x0e, 0x8b, 0xfd, 0x1f, 0x78, 0xe5, 0x43, 0xf9, 0x05, 0x43, 0xf9,
+       0x30, 0x3e, 0xf6, 0xb6, 0xc2, 0xf7, 0x15, 0x06, 0xaa, 0x3c, 0x2e, 0x3e,
+       0xbd, 0xbc, 0x58, 0x4d, 0x87, 0xef, 0xe6, 0x37, 0xba, 0x87, 0xa1, 0x8a,
+       0xe9, 0x21, 0xda, 0x0f, 0x54, 0x3d, 0xf4, 0x3e, 0x5b, 0xf4, 0xd3, 0xda,
+       0xf5, 0x58, 0xc2, 0xdb, 0x1d, 0x33, 0xbb, 0xab, 0xe2, 0xad, 0x7f, 0xb2,
+       0x99, 0xaf, 0x7f, 0x01, 0xf3, 0x7e, 0x77, 0xb4, 0xf4, 0xaf, 0x87, 0xb7,
+       0xe2, 0x9f, 0x3a, 0xc3, 0x25, 0xa8, 0xdf, 0xcb, 0x24, 0x92, 0x23, 0x5d,
+       0xe9, 0x9a, 0x11, 0x7f, 0x5c, 0x98, 0x28, 0x85, 0x50, 0xff, 0xa2, 0x1f,
+       0x4b, 0xf5, 0x72, 0x89, 0xf4, 0xff, 0x61, 0x2d, 0xff, 0x60, 0x1a, 0xd7,
+       0x97, 0x1a, 0xdd, 0xc7, 0xc2, 0x59, 0x52, 0x39, 0x9c, 0xb5, 0xef, 0xe7,
+       0xa8, 0x9c, 0x9e, 0xcd, 0x2a, 0x87, 0x8f, 0x06, 0x67, 0x0d, 0xbe, 0xb1,
+       0xf3, 0xd5, 0xda, 0x83, 0xbc, 0xba, 0x51, 0x1f, 0x5f, 0x99, 0xda, 0x34,
+       0xec, 0xb7, 0x68, 0x9f, 0x54, 0x35, 0x4b, 0x6e, 0x0c, 0xfd, 0x55, 0x29,
+       0x6d, 0x66, 0xe4, 0xc3, 0xea, 0xa6, 0x47, 0x55, 0xdc, 0x2f, 0xb8, 0xc3,
+       0xc3, 0xc7, 0x65, 0x8a, 0x7f, 0xa8, 0x7e, 0xbf, 0x76, 0xa0, 0xaa, 0xd0,
+       0x7c, 0xf6, 0x17, 0x8c, 0x25, 0xfb, 0xf1, 0xe2, 0x5a, 0x6e, 0x1f, 0xfb,
+       0xee, 0x39, 0xef, 0x42, 0x3b, 0xe8, 0xb0, 0xc9, 0xfb, 0xfb, 0xb1, 0xc8,
+       0x8f, 0x6f, 0xca, 0x94, 0x4f, 0x90, 0x08, 0x8e, 0x1f, 0x2c, 0xdb, 0x32,
+       0xa3, 0x4c, 0xd1, 0x8f, 0x9b, 0x43, 0xf3, 0x9c, 0xbe, 0xa4, 0x58, 0xc5,
+       0x70, 0xd0, 0x77, 0x96, 0xec, 0x55, 0xbb, 0xeb, 0xe8, 0x69, 0xa0, 0x9a,
+       0x4a, 0xef, 0xb5, 0xe7, 0x3d, 0x96, 0x78, 0x0a, 0xf0, 0x39, 0x7c, 0x8f,
+       0xe6, 0x11, 0xfc, 0x89, 0x85, 0x61, 0x1e, 0x47, 0x7e, 0x43, 0x6b, 0x49,
+       0x12, 0xbc, 0xff, 0x4e, 0x4d, 0x0a, 0xa7, 0xc3, 0x8a, 0x86, 0xbd, 0x66,
+       0xaa, 0xe7, 0x50, 0x7b, 0xed, 0x7b, 0xda, 0x77, 0x62, 0xf9, 0x69, 0x46,
+       0x79, 0x92, 0xa1, 0x3e, 0xaf, 0xb4, 0xad, 0x27, 0xc2, 0xa5, 0xdc, 0x12,
+       0x7e, 0xc0, 0x1b, 0x87, 0x4e, 0x5b, 0x54, 0x6d, 0x9f, 0xe4, 0xef, 0xd4,
+       0x13, 0x3e, 0xa0, 0xdb, 0xa1, 0xff, 0x3f, 0xe8, 0x89, 0xf3, 0x13, 0x7c,
+       0x71, 0xe0, 0xf6, 0x98, 0xda, 0x45, 0x3f, 0x74, 0x8f, 0xa7, 0x1f, 0x96,
+       0x2e, 0xf7, 0x74, 0x47, 0xf8, 0x2f, 0xdd, 0x95, 0xd7, 0x1d, 0x99, 0x63,
+       0xe9, 0x6b, 0xe3, 0x33, 0xe2, 0xe9, 0x87, 0x77, 0x96, 0xf1, 0xfd, 0xc0,
+       0xf7, 0x40, 0x9e, 0x61, 0xd9, 0x3e, 0x03, 0xf4, 0xc3, 0xf5, 0x3a, 0xfd,
+       0x30, 0xc3, 0x46, 0xf4, 0x11, 0xdb, 0xef, 0x07, 0xea, 0x35, 0xea, 0x07,
+       0x0d, 0x5f, 0xff, 0xc3, 0x72, 0xe6, 0x1d, 0xd4, 0x0f, 0x71, 0xf8, 0xba,
+       0x5e, 0x35, 0xea, 0x87, 0xdb, 0x9a, 0xe7, 0x92, 0x7e, 0xb8, 0x6d, 0x86,
+       0xcc, 0x3c, 0xba, 0x78, 0xdc, 0x0f, 0x55, 0xb1, 0xcf, 0x95, 0x50, 0x3f,
+       0x14, 0x67, 0xdc, 0x41, 0x75, 0xd5, 0x9b, 0x14, 0x87, 0x6e, 0xde, 0x11,
+       0x7e, 0x09, 0xc2, 0x15, 0x4b, 0xfc, 0x0e, 0xea, 0x89, 0x3d, 0x42, 0xee,
+       0xc7, 0xea, 0x8b, 0x44, 0xf2, 0x7c, 0x9a, 0x59, 0x12, 0xfb, 0xd5, 0x57,
+       0x91, 0xe7, 0xff, 0x97, 0xe0, 0xac, 0xc9, 0xf3, 0xa5, 0xe0, 0xbf, 0xa0,
+       0x1d, 0xd8, 0x95, 0x0e, 0x19, 0xc9, 0xeb, 0xa5, 0x77, 0x80, 0x3c, 0x97,
+       0x90, 0x1e, 0xb9, 0x3c, 0x5f, 0x7a, 0x97, 0x88, 0x4b, 0xc6, 0xc8, 0x57,
+       0x3f, 0xca, 0xd7, 0x11, 0x7a, 0xf9, 0xca, 0xfb, 0x57, 0x05, 0xb8, 0x3e,
+       0xa8, 0x6e, 0xca, 0x79, 0x7c, 0x16, 0xbc, 0xbf, 0xb3, 0x5e, 0xf5, 0x5a,
+       0xa1, 0xfd, 0x9d, 0x9d, 0xf2, 0xb6, 0x50, 0x2f, 0x6f, 0xf7, 0x08, 0x79,
+       0x0b, 0x70, 0xee, 0xed, 0x8e, 0x83, 0xdf, 0x99, 0xb3, 0x92, 0x98, 0xc7,
+       0x28, 0xaf, 0xfa, 0xa2, 0x9c, 0x3a, 0x31, 0xec, 0x77, 0xf9, 0x3b, 0x91,
+       0xee, 0x0f, 0xcb, 0xb4, 0x8f, 0xf8, 0x67, 0xa1, 0xc7, 0x0f, 0x0d, 0xfb,
+       0xdd, 0x08, 0x8c, 0x9f, 0x77, 0x33, 0x2b, 0x44, 0x3f, 0x7f, 0x16, 0xf2,
+       0xeb, 0xdc, 0xb2, 0xd0, 0x8c, 0x32, 0xe0, 0xe3, 0xd2, 0x7b, 0xb8, 0x3d,
+       0x5c, 0xb9, 0x4d, 0x26, 0x38, 0x54, 0x35, 0x72, 0x3b, 0xaf, 0xaa, 0xaf,
+       0x3d, 0xe4, 0x81, 0xfa, 0x84, 0x82, 0xaf, 0x68, 0x3f, 0x70, 0xf1, 0x2e,
+       0xbe, 0x1f, 0x08, 0x80, 0x2a, 0x2f, 0xd6, 0xe1, 0x71, 0xf1, 0xe1, 0xb6,
+       0xba, 0x6c, 0x7c, 0xbf, 0x41, 0xa2, 0xfd, 0xcc, 0xf9, 0xde, 0xc5, 0x14,
+       0xc7, 0x67, 0xeb, 0x78, 0x9c, 0xd8, 0x0a, 0xff, 0xf0, 0xbc, 0x0e, 0x1f,
+       0xc5, 0x91, 0x2b, 0x05, 0xbc, 0x16, 0x36, 0x6f, 0xa0, 0x78, 0xf3, 0xc2,
+       0x90, 0x31, 0x0e, 0x5d, 0xd9, 0xf7, 0xe6, 0x53, 0xe8, 0x0f, 0x68, 0xf2,
+       0x77, 0xf1, 0x96, 0x98, 0xf7, 0xde, 0x87, 0x69, 0xbf, 0xa2, 0x12, 0xe3,
+       0xcd, 0x3a, 0x3f, 0x44, 0x16, 0xf6, 0xc3, 0xbd, 0x72, 0x38, 0x7f, 0x27,
+       0xe6, 0x76, 0xfe, 0x9e, 0xfb, 0x55, 0xb1, 0xf8, 0xd7, 0xda, 0x75, 0xac,
+       0xbf, 0xe2, 0xbf, 0xb9, 0xfe, 0x23, 0xb0, 0xfe, 0x11, 0xff, 0xfc, 0xf5,
+       0x5f, 0xeb, 0xba, 0x55, 0xb3, 0xe0, 0xf7, 0x02, 0x36, 0x02, 0xf9, 0xe3,
+       0xcf, 0x26, 0x1f, 0xf1, 0x7b, 0xf0, 0x75, 0x58, 0x3f, 0x7c, 0xe7, 0x9e,
+       0x47, 0xfb, 0x75, 0xd7, 0xe7, 0x19, 0xa5, 0x09, 0xbe, 0x3c, 0x6c, 0x0a,
+       0xd4, 0x65, 0x61, 0xbb, 0x2a, 0x89, 0xda, 0x2d, 0x58, 0xbf, 0xfd, 0x40,
+       0x06, 0xd4, 0x67, 0x35, 0xb0, 0x61, 0x18, 0xa6, 0x5f, 0xb0, 0xce, 0xa8,
+       0x17, 0x3b, 0xf4, 0x70, 0xa3, 0x87, 0xf4, 0xec, 0xac, 0x9a, 0xed, 0xd2,
+       0xdd, 0xf9, 0x08, 0x6f, 0x56, 0x83, 0x74, 0x36, 0xaf, 0xc0, 0x12, 0xc0,
+       0xfd, 0xd4, 0x23, 0xb6, 0x08, 0xc9, 0x2f, 0x8d, 0xee, 0xc6, 0x99, 0x39,
+       0x3d, 0x8f, 0x15, 0xdf, 0x3d, 0xd1, 0x23, 0x52, 0x46, 0x7e, 0x44, 0x93,
+       0xe4, 0x26, 0xbe, 0x08, 0xdb, 0xb8, 0x5f, 0x01, 0xf0, 0xb7, 0x41, 0x7d,
+       0xff, 0x98, 0x2f, 0x27, 0x08, 0x78, 0x53, 0x3c, 0xa6, 0xba, 0x89, 0xe3,
+       0xa7, 0x1a, 0xf0, 0x81, 0x7c, 0x35, 0xa1, 0x59, 0xd4, 0xb7, 0x70, 0x3b,
+       0xec, 0x3b, 0xa0, 0x6f, 0x68, 0x3f, 0xac, 0x79, 0xaf, 0x8a, 0xfd, 0x2a,
+       0xa0, 0x7d, 0x1a, 0xc9, 0x9b, 0x41, 0x86, 0x7d, 0x2e, 0xdc, 0x9f, 0x2b,
+       0xce, 0xd0, 0xe1, 0x6d, 0xd7, 0x31, 0x4e, 0xb7, 0x9b, 0x25, 0x2f, 0x8b,
+       0x83, 0xb7, 0x01, 0xf0, 0x4f, 0x5c, 0xbc, 0xfd, 0x93, 0xe8, 0x55, 0x83,
+       0xc7, 0x38, 0xb3, 0xb0, 0xe7, 0x05, 0xfe, 0x8e, 0xd8, 0x5a, 0xcb, 0x87,
+       0xd3, 0x3e, 0x94, 0xe4, 0xdd, 0x88, 0x8d, 0x9b, 0x53, 0x68, 0x1f, 0xe5,
+       0x93, 0xfa, 0x3c, 0xc2, 0xe3, 0x24, 0x41, 0xbf, 0xb1, 0x74, 0x8d, 0xf6,
+       0xbd, 0x47, 0x17, 0x4f, 0xba, 0x05, 0x27, 0x0e, 0xf2, 0x95, 0x4d, 0xb4,
+       0x51, 0x9e, 0x1b, 0x7d, 0x37, 0x97, 0xdb, 0x3f, 0x7a, 0x79, 0x12, 0xeb,
+       0x37, 0x57, 0xb3, 0x56, 0xb2, 0x63, 0x26, 0x4b, 0x81, 0x8f, 0x14, 0x5d,
+       0x5e, 0xdb, 0x6d, 0x22, 0xff, 0x44, 0xdb, 0xa7, 0xd5, 0xb5, 0x7b, 0x5c,
+       0xbd, 0x42, 0x3b, 0x96, 0xe9, 0x36, 0xa1, 0x9c, 0xbc, 0x5f, 0xcb, 0xb7,
+       0xc4, 0xfc, 0xe1, 0x0c, 0xca, 0x5b, 0xa2, 0xdf, 0xfe, 0x5e, 0x85, 0xef,
+       0xcd, 0x82, 0xf5, 0x5e, 0x5c, 0x23, 0x7b, 0x71, 0xff, 0xe7, 0x76, 0x93,
+       0xe7, 0xdd, 0x22, 0xe4, 0xdf, 0x47, 0x54, 0x86, 0x74, 0x79, 0xf1, 0x90,
+       0xea, 0xe3, 0x76, 0x67, 0x12, 0xc9, 0xdd, 0xb9, 0x87, 0x4f, 0xa8, 0x18,
+       0x0a, 0x99, 0x0b, 0x30, 0x41, 0x7c, 0xcf, 0xfd, 0x01, 0x97, 0xaf, 0x27,
+       0x70, 0x30, 0x78, 0xf6, 0x47, 0xd0, 0x5b, 0x3e, 0xdc, 0xab, 0x67, 0x0d,
+       0x23, 0x31, 0x7f, 0x78, 0x86, 0x77, 0xef, 0x78, 0x0f, 0xe0, 0xe5, 0xd6,
+       0x11, 0x47, 0x56, 0xe3, 0x3e, 0xdc, 0xf4, 0x52, 0xf7, 0xbb, 0xef, 0x22,
+       0x7c, 0x1f, 0x96, 0x19, 0xc2, 0xf7, 0xf8, 0x9a, 0x52, 0xf2, 0x4f, 0xee,
+       0xbf, 0x4f, 0x22, 0xba, 0x3e, 0x0a, 0x70, 0xc4, 0xfe, 0xb7, 0xce, 0xc8,
+       0x79, 0xf7, 0x5d, 0xf8, 0xee, 0x5d, 0x6b, 0xd2, 0x69, 0x5f, 0x6d, 0x96,
+       0xef, 0xc0, 0x78, 0xa4, 0xb3, 0x79, 0x53, 0x9d, 0x0e, 0xdc, 0x5f, 0x9b,
+       0x34, 0x40, 0x66, 0x01, 0x1d, 0x1c, 0xef, 0x62, 0xad, 0xab, 0x51, 0x5e,
+       0xcf, 0xaa, 0xb9, 0xef, 0x56, 0x9c, 0x6f, 0x05, 0xe8, 0x01, 0x8c, 0xb3,
+       0x56, 0x34, 0x1f, 0x19, 0xdf, 0x1d, 0xeb, 0xeb, 0x25, 0xaf, 0x07, 0xc6,
+       0xaf, 0x0e, 0x06, 0xcc, 0xdd, 0x01, 0x85, 0xad, 0xeb, 0xce, 0x9b, 0x31,
+       0xde, 0x31, 0x1f, 0xda, 0x21, 0x7a, 0xaa, 0xd7, 0xf3, 0x76, 0xd5, 0x9b,
+       0x24, 0xaf, 0x0d, 0xe9, 0xb1, 0xf9, 0x51, 0x92, 0x3b, 0xf3, 0x37, 0x49,
+       0xcc, 0x8d, 0xed, 0xc1, 0xde, 0xb3, 0xf2, 0x71, 0x43, 0x56, 0x18, 0xb7,
+       0x75, 0x3d, 0xf4, 0x87, 0xfa, 0x02, 0xec, 0x8f, 0xe3, 0x6e, 0x4a, 0xb9,
+       0x0d, 0xf7, 0xd1, 0xaa, 0x0f, 0xc9, 0xbc, 0xff, 0xe8, 0xe5, 0xaf, 0xa2,
+       0x5c, 0x9a, 0x0f, 0xfd, 0xe0, 0x35, 0x6b, 0xdd, 0x74, 0x1f, 0x8d, 0xb7,
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+       0xe5, 0xe1, 0x21, 0xbe, 0xca, 0x3d, 0xa8, 0xe7, 0x3f, 0xef, 0x8d, 0x71,
+       0xcb, 0x4f, 0xd5, 0x08, 0xc5, 0x03, 0x23, 0xbb, 0x2c, 0x6e, 0xcc, 0xdb,
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+       0x26, 0xf2, 0x67, 0xcf, 0xb1, 0x8e, 0x1f, 0xcf, 0x77, 0x14, 0x31, 0x89,
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+       0xef, 0x58, 0x72, 0xc5, 0xb9, 0x0b, 0x9e, 0x17, 0x57, 0xe9, 0x69, 0x35,
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+       0x39, 0xc2, 0x2f, 0xd1, 0xf2, 0xc8, 0xb4, 0xf9, 0xd6, 0x35, 0x70, 0xbd,
+       0x7b, 0x66, 0x0b, 0xb7, 0x0b, 0x63, 0xf9, 0xb9, 0x4a, 0xc4, 0xdb, 0x63,
+       0xbf, 0xf3, 0x95, 0xf8, 0x4e, 0x55, 0xd3, 0xde, 0xa1, 0x28, 0x77, 0xce,
+       0xec, 0x7b, 0x49, 0xd0, 0x1b, 0xa7, 0xe7, 0xaa, 0x6d, 0xc7, 0xcc, 0x41,
+       0x21, 0x9f, 0x43, 0x7a, 0xf9, 0x8c, 0xe3, 0xc5, 0x91, 0x27, 0xb2, 0x95,
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+       0x69, 0xc5, 0x77, 0x3b, 0xce, 0xff, 0x74, 0x2b, 0xb7, 0x33, 0x4e, 0x37,
+       0xc8, 0x13, 0x43, 0x71, 0xc6, 0x3f, 0x2b, 0xf4, 0x4f, 0xc7, 0xba, 0x9d,
+       0x66, 0xf2, 0xab, 0x64, 0x97, 0x9d, 0xe4, 0xcf, 0x03, 0xce, 0xd1, 0x47,
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+       0x8f, 0x40, 0xff, 0x49, 0x9b, 0xaf, 0xf6, 0xde, 0xdc, 0xcd, 0xc4, 0x42,
+       0x7a, 0xfc, 0x2b, 0xc1, 0x9e, 0x18, 0x77, 0x9d, 0x92, 0xfb, 0xa5, 0x82,
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+       0xe3, 0xb5, 0x96, 0x49, 0x5e, 0xb4, 0x67, 0xbb, 0xd2, 0x99, 0x71, 0xfc,
+       0x5b, 0x7c, 0xb2, 0x21, 0x1e, 0x86, 0xb1, 0x67, 0x5c, 0xd7, 0x05, 0xaf,
+       0x89, 0xf0, 0xe9, 0x34, 0x85, 0xdd, 0xd0, 0x84, 0x39, 0x6d, 0xad, 0x99,
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+       0x64, 0xd9, 0x96, 0x5e, 0x78, 0xce, 0xca, 0xc5, 0xbc, 0x12, 0xbe, 0x77,
+       0x7a, 0x3b, 0xce, 0xb7, 0xd0, 0x78, 0xc9, 0x2c, 0x36, 0xcf, 0x9a, 0xbd,
+       0xdd, 0xb7, 0x90, 0x89, 0x23, 0xc0, 0xf8, 0xde, 0xbd, 0x17, 0xe3, 0x12,
+       0xf6, 0x01, 0x6c, 0x00, 0x9e, 0xdf, 0x71, 0x33, 0xbb, 0x17, 0xef, 0x57,
+       0x78, 0x4c, 0x9c, 0x7b, 0x5c, 0xeb, 0x0c, 0x90, 0xbe, 0x4d, 0xc8, 0x37,
+       0x5e, 0x7e, 0xee, 0x45, 0x8b, 0x13, 0x25, 0x8f, 0x56, 0x0c, 0xe7, 0x62,
+       0x52, 0x7c, 0xc6, 0x7a, 0x5a, 0xcc, 0x39, 0x48, 0x4d, 0x5e, 0xd3, 0x11,
+       0x3a, 0x80, 0xff, 0x04, 0x71, 0xef, 0x43, 0xca, 0x78, 0xbe, 0x7e, 0x8c,
+       0x57, 0xf5, 0xcb, 0xe8, 0x9c, 0x6f, 0x4a, 0x3a, 0xf3, 0x86, 0xf1, 0xfd,
+       0x64, 0x07, 0xe5, 0x33, 0x3b, 0x1c, 0x7c, 0x7e, 0xda, 0x7c, 0x61, 0x3e,
+       0x24, 0x0f, 0x00, 0x4c, 0x7c, 0x3e, 0xf9, 0x6d, 0x41, 0xb4, 0xc3, 0x61,
+       0x5e, 0x31, 0x7c, 0xcc, 0xe8, 0xdc, 0x13, 0xcc, 0xef, 0x78, 0xcc, 0xfc,
+       0x0c, 0x76, 0xdc, 0x1d, 0x56, 0xa1, 0x1f, 0x14, 0xa6, 0xa0, 0x1c, 0x71,
+       0x58, 0x5b, 0x99, 0x80, 0xf3, 0x05, 0x63, 0x9e, 0x69, 0x90, 0x61, 0xde,
+       0x41, 0x72, 0x07, 0x5c, 0xe1, 0x3d, 0x8c, 0x93, 0x23, 0x4d, 0xb5, 0x60,
+       0xde, 0x82, 0x1b, 0xbd, 0xe0, 0x3c, 0xfa, 0x5e, 0x4c, 0xbf, 0x9e, 0x6e,
+       0xfd, 0x79, 0xb1, 0xeb, 0x85, 0xde, 0x28, 0xca, 0x64, 0xf9, 0x74, 0xae,
+       0xb0, 0xb9, 0x1b, 0xc9, 0xad, 0xdc, 0xda, 0x12, 0x76, 0x02, 0xea, 0x52,
+       0x3d, 0xa7, 0x8f, 0xbe, 0x6b, 0x19, 0xd1, 0x7d, 0xdf, 0x88, 0xc8, 0x63,
+       0x59, 0x65, 0x27, 0x7b, 0x4c, 0xbb, 0x77, 0x40, 0x52, 0x58, 0x50, 0x2d,
+       0xe8, 0xa4, 0x37, 0x80, 0xc8, 0x0a, 0x3c, 0x17, 0xaa, 0xac, 0x01, 0x9a,
+       0x81, 0x7e, 0xcd, 0x91, 0x12, 0xd3, 0xbd, 0x00, 0xd4, 0x06, 0x7c, 0x05,
+       0xe3, 0xdf, 0x6b, 0xf5, 0x3d, 0x68, 0x85, 0x76, 0x75, 0xb7, 0x04, 0x32,
+       0x4d, 0xc3, 0x70, 0x39, 0xc5, 0xab, 0x5a, 0x8a, 0xe8, 0x14, 0xef, 0x40,
+       0x8c, 0x30, 0x99, 0x96, 0xfb, 0x5a, 0x0e, 0xf6, 0x22, 0x51, 0xc3, 0xd8,
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+       0x14, 0x76, 0x48, 0xac, 0x7d, 0xde, 0x69, 0x97, 0xd7, 0xc7, 0xf5, 0xe7,
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+       0x17, 0xf4, 0xf4, 0x19, 0xfb, 0xfd, 0x84, 0xe3, 0xc6, 0xf4, 0x5b, 0x25,
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+       0xfa, 0x85, 0x81, 0x4c, 0xd5, 0x8b, 0xe1, 0x81, 0x92, 0xd5, 0x56, 0xf0,
+       0x73, 0xea, 0x72, 0x98, 0x8d, 0x81, 0x9f, 0xb3, 0xc2, 0x5e, 0x32, 0x7e,
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+       0xfe, 0x46, 0xc0, 0xc3, 0x65, 0x90, 0x50, 0x76, 0x9d, 0xdf, 0x72, 0x99,
+       0x95, 0x51, 0x9d, 0xf5, 0xcc, 0x30, 0x9c, 0x0f, 0xfe, 0x88, 0xed, 0xcd,
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+       0x15, 0xf4, 0x37, 0x0b, 0xef, 0x8d, 0x1c, 0x8e, 0xed, 0xc2, 0xd9, 0x78,
+       0x7f, 0xcb, 0x2c, 0x25, 0xac, 0x52, 0x7e, 0x46, 0xd4, 0xcc, 0xef, 0x39,
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+       0xb5, 0xd3, 0xce, 0xed, 0xf8, 0x59, 0xe2, 0xde, 0xc9, 0x66, 0x5b, 0xec,
+       0x38, 0x0a, 0x1f, 0x5f, 0xdc, 0x33, 0x17, 0x0b, 0xf7, 0x34, 0x7b, 0xe9,
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+       0x4a, 0xf7, 0xbc, 0x2c, 0x79, 0x5e, 0xa6, 0x7b, 0x0a, 0xe0, 0xbb, 0x19,
+       0xdf, 0xa1, 0xfe, 0xf3, 0x0a, 0xf9, 0x39, 0x2b, 0x7e, 0x4e, 0x48, 0xd3,
+       0xcb, 0x05, 0x5f, 0xef, 0xcf, 0xf6, 0xf3, 0xe0, 0x20, 0x9d, 0xfb, 0xd1,
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+       0x01, 0x7a, 0xdb, 0x70, 0xef, 0xcf, 0x8d, 0xe2, 0xde, 0x9f, 0x58, 0x7b,
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+       0x3b, 0x89, 0xf8, 0xbf, 0x28, 0x9a, 0xca, 0x42, 0x3a, 0xf9, 0x50, 0xa4,
+       0x84, 0x65, 0x9c, 0x7f, 0x51, 0x34, 0x83, 0x85, 0x00, 0xbe, 0x67, 0x0f,
+       0xe6, 0x3e, 0x56, 0x8e, 0xf4, 0xca, 0x54, 0x6f, 0x3f, 0x1c, 0x56, 0x61,
+       0x2d, 0x64, 0x0f, 0x8b, 0xfd, 0x1b, 0xf8, 0xb5, 0xe0, 0xfd, 0x74, 0xbb,
+       0x45, 0x65, 0x4f, 0xe3, 0xc5, 0xe9, 0x63, 0x89, 0xf9, 0xdc, 0xab, 0x06,
+       0x43, 0x9b, 0x6f, 0x85, 0x03, 0xdd, 0xc8, 0x3e, 0xc6, 0x10, 0x68, 0x61,
+       0xa7, 0xdd, 0x77, 0x63, 0xd4, 0x18, 0x57, 0x8d, 0xb5, 0x93, 0x4b, 0x9a,
+       0x87, 0xad, 0x42, 0x93, 0xf2, 0x0c, 0x3e, 0x40, 0xfa, 0x8b, 0xf0, 0x7b,
+       0x91, 0xba, 0xd8, 0xcf, 0x91, 0x09, 0x71, 0xed, 0x66, 0xc6, 0x1e, 0x25,
+       0x38, 0x14, 0x3c, 0x9f, 0x37, 0x09, 0xef, 0x7b, 0x29, 0x78, 0xcd, 0xe4,
+       0xc6, 0xef, 0xee, 0x41, 0xbe, 0xc6, 0x78, 0x7e, 0xe3, 0x45, 0xba, 0x8f,
+       0xa4, 0x8a, 0x85, 0x6f, 0xc3, 0xf7, 0x55, 0x8d, 0xb2, 0x3b, 0xcc, 0xae,
+       0x14, 0xcf, 0x5a, 0xf5, 0xc6, 0x8d, 0x30, 0x8f, 0x3d, 0x11, 0xc5, 0x83,
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+       0x0e, 0x17, 0x0d, 0x46, 0xbe, 0x6d, 0x8e, 0x28, 0x14, 0xff, 0x2f, 0x3a,
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+       0x7b, 0x2e, 0xef, 0xa3, 0xe7, 0xda, 0xb8, 0xcd, 0x91, 0xd4, 0xc1, 0xa8,
+       0x8f, 0xb7, 0x9b, 0xb8, 0x3f, 0xdd, 0xf2, 0xea, 0xa5, 0x24, 0x94, 0xa7,
+       0x7b, 0x2e, 0x5f, 0x48, 0xe3, 0xf7, 0x0f, 0x2d, 0xd7, 0xee, 0x05, 0x8a,
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+       0x37, 0xcd, 0x95, 0x4d, 0xf0, 0xdd, 0x57, 0x98, 0x87, 0xc7, 0xf3, 0xde,
+       0x36, 0xd1, 0x7c, 0x3b, 0xe2, 0x9f, 0x60, 0x07, 0xe2, 0x7a, 0x7f, 0x20,
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+       0x95, 0x49, 0x2a, 0xbd, 0x9f, 0x97, 0xc4, 0xe3, 0x69, 0x3b, 0x0e, 0x96,
+       0xa4, 0x61, 0xfe, 0xe9, 0x1e, 0x7b, 0x60, 0x3e, 0xc2, 0xb3, 0xfa, 0x93,
+       0xb6, 0x3a, 0x97, 0xa7, 0x33, 0xfe, 0xa7, 0xd9, 0x81, 0x63, 0xde, 0xde,
+       0x31, 0x69, 0x08, 0xfc, 0xe7, 0x98, 0x33, 0x26, 0x37, 0xa2, 0xcf, 0xf3,
+       0xf6, 0x46, 0x19, 0xd7, 0xeb, 0xf9, 0x94, 0xb1, 0x14, 0xa9, 0x6b, 0x7c,
+       0x0a, 0xc6, 0xab, 0x41, 0x3c, 0x68, 0xe3, 0xbd, 0x72, 0x86, 0x8f, 0x07,
+       0xf3, 0xd8, 0x87, 0xfc, 0x16, 0x59, 0xce, 0xdc, 0x94, 0x97, 0xc9, 0xfc,
+       0x3f, 0xca, 0x87, 0xfa, 0x2b, 0xad, 0x4a, 0x2a, 0xe6, 0x2d, 0x6d, 0x15,
+       0xfb, 0xaa, 0x1a, 0x1e, 0xb4, 0xf5, 0x68, 0xf3, 0xf0, 0x34, 0x30, 0xdf,
+       0x06, 0x07, 0xb1, 0x86, 0x6f, 0xc7, 0x95, 0xe2, 0xcc, 0x22, 0x3f, 0x72,
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+       0xfb, 0xd3, 0x03, 0x76, 0xb2, 0xbb, 0x76, 0x8a, 0x78, 0x35, 0xcb, 0x9c,
+       0xdb, 0x07, 0xe1, 0xa7, 0xe1, 0x69, 0xbd, 0x28, 0x63, 0xe7, 0x93, 0xe8,
+       0xfb, 0x8f, 0x27, 0x71, 0xbd, 0xa1, 0x95, 0x5b, 0x55, 0x4f, 0x90, 0xe8,
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+       0xe5, 0x51, 0xdd, 0x13, 0x0c, 0x26, 0x0d, 0xc5, 0x3c, 0xa8, 0xa6, 0x7e,
+       0x5e, 0xdc, 0xef, 0xc3, 0xfc, 0xcf, 0x24, 0xdd, 0x3e, 0xeb, 0x38, 0x41,
+       0xe7, 0x9e, 0x86, 0x88, 0x39, 0x47, 0x87, 0x87, 0xc4, 0x72, 0x8d, 0xc3,
+       0xbd, 0x83, 0x7e, 0x94, 0x06, 0xa2, 0xab, 0xa6, 0xa3, 0x8c, 0xf8, 0x6d,
+       0xd1, 0x96, 0xfb, 0x78, 0x7c, 0x11, 0xe4, 0x81, 0xb8, 0xcf, 0x89, 0xf6,
+       0x8f, 0x91, 0x2f, 0xc4, 0x3e, 0x72, 0x96, 0xc4, 0x4b, 0x17, 0xf2, 0xc9,
+       0x98, 0xe6, 0x0d, 0x2b, 0xb3, 0x3d, 0x74, 0xbe, 0x80, 0xf6, 0x6d, 0x35,
+       0x38, 0x78, 0x90, 0x2f, 0xa0, 0xdc, 0x2d, 0xf0, 0x82, 0x70, 0xc1, 0xf7,
+       0x2f, 0x89, 0x75, 0x6b, 0xef, 0x5f, 0x14, 0xf0, 0x1b, 0x2f, 0xe7, 0x27,
+       0xeb, 0xf3, 0x11, 0x63, 0xcb, 0x3d, 0xcb, 0x32, 0x29, 0xa6, 0xa8, 0xd5,
+       0x5f, 0x12, 0xf3, 0x5f, 0xc8, 0x1e, 0x25, 0x3b, 0x74, 0xe1, 0xe5, 0x7a,
+       0xb2, 0x4f, 0x3d, 0x35, 0xbc, 0x5c, 0xf8, 0x00, 0x2f, 0xfb, 0xaf, 0x9f,
+       0x6b, 0xc6, 0xf8, 0xef, 0xc2, 0x75, 0xf1, 0xef, 0xad, 0x1b, 0x95, 0xc4,
+       0xed, 0x97, 0xb3, 0x82, 0x0f, 0x98, 0xc9, 0xde, 0x03, 0xf3, 0x39, 0x3a,
+       0xf4, 0x63, 0x12, 0xd7, 0xaf, 0xa7, 0x1a, 0x1f, 0xdb, 0x9f, 0x4d, 0xfa,
+       0x24, 0xf0, 0x2a, 0xd2, 0xc7, 0x0d, 0x4d, 0x8f, 0xfe, 0x12, 0xc1, 0xa4,
+       0xd1, 0xff, 0xa9, 0x4d, 0x2a, 0xf5, 0xd7, 0xe4, 0x88, 0xd6, 0xff, 0x0d,
+       0x31, 0xfe, 0xf3, 0x6f, 0x73, 0xfe, 0x19, 0xb3, 0x49, 0x2d, 0xc1, 0x7b,
+       0x8c, 0xc6, 0x04, 0x99, 0x1b, 0xe3, 0xe4, 0xaf, 0x6c, 0xda, 0x2c, 0xa3,
+       0x5c, 0x7f, 0x05, 0xf9, 0x23, 0x87, 0xcb, 0x0d, 0xd4, 0xc7, 0x9f, 0x1e,
+       0x78, 0x24, 0xe9, 0x21, 0xa4, 0x83, 0x63, 0x26, 0x86, 0xf1, 0xf8, 0x9d,
+       0x66, 0x56, 0xb1, 0x5d, 0x87, 0xdf, 0x96, 0x0d, 0x2f, 0x1a, 0xe4, 0xc1,
+       0xa2, 0x2d, 0xcb, 0x27, 0xe1, 0x38, 0xa3, 0xda, 0x52, 0x25, 0x94, 0xff,
+       0x9a, 0x1c, 0xd0, 0xf0, 0xbd, 0xd3, 0xec, 0xbd, 0x89, 0xe4, 0xc9, 0x94,
+       0x18, 0x79, 0x52, 0xc6, 0xfb, 0x47, 0x05, 0x3c, 0x1f, 0x13, 0xf2, 0xe4,
+       0xb1, 0x89, 0x20, 0x4f, 0xe0, 0x51, 0xca, 0xa6, 0x14, 0x09, 0xc7, 0xd9,
+       0x69, 0x8e, 0x7f, 0xaf, 0xd5, 0x67, 0x1a, 0xdf, 0x09, 0x7a, 0x1c, 0xdb,
+       0x29, 0x77, 0x3f, 0xe3, 0x72, 0xb7, 0xcd, 0x95, 0x07, 0xe3, 0x54, 0x4d,
+       0xbe, 0x40, 0xf1, 0xd7, 0x8e, 0xef, 0x08, 0xba, 0x7b, 0xac, 0x4c, 0xa3,
+       0xbb, 0x1c, 0x09, 0xe1, 0x08, 0xf6, 0xbc, 0xa9, 0x2f, 0xae, 0x1b, 0xe0,
+       0x83, 0xf4, 0x0f, 0xf6, 0xfc, 0x9c, 0x69, 0xf9, 0xc4, 0xa5, 0x07, 0x15,
+       0xda, 0xf7, 0x11, 0xfb, 0x48, 0x22, 0x6f, 0x82, 0x38, 0x4c, 0xc7, 0xbf,
+       0x9a, 0x9c, 0xfb, 0xda, 0x1e, 0xf8, 0x1b, 0xf2, 0x49, 0x61, 0x59, 0xcd,
+       0x4a, 0xf4, 0x33, 0xd2, 0xca, 0x83, 0x44, 0xd7, 0xa7, 0xa4, 0x40, 0x9f,
+       0x54, 0xd0, 0x57, 0xa7, 0x90, 0xaf, 0xe3, 0xc8, 0x85, 0xe3, 0x62, 0x3d,
+       0x5f, 0xa8, 0x81, 0x3e, 0xee, 0x38, 0xef, 0x3b, 0xf9, 0x88, 0xf5, 0x40,
+       0x3e, 0xa8, 0x60, 0x01, 0x13, 0xae, 0x83, 0xad, 0x97, 0xdc, 0xfa, 0xf3,
+       0x0f, 0x9e, 0xf5, 0x9c, 0xde, 0x52, 0x1c, 0x92, 0x21, 0x7f, 0x5c, 0xab,
+       0x6b, 0xf0, 0xba, 0x91, 0x75, 0xdc, 0x33, 0x98, 0xe2, 0x48, 0x27, 0x3d,
+       0x65, 0xc6, 0xbc, 0xca, 0xfe, 0x21, 0xae, 0xa7, 0x98, 0x54, 0x42, 0xf4,
+       0xc8, 0x4c, 0x37, 0xf7, 0x40, 0x7e, 0x3b, 0xa5, 0x32, 0xa2, 0x9f, 0x53,
+       0x20, 0x17, 0x11, 0x6e, 0x0b, 0xed, 0x46, 0x3f, 0x44, 0x5b, 0x57, 0x4f,
+       0x07, 0xe7, 0xab, 0x2f, 0x52, 0xf8, 0x3a, 0xfe, 0x28, 0xf8, 0x8e, 0x7c,
+       0xdc, 0x91, 0xd4, 0x8e, 0xdb, 0x59, 0xc5, 0x26, 0xda, 0x87, 0x45, 0xfa,
+       0x20, 0x7a, 0x9b, 0x92, 0x4a, 0x7e, 0x0a, 0x38, 0x46, 0x0a, 0xf1, 0x79,
+       0xc7, 0x3e, 0x43, 0x58, 0x96, 0xb8, 0x3c, 0x90, 0x71, 0x1e, 0x6e, 0xf4,
+       0xdf, 0x28, 0x0e, 0xb4, 0x81, 0xe7, 0x85, 0x6d, 0xdb, 0x40, 0x74, 0x93,
+       0x32, 0xd1, 0x4d, 0xe7, 0x19, 0x1e, 0x53, 0xbc, 0xb6, 0x14, 0x5d, 0x1c,
+       0xb7, 0x65, 0xf3, 0xe3, 0xe4, 0x37, 0x22, 0x3d, 0xe1, 0x1c, 0x12, 0xd1,
+       0x63, 0x05, 0xd2, 0x23, 0x8b, 0x43, 0x87, 0x21, 0xa0, 0x43, 0xe8, 0x97,
+       0x3a, 0xb1, 0x86, 0xf0, 0x08, 0xf8, 0x1d, 0xe5, 0x80, 0x71, 0x53, 0xca,
+       0x02, 0x32, 0xd2, 0x4d, 0x2c, 0x7e, 0xb5, 0xfd, 0x43, 0x0d, 0x1e, 0x3b,
+       0x63, 0xf6, 0x1b, 0xbf, 0xe7, 0xe0, 0x7c, 0x39, 0x51, 0x94, 0x9e, 0x04,
+       0x79, 0x27, 0x9d, 0x7a, 0xc2, 0x28, 0x6f, 0x01, 0x5f, 0xdf, 0xe6, 0xf8,
+       0xea, 0xa4, 0x6f, 0xc4, 0x9b, 0xc6, 0x6f, 0xc3, 0x1d, 0x57, 0xa6, 0xf3,
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+       0x99, 0xb4, 0x7d, 0x63, 0xed, 0xfb, 0x77, 0x08, 0x7a, 0x49, 0xb4, 0x4f,
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+       0xef, 0xff, 0x84, 0x7e, 0x39, 0x94, 0x77, 0x3d, 0x70, 0x4c, 0xea, 0x4e,
+       0x70, 0x77, 0x53, 0xda, 0xef, 0x1c, 0xd1, 0xaf, 0xd7, 0xf7, 0x8f, 0x90,
+       0xff, 0xd8, 0xab, 0xa6, 0x95, 0xec, 0xf7, 0xd9, 0xb5, 0x7b, 0x25, 0xd4,
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+       0x7a, 0xc9, 0x64, 0x8d, 0xbc, 0x86, 0xfb, 0xdb, 0x95, 0xcd, 0xb2, 0x07,
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+       0x71, 0x7f, 0x33, 0xcf, 0xe7, 0x7b, 0xaa, 0x8e, 0xe7, 0x6d, 0x6b, 0xdf,
+       0x3d, 0xf7, 0x7c, 0x32, 0xed, 0xef, 0x9c, 0x13, 0xfb, 0x7c, 0xcc, 0x77,
+       0x29, 0x63, 0x1a, 0xed, 0x7b, 0x5f, 0xca, 0xc0, 0xf3, 0x45, 0x1f, 0x3b,
+       0x02, 0x6f, 0xe8, 0xe5, 0xe0, 0x53, 0xcd, 0x9f, 0xdb, 0x50, 0x5f, 0x0c,
+       0xd6, 0xf2, 0x64, 0x63, 0xf4, 0x0b, 0x0a, 0x5e, 0x3c, 0xaf, 0x42, 0x67,
+       0x1f, 0x25, 0xb4, 0x7b, 0x86, 0xad, 0x91, 0x71, 0x1d, 0xb7, 0x05, 0x86,
+       0x63, 0x4a, 0x1b, 0xf0, 0xf7, 0x3b, 0x9c, 0x3e, 0xb9, 0x1e, 0xfa, 0xcd,
+       0xb6, 0x12, 0x93, 0xfe, 0x9e, 0x8e, 0x8b, 0x4d, 0x7f, 0x9d, 0xbd, 0xcf,
+       0xd3, 0xb9, 0x6f, 0xa4, 0xed, 0x2b, 0x69, 0xef, 0xb5, 0x7d, 0x27, 0x49,
+       0x0a, 0x7c, 0xac, 0x97, 0xeb, 0xb1, 0xfb, 0x4a, 0xb1, 0xfb, 0x21, 0xb2,
+       0xcb, 0x4a, 0x79, 0xd6, 0x5e, 0xd9, 0xee, 0x95, 0x8d, 0x7a, 0x95, 0xe8,
+       0x6e, 0x65, 0x3f, 0xae, 0x37, 0x57, 0xee, 0xb5, 0x13, 0xdc, 0x56, 0xf6,
+       0x73, 0xd0, 0xfe, 0x2d, 0xcc, 0xf7, 0x0c, 0xce, 0xb7, 0x05, 0xf4, 0x16,
+       0x9e, 0xc3, 0xbb, 0x78, 0xd4, 0x41, 0xed, 0xb4, 0xf9, 0xc3, 0x7c, 0x87,
+       0x1e, 0xd2, 0xcd, 0xb7, 0xda, 0x14, 0x99, 0xbd, 0x4f, 0x8a, 0x3b, 0xdf,
+       0xcf, 0xf5, 0x70, 0xec, 0x3a, 0x5f, 0x63, 0x3e, 0xb2, 0x36, 0x3f, 0xd9,
+       0xa9, 0xd0, 0xbc, 0xdb, 0x99, 0xdd, 0x8b, 0x78, 0x6b, 0x30, 0xf3, 0xfb,
+       0xdb, 0x82, 0x6f, 0xda, 0x29, 0x1e, 0xda, 0xee, 0xbb, 0x64, 0xc3, 0x7b,
+       0x83, 0xdb, 0xd9, 0x25, 0x1b, 0xc6, 0x69, 0x4f, 0x3b, 0x02, 0x92, 0x0b,
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+       0xd2, 0x7f, 0xa2, 0x7d, 0xbe, 0x41, 0xce, 0x12, 0x15, 0xdb, 0xc3, 0x3a,
+       0xad, 0x58, 0x8e, 0x72, 0x07, 0x2e, 0x6e, 0x63, 0x9c, 0xcf, 0x02, 0x57,
+       0xe8, 0x37, 0xc9, 0x59, 0xe2, 0x70, 0x8d, 0xfc, 0xbb, 0xd6, 0x9f, 0xee,
+       0xba, 0x22, 0xbe, 0x8c, 0xeb, 0xaf, 0xc6, 0xbf, 0x83, 0xa2, 0xb3, 0xa3,
+       0x24, 0x21, 0x6f, 0x63, 0xe9, 0x4d, 0x6a, 0xde, 0xfb, 0x15, 0xc6, 0xf5,
+       0x81, 0xbf, 0x28, 0x5f, 0x34, 0xd8, 0x9b, 0x85, 0x56, 0x02, 0x9c, 0xea,
+       0x86, 0x08, 0xba, 0x9b, 0xc1, 0xc4, 0xdf, 0x41, 0x32, 0xd2, 0xc3, 0xc7,
+       0x0e, 0x7f, 0x3f, 0x5c, 0xaf, 0xc6, 0x97, 0x57, 0x80, 0xcf, 0x40, 0x9c,
+       0xf7, 0x5b, 0x0e, 0xff, 0x60, 0x6c, 0x8f, 0xf3, 0xc0, 0xf3, 0x3c, 0x20,
+       0x77, 0x86, 0xb8, 0xb8, 0x9e, 0xda, 0x89, 0x47, 0x96, 0x35, 0xfb, 0xa9,
+       0x4f, 0x1e, 0x97, 0x63, 0x91, 0x14, 0x46, 0x79, 0x26, 0xb1, 0xfb, 0xb3,
+       0x93, 0x9c, 0xd3, 0x46, 0x60, 0xbf, 0xdc, 0x01, 0x1e, 0x13, 0xde, 0xe3,
+       0xfe, 0x77, 0xd0, 0xfb, 0xb8, 0x2b, 0xc3, 0x2f, 0x4c, 0x79, 0x2a, 0xda,
+       0x79, 0xe2, 0x4a, 0xdc, 0x27, 0xc4, 0x73, 0x7c, 0x8d, 0xea, 0x19, 0xe3,
+       0xdf, 0x4b, 0x32, 0xc2, 0xe1, 0xb4, 0xc3, 0xff, 0x6d, 0x1c, 0x37, 0x58,
+       0xd2, 0x49, 0x57, 0x2b, 0x3d, 0x57, 0x84, 0xc7, 0x24, 0x84, 0xc3, 0x5b,
+       0x8e, 0xc0, 0x14, 0x2c, 0x9d, 0x2a, 0xd0, 0x0b, 0x02, 0x65, 0xf4, 0x5c,
+       0xfa, 0xfb, 0x55, 0x59, 0x36, 0xdf, 0x2a, 0xdc, 0xbf, 0xdc, 0xba, 0x9c,
+       0xc3, 0xa1, 0xfd, 0x59, 0x0e, 0x87, 0xed, 0x2d, 0x26, 0xa2, 0xe3, 0x0d,
+       0x6c, 0x10, 0xf1, 0xdf, 0x20, 0xd3, 0x85, 0xd9, 0x38, 0x3e, 0xc8, 0x97,
+       0x99, 0x38, 0xce, 0x88, 0xd6, 0x7a, 0x13, 0xe6, 0xf3, 0xf5, 0x0b, 0x79,
+       0x4c, 0x74, 0x8f, 0x53, 0x6b, 0x83, 0xc9, 0x74, 0x65, 0xba, 0x9d, 0x25,
+       0xe8, 0x76, 0x8e, 0xc0, 0xc3, 0xfd, 0x88, 0x87, 0xc1, 0xdb, 0x78, 0x5c,
+       0xe5, 0x0a, 0x74, 0x3b, 0x4f, 0xd0, 0xed, 0xb5, 0xc2, 0x7d, 0x89, 0xeb,
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+       0x92, 0x38, 0x07, 0x1b, 0x3b, 0x1e, 0x63, 0x6d, 0x14, 0xbf, 0xdf, 0xfb,
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+       0xe4, 0x93, 0x76, 0x5b, 0xe0, 0x6b, 0x2c, 0xfb, 0xfc, 0x66, 0x10, 0xfd,
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+       0x32, 0x99, 0xec, 0x2b, 0x13, 0x76, 0x15, 0x70, 0x80, 0x10, 0x10, 0xa2,
+       0x7e, 0x49, 0x00, 0xa3, 0x10, 0x1c, 0x50, 0x01, 0x35, 0xe8, 0x24, 0x90,
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+       0x68, 0x43, 0xb5, 0x8a, 0x8a, 0x76, 0x50, 0xf0, 0x51, 0x45, 0x0d, 0x82,
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+       0x73, 0xef, 0xcd, 0xcc, 0x37, 0x99, 0xb0, 0xf4, 0xf9, 0x7e, 0xbf, 0x7f,
+       0xfa, 0xb3, 0x97, 0xfb, 0xdd, 0xfd, 0xec, 0xe7, 0xdc, 0x65, 0x66, 0x45,
+       0x1b, 0x18, 0x1b, 0xc3, 0xd8, 0xb3, 0x26, 0x36, 0xbb, 0xd5, 0x06, 0xa9,
+       0x02, 0xe9, 0x30, 0xc6, 0xce, 0xe2, 0xdf, 0xd5, 0x8c, 0xc5, 0x38, 0x0a,
+       0x66, 0x45, 0x27, 0x31, 0xb6, 0xdf, 0x0a, 0x29, 0xd4, 0x63, 0xcc, 0xea,
+       0x38, 0x34, 0x94, 0xb1, 0x5c, 0x66, 0x60, 0x71, 0x2a, 0x63, 0x25, 0x8a,
+       0x37, 0xc6, 0x01, 0xe5, 0xd5, 0xd6, 0xae, 0x07, 0xca, 0xa0, 0x74, 0xc9,
+       0x6f, 0xbe, 0x35, 0x43, 0x11, 0xdb, 0x10, 0xed, 0x4d, 0x35, 0x26, 0x32,
+       0xe6, 0x4b, 0x37, 0xbb, 0x37, 0xe5, 0x04, 0xfb, 0x93, 0x69, 0x92, 0x03,
+       0x2a, 0x41, 0xbb, 0xfe, 0x2b, 0x0a, 0xd9, 0xc1, 0x04, 0xc6, 0x2c, 0x56,
+       0xe6, 0x8b, 0x1a, 0xc5, 0x98, 0x62, 0x64, 0x3e, 0xd3, 0x28, 0x1c, 0xc7,
+       0xb5, 0xd2, 0x00, 0xed, 0x8d, 0x4d, 0x8c, 0xad, 0x81, 0xf6, 0xb1, 0x76,
+       0x46, 0xf3, 0x64, 0x43, 0x53, 0x0d, 0x2c, 0x99, 0xb1, 0x3b, 0xac, 0x8c,
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+       0x63, 0xdf, 0x33, 0x2d, 0x03, 0xe7, 0xf3, 0x03, 0xd3, 0x32, 0x1d, 0x50,
+       0xff, 0x23, 0xa6, 0x65, 0x61, 0x5e, 0x8e, 0xdb, 0x28, 0xd6, 0x69, 0x34,
+       0x30, 0xef, 0x56, 0x5b, 0xef, 0x79, 0xcd, 0x74, 0x28, 0x7c, 0x1c, 0xe6,
+       0x19, 0xec, 0x81, 0x31, 0x2b, 0x0a, 0x99, 0x37, 0x14, 0x1e, 0x32, 0x2d,
+       0x70, 0x18, 0xa9, 0x5e, 0xc1, 0xc3, 0x37, 0x67, 0x77, 0x41, 0xf9, 0x67,
+       0x1d, 0xb7, 0x64, 0x33, 0xe8, 0x6f, 0xd7, 0xaf, 0xc6, 0xc6, 0x75, 0x45,
+       0xa8, 0x2f, 0xd3, 0xb5, 0x75, 0xb5, 0xee, 0x89, 0xd0, 0xf4, 0xfe, 0x3a,
+       0x2f, 0xa5, 0xf1, 0x8c, 0x69, 0x38, 0x9f, 0x5f, 0xd4, 0xcd, 0xa7, 0xbc,
+       0x13, 0xf2, 0x5b, 0xa1, 0x7d, 0x85, 0xd9, 0x33, 0x38, 0x3e, 0xa4, 0x9f,
+       0x81, 0x8e, 0x78, 0x82, 0x97, 0xa3, 0xe0, 0x4f, 0x9e, 0x01, 0x00, 0x97,
+       0x43, 0xcd, 0xaa, 0x43, 0x71, 0x41, 0xca, 0x0c, 0xc5, 0xd8, 0xfe, 0xa0,
+       0x3f, 0xae, 0x78, 0xbb, 0x68, 0x97, 0xa8, 0x6b, 0xc7, 0xe7, 0xa9, 0x32,
+       0x8d, 0xb1, 0x01, 0xb0, 0x6e, 0x9b, 0xf1, 0x5f, 0x5d, 0x02, 0x76, 0x67,
+       0x19, 0xae, 0x97, 0x51, 0xbf, 0x7d, 0xad, 0x73, 0xa6, 0x83, 0xd3, 0x87,
+       0x99, 0xb9, 0xad, 0xd8, 0xde, 0xbc, 0xe3, 0x3a, 0x2b, 0xe2, 0x57, 0x55,
+       0x34, 0x07, 0xe6, 0x25, 0x3d, 0x5c, 0x01, 0x23, 0x20, 0x3d, 0xdc, 0x83,
+       0x9f, 0xae, 0x60, 0x6c, 0xb4, 0xe2, 0xf5, 0x38, 0xa8, 0x9d, 0x96, 0x20,
+       0xcb, 0xcf, 0xe6, 0xe0, 0xf8, 0xc5, 0x94, 0x97, 0xe3, 0xb3, 0x4c, 0x58,
+       0x71, 0x5a, 0xdf, 0xf0, 0x62, 0x8a, 0x76, 0x13, 0xe2, 0xef, 0x08, 0xd3,
+       0x66, 0x62, 0x7f, 0xad, 0x66, 0x76, 0x99, 0x03, 0xd6, 0xdb, 0x1a, 0xcd,
+       0xe6, 0x47, 0x9a, 0x6f, 0xa9, 0xc0, 0x5f, 0xba, 0x43, 0xd0, 0x0b, 0xb3,
+       0x39, 0x0e, 0x5f, 0x26, 0xc6, 0x83, 0xf9, 0x9d, 0x8c, 0xd1, 0x6e, 0xc7,
+       0x7e, 0xd2, 0xa2, 0x3c, 0x65, 0xd8, 0x6f, 0x5e, 0x46, 0xad, 0x6a, 0x82,
+       0x26, 0xb3, 0xa2, 0x1d, 0xa2, 0xbe, 0xa6, 0x78, 0x86, 0x53, 0x79, 0x25,
+       0xd6, 0x63, 0xa9, 0x9a, 0x52, 0x02, 0xf0, 0xce, 0xfb, 0x04, 0xe8, 0x10,
+       0xb2, 0xdb, 0xf6, 0x14, 0x2a, 0x2e, 0x18, 0x3f, 0xb1, 0x73, 0xa2, 0xe2,
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+       0xb9, 0xbd, 0xdb, 0x9b, 0xc4, 0xb8, 0xd0, 0xde, 0xe4, 0x84, 0x74, 0x6c,
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+       0xfd, 0x2f, 0xea, 0x8f, 0x70, 0x9e, 0x5b, 0x4e, 0xb8, 0x7b, 0xf0, 0x22,
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+       0xfc, 0x99, 0x42, 0xa7, 0x4d, 0x37, 0xaf, 0x2b, 0x85, 0x9f, 0xc2, 0xda,
+       0xff, 0xfb, 0xb7, 0xff, 0x91, 0xc7, 0x58, 0x0d, 0x16, 0xf1, 0x79, 0x16,
+       0x3a, 0x43, 0xfc, 0x96, 0x07, 0xa7, 0x7e, 0x9a, 0xec, 0x25, 0x3f, 0x8e,
+       0xe9, 0xe2, 0x2b, 0xbf, 0x5e, 0xe9, 0x7e, 0x6f, 0x08, 0x8e, 0xf7, 0xae,
+       0xca, 0x90, 0xbf, 0x7e, 0xfd, 0x9f, 0x5d, 0x66, 0x84, 0x77, 0x6b, 0x74,
+       0xec, 0x08, 0x16, 0x17, 0x1c, 0xb7, 0xe6, 0x5f, 0x40, 0x58, 0x60, 0xcf,
+       0x9f, 0xfc, 0x97, 0x81, 0x52, 0x89, 0xc7, 0x25, 0xed, 0xca, 0x68, 0x06,
+       0x0c, 0x59, 0xb0, 0xf3, 0x3b, 0x8a, 0x93, 0x9c, 0xec, 0xf8, 0x17, 0xc5,
+       0x49, 0x2e, 0xb5, 0x97, 0xcf, 0xc0, 0x75, 0xed, 0x7a, 0x8d, 0xc7, 0x4b,
+       0x4e, 0xbf, 0x7d, 0xd0, 0x89, 0x74, 0x24, 0xc7, 0x5f, 0x26, 0xfc, 0xc8,
+       0x49, 0xea, 0xb0, 0xd6, 0x00, 0xd0, 0xd3, 0xa9, 0xcd, 0x66, 0x37, 0xfa,
+       0x21, 0x2a, 0x73, 0x3d, 0x92, 0x0f, 0xf3, 0xa9, 0xd9, 0x63, 0x62, 0x7e,
+       0x92, 0x83, 0xcc, 0x8a, 0xf5, 0x4d, 0x7c, 0xba, 0xcc, 0xb4, 0x79, 0x75,
+       0xa7, 0x1a, 0x8b, 0x79, 0xa3, 0x4f, 0xc4, 0x39, 0x94, 0xb3, 0xa4, 0xef,
+       0x5c, 0x71, 0x48, 0x97, 0xa6, 0x3d, 0x2a, 0xf9, 0x15, 0x2c, 0x91, 0x97,
+       0xd7, 0x32, 0x6b, 0xfd, 0xd9, 0xfe, 0x20, 0x57, 0xc7, 0x19, 0x98, 0x2b,
+       0x24, 0x2e, 0x12, 0xaf, 0x45, 0x33, 0x57, 0x48, 0x9c, 0x22, 0xa1, 0xd8,
+       0xa9, 0xcb, 0x33, 0x8c, 0xa7, 0xc0, 0xb8, 0x8b, 0x18, 0x9f, 0x67, 0x92,
+       0x27, 0x5d, 0xd7, 0x3e, 0x65, 0x76, 0x7f, 0x5d, 0xfd, 0x34, 0xef, 0xa5,
+       0xba, 0xf2, 0x8c, 0xf9, 0xa3, 0x74, 0xf9, 0xac, 0xda, 0xf1, 0xba, 0xfa,
+       0xfd, 0xc0, 0x3f, 0x0a, 0xcd, 0xe7, 0xf8, 0xae, 0xd3, 0xd5, 0x1f, 0xd0,
+       0x34, 0x43, 0x97, 0x1f, 0xd4, 0x72, 0x8b, 0xae, 0xfe, 0xe7, 0xac, 0xf6,
+       0xe1, 0x7c, 0x5c, 0xb7, 0x4f, 0xeb, 0x1c, 0x08, 0xf3, 0x9c, 0x27, 0xe6,
+       0x39, 0x64, 0x5d, 0xb9, 0xae, 0xdd, 0xa5, 0x86, 0xd6, 0x3c, 0xe0, 0x68,
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+       0xe7, 0xf8, 0xb3, 0xc5, 0x7b, 0x14, 0xf8, 0xce, 0x5a, 0x4c, 0x87, 0x38,
+       0xbc, 0x6a, 0x19, 0xc2, 0x8b, 0xd6, 0x0f, 0xf0, 0xac, 0x6c, 0x53, 0xd8,
+       0x63, 0xd0, 0xbe, 0x6a, 0x1d, 0x2f, 0x97, 0xed, 0xe6, 0xb7, 0xaf, 0x5d,
+       0x9d, 0x01, 0xe9, 0x02, 0xbf, 0xfe, 0x3b, 0x63, 0x7e, 0x33, 0xca, 0xfd,
+       0x45, 0x9b, 0xf5, 0xdf, 0x1f, 0x74, 0xda, 0x13, 0x29, 0x4e, 0x93, 0xce,
+       0xd2, 0xcf, 0xaa, 0x91, 0xe8, 0xc0, 0x46, 0xe3, 0x9d, 0x5a, 0xaf, 0xfa,
+       0x2d, 0x80, 0x3f, 0xd5, 0x37, 0x24, 0x8c, 0x0e, 0xf4, 0xf8, 0x60, 0xff,
+       0x4b, 0xba, 0x70, 0x09, 0xba, 0xb0, 0xa4, 0xea, 0xe9, 0x22, 0xca, 0xa5,
+       0xa7, 0x8b, 0xaa, 0xbd, 0xdb, 0xf2, 0x02, 0xac, 0x37, 0x9c, 0x63, 0x86,
+       0x3a, 0x23, 0xc2, 0x51, 0xc2, 0xd9, 0xee, 0xd6, 0xd3, 0x8b, 0x84, 0x2f,
+       0xe8, 0xc9, 0xff, 0x13, 0xf8, 0xbe, 0x81, 0xf0, 0x8d, 0x09, 0xc2, 0x37,
+       0x2d, 0xca, 0xbb, 0x03, 0xf9, 0xef, 0x74, 0xdb, 0x72, 0x95, 0xe1, 0x78,
+       0x5e, 0xef, 0x68, 0x6c, 0xd7, 0x97, 0xfc, 0x9d, 0x62, 0x2f, 0xdc, 0x8d,
+       0xf2, 0xe2, 0x74, 0xdb, 0xd7, 0xb7, 0xed, 0x80, 0xf5, 0xd5, 0xc4, 0x70,
+       0xfe, 0x3f, 0xb9, 0xe3, 0xbb, 0xc1, 0x28, 0xdf, 0x64, 0xbd, 0xeb, 0x56,
+       0x94, 0xbb, 0x27, 0x8e, 0x06, 0xe0, 0x2a, 0xde, 0xf7, 0xb0, 0x7f, 0xf9,
+       0xbd, 0x73, 0xe8, 0xd3, 0xcd, 0xa3, 0x60, 0x3d, 0xa5, 0x6d, 0x2a, 0xf1,
+       0xf1, 0x49, 0xa3, 0xad, 0x49, 0xb9, 0x9c, 0x96, 0xe9, 0x72, 0x00, 0xdc,
+       0x94, 0x1e, 0xbc, 0x71, 0x3c, 0x4a, 0xbc, 0x29, 0xed, 0x3b, 0xff, 0xa9,
+       0x00, 0xde, 0x2c, 0x30, 0x43, 0x13, 0xc6, 0x1b, 0xc7, 0xb9, 0xad, 0x38,
+       0x4f, 0x8c, 0xf4, 0x21, 0xbd, 0x28, 0x60, 0x87, 0x9e, 0x8d, 0x21, 0x7d,
+       0xf2, 0x31, 0xce, 0xcf, 0x57, 0xa8, 0x31, 0x8a, 0xf7, 0xfc, 0x89, 0xb9,
+       0x1b, 0xa0, 0x56, 0x83, 0x3d, 0xef, 0xb2, 0xf3, 0xc4, 0x05, 0x0e, 0x38,
+       0x49, 0x5f, 0x7a, 0x1b, 0x51, 0xbe, 0x8e, 0xed, 0xf4, 0x9e, 0xde, 0x82,
+       0xdd, 0x1b, 0x3b, 0x1d, 0x18, 0xff, 0x9d, 0xe2, 0xf5, 0xd2, 0x7a, 0x2e,
+       0xc7, 0x09, 0x82, 0xfd, 0xc4, 0x1c, 0x00, 0x27, 0x7b, 0xb0, 0x3d, 0xb4,
+       0x3b, 0x8e, 0xe3, 0x4e, 0x29, 0x70, 0xc6, 0xa0, 0xbd, 0xb5, 0x75, 0xd7,
+       0x32, 0xf2, 0xdf, 0x58, 0x7b, 0x22, 0xd9, 0x83, 0x48, 0x32, 0xa1, 0x76,
+       0x4e, 0xb8, 0x9f, 0x25, 0xed, 0x46, 0xb0, 0xd3, 0x4f, 0xf1, 0x79, 0x78,
+       0xbe, 0x76, 0x86, 0xda, 0xe9, 0xc2, 0x6e, 0x93, 0xf6, 0x76, 0x5f, 0xfd,
+       0x80, 0x7e, 0x1d, 0x8a, 0xf6, 0x41, 0x5f, 0xa9, 0xb2, 0x43, 0x1d, 0x6a,
+       0x04, 0xb8, 0x74, 0x2b, 0xd1, 0xee, 0xa7, 0x22, 0xe8, 0x0d, 0x4b, 0x82,
+       0xde, 0x9f, 0xbd, 0x32, 0x18, 0xdf, 0xb2, 0x24, 0x84, 0xe8, 0x89, 0x25,
+       0x77, 0x9e, 0xde, 0x8d, 0xfa, 0x03, 0xe0, 0x1d, 0x9d, 0x00, 0xf3, 0xb4,
+       0xdb, 0x41, 0x7f, 0x2b, 0x17, 0xa4, 0xbf, 0x63, 0xb1, 0xfe, 0x23, 0x31,
+       0xb1, 0x44, 0xd7, 0xdd, 0x7b, 0x55, 0xff, 0x10, 0x68, 0x70, 0xca, 0xea,
+       0x8a, 0x73, 0x02, 0xbc, 0xf2, 0x51, 0x9f, 0x5c, 0x4e, 0x71, 0x20, 0x96,
+       0xe1, 0x0c, 0xb6, 0xab, 0xb5, 0xa6, 0x0f, 0x33, 0x82, 0x3e, 0xc9, 0x3f,
+       0x35, 0x34, 0x8e, 0x9d, 0x23, 0xae, 0x9e, 0x8f, 0xf5, 0x46, 0x07, 0xf3,
+       0xed, 0x51, 0x4c, 0x67, 0x17, 0xac, 0x1e, 0xc5, 0xe7, 0xe5, 0x12, 0xeb,
+       0x3c, 0x10, 0xc5, 0xed, 0xac, 0xb1, 0x22, 0x5f, 0x13, 0x16, 0x8f, 0xaa,
+       0x69, 0xe2, 0xf1, 0xd7, 0x0d, 0x66, 0x60, 0xb5, 0x90, 0x7e, 0xc6, 0x26,
+       0xd8, 0x79, 0xbc, 0xc7, 0x5a, 0x30, 0x16, 0xd7, 0xb3, 0x41, 0xc4, 0xa1,
+       0x57, 0xe7, 0x28, 0x64, 0x27, 0xac, 0x56, 0x14, 0xb2, 0x1b, 0x76, 0xda,
+       0x0a, 0xa9, 0xfc, 0x90, 0xb3, 0x20, 0x0f, 0xe1, 0x77, 0xb9, 0x18, 0x67,
+       0x2c, 0x8c, 0x81, 0xfa, 0xb9, 0xa5, 0xbf, 0x98, 0x8f, 0xb0, 0xc7, 0x64,
+       0xff, 0xdd, 0xa2, 0x7e, 0xb7, 0xb3, 0x90, 0xd2, 0xb1, 0x09, 0x0e, 0x81,
+       0x17, 0xc7, 0xa5, 0x88, 0xff, 0x0a, 0xab, 0x46, 0xfd, 0x9a, 0x55, 0x35,
+       0x22, 0x9c, 0xf3, 0x13, 0xb8, 0xfd, 0x53, 0x13, 0xcd, 0xa4, 0x9f, 0x46,
+       0xfc, 0x34, 0x49, 0xf0, 0xd7, 0x64, 0x21, 0x47, 0x8b, 0xec, 0x20, 0x47,
+       0xb9, 0x1f, 0x38, 0x75, 0x12, 0x94, 0x5f, 0x25, 0xf9, 0x4f, 0xcd, 0xff,
+       0xd0, 0x0c, 0xa4, 0x3b, 0x29, 0xce, 0xc4, 0x30, 0x5e, 0x7c, 0x95, 0x90,
+       0x57, 0xec, 0x8c, 0xf1, 0x53, 0x94, 0x27, 0x0e, 0xf8, 0x1f, 0xca, 0x27,
+       0x6d, 0xa8, 0x63, 0x17, 0x8c, 0xc4, 0x0a, 0x98, 0xe9, 0xd3, 0x50, 0x39,
+       0x53, 0xc8, 0x3a, 0xd3, 0x91, 0x3e, 0x8a, 0xac, 0xfa, 0xef, 0x93, 0xb6,
+       0x4f, 0x3e, 0x8a, 0xf2, 0x6f, 0x12, 0x33, 0x06, 0xbf, 0xe7, 0x70, 0x78,
+       0xc7, 0x38, 0x83, 0x7c, 0x70, 0x63, 0x42, 0x8f, 0x1e, 0xc8, 0x44, 0x39,
+       0xd5, 0x16, 0xdd, 0xf5, 0xcb, 0x29, 0xe8, 0x1f, 0xbf, 0xa3, 0xba, 0x9f,
+       0x62, 0xbd, 0xd7, 0x5b, 0x91, 0xc0, 0xed, 0xb0, 0x66, 0xb4, 0xa3, 0x6d,
+       0x04, 0x2a, 0x0d, 0xe3, 0x97, 0xd9, 0x62, 0x1f, 0xa5, 0x77, 0x7d, 0x0e,
+       0x9f, 0x0d, 0x7d, 0xc4, 0x79, 0x2b, 0xac, 0x05, 0x73, 0x11, 0xbe, 0xaa,
+       0xdd, 0x53, 0x81, 0x29, 0xb0, 0xc3, 0xa5, 0xc8, 0xef, 0x6d, 0x66, 0x6f,
+       0x03, 0xfa, 0x1d, 0xdd, 0x2f, 0x33, 0x9a, 0xc7, 0x50, 0x3f, 0xdb, 0x81,
+       0xf9, 0xe1, 0x3e, 0x17, 0x2e, 0x17, 0xf0, 0xef, 0x8b, 0x19, 0x81, 0x74,
+       0x3d, 0xd2, 0x40, 0x7e, 0xbc, 0x6b, 0x5d, 0xcb, 0xce, 0x28, 0x28, 0x77,
+       0xad, 0x57, 0x9c, 0x0a, 0xe4, 0x4d, 0x46, 0xe6, 0xb3, 0x8f, 0x0a, 0xca,
+       0x93, 0xc6, 0x84, 0x1c, 0x9a, 0x6c, 0x73, 0x57, 0xf9, 0x0e, 0x3b, 0x94,
+       0x27, 0xad, 0x9f, 0xae, 0xf4, 0x87, 0xf9, 0xb4, 0xb0, 0x96, 0xa2, 0x58,
+       0xb4, 0xb7, 0xd6, 0xb3, 0x88, 0x71, 0xc1, 0x3a, 0x41, 0x47, 0x53, 0x0a,
+       0x76, 0x50, 0x7c, 0x3d, 0xa9, 0x1b, 0xe8, 0x34, 0x02, 0x1d, 0xd4, 0x25,
+       0x18, 0xa4, 0x1d, 0xff, 0x9f, 0xb8, 0x8e, 0xb1, 0xdd, 0xde, 0xd1, 0x4a,
+       0xff, 0xa0, 0x3c, 0x22, 0x51, 0x8b, 0x7e, 0xd3, 0x2e, 0x83, 0x3f, 0x52,
+       0x9c, 0x76, 0x9a, 0xad, 0xa8, 0x11, 0xdb, 0x0d, 0xf7, 0xb3, 0x88, 0x71,
+       0xbf, 0x9a, 0x68, 0x3e, 0x8f, 0x26, 0xab, 0x67, 0x0d, 0xd2, 0xe9, 0xf0,
+       0xed, 0x01, 0xf2, 0x87, 0xaa, 0xa4, 0x5c, 0x9f, 0x67, 0x60, 0x46, 0xa0,
+       0xab, 0x1b, 0x84, 0x1c, 0xbf, 0x61, 0x7d, 0xc7, 0x3f, 0xc9, 0x8e, 0xf8,
+       0xee, 0xec, 0x59, 0x55, 0xda, 0xa1, 0x8c, 0xfa, 0x67, 0x28, 0x97, 0xaa,
+       0x6e, 0xb4, 0xfb, 0x31, 0x7e, 0x5f, 0xd5, 0x9e, 0xe3, 0xa3, 0x79, 0x79,
+       0x14, 0xf7, 0x20, 0x48, 0x6a, 0xda, 0xdf, 0xf7, 0x60, 0xbe, 0x2a, 0x37,
+       0xd7, 0x81, 0x71, 0x66, 0xed, 0xef, 0x4c, 0x39, 0x3c, 0x94, 0x4c, 0x58,
+       0xc6, 0xe5, 0x9f, 0x91, 0x1d, 0x96, 0x7a, 0x96, 0xec, 0x06, 0x74, 0x8a,
+       0x18, 0x9b, 0x21, 0xe8, 0xb9, 0x06, 0xfd, 0xd1, 0x24, 0xd2, 0x1f, 0xcd,
+       0x31, 0x00, 0xff, 0xaa, 0xf5, 0xf5, 0x3b, 0xd2, 0xa0, 0xbf, 0x3f, 0x3f,
+       0x0d, 0x7d, 0x40, 0xd1, 0x3e, 0xd5, 0xbb, 0xef, 0x67, 0xd0, 0xef, 0x4d,
+       0xa0, 0xc4, 0x56, 0x8c, 0xc2, 0xd4, 0xc8, 0x4a, 0x29, 0x0e, 0x9d, 0x4a,
+       0xfd, 0xdc, 0x28, 0xfa, 0xf1, 0xfd, 0x0b, 0xc6, 0xb5, 0x06, 0xc7, 0xbd,
+       0xa9, 0x7d, 0x2f, 0xad, 0x67, 0x9f, 0x89, 0xf9, 0xac, 0x40, 0xbf, 0xa6,
+       0x42, 0x3e, 0xb4, 0xe9, 0x3f, 0xe2, 0xfc, 0x0d, 0x28, 0x08, 0x99, 0x9f,
+       0xe8, 0x6c, 0xa6, 0xb5, 0x65, 0x12, 0xea, 0xd7, 0x93, 0xe6, 0xee, 0x11,
+       0x6e, 0xb4, 0x7f, 0x5f, 0xfb, 0x6b, 0x96, 0x0f, 0xe0, 0xff, 0xf1, 0xcf,
+       0x4f, 0xdb, 0xd1, 0x2e, 0xfe, 0xc4, 0xd8, 0x6d, 0xc7, 0xef, 0x47, 0xee,
+       0xfe, 0xc0, 0xae, 0x01, 0xfc, 0x3e, 0xbe, 0x5b, 0x2d, 0x46, 0x78, 0xdf,
+       0x26, 0xf4, 0x8d, 0x84, 0x77, 0x87, 0xc0, 0x7b, 0x42, 0xa2, 0xa7, 0x0d,
+       0xf1, 0x72, 0x7b, 0xdd, 0xf7, 0x79, 0xde, 0x10, 0xbc, 0xb3, 0x15, 0x49,
+       0xc4, 0x3f, 0x0b, 0xfc, 0x30, 0xc3, 0x10, 0xbb, 0x63, 0xd1, 0xe6, 0x18,
+       0xb4, 0x84, 0x7a, 0xf2, 0xd5, 0xad, 0x09, 0xba, 0xbc, 0xd4, 0x1f, 0xd5,
+       0x16, 0x56, 0x1b, 0x29, 0x0e, 0xf4, 0x8d, 0xe0, 0x97, 0x05, 0x5b, 0x36,
+       0x98, 0x33, 0x5c, 0x38, 0xbe, 0xf7, 0x2d, 0x1c, 0xff, 0x88, 0x91, 0xd3,
+       0xcf, 0x91, 0xed, 0x76, 0xbf, 0x2f, 0x27, 0x38, 0x9f, 0xf2, 0x2d, 0x23,
+       0xcd, 0x68, 0x97, 0x7c, 0xd2, 0x6e, 0x61, 0x01, 0xd4, 0x83, 0xc6, 0x4e,
+       0x13, 0xb3, 0x71, 0x39, 0xa3, 0x00, 0x3d, 0x78, 0x05, 0xde, 0xc3, 0xe7,
+       0xb9, 0xfb, 0xf5, 0x18, 0xea, 0xaf, 0xe2, 0x57, 0x5c, 0x2e, 0x95, 0xc1,
+       0x58, 0x2b, 0x00, 0xae, 0xde, 0xf6, 0x05, 0x24, 0x7f, 0xc2, 0xd7, 0x51,
+       0xf1, 0xb1, 0x6b, 0x72, 0x0a, 0xc0, 0xbb, 0xe2, 0x5e, 0x85, 0xe1, 0xbe,
+       0x0a, 0xd6, 0xbf, 0x1b, 0xf0, 0xe6, 0x5d, 0x71, 0xcf, 0x57, 0x68, 0xe7,
+       0x85, 0xaf, 0xb3, 0xcc, 0xa7, 0x97, 0x47, 0x73, 0x9b, 0xf4, 0x79, 0x29,
+       0x27, 0xab, 0x04, 0xbe, 0xe7, 0x31, 0x77, 0x13, 0xda, 0xcf, 0x15, 0x2d,
+       0xfa, 0x7a, 0x55, 0xed, 0xf7, 0x51, 0xff, 0x55, 0x61, 0x72, 0xec, 0x78,
+       0x82, 0xb0, 0xaf, 0xf2, 0xd8, 0xd8, 0xb3, 0x60, 0xa7, 0x34, 0xd8, 0xfa,
+       0xc7, 0x79, 0xcf, 0xa1, 0xaf, 0x4e, 0xd4, 0x81, 0x5c, 0x1f, 0xcc, 0xd8,
+       0xb1, 0x3a, 0x2b, 0xa5, 0x47, 0xea, 0x18, 0xa5, 0x6d, 0x09, 0x2e, 0x82,
+       0xf7, 0xe2, 0xf6, 0xf7, 0xef, 0x42, 0xba, 0x59, 0xd2, 0xb6, 0xd5, 0x8c,
+       0xfd, 0x34, 0xfa, 0x27, 0x39, 0xc6, 0x43, 0x15, 0x4b, 0xfb, 0xcd, 0x0c,
+       0xbf, 0x5b, 0x70, 0x5f, 0x15, 0x9a, 0xce, 0xc1, 0x7d, 0x55, 0x98, 0x27,
+       0xda, 0x3a, 0x88, 0xff, 0xd1, 0x8a, 0xe7, 0x7b, 0xe4, 0x47, 0x93, 0x23,
+       0x6c, 0x9f, 0x55, 0xac, 0xaf, 0x54, 0xc0, 0x9f, 0xd9, 0xb8, 0x5d, 0x51,
+       0x8a, 0xeb, 0x19, 0x81, 0xdf, 0x8d, 0x5f, 0x87, 0xae, 0xe7, 0xd4, 0x9e,
+       0xd1, 0x56, 0x1c, 0xd7, 0x9c, 0x28, 0xe4, 0xf1, 0x58, 0x58, 0x97, 0x7a,
+       0xe1, 0xeb, 0x92, 0xeb, 0x91, 0xeb, 0x93, 0xe5, 0xd5, 0x2a, 0xd0, 0x59,
+       0x84, 0xf6, 0x92, 0xbe, 0xdb, 0x04, 0xbd, 0xcd, 0xdb, 0x38, 0x7d, 0x75,
+       0x3a, 0x80, 0xa2, 0xe1, 0xb5, 0xcf, 0xb3, 0xbb, 0xb8, 0x5f, 0x4a, 0xf6,
+       0xbc, 0x51, 0xe0, 0xc7, 0x68, 0x5b, 0x43, 0xf6, 0xbc, 0x91, 0x81, 0xbd,
+       0xce, 0xd7, 0x29, 0xec, 0x79, 0xf6, 0x21, 0xf2, 0xad, 0xa4, 0xb3, 0x70,
+       0x3a, 0xaa, 0x42, 0x38, 0x50, 0x00, 0x87, 0xb7, 0xb3, 0x0a, 0x3b, 0xbf,
+       0x87, 0x7e, 0xda, 0xef, 0x27, 0x78, 0x48, 0x3c, 0x03, 0x7f, 0xa4, 0x8a,
+       0x7d, 0xb3, 0x54, 0xdc, 0x37, 0x03, 0x3a, 0x3a, 0x14, 0x46, 0x47, 0xba,
+       0x7c, 0x45, 0x8b, 0x3e, 0xff, 0xa5, 0xa9, 0x2b, 0x1b, 0xf9, 0x1b, 0xe8,
+       0xe5, 0x50, 0x28, 0x7c, 0xbf, 0x0c, 0x3b, 0x67, 0x21, 0xd3, 0xa4, 0xc4,
+       0xfe, 0x04, 0x87, 0x79, 0x2e, 0x6d, 0xb2, 0x03, 0xca, 0x2b, 0x98, 0x67,
+       0x35, 0xdf, 0x5f, 0x6d, 0x21, 0xb8, 0x1c, 0x31, 0xb6, 0xec, 0xfe, 0x19,
+       0xf2, 0xdd, 0x46, 0x4e, 0xf7, 0x9f, 0x08, 0xbc, 0xff, 0x32, 0xd1, 0x33,
+       0x21, 0x11, 0xf5, 0x95, 0x51, 0x1b, 0x81, 0xf2, 0xbd, 0x70, 0x65, 0x9a,
+       0x9a, 0x08, 0xf5, 0xca, 0x9a, 0x15, 0x07, 0xf2, 0xd3, 0xdc, 0xc6, 0x91,
+       0x93, 0x91, 0x0f, 0x47, 0x31, 0x8d, 0xfa, 0x9b, 0x93, 0x10, 0xd9, 0x4e,
+       0x9b, 0x93, 0xc8, 0xe1, 0x5f, 0x5e, 0x6b, 0x62, 0x66, 0xb0, 0xef, 0xcb,
+       0x61, 0x0c, 0x94, 0x6b, 0xe5, 0xdb, 0x55, 0xe2, 0x73, 0xa0, 0x23, 0x5b,
+       0x09, 0xe0, 0x61, 0xbe, 0xc0, 0x43, 0xf5, 0xbd, 0x5b, 0xcd, 0x69, 0x90,
+       0xce, 0xaf, 0xad, 0xe2, 0x76, 0x82, 0x9f, 0xf3, 0x0b, 0xc0, 0x95, 0xec,
+       0x84, 0x85, 0xcd, 0x1d, 0x66, 0xa4, 0x57, 0xf0, 0x47, 0x22, 0xf2, 0x9b,
+       0xd4, 0x03, 0xd5, 0xad, 0xfa, 0xf2, 0x1a, 0xd6, 0x4c, 0x78, 0xa8, 0x41,
+       0x3e, 0x93, 0x74, 0x0c, 0xe3, 0xcf, 0x4e, 0x14, 0x7c, 0xe6, 0x66, 0x6e,
+       0xa4, 0x47, 0xef, 0x5d, 0x76, 0xab, 0x12, 0x77, 0xfe, 0xf5, 0xb2, 0xde,
+       0x71, 0x05, 0x8a, 0x3b, 0x9c, 0xda, 0x33, 0x88, 0xec, 0xca, 0x53, 0x2e,
+       0x57, 0x0a, 0xd6, 0xf3, 0x02, 0xce, 0x3b, 0xd1, 0x5e, 0x36, 0x7a, 0xc7,
+       0xe2, 0x77, 0x80, 0x13, 0xe9, 0xa3, 0xee, 0xfa, 0x18, 0x3f, 0xda, 0xcd,
+       0x07, 0xce, 0x80, 0x3f, 0x88, 0x36, 0x9c, 0xc3, 0x3b, 0x16, 0xed, 0xa4,
+       0xae, 0xbf, 0x67, 0xb1, 0x35, 0x4a, 0x90, 0x3e, 0xe5, 0x7a, 0x6a, 0xac,
+       0xcd, 0x44, 0x9f, 0x35, 0x4c, 0xef, 0x6f, 0x96, 0x81, 0x63, 0x83, 0xfb,
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+       0x9b, 0xc7, 0x10, 0xbe, 0xc2, 0xf1, 0x54, 0xfc, 0xc3, 0x5c, 0xc2, 0x07,
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+       0xab, 0xcf, 0x8c, 0x2e, 0xf3, 0x74, 0x0c, 0x6c, 0x0f, 0x1d, 0x1d, 0xfc,
+       0x4e, 0xf6, 0x9c, 0xcb, 0x3c, 0x03, 0xf8, 0xfd, 0xe6, 0xa9, 0x09, 0xba,
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+       0xe2, 0x01, 0xba, 0xef, 0xb7, 0x94, 0x5e, 0xa6, 0xcb, 0x97, 0x9d, 0x01,
+       0x20, 0x8c, 0x46, 0x6a, 0x76, 0x12, 0x1e, 0x96, 0x5b, 0x99, 0x30, 0x16,
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+       0x98, 0xef, 0xd7, 0x6f, 0x9b, 0xa8, 0x3c, 0x1c, 0x1f, 0x12, 0xaf, 0xf3,
+       0xd6, 0x19, 0x98, 0x17, 0xa6, 0x36, 0x77, 0x1d, 0xac, 0x0d, 0xfa, 0x3d,
+       0xd4, 0x02, 0x78, 0x82, 0x76, 0xc7, 0xf7, 0xd9, 0xc9, 0xbf, 0x58, 0xbd,
+       0x65, 0xf4, 0xbb, 0xe3, 0x20, 0x7f, 0x60, 0x8b, 0x89, 0xe2, 0x02, 0x07,
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+       0xfa, 0xdb, 0x50, 0x2e, 0x95, 0xf9, 0x2d, 0x6e, 0xb2, 0x17, 0x76, 0xf9,
+       0x9e, 0x94, 0x79, 0x17, 0xfa, 0xa3, 0x38, 0x49, 0xe4, 0x97, 0x0f, 0x55,
+       0x3f, 0xc6, 0xb7, 0x00, 0x7f, 0x3c, 0x2e, 0xf0, 0xac, 0x85, 0xec, 0xdd,
+       0x23, 0x60, 0xb7, 0xe1, 0xd6, 0xf8, 0x11, 0x85, 0x35, 0x62, 0x8a, 0x8a,
+       0x25, 0x0e, 0xca, 0xbf, 0xe9, 0x4c, 0xf2, 0x23, 0x3f, 0x17, 0xff, 0xa0,
+       0x6a, 0xa9, 0x48, 0x4f, 0xcf, 0x46, 0x51, 0x7d, 0x8a, 0x50, 0x40, 0xf9,
+       0xb1, 0xf7, 0x07, 0x3d, 0xb5, 0x86, 0xe8, 0xcb, 0xd5, 0x1a, 0x20, 0xbe,
+       0xb5, 0x90, 0x3f, 0x30, 0xb7, 0x8b, 0xaf, 0x8f, 0x29, 0xa3, 0x32, 0x10,
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+       0x46, 0xc0, 0xd3, 0x82, 0xc1, 0x9d, 0x23, 0x02, 0xd0, 0xae, 0x34, 0x27,
+       0x90, 0x34, 0x0b, 0xda, 0x9d, 0xd8, 0x68, 0xa2, 0xf3, 0x20, 0xd8, 0xaf,
+       0x03, 0xf2, 0xd5, 0xcf, 0x59, 0x36, 0x70, 0x39, 0xa2, 0xa5, 0x4c, 0x1f,
+       0x1e, 0x0a, 0x4f, 0xff, 0x08, 0x5c, 0xf7, 0x1c, 0x83, 0xe7, 0xff, 0x25,
+       0x02, 0xfe, 0x8e, 0x55, 0xfa, 0x47, 0x90, 0x3c, 0xbb, 0x3b, 0x89, 0xf8,
+       0x2a, 0x1c, 0xee, 0x87, 0xcc, 0x5e, 0x82, 0xaf, 0x0f, 0xf9, 0x40, 0x09,
+       0xca, 0xc7, 0x20, 0x9f, 0xf1, 0x7d, 0x1e, 0x10, 0x6a, 0x69, 0x28, 0x67,
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+       0x26, 0xe3, 0xba, 0x0f, 0x35, 0xe5, 0x30, 0x94, 0x57, 0x72, 0xdc, 0xf2,
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+       0x5b, 0x14, 0xc6, 0xd7, 0xef, 0xe7, 0xe7, 0x05, 0x84, 0x1e, 0x77, 0x3c,
+       0xa4, 0xa0, 0x2d, 0xc5, 0x0e, 0x8e, 0xb1, 0xaf, 0xc1, 0x78, 0xc7, 0x5c,
+       0x60, 0x8f, 0x50, 0xbb, 0xfb, 0xa0, 0x89, 0xdb, 0x05, 0x79, 0x49, 0x5c,
+       0x9e, 0x48, 0xfd, 0xbe, 0x5c, 0xe4, 0xe7, 0x1a, 0x38, 0x5d, 0xb3, 0xd7,
+       0x15, 0xff, 0x26, 0x61, 0xef, 0x84, 0xea, 0x01, 0x29, 0x97, 0x27, 0x25,
+       0xf5, 0xa7, 0xfa, 0x3d, 0x7a, 0x99, 0xb5, 0x92, 0xbc, 0xaa, 0xc4, 0x73,
+       0x1d, 0xb0, 0xbe, 0xc5, 0x9b, 0x2d, 0x7e, 0x7f, 0x0e, 0xb5, 0x71, 0x20,
+       0x9f, 0x2f, 0xe0, 0xe8, 0x61, 0xf5, 0x49, 0x2e, 0x7e, 0xbe, 0xc7, 0xfc,
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+       0xec, 0xcc, 0xc1, 0xf6, 0x1b, 0x1a, 0x9d, 0xd4, 0xde, 0xe4, 0xa6, 0xb8,
+       0xab, 0xd0, 0x27, 0x56, 0x60, 0x20, 0x94, 0x47, 0x55, 0x82, 0xef, 0xaa,
+       0x5b, 0x14, 0x7f, 0x80, 0xf8, 0x86, 0xeb, 0xc5, 0x0a, 0xd1, 0x3f, 0x43,
+       0x3d, 0x13, 0x22, 0xbf, 0x7a, 0xeb, 0x15, 0xbd, 0x3e, 0xa9, 0x10, 0x7a,
+       0xb4, 0x82, 0x85, 0xc5, 0x6d, 0x5b, 0xf4, 0xfa, 0xcd, 0x13, 0x63, 0xa7,
+       0x75, 0x2d, 0x84, 0x71, 0x51, 0x5f, 0x06, 0xe7, 0x05, 0xf6, 0x31, 0xc0,
+       0xac, 0xd2, 0xeb, 0xdf, 0x3d, 0x8d, 0xe6, 0xad, 0xb8, 0xfd, 0x11, 0xe6,
+       0x51, 0xc5, 0xba, 0x03, 0x78, 0x9e, 0xae, 0x7a, 0x8b, 0xe2, 0x0e, 0xb0,
+       0xde, 0xf3, 0x0a, 0x5f, 0xc7, 0x85, 0xce, 0xb3, 0xd2, 0x3d, 0x7d, 0x62,
+       0x7c, 0x6e, 0xc8, 0xb8, 0x61, 0xf3, 0x96, 0xf0, 0xa6, 0xc0, 0x6f, 0x08,
+       0x1e, 0x24, 0xdc, 0x2b, 0x7d, 0x1c, 0x9e, 0x95, 0xed, 0x0a, 0xe1, 0xeb,
+       0x33, 0x61, 0x97, 0xc1, 0x1f, 0xc5, 0x9b, 0x25, 0xde, 0xab, 0x98, 0x67,
+       0x1a, 0x9e, 0x37, 0xa8, 0x7a, 0x08, 0xe4, 0x65, 0x4e, 0x90, 0x0e, 0x7a,
+       0xf4, 0xfe, 0x56, 0xbf, 0x19, 0xed, 0xde, 0xe3, 0xac, 0x25, 0xd6, 0x06,
+       0x74, 0xbf, 0x78, 0xdd, 0xd6, 0x99, 0x57, 0x60, 0xbb, 0xf5, 0xef, 0x93,
+       0x7f, 0x51, 0xea, 0x0c, 0x0c, 0x32, 0xc4, 0x83, 0x7f, 0xe7, 0xeb, 0x58,
+       0x53, 0x9c, 0xd5, 0xdb, 0x4e, 0x08, 0xb7, 0x0f, 0x7e, 0x2c, 0xf8, 0xe0,
+       0xec, 0x8d, 0x79, 0xa2, 0x1d, 0xc0, 0xa3, 0x62, 0xa3, 0xaa, 0x45, 0x8d,
+       0xd0, 0xd5, 0xa3, 0xf6, 0xd2, 0x3e, 0x98, 0xef, 0xf3, 0x99, 0x31, 0x9e,
+       0x39, 0x5f, 0xc4, 0x09, 0xcf, 0x37, 0xcf, 0x1a, 0xac, 0x37, 0xea, 0x42,
+       0xe6, 0x1b, 0xd9, 0x9e, 0xf9, 0xdf, 0xce, 0xfb, 0x85, 0x24, 0xe1, 0x3f,
+       0xf5, 0xb2, 0x87, 0x06, 0x45, 0xf4, 0xa3, 0x7a, 0xec, 0xa0, 0xf3, 0xe8,
+       0xdf, 0x8f, 0x4c, 0x81, 0x2c, 0xd4, 0xbf, 0xdd, 0x59, 0x46, 0xd2, 0x3f,
+       0x5f, 0x1b, 0xdd, 0x7f, 0x2d, 0x48, 0x44, 0x7d, 0x3c, 0x88, 0xfc, 0x82,
+       0xbe, 0xe4, 0x6b, 0xa5, 0xd0, 0xc3, 0x15, 0xa8, 0x97, 0x21, 0x3d, 0xbc,
+       0x6e, 0x5b, 0x2c, 0xfa, 0xed, 0x9f, 0x3d, 0xb4, 0x8d, 0xf6, 0xff, 0xcc,
+       0xcf, 0x57, 0xc4, 0xa2, 0x5d, 0x7c, 0x78, 0xdd, 0xdc, 0x07, 0x7c, 0xc0,
+       0x52, 0x87, 0xb7, 0xcc, 0x25, 0x3d, 0x5c, 0xf5, 0x98, 0xd4, 0xc3, 0x5e,
+       0x73, 0xa8, 0x7e, 0x2f, 0x5a, 0x57, 0xf6, 0xeb, 0x9f, 0x23, 0x7d, 0x6e,
+       0x8e, 0x72, 0x5b, 0xa0, 0xb8, 0x72, 0x97, 0x57, 0xd8, 0xdd, 0x20, 0xef,
+       0x50, 0x0e, 0xae, 0xe3, 0xf2, 0x8e, 0x3d, 0xc4, 0xe5, 0x61, 0x15, 0xea,
+       0xab, 0x61, 0xa4, 0xaf, 0x86, 0x60, 0xbd, 0xbb, 0x2a, 0xbd, 0x43, 0x90,
+       0xce, 0x43, 0xbe, 0x93, 0x1e, 0xbb, 0x6b, 0xae, 0x77, 0x2c, 0xb5, 0x67,
+       0x8e, 0x00, 0xfa, 0x5d, 0x20, 0x39, 0x03, 0xa8, 0xaf, 0xa4, 0x3e, 0x95,
+       0x7a, 0xd6, 0x68, 0xf0, 0x7e, 0x94, 0x84, 0xfc, 0xa3, 0xbe, 0xfd, 0xe7,
+       0x9f, 0xc2, 0xfa, 0xbf, 0x78, 0x49, 0x25, 0xf7, 0xae, 0x5a, 0xdd, 0x90,
+       0xed, 0xc0, 0xfd, 0x82, 0x3e, 0xe4, 0xf6, 0xbf, 0x0f, 0x6f, 0x43, 0x0f,
+       0xbc, 0x73, 0x2e, 0x00, 0xde, 0xe5, 0x08, 0x6f, 0xb2, 0x7f, 0x38, 0xbc,
+       0x3f, 0x6d, 0xe2, 0x70, 0x3e, 0xd8, 0xcc, 0xe1, 0xbe, 0x7a, 0xcb, 0x80,
+       0x58, 0xf4, 0x6f, 0x3f, 0x6d, 0x1a, 0x40, 0x76, 0xcf, 0xa7, 0x5b, 0x06,
+       0x11, 0xbc, 0xe7, 0xad, 0x01, 0x78, 0x93, 0xdd, 0xeb, 0xd2, 0xdb, 0x3d,
+       0x4d, 0x00, 0x6f, 0xb4, 0xf3, 0x11, 0xde, 0x30, 0x6e, 0xf9, 0x2e, 0x97,
+       0x80, 0xb7, 0x9b, 0xc3, 0xbb, 0x49, 0xe8, 0x9d, 0x66, 0x9e, 0xce, 0xeb,
+       0x05, 0x57, 0x1f, 0x9d, 0x1b, 0xbd, 0xeb, 0x69, 0x8b, 0x1b, 0xf5, 0xf9,
+       0x91, 0xa8, 0x40, 0x12, 0xfa, 0x23, 0x47, 0xb6, 0xaa, 0x0c, 0xf7, 0xe5,
+       0x7b, 0xec, 0x22, 0x61, 0xbf, 0x48, 0x38, 0x7f, 0xc3, 0x5a, 0x9e, 0x44,
+       0x3b, 0xaa, 0x97, 0x3d, 0xb3, 0xd6, 0xc2, 0x1c, 0xd0, 0xdf, 0x82, 0x97,
+       0xed, 0x7e, 0x06, 0xf9, 0x63, 0x4a, 0x41, 0x0a, 0x22, 0xe0, 0x44, 0xcb,
+       0x1f, 0x62, 0x71, 0xbc, 0xe0, 0xf8, 0x3d, 0x76, 0x8c, 0x23, 0x79, 0x4c,
+       0x88, 0x1d, 0x73, 0x81, 0xf8, 0x59, 0xc2, 0x3c, 0x74, 0x7e, 0x7d, 0x49,
+       0xfb, 0x1f, 0xf6, 0xa1, 0x1d, 0xaf, 0x68, 0xdc, 0xaf, 0x5f, 0x62, 0xb5,
+       0x05, 0x90, 0x6f, 0xc1, 0xdf, 0x39, 0x11, 0x2a, 0xcf, 0x15, 0x17, 0xca,
+       0x34, 0x8c, 0x93, 0xb8, 0xad, 0x56, 0xa4, 0x83, 0x4c, 0xe6, 0xd2, 0xef,
+       0x1b, 0x79, 0x19, 0xee, 0x1b, 0x7d, 0x3b, 0xe8, 0xab, 0xdb, 0x96, 0x11,
+       0x3f, 0x77, 0x0f, 0x0e, 0xdd, 0xd7, 0xa9, 0x89, 0x0e, 0x98, 0x30, 0xbe,
+       0xd4, 0xbd, 0x55, 0x21, 0x7c, 0x57, 0x2f, 0x2f, 0x88, 0x2d, 0x60, 0xb8,
+       0x2f, 0x55, 0x4b, 0xf3, 0x18, 0x9e, 0xcc, 0xf5, 0xb1, 0xa2, 0x69, 0x14,
+       0x37, 0xb4, 0x00, 0xdd, 0x44, 0xc3, 0x78, 0xee, 0x64, 0x17, 0xff, 0xee,
+       0x72, 0xf0, 0x38, 0xe2, 0x7a, 0x18, 0xd7, 0x1e, 0x9c, 0x6f, 0xf8, 0xf7,
+       0x69, 0x48, 0x7a, 0xa8, 0xcf, 0x6d, 0x06, 0xd2, 0xe7, 0xe1, 0xeb, 0xbf,
+       0x2d, 0x99, 0xfb, 0x2b, 0xd5, 0xaa, 0x81, 0xfc, 0x8e, 0xc5, 0x66, 0xee,
+       0x7f, 0xc8, 0xf3, 0x0f, 0x57, 0x8a, 0xf2, 0x2b, 0x93, 0x79, 0xbc, 0xb7,
+       0x28, 0x99, 0xef, 0x17, 0x9c, 0x8c, 0x62, 0xa4, 0x37, 0x4e, 0xae, 0x8d,
+       0xf1, 0xd7, 0xd3, 0xfa, 0x26, 0x52, 0x3c, 0xb3, 0x27, 0x7e, 0x22, 0xe1,
+       0xe6, 0x30, 0x7e, 0xd9, 0x23, 0xaf, 0x90, 0xaf, 0x44, 0xfc, 0x60, 0x3f,
+       0xb6, 0x81, 0x79, 0xce, 0xb3, 0x88, 0x78, 0x2e, 0xa8, 0x58, 0x6c, 0x7f,
+       0xab, 0x68, 0x7f, 0x6b, 0xcb, 0x3b, 0xb4, 0x2f, 0x07, 0x9e, 0xcb, 0x13,
+       0xa8, 0x77, 0xe7, 0xac, 0xb0, 0xb8, 0xd1, 0x7e, 0xf5, 0xbd, 0x66, 0x21,
+       0xba, 0xbb, 0x27, 0x9a, 0xef, 0xa3, 0xb0, 0xc4, 0x38, 0x23, 0xf2, 0xd1,
+       0x2d, 0x42, 0xce, 0xde, 0xda, 0x72, 0x9f, 0x07, 0xcf, 0x3d, 0xcc, 0x69,
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+       0x36, 0xdd, 0x4c, 0xf1, 0xd3, 0x52, 0x6b, 0xd7, 0xf3, 0xe8, 0x66, 0xdf,
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+       0x55, 0x94, 0x1b, 0xe9, 0xfa, 0x56, 0x73, 0xeb, 0xa0, 0x5a, 0x5b, 0xef,
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+       0xb8, 0xbb, 0xa6, 0xa1, 0x5d, 0x58, 0x1a, 0x6b, 0x36, 0x62, 0x7a, 0x3b,
+       0xeb, 0xb4, 0xe7, 0xe4, 0x04, 0xed, 0x92, 0xd5, 0x05, 0x2a, 0xee, 0xc1,
+       0xc1, 0xc0, 0xd5, 0x53, 0x34, 0xc8, 0x37, 0xa0, 0x3c, 0xe1, 0xf9, 0xfb,
+       0xb4, 0x4c, 0x8a, 0x0e, 0x89, 0xfc, 0xb2, 0x3f, 0x62, 0xf9, 0x8d, 0xdf,
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+       0x39, 0x5b, 0x4e, 0xed, 0x4f, 0xae, 0x12, 0x74, 0xec, 0x5b, 0x31, 0x05,
+       0xf7, 0x39, 0x4e, 0xfe, 0x4a, 0x96, 0xff, 0x9c, 0x97, 0xdf, 0x2b, 0xcb,
+       0xeb, 0x79, 0xf9, 0xfd, 0xb2, 0x7f, 0x91, 0x5f, 0x1b, 0x56, 0x5e, 0x1f,
+       0x56, 0xfe, 0x28, 0xcf, 0x77, 0x3d, 0x5c, 0x3f, 0xc5, 0x87, 0x70, 0x12,
+       0xfb, 0x31, 0xa5, 0xe3, 0x15, 0x92, 0x27, 0x2e, 0x41, 0x67, 0xa5, 0x2b,
+       0x03, 0x04, 0xdf, 0x52, 0xc3, 0x0e, 0x9e, 0x16, 0xb2, 0x80, 0x21, 0xf7,
+       0xfc, 0xf5, 0x6c, 0x29, 0x1e, 0x57, 0x32, 0xed, 0x0b, 0x1e, 0xb2, 0xa3,
+       0xde, 0x4e, 0x48, 0xd3, 0x5c, 0xc9, 0x50, 0xcf, 0x96, 0xe4, 0x3d, 0x8e,
+       0xdf, 0x17, 0x4e, 0x57, 0x7c, 0x66, 0x94, 0x93, 0x1f, 0xfa, 0x07, 0x0b,
+       0xb9, 0x1e, 0xf1, 0x5c, 0xad, 0x4b, 0xd0, 0x6d, 0x54, 0x2a, 0xef, 0x4f,
+       0xc2, 0x1b, 0xfa, 0xf9, 0x1a, 0xfb, 0xbb, 0xd8, 0x7e, 0xd6, 0xe1, 0xbc,
+       0x92, 0x74, 0xfd, 0x7c, 0xff, 0xef, 0xf4, 0x33, 0x2f, 0xb5, 0x57, 0x3f,
+       0xe6, 0x94, 0x7f, 0xa3, 0x9f, 0xbd, 0x61, 0xeb, 0x92, 0x76, 0x51, 0x59,
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+       0x17, 0xc0, 0x79, 0xcc, 0x87, 0x7c, 0x9f, 0xb9, 0x72, 0x7d, 0xce, 0x28,
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+       0x7c, 0x06, 0x2c, 0x0b, 0x6d, 0x8b, 0x2d, 0x32, 0xdf, 0x36, 0x65, 0x62,
+       0x3e, 0xc5, 0xb9, 0x28, 0x7f, 0xc3, 0x23, 0x5b, 0xef, 0x43, 0xbe, 0xd9,
+       0x13, 0xcd, 0xcf, 0x4d, 0xcc, 0x19, 0x3b, 0x3c, 0x1a, 0xe5, 0x42, 0x57,
+       0x4e, 0x8c, 0xc1, 0x01, 0xf2, 0x62, 0x5c, 0x62, 0x59, 0x2d, 0xe2, 0x6f,
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+       0x0d, 0xaf, 0x99, 0xc7, 0xb9, 0xbc, 0x6f, 0xa9, 0x14, 0xe7, 0xf2, 0x8e,
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+       0x73, 0xdd, 0x03, 0x68, 0x46, 0xbb, 0x43, 0xce, 0x43, 0x8e, 0x0f, 0x86,
+       0xca, 0xf2, 0x4e, 0xe8, 0xef, 0xd0, 0xca, 0xb4, 0x91, 0x6b, 0x5c, 0xb8,
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+       0x9c, 0x31, 0x31, 0x46, 0x97, 0xbf, 0x71, 0x6a, 0x02, 0xd3, 0x42, 0xe3,
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+       0xef, 0x32, 0x5d, 0x79, 0x89, 0xa5, 0x33, 0xb7, 0xf6, 0x22, 0xec, 0xdf,
+       0x1a, 0xbb, 0x3d, 0x1a, 0xed, 0xb0, 0x8f, 0xdb, 0xbf, 0xf9, 0xcb, 0xad,
+       0x68, 0xd7, 0x6d, 0x54, 0xdd, 0x0a, 0xac, 0x67, 0xc1, 0x6b, 0x9b, 0xfe,
+       0x32, 0x01, 0x6a, 0x9d, 0xc2, 0xe3, 0x97, 0xfc, 0xfe, 0x14, 0xc5, 0xbd,
+       0x8e, 0xe1, 0x79, 0x36, 0xe4, 0x3d, 0xa3, 0x66, 0x0c, 0xdd, 0xaf, 0xf9,
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+       0xc7, 0x2e, 0x3a, 0xaf, 0xfa, 0x63, 0xed, 0xd7, 0x3c, 0x90, 0x22, 0xfc,
+       0xdf, 0x51, 0x6c, 0x14, 0xea, 0xbf, 0x53, 0xb5, 0x7f, 0xa6, 0x38, 0xdb,
+       0x12, 0x1b, 0x5f, 0xcf, 0x17, 0xaf, 0x1e, 0x30, 0xe3, 0x39, 0x06, 0x3c,
+       0x17, 0x70, 0x16, 0xe8, 0xfb, 0x1a, 0x6c, 0xa8, 0x22, 0x9f, 0xfb, 0x28,
+       0x0e, 0x5d, 0xd4, 0x76, 0xc0, 0x8c, 0xfe, 0x91, 0x3b, 0x85, 0xcb, 0xe5,
+       0x25, 0x99, 0x4b, 0x8d, 0x60, 0x91, 0xb1, 0x1a, 0x48, 0x51, 0x6f, 0x4c,
+       0x06, 0xf9, 0x14, 0x07, 0xf4, 0xd1, 0xd9, 0xc1, 0x86, 0x6f, 0xc7, 0x73,
+       0x13, 0x39, 0x76, 0x3a, 0x07, 0x5e, 0x7d, 0x66, 0x06, 0x08, 0x69, 0xa4,
+       0x23, 0xdf, 0xb0, 0xa5, 0x50, 0x6f, 0x51, 0x53, 0x31, 0xe5, 0x97, 0x9c,
+       0x89, 0xa6, 0x7e, 0xdf, 0x53, 0x3b, 0x27, 0xd3, 0x79, 0xe4, 0x57, 0x14,
+       0xda, 0x2f, 0x28, 0xc9, 0x98, 0xb3, 0x12, 0xed, 0x51, 0xac, 0x7f, 0x07,
+       0x8c, 0x57, 0xf2, 0xe2, 0x35, 0xc5, 0x08, 0x9f, 0x25, 0xdb, 0xf9, 0xbd,
+       0xa7, 0x12, 0xf5, 0x4f, 0xb9, 0xd8, 0xcf, 0xe2, 0x96, 0x62, 0x6a, 0x5f,
+       0xa2, 0xb2, 0x3d, 0x0a, 0xd8, 0x07, 0x53, 0x8a, 0xb8, 0x9e, 0x2d, 0x41,
+       0xdd, 0x0e, 0x79, 0x35, 0xcf, 0xbe, 0x06, 0xf5, 0xab, 0x6a, 0x0e, 0x0c,
+       0x7e, 0x1c, 0xe5, 0x89, 0xd9, 0x4e, 0xf2, 0x24, 0xee, 0xcc, 0x2d, 0x34,
+       0x7e, 0xcd, 0x19, 0x2b, 0xb5, 0xff, 0xad, 0x90, 0x17, 0xa6, 0x2e, 0x3e,
+       0xaf, 0x49, 0x67, 0x3c, 0xf4, 0x5d, 0xe2, 0xbd, 0x3d, 0x85, 0xef, 0x03,
+       0xca, 0xbc, 0x29, 0x69, 0xa3, 0x11, 0xef, 0x15, 0x98, 0xba, 0x18, 0xd5,
+       0xbf, 0xee, 0xcc, 0xa5, 0x94, 0xca, 0x75, 0xbe, 0x35, 0xf4, 0xe9, 0x44,
+       0x94, 0x63, 0xa6, 0xa4, 0xaf, 0x27, 0x67, 0x00, 0x7d, 0xbc, 0x95, 0xa8,
+       0x38, 0xc8, 0xdc, 0x08, 0x93, 0xb7, 0xa7, 0x6b, 0xc7, 0xc6, 0xb1, 0x08,
+       0xf2, 0xa8, 0x67, 0x9c, 0x33, 0xfc, 0xfc, 0xae, 0xe5, 0x0c, 0x3f, 0xcf,
+       0xdb, 0x9e, 0xa6, 0xfd, 0x09, 0xf9, 0x6a, 0xda, 0xdd, 0x5d, 0x46, 0xdc,
+       0xbf, 0x61, 0x36, 0xab, 0x03, 0xe1, 0x35, 0x6d, 0xdc, 0x48, 0x57, 0x65,
+       0x08, 0x1f, 0xa9, 0x3b, 0x6e, 0x36, 0x23, 0x5e, 0x4c, 0x0f, 0xbd, 0x6f,
+       0x46, 0x7d, 0x6c, 0x81, 0xb4, 0x28, 0xa4, 0xbc, 0x5a, 0x9e, 0x3b, 0x0f,
+       0x93, 0xc7, 0xfb, 0x04, 0xdf, 0xc9, 0x7b, 0x07, 0x52, 0xbf, 0x30, 0xdf,
+       0x6c, 0xb2, 0x47, 0x6f, 0x13, 0xfe, 0xb7, 0xe4, 0x93, 0x37, 0x45, 0x7d,
+       0xd9, 0xbe, 0x13, 0x69, 0x1c, 0xf1, 0xf8, 0xb2, 0x85, 0xfc, 0xa7, 0x3f,
+       0xa7, 0x79, 0x8f, 0xa3, 0xbc, 0xec, 0x2c, 0x60, 0xb3, 0x5f, 0x22, 0xf9,
+       0xd8, 0x99, 0x8d, 0xfb, 0x26, 0x3f, 0xd6, 0xfc, 0x01, 0xcf, 0x56, 0x85,
+       0xec, 0xfb, 0x2e, 0x3a, 0xcf, 0x3e, 0x6d, 0x9c, 0xcb, 0x80, 0xfb, 0x01,
+       0xdd, 0x3d, 0xeb, 0xe0, 0xfc, 0x7a, 0xbe, 0x75, 0x7c, 0x2c, 0xea, 0xbf,
+       0xa7, 0xb2, 0x15, 0xd8, 0xef, 0x7b, 0x57, 0x5f, 0xdd, 0xa9, 0x41, 0x7f,
+       0x1d, 0x3f, 0x1b, 0x3d, 0x1a, 0xe5, 0xbe, 0x1c, 0x57, 0x49, 0xe5, 0xf7,
+       0x70, 0x98, 0xa3, 0xfb, 0x3b, 0xf4, 0xe7, 0x6a, 0x5e, 0x8f, 0x71, 0x21,
+       0x5f, 0x97, 0xa0, 0x73, 0x94, 0x1b, 0xb4, 0x63, 0xe1, 0x3b, 0xc3, 0xf8,
+       0x5f, 0xcd, 0xeb, 0x96, 0xa7, 0x14, 0x28, 0xaf, 0x89, 0x05, 0x7f, 0x16,
+       0xc6, 0x2f, 0x7a, 0x23, 0x2a, 0x80, 0x74, 0xdc, 0xf1, 0x46, 0x94, 0x11,
+       0xf5, 0x43, 0x7d, 0xa6, 0x57, 0x49, 0x1d, 0x83, 0xdf, 0x87, 0x4c, 0x44,
+       0xff, 0x4d, 0x6b, 0xb7, 0x18, 0x19, 0xd9, 0x37, 0x9a, 0x01, 0xbf, 0xf7,
+       0x35, 0xdf, 0xf3, 0xc9, 0xa7, 0x70, 0x3a, 0x93, 0x7c, 0xe9, 0x6d, 0xe2,
+       0xfc, 0x52, 0x26, 0xe8, 0xb4, 0x5c, 0xf0, 0x9f, 0x57, 0xf0, 0xd1, 0xe9,
+       0xda, 0x14, 0xe2, 0xc3, 0xd3, 0x77, 0xc3, 0xa4, 0x71, 0x9f, 0xf3, 0x6e,
+       0x65, 0xf8, 0x76, 0xb4, 0x07, 0x5c, 0x76, 0xf7, 0x20, 0x57, 0x90, 0x2f,
+       0x4b, 0xd0, 0xef, 0x81, 0xef, 0x25, 0x97, 0xc5, 0x93, 0xff, 0x17, 0xc2,
+       0x77, 0xc4, 0x87, 0x8b, 0xcf, 0x38, 0xa8, 0xbf, 0xea, 0x33, 0x2e, 0xc1,
+       0xe7, 0x4e, 0xca, 0x4b, 0x7e, 0x2b, 0x17, 0xfc, 0x62, 0x11, 0x76, 0xc4,
+       0x3c, 0x41, 0xdf, 0x49, 0xe9, 0xde, 0x91, 0xa9, 0x30, 0xff, 0x92, 0x06,
+       0xe0, 0x77, 0x18, 0xc7, 0xbb, 0x32, 0x2d, 0x17, 0xf9, 0x28, 0x48, 0x2f,
+       0x66, 0x07, 0xd2, 0x15, 0xd0, 0x4b, 0x6a, 0x65, 0x08, 0xdf, 0x34, 0x74,
+       0xdc, 0xcc, 0xd0, 0xfe, 0xb0, 0x24, 0x7a, 0x88, 0x5e, 0xe6, 0x41, 0x1a,
+       0x6a, 0x7f, 0x54, 0xf4, 0xd8, 0x1f, 0x8e, 0xc9, 0xc9, 0x30, 0xef, 0x69,
+       0x8d, 0x39, 0xba, 0x7b, 0x16, 0x79, 0xa9, 0x17, 0x47, 0xf7, 0x03, 0x52,
+       0xc5, 0xbe, 0xbc, 0x2d, 0x30, 0x08, 0xed, 0x55, 0x53, 0x6d, 0x94, 0x1b,
+       0xef, 0x83, 0x9d, 0x4a, 0xe4, 0xfb, 0x33, 0xcb, 0xee, 0xe5, 0xf0, 0x5b,
+       0x66, 0xf2, 0x14, 0xa1, 0xfd, 0xb0, 0xec, 0x51, 0xc5, 0x0d, 0x98, 0x21,
+       0xbb, 0x02, 0xe5, 0x51, 0xde, 0xbe, 0x5a, 0x73, 0x68, 0xbc, 0xf1, 0xe6,
+       0x33, 0x23, 0x98, 0x0b, 0xe0, 0x70, 0xc3, 0x99, 0x81, 0x94, 0x5e, 0x9e,
+       0xe4, 0x9d, 0x88, 0xf8, 0x2f, 0x3b, 0x33, 0x53, 0xc0, 0x6b, 0xc4, 0xbf,
+       0xb5, 0x0f, 0x38, 0x46, 0xe3, 0xf1, 0x25, 0x93, 0xdf, 0xe2, 0xde, 0x80,
+       0xfb, 0x6c, 0x51, 0x5e, 0x15, 0xf1, 0x7b, 0x24, 0x8b, 0x39, 0x1e, 0x0c,
+       0x89, 0x2f, 0x61, 0x3c, 0x0c, 0xe3, 0x62, 0x72, 0x7f, 0x50, 0xc6, 0x9b,
+       0x2c, 0xb8, 0x9f, 0x1a, 0xa2, 0x27, 0xbf, 0x31, 0xb6, 0x64, 0xa3, 0xbf,
+       0xd3, 0x2b, 0xee, 0x54, 0xa0, 0xdf, 0x47, 0x5b, 0xdc, 0xf1, 0xa7, 0x3c,
+       0x03, 0x94, 0x1f, 0xcb, 0xd1, 0x28, 0xfe, 0x34, 0xc7, 0xe0, 0xbd, 0x0d,
+       0xf1, 0xba, 0x70, 0x86, 0xff, 0x05, 0x13, 0xe4, 0x17, 0xdd, 0xbf, 0x2d,
+       0x16, 0xe3, 0xdd, 0x12, 0x9e, 0xad, 0xc6, 0xc0, 0x20, 0xd4, 0x93, 0xad,
+       0x00, 0x47, 0x8c, 0x83, 0xb5, 0x36, 0xab, 0xc5, 0x7e, 0x6e, 0xcf, 0xc4,
+       0xf0, 0xfd, 0x2f, 0x4e, 0xd7, 0x92, 0x8e, 0xc3, 0xe9, 0x7b, 0xe1, 0x99,
+       0xfe, 0x44, 0x4f, 0xa7, 0x6b, 0x2d, 0xa4, 0x77, 0x4e, 0x03, 0xbd, 0xb2,
+       0x10, 0xbd, 0x23, 0xf5, 0x8d, 0x94, 0xef, 0x52, 0xef, 0x48, 0x7a, 0xae,
+       0x36, 0x72, 0xb9, 0x55, 0x6d, 0x8b, 0xa3, 0x73, 0x15, 0x41, 0x7d, 0x33,
+       0xdd, 0x83, 0x71, 0x5c, 0x36, 0x94, 0x9f, 0x7f, 0x0b, 0xea, 0x9b, 0xa7,
+       0x1e, 0x18, 0x8f, 0xf4, 0x7f, 0x32, 0x91, 0xce, 0x35, 0x87, 0xd3, 0xff,
+       0x2b, 0x75, 0xa9, 0x74, 0xce, 0x46, 0xea, 0x91, 0x70, 0x7d, 0x23, 0xe5,
+       0xb9, 0x94, 0xef, 0x52, 0x5f, 0xdd, 0x95, 0xe6, 0x5d, 0x8b, 0x70, 0x2a,
+       0x7c, 0xee, 0xbf, 0xb7, 0xfd, 0x1d, 0x3e, 0x5d, 0x67, 0xe4, 0x7a, 0xeb,
+       0x3a, 0xa3, 0x9d, 0xe8, 0xe7, 0xc2, 0xe5, 0xe6, 0x01, 0x21, 0x37, 0x0f,
+       0xe8, 0xe4, 0xe6, 0x92, 0x3e, 0xe4, 0xfe, 0xc3, 0x17, 0x49, 0xff, 0x8d,
+       0xa2, 0x3e, 0xd8, 0xaf, 0x64, 0x17, 0xa2, 0x5c, 0x0f, 0xed, 0xef, 0xcf,
+       0x69, 0x85, 0xbf, 0x41, 0xfa, 0x7d, 0x21, 0x95, 0xeb, 0xd5, 0x1f, 0x6b,
+       0xde, 0x7d, 0xc9, 0xfb, 0x17, 0x52, 0xa5, 0x1f, 0x71, 0x61, 0xf2, 0xfe,
+       0x71, 0x51, 0xff, 0x7c, 0xf2, 0xbe, 0x43, 0xc8, 0xfb, 0x70, 0xf9, 0xce,
+       0xa0, 0x3f, 0x94, 0xef, 0x27, 0x5f, 0xbb, 0x84, 0xf6, 0xa7, 0xf7, 0x33,
+       0xd0, 0x07, 0xa8, 0xf7, 0xda, 0x63, 0x5c, 0x9b, 0x84, 0xfc, 0x27, 0xfd,
+       0x10, 0x1d, 0xe7, 0x3f, 0x97, 0xfc, 0xf7, 0x64, 0xce, 0xed, 0xe8, 0x43,
+       0xfe, 0xef, 0xf8, 0xdf, 0xc8, 0x7f, 0x49, 0x8f, 0x92, 0x5f, 0x24, 0x7f,
+       0x48, 0x7e, 0x08, 0xe7, 0x1f, 0xc9, 0x0f, 0x53, 0xee, 0x03, 0xff, 0x0f,
+       0xf1, 0xf4, 0x1e, 0xbf, 0x5f, 0x54, 0x6d, 0xf4, 0x6d, 0xa1, 0xfd, 0x43,
+       0x57, 0xcc, 0x48, 0xe4, 0xcb, 0x1e, 0xbb, 0x6d, 0xbb, 0x42, 0x7c, 0xd6,
+       0x4b, 0x2f, 0x08, 0xbe, 0x09, 0xf2, 0x89, 0x5e, 0x4f, 0x48, 0xbe, 0x90,
+       0x7c, 0x22, 0xf9, 0xa3, 0x5a, 0xf0, 0x43, 0x45, 0x18, 0x3f, 0xec, 0x54,
+       0x5b, 0x1f, 0x1c, 0x0f, 0xed, 0x6e, 0x4e, 0xf3, 0x9e, 0x0e, 0xe5, 0x8b,
+       0xc5, 0x2f, 0x85, 0xeb, 0x85, 0x3e, 0xe9, 0x0a, 0x23, 0x86, 0xac, 0x22,
+       0xb1, 0x96, 0x21, 0x5d, 0x55, 0x43, 0x1a, 0x4a, 0x57, 0x96, 0x3e, 0xf8,
+       0xe1, 0x4c, 0x0f, 0x3d, 0x5d, 0x18, 0x3f, 0x1c, 0xbe, 0x40, 0x7a, 0x8a,
+       0x49, 0x33, 0x53, 0xbd, 0xff, 0x43, 0x7a, 0x8a, 0x49, 0x4b, 0x8a, 0x48,
+       0x4f, 0xb6, 0xb4, 0x1f, 0xd1, 0x9e, 0x38, 0x5d, 0xfb, 0xd7, 0x5c, 0x17,
+       0xcc, 0xe7, 0x74, 0x2e, 0xc8, 0xd9, 0x9c, 0x20, 0xbd, 0x4d, 0xf9, 0x23,
+       0xe3, 0xf6, 0xc2, 0x00, 0x6e, 0xf7, 0xef, 0x89, 0xe6, 0xeb, 0xdc, 0x63,
+       0xce, 0xa2, 0x78, 0xce, 0x94, 0xb3, 0xfc, 0x5c, 0xab, 0xa4, 0x4b, 0x89,
+       0x67, 0x69, 0x07, 0x54, 0x88, 0x78, 0x42, 0x71, 0xba, 0xc7, 0x8d, 0xf3,
+       0x95, 0xfe, 0xc2, 0x85, 0xe2, 0xd9, 0x92, 0xd8, 0x69, 0x46, 0x3f, 0xa4,
+       0x02, 0xd2, 0x50, 0xfd, 0xdf, 0x97, 0xbd, 0x3b, 0x26, 0xed, 0xe2, 0xf0,
+       0x3c, 0x20, 0xed, 0xc2, 0xec, 0xc4, 0xc9, 0x02, 0xcf, 0x3f, 0xa2, 0x9d,
+       0x38, 0x3d, 0x12, 0x5e, 0x99, 0xc3, 0xa9, 0x8b, 0x43, 0x80, 0xfe, 0xbb,
+       0x81, 0xec, 0xb7, 0x80, 0x91, 0x8e, 0xc8, 0xf4, 0xe9, 0x57, 0xac, 0xe3,
+       0x70, 0x96, 0xf9, 0x55, 0x01, 0xa3, 0xd4, 0xb7, 0x09, 0xa8, 0x6f, 0x81,
+       0x5e, 0x66, 0xe0, 0x78, 0xff, 0x2e, 0xbd, 0x94, 0x14, 0x31, 0x11, 0x0f,
+       0x7c, 0x79, 0xaa, 0x96, 0x0f, 0x78, 0xff, 0x85, 0xc8, 0xb3, 0x57, 0xa7,
+       0x22, 0x7e, 0x66, 0x8e, 0x93, 0xe5, 0xbf, 0x6d, 0xd6, 0x06, 0xa2, 0xdc,
+       0x61, 0x32, 0x8e, 0x4e, 0x71, 0x91, 0xf7, 0x54, 0x91, 0xf7, 0xbd, 0xf2,
+       0xf6, 0x44, 0xa8, 0x3f, 0xe5, 0x41, 0x16, 0x8c, 0xb3, 0x43, 0xf9, 0xa4,
+       0xfc, 0xb8, 0x9e, 0x38, 0x8a, 0xc2, 0x82, 0xf5, 0x97, 0x3e, 0xba, 0xfd,
+       0xed, 0x66, 0xc2, 0x33, 0x3f, 0xf7, 0xc2, 0xbc, 0x5d, 0x46, 0xbe, 0xcf,
+       0x24, 0xf2, 0xb9, 0x90, 0xb7, 0x87, 0xe4, 0xc7, 0x85, 0xe5, 0xd7, 0xf3,
+       0xfa, 0xb1, 0xc6, 0x2e, 0xc6, 0xcf, 0x29, 0xfa, 0x39, 0xbf, 0xaa, 0xb8,
+       0xf5, 0xc6, 0xe9, 0xc7, 0x13, 0x62, 0x8f, 0x00, 0x26, 0x27, 0xe3, 0x79,
+       0x82, 0x69, 0xdb, 0x15, 0x07, 0xc6, 0x41, 0x6e, 0xc9, 0x3f, 0x49, 0xfb,
+       0xb1, 0xc1, 0xf5, 0xbf, 0x41, 0xeb, 0x5f, 0xd2, 0xae, 0x88, 0xfc, 0xce,
+       0xb7, 0x71, 0xbd, 0xb7, 0x6c, 0xe7, 0xf9, 0x47, 0x1e, 0xfd, 0x43, 0xb3,
+       0x6f, 0xa0, 0xe8, 0x2f, 0x99, 0xe2, 0x64, 0xf4, 0x67, 0x6a, 0x55, 0x34,
+       0x3c, 0xff, 0xb0, 0x78, 0x9c, 0xe2, 0xef, 0x9f, 0xd3, 0x1b, 0xce, 0x8f,
+       0xa4, 0xe9, 0xfd, 0x1b, 0xfc, 0x33, 0xea, 0xdb, 0x33, 0x3c, 0x7f, 0x77,
+       0x31, 0xed, 0x11, 0xcf, 0xd4, 0xbe, 0x3f, 0xb5, 0x0f, 0x58, 0x2e, 0x62,
+       0xfc, 0x59, 0xf9, 0x91, 0xef, 0x3d, 0xfc, 0x97, 0xac, 0x27, 0xe2, 0x09,
+       0xd4, 0x3f, 0xc0, 0xf2, 0x86, 0xd6, 0xc8, 0xef, 0x97, 0xbc, 0x28, 0xf8,
+       0xb1, 0x13, 0xf7, 0x4d, 0x08, 0x5e, 0x1f, 0x35, 0x23, 0xfc, 0x3a, 0xcd,
+       0x12, 0x9e, 0xff, 0x68, 0xc6, 0x78, 0x37, 0xdd, 0x9f, 0x81, 0xfc, 0xab,
+       0x8f, 0xfe, 0x63, 0xaa, 0x6f, 0x18, 0x9f, 0xbe, 0x16, 0xb6, 0xfe, 0x73,
+       0xcd, 0xff, 0xf1, 0x08, 0xeb, 0x77, 0xe9, 0xdb, 0x07, 0xce, 0x05, 0xbf,
+       0x0d, 0xbd, 0xda, 0x0b, 0xfa, 0x99, 0xaf, 0xa7, 0xa7, 0x38, 0xa3, 0x67,
+       0xd7, 0x69, 0xe8, 0x27, 0x0e, 0xfc, 0x7f, 0xb4, 0x8b, 0x97, 0x78, 0xa2,
+       0x9a, 0xd1, 0xfe, 0x0f, 0xd2, 0xc7, 0x61, 0xa2, 0x8f, 0x4e, 0x19, 0xcf,
+       0xef, 0x45, 0xff, 0x9f, 0x4f, 0x9d, 0x68, 0x23, 0xfb, 0x47, 0xd4, 0x3f,
+       0xda, 0x8c, 0x7a, 0xcc, 0x63, 0xe8, 0xa9, 0xcf, 0xf9, 0x41, 0xd2, 0x17,
+       0x5e, 0x05, 0xc2, 0xb3, 0x73, 0x8c, 0xb7, 0xff, 0xe0, 0xd1, 0x23, 0xcd,
+       0x08, 0x1f, 0xc0, 0x0f, 0x95, 0x53, 0xde, 0x78, 0x0e, 0x7e, 0x68, 0x0d,
+       0xcb, 0xe7, 0x87, 0xf1, 0x8f, 0xa0, 0x7f, 0xe2, 0x5f, 0x94, 0xf3, 0x00,
+       0x9f, 0x41, 0x11, 0xe4, 0xcc, 0x29, 0x01, 0x9f, 0x2f, 0xc4, 0xb9, 0xea,
+       0xce, 0x42, 0x6e, 0x27, 0x76, 0xf6, 0xe7, 0xa9, 0x33, 0x9d, 0xdb, 0x85,
+       0xff, 0x12, 0xf8, 0x36, 0xa4, 0xf3, 0xfa, 0x9d, 0xd1, 0x21, 0x70, 0x08,
+       0xc1, 0x33, 0xfc, 0x05, 0xd0, 0x0f, 0x09, 0x59, 0x37, 0xc1, 0xe9, 0xe6,
+       0x44, 0xb9, 0xee, 0xa8, 0x92, 0xa9, 0xb0, 0xae, 0x4e, 0x27, 0x2f, 0xb7,
+       0xa5, 0x9b, 0xee, 0xf7, 0xe5, 0x07, 0xf3, 0xe1, 0xfd, 0xc5, 0xa6, 0x47,
+       0x95, 0x20, 0x5c, 0x82, 0xfd, 0x5b, 0xde, 0x41, 0xb9, 0x74, 0xb3, 0x80,
+       0x9b, 0x33, 0xdd, 0xfa, 0x8e, 0x8f, 0xcb, 0x43, 0x05, 0xf9, 0xb2, 0x9a,
+       0x08, 0x04, 0xe8, 0x62, 0xbb, 0xe2, 0x53, 0xd1, 0x4f, 0x40, 0xba, 0x88,
+       0xb0, 0xee, 0xbf, 0xf7, 0xa6, 0x2b, 0x5f, 0x58, 0x7b, 0xcd, 0x74, 0x8e,
+       0xf6, 0x5d, 0xbd, 0xdb, 0x6b, 0x61, 0xed, 0x99, 0x29, 0xf7, 0x62, 0xda,
+       0x0b, 0xbc, 0x4d, 0x0d, 0xc3, 0x6b, 0x71, 0x18, 0x5e, 0x27, 0x86, 0xe5,
+       0x4b, 0x65, 0xde, 0xaf, 0x93, 0x7f, 0x52, 0x2e, 0x96, 0xb7, 0xad, 0x5d,
+       0x95, 0x9c, 0x88, 0x71, 0x49, 0x85, 0xee, 0x8a, 0x06, 0xe9, 0x39, 0xa5,
+       0x04, 0xe9, 0x79, 0x91, 0x43, 0xd2, 0x6f, 0x2a, 0xc1, 0x35, 0x48, 0xcf,
+       0x69, 0xef, 0x20, 0xfd, 0xce, 0x68, 0x95, 0xf2, 0x30, 0xfd, 0x7e, 0x0d,
+       0xf0, 0x36, 0x1d, 0xe5, 0xe1, 0xf8, 0x60, 0xfe, 0x06, 0x94, 0x17, 0x94,
+       0xcf, 0x28, 0xd1, 0xe2, 0x42, 0xf5, 0x45, 0x26, 0x95, 0xcf, 0x6a, 0x92,
+       0xf5, 0xb3, 0xee, 0x27, 0x79, 0xda, 0x28, 0xfb, 0xcb, 0xa6, 0xbc, 0xc4,
+       0x23, 0xf3, 0xf5, 0x2b, 0x21, 0xbc, 0xe6, 0x0a, 0x7d, 0xe1, 0x73, 0xbd,
+       0x83, 0xe5, 0x0b, 0xdb, 0x79, 0xfb, 0x49, 0x8f, 0xe5, 0xbc, 0x73, 0x4e,
+       0x7e, 0x68, 0x09, 0x83, 0xcb, 0xfa, 0xb0, 0xbc, 0x2f, 0xac, 0xfe, 0x43,
+       0xe7, 0xd1, 0x2f, 0x8d, 0x61, 0xed, 0xef, 0x0e, 0x2b, 0x6f, 0x0e, 0xcb,
+       0xaf, 0x0b, 0xcb, 0x37, 0xe9, 0xdb, 0x97, 0xcd, 0x53, 0x88, 0x0f, 0xcb,
+       0x80, 0x1e, 0x10, 0x11, 0xe7, 0xe3, 0xcb, 0x9b, 0xd2, 0x7b, 0xec, 0xd4,
+       0x1e, 0x7d, 0xaa, 0xd8, 0xc8, 0x6e, 0xd3, 0xf1, 0xd5, 0x94, 0x06, 0x9e,
+       0xbf, 0xfd, 0xb1, 0x11, 0x25, 0x4d, 0xb6, 0x90, 0x7c, 0xba, 0xbb, 0x24,
+       0x94, 0x2f, 0xe4, 0xbd, 0x60, 0x4b, 0x22, 0x23, 0xbe, 0x30, 0xf5, 0x21,
+       0x2f, 0x4b, 0xd2, 0xf5, 0xfe, 0x59, 0xcf, 0x7a, 0x86, 0x86, 0xeb, 0x5b,
+       0x5e, 0xfe, 0x09, 0xfe, 0x33, 0x8d, 0xf6, 0x77, 0x74, 0x76, 0xc1, 0x4e,
+       0x55, 0x9f, 0xef, 0x50, 0xe5, 0xbc, 0xaf, 0x7a, 0x67, 0xb9, 0x2d, 0x64,
+       0x1f, 0x94, 0x5d, 0x59, 0x82, 0xf1, 0x95, 0xbe, 0xf7, 0x5b, 0x26, 0x94,
+       0x4c, 0xcc, 0x0c, 0xb1, 0x4b, 0x7c, 0xe3, 0x4b, 0xb4, 0x90, 0x75, 0xca,
+       0xfa, 0x93, 0xbf, 0x3f, 0xab, 0xe2, 0x78, 0x77, 0xa6, 0x8f, 0x2f, 0xd9,
+       0x88, 0xfb, 0x39, 0x85, 0x62, 0x1f, 0xd2, 0xc9, 0x53, 0xd0, 0x6b, 0x2a,
+       0xea, 0xcd, 0x1a, 0x11, 0x8f, 0x99, 0x8c, 0xe7, 0x63, 0xb1, 0x5e, 0x74,
+       0x60, 0xd0, 0xb2, 0x50, 0x3b, 0x84, 0xb5, 0x0e, 0xc6, 0x75, 0x76, 0xfc,
+       0x8c, 0xdf, 0x1b, 0xf0, 0x35, 0x00, 0x7e, 0x30, 0xbe, 0xc6, 0xdc, 0x66,
+       0x8c, 0xa7, 0x74, 0xc4, 0xc5, 0xad, 0x78, 0x06, 0xea, 0xef, 0xfc, 0x99,
+       0xba, 0x02, 0xf5, 0xe8, 0xfe, 0x15, 0x09, 0x74, 0x2e, 0xe9, 0x4f, 0xe9,
+       0xdc, 0xff, 0xdc, 0x19, 0xd7, 0x2f, 0xb9, 0x02, 0xf2, 0x1d, 0x31, 0xb7,
+       0x9b, 0xf1, 0xbd, 0x92, 0x8e, 0x7b, 0x26, 0x51, 0xba, 0x43, 0xd5, 0x56,
+       0x77, 0x03, 0xaf, 0x3d, 0xf8, 0xd8, 0xb5, 0x25, 0xb6, 0x4b, 0xb0, 0x3c,
+       0x8e, 0xe0, 0xf3, 0x8b, 0xf4, 0x49, 0x25, 0xf5, 0x40, 0xd7, 0xbf, 0xc4,
+       0x4b, 0x3b, 0xd0, 0xde, 0xeb, 0x74, 0x24, 0xe3, 0xbd, 0x06, 0xb6, 0xc6,
+       0x44, 0xfb, 0x7a, 0x8c, 0xb9, 0x9f, 0x24, 0xba, 0xb9, 0xdf, 0x32, 0x12,
+       0xfd, 0xe7, 0xb2, 0xfa, 0xcb, 0x68, 0xdf, 0xaa, 0xfc, 0x57, 0xd3, 0x27,
+       0xd3, 0xbd, 0x85, 0x55, 0x26, 0xda, 0xcf, 0x80, 0x3f, 0x3a, 0x7f, 0xe2,
+       0x5d, 0x33, 0x89, 0xce, 0x3d, 0xcd, 0x6b, 0x14, 0xa9, 0xef, 0x1a, 0x4a,
+       0xdf, 0xf8, 0xe1, 0xe9, 0x06, 0xbc, 0x1f, 0xd9, 0xfd, 0x84, 0x42, 0xf7,
+       0x25, 0xae, 0xfc, 0xba, 0xf5, 0x8f, 0x23, 0xf0, 0xdc, 0x63, 0xd3, 0x00,
+       0x37, 0xa2, 0xe6, 0x75, 0xb0, 0xeb, 0xf1, 0x3c, 0xd2, 0xa7, 0xeb, 0x86,
+       0xd0, 0x3d, 0x89, 0x83, 0x51, 0xb5, 0x74, 0xee, 0x13, 0xea, 0x33, 0xac,
+       0x5f, 0xf5, 0x9d, 0xeb, 0xdd, 0x69, 0xb9, 0x58, 0x5f, 0x75, 0xe0, 0xd1,
+       0x8a, 0xc3, 0xf0, 0x1d, 0xed, 0xe1, 0xc3, 0xf7, 0xaa, 0x4f, 0xe1, 0xfd,
+       0xc3, 0xb2, 0x58, 0x7b, 0x34, 0x9e, 0x97, 0x3e, 0xfc, 0xbd, 0xeb, 0x5d,
+       0xb4, 0x6b, 0xa1, 0xdc, 0xb1, 0x12, 0xbe, 0x1f, 0x5e, 0xb5, 0x20, 0x19,
+       0xed, 0xac, 0xc3, 0x8a, 0x2b, 0x16, 0xdf, 0x12, 0x79, 0xf1, 0xb1, 0x59,
+       0x25, 0xa9, 0x69, 0x78, 0x2f, 0xdf, 0x22, 0xf0, 0x39, 0xcb, 0x5e, 0x06,
+       0x7c, 0x5e, 0x66, 0xe8, 0xa1, 0x17, 0xd2, 0x1f, 0x95, 0xf1, 0x3c, 0xff,
+       0x62, 0xfa, 0xac, 0x92, 0x4d, 0x30, 0xff, 0xc3, 0x8f, 0x0e, 0xa1, 0x73,
+       0x5f, 0x83, 0x33, 0xb4, 0xd6, 0x74, 0xc0, 0xd3, 0xe9, 0x0c, 0x6d, 0x2b,
+       0xa6, 0x07, 0xc5, 0x7d, 0xe5, 0x37, 0x7e, 0xe0, 0xfb, 0x85, 0xbf, 0x3f,
+       0x51, 0x9e, 0x8c, 0xf4, 0xf4, 0x7b, 0x41, 0xc7, 0xaf, 0x9f, 0x29, 0x4f,
+       0x2e, 0x0f, 0xb1, 0x77, 0x2a, 0xbf, 0x30, 0x12, 0xde, 0xdf, 0x30, 0xbb,
+       0x96, 0xe3, 0x3c, 0xdf, 0x88, 0xce, 0x52, 0xe8, 0x7c, 0x36, 0x6b, 0x4d,
+       0xc0, 0x78, 0xf7, 0x3c, 0xe1, 0x7f, 0x00, 0xfd, 0xae, 0xd8, 0x16, 0xc1,
+       0xee, 0x79, 0x38, 0x5d, 0x25, 0x3c, 0x75, 0xdc, 0x97, 0x94, 0x8f, 0x78,
+       0x0d, 0xd2, 0x71, 0x25, 0xc9, 0x4b, 0xf2, 0x1b, 0x20, 0xff, 0xf6, 0x63,
+       0xe5, 0xa4, 0xd7, 0x0e, 0x59, 0x56, 0xb0, 0x83, 0x68, 0x37, 0x8a, 0xf3,
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+       0x91, 0x74, 0x77, 0x37, 0xca, 0x1b, 0xa0, 0x17, 0x8c, 0x8f, 0x85, 0xaf,
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+       0xd4, 0xf9, 0x07, 0x77, 0x9c, 0x93, 0x0f, 0x0f, 0x3f, 0xb6, 0xac, 0x64,
+       0xa3, 0xad, 0x6f, 0x3e, 0xac, 0x12, 0x7e, 0xca, 0xe4, 0x27, 0x4c, 0x74,
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+       0x8d, 0xfb, 0x91, 0xb2, 0x5e, 0xd5, 0xca, 0x9f, 0x0d, 0xe6, 0xf5, 0xc0,
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+       0xf4, 0x1d, 0xf0, 0x78, 0x2a, 0x0b, 0xb9, 0xcf, 0x3c, 0xaf, 0x71, 0xaf,
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+       0x02, 0xc9, 0x45, 0xf7, 0x7e, 0xae, 0xcf, 0xe0, 0xf6, 0xeb, 0xc4, 0x0c,
+       0x7e, 0xde, 0xa9, 0x2c, 0xdb, 0x4d, 0xf7, 0x5f, 0xaa, 0x1f, 0xb0, 0xb8,
+       0x57, 0xe6, 0xf0, 0x7e, 0x7a, 0xee, 0x55, 0xe3, 0x39, 0x27, 0x43, 0x67,
+       0x25, 0xed, 0x3f, 0xfe, 0xd6, 0x42, 0x71, 0x91, 0x9a, 0xc6, 0x28, 0x2d,
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+       0x2b, 0x36, 0xd8, 0xef, 0x1e, 0x03, 0x6b, 0xc2, 0xb8, 0x0b, 0xd6, 0xbf,
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+       0x74, 0x17, 0x7d, 0x7f, 0x69, 0xc3, 0x64, 0xc6, 0xdb, 0xef, 0x42, 0x3a,
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+       0x39, 0xb7, 0x2e, 0x3a, 0xb7, 0x57, 0x23, 0xee, 0x2b, 0xf6, 0xc8, 0xa7,
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+       0xfe, 0x30, 0x83, 0xeb, 0x83, 0xd7, 0x44, 0xba, 0x18, 0xe8, 0x02, 0xef,
+       0x67, 0x31, 0xbc, 0x9e, 0x28, 0xe5, 0x04, 0x14, 0x7d, 0xb1, 0x75, 0x03,
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+       0xfc, 0x0e, 0xac, 0x4a, 0xc9, 0x6e, 0x03, 0xb8, 0x1d, 0xdf, 0x4c, 0xcf,
+       0x54, 0x12, 0xbd, 0x1a, 0x43, 0xc6, 0x93, 0x74, 0x23, 0xc7, 0x2b, 0x7a,
+       0x6e, 0xfa, 0x75, 0xb8, 0x5e, 0xe8, 0x3f, 0x80, 0xfd, 0xcb, 0x71, 0xf7,
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+       0xa7, 0xe4, 0xcb, 0xa2, 0x86, 0x39, 0xd7, 0x8d, 0xc4, 0x73, 0xbf, 0xbe,
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+       0x3b, 0x49, 0x67, 0xf8, 0x87, 0xf1, 0x28, 0x39, 0xdf, 0x3d, 0x4e, 0x1e,
+       0xc7, 0x0d, 0x9f, 0xb7, 0x94, 0x43, 0x72, 0xde, 0x45, 0xf7, 0xcc, 0xba,
+       0x0e, 0xbf, 0xcb, 0xf9, 0x4b, 0x7a, 0x95, 0xf4, 0x29, 0xe1, 0x28, 0xe9,
+       0x54, 0xde, 0x7f, 0x0b, 0xa7, 0x57, 0xa2, 0x35, 0xa9, 0x3f, 0x55, 0x9d,
+       0xbc, 0x27, 0xfd, 0x78, 0x4d, 0xe6, 0x57, 0x66, 0xaf, 0xad, 0xf7, 0xf7,
+       0xf0, 0xbc, 0xb4, 0x83, 0x0e, 0x8a, 0xf3, 0xdb, 0xdd, 0x49, 0x8c, 0xc7,
+       0xeb, 0x1b, 0x53, 0x77, 0x85, 0xde, 0xf7, 0x81, 0x3f, 0x5b, 0xa8, 0xde,
+       0x09, 0xd1, 0x27, 0xcd, 0xc6, 0x10, 0x7d, 0x22, 0xf5, 0x7f, 0x4d, 0xa2,
+       0x76, 0x14, 0xf1, 0x55, 0x9c, 0xc9, 0xcf, 0x95, 0x1c, 0x63, 0xad, 0xe6,
+       0x02, 0xe8, 0x77, 0xf1, 0x91, 0xce, 0xc9, 0xf8, 0x4e, 0xa2, 0xb4, 0x3b,
+       0xaf, 0xfc, 0x3a, 0xa0, 0xc6, 0x61, 0x1c, 0x6a, 0x3b, 0x3f, 0x7f, 0x26,
+       0xe1, 0xbd, 0xf8, 0xc4, 0x2e, 0xa2, 0xfb, 0x6a, 0x71, 0x2f, 0xa9, 0xec,
+       0xde, 0x0f, 0x4a, 0xc6, 0x22, 0x7d, 0xff, 0xc6, 0x44, 0xfb, 0x31, 0x65,
+       0xab, 0x26, 0xd1, 0xfd, 0xe3, 0x05, 0x9b, 0xe6, 0xe6, 0x21, 0xfd, 0xe0,
+       0x7d, 0x06, 0x94, 0xe7, 0x47, 0x37, 0x8e, 0x19, 0xcd, 0x9f, 0xf3, 0x72,
+       0x24, 0xcf, 0xc4, 0x7b, 0x0d, 0x1b, 0x1f, 0x9c, 0x79, 0x0b, 0x7c, 0x9f,
+       0xd7, 0xa6, 0xba, 0x49, 0xae, 0x43, 0x3f, 0xc8, 0xaf, 0x65, 0x77, 0x8e,
+       0x66, 0x48, 0x2f, 0x07, 0xa3, 0xba, 0x4a, 0xc6, 0xa3, 0xbd, 0xfe, 0x53,
+       0xd5, 0x81, 0xf6, 0xfa, 0x84, 0x4d, 0x63, 0xee, 0xc6, 0xfa, 0x13, 0xec,
+       0xfd, 0xe2, 0x71, 0x3d, 0xda, 0xc6, 0x04, 0xca, 0x6b, 0xc6, 0x38, 0xd2,
+       0x0b, 0xd2, 0xce, 0x95, 0xe7, 0xf2, 0x1a, 0x4c, 0x9c, 0x1e, 0x46, 0x65,
+       0x72, 0xfe, 0xb9, 0xa4, 0x27, 0x55, 0xc4, 0x79, 0xbc, 0x86, 0xc1, 0xb8,
+       0x7f, 0xde, 0xbd, 0x21, 0x8a, 0xde, 0x41, 0x2a, 0x35, 0x8b, 0x7b, 0x9c,
+       0xaf, 0xa5, 0x90, 0x3f, 0x51, 0x63, 0xc6, 0x2b, 0x85, 0x74, 0x2f, 0x94,
+       0xec, 0xb0, 0xf9, 0x66, 0x66, 0x4d, 0xe3, 0xe7, 0x9d, 0xad, 0x69, 0xf0,
+       0x7d, 0xaf, 0xa9, 0xf3, 0x4e, 0xd4, 0x1f, 0x7b, 0xef, 0xb4, 0x8f, 0xa4,
+       0x73, 0xf5, 0xea, 0x77, 0x79, 0xe5, 0xdc, 0x7e, 0xe6, 0xfb, 0x85, 0x09,
+       0xfa, 0x77, 0x87, 0xe4, 0x3c, 0x46, 0x8a, 0xf1, 0xc3, 0xfb, 0x93, 0xed,
+       0xf7, 0x88, 0xf3, 0xc6, 0x07, 0xc5, 0xfc, 0x8f, 0x36, 0xfe, 0x66, 0x26,
+       0xea, 0xbf, 0xa3, 0x9b, 0x07, 0x39, 0x71, 0xdd, 0x9f, 0xbf, 0x16, 0x45,
+       0xe7, 0xf0, 0x3f, 0x0f, 0x7b, 0xb7, 0xf0, 0x62, 0xef, 0x69, 0x01, 0xdd,
+       0x86, 0xdd, 0x83, 0x5a, 0xc9, 0xe5, 0x45, 0xa6, 0xfe, 0x9c, 0x96, 0xa4,
+       0xf3, 0xf3, 0xde, 0x53, 0xfa, 0x28, 0x31, 0x6c, 0x3f, 0xe0, 0xdc, 0xe7,
+       0x8b, 0x4e, 0xd4, 0x31, 0xba, 0x4f, 0x6d, 0x01, 0x5f, 0x98, 0xec, 0x99,
+       0x98, 0xef, 0xb7, 0xe1, 0xb9, 0xbe, 0xca, 0x16, 0x8b, 0x03, 0xef, 0xb3,
+       0x1c, 0x42, 0xba, 0xa7, 0xf3, 0x3c, 0x2a, 0xbf, 0x77, 0x6b, 0xe5, 0x7c,
+       0x70, 0x68, 0xeb, 0x48, 0x3f, 0xfa, 0x8d, 0x95, 0x1f, 0xf1, 0xfb, 0x45,
+       0xbb, 0xd6, 0xde, 0x43, 0xe7, 0x0a, 0x2a, 0xc0, 0xae, 0xc4, 0xa3, 0x54,
+       0x3d, 0x76, 0xf2, 0x43, 0x6b, 0x67, 0x22, 0x1b, 0x9c, 0x72, 0x7b, 0x57,
+       0xe3, 0x3b, 0x2f, 0xa7, 0x36, 0xf3, 0x73, 0x10, 0xbd, 0xde, 0x2d, 0xd8,
+       0xbb, 0x6d, 0x77, 0xe8, 0xbb, 0x05, 0x17, 0x6b, 0x1f, 0x5f, 0xa8, 0x5d,
+       0x2c, 0xe3, 0x0a, 0x35, 0x99, 0xfa, 0x7b, 0xf1, 0x12, 0xae, 0xd2, 0x3f,
+       0x7a, 0x03, 0xf0, 0x3f, 0x6e, 0x54, 0x10, 0x4e, 0x5f, 0xd6, 0xcd, 0x27,
+       0xbb, 0xf8, 0x44, 0x9d, 0x97, 0xd2, 0x93, 0xca, 0x81, 0x07, 0x26, 0x20,
+       0xdd, 0xda, 0xe3, 0xe8, 0xbc, 0xfe, 0xef, 0xdb, 0x1e, 0x54, 0xf1, 0x9d,
+       0x95, 0xea, 0xed, 0x23, 0xbf, 0x43, 0xff, 0x76, 0xbc, 0x2d, 0xce, 0x81,
+       0xfc, 0xfa, 0x65, 0xdd, 0x0a, 0xda, 0xef, 0x3c, 0x51, 0x57, 0x4b, 0x69,
+       0xf0, 0x5d, 0x57, 0x3f, 0xa5, 0x57, 0x6e, 0xef, 0xa0, 0x76, 0x5f, 0xb6,
+       0x8d, 0x6e, 0xc7, 0x7b, 0xae, 0xaf, 0xdb, 0xe2, 0x84, 0xbc, 0x0f, 0xdf,
+       0xd7, 0xe1, 0x78, 0xec, 0xeb, 0xfe, 0xae, 0x5c, 0xd7, 0xb1, 0x9f, 0x72,
+       0x7c, 0xca, 0x79, 0x1f, 0xdb, 0x3c, 0x37, 0x16, 0xd7, 0xd5, 0xf1, 0x78,
+       0x42, 0xfb, 0x15, 0x88, 0xc7, 0x98, 0x38, 0x07, 0xda, 0x77, 0x55, 0xe2,
+       0x9c, 0xc7, 0xe1, 0x75, 0xdc, 0x7e, 0x3e, 0x62, 0x8d, 0x7b, 0x66, 0x2a,
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+       0x4c, 0xfc, 0x5e, 0xf9, 0x9a, 0xe2, 0x40, 0xbb, 0xdf, 0xfd, 0xda, 0xf4,
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+       0x9a, 0x2e, 0x9f, 0xe3, 0x2b, 0xd6, 0xd5, 0x1f, 0xd0, 0xe4, 0xd1, 0xe5,
+       0x07, 0xb5, 0xcc, 0xd6, 0xd5, 0x1f, 0xb2, 0xce, 0xab, 0x2b, 0xbf, 0xc4,
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+       0xcb, 0x5f, 0xd9, 0xdd, 0xa6, 0xab, 0x7f, 0xf5, 0x99, 0x80, 0x2e, 0x5f,
+       0xc0, 0xf6, 0xea, 0xea, 0x17, 0x59, 0xdf, 0xd7, 0xe5, 0x27, 0x39, 0xfe,
+       0xa6, 0xab, 0x7f, 0x4d, 0xea, 0x01, 0x5d, 0xf9, 0xb5, 0xae, 0xa3, 0xba,
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+       0xdc, 0xff, 0xd4, 0xb5, 0xf7, 0x15, 0x8a, 0x77, 0xa5, 0x5f, 0x52, 0xdc,
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+       0xbb, 0x88, 0x3e, 0x0f, 0xc5, 0x7d, 0x9c, 0x78, 0xb0, 0x0f, 0xe5, 0x14,
+       0xde, 0xbb, 0x76, 0xf2, 0x73, 0x31, 0xa5, 0x14, 0x3f, 0x4a, 0x24, 0x3b,
+       0x87, 0x54, 0x91, 0x0b, 0xcf, 0xe9, 0x80, 0x1d, 0x10, 0x8b, 0xde, 0x55,
+       0x4e, 0x0e, 0xda, 0xc9, 0x31, 0x41, 0x7b, 0x2c, 0xf3, 0x6c, 0xc8, 0x39,
+       0xb9, 0xf3, 0xd9, 0x63, 0xd7, 0x64, 0x33, 0x9a, 0xc7, 0x5d, 0xd9, 0xde,
+       0xfc, 0xec, 0x24, 0xf4, 0x3f, 0xb6, 0x4e, 0xa6, 0x77, 0xc1, 0x99, 0x6f,
+       0x35, 0xce, 0x43, 0xbe, 0x73, 0xf7, 0x6e, 0xd8, 0x7b, 0xc8, 0x32, 0xbd,
+       0xd6, 0x7a, 0x84, 0x19, 0x43, 0xec, 0xbf, 0xbd, 0x51, 0x2d, 0x99, 0xa3,
+       0xce, 0xe1, 0xbf, 0x5f, 0x6b, 0x3d, 0xc1, 0xf0, 0x9d, 0xe5, 0x9e, 0x7e,
+       0x45, 0xbc, 0x42, 0x81, 0xf5, 0x2d, 0x0b, 0xe9, 0xff, 0x01, 0xf0, 0x17,
+       0x8c, 0x03, 0x19, 0x6b, 0xa9, 0x03, 0xbe, 0xc1, 0x7d, 0xe1, 0x3a, 0x07,
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+       0x0d, 0xa5, 0xf4, 0xb1, 0x3a, 0x37, 0x95, 0xaf, 0xaf, 0x1b, 0x47, 0xf9,
+       0x27, 0xeb, 0x34, 0xca, 0xfb, 0xeb, 0x8a, 0x29, 0x7d, 0xaa, 0xce, 0x43,
+       0xdf, 0x37, 0xd6, 0xcd, 0xa6, 0xfc, 0x33, 0xe0, 0x17, 0x63, 0xba, 0x19,
+       0xfc, 0x64, 0x4c, 0x9f, 0x05, 0x7f, 0x17, 0xcb, 0xb7, 0x80, 0xff, 0x8b,
+       0xf9, 0x17, 0xea, 0x7c, 0x94, 0xb6, 0xd6, 0x35, 0xd1, 0xf7, 0x97, 0xea,
+       0x5a, 0x28, 0xbf, 0xbd, 0x6e, 0x1d, 0xe5, 0x7f, 0x5b, 0xe7, 0xa7, 0xb4,
+       0xad, 0x6e, 0x33, 0xa5, 0xbf, 0xab, 0x6b, 0xa5, 0xf2, 0xf6, 0xba, 0x36,
+       0xca, 0xbf, 0x5e, 0x17, 0xa0, 0x7c, 0xa0, 0x6e, 0x0f, 0xe5, 0x77, 0xd4,
+       0x75, 0x52, 0x7e, 0x57, 0xdd, 0x3e, 0xca, 0xef, 0xae, 0xeb, 0xa2, 0x74,
+       0x4f, 0xdd, 0x11, 0x4a, 0xdf, 0xaa, 0xeb, 0xa6, 0xf2, 0xb7, 0xeb, 0xce,
+       0x50, 0xfe, 0x98, 0x88, 0xb7, 0x2e, 0xcf, 0x56, 0x74, 0xf7, 0x95, 0x64,
+       0x5e, 0xbe, 0xc7, 0x20, 0xed, 0xbf, 0x69, 0x68, 0xbf, 0x23, 0x71, 0x8c,
+       0x33, 0x7d, 0xa9, 0xb3, 0xdf, 0xc3, 0xec, 0xe8, 0x70, 0x7c, 0xc8, 0x71,
+       0x82, 0xef, 0x27, 0x0c, 0x7e, 0xaa, 0x21, 0xc4, 0x7f, 0xf2, 0x65, 0x73,
+       0xff, 0x4a, 0xbe, 0xc7, 0x10, 0xfe, 0x8e, 0x02, 0x13, 0xf6, 0xa9, 0x7c,
+       0xf7, 0x54, 0xbe, 0xd7, 0x50, 0x29, 0xe6, 0x55, 0x25, 0xf8, 0x61, 0x0c,
+       0xd2, 0xe7, 0x50, 0xa2, 0xcf, 0xb7, 0x2f, 0xc6, 0x5f, 0x90, 0xfe, 0xa0,
+       0x2d, 0xc9, 0xdb, 0x42, 0xf4, 0x99, 0x65, 0xf0, 0x91, 0x3f, 0x6c, 0xe3,
+       0xf7, 0x89, 0x2f, 0x4f, 0xf2, 0x3e, 0x98, 0x3d, 0x06, 0xf7, 0x0b, 0x2b,
+       0x76, 0xd3, 0x78, 0x0e, 0x37, 0xed, 0x1b, 0x96, 0x58, 0x02, 0x49, 0xb3,
+       0x72, 0xe9, 0x9d, 0x70, 0x8a, 0xcb, 0xf5, 0x35, 0x5e, 0x8d, 0x38, 0xf7,
+       0xdd, 0x67, 0xf9, 0xeb, 0x47, 0x33, 0xd1, 0x9e, 0x2e, 0xfe, 0x41, 0xa5,
+       0x77, 0xb6, 0xde, 0x35, 0xd9, 0x67, 0xa3, 0xff, 0xff, 0x8c, 0xc0, 0xc3,
+       0x33, 0xd9, 0x06, 0x5d, 0xba, 0x2d, 0xc9, 0xbb, 0x09, 0xe7, 0xf3, 0xad,
+       0xbd, 0xf6, 0x36, 0x03, 0xcc, 0xff, 0xdb, 0xab, 0x96, 0x3e, 0x73, 0x47,
+       0x4e, 0xd0, 0x4f, 0xbe, 0x1e, 0x5d, 0x4d, 0xf0, 0x6f, 0xa6, 0x33, 0x97,
+       0x89, 0xce, 0x15, 0x32, 0xed, 0xcd, 0x1c, 0xb4, 0x9b, 0xc0, 0xb0, 0xc2,
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+       0xe6, 0x61, 0x6c, 0x91, 0x3c, 0xd6, 0x27, 0x8e, 0x62, 0xcc, 0xe5, 0xf8,
+       0x4a, 0x55, 0x1a, 0xd4, 0x6f, 0x97, 0x4b, 0x37, 0x9b, 0x9d, 0x8c, 0x15,
+       0xca, 0xf3, 0x6b, 0xd7, 0xc4, 0xd4, 0xe5, 0xe4, 0xf2, 0xfb, 0xf6, 0x48,
+       0xd1, 0xfa, 0x18, 0xf7, 0x76, 0xd1, 0x0a, 0xed, 0xcb, 0x42, 0x13, 0x36,
+       0xdb, 0x05, 0xbe, 0x0e, 0x96, 0xc5, 0xd8, 0xbd, 0x72, 0xb9, 0x6f, 0x0d,
+       0xe0, 0x51, 0x38, 0x8f, 0x05, 0x11, 0xee, 0x03, 0x4e, 0x63, 0x68, 0x07,
+       0xb4, 0xaf, 0xc0, 0xf3, 0x12, 0x71, 0xfd, 0x12, 0xad, 0xff, 0x66, 0xd6,
+       0xee, 0xd0, 0xc1, 0xfa, 0xc7, 0xc8, 0xc6, 0x72, 0x26, 0x50, 0xff, 0x30,
+       0xb3, 0x5f, 0x7b, 0xff, 0x46, 0x59, 0xa6, 0xe7, 0xf1, 0xef, 0x5d, 0xa9,
+       0x9f, 0x6e, 0xe2, 0x35, 0xf5, 0x63, 0xfa, 0x2b, 0x8c, 0x87, 0xed, 0xc2,
+       0x15, 0xc6, 0x31, 0x0b, 0x0b, 0xcd, 0x11, 0x58, 0xfb, 0x26, 0x03, 0xfc,
+       0x0f, 0x3c, 0x0f, 0x66, 0xd8, 0x42, 0x3b, 0x01, 0x5e, 0x9d, 0x06, 0xb6,
+       0xcc, 0x07, 0x70, 0xef, 0xb4, 0xf0, 0xf2, 0x88, 0x93, 0xd3, 0xdf, 0xb3,
+       0xce, 0xaa, 0xf1, 0x4e, 0xa0, 0xa3, 0xf1, 0x4e, 0x7e, 0xae, 0x9d, 0x96,
+       0xa0, 0x54, 0x85, 0xf3, 0x97, 0xea, 0x3c, 0x3b, 0x10, 0x9d, 0x5b, 0x9d,
+       0x3f, 0xcf, 0x83, 0xf9, 0xbe, 0xfa, 0xba, 0xc8, 0x36, 0xca, 0x51, 0xfc,
+       0xec, 0x40, 0x3c, 0x80, 0xf7, 0x0a, 0xc6, 0x24, 0x7b, 0x71, 0x1e, 0xf6,
+       0x8f, 0xe6, 0x50, 0x01, 0xcc, 0xf3, 0xa5, 0x31, 0x2f, 0x75, 0xa4, 0x41,
+       0xbd, 0xe0, 0x3b, 0x1e, 0x8f, 0x1e, 0xfa, 0x6f, 0x62, 0x1e, 0x2b, 0xe2,
+       0x49, 0xf0, 0x51, 0x1d, 0xdb, 0x09, 0xf5, 0x17, 0x26, 0xe6, 0xa7, 0xcd,
+       0x87, 0xee, 0x25, 0x93, 0x7e, 0x90, 0xe6, 0x07, 0x7c, 0x39, 0x8d, 0x7c,
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+       0xfa, 0xa1, 0xfc, 0xd3, 0x09, 0xff, 0x18, 0x09, 0xd6, 0xf9, 0xb8, 0x32,
+       0xcf, 0x76, 0x43, 0xa4, 0x99, 0xce, 0x73, 0x92, 0x8d, 0xe1, 0xbe, 0x19,
+       0xdb, 0x9c, 0xa4, 0x73, 0x40, 0x7f, 0x07, 0x1c, 0xd2, 0x75, 0x8c, 0xe9,
+       0x46, 0xf1, 0xd2, 0x68, 0x90, 0x6e, 0xc7, 0x7e, 0xc6, 0x75, 0x46, 0x16,
+       0x84, 0xf5, 0x18, 0xff, 0x72, 0x9d, 0xd9, 0x07, 0xe3, 0xb5, 0x5f, 0x34,
+       0xd5, 0x20, 0x1f, 0x61, 0x2c, 0x92, 0xa4, 0x9b, 0x02, 0xcf, 0x2d, 0x7e,
+       0x29, 0x15, 0x9e, 0x6f, 0x0e, 0xea, 0x88, 0x2f, 0xb4, 0xcb, 0xb6, 0x90,
+       0x00, 0xe3, 0x6e, 0xb2, 0x95, 0x1f, 0x95, 0xa1, 0x1e, 0x94, 0x74, 0x9e,
+       0x02, 0x84, 0xa3, 0x5b, 0x47, 0x70, 0xec, 0xb0, 0x7d, 0x39, 0xa4, 0x87,
+       0xf1, 0x44, 0x61, 0x4d, 0x03, 0xcb, 0x87, 0xf5, 0x4a, 0x2f, 0x9b, 0x9d,
+       0xf0, 0x3c, 0xe4, 0xd6, 0x49, 0x48, 0xe7, 0x21, 0xef, 0x82, 0x1a, 0xac,
+       0x07, 0xfd, 0xa2, 0xa7, 0x40, 0x56, 0x18, 0x04, 0xb6, 0xfb, 0xd3, 0x42,
+       0x1b, 0x71, 0x5c, 0x36, 0xf0, 0xd3, 0x09, 0xd8, 0x5e, 0xc7, 0x3c, 0x08,
+       0x87, 0x75, 0x99, 0xff, 0xde, 0x97, 0x04, 0xf5, 0xf6, 0xc5, 0x92, 0x47,
+       0xcf, 0x7b, 0xcb, 0xe2, 0x64, 0xc6, 0x46, 0xe1, 0x5f, 0x30, 0x65, 0xbb,
+       0xa1, 0x7f, 0x6d, 0x12, 0xae, 0x63, 0x09, 0xef, 0x0f, 0x7f, 0x79, 0xe6,
+       0x03, 0x1d, 0xa6, 0x98, 0xf8, 0xf9, 0x7d, 0xa3, 0x77, 0xb6, 0x94, 0x57,
+       0x8a, 0xcf, 0xc5, 0x60, 0x3f, 0xe7, 0x4b, 0xc2, 0x65, 0x20, 0x44, 0xd1,
+       0xe0, 0x31, 0x7b, 0xa0, 0x7d, 0xbc, 0xad, 0xbc, 0xc6, 0x0b, 0xa5, 0x98,
+       0x5c, 0x6e, 0x96, 0x61, 0x9f, 0x1d, 0x52, 0xb9, 0x79, 0x39, 0xed, 0x9f,
+       0xd9, 0x18, 0xcc, 0x93, 0xce, 0x38, 0x7f, 0x6a, 0x97, 0x74, 0x35, 0x21,
+       0xa5, 0xfd, 0x2e, 0xa4, 0x77, 0x91, 0x1d, 0x72, 0x4d, 0x26, 0x52, 0xa2,
+       0xf6, 0x0e, 0xdb, 0x96, 0x5e, 0x84, 0x87, 0x78, 0x37, 0x63, 0x4e, 0x19,
+       0xd7, 0x07, 0xf3, 0xa9, 0x7c, 0x0f, 0xe0, 0x61, 0xce, 0xbf, 0xe1, 0xa8,
+       0x0c, 0xfb, 0xe8, 0xbc, 0x27, 0x8d, 0xf6, 0x21, 0x0a, 0x1e, 0xaa, 0xb3,
+       0xbb, 0x45, 0x5a, 0x77, 0x96, 0x6c, 0x0d, 0xb3, 0xf1, 0x70, 0x8e, 0xc6,
+       0x79, 0x47, 0x19, 0xf0, 0x8f, 0x2c, 0xf3, 0xfd, 0x73, 0xb1, 0x3e, 0xaa,
+       0x41, 0xfc, 0xa0, 0x3f, 0x86, 0x4f, 0x8f, 0xf4, 0x6b, 0xeb, 0x19, 0xb5,
+       0xda, 0x7a, 0x3a, 0x83, 0xba, 0x39, 0x3a, 0xef, 0x6f, 0x14, 0xf9, 0x11,
+       0x0f, 0xb7, 0x78, 0x78, 0x8c, 0x92, 0x3a, 0x4e, 0xe0, 0xfa, 0x47, 0xf9,
+       0x45, 0x7a, 0x18, 0xbf, 0xfe, 0xa7, 0xa4, 0x27, 0x52, 0x2b, 0x19, 0xae,
+       0xd3, 0x46, 0xeb, 0xcc, 0xb4, 0xdd, 0x59, 0x09, 0x10, 0x82, 0xa1, 0x7d,
+       0x6b, 0x10, 0xff, 0xfe, 0xd6, 0x75, 0x8e, 0x97, 0x16, 0x98, 0x9d, 0x30,
+       0xff, 0x78, 0xbb, 0x0e, 0xc1, 0xc9, 0x26, 0xb0, 0x81, 0xb5, 0x38, 0xee,
+       0x26, 0x05, 0xdf, 0x3b, 0x9d, 0xfc, 0x3c, 0xa3, 0x74, 0xa5, 0x57, 0xe9,
+       0x72, 0x24, 0xd2, 0xe5, 0x98, 0x56, 0x1d, 0x0b, 0xc6, 0xc8, 0x1d, 0x67,
+       0xd0, 0xca, 0x82, 0x31, 0xf3, 0xe5, 0x77, 0xa6, 0x69, 0xea, 0x05, 0x9b,
+       0xb3, 0x34, 0xfd, 0xc7, 0x6e, 0xcd, 0xd3, 0xb4, 0x8f, 0x0b, 0x15, 0x6b,
+       0xda, 0x4b, 0x76, 0x97, 0x6b, 0xea, 0xa5, 0x5d, 0xd7, 0x6b, 0xfa, 0x4f,
+       0xe8, 0xae, 0xd2, 0xd4, 0xcb, 0xc2, 0x73, 0x34, 0xfd, 0x2b, 0x8e, 0x2e,
+       0xd0, 0xd4, 0x27, 0x45, 0x6e, 0xd7, 0xf4, 0xbf, 0xee, 0xe4, 0x9d, 0x9a,
+       0xf6, 0xa9, 0xfd, 0xf7, 0x69, 0xda, 0xa7, 0x7d, 0xb4, 0x4a, 0x53, 0xbf,
+       0x71, 0xe0, 0x21, 0x4d, 0x7f, 0x20, 0xe3, 0x86, 0xae, 0x04, 0x72, 0x32,
+       0x55, 0xe1, 0x57, 0x1d, 0x0e, 0x6f, 0xc4, 0x9b, 0x40, 0x9e, 0xab, 0x25,
+       0x93, 0xc4, 0x81, 0xc1, 0xf3, 0x00, 0xde, 0x69, 0x72, 0x00, 0x66, 0xc7,
+       0xcc, 0x97, 0xec, 0xb1, 0x02, 0x12, 0x47, 0xeb, 0xa0, 0x99, 0x48, 0x1f,
+       0x26, 0x29, 0x75, 0x92, 0xeb, 0xed, 0xf2, 0x5a, 0xc4, 0xe7, 0x14, 0x23,
+       0xe1, 0xb3, 0x88, 0xf2, 0x1c, 0xea, 0xab, 0x1e, 0x34, 0x86, 0x4c, 0x88,
+       0xff, 0x37, 0x79, 0x64, 0xe4, 0x2f, 0x26, 0x27, 0xe7, 0x63, 0xfb, 0x0a,
+       0xbd, 0xa3, 0x9d, 0xb0, 0xae, 0xca, 0x14, 0x33, 0xc9, 0x05, 0xd1, 0xc6,
+       0xfb, 0x89, 0xb6, 0x59, 0xa4, 0xa7, 0x8c, 0xde, 0x0a, 0x7c, 0xa9, 0x02,
+       0xea, 0x12, 0x1b, 0x6c, 0x4f, 0x42, 0xfe, 0xdc, 0x16, 0xf4, 0xb9, 0x5c,
+       0xd1, 0x75, 0x5b, 0xa4, 0xcd, 0x0c, 0xe9, 0xb7, 0x32, 0xa5, 0x86, 0xf5,
+       0xdb, 0xa2, 0xef, 0x8b, 0x92, 0x97, 0xf9, 0x93, 0x71, 0x3e, 0x99, 0xeb,
+       0x3f, 0x52, 0x90, 0xfa, 0x59, 0x64, 0x78, 0x3f, 0x66, 0x5f, 0x07, 0x74,
+       0x3a, 0x66, 0x43, 0x3e, 0xde, 0x0b, 0x72, 0x02, 0xc6, 0xef, 0x4a, 0xce,
+       0x16, 0x91, 0xfe, 0xba, 0xfe, 0x52, 0x5c, 0x4d, 0x65, 0xf2, 0xb4, 0x59,
+       0x88, 0xef, 0x65, 0x12, 0xfb, 0xce, 0xbf, 0x40, 0xff, 0x2e, 0x81, 0x1d,
+       0x65, 0xa0, 0x27, 0x75, 0xe9, 0xd8, 0x85, 0xe9, 0xb0, 0xef, 0x97, 0x6d,
+       0xe5, 0x8f, 0x83, 0xb8, 0x06, 0xd6, 0xe8, 0xd3, 0x23, 0xbf, 0x9b, 0xcc,
+       0x9a, 0xa9, 0x1c, 0xad, 0x63, 0x56, 0x2c, 0xb7, 0x0b, 0xfd, 0xab, 0x19,
+       0xf4, 0x73, 0x37, 0x9f, 0xa8, 0x1a, 0x09, 0xfd, 0x9e, 0x77, 0xf9, 0xbd,
+       0xb8, 0xef, 0xaf, 0x83, 0x0e, 0x81, 0xfb, 0xfa, 0xfa, 0x78, 0xae, 0x67,
+       0xad, 0xcb, 0x9c, 0x23, 0xa3, 0x5e, 0xd6, 0xe9, 0xec, 0x3a, 0x9a, 0x87,
+       0xeb, 0xc9, 0x00, 0xb9, 0x82, 0x84, 0x20, 0xfa, 0x3c, 0xa8, 0x57, 0xa8,
+       0xfb, 0xbd, 0x4f, 0x39, 0x4f, 0x31, 0xaf, 0xb3, 0x1f, 0xe5, 0xdf, 0xaa,
+       0x54, 0xb3, 0x8c, 0xfa, 0x92, 0x68, 0xde, 0xec, 0xfb, 0x00, 0xe0, 0xf5,
+       0x8c, 0xa1, 0xff, 0xb9, 0x76, 0xa8, 0x77, 0x08, 0xd2, 0xca, 0x2e, 0xe4,
+       0x8b, 0x0f, 0xda, 0x3c, 0x3b, 0x19, 0xea, 0x8f, 0x1c, 0x6e, 0x72, 0xb2,
+       0xae, 0x62, 0x2d, 0x8c, 0xdb, 0xb5, 0xc6, 0x2b, 0xa6, 0x42, 0x7b, 0xd7,
+       0x06, 0xe6, 0xe9, 0x40, 0xfa, 0xb0, 0x57, 0xae, 0x4d, 0x85, 0xe7, 0x05,
+       0x39, 0xcb, 0x75, 0x69, 0x48, 0x0f, 0xae, 0x35, 0x6b, 0xb1, 0xac, 0x73,
+       0xe6, 0x11, 0xfc, 0xc6, 0xb9, 0xb7, 0xeb, 0xd2, 0xa1, 0xbd, 0x64, 0x62,
+       0x65, 0x2d, 0x43, 0xd9, 0x2b, 0xc1, 0x7c, 0xe9, 0xc3, 0xe3, 0x93, 0x3e,
+       0x65, 0x2b, 0xc3, 0xfd, 0x30, 0x97, 0xf8, 0x21, 0xe2, 0x95, 0x4e, 0x06,
+       0x3e, 0x03, 0x4b, 0xaf, 0x4c, 0x83, 0xf3, 0x86, 0x79, 0x2d, 0x78, 0xde,
+       0x02, 0x95, 0x04, 0x07, 0xcb, 0x45, 0x5b, 0xc8, 0x82, 0x75, 0x17, 0x87,
+       0x8b, 0xc5, 0x2b, 0x84, 0x92, 0xa0, 0x6e, 0x77, 0x79, 0x05, 0xaf, 0x1b,
+       0xdf, 0xdb, 0x4a, 0xe7, 0x6b, 0x09, 0x6b, 0xf5, 0xd8, 0x2a, 0x97, 0xff,
+       0x3e, 0xa4, 0x7f, 0xfb, 0x5c, 0xed, 0xb9, 0x8a, 0xe6, 0x27, 0x68, 0x7d,
+       0x9b, 0x74, 0x9c, 0x2e, 0x3a, 0x53, 0xe5, 0x63, 0x28, 0x9f, 0x3b, 0x9d,
+       0xae, 0xb4, 0x76, 0x39, 0xba, 0x4e, 0x95, 0xaf, 0x3c, 0xa0, 0xe8, 0x6b,
+       0xea, 0x73, 0x95, 0xaf, 0xfc, 0x0e, 0xcf, 0x20, 0x23, 0xaa, 0xdf, 0x00,
+       0x9e, 0x6f, 0xd5, 0xe5, 0xa3, 0x7e, 0xb6, 0x99, 0x21, 0x7f, 0xb2, 0x3c,
+       0xbc, 0x99, 0x21, 0x5e, 0x5b, 0xa4, 0xa0, 0xcc, 0x50, 0x0f, 0xff, 0xa7,
+       0x20, 0xe1, 0xb9, 0xaa, 0xdf, 0xae, 0x56, 0x68, 0xa6, 0x3a, 0xaf, 0xd6,
+       0x8c, 0xf2, 0xfa, 0x82, 0xbd, 0x9c, 0xf4, 0x59, 0x4b, 0xeb, 0x2e, 0x3a,
+       0xaf, 0x78, 0xb8, 0x59, 0xfa, 0x75, 0xcc, 0x7b, 0x05, 0xb8, 0xa6, 0x14,
+       0x3e, 0x4d, 0xf2, 0x1d, 0x18, 0xb0, 0x5c, 0x00, 0xf0, 0xe9, 0xcb, 0xb4,
+       0x35, 0x6c, 0x4f, 0xa0, 0xf7, 0x8f, 0x50, 0xf4, 0x85, 0x0d, 0x40, 0xc6,
+       0x11, 0x92, 0x57, 0x3e, 0x33, 0xf2, 0x6b, 0x83, 0x1e, 0xf4, 0x55, 0x92,
+       0x6f, 0xb0, 0x61, 0x90, 0x07, 0x17, 0x24, 0x46, 0xf2, 0x8b, 0x75, 0x39,
+       0xa9, 0xbe, 0x3a, 0x95, 0xd7, 0xd5, 0x71, 0x56, 0x67, 0x94, 0x8f, 0xbc,
+       0x92, 0xfe, 0x6d, 0xd9, 0x6a, 0x66, 0xfe, 0x98, 0x7d, 0x6c, 0x80, 0x79,
+       0x10, 0x2e, 0xeb, 0x2e, 0xcd, 0xaf, 0x41, 0xb8, 0x32, 0x91, 0x88, 0x83,
+       0x6d, 0xfa, 0x8b, 0x7b, 0xfb, 0x46, 0xa0, 0x2f, 0xd5, 0xae, 0x19, 0xa1,
+       0xe8, 0x2b, 0x39, 0x38, 0x37, 0x94, 0xa3, 0x8d, 0x8c, 0xec, 0x02, 0x8f,
+       0x7d, 0x6e, 0x0d, 0xd2, 0x9d, 0xef, 0x62, 0x1e, 0x09, 0xdf, 0x83, 0xce,
+       0x34, 0x6a, 0xf7, 0x04, 0x99, 0xbe, 0x99, 0xd6, 0x6d, 0x50, 0xe5, 0x92,
+       0xee, 0xf2, 0x04, 0x5a, 0xab, 0x6c, 0x54, 0xe5, 0x30, 0xa9, 0xb6, 0x5c,
+       0x6e, 0xc1, 0xff, 0xf7, 0x5e, 0x16, 0x90, 0xef, 0xc7, 0xc8, 0x31, 0x5e,
+       0x90, 0x5c, 0x57, 0xe5, 0x76, 0xc1, 0x66, 0x6d, 0xfb, 0xd8, 0xad, 0xda,
+       0xfa, 0xb8, 0xd0, 0x90, 0xf7, 0xdf, 0x42, 0xb9, 0xbf, 0x98, 0xff, 0x0d,
+       0x72, 0x41, 0xdb, 0xfe, 0xb4, 0x22, 0xbf, 0x17, 0xa3, 0xfc, 0x86, 0x92,
+       0x2d, 0x32, 0x90, 0xdc, 0x33, 0xc3, 0x8a, 0x2e, 0x73, 0xb9, 0x1b, 0x95,
+       0x83, 0xc0, 0x17, 0x72, 0xbb, 0xc2, 0x95, 0xc8, 0x46, 0x73, 0x5a, 0x62,
+       0xe4, 0x21, 0xa3, 0x7d, 0x68, 0xe4, 0x63, 0x95, 0x4b, 0x26, 0xfc, 0xf3,
+       0x1d, 0x15, 0x0d, 0x78, 0x8e, 0xbe, 0x8b, 0x60, 0x7c, 0x54, 0x0c, 0xe5,
+       0xcb, 0xa3, 0x4d, 0x1c, 0xde, 0x7d, 0xc6, 0xe4, 0xd0, 0x5a, 0x78, 0xef,
+       0x51, 0xb0, 0x8b, 0xfc, 0xd0, 0x75, 0x3d, 0xd8, 0x43, 0x7e, 0x20, 0xb5,
+       0xaf, 0x8b, 0x9e, 0x5f, 0xd6, 0xa1, 0x9d, 0x75, 0x54, 0xef, 0x01, 0x8c,
+       0x1d, 0x3c, 0xa7, 0xf8, 0x73, 0xf5, 0xe4, 0xa9, 0x7a, 0xaf, 0xef, 0x2d,
+       0xa4, 0x03, 0xc6, 0xfa, 0x2b, 0x7c, 0xc9, 0x7c, 0x3e, 0x7f, 0xcc, 0x7c,
+       0x7d, 0xd6, 0x94, 0xf1, 0x0c, 0xec, 0x96, 0x5d, 0x85, 0xfe, 0x5f, 0x61,
+       0xbf, 0x4f, 0x6a, 0xec, 0x13, 0x91, 0x3f, 0x98, 0x72, 0x98, 0x01, 0xe9,
+       0x13, 0xe7, 0x67, 0xca, 0xfc, 0xcc, 0x88, 0xfa, 0x33, 0x3f, 0xef, 0x4d,
+       0x9e, 0x37, 0x9b, 0x0f, 0xc2, 0x3a, 0x1e, 0x39, 0x69, 0x42, 0x75, 0x9c,
+       0xcd, 0xd4, 0x1f, 0x3b, 0xda, 0x06, 0xf5, 0x55, 0xb9, 0x22, 0xf1, 0x33,
+       0xe9, 0xba, 0x95, 0xcf, 0x5a, 0x81, 0x0f, 0x54, 0xfd, 0x1a, 0xda, 0xe1,
+       0x9d, 0x47, 0x64, 0x79, 0x24, 0xe9, 0xe9, 0x47, 0x0d, 0x0c, 0xf5, 0xf4,
+       0x2a, 0x05, 0x8f, 0xab, 0x14, 0xfb, 0xeb, 0x99, 0x02, 0x03, 0x8d, 0xfb,
+       0x89, 0x22, 0x5f, 0xce, 0x3a, 0x55, 0xbd, 0x27, 0x68, 0x45, 0xfd, 0x17,
+       0x2c, 0x02, 0x2b, 0xea, 0xb3, 0x25, 0xbb, 0x81, 0x17, 0x6b, 0xcf, 0x33,
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+       0xe3, 0x62, 0x05, 0x5f, 0xa0, 0x6e, 0xab, 0x84, 0x7a, 0x99, 0x52, 0xef,
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+       0x8b, 0x3e, 0x21, 0x5e, 0x3f, 0xa9, 0x9c, 0xdf, 0x1a, 0xe7, 0x7a, 0x07,
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+       0xd6, 0x7a, 0x9b, 0xbd, 0x9c, 0xfc, 0xe6, 0x36, 0xe0, 0x17, 0x31, 0x7e,
+       0x24, 0x9b, 0xed, 0x08, 0xe1, 0xa1, 0xcd, 0xc3, 0xfd, 0x6b, 0x36, 0xe4,
+       0xbb, 0xe8, 0x47, 0x52, 0xf6, 0xdf, 0xeb, 0x3c, 0x42, 0xfb, 0x57, 0xfb,
+       0xad, 0x52, 0xf8, 0x8f, 0xcd, 0x13, 0xe6, 0x71, 0x47, 0xb0, 0x62, 0xb0,
+       0x9f, 0x45, 0xf4, 0x05, 0xd1, 0xbe, 0xb0, 0xd8, 0x19, 0xd9, 0x93, 0x16,
+       0x33, 0xa7, 0xa7, 0x24, 0x38, 0x0e, 0x73, 0x0c, 0x1f, 0x51, 0xe7, 0xbd,
+       0x3f, 0x9f, 0xdb, 0x69, 0xeb, 0x73, 0xca, 0x23, 0x95, 0xb4, 0x3e, 0x11,
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+       0x69, 0xef, 0xe5, 0xfb, 0xf4, 0xb5, 0x3a, 0xbc, 0xd5, 0xe9, 0x68, 0x7f,
+       0xfa, 0x9e, 0x45, 0xbe, 0xb0, 0xde, 0x76, 0xa7, 0x39, 0x88, 0xf2, 0x20,
+       0x79, 0xe2, 0x15, 0xc7, 0x7b, 0x25, 0x5f, 0xd0, 0xf8, 0x7b, 0xa2, 0xe3,
+       0xb5, 0xce, 0x50, 0xc6, 0x7b, 0x0e, 0xc7, 0xd3, 0x27, 0x97, 0x4b, 0x38,
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+       0x91, 0xfe, 0xa0, 0x96, 0x66, 0xc5, 0xaf, 0x35, 0xf4, 0x3d, 0xce, 0x27,
+       0x9d, 0x8a, 0xdd, 0x02, 0x7c, 0xf2, 0x18, 0xae, 0xbf, 0x31, 0xe7, 0xf4,
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+       0x3b, 0xd0, 0x96, 0xde, 0x6c, 0x20, 0xff, 0xa8, 0x19, 0x26, 0x47, 0x78,
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+       0x7c, 0x12, 0xe6, 0x95, 0x64, 0x32, 0x6d, 0x1e, 0xc1, 0xe0, 0x7c, 0x12,
+       0xcc, 0x57, 0xfa, 0x77, 0xd8, 0x4f, 0xed, 0xd0, 0xf3, 0x30, 0x5c, 0xe9,
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+       0xc3, 0x17, 0x56, 0x15, 0xbc, 0x16, 0xf8, 0xf6, 0xc1, 0xb8, 0xba, 0x18,
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+       0x3a, 0x6a, 0x87, 0xfe, 0x94, 0xf7, 0xe4, 0x0e, 0x5b, 0xd1, 0x6d, 0xc1,
+       0x4a, 0x59, 0x84, 0xfc, 0x02, 0x1b, 0x6e, 0xa8, 0x76, 0x2c, 0x47, 0xfc,
+       0x69, 0xe6, 0x79, 0x54, 0x6a, 0x5e, 0x91, 0x2a, 0x0f, 0x99, 0x12, 0xaf,
+       0xa4, 0x7d, 0xc1, 0x8b, 0x23, 0x6e, 0xdc, 0x3b, 0xd0, 0x07, 0xfd, 0x37,
+       0x34, 0x4f, 0xa4, 0xbc, 0xb1, 0x11, 0xa9, 0xff, 0x4e, 0xf9, 0x52, 0x9b,
+       0x1a, 0x3c, 0x1e, 0x6c, 0xff, 0xb6, 0x85, 0xc7, 0x1d, 0x9f, 0x54, 0xe2,
+       0x4e, 0x88, 0xa8, 0xe4, 0x57, 0x1b, 0x7f, 0xfd, 0x77, 0x30, 0xfe, 0x5a,
+       0x5e, 0xb0, 0x4a, 0xa0, 0x78, 0xe3, 0xca, 0x2b, 0xc7, 0x1b, 0xcb, 0xcf,
+       0x47, 0xaa, 0x30, 0xef, 0x8a, 0x2d, 0xe7, 0x79, 0x55, 0x8e, 0x3a, 0x31,
+       0x4e, 0x1e, 0x6a, 0xe9, 0x76, 0x13, 0xc2, 0x95, 0xe7, 0x3f, 0x85, 0x04,
+       0x0e, 0x5f, 0xcd, 0x78, 0x2d, 0x05, 0x19, 0x3c, 0x1e, 0xed, 0xda, 0xc1,
+       0xd0, 0xee, 0x7b, 0x05, 0xc6, 0xd2, 0x6b, 0xe9, 0x4b, 0x87, 0x79, 0x48,
+       0xf1, 0xf4, 0x28, 0x1a, 0xbd, 0x52, 0x25, 0xea, 0xeb, 0xab, 0x74, 0xb4,
+       0x8e, 0x6c, 0x0c, 0xed, 0x83, 0x88, 0x2b, 0x2f, 0x9d, 0xeb, 0x58, 0x0e,
+       0xcf, 0x73, 0xee, 0x16, 0x3d, 0x02, 0x3c, 0x1f, 0xe9, 0x7e, 0x98, 0xf2,
+       0x91, 0x40, 0xdb, 0x27, 0x7d, 0xc3, 0xed, 0x3e, 0x56, 0x85, 0xf5, 0x21,
+       0xfb, 0x5c, 0xa1, 0xdd, 0x47, 0xfc, 0xbe, 0xe2, 0xd7, 0x0d, 0x82, 0x8b,
+       0xd6, 0xad, 0x9e, 0x57, 0xf9, 0x79, 0x4f, 0x12, 0xda, 0x57, 0xe5, 0x05,
+       0x0b, 0x28, 0x5f, 0x8c, 0x7e, 0x2a, 0xbd, 0xeb, 0xe3, 0xf6, 0x93, 0x8e,
+       0x76, 0xb1, 0xce, 0x6b, 0x19, 0x8f, 0x76, 0x41, 0xcc, 0xbe, 0x98, 0xa6,
+       0x9f, 0x62, 0xbf, 0xfd, 0xd7, 0xd6, 0xef, 0x44, 0x64, 0x42, 0xbd, 0x30,
+       0x3e, 0x1e, 0xf6, 0x4f, 0x3e, 0x5a, 0xa7, 0x89, 0x79, 0xcc, 0x46, 0x7a,
+       0xaf, 0x8e, 0xec, 0x48, 0x35, 0xce, 0x96, 0x85, 0xb4, 0x83, 0xe7, 0x3e,
+       0x9a, 0xf1, 0x38, 0x45, 0xfc, 0xfb, 0x93, 0xf9, 0xfb, 0xcc, 0xc1, 0xe3,
+       0x6e, 0x26, 0x2b, 0x98, 0xa4, 0x40, 0x7f, 0xc2, 0x7d, 0x56, 0xf2, 0x67,
+       0x9a, 0x4c, 0x50, 0x87, 0xf3, 0x11, 0x8c, 0xcc, 0x3c, 0x0a, 0x9e, 0x3f,
+       0xad, 0xf8, 0x03, 0xd7, 0x08, 0x4c, 0xc4, 0x7a, 0x74, 0xbe, 0x30, 0xc3,
+       0xf9, 0xda, 0x05, 0xdf, 0x66, 0x8f, 0x13, 0x4b, 0x6e, 0x47, 0x19, 0x52,
+       0x7d, 0x94, 0x6f, 0x88, 0x61, 0xdb, 0x58, 0x7b, 0xb4, 0x0f, 0xf3, 0x38,
+       0xa0, 0x7d, 0xd5, 0xbd, 0xce, 0x91, 0xe8, 0xcf, 0x1b, 0x01, 0x04, 0x11,
+       0x41, 0x7b, 0x5a, 0x89, 0x53, 0xa9, 0xfe, 0x93, 0x94, 0xfc, 0xfe, 0xa5,
+       0x28, 0xbf, 0x5f, 0x2c, 0xf8, 0x68, 0x81, 0x19, 0xe5, 0x33, 0x3a, 0x9c,
+       0xae, 0x67, 0x6c, 0xff, 0xce, 0xd3, 0x5b, 0x82, 0x39, 0x51, 0xba, 0x34,
+       0x5d, 0xcc, 0x62, 0x72, 0x8c, 0x5d, 0x63, 0x12, 0x9b, 0x29, 0x9f, 0xc3,
+       0x74, 0x71, 0xb4, 0xc6, 0xcf, 0x12, 0x56, 0xec, 0x31, 0xb5, 0xee, 0xb5,
+       0x8b, 0xd5, 0x38, 0x5f, 0x04, 0xed, 0x05, 0xcc, 0x5f, 0x62, 0x52, 0x07,
+       0xbe, 0x57, 0x09, 0x40, 0x91, 0x63, 0xfd, 0xa6, 0x17, 0x1d, 0x9a, 0x71,
+       0xa2, 0xe3, 0xe7, 0x68, 0xe6, 0x0d, 0x83, 0x5d, 0x1d, 0x1b, 0x17, 0x18,
+       0x7e, 0xfc, 0x24, 0x26, 0x17, 0xc5, 0x8e, 0x9f, 0x37, 0xcc, 0xf8, 0x85,
+       0x71, 0xe3, 0x4b, 0x09, 0xc7, 0x8f, 0x8e, 0x9b, 0xae, 0x19, 0x77, 0x9d,
+       0xc8, 0xf9, 0x45, 0xd0, 0x6e, 0x0d, 0x25, 0xf2, 0xf3, 0x9d, 0x2d, 0xa8,
+       0x7a, 0x1b, 0x49, 0x79, 0xb8, 0x7c, 0xb3, 0x33, 0x05, 0xdc, 0x0f, 0x08,
+       0xfc, 0x58, 0xa4, 0x38, 0x94, 0x82, 0x37, 0x8f, 0x38, 0x9a, 0x29, 0xff,
+       0x4c, 0x6f, 0xe5, 0xf1, 0x52, 0x83, 0x12, 0x3f, 0x39, 0x98, 0xdc, 0xc0,
+       0xf3, 0x24, 0x72, 0xb4, 0xf9, 0x67, 0x55, 0x4c, 0x12, 0xb1, 0x7d, 0x5d,
+       0xca, 0xac, 0xa3, 0x02, 0xb4, 0x57, 0xd9, 0xb4, 0x7a, 0xfa, 0xf4, 0x4b,
+       0xa7, 0xf5, 0xc8, 0x77, 0xa6, 0x8b, 0x5a, 0x3d, 0xdd, 0xcb, 0x9a, 0x09,
+       0x3f, 0x6f, 0x62, 0xda, 0xe7, 0x86, 0x1c, 0x2d, 0x1f, 0xd8, 0xa8, 0xd0,
+       0x87, 0x2e, 0x79, 0x62, 0x84, 0xf2, 0xd4, 0x32, 0x6c, 0x94, 0x77, 0x30,
+       0x9c, 0x5f, 0xe1, 0xdd, 0x36, 0x46, 0xf9, 0x53, 0x86, 0x24, 0x5f, 0x33,
+       0xca, 0x38, 0x63, 0xe1, 0xa5, 0xb4, 0x75, 0x0e, 0xa8, 0x8f, 0xe0, 0xf8,
+       0x65, 0x2f, 0x4c, 0x5d, 0x88, 0x7e, 0xa2, 0x77, 0x15, 0x3c, 0x5e, 0x07,
+       0x74, 0x8f, 0x70, 0xac, 0x5b, 0x35, 0x72, 0xbb, 0x3e, 0x66, 0xdc, 0x3a,
+       0x63, 0xb8, 0x00, 0xe5, 0x48, 0x9d, 0x8e, 0xe7, 0xeb, 0xd3, 0x0f, 0xe6,
+       0x7f, 0x37, 0x23, 0x8b, 0xfc, 0xac, 0xf1, 0xf3, 0x52, 0xc6, 0x6f, 0x8c,
+       0xdf, 0xab, 0xbe, 0x59, 0xf0, 0xb9, 0x62, 0xf6, 0xf1, 0xae, 0x42, 0x17,
+       0x83, 0xf3, 0xad, 0xce, 0xde, 0x8e, 0x7a, 0xec, 0xe0, 0x7c, 0xa6, 0xf0,
+       0x24, 0x9a, 0x6f, 0x30, 0xef, 0x47, 0x99, 0x2f, 0xf3, 0x8b, 0xcd, 0xf7,
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+       0x49, 0xc7, 0xcc, 0x5a, 0x61, 0xb1, 0x61, 0xd9, 0x59, 0x66, 0x0a, 0xe3,
+       0xb9, 0x75, 0x66, 0xf1, 0x38, 0xab, 0xe9, 0xb5, 0x07, 0x1c, 0x61, 0x84,
+       0xfa, 0x88, 0x17, 0xcd, 0x95, 0x50, 0xbe, 0x20, 0x84, 0xaa, 0x30, 0x5e,
+       0x64, 0x56, 0xec, 0xbc, 0xe2, 0x87, 0x99, 0x86, 0x9f, 0x8f, 0x2d, 0xe1,
+       0x78, 0xae, 0x96, 0xef, 0x8f, 0xf5, 0x7f, 0x5c, 0x04, 0xa5, 0x7b, 0xb7,
+       0x9c, 0xcd, 0xf3, 0xa7, 0x23, 0xc5, 0x78, 0x3e, 0x66, 0x74, 0x20, 0x22,
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+       0xe5, 0x6f, 0x51, 0xae, 0xb8, 0x1f, 0xf6, 0xce, 0x26, 0xbf, 0x54, 0x37,
+       0x93, 0xf0, 0xfe, 0xec, 0x0e, 0x23, 0xcf, 0x73, 0x0a, 0xee, 0xe3, 0xf9,
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+       0xac, 0x18, 0xbf, 0xfc, 0x97, 0xae, 0xc4, 0xf9, 0x69, 0x63, 0x8a, 0x8c,
+       0x34, 0xfe, 0x11, 0x85, 0xdf, 0xd6, 0x3f, 0xc0, 0xf9, 0x2d, 0x20, 0xdc,
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+       0x18, 0x46, 0xce, 0x1d, 0x51, 0xf8, 0xd6, 0xdf, 0x4b, 0xde, 0xf5, 0x8d,
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+       0x7c, 0x02, 0xe9, 0xd9, 0x81, 0x3a, 0x43, 0x08, 0xdb, 0xd5, 0xf5, 0x44,
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+       0x05, 0x3e, 0x70, 0x18, 0xfd, 0x9f, 0xb7, 0x7d, 0x59, 0xa0, 0xef, 0x76,
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+       0x33, 0x63, 0xbf, 0x6d, 0x78, 0xbd, 0x1b, 0xe4, 0xb4, 0x58, 0x4c, 0xef,
+       0x31, 0xc2, 0xdb, 0x89, 0x6f, 0x8b, 0xbe, 0x44, 0x76, 0xf7, 0xb7, 0xc6,
+       0x71, 0x7e, 0x6c, 0x2f, 0x56, 0xce, 0x2d, 0x72, 0xa8, 0x12, 0xd7, 0x9b,
+       0xcb, 0x22, 0x94, 0x17, 0x35, 0x9c, 0xfc, 0xfc, 0xb4, 0x98, 0xd3, 0xc3,
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+       0x7b, 0xf8, 0xf7, 0x2b, 0xf9, 0x4a, 0xf7, 0x5d, 0x94, 0xa8, 0xec, 0xc4,
+       0x0f, 0x85, 0x61, 0xfb, 0x03, 0x4e, 0xf2, 0xdb, 0xdc, 0xb7, 0xfb, 0x84,
+       0xc1, 0x0b, 0xef, 0x2f, 0x6d, 0x11, 0xca, 0xd0, 0x1f, 0xb4, 0xb4, 0x41,
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+       0x8a, 0x2b, 0x04, 0x77, 0xe6, 0xcb, 0x38, 0x7e, 0x3d, 0x6e, 0x16, 0xfd,
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+       0xfc, 0xee, 0xdb, 0xc4, 0x17, 0xe3, 0xf5, 0x88, 0xb4, 0xbd, 0x7c, 0x1c,
+       0x8c, 0xb7, 0xa0, 0x5f, 0xe6, 0x70, 0xee, 0x64, 0x01, 0xeb, 0x8d, 0x60,
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+       0xe2, 0x2f, 0x5e, 0x8d, 0x1f, 0xe5, 0x93, 0xa3, 0xbf, 0x25, 0x3b, 0x72,
+       0xe9, 0x7e, 0x81, 0xa5, 0x93, 0xde, 0x11, 0x17, 0x7f, 0xe9, 0x9c, 0x13,
+       0x17, 0x7f, 0x39, 0x72, 0x38, 0x1b, 0xc7, 0x51, 0xf4, 0x0c, 0x09, 0xfe,
+       0x0f, 0xfd, 0x87, 0xf1, 0x7a, 0x46, 0x53, 0xf7, 0x09, 0x03, 0xda, 0x05,
+       0x57, 0x8b, 0xb3, 0x6c, 0x2e, 0xd6, 0xfa, 0x05, 0xc7, 0x88, 0xdc, 0xcf,
+       0x3a, 0xa6, 0x47, 0x90, 0xd0, 0x9f, 0x34, 0x46, 0x81, 0xd3, 0x75, 0x1b,
+       0xac, 0x04, 0xa7, 0x59, 0xef, 0xad, 0x48, 0x47, 0x3a, 0x57, 0xcf, 0xe7,
+       0xec, 0x7c, 0x7e, 0x5e, 0x67, 0xdf, 0xf9, 0xb4, 0x12, 0xdf, 0x9b, 0xfc,
+       0x9e, 0x28, 0x21, 0xbf, 0xfd, 0xf1, 0x3b, 0x2d, 0x3f, 0xcf, 0xe6, 0x75,
+       0xd9, 0x2c, 0xe3, 0x7b, 0x2d, 0x49, 0x68, 0x87, 0x9c, 0x7d, 0x6f, 0x55,
+       0x12, 0xc2, 0xf1, 0xc7, 0x50, 0xe2, 0xf7, 0x92, 0x7e, 0x78, 0x52, 0x4c,
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+       0x87, 0x15, 0xbf, 0xb1, 0x08, 0xf2, 0x2d, 0x39, 0xea, 0x7f, 0x89, 0x7f,
+       0x2f, 0xa7, 0x84, 0xf3, 0xa9, 0x4e, 0xfc, 0x8e, 0x11, 0xe2, 0xdf, 0x7e,
+       0x1e, 0xdf, 0xee, 0x1c, 0xe5, 0x9f, 0x43, 0xf5, 0xa7, 0xf2, 0x78, 0x1e,
+       0xb1, 0xc8, 0xf1, 0xf5, 0x95, 0x9e, 0x54, 0x09, 0xf5, 0xbd, 0x12, 0xd8,
+       0x2c, 0xc6, 0x61, 0xbf, 0x6f, 0x65, 0x1d, 0x18, 0x5f, 0xe9, 0xcc, 0xf0,
+       0xbf, 0x4e, 0xf4, 0xf1, 0x94, 0x8e, 0xf0, 0x17, 0xde, 0xe7, 0xdf, 0xa1,
+       0xd8, 0x23, 0x93, 0xbc, 0xc3, 0xd0, 0x14, 0xc6, 0x3f, 0xc6, 0x83, 0xac,
+       0x31, 0x53, 0x5e, 0xa3, 0x9d, 0xe2, 0x20, 0xea, 0x77, 0x62, 0x46, 0x81,
+       0x1d, 0xaa, 0x7c, 0x57, 0x61, 0x11, 0xc6, 0x5d, 0x4b, 0x94, 0x38, 0xc8,
+       0x78, 0x2b, 0x13, 0x71, 0xfc, 0x4d, 0x06, 0xff, 0xc6, 0x71, 0x18, 0x77,
+       0xe9, 0x15, 0x3d, 0x6b, 0xf0, 0x1d, 0xd1, 0x93, 0x8e, 0xdf, 0x45, 0x8a,
+       0x8f, 0xc7, 0xa8, 0xf1, 0x61, 0x35, 0x2e, 0xa3, 0xc6, 0x89, 0x87, 0x8b,
+       0xcb, 0x08, 0x38, 0xcf, 0x78, 0x8e, 0x67, 0xb1, 0xdf, 0x3d, 0x51, 0xe3,
+       0x2f, 0xec, 0xcb, 0x3c, 0x7f, 0xb3, 0x7d, 0x4a, 0x33, 0xdd, 0x8b, 0xdd,
+       0x8e, 0x31, 0x12, 0xe2, 0x9f, 0x43, 0xe2, 0x29, 0x7f, 0x46, 0x3b, 0x35,
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+       0xe8, 0x65, 0xc2, 0xb7, 0xcf, 0x1b, 0x47, 0x9b, 0x5e, 0x3c, 0xdc, 0xfc,
+       0x32, 0xb7, 0xe7, 0xe2, 0xe6, 0x9f, 0x98, 0xfa, 0x49, 0x26, 0xd9, 0x2f,
+       0x7f, 0xf9, 0x73, 0x0a, 0xc9, 0xb3, 0x9e, 0x0b, 0x24, 0x77, 0xce, 0x0d,
+       0x98, 0x94, 0xfb, 0x9d, 0xfd, 0xdc, 0x4f, 0xdd, 0x63, 0x20, 0x7b, 0xfd,
+       0x1c, 0xd8, 0x41, 0x19, 0x31, 0xf2, 0x6c, 0xf9, 0x38, 0x0e, 0x87, 0xbe,
+       0x9e, 0x19, 0x84, 0x8f, 0x7b, 0x23, 0xd5, 0x49, 0xd8, 0xbf, 0x53, 0xd1,
+       0x73, 0x36, 0xbc, 0xb5, 0x68, 0x21, 0xea, 0xd3, 0xc1, 0x88, 0xc8, 0xf3,
+       0xb1, 0x19, 0xb7, 0x6b, 0xf6, 0x46, 0xc4, 0x49, 0x5c, 0x3f, 0x18, 0x02,
+       0x27, 0xa9, 0x38, 0x41, 0xdc, 0xc9, 0x6c, 0x4d, 0x9c, 0x07, 0x14, 0x56,
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+       0x33, 0x05, 0xd5, 0x8f, 0x3c, 0x32, 0x51, 0x7c, 0x61, 0xff, 0x00, 0xf1,
+       0xd9, 0xfa, 0x7b, 0x79, 0x7c, 0xf7, 0x9a, 0xe3, 0x0b, 0xdd, 0xbd, 0x06,
+       0x96, 0x97, 0xc0, 0x6f, 0x5b, 0x33, 0x8b, 0xf8, 0xcd, 0xb5, 0xfa, 0x6b,
+       0x19, 0x5a, 0xc1, 0x93, 0xa3, 0xfc, 0x39, 0xab, 0x44, 0xe1, 0x27, 0xa5,
+       0x8a, 0xff, 0xb6, 0x98, 0xe7, 0xf3, 0xa7, 0x35, 0x97, 0x55, 0xe2, 0xf7,
+       0xef, 0xc2, 0xc3, 0x9e, 0xb7, 0x7f, 0x63, 0x49, 0x82, 0xf3, 0x4e, 0xd0,
+       0x6f, 0xab, 0xfb, 0xda, 0xe2, 0x81, 0xbf, 0xbe, 0xc6, 0xb8, 0x61, 0x6a,
+       0xd1, 0xb5, 0xf5, 0x1b, 0x93, 0x88, 0x1e, 0x12, 0xf4, 0x9b, 0x7e, 0x8d,
+       0xe3, 0x7d, 0xf3, 0x1a, 0xfb, 0xb5, 0x5d, 0xe3, 0xbc, 0x0b, 0xc7, 0x25,
+       0xea, 0xf7, 0xff, 0x68, 0xfc, 0x33, 0x3e, 0xbe, 0x19, 0x1f, 0x0f, 0x8d,
+       0x8f, 0x73, 0x9a, 0x5e, 0xbb, 0x3b, 0x88, 0x6d, 0x8f, 0x08, 0x8f, 0x0e,
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+       0x66, 0xe4, 0x6b, 0x73, 0xa7, 0xf2, 0x78, 0xc0, 0x86, 0x6a, 0x73, 0x68,
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+       0x9f, 0x0f, 0xe2, 0x77, 0x12, 0x47, 0x7b, 0x23, 0xd5, 0xe9, 0x40, 0xc7,
+       0xe7, 0xa6, 0x32, 0xb2, 0x1b, 0xce, 0x59, 0x94, 0xef, 0x23, 0x89, 0xd2,
+       0xa8, 0xf9, 0x74, 0x7e, 0x12, 0x7d, 0x1f, 0xa7, 0xd3, 0x92, 0x38, 0xbe,
+       0x34, 0x51, 0x19, 0x6f, 0x38, 0x3e, 0xf2, 0xbd, 0xd2, 0xca, 0xf5, 0x48,
+       0x2f, 0xd2, 0x30, 0xdf, 0xaf, 0xc8, 0x2d, 0xe1, 0x76, 0x80, 0xd4, 0xcd,
+       0xc8, 0x5f, 0xc3, 0x44, 0x79, 0xd4, 0x02, 0x9a, 0x57, 0x1e, 0x45, 0xdf,
+       0xdf, 0x3b, 0xc4, 0x9f, 0xa7, 0x84, 0x19, 0xe5, 0xf7, 0x41, 0xbb, 0x73,
+       0x01, 0xe9, 0xcf, 0xb2, 0x13, 0xd7, 0xb7, 0x45, 0x89, 0x7b, 0xa5, 0xcd,
+       0x29, 0x74, 0xa2, 0x9f, 0x2e, 0x0d, 0xe4, 0x2d, 0xc6, 0x45, 0x1e, 0xc3,
+       0xf8, 0x08, 0xf9, 0xf5, 0x25, 0xea, 0xa7, 0xce, 0x97, 0xec, 0xe6, 0xf3,
+       0x6d, 0x31, 0x30, 0x01, 0xe3, 0x58, 0xc1, 0x71, 0x3c, 0xaf, 0x82, 0x75,
+       0x7c, 0x5f, 0x13, 0xd7, 0x38, 0x66, 0x08, 0x7f, 0xb0, 0x5c, 0xa0, 0xb8,
+       0xc6, 0x76, 0x5c, 0xff, 0xcf, 0x74, 0x61, 0xf7, 0x0e, 0x27, 0x3f, 0x17,
+       0x84, 0xaf, 0x7b, 0xaf, 0x44, 0xf1, 0x96, 0x37, 0xa6, 0x7e, 0xaf, 0x88,
+       0xee, 0xcb, 0x2b, 0x71, 0x8e, 0xd5, 0x12, 0xef, 0x72, 0x10, 0xed, 0x0c,
+       0x58, 0xc7, 0xea, 0x57, 0x2b, 0x08, 0x7f, 0x97, 0xf6, 0x4d, 0xfd, 0x65,
+       0x1d, 0xea, 0x83, 0x2e, 0x91, 0xe0, 0x3c, 0x44, 0x0f, 0x57, 0xec, 0xab,
+       0x93, 0x8a, 0x7d, 0xa8, 0xda, 0x57, 0xfd, 0x68, 0x27, 0xc6, 0xd8, 0x1b,
+       0x3f, 0x50, 0xf4, 0x86, 0x04, 0x74, 0xf5, 0x83, 0x44, 0x7c, 0x69, 0x8b,
+       0xc0, 0xed, 0xdf, 0xe0, 0xcf, 0xb8, 0xfd, 0x5b, 0x61, 0xf4, 0xe4, 0xc7,
+       0xe6, 0x53, 0xf5, 0x2a, 0x71, 0x92, 0xe5, 0x61, 0xee, 0x87, 0x55, 0xed,
+       0xda, 0xf1, 0xde, 0x90, 0x2e, 0x13, 0xe0, 0x50, 0xf1, 0xa0, 0x3e, 0x6c,
+       0x02, 0x39, 0x5d, 0xb1, 0xbe, 0xd4, 0x88, 0xfc, 0xba, 0x62, 0x7d, 0xae,
+       0x95, 0xfc, 0x4a, 0x2b, 0xf6, 0xe8, 0x54, 0x78, 0x27, 0x3a, 0xf7, 0x9f,
+       0x2a, 0xeb, 0xdc, 0x70, 0x74, 0x80, 0xe2, 0x12, 0xaf, 0xc4, 0xc5, 0x27,
+       0x93, 0xdd, 0x46, 0x6a, 0x7f, 0x48, 0xc1, 0x9f, 0x64, 0x3c, 0x5b, 0x28,
+       0x57, 0x17, 0x88, 0xed, 0x28, 0x7e, 0x47, 0xdc, 0x20, 0xe9, 0x13, 0xf9,
+       0xc5, 0xeb, 0x41, 0xef, 0xc7, 0xf5, 0x2d, 0xef, 0xe4, 0xeb, 0x55, 0xe3,
+       0x20, 0xf5, 0x61, 0x79, 0x06, 0xce, 0x73, 0xea, 0xf0, 0xc0, 0x7a, 0x2c,
+       0xcb, 0x1b, 0x9c, 0x33, 0xc8, 0x6f, 0xb8, 0xf2, 0xfc, 0x7a, 0x94, 0x9b,
+       0x81, 0x4b, 0x17, 0x8e, 0x4c, 0x27, 0x3f, 0x80, 0x51, 0x4e, 0x74, 0x5f,
+       0x60, 0x4b, 0x29, 0xf7, 0x1f, 0xbe, 0x82, 0x8a, 0x08, 0xc2, 0x6b, 0xb6,
+       0x48, 0x79, 0xbb, 0x15, 0xb3, 0x45, 0x3a, 0xef, 0xb4, 0x7a, 0x0b, 0xd9,
+       0xe1, 0x69, 0x06, 0xa6, 0xc7, 0xef, 0xb0, 0xa6, 0xcd, 0xe7, 0x72, 0xac,
+       0xbc, 0xc6, 0x3e, 0x03, 0xeb, 0x6c, 0x51, 0x2a, 0xc9, 0xe1, 0xf2, 0xa3,
+       0x72, 0xea, 0xdd, 0xee, 0xa8, 0x9d, 0x9f, 0x36, 0xbb, 0x25, 0x03, 0xe1,
+       0x74, 0xb5, 0xf8, 0x90, 0xea, 0x2f, 0xb8, 0xcd, 0xe8, 0xfd, 0x63, 0x49,
+       0xc6, 0xe7, 0x8f, 0x0f, 0x35, 0x1e, 0x7b, 0x8b, 0xf2, 0xcc, 0xee, 0xe8,
+       0xd7, 0xc6, 0x87, 0xd4, 0x78, 0xcf, 0x70, 0xf1, 0x21, 0x35, 0x3e, 0x1b,
+       0xa8, 0xf9, 0x54, 0x13, 0x4f, 0x0e, 0x88, 0x03, 0xb3, 0xd0, 0xaf, 0x52,
+       0xf1, 0xea, 0x29, 0x8a, 0x0f, 0x07, 0xba, 0x05, 0xc9, 0xe1, 0x8c, 0xc6,
+       0x8d, 0x02, 0x7b, 0xcf, 0x1b, 0x09, 0xbe, 0x4a, 0xbc, 0x08, 0xfa, 0x1b,
+       0xf1, 0xbd, 0x0a, 0x38, 0xf6, 0x51, 0x69, 0xf8, 0x1d, 0x02, 0x1e, 0x3f,
+       0xda, 0x87, 0xf9, 0xb8, 0x46, 0xfc, 0xbe, 0x9e, 0x44, 0x79, 0xb7, 0x3f,
+       0xc2, 0x7c, 0xdc, 0x42, 0xfc, 0xbe, 0x1e, 0xcf, 0xc7, 0x3d, 0x80, 0xf9,
+       0xb8, 0x46, 0xbc, 0xff, 0xc1, 0xf3, 0x71, 0xfb, 0x94, 0xfc, 0xde, 0x40,
+       0xcf, 0x79, 0x8a, 0x37, 0xa5, 0xb9, 0x87, 0xe4, 0x53, 0x51, 0x3c, 0xe2,
+       0x21, 0xc1, 0x97, 0xe1, 0x9e, 0xa4, 0x89, 0x57, 0x50, 0x3d, 0x3e, 0x5e,
+       0xa1, 0xb7, 0x72, 0x3b, 0x34, 0x70, 0xd4, 0x40, 0xdf, 0x3f, 0x0f, 0x1c,
+       0x33, 0x13, 0x9f, 0xad, 0xec, 0x59, 0x3e, 0x06, 0xf5, 0x31, 0xf5, 0xbb,
+       0xe4, 0x4d, 0x18, 0x2f, 0x88, 0xf1, 0x2f, 0x9d, 0xf5, 0x7a, 0x2c, 0x78,
+       0xbf, 0xe7, 0xac, 0xcf, 0x63, 0xc1, 0x38, 0x41, 0x45, 0xef, 0xc7, 0x46,
+       0x99, 0xf8, 0x4e, 0x38, 0x1b, 0x53, 0x98, 0x9a, 0xc4, 0x88, 0x11, 0xed,
+       0x7d, 0x84, 0x03, 0xe5, 0xf9, 0xf5, 0x54, 0x5a, 0x10, 0xae, 0x57, 0xf5,
+       0xeb, 0x77, 0xff, 0x7f, 0xbf, 0xfe, 0xe7, 0xf1, 0xeb, 0x7f, 0x2b, 0x4a,
+       0x97, 0xc4, 0x3f, 0xca, 0x7d, 0x3a, 0xba, 0x57, 0x5e, 0x7e, 0xd4, 0x6b,
+       0xb9, 0x3b, 0x86, 0x3f, 0x6c, 0xf0, 0x71, 0xff, 0xf0, 0x06, 0x57, 0x1e,
+       0xd1, 0xdf, 0x13, 0xbe, 0xbc, 0xd4, 0x15, 0xb1, 0x7e, 0xfc, 0x1a, 0x6e,
+       0xbf, 0xa5, 0xcd, 0x76, 0x59, 0x62, 0x9f, 0xbf, 0x5b, 0xca, 0xfd, 0xf8,
+       0x69, 0x42, 0xe2, 0xfb, 0x05, 0x77, 0xb9, 0x87, 0xe5, 0xb7, 0x77, 0xb9,
+       0x13, 0xea, 0x3b, 0x89, 0xe3, 0x01, 0x1b, 0x6a, 0x38, 0x1f, 0x51, 0xfd,
+       0xfd, 0x43, 0xe3, 0x03, 0x9e, 0xd7, 0x5c, 0x31, 0x7e, 0xfe, 0xb3, 0x3f,
+       0x33, 0xd3, 0xbf, 0xaf, 0xd0, 0xbb, 0xdf, 0x44, 0xf2, 0xfc, 0x4f, 0xaf,
+       0x9a, 0x76, 0xa0, 0xde, 0x5d, 0x5e, 0xb3, 0x62, 0x4c, 0x32, 0xd4, 0xcb,
+       0x4f, 0x9a, 0x98, 0x93, 0xcb, 0x23, 0x4d, 0x5c, 0x61, 0x69, 0x8d, 0xce,
+       0x6b, 0x49, 0x49, 0x14, 0x47, 0xf0, 0x66, 0xd3, 0xf7, 0x43, 0xe3, 0xe3,
+       0x05, 0x35, 0x3a, 0xe2, 0xef, 0x83, 0xf1, 0x82, 0x1a, 0xf1, 0x14, 0xd5,
+       0x15, 0xfd, 0xfc, 0x8e, 0xf3, 0xbf, 0x4b, 0xc6, 0x4f, 0x94, 0xbe, 0x22,
+       0x84, 0x3a, 0xd1, 0xbe, 0x78, 0xa5, 0x51, 0xf0, 0xf4, 0xb2, 0xa1, 0xf1,
+       0x03, 0x18, 0x38, 0x9b, 0x4d, 0x81, 0x5d, 0xd4, 0x70, 0x3b, 0xc1, 0x53,
+       0x6b, 0x26, 0xbb, 0xe0, 0x6a, 0x71, 0x85, 0xba, 0xbd, 0x27, 0xd6, 0xa1,
+       0x9f, 0xa0, 0x8c, 0x6d, 0xee, 0xc4, 0xef, 0x51, 0x96, 0xb9, 0x74, 0x12,
+       0x88, 0xa2, 0x04, 0x71, 0x05, 0x9e, 0xdf, 0x59, 0xae, 0xe8, 0x11, 0xf1,
+       0xfe, 0x01, 0xc4, 0x0f, 0x94, 0xfb, 0xf1, 0x7e, 0xc1, 0xad, 0x6e, 0x6e,
+       0x9f, 0x6f, 0x55, 0xe4, 0x7e, 0x5e, 0x09, 0x97, 0x33, 0xea, 0x38, 0xea,
+       0x7b, 0xf1, 0xe7, 0x7e, 0xc6, 0xad, 0x8d, 0x3f, 0xc4, 0xb7, 0xbf, 0xa7,
+       0xb4, 0x77, 0xd4, 0x94, 0x6f, 0xc0, 0x73, 0x0b, 0xce, 0xd5, 0x31, 0xe4,
+       0xff, 0x1d, 0x35, 0x55, 0x66, 0x57, 0xcc, 0x78, 0x2f, 0xb8, 0x79, 0xde,
+       0xcc, 0x16, 0x8c, 0x53, 0xd8, 0x63, 0xe3, 0x14, 0x3c, 0x1e, 0x11, 0x1f,
+       0x9f, 0x50, 0xf9, 0x53, 0x45, 0xef, 0x67, 0xb3, 0xf0, 0xdc, 0x9f, 0xe8,
+       0xe1, 0xfe, 0xa3, 0x80, 0x83, 0xfb, 0x33, 0x2b, 0x0e, 0x54, 0xd2, 0x3d,
+       0x93, 0xe8, 0x3a, 0x39, 0x7e, 0x3e, 0xe1, 0x18, 0xbc, 0x67, 0x98, 0xca,
+       0xf8, 0xbe, 0x98, 0x99, 0xfb, 0xb9, 0xc8, 0xaf, 0x50, 0x3e, 0xf7, 0xd3,
+       0x3e, 0xfc, 0xf7, 0x07, 0x98, 0x2f, 0x95, 0xfe, 0x3d, 0x83, 0xc0, 0x31,
+       0x57, 0xbb, 0x0d, 0xf9, 0xc8, 0x5c, 0x71, 0x92, 0x20, 0x93, 0x7f, 0x7b,
+       0xd0, 0xdf, 0x8d, 0xfe, 0xa8, 0x85, 0xc7, 0x1b, 0xe6, 0x60, 0x3e, 0x70,
+       0xc5, 0xe2, 0xb2, 0x13, 0x78, 0x2e, 0x8b, 0xeb, 0x0c, 0x94, 0x77, 0xb4,
+       0xf0, 0x78, 0x2d, 0x7d, 0x67, 0x5c, 0x95, 0x57, 0x15, 0x8b, 0xb7, 0xaf,
+       0xb5, 0x62, 0x7b, 0x91, 0xe0, 0xb1, 0xc8, 0xd8, 0x5e, 0x53, 0x85, 0xed,
+       0x37, 0xbf, 0x18, 0x46, 0xcf, 0x1e, 0x9b, 0x87, 0xbb, 0x07, 0x7a, 0x89,
+       0x1c, 0x83, 0xde, 0x79, 0xe4, 0xdf, 0xfe, 0x29, 0xda, 0x45, 0x15, 0xf3,
+       0x15, 0xbf, 0x77, 0x1d, 0x97, 0xab, 0x8b, 0x7b, 0xe6, 0x1b, 0xf8, 0x47,
+       0xaf, 0xb4, 0x72, 0xee, 0x60, 0xee, 0x9f, 0xc8, 0x6e, 0xbe, 0xd0, 0x53,
+       0x41, 0xfe, 0xec, 0x74, 0x8c, 0xb7, 0xba, 0xa3, 0x72, 0xa6, 0xe2, 0x55,
+       0x90, 0x3f, 0xc9, 0x51, 0xf9, 0xf3, 0xb7, 0xca, 0x9d, 0x33, 0x6e, 0x9e,
+       0xe7, 0x3f, 0x01, 0xe4, 0x0f, 0xae, 0x27, 0x6d, 0x3e, 0x8f, 0x0b, 0xc6,
+       0x9f, 0xff, 0x0b, 0x0a, 0x3e, 0x0d, 0x27, 0x4f, 0x86, 0xe3, 0x9f, 0x28,
+       0x3f, 0x74, 0x53, 0x38, 0xbd, 0x08, 0x8e, 0xa8, 0xdc, 0x95, 0xd1, 0x9e,
+       0xbe, 0x2e, 0x2a, 0x7f, 0xa5, 0x6e, 0xa8, 0x8f, 0x1c, 0x1e, 0xff, 0xf2,
+       0x15, 0xbc, 0x4e, 0x1d, 0x46, 0xff, 0x1a, 0x5d, 0x2a, 0x28, 0xdf, 0x1b,
+       0x1b, 0x26, 0x5f, 0xa3, 0xfb, 0xef, 0xe3, 0xf7, 0xce, 0x2a, 0x55, 0xf9,
+       0xe7, 0xff, 0xe5, 0x7e, 0x6f, 0xc5, 0xbe, 0x51, 0xfd, 0xdf, 0xaa, 0x3d,
+       0xd4, 0xa2, 0xc0, 0x59, 0x2d, 0x1f, 0x50, 0xf4, 0xd9, 0xbf, 0x39, 0x5f,
+       0x19, 0x85, 0x62, 0xc2, 0x7c, 0xe5, 0xb4, 0xc4, 0xf9, 0xca, 0x77, 0x74,
+       0x09, 0xf4, 0x1d, 0x16, 0x25, 0x5f, 0xf9, 0xb0, 0x91, 0x55, 0xee, 0xb1,
+       0x63, 0x9e, 0x9e, 0x72, 0x2f, 0x21, 0xe4, 0x23, 0xfd, 0xe6, 0xf0, 0xd3,
+       0xbf, 0x5a, 0xff, 0x9c, 0x1d, 0xef, 0x25, 0x08, 0x12, 0x8a, 0x9d, 0xc6,
+       0xae, 0x13, 0x24, 0x9f, 0x1b, 0x41, 0x9f, 0x21, 0x3d, 0xa8, 0xe7, 0x0f,
+       0xdc, 0x2f, 0xd5, 0xc5, 0xf3, 0x4b, 0x1b, 0xbb, 0xb5, 0xf7, 0x1f, 0xd4,
+       0x72, 0x5b, 0x29, 0xbf, 0xaf, 0x50, 0x0d, 0xfb, 0x21, 0x3f, 0xb2, 0x92,
+       0xc7, 0x37, 0x6b, 0x2f, 0xa7, 0xeb, 0x80, 0xd7, 0x18, 0x92, 0x9d, 0xe8,
+       0x17, 0xfa, 0xaa, 0x18, 0xeb, 0x17, 0x0a, 0xc8, 0x91, 0x0c, 0x35, 0x3f,
+       0x30, 0xc4, 0xe5, 0x52, 0xc2, 0x3c, 0xbe, 0x26, 0x36, 0x40, 0xf9, 0x7e,
+       0x4d, 0x0d, 0x82, 0x07, 0xe5, 0xc1, 0x17, 0xf6, 0x13, 0x79, 0x79, 0x7e,
+       0xdf, 0xb5, 0xfa, 0x89, 0xea, 0x4b, 0xb5, 0x7e, 0xe6, 0xb5, 0x25, 0xdc,
+       0x2f, 0x54, 0xeb, 0x17, 0x04, 0xd4, 0x47, 0xcd, 0x3a, 0xdf, 0x4a, 0xca,
+       0xef, 0x3d, 0x20, 0x48, 0x89, 0xf2, 0x44, 0x57, 0x2b, 0xf8, 0x7e, 0xb3,
+       0xe2, 0xa7, 0xdd, 0x65, 0xe4, 0x78, 0xb0, 0xeb, 0x7a, 0x81, 0xf2, 0x6a,
+       0xf1, 0x5e, 0x0c, 0x9e, 0xef, 0xae, 0x03, 0x3c, 0x7f, 0x7e, 0x57, 0x39,
+       0xcf, 0x9f, 0x57, 0xfd, 0xb2, 0x6a, 0x5e, 0xfc, 0xb8, 0xa8, 0x5f, 0x96,
+       0xee, 0xc3, 0xa8, 0xf9, 0xf4, 0x6a, 0x7e, 0xbc, 0x7a, 0x3f, 0x74, 0xfe,
+       0x56, 0x6b, 0x18, 0xf5, 0x8b, 0x4d, 0x86, 0x2e, 0x07, 0xd2, 0xa1, 0x9a,
+       0x57, 0xe4, 0x2a, 0xe5, 0x72, 0xce, 0xaa, 0x7c, 0x77, 0x3c, 0x7e, 0x9d,
+       0xcb, 0x4a, 0x2b, 0x5d, 0xa5, 0x18, 0xa7, 0x2b, 0xd5, 0x0d, 0xe7, 0xe7,
+       0x6a, 0x2b, 0x4d, 0xa0, 0xdf, 0xbc, 0xae, 0xc8, 0xcf, 0x75, 0xa5, 0xc3,
+       0xea, 0xe5, 0x9d, 0xa5, 0x5a, 0xbd, 0x9c, 0xea, 0xf1, 0x7a, 0xf9, 0x7f,
+       0x95, 0x5f, 0x76, 0xcc, 0xf0, 0x7e, 0xe1, 0x5f, 0x97, 0x5c, 0x9b, 0xdf,
+       0xea, 0x96, 0xc4, 0x7a, 0xdc, 0x90, 0x7e, 0x95, 0xa5, 0x09, 0xc6, 0x6b,
+       0xb7, 0x24, 0xfe, 0x8e, 0xe8, 0xef, 0x54, 0xfe, 0x1b, 0xf7, 0xef, 0x8f,
+       0xb0, 0x21, 0xf7, 0x7b, 0xb8, 0x7c, 0xeb, 0x14, 0xe4, 0x5f, 0x4e, 0xa3,
+       0x38, 0x97, 0x81, 0xe2, 0x5c, 0x2a, 0x7f, 0xe9, 0x4c, 0xe6, 0xe3, 0xef,
+       0x53, 0xf8, 0x8a, 0x5a, 0x9e, 0x50, 0xc6, 0x1f, 0xee, 0x7b, 0x93, 0xef,
+       0x2a, 0xfd, 0x5a, 0x04, 0xef, 0x0f, 0x70, 0xdd, 0x25, 0xbb, 0xb5, 0x7e,
+       0xb2, 0xd2, 0x2e, 0xad, 0x9f, 0x6c, 0x42, 0x77, 0x9a, 0xa6, 0x5e, 0x16,
+       0xce, 0xd2, 0xf4, 0xaf, 0x38, 0x9a, 0xa7, 0x69, 0x9f, 0x14, 0x29, 0xd6,
+       0xb4, 0x5f, 0x77, 0xb2, 0x5c, 0x53, 0x9f, 0xda, 0x7f, 0xbd, 0xa6, 0xff,
+       0xb4, 0x8f, 0xaa, 0x34, 0xf5, 0x1b, 0x07, 0xb4, 0x7e, 0xb2, 0xe9, 0x17,
+       0x17, 0xc4, 0xdd, 0x3b, 0xe2, 0xf8, 0x5d, 0x09, 0x18, 0x11, 0xfb, 0xde,
+       0x0c, 0xf3, 0x5d, 0x9a, 0x7e, 0xd9, 0x0d, 0xda, 0x7d, 0xe5, 0x36, 0x6b,
+       0xf7, 0x35, 0xa6, 0x55, 0xbb, 0x2f, 0x75, 0x5c, 0x67, 0x50, 0xbb, 0xbf,
+       0xfc, 0x4e, 0xed, 0xfe, 0xd2, 0xd0, 0x7f, 0xef, 0xfe, 0xe2, 0xfe, 0xfb,
+       0xdb, 0xdd, 0x32, 0xcd, 0xd3, 0xd7, 0x93, 0x4f, 0xdf, 0x03, 0xdc, 0x52,
+       0xe3, 0xa2, 0xef, 0x5e, 0xab, 0xf7, 0xff, 0xfe, 0x13, 0x07, 0xaf, 0xfb,
+       0x52, 0x40, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 csem_int_table_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x53, 0xe1,
+       0x67, 0x60, 0xf8, 0x51, 0x0f, 0xc1, 0x5b, 0xf9, 0x18, 0x18, 0x2e, 0xf0,
+       0x21, 0xf8, 0xf4, 0xc0, 0x1c, 0xcc, 0x0c, 0x0c, 0x9c, 0x40, 0xac, 0xc8,
+       0xc8, 0xc0, 0x20, 0x01, 0xc4, 0xfc, 0x40, 0xcc, 0x06, 0xc4, 0x9e, 0x0c,
+       0x0c, 0x0c, 0xff, 0x81, 0xf8, 0x1b, 0x10, 0xbf, 0x05, 0xe2, 0x27, 0x40,
+       0xec, 0x0c, 0xc4, 0x07, 0x58, 0xb0, 0x9b, 0xe3, 0xc6, 0xca, 0xc0, 0xe0,
+       0x01, 0xc4, 0xdc, 0x40, 0xb3, 0x78, 0x98, 0x89, 0xb7, 0xdf, 0x89, 0x17,
+       0xc1, 0x7e, 0xcc, 0xc3, 0xc0, 0x70, 0x0e, 0x88, 0x9f, 0xf1, 0xd0, 0x37,
+       0x0c, 0x06, 0x1b, 0x5e, 0x27, 0x40, 0x3f, 0xbb, 0x7e, 0x43, 0xed, 0x3a,
+       0x29, 0x32, 0xf0, 0xfe, 0x06, 0x61, 0x21, 0x31, 0x60, 0x9a, 0x14, 0x47,
+       0xf0, 0xa7, 0x8a, 0xa3, 0xca, 0x0b, 0x8b, 0x21, 0xd8, 0xc9, 0xd2, 0x94,
+       0xd9, 0x95, 0x0f, 0xd4, 0x0f, 0x00, 0xf1, 0x93, 0x21, 0xf0, 0x80, 0x03,
+       0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 csem_pram_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
+       0x0b, 0x7c, 0x94, 0xc5, 0xb5, 0xf8, 0x7c, 0xbb, 0xdf, 0xbe, 0x92, 0xdd,
+       0xcd, 0x26, 0xe4, 0x49, 0x00, 0x37, 0x09, 0x60, 0x50, 0x1e, 0x4b, 0x80,
+       0xc8, 0x4b, 0xdd, 0xf0, 0x32, 0x52, 0xc4, 0x04, 0x11, 0x82, 0x8a, 0x2c,
+       0xaf, 0x10, 0x02, 0x79, 0x14, 0xa9, 0xa5, 0xff, 0xda, 0xbb, 0x0b, 0x28,
+       0x04, 0xaa, 0xde, 0x58, 0x51, 0xa3, 0x7f, 0x6a, 0x17, 0x04, 0x1b, 0x2d,
+       0xda, 0x80, 0xd1, 0x1b, 0x6d, 0xe0, 0x2e, 0xa2, 0x08, 0xd5, 0x6a, 0x68,
+       0x45, 0x51, 0xab, 0x0d, 0x88, 0x88, 0x08, 0x49, 0x8c, 0x8f, 0x6a, 0xb5,
+       0x7a, 0xcf, 0x39, 0x33, 0xdf, 0x66, 0xe7, 0xcb, 0x2e, 0x89, 0xb6, 0xfe,
+       0x6f, 0xff, 0xbf, 0x7b, 0xc3, 0xaf, 0x1d, 0xe7, 0x9b, 0x99, 0x33, 0x67,
+       0xce, 0x39, 0x73, 0xe6, 0xcc, 0x99, 0x99, 0xb3, 0x26, 0x96, 0xc2, 0x0c,
+       0x97, 0x33, 0xf6, 0x0d, 0xfe, 0x41, 0x6a, 0x33, 0x31, 0xc6, 0xc6, 0x74,
+       0xa5, 0xed, 0x4a, 0xc7, 0x70, 0x35, 0xa7, 0xab, 0xfc, 0x36, 0xbf, 0x97,
+       0x79, 0xcd, 0x8c, 0xd5, 0xf9, 0xad, 0x94, 0x6e, 0xf1, 0xa7, 0x33, 0xef,
+       0x60, 0xf8, 0xee, 0x33, 0x14, 0x06, 0xed, 0x8c, 0xdd, 0xeb, 0x77, 0x51,
+       0xfe, 0x17, 0xfe, 0x42, 0x4a, 0x6b, 0xfd, 0x45, 0x54, 0xef, 0x4e, 0x7f,
+       0x09, 0xe5, 0x6f, 0xf7, 0xfb, 0x28, 0xdd, 0xec, 0x2f, 0xa3, 0xef, 0x35,
+       0xfe, 0x6a, 0xca, 0x6f, 0xf0, 0xaf, 0xa1, 0x74, 0x93, 0xba, 0x28, 0x0d,
+       0x50, 0x82, 0xbf, 0xa2, 0xc2, 0xac, 0x64, 0xc6, 0xaa, 0x9e, 0xc9, 0xc9,
+       0xdb, 0x0c, 0xb9, 0x2d, 0xb3, 0xc6, 0x27, 0xa8, 0xa3, 0x21, 0xff, 0x8a,
+       0x91, 0x19, 0xb3, 0x00, 0xbe, 0x4f, 0xa5, 0xfe, 0x98, 0xea, 0xde, 0x34,
+       0x70, 0x74, 0x57, 0x3d, 0x0d, 0xcf, 0x4d, 0xea, 0xa4, 0x7e, 0x08, 0xa7,
+       0x76, 0x09, 0xc7, 0x8b, 0x59, 0x99, 0x2d, 0x46, 0xbd, 0x2c, 0x1c, 0xe7,
+       0x9d, 0x4b, 0x04, 0x3c, 0x7b, 0x6b, 0x4d, 0x4e, 0x72, 0xd4, 0x7a, 0x83,
+       0x11, 0xde, 0xed, 0x25, 0x00, 0x6f, 0x28, 0x14, 0xb8, 0x42, 0xd6, 0x9c,
+       0xe8, 0xf0, 0x2e, 0x46, 0x78, 0x9b, 0x4b, 0x54, 0x5e, 0x2f, 0x39, 0x58,
+       0x93, 0x1d, 0x1d, 0x9e, 0x07, 0xeb, 0xd5, 0xdc, 0x20, 0xe0, 0xa5, 0x07,
+       0xac, 0x31, 0xea, 0x8d, 0xc1, 0x7a, 0x1b, 0x6e, 0x10, 0xf8, 0xf5, 0xf3,
+       0xd5, 0x64, 0x45, 0xef, 0x77, 0x3c, 0xd6, 0x63, 0x2e, 0xf5, 0x6f, 0xad,
+       0x56, 0x46, 0x7f, 0xdf, 0x64, 0xe3, 0xff, 0xdb, 0x5d, 0xa7, 0x2e, 0x16,
+       0x79, 0x23, 0x66, 0x93, 0x18, 0x1b, 0xd7, 0xd5, 0x4e, 0x9f, 0x32, 0x16,
+       0x60, 0x38, 0x4e, 0x95, 0xf9, 0x0a, 0x89, 0x0f, 0xee, 0xcc, 0xaf, 0xbf,
+       0xc9, 0x67, 0xec, 0x26, 0x84, 0x09, 0xed, 0x03, 0x93, 0x58, 0xc8, 0x08,
+       0xfd, 0x07, 0x92, 0x58, 0x70, 0x7d, 0x96, 0x54, 0x7f, 0x26, 0xd5, 0x6f,
+       0xed, 0xfb, 0xf5, 0x37, 0xa9, 0x52, 0xfd, 0x80, 0x21, 0x4a, 0x7d, 0x13,
+       0x6b, 0x50, 0xb0, 0xfc, 0xe7, 0x28, 0x47, 0xc0, 0xf7, 0xfb, 0xfc, 0xb9,
+       0x94, 0x6e, 0x14, 0xf2, 0x73, 0xdf, 0x50, 0x03, 0x63, 0xd8, 0x2e, 0xdd,
+       0x1c, 0x1c, 0x04, 0xed, 0xee, 0xf1, 0x7b, 0x48, 0x5e, 0xee, 0xf6, 0x8f,
+       0xa5, 0xf2, 0xbb, 0x84, 0x1c, 0xfe, 0xbb, 0x90, 0xb3, 0xa0, 0x90, 0xb3,
+       0x07, 0x51, 0xce, 0x20, 0xdd, 0x8a, 0x72, 0x66, 0xc6, 0xfe, 0x7c, 0xad,
+       0xa5, 0x00, 0xa7, 0x7d, 0x6f, 0x3c, 0xdb, 0xec, 0x26, 0xf9, 0x5a, 0x4c,
+       0x78, 0xaa, 0x8c, 0xe0, 0x6f, 0xd8, 0x3b, 0x64, 0xfb, 0x66, 0x80, 0x7f,
+       0xdf, 0x0d, 0xab, 0x4e, 0x6f, 0x03, 0xfa, 0xb7, 0x35, 0x0f, 0xf3, 0x18,
+       0xa1, 0xde, 0x3d, 0x43, 0x35, 0xf9, 0x62, 0x5e, 0x96, 0xdc, 0x55, 0xef,
+       0x9e, 0xd9, 0x27, 0x9c, 0x8b, 0x86, 0x12, 0xbd, 0xcb, 0x10, 0xce, 0xdd,
+       0x1e, 0xc1, 0x3f, 0x15, 0x06, 0x16, 0x51, 0xef, 0xee, 0x19, 0xe1, 0x7a,
+       0x15, 0x58, 0xef, 0x2e, 0x4f, 0x18, 0x5e, 0x28, 0xb2, 0xdf, 0xbb, 0xa6,
+       0x84, 0xeb, 0xad, 0x22, 0x3e, 0x2b, 0xac, 0xa4, 0xc1, 0xde, 0x9d, 0x2f,
+       0x3b, 0x98, 0x42, 0xf3, 0x11, 0x04, 0x85, 0xe8, 0x6b, 0x42, 0xfa, 0xc2,
+       0xbc, 0x7c, 0x76, 0xc0, 0x75, 0x4a, 0x2b, 0xb4, 0x4f, 0x49, 0xce, 0x4b,
+       0x63, 0xd0, 0xee, 0x7e, 0x9c, 0x8f, 0x66, 0x9c, 0x77, 0x6e, 0xa2, 0x8b,
+       0xd6, 0x1e, 0xe9, 0xec, 0x83, 0xef, 0x19, 0x16, 0x56, 0x8d, 0xf0, 0x81,
+       0xb2, 0xfb, 0x8d, 0x80, 0xaf, 0x69, 0xb6, 0x3b, 0x11, 0xe9, 0x72, 0xfb,
+       0xb5, 0x45, 0x4c, 0x19, 0xc6, 0x58, 0x5f, 0x51, 0x9e, 0x1a, 0x28, 0x52,
+       0xb2, 0x00, 0xae, 0x7d, 0x4e, 0x91, 0x82, 0xdf, 0x4d, 0xb3, 0xa1, 0x1c,
+       0xbe, 0xbb, 0x44, 0x79, 0xf2, 0x1a, 0x5e, 0x7e, 0x3b, 0x96, 0x3b, 0xba,
+       0xca, 0x13, 0xb1, 0x1c, 0xbe, 0x27, 0x55, 0x43, 0x39, 0xe4, 0xed, 0x73,
+       0x79, 0xf9, 0x1d, 0x7e, 0xe0, 0xc4, 0xe0, 0xae, 0x7a, 0x9b, 0x80, 0xcf,
+       0x3e, 0xe2, 0x77, 0x3a, 0xff, 0x0e, 0x6c, 0x45, 0xfa, 0x98, 0x46, 0xf3,
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+       0x7a, 0x07, 0xa7, 0xf1, 0x35, 0x99, 0x3e, 0x8d, 0xaf, 0x85, 0xe9, 0xf3,
+       0x15, 0xc1, 0xe9, 0xdf, 0xbb, 0x71, 0x8d, 0x7e, 0x5d, 0xa6, 0xcf, 0xe8,
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+       0xbd, 0x13, 0xa6, 0x8f, 0x9b, 0xf0, 0x19, 0xd6, 0xbb, 0x71, 0xe5, 0xff,
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+       0x0e, 0x9f, 0xa6, 0xf7, 0x64, 0xfa, 0x34, 0xbd, 0x17, 0xa6, 0x4f, 0x1e,
+       0xc1, 0x19, 0xd3, 0x3b, 0x7c, 0xc6, 0x9e, 0x92, 0xe9, 0x33, 0xf6, 0x54,
+       0x98, 0x3e, 0x13, 0x08, 0xce, 0xb8, 0xde, 0xc1, 0x69, 0x3a, 0x25, 0xd3,
+       0xa7, 0xe9, 0x54, 0x98, 0x3e, 0x53, 0x88, 0xce, 0x97, 0xf6, 0x6e, 0x5c,
+       0x63, 0xdf, 0x97, 0xe9, 0x33, 0xf6, 0xfd, 0x30, 0x7d, 0xae, 0x22, 0x38,
+       0x05, 0xbe, 0x7a, 0xc2, 0x87, 0x01, 0x1c, 0x47, 0x6c, 0x38, 0xcf, 0x9c,
+       0x93, 0xe9, 0xf3, 0xcc, 0xb9, 0x30, 0x7d, 0xe6, 0x10, 0x9c, 0xa9, 0x00,
+       0x27, 0xa7, 0x67, 0x38, 0xe3, 0xdb, 0x64, 0xfa, 0x8c, 0x6f, 0x0b, 0xd3,
+       0x67, 0x01, 0xc1, 0xb9, 0xb2, 0x77, 0x70, 0x9e, 0x69, 0x93, 0xe9, 0xf3,
+       0x4c, 0x5b, 0x98, 0x3e, 0x65, 0x44, 0xe7, 0xab, 0x7a, 0x37, 0xae, 0xf1,
+       0xed, 0x32, 0x7d, 0xc6, 0xb7, 0x73, 0xfa, 0x54, 0x59, 0x3c, 0x93, 0x1d,
+       0x68, 0xdf, 0x25, 0x32, 0xcf, 0x76, 0x68, 0x72, 0xc9, 0xc9, 0x86, 0x03,
+       0x4e, 0xc8, 0x9b, 0xec, 0xcc, 0x83, 0x60, 0x5f, 0x52, 0x42, 0x3b, 0x10,
+       0x3e, 0xac, 0x95, 0x64, 0x17, 0xaa, 0x1e, 0xcd, 0x4e, 0xf1, 0x30, 0xb4,
+       0x43, 0x67, 0x38, 0xdd, 0x1e, 0xf4, 0xfb, 0x18, 0x35, 0x7b, 0x84, 0xb5,
+       0xd0, 0x7e, 0xc1, 0xbe, 0x2b, 0x51, 0xf2, 0x07, 0x7d, 0x69, 0x98, 0x74,
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+       0xd9, 0x43, 0x89, 0xde, 0x24, 0x29, 0xdf, 0xa7, 0xb0, 0xaf, 0x54, 0x3f,
+       0xa5, 0x28, 0x5b, 0x2a, 0x4f, 0x2b, 0xb9, 0x48, 0x2a, 0xcf, 0xf0, 0xe5,
+       0x49, 0xf9, 0xcc, 0xb2, 0xf1, 0x52, 0xfd, 0xfe, 0xd5, 0x93, 0xa4, 0xfc,
+       0x05, 0x6b, 0xa6, 0x4b, 0xf5, 0xb3, 0x02, 0xb3, 0xa4, 0x7c, 0x4e, 0xcd,
+       0x75, 0x52, 0xfd, 0x41, 0xb5, 0x8b, 0xa4, 0xf2, 0x0b, 0xeb, 0xca, 0xa5,
+       0xf2, 0x21, 0xc1, 0x55, 0x52, 0xfe, 0xe2, 0xfa, 0xff, 0x23, 0xd5, 0x1f,
+       0xd6, 0xb0, 0x4e, 0x2a, 0x1f, 0xd1, 0xb4, 0x59, 0x2a, 0x1f, 0x19, 0xfa,
+       0x85, 0x94, 0x1f, 0x75, 0xe8, 0x01, 0xa9, 0xfe, 0x98, 0x96, 0xed, 0x52,
+       0xf9, 0x25, 0xc7, 0x1e, 0x95, 0xca, 0xc7, 0xb5, 0xee, 0x91, 0xf2, 0x13,
+       0x4e, 0x3f, 0xa3, 0xb3, 0x03, 0xe5, 0xfd, 0xff, 0xfa, 0x02, 0xc6, 0xed,
+       0xc1, 0x0c, 0x33, 0xd9, 0x83, 0x21, 0x87, 0x99, 0xf2, 0xe6, 0x7d, 0x36,
+       0xb2, 0xff, 0xf7, 0x63, 0x1e, 0xf8, 0x69, 0xee, 0x3b, 0x83, 0xf2, 0xe6,
+       0x67, 0x17, 0xbb, 0x93, 0x71, 0x3f, 0x8d, 0x00, 0x60, 0xbd, 0x2f, 0xe8,
+       0x5b, 0x76, 0x21, 0xfa, 0x7b, 0x6e, 0x1e, 0xef, 0xbb, 0xd0, 0x05, 0xdf,
+       0x6f, 0x36, 0xfb, 0x46, 0xb8, 0xa2, 0xf8, 0x23, 0x3c, 0xaa, 0x6f, 0x9f,
+       0x81, 0xfc, 0x45, 0x2d, 0x0a, 0x4b, 0xc7, 0xd4, 0x6d, 0xc0, 0x34, 0xce,
+       0x28, 0xf6, 0xeb, 0x16, 0x2e, 0x5f, 0x1b, 0xb3, 0xf2, 0x1f, 0x0a, 0x44,
+       0xc8, 0x69, 0x4d, 0x7f, 0x98, 0x7f, 0x90, 0x3f, 0x6c, 0x30, 0x93, 0xfd,
+       0xaa, 0xc9, 0xf7, 0xc6, 0xfe, 0xa5, 0xe9, 0x0b, 0x23, 0xfa, 0xd9, 0xd0,
+       0xdf, 0x5c, 0xb2, 0x7d, 0x28, 0xff, 0xbe, 0xd8, 0x8e, 0xfd, 0x15, 0xbd,
+       0x88, 0xf3, 0xac, 0xca, 0xdc, 0x31, 0x18, 0xf1, 0xd2, 0xf7, 0x63, 0xc9,
+       0x1e, 0x2b, 0xf5, 0x63, 0x1d, 0x50, 0x46, 0xfd, 0xbc, 0x86, 0xfd, 0x44,
+       0xf8, 0xbd, 0x2c, 0x03, 0xca, 0x74, 0xfd, 0x58, 0x4b, 0xb6, 0x8b, 0xef,
+       0xa2, 0x9f, 0x63, 0x38, 0xae, 0x58, 0xfd, 0x6c, 0xcc, 0x1e, 0x2f, 0x8f,
+       0x67, 0x40, 0x39, 0xf5, 0xf3, 0xae, 0xae, 0x9f, 0x8d, 0x03, 0xca, 0x75,
+       0xfd, 0xc4, 0xf1, 0xf1, 0xc0, 0x77, 0xd1, 0xcf, 0x7b, 0xe7, 0x1d, 0x4f,
+       0xce, 0x44, 0x79, 0x3c, 0x17, 0xac, 0xa4, 0x7e, 0x3a, 0x74, 0x74, 0xb3,
+       0x5c, 0xb0, 0x52, 0xd7, 0x8f, 0x9d, 0xfa, 0xc1, 0xef, 0x8b, 0xc9, 0x9f,
+       0x0b, 0xbb, 0x80, 0x34, 0xe0, 0xb3, 0xa5, 0xa3, 0x94, 0xe4, 0xe0, 0x3f,
+       0x6d, 0x2c, 0x00, 0x72, 0x61, 0xce, 0x2c, 0xff, 0x35, 0xe6, 0xd9, 0x5b,
+       0x36, 0x36, 0x08, 0xfb, 0x71, 0x43, 0xbf, 0x50, 0x8f, 0xe5, 0x72, 0xff,
+       0xd1, 0xd3, 0x86, 0x24, 0x1a, 0xcf, 0x67, 0x71, 0xc0, 0xff, 0x08, 0x3b,
+       0xb5, 0x6b, 0x3f, 0x1b, 0xa0, 0x7d, 0xf1, 0x52, 0x81, 0x22, 0x0b, 0x02,
+       0x46, 0xb0, 0xbf, 0xad, 0x14, 0xb2, 0xb9, 0x64, 0x57, 0xf1, 0x80, 0x9b,
+       0xdc, 0x90, 0x36, 0x1d, 0x18, 0x78, 0x37, 0xf6, 0xb3, 0xc5, 0xe1, 0x19,
+       0x04, 0xf9, 0xb6, 0xa6, 0xc9, 0xe6, 0xc5, 0x51, 0xe4, 0x69, 0x69, 0xad,
+       0xe9, 0x54, 0x6b, 0xa4, 0x5f, 0x44, 0xdb, 0xdf, 0x4c, 0x62, 0xb9, 0xd5,
+       0xd0, 0xff, 0x2e, 0x9b, 0x4b, 0xca, 0x6b, 0xe9, 0x4a, 0xc5, 0xc5, 0x84,
+       0x3f, 0x82, 0xf2, 0x27, 0x60, 0xdf, 0xc2, 0x60, 0x3f, 0xf0, 0x67, 0xd8,
+       0x17, 0x30, 0x20, 0xd5, 0xbb, 0x26, 0xbe, 0x4f, 0x7b, 0x07, 0xf6, 0x37,
+       0x98, 0x6f, 0x85, 0xfd, 0x0d, 0x96, 0x33, 0xb6, 0x96, 0xda, 0x9d, 0x10,
+       0x7e, 0xda, 0x13, 0xb7, 0x2b, 0x41, 0xa4, 0xf7, 0x67, 0x3f, 0xf9, 0xa1,
+       0x89, 0xf4, 0x78, 0x80, 0xbd, 0x9a, 0x9e, 0x8a, 0x7e, 0x37, 0xfe, 0xb7,
+       0x60, 0x4d, 0x3c, 0xfa, 0xf8, 0xc3, 0xf8, 0x2d, 0x0c, 0xf4, 0x91, 0xf2,
+       0xa0, 0x2e, 0x33, 0x0d, 0xe9, 0xb4, 0x2f, 0xa4, 0xfd, 0x6f, 0xc7, 0xd3,
+       0x96, 0xe0, 0x76, 0xa4, 0x6b, 0x4d, 0x26, 0xd0, 0x54, 0xd4, 0xcb, 0x66,
+       0xec, 0x75, 0xd8, 0xe4, 0x66, 0x24, 0x51, 0x36, 0xd3, 0x30, 0x96, 0xb1,
+       0xd9, 0xd5, 0xc5, 0x53, 0xd3, 0x68, 0x16, 0x29, 0xfd, 0x57, 0x01, 0x9e,
+       0xb3, 0x1a, 0x47, 0x9a, 0xa0, 0x05, 0x6b, 0x33, 0xb5, 0xde, 0xe8, 0xb1,
+       0x77, 0xc1, 0x65, 0x5e, 0xd3, 0x09, 0xa4, 0x8f, 0x15, 0xfe, 0x21, 0x9c,
+       0x6b, 0x0a, 0x21, 0x1f, 0xd1, 0xff, 0xb5, 0x45, 0x72, 0x7e, 0x2e, 0x53,
+       0xbb, 0xf2, 0xc0, 0xef, 0xc1, 0xc6, 0x6c, 0xc1, 0x37, 0xd1, 0xaf, 0xdb,
+       0x6b, 0x42, 0xbe, 0x16, 0xa5, 0x72, 0x7c, 0xe6, 0x62, 0x9a, 0x87, 0xc5,
+       0xdc, 0xdf, 0x51, 0xe2, 0xe2, 0x6d, 0x35, 0x7c, 0xaa, 0x16, 0x9b, 0x58,
+       0x88, 0xf6, 0xa7, 0x81, 0x14, 0x86, 0xfe, 0xe8, 0x40, 0x32, 0xd5, 0xbb,
+       0x4e, 0xdb, 0x67, 0xea, 0xf0, 0x2b, 0x31, 0x59, 0xbd, 0x45, 0x40, 0xd7,
+       0x92, 0x85, 0x46, 0xa2, 0xab, 0x1e, 0xdf, 0x37, 0xf7, 0xc5, 0x7b, 0x0d,
+       0xc3, 0x21, 0xad, 0xb9, 0xdb, 0x84, 0xae, 0xcd, 0x9e, 0xf0, 0x9f, 0xe7,
+       0x93, 0xcb, 0x59, 0x19, 0xef, 0x4f, 0xa3, 0xab, 0x26, 0x2f, 0xa7, 0x04,
+       0x7f, 0x4f, 0x20, 0xff, 0x21, 0x7d, 0x1f, 0xf9, 0x0f, 0x78, 0x9f, 0x14,
+       0xfc, 0xef, 0x92, 0x63, 0xce, 0xff, 0x2a, 0x8b, 0x6f, 0x26, 0xf2, 0xbf,
+       0xe3, 0x7e, 0x23, 0x23, 0x7e, 0x09, 0xbe, 0xcf, 0x11, 0x7c, 0x5f, 0x5a,
+       0x2b, 0xf3, 0x7d, 0x0e, 0xfa, 0xc9, 0xa1, 0xfe, 0x9c, 0xd5, 0x59, 0xc1,
+       0xf5, 0x58, 0xbf, 0xae, 0x8f, 0xc4, 0x5f, 0x18, 0xb8, 0x4c, 0x87, 0xda,
+       0xbb, 0xa6, 0x82, 0x5a, 0xed, 0x86, 0xff, 0xdb, 0x42, 0x0e, 0xae, 0xab,
+       0xd9, 0xfd, 0x3c, 0xb2, 0xf7, 0xfa, 0x32, 0xdd, 0xf8, 0x04, 0x1f, 0x6e,
+       0x14, 0x7c, 0x98, 0xaf, 0xa3, 0xc7, 0x1c, 0xc1, 0xb7, 0xf9, 0x82, 0x6f,
+       0xcb, 0x58, 0xe0, 0xb6, 0x0c, 0xf2, 0x1f, 0x05, 0x4d, 0xe8, 0x17, 0x9b,
+       0x57, 0xa6, 0x30, 0xd4, 0x17, 0x55, 0x3f, 0xd5, 0xf8, 0xd6, 0x2a, 0xf1,
+       0xcd, 0xa7, 0xf1, 0x4d, 0x87, 0xef, 0x8d, 0x82, 0x6f, 0x37, 0xfe, 0x84,
+       0xf3, 0x4d, 0x8f, 0x77, 0xab, 0xe0, 0x5b, 0x6b, 0xdd, 0xc7, 0x26, 0x96,
+       0xdd, 0x1d, 0x6f, 0x3d, 0x9e, 0x0b, 0xd6, 0xe8, 0xc6, 0x15, 0xd0, 0xf3,
+       0xad, 0x56, 0x9c, 0x3b, 0xb8, 0xcc, 0x68, 0xef, 0x14, 0x7b, 0x0b, 0xfa,
+       0x9c, 0x8c, 0xa8, 0x7f, 0x4d, 0xe1, 0x95, 0x7d, 0x4e, 0x46, 0xe8, 0x85,
+       0x6b, 0x8b, 0x8a, 0xa5, 0xfc, 0xdc, 0x92, 0x79, 0x52, 0xfd, 0x79, 0xbe,
+       0x85, 0x52, 0xf9, 0xf5, 0x65, 0xcb, 0xa5, 0xf2, 0xf9, 0xd5, 0x3f, 0x94,
+       0xf2, 0x0b, 0xd6, 0xfc, 0x44, 0xaa, 0xbf, 0x30, 0xb0, 0x56, 0x2a, 0x5f,
+       0x5c, 0xb3, 0x49, 0x2a, 0x5f, 0x5a, 0x7b, 0x97, 0x94, 0x5f, 0x56, 0x77,
+       0xbf, 0x54, 0x7f, 0x79, 0x70, 0x9b, 0x54, 0xbe, 0xa2, 0xfe, 0x11, 0xa9,
+       0xbc, 0xa2, 0x61, 0xb7, 0x94, 0xaf, 0x6a, 0x7a, 0x5a, 0xaa, 0x6f, 0xd8,
+       0x37, 0xe4, 0x6a, 0x94, 0xaf, 0x97, 0x8e, 0x1a, 0x19, 0xfa, 0xcb, 0x3e,
+       0xf5, 0xbc, 0x4f, 0xfe, 0xba, 0x4f, 0x3d, 0x26, 0x0f, 0xd6, 0xa9, 0x44,
+       0x99, 0x1b, 0x87, 0xf2, 0xec, 0x26, 0x79, 0x3e, 0xe5, 0xcf, 0xa5, 0xf4,
+       0xb4, 0xdf, 0x43, 0xf2, 0x7e, 0xc6, 0x3f, 0x96, 0xd2, 0xb6, 0xa6, 0x03,
+       0x76, 0xf4, 0x3f, 0x56, 0xc5, 0x81, 0xde, 0x4f, 0x04, 0x3b, 0xdc, 0xf8,
+       0xe6, 0xda, 0x9a, 0x7e, 0xb8, 0xde, 0x40, 0xfb, 0xf1, 0x8c, 0x35, 0x1b,
+       0x5b, 0xd7, 0x06, 0x20, 0x7f, 0x00, 0x0f, 0xa3, 0x60, 0xde, 0xcc, 0xa8,
+       0x33, 0xb3, 0xd0, 0x28, 0x06, 0xd2, 0xdd, 0x37, 0x2c, 0xcf, 0x1d, 0xc6,
+       0x88, 0xf2, 0xd6, 0x1e, 0xca, 0xeb, 0x54, 0x16, 0xea, 0xd3, 0xbd, 0x7c,
+       0x46, 0x6b, 0xf4, 0xef, 0xed, 0x4a, 0xc7, 0xe0, 0x0c, 0xf4, 0x13, 0xbe,
+       0x61, 0x61, 0x3b, 0x23, 0xfc, 0x75, 0xdd, 0xcf, 0x2b, 0x58, 0x26, 0xda,
+       0x15, 0xb1, 0xca, 0xcf, 0x1a, 0x58, 0x59, 0xe4, 0x79, 0xd6, 0x49, 0x23,
+       0x3f, 0x27, 0x71, 0x1a, 0x27, 0x9d, 0x34, 0x42, 0xba, 0xd2, 0xcc, 0xe7,
+       0xff, 0xca, 0x3d, 0x19, 0x93, 0x98, 0x13, 0xf3, 0xa1, 0xc1, 0xd5, 0x51,
+       0xfc, 0x2e, 0xe1, 0xfe, 0x1a, 0x00, 0x99, 0x34, 0xe4, 0x73, 0x8e, 0x34,
+       0xef, 0x97, 0xd5, 0x5d, 0xdc, 0x35, 0xcf, 0x19, 0xf6, 0x93, 0x4d, 0x72,
+       0xbb, 0x3c, 0x38, 0x4a, 0xfa, 0xbe, 0xa2, 0x7e, 0x82, 0xd4, 0x2e, 0x57,
+       0xf1, 0xbd, 0x6b, 0x84, 0x7a, 0x67, 0xf7, 0x1b, 0x69, 0xbd, 0x66, 0xa1,
+       0x03, 0x03, 0xae, 0x19, 0x86, 0xf8, 0x79, 0x4f, 0xe2, 0x77, 0xd6, 0x94,
+       0x42, 0x76, 0x57, 0x8b, 0xdf, 0xdb, 0xe7, 0xe4, 0x40, 0xc6, 0xfe, 0xe8,
+       0x2f, 0xa4, 0xf4, 0x55, 0x7f, 0x11, 0xa5, 0xaf, 0xf9, 0x4b, 0x28, 0x3d,
+       0xe6, 0xf7, 0x51, 0xfa, 0xa6, 0xbf, 0x8c, 0xd2, 0x3f, 0xfb, 0xab, 0x29,
+       0x7d, 0xc7, 0xbf, 0x86, 0xd2, 0x56, 0x7f, 0x80, 0xd2, 0x13, 0xfe, 0x1a,
+       0x4a, 0x4f, 0xfa, 0x6b, 0x29, 0x3d, 0xe5, 0xaf, 0xa3, 0xf4, 0xb4, 0x3f,
+       0x48, 0xe9, 0x19, 0x7f, 0x3d, 0xa5, 0x67, 0xfd, 0x0d, 0x94, 0xb6, 0xf9,
+       0x9b, 0x28, 0xd5, 0xf4, 0x67, 0x4f, 0xf2, 0x77, 0x5a, 0xac, 0xaf, 0x67,
+       0x50, 0xfe, 0xa2, 0xc8, 0x99, 0xf9, 0x56, 0xb6, 0xae, 0x66, 0x62, 0x97,
+       0x9c, 0xc5, 0xa9, 0x96, 0x75, 0x28, 0x67, 0x1a, 0x7d, 0x67, 0xd4, 0x59,
+       0x84, 0x3c, 0xa4, 0x4a, 0xf2, 0x90, 0x88, 0xeb, 0x30, 0xc9, 0x59, 0x0f,
+       0xe5, 0x75, 0x26, 0x21, 0x87, 0xb1, 0xda, 0x47, 0x2f, 0x47, 0x79, 0xeb,
+       0xfb, 0x3d, 0xc8, 0x1b, 0x63, 0xeb, 0x48, 0x0e, 0x66, 0x0a, 0xb9, 0xfb,
+       0xae, 0xf2, 0xc6, 0xd0, 0x1b, 0x9f, 0x82, 0xf2, 0x94, 0xa9, 0x93, 0x27,
+       0x59, 0x0e, 0x35, 0x39, 0xd2, 0xf4, 0x40, 0xae, 0x52, 0x34, 0x5c, 0x1d,
+       0xd3, 0x25, 0x57, 0x33, 0x8d, 0xdc, 0x4e, 0xd2, 0xe4, 0xea, 0xe7, 0x68,
+       0x27, 0x46, 0xb1, 0xb7, 0x6e, 0x50, 0x15, 0xb1, 0xfe, 0x71, 0xfb, 0x88,
+       0xf9, 0x32, 0x0c, 0x68, 0xbf, 0xad, 0x12, 0x7e, 0x7f, 0xe6, 0x4e, 0xa7,
+       0x7c, 0xa7, 0xe8, 0x7b, 0x3d, 0x80, 0x6b, 0xc1, 0x7a, 0x6a, 0x30, 0x17,
+       0xd7, 0x91, 0xce, 0xdc, 0xbf, 0x0d, 0x46, 0xff, 0x78, 0xe7, 0x31, 0x0b,
+       0x43, 0x3f, 0x7c, 0xac, 0xf1, 0xe9, 0xe5, 0x25, 0x36, 0xdd, 0xbd, 0xb4,
+       0x7f, 0x28, 0x0d, 0xc2, 0xa2, 0x36, 0xaa, 0x7b, 0xb9, 0x2d, 0x8e, 0xd3,
+       0xd5, 0x66, 0x60, 0x85, 0x2c, 0x0f, 0xcf, 0x67, 0xf3, 0x8f, 0xf9, 0x80,
+       0x9f, 0x71, 0xff, 0x79, 0x71, 0x1e, 0xee, 0x6b, 0xe1, 0xbb, 0xca, 0xc8,
+       0xae, 0x0a, 0x7a, 0x8a, 0xa3, 0xf8, 0xdb, 0x19, 0xca, 0x78, 0x5a, 0xcf,
+       0xf4, 0xd5, 0xea, 0x9f, 0x7a, 0xe0, 0xcb, 0x7c, 0x3c, 0x37, 0x9f, 0x29,
+       0xe6, 0x79, 0xdc, 0x01, 0x23, 0x3f, 0xd7, 0x0e, 0x3d, 0xe4, 0xb9, 0x26,
+       0xe2, 0x7c, 0x06, 0xf6, 0xdb, 0xe9, 0xe8, 0x77, 0xee, 0x18, 0x64, 0x76,
+       0x91, 0xfd, 0x10, 0xea, 0x2b, 0xd3, 0x31, 0xd8, 0x57, 0xa2, 0xe3, 0x81,
+       0x41, 0x9f, 0x0d, 0xc6, 0xf3, 0x8d, 0x4d, 0x20, 0x87, 0x38, 0xbf, 0x3a,
+       0x07, 0x0e, 0x4e, 0x60, 0xe7, 0x91, 0x8f, 0x9e, 0xf4, 0x7c, 0x4f, 0xf4,
+       0x5c, 0x14, 0xec, 0xdb, 0x4b, 0x7a, 0x9a, 0x19, 0x9e, 0x1b, 0x01, 0x3d,
+       0xb7, 0xe3, 0xfd, 0x97, 0xde, 0xd2, 0xb3, 0x27, 0x3d, 0xd9, 0x93, 0x7e,
+       0x3c, 0xb1, 0x99, 0xd3, 0xd9, 0x29, 0xec, 0xd3, 0x58, 0x74, 0x6e, 0x9f,
+       0x04, 0xf3, 0x2e, 0x8a, 0x1c, 0xdf, 0xa3, 0xaa, 0xb2, 0x1c, 0xb3, 0x81,
+       0xfc, 0xbc, 0x43, 0xa3, 0x3f, 0xee, 0x4b, 0x23, 0xe8, 0x7f, 0xa9, 0xdd,
+       0x4d, 0xf5, 0x9f, 0xdb, 0xf7, 0xd6, 0x80, 0x56, 0xe8, 0xa7, 0xb3, 0xf1,
+       0xc2, 0x04, 0xc6, 0xcf, 0x73, 0xc8, 0xae, 0xeb, 0x78, 0x52, 0xd8, 0xed,
+       0xee, 0x4c, 0x99, 0x8f, 0xad, 0x7d, 0x09, 0xae, 0x06, 0xe7, 0xb9, 0x27,
+       0x5f, 0x1f, 0x80, 0xfb, 0xe4, 0xdb, 0x30, 0x03, 0xf3, 0xec, 0xc9, 0xf8,
+       0xa2, 0x5f, 0xa9, 0x29, 0x5d, 0xf0, 0x7a, 0x7b, 0x0e, 0x1f, 0x6b, 0x5c,
+       0xbb, 0xbf, 0xe5, 0xfc, 0x6c, 0x4f, 0xd5, 0xe6, 0x67, 0xcb, 0x00, 0x94,
+       0xa7, 0xcf, 0x84, 0x1e, 0x88, 0x39, 0xbe, 0x9e, 0xe4, 0x14, 0xc7, 0x07,
+       0x70, 0xae, 0x52, 0xf8, 0xf8, 0x36, 0x18, 0x8b, 0x7e, 0x87, 0x7a, 0x26,
+       0x3c, 0xbe, 0xd1, 0x29, 0xbd, 0x1a, 0x5f, 0x55, 0x82, 0x99, 0x29, 0x23,
+       0x00, 0x3f, 0x87, 0xd9, 0xcc, 0x12, 0x18, 0xdb, 0xa1, 0xfa, 0x0e, 0xaa,
+       0xb4, 0x8f, 0xf3, 0xb4, 0x06, 0xd0, 0x4f, 0xb1, 0x2f, 0xde, 0xb3, 0x1e,
+       0x58, 0x52, 0xe5, 0x3c, 0xf3, 0x72, 0xc8, 0x8d, 0xed, 0x64, 0x7f, 0xc6,
+       0x8a, 0x7a, 0x9b, 0x4b, 0xb6, 0x9f, 0x12, 0x5d, 0xb2, 0xfd, 0x94, 0xe1,
+       0x8a, 0xb4, 0x9f, 0x3a, 0x0f, 0x3d, 0xe4, 0xf4, 0x01, 0x7e, 0xab, 0xd2,
+       0x0d, 0xae, 0x93, 0xa3, 0x70, 0x9d, 0xf3, 0x8a, 0x75, 0x8e, 0xaf, 0xab,
+       0x1a, 0x7e, 0x15, 0x0d, 0x59, 0x2e, 0xbb, 0x04, 0x47, 0xce, 0x77, 0xd6,
+       0x2a, 0x85, 0x0d, 0x24, 0x4f, 0xee, 0x84, 0xd9, 0x51, 0xce, 0xcb, 0xb4,
+       0x74, 0x55, 0xba, 0xd9, 0x75, 0x12, 0xd6, 0xab, 0x33, 0xf5, 0x39, 0x09,
+       0xd8, 0xef, 0x19, 0xbf, 0xd5, 0xc5, 0xd7, 0x57, 0x97, 0x8b, 0xf7, 0x9b,
+       0xee, 0x8a, 0x5c, 0x5f, 0x57, 0xae, 0x89, 0xa3, 0xfa, 0x1a, 0x7e, 0xb1,
+       0xe0, 0xfe, 0xb3, 0xf1, 0x63, 0xac, 0x91, 0xbd, 0x6b, 0xc5, 0x75, 0x11,
+       0xca, 0x72, 0x62, 0xd7, 0x8f, 0xc9, 0x4f, 0xf5, 0x13, 0x33, 0x9d, 0x4b,
+       0x37, 0x9b, 0x3e, 0x43, 0xfb, 0xdd, 0x96, 0xab, 0xd9, 0xef, 0x2a, 0xe5,
+       0x35, 0xb8, 0x55, 0x0d, 0xc6, 0x80, 0x65, 0x04, 0x7e, 0xdf, 0x25, 0xf5,
+       0x07, 0xed, 0xdc, 0xda, 0x19, 0x33, 0xb6, 0x8b, 0x2d, 0x37, 0x2a, 0x3b,
+       0xa5, 0xf1, 0x13, 0xf8, 0x6f, 0xc5, 0x83, 0x77, 0xda, 0xb7, 0x5a, 0x89,
+       0xcf, 0x3e, 0x80, 0x98, 0x00, 0xf0, 0xda, 0x55, 0x7b, 0x0d, 0xca, 0xd5,
+       0x09, 0x95, 0xcf, 0xe7, 0x2a, 0x21, 0xa7, 0x15, 0xd6, 0x56, 0xb3, 0xcf,
+       0x4d, 0xe4, 0x6e, 0x41, 0x79, 0x5e, 0x34, 0x96, 0x69, 0x13, 0x66, 0xee,
+       0x5b, 0xa0, 0xa7, 0x3f, 0x78, 0xd1, 0x44, 0xf7, 0xb4, 0xd8, 0x57, 0x00,
+       0x3d, 0xbf, 0xeb, 0xaa, 0xc0, 0x12, 0x56, 0xe4, 0x44, 0xa7, 0xe7, 0xa2,
+       0xc6, 0x15, 0x33, 0x70, 0xdd, 0xfe, 0xc0, 0xa0, 0xed, 0x87, 0x6b, 0xf3,
+       0x71, 0xdc, 0xe7, 0x98, 0xa1, 0x10, 0xf5, 0xd2, 0x39, 0xf6, 0x47, 0xe7,
+       0xa8, 0x88, 0xf9, 0x3a, 0xc4, 0xc4, 0xfd, 0x31, 0xac, 0x86, 0xef, 0x73,
+       0x02, 0xf0, 0x0f, 0xc7, 0xb7, 0xb4, 0x56, 0xde, 0xf7, 0x2c, 0xab, 0x93,
+       0xf3, 0xa5, 0x6c, 0x56, 0x2a, 0xea, 0xdb, 0xd2, 0x2d, 0x26, 0x16, 0x04,
+       0xdc, 0x97, 0xe3, 0xbe, 0x49, 0x1b, 0x37, 0xe8, 0xdf, 0x0c, 0x13, 0xf7,
+       0x6b, 0x2c, 0x63, 0xd5, 0x1b, 0x70, 0x9f, 0x7e, 0xaf, 0x89, 0xfb, 0x7b,
+       0x16, 0xb9, 0x98, 0x9a, 0x09, 0x78, 0x55, 0xfc, 0xc7, 0x2f, 0xf3, 0xd1,
+       0xef, 0xe3, 0x31, 0x71, 0xbb, 0x43, 0x3b, 0x4f, 0x5e, 0x9e, 0xc4, 0xf1,
+       0x2e, 0x9f, 0x1d, 0x34, 0x7b, 0xa1, 0xfe, 0xbb, 0x8d, 0xa3, 0xe6, 0x80,
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+       0x27, 0xd7, 0xab, 0xf8, 0x8f, 0xc7, 0x9e, 0x0a, 0x80, 0xbc, 0x94, 0xff,
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+       0x72, 0xbb, 0x75, 0xfd, 0x23, 0xf7, 0x0d, 0x3f, 0x0e, 0xf8, 0x9c, 0xdd,
+       0xf1, 0xa2, 0x53, 0x19, 0x1a, 0xa9, 0x1f, 0xb8, 0x9c, 0x75, 0x36, 0x2c,
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+       0xf1, 0xd8, 0xf3, 0xaf, 0x8d, 0x07, 0xba, 0xaf, 0xd8, 0x6d, 0x4a, 0x9e,
+       0xc1, 0x87, 0x63, 0x57, 0x52, 0xbb, 0xf8, 0x52, 0x05, 0xff, 0x5b, 0x93,
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+       0x5c, 0x67, 0xd7, 0x3f, 0xf2, 0x57, 0x33, 0xfa, 0x13, 0x3f, 0xd8, 0xa7,
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+       0x89, 0xf8, 0x28, 0xf8, 0x14, 0xe6, 0x5b, 0x37, 0x7e, 0x85, 0x66, 0x3e,
+       0x33, 0x9a, 0xea, 0xb9, 0x50, 0x0f, 0xc6, 0xe2, 0xd7, 0x32, 0xa1, 0x77,
+       0x41, 0x9e, 0x1f, 0x7f, 0x06, 0xef, 0xff, 0xbc, 0x69, 0xf1, 0xe0, 0xf8,
+       0xcb, 0x1e, 0xbf, 0xc9, 0x89, 0xe3, 0x78, 0x5f, 0xad, 0xe6, 0x72, 0xfd,
+       0xcb, 0xdb, 0x52, 0x71, 0x7e, 0x97, 0x99, 0x02, 0xa9, 0x2e, 0x4a, 0xf9,
+       0xf7, 0xb2, 0x07, 0x7f, 0x44, 0xf2, 0xb6, 0xec, 0xc8, 0x8f, 0x52, 0xc9,
+       0x5e, 0x60, 0xde, 0x0c, 0x03, 0xe9, 0xe2, 0x40, 0x06, 0x8e, 0x6f, 0xe9,
+       0xd6, 0x6b, 0x69, 0x7c, 0xa5, 0xcc, 0x47, 0x72, 0x57, 0xf6, 0x4b, 0x63,
+       0x11, 0xde, 0x47, 0xfc, 0x54, 0x65, 0x85, 0xbb, 0xa3, 0xcc, 0x8b, 0x38,
+       0xb3, 0x42, 0xf8, 0xbc, 0xbf, 0x1d, 0x0c, 0x19, 0x18, 0xdf, 0xfb, 0xb8,
+       0xbf, 0x44, 0x7d, 0xf6, 0x47, 0x23, 0xdd, 0x8b, 0x62, 0xec, 0x87, 0x74,
+       0x6f, 0xec, 0x47, 0x62, 0xac, 0xb0, 0xf2, 0x51, 0xfe, 0x53, 0x2b, 0xe7,
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+       0xf2, 0xe7, 0x4c, 0x7f, 0x6f, 0x1a, 0x9e, 0x73, 0x00, 0x1d, 0x02, 0x82,
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+       0x0c, 0x8b, 0x36, 0x4f, 0x3f, 0xb4, 0xc3, 0xfe, 0x2a, 0xda, 0x3c, 0x85,
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+       0xdd, 0x86, 0x9a, 0x65, 0xbd, 0x89, 0x7a, 0xf0, 0x19, 0x77, 0x6c, 0xfa,
+       0xe9, 0xf5, 0xe0, 0xef, 0x4d, 0x6e, 0xa2, 0xa3, 0x5e, 0x0f, 0xc2, 0xdf,
+       0xab, 0x2c, 0xbf, 0xbb, 0xdc, 0x69, 0xf2, 0xa6, 0xc9, 0x59, 0xf9, 0x6f,
+       0x2a, 0x2e, 0x40, 0x7d, 0x13, 0x96, 0x47, 0x4d, 0xde, 0xc2, 0xf2, 0xa8,
+       0xc9, 0x9b, 0x7e, 0x9c, 0x32, 0xdd, 0xf4, 0xe5, 0x7f, 0x15, 0xfa, 0xe6,
+       0x7a, 0x6b, 0xe1, 0x35, 0x68, 0x17, 0x5b, 0x3b, 0x18, 0xed, 0x57, 0x0a,
+       0x66, 0x1b, 0x83, 0xb8, 0x4f, 0xb6, 0x7e, 0xc2, 0x68, 0xbe, 0x4f, 0xba,
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+       0x9e, 0xf3, 0x54, 0x16, 0x48, 0x48, 0x42, 0x7f, 0xb1, 0xc2, 0x4e, 0x44,
+       0xe0, 0x71, 0x7d, 0x99, 0x9c, 0xc7, 0xbf, 0xcb, 0x52, 0xbb, 0xe0, 0xf4,
+       0x54, 0xff, 0xdb, 0xda, 0xd5, 0xdf, 0x35, 0x3d, 0xe2, 0xe7, 0x67, 0x57,
+       0x7f, 0xc2, 0x94, 0xf6, 0x17, 0x60, 0x38, 0x47, 0xc8, 0x51, 0x71, 0x33,
+       0x3f, 0xa7, 0xa8, 0x1a, 0xad, 0x04, 0xb3, 0x69, 0xfe, 0xb5, 0xaa, 0x45,
+       0x11, 0xfb, 0x84, 0xc7, 0xcc, 0xdc, 0xce, 0x38, 0x32, 0xe5, 0x9a, 0x31,
+       0x48, 0xbf, 0x82, 0xb9, 0xc3, 0x12, 0x48, 0xbe, 0x6b, 0x87, 0xd0, 0x3e,
+       0xb0, 0x4a, 0xe8, 0xad, 0xce, 0x80, 0x3b, 0x01, 0xf5, 0x79, 0x67, 0x73,
+       0x0e, 0xed, 0xfb, 0x3a, 0x0f, 0x2d, 0x76, 0xf8, 0xa2, 0xe8, 0xaf, 0x03,
+       0x42, 0xce, 0x9e, 0x17, 0xe7, 0x2c, 0xed, 0x76, 0xa5, 0xd6, 0x08, 0xf2,
+       0xde, 0xce, 0x3a, 0xc8, 0x6e, 0x09, 0xd8, 0x6d, 0x51, 0xfd, 0x6e, 0x75,
+       0x66, 0x83, 0xb0, 0x77, 0x04, 0xdf, 0xe0, 0xcf, 0x08, 0xfd, 0x97, 0x08,
+       0x39, 0x9c, 0x07, 0x4d, 0x13, 0xf2, 0x22, 0xf8, 0x36, 0xfb, 0xaa, 0x0f,
+       0x54, 0x67, 0x77, 0x3e, 0xe0, 0xdf, 0x89, 0x88, 0x7d, 0xc3, 0x3f, 0x4a,
+       0x5f, 0x94, 0x6b, 0xa4, 0xef, 0x01, 0x5b, 0xeb, 0xb4, 0xa2, 0x28, 0xfe,
+       0x99, 0x47, 0x85, 0xbe, 0xbe, 0xec, 0xd9, 0x2f, 0xcc, 0xb8, 0xce, 0x4d,
+       0x69, 0x2e, 0x50, 0x91, 0x8e, 0x53, 0xec, 0x46, 0xc9, 0xdf, 0xb1, 0x5d,
+       0x9b, 0xaf, 0x43, 0xd9, 0x50, 0xc4, 0xeb, 0xb2, 0x67, 0x97, 0xdf, 0x31,
+       0x06, 0xe4, 0xb8, 0xea, 0x90, 0xd1, 0x63, 0x83, 0xf1, 0x55, 0x35, 0x7f,
+       0x64, 0xf6, 0x45, 0xd9, 0xbf, 0xe9, 0xe9, 0x89, 0xf0, 0xd1, 0x7e, 0x6c,
+       0x35, 0x73, 0xfb, 0xf8, 0xa8, 0xa9, 0x68, 0x29, 0xd2, 0xf5, 0xe8, 0xb5,
+       0xfc, 0x3c, 0xf7, 0x4f, 0x66, 0x4f, 0x45, 0x34, 0x3c, 0x67, 0x5b, 0x39,
+       0x9e, 0xf3, 0x58, 0xd1, 0xa7, 0xa3, 0x95, 0x7f, 0x3d, 0xfa, 0x16, 0xcc,
+       0x75, 0x84, 0x26, 0x01, 0x3d, 0x3a, 0xed, 0xfc, 0x7e, 0x72, 0x77, 0xf9,
+       0xe3, 0xf3, 0xbe, 0xd3, 0xa5, 0x04, 0xd7, 0x2a, 0x28, 0x87, 0x46, 0x9e,
+       0x4f, 0xe6, 0xf7, 0x7f, 0xa7, 0x31, 0xdf, 0x1d, 0x13, 0x15, 0x9a, 0xef,
+       0x97, 0x47, 0xea, 0xaf, 0x82, 0xa6, 0xe2, 0xc7, 0xf0, 0x3e, 0x4b, 0x65,
+       0xb3, 0xe2, 0x32, 0x40, 0x79, 0xa5, 0xda, 0x6a, 0x46, 0x39, 0xae, 0x6a,
+       0xda, 0xad, 0xa2, 0x5d, 0xfe, 0x03, 0x37, 0x7f, 0x67, 0xc1, 0xd4, 0xea,
+       0x61, 0xb3, 0x23, 0xfc, 0x5b, 0xad, 0x66, 0xee, 0x4f, 0x3a, 0xf0, 0xb7,
+       0xeb, 0xe6, 0x23, 0x7d, 0x3f, 0x9e, 0x6d, 0x61, 0x88, 0x97, 0x77, 0xe8,
+       0x47, 0x4e, 0x5c, 0xef, 0x3f, 0x6e, 0x1e, 0x45, 0xf3, 0x20, 0xd6, 0xb8,
+       0xfe, 0xe0, 0xf7, 0x5c, 0x33, 0x05, 0xfd, 0xf1, 0x66, 0xae, 0xcf, 0xf4,
+       0xf2, 0x30, 0x2d, 0x39, 0x5e, 0xca, 0x5f, 0x3b, 0x99, 0xf5, 0xc3, 0x73,
+       0xde, 0xcb, 0x2c, 0xad, 0x37, 0x79, 0xa2, 0xf0, 0x6f, 0x9d, 0x85, 0xcf,
+       0xd3, 0x5e, 0xeb, 0x37, 0xeb, 0xff, 0x30, 0xfd, 0x36, 0x11, 0xf4, 0x1b,
+       0x97, 0x6b, 0x53, 0xa4, 0x7e, 0x9b, 0x6e, 0xe1, 0x72, 0x1f, 0xa1, 0xdf,
+       0xd2, 0xa2, 0xe9, 0xb7, 0x55, 0x6b, 0xdd, 0x69, 0x28, 0x17, 0xab, 0xf6,
+       0xe6, 0xa4, 0x21, 0x5f, 0x57, 0x1d, 0x5e, 0x9a, 0x12, 0x4d, 0xbf, 0xbd,
+       0x20, 0xf6, 0xb5, 0x87, 0xc5, 0x3d, 0xe9, 0xf6, 0x7e, 0xa0, 0xdf, 0x46,
+       0x44, 0xe8, 0xb7, 0x7e, 0xa0, 0xdf, 0xa2, 0xf8, 0xc1, 0x47, 0x5b, 0x34,
+       0xbb, 0xb3, 0x07, 0xfd, 0x66, 0xfd, 0xef, 0x99, 0x7f, 0x2f, 0xa0, 0x7e,
+       0x8b, 0x32, 0xde, 0x2b, 0x84, 0xdc, 0x69, 0xfa, 0xad, 0xb0, 0x79, 0x2d,
+       0xe9, 0xb7, 0xc2, 0x7e, 0x46, 0xe9, 0x3e, 0xd2, 0x65, 0x16, 0x61, 0xc7,
+       0xc5, 0xd4, 0x6f, 0x0b, 0xef, 0xb9, 0x96, 0xf2, 0x26, 0x4f, 0x7c, 0x14,
+       0xf9, 0x41, 0xba, 0xa2, 0x7e, 0x3b, 0x2c, 0xf4, 0x1c, 0xf6, 0x83, 0x7a,
+       0xee, 0x67, 0x96, 0x6f, 0xa7, 0xe7, 0xe6, 0x59, 0x39, 0xbe, 0x3d, 0xea,
+       0xb9, 0xff, 0x26, 0x3a, 0x6b, 0x7a, 0x6e, 0x55, 0x7f, 0x85, 0xec, 0x97,
+       0xee, 0x72, 0xc8, 0xf5, 0xdc, 0xaa, 0x2c, 0xae, 0xe7, 0x56, 0xed, 0xe5,
+       0x7a, 0x6e, 0xd5, 0x20, 0xae, 0xe7, 0xf4, 0xfa, 0x6d, 0x52, 0x37, 0xfd,
+       0xc6, 0xdb, 0x57, 0xe6, 0x42, 0x7b, 0xda, 0x27, 0x66, 0xdd, 0x77, 0x03,
+       0xde, 0xe7, 0x2b, 0x31, 0x79, 0xac, 0x50, 0x7f, 0x86, 0x5b, 0x7b, 0x5f,
+       0x50, 0x3d, 0x26, 0x52, 0xdf, 0xfd, 0xcc, 0x12, 0x43, 0xdf, 0x79, 0x40,
+       0xdf, 0xd9, 0x7b, 0xd6, 0x77, 0xaf, 0xa0, 0xbe, 0x53, 0x49, 0x8f, 0x0d,
+       0xc4, 0x79, 0xa4, 0x97, 0x8f, 0xe9, 0x03, 0xe3, 0xa5, 0xfb, 0x6a, 0x47,
+       0xbf, 0x38, 0xf5, 0x9b, 0xdf, 0xe2, 0x7c, 0xf9, 0x83, 0x91, 0xee, 0x03,
+       0xbd, 0x6e, 0xe0, 0xfb, 0xa1, 0x7d, 0x5f, 0x9c, 0x1a, 0x85, 0xf3, 0xee,
+       0x65, 0xc4, 0x07, 0xe6, 0xcb, 0x4e, 0x21, 0x7f, 0x6d, 0xfe, 0xb1, 0xa4,
+       0x4f, 0x27, 0x0f, 0xe5, 0xf3, 0xbd, 0xe2, 0x50, 0x1c, 0xad, 0x13, 0x95,
+       0x8d, 0x0a, 0x1f, 0xef, 0x2d, 0x4a, 0xd0, 0x8d, 0xeb, 0xc0, 0xdf, 0x3e,
+       0xa7, 0x7d, 0xf2, 0xfc, 0xbd, 0x7c, 0x9f, 0x3c, 0xd7, 0xc2, 0xe9, 0xc1,
+       0x7e, 0x6c, 0xe4, 0xef, 0x22, 0x80, 0x04, 0x0b, 0x23, 0xe4, 0xa1, 0xe4,
+       0xf3, 0x72, 0xf2, 0xf3, 0x95, 0xa8, 0xcc, 0x8a, 0xf6, 0xeb, 0x82, 0x43,
+       0xd3, 0x3f, 0x40, 0xbb, 0x75, 0xc1, 0xe7, 0x35, 0x64, 0xef, 0x2e, 0xc0,
+       0xef, 0x78, 0xbf, 0x62, 0x77, 0xeb, 0x86, 0x4c, 0xe8, 0x77, 0xfe, 0x72,
+       0x85, 0xf6, 0x1b, 0x4c, 0xdc, 0x87, 0xd0, 0xee, 0x4b, 0x5c, 0xdf, 0xbc,
+       0x9f, 0xee, 0xaf, 0xe8, 0xef, 0x41, 0x68, 0xfa, 0x7c, 0x7e, 0xb5, 0xfc,
+       0x7d, 0x81, 0xce, 0xae, 0x3f, 0x20, 0xc6, 0x09, 0xf6, 0x2c, 0xd1, 0x85,
+       0xbd, 0x62, 0x8c, 0xea, 0x9f, 0x3b, 0xa0, 0xa7, 0x87, 0x87, 0x8f, 0xbf,
+       0x62, 0x35, 0xb7, 0x8f, 0xc3, 0xf4, 0x00, 0xfa, 0xb8, 0x95, 0xee, 0xf4,
+       0x00, 0x8e, 0xce, 0x58, 0x98, 0xda, 0x35, 0xfe, 0xf9, 0x4f, 0xc2, 0xb8,
+       0x92, 0xbb, 0xc6, 0xa5, 0xd1, 0x43, 0x3f, 0x3e, 0x6d, 0x7f, 0xb2, 0x40,
+       0xcc, 0x8d, 0x58, 0xe3, 0xd5, 0xe8, 0xd7, 0x6d, 0xbc, 0x1a, 0x3d, 0x75,
+       0xe3, 0x7e, 0xde, 0x22, 0xec, 0xa2, 0x8b, 0xd9, 0x30, 0x9c, 0x67, 0xaf,
+       0x1b, 0x7c, 0x77, 0x8c, 0x41, 0xb9, 0xf8, 0x3d, 0x8c, 0x1f, 0xf0, 0x99,
+       0x33, 0x6f, 0x50, 0x5a, 0xa4, 0x1e, 0x7e, 0x51, 0xe8, 0xf3, 0xab, 0x7c,
+       0xc7, 0xa7, 0xa4, 0xba, 0x91, 0x5e, 0xfc, 0xfd, 0xdd, 0x75, 0x65, 0xbb,
+       0x9f, 0x4f, 0x85, 0x71, 0x5c, 0xed, 0xcd, 0xca, 0xc3, 0xab, 0x08, 0xd7,
+       0xfe, 0xcd, 0xec, 0x43, 0x3f, 0xc2, 0x01, 0x5b, 0x07, 0xe9, 0x35, 0x4d,
+       0xae, 0x2e, 0xb4, 0x72, 0x39, 0xff, 0xbb, 0x80, 0x73, 0xb4, 0xaf, 0x6b,
+       0x0a, 0xad, 0x1f, 0x4d, 0x8a, 0x8b, 0xe6, 0x4b, 0x48, 0xa7, 0xb7, 0xc4,
+       0xbd, 0xb0, 0x2a, 0xa0, 0x27, 0xce, 0xc7, 0xaa, 0x26, 0xb1, 0xde, 0x80,
+       0xbc, 0xe1, 0x7c, 0x9b, 0xa6, 0xad, 0x3f, 0x48, 0x7f, 0xf8, 0xcf, 0xab,
+       0x9a, 0x39, 0xfd, 0xab, 0xaa, 0x15, 0xa2, 0xff, 0x4c, 0xd6, 0x71, 0x10,
+       0xe9, 0x5b, 0x99, 0xac, 0x78, 0x42, 0x00, 0x6a, 0x5a, 0xd3, 0xee, 0xdb,
+       0xf0, 0x1e, 0xd5, 0x0b, 0x36, 0xf8, 0x8e, 0xf3, 0xb6, 0x4c, 0xf1, 0x6c,
+       0xe7, 0xe4, 0xb0, 0x67, 0xa4, 0x46, 0x95, 0x4b, 0x35, 0x9a, 0x5c, 0xb2,
+       0xea, 0x21, 0xe4, 0x57, 0xd0, 0xd6, 0xc1, 0x05, 0x58, 0x2f, 0x09, 0xdf,
+       0x8b, 0xbc, 0x9e, 0x82, 0xf6, 0x89, 0xde, 0xde, 0xb8, 0xcc, 0xd2, 0x72,
+       0x14, 0xf1, 0xb8, 0xec, 0xc7, 0x26, 0xb6, 0x8d, 0x75, 0xb7, 0x3f, 0x34,
+       0x7e, 0xe7, 0xc2, 0xbf, 0x6f, 0xa2, 0xdd, 0xe7, 0xe9, 0x41, 0x7e, 0x07,
+       0x09, 0xfb, 0xf2, 0x05, 0xa4, 0xb7, 0x1d, 0xe9, 0xda, 0x61, 0x46, 0xb9,
+       0xaf, 0x0a, 0xf1, 0x75, 0x43, 0x2b, 0xaf, 0x52, 0xdd, 0x53, 0x88, 0x3e,
+       0x1a, 0xbd, 0x9b, 0x60, 0x5d, 0x18, 0xcd, 0xe9, 0x8d, 0xef, 0xbe, 0xf4,
+       0xf4, 0xbc, 0x5a, 0xcb, 0xa3, 0x3c, 0x63, 0xfd, 0x66, 0xc5, 0x84, 0xed,
+       0xaf, 0x04, 0x3e, 0xf4, 0x81, 0xa2, 0xc9, 0x86, 0x2f, 0x0e, 0x6a, 0xf2,
+       0x8b, 0xef, 0xc4, 0xf4, 0x74, 0xc1, 0xfd, 0x7f, 0x46, 0xc4, 0x7c, 0x47,
+       0xbd, 0x14, 0x79, 0xee, 0x58, 0xd9, 0x74, 0x84, 0xe8, 0x32, 0x7d, 0x35,
+       0x98, 0x55, 0x11, 0x74, 0x47, 0x7d, 0x75, 0x3e, 0xfa, 0x74, 0x9b, 0x0f,
+       0x4d, 0xfb, 0xa3, 0xde, 0x83, 0xfa, 0xb6, 0xf3, 0xe1, 0x42, 0xab, 0x3c,
+       0x1f, 0xf6, 0xd9, 0x3a, 0x5e, 0x1c, 0x81, 0xfe, 0xad, 0xbd, 0x0a, 0xe9,
+       0x03, 0xd6, 0x9c, 0x28, 0xed, 0xef, 0xaf, 0xb0, 0xf2, 0x7d, 0xd3, 0x01,
+       0x9b, 0x8f, 0xe4, 0xb6, 0xe3, 0xb0, 0x89, 0xee, 0x7b, 0xeb, 0xf5, 0xc6,
+       0x58, 0x41, 0x7f, 0xdc, 0x4f, 0x44, 0xbe, 0x83, 0x9b, 0x8c, 0x03, 0xc1,
+       0xf3, 0x5d, 0x97, 0x8d, 0xbd, 0xab, 0xe1, 0x91, 0xcd, 0xe5, 0x27, 0x52,
+       0x5f, 0xbf, 0x60, 0xf3, 0x11, 0x9f, 0x62, 0xc1, 0x9f, 0x26, 0xe0, 0xc7,
+       0xb2, 0x97, 0xc2, 0xf8, 0x62, 0x7f, 0x78, 0x9e, 0xe2, 0x96, 0xfb, 0xd3,
+       0xaf, 0x17, 0x9a, 0x9f, 0xa7, 0xa7, 0x71, 0x5d, 0x23, 0xd6, 0xfb, 0xef,
+       0x3a, 0xae, 0xf0, 0xf9, 0x24, 0x6b, 0x31, 0x33, 0xee, 0xcf, 0xdf, 0x6d,
+       0x8e, 0x38, 0x67, 0x9a, 0x23, 0xfc, 0xfc, 0x9a, 0x1f, 0x2c, 0xa2, 0xde,
+       0x4c, 0xcb, 0x98, 0xd8, 0xf5, 0xd0, 0xdf, 0x12, 0x82, 0x71, 0xbf, 0xb0,
+       0xeb, 0x21, 0xf2, 0xeb, 0x9e, 0x7b, 0xf4, 0xf8, 0x4c, 0x94, 0xdb, 0x15,
+       0xbf, 0x33, 0x32, 0x2b, 0xf0, 0xb9, 0x6d, 0x97, 0x83, 0x85, 0xf8, 0x3d,
+       0x0a, 0x33, 0xae, 0xab, 0xe5, 0x8d, 0xc6, 0xa8, 0xe7, 0x22, 0x8c, 0xad,
+       0x27, 0xfc, 0x56, 0xfc, 0xd6, 0x41, 0x7a, 0xa5, 0x7c, 0x8f, 0x25, 0x38,
+       0x03, 0xda, 0x97, 0x3f, 0xf5, 0xee, 0x70, 0xf4, 0x4f, 0xb5, 0xad, 0xe3,
+       0xfa, 0x25, 0xf0, 0xa8, 0x90, 0x8f, 0x40, 0xeb, 0x70, 0x3c, 0x2f, 0x2f,
+       0x57, 0xf9, 0x79, 0xb1, 0x1e, 0xde, 0x8f, 0x85, 0xbc, 0x9c, 0x7d, 0x3a,
+       0xbe, 0x04, 0xf5, 0xa3, 0x52, 0xcf, 0xdf, 0x75, 0x96, 0x37, 0xcc, 0x35,
+       0x59, 0x22, 0xf6, 0xe5, 0x95, 0x78, 0xe0, 0xc6, 0xeb, 0xd1, 0x3d, 0xe4,
+       0xc0, 0x23, 0x0a, 0xf9, 0xc1, 0xbb, 0xe3, 0xb7, 0x96, 0xd7, 0x7b, 0x84,
+       0xeb, 0xbd, 0xf2, 0x26, 0x53, 0x10, 0xdf, 0x87, 0x96, 0xd7, 0x6f, 0xa3,
+       0xfd, 0x6c, 0x55, 0xfd, 0x47, 0x66, 0xb4, 0xe3, 0x26, 0xff, 0xf6, 0x31,
+       0xb2, 0x23, 0xaa, 0x9a, 0x8c, 0xb2, 0x9f, 0xb0, 0xde, 0x18, 0xb2, 0x90,
+       0x1f, 0xd3, 0x78, 0x1c, 0x53, 0xbd, 0xbf, 0xae, 0xb2, 0xb1, 0x82, 0xe6,
+       0x63, 0x65, 0x83, 0xf0, 0x87, 0xe9, 0xfc, 0x45, 0x2b, 0x7e, 0xbb, 0xf7,
+       0xa9, 0x00, 0x90, 0x66, 0xc5, 0x13, 0xbf, 0x76, 0xa2, 0x9e, 0x39, 0xd3,
+       0xb2, 0xd3, 0x49, 0x7e, 0xb8, 0x7a, 0xee, 0x67, 0x53, 0xed, 0x6a, 0x74,
+       0x3f, 0x5c, 0x4f, 0xfe, 0xb7, 0x86, 0x4d, 0x51, 0xfd, 0x6f, 0x67, 0xf0,
+       0x3f, 0x60, 0xfe, 0x6d, 0xb5, 0xca, 0xfe, 0x37, 0x56, 0xdf, 0xa7, 0x57,
+       0xe7, 0xe0, 0x2b, 0x1e, 0xfb, 0xf4, 0x41, 0x3c, 0x17, 0x3a, 0xbb, 0xe7,
+       0xc3, 0x07, 0x11, 0xef, 0x95, 0x5f, 0x7f, 0xfc, 0xe0, 0x4f, 0xd1, 0x3e,
+       0xd9, 0x67, 0x73, 0xe1, 0x7a, 0x57, 0xf5, 0xe8, 0x51, 0xf2, 0xab, 0x6b,
+       0xed, 0x9e, 0x12, 0xf3, 0xaa, 0xed, 0x91, 0x5f, 0x3f, 0xfc, 0x00, 0xcc,
+       0xbf, 0xb6, 0x37, 0x2c, 0x74, 0xff, 0xaa, 0x6d, 0xef, 0xfb, 0x03, 0xdc,
+       0x30, 0xce, 0xb6, 0xdd, 0x5f, 0xa4, 0xa2, 0xff, 0x72, 0xf5, 0xde, 0xa9,
+       0xb4, 0x6f, 0x59, 0xfd, 0xe4, 0xe4, 0xb4, 0xf3, 0xdd, 0x23, 0x41, 0xb9,
+       0x0c, 0xf6, 0xe2, 0x3c, 0x44, 0xcf, 0x87, 0x03, 0x8d, 0x46, 0x86, 0xef,
+       0x20, 0xcf, 0x1d, 0xb3, 0x90, 0x9d, 0x11, 0xf6, 0xa3, 0x36, 0x54, 0x70,
+       0xbf, 0xb4, 0x5b, 0xf8, 0x4f, 0x77, 0x45, 0x3f, 0x77, 0xd2, 0xfc, 0x7e,
+       0x95, 0x8d, 0xd7, 0x5c, 0x7d, 0x29, 0xae, 0x7b, 0x8d, 0x26, 0x8f, 0x9b,
+       0xbe, 0x0b, 0x3f, 0x60, 0x4f, 0x7e, 0xd3, 0x57, 0x81, 0x9f, 0x23, 0x7a,
+       0xc1, 0xb7, 0x5d, 0xc2, 0x2f, 0xae, 0xe3, 0xdb, 0x39, 0xfc, 0x0f, 0xe0,
+       0xcf, 0x9f, 0xac, 0xb2, 0xbf, 0xf9, 0xd3, 0xc6, 0xa5, 0xbf, 0x7a, 0x00,
+       0xcb, 0x1a, 0xfb, 0xc4, 0xf4, 0x9b, 0x86, 0x7a, 0x41, 0x2f, 0xed, 0x5c,
+       0x6b, 0x9b, 0xd5, 0xfb, 0x8e, 0x15, 0xe7, 0xc3, 0x9e, 0xdf, 0x90, 0x7f,
+       0x1a, 0xf9, 0x05, 0x36, 0x37, 0x6b, 0x7b, 0xec, 0xd3, 0x01, 0xe8, 0x6f,
+       0x38, 0x6d, 0xea, 0xb8, 0x91, 0xee, 0x5f, 0xec, 0xb5, 0xd0, 0x3d, 0xa1,
+       0xf2, 0xbd, 0xaf, 0xd3, 0xfc, 0x68, 0x7b, 0xf2, 0x08, 0x9d, 0x17, 0x31,
+       0x71, 0xae, 0xd4, 0xc6, 0xc2, 0x7f, 0xfc, 0x1c, 0x40, 0xec, 0x65, 0xaa,
+       0x76, 0x38, 0xb8, 0xbf, 0x55, 0xd0, 0x1d, 0xfd, 0xb1, 0x6e, 0x27, 0x7d,
+       0x17, 0x7e, 0x57, 0x2e, 0xb7, 0x9a, 0x3f, 0x36, 0x96, 0x1f, 0xb6, 0x8f,
+       0x4d, 0xdc, 0x03, 0x17, 0xe7, 0x6c, 0x15, 0x3b, 0xde, 0x32, 0x33, 0x9d,
+       0x5f, 0x5b, 0x19, 0x8b, 0x7c, 0x3a, 0x2e, 0x9d, 0x0b, 0x6a, 0xe3, 0xd6,
+       0xc3, 0x73, 0x21, 0x1d, 0x2e, 0x89, 0x3c, 0x4f, 0x88, 0xe5, 0xe7, 0x16,
+       0x7a, 0x34, 0xcc, 0x27, 0x7e, 0x8e, 0xd0, 0xb6, 0x4d, 0x9c, 0x2f, 0x84,
+       0xcf, 0x0d, 0x18, 0xeb, 0x97, 0x87, 0xf7, 0xdf, 0xf9, 0x79, 0x77, 0x55,
+       0x50, 0x79, 0x9d, 0x45, 0x99, 0x8f, 0xda, 0x79, 0x82, 0xd3, 0xa6, 0x9b,
+       0x8f, 0xc1, 0xde, 0x9d, 0x23, 0xf4, 0x8c, 0xef, 0x77, 0xa3, 0x87, 0x62,
+       0xe3, 0xfb, 0x56, 0x8d, 0x2e, 0x67, 0xbf, 0x8a, 0xae, 0x8f, 0x87, 0xd8,
+       0x14, 0xf1, 0xfe, 0xc0, 0x97, 0x6b, 0x8b, 0x58, 0x77, 0x16, 0x88, 0xf5,
+       0xa4, 0x12, 0xe8, 0xc5, 0xdf, 0x93, 0x71, 0x7c, 0xcf, 0x8a, 0xfd, 0xdd,
+       0xd9, 0x47, 0x8d, 0x41, 0xdc, 0x07, 0x6f, 0x68, 0x38, 0x40, 0x7a, 0x55,
+       0x3f, 0xaf, 0x2b, 0x59, 0xf4, 0xf8, 0x21, 0xe3, 0x6d, 0x5c, 0x9f, 0x54,
+       0x36, 0xed, 0x1f, 0x8e, 0xfa, 0xe7, 0xec, 0xb3, 0x4f, 0x93, 0xdc, 0x55,
+       0xee, 0x3a, 0x6e, 0x0e, 0x00, 0x9c, 0x83, 0xf5, 0x4f, 0x98, 0x5b, 0x87,
+       0x76, 0xc9, 0x39, 0xea, 0xeb, 0x60, 0x84, 0xbe, 0x3e, 0xfb, 0xf8, 0xfe,
+       0xe1, 0xfc, 0x9c, 0x83, 0xef, 0x23, 0xf5, 0xf0, 0xaf, 0x10, 0xf0, 0xab,
+       0x9a, 0x65, 0xf8, 0x55, 0xbb, 0x3e, 0x92, 0xe0, 0xaf, 0x08, 0x34, 0x98,
+       0x5d, 0xf6, 0x9e, 0xfb, 0x39, 0xa3, 0x7a, 0xe7, 0xe2, 0x78, 0xcf, 0xb4,
+       0x98, 0x28, 0x2e, 0xca, 0x99, 0x06, 0x63, 0x61, 0xb4, 0x78, 0x25, 0x43,
+       0x31, 0x90, 0x54, 0x4a, 0x17, 0x9d, 0x36, 0x38, 0xf8, 0xfb, 0x38, 0x63,
+       0x92, 0x99, 0xec, 0xc8, 0xd5, 0x8e, 0xb1, 0xc7, 0x12, 0x92, 0x31, 0x35,
+       0xbb, 0x71, 0x1f, 0xbd, 0x7e, 0x2d, 0xbf, 0x0f, 0xb9, 0xfe, 0x67, 0x9e,
+       0x74, 0xe4, 0xcb, 0xfa, 0xc4, 0x39, 0x74, 0x0e, 0x54, 0xab, 0xa3, 0xa3,
+       0x2b, 0xd9, 0x55, 0x80, 0xfb, 0x6b, 0xd7, 0x94, 0xa2, 0xd1, 0x28, 0x56,
+       0x7a, 0x3d, 0x90, 0xe8, 0x35, 0x48, 0x78, 0xaf, 0x76, 0x14, 0xa6, 0xe1,
+       0x7b, 0xee, 0x5b, 0x85, 0x3d, 0xc2, 0x54, 0x0f, 0xbd, 0xdf, 0x33, 0x3a,
+       0xa7, 0x15, 0xe2, 0x38, 0x8c, 0x2e, 0x83, 0xcb, 0x16, 0x75, 0x1d, 0xe5,
+       0xf0, 0x4c, 0xf6, 0x22, 0x8a, 0x17, 0x61, 0x72, 0xc9, 0xef, 0xe9, 0xbe,
+       0xf7, 0xf8, 0x0f, 0xee, 0x7e, 0x72, 0xfc, 0x87, 0x40, 0xbf, 0x7f, 0x34,
+       0xfe, 0x03, 0xa3, 0x38, 0x18, 0xff, 0xef, 0xe3, 0x3f, 0x04, 0xb0, 0x9f,
+       0x7f, 0x81, 0xf8, 0x0f, 0x21, 0xf2, 0xdb, 0x68, 0xf1, 0x1f, 0x92, 0xbf,
+       0xe7, 0xf8, 0x0f, 0x6b, 0x99, 0x1c, 0xff, 0x41, 0xf0, 0x33, 0x1c, 0xff,
+       0x41, 0xf0, 0xf3, 0x7f, 0xe3, 0x3f, 0xfc, 0xff, 0x15, 0xff, 0xc1, 0x18,
+       0xf7, 0xf7, 0x29, 0x18, 0x9f, 0x41, 0x8b, 0xff, 0x90, 0x12, 0x67, 0x9e,
+       0x1a, 0x19, 0xff, 0xe1, 0xc2, 0xb8, 0x84, 0xa9, 0x91, 0xf1, 0x1f, 0xc6,
+       0xc5, 0xa5, 0x4f, 0x8d, 0x8c, 0xff, 0xf0, 0x83, 0xb8, 0xac, 0xa9, 0x91,
+       0xf1, 0x1f, 0xe6, 0xc7, 0x5d, 0x34, 0x35, 0x32, 0xfe, 0x43, 0x55, 0xdc,
+       0xa8, 0xa9, 0x91, 0xf1, 0x1f, 0xd6, 0xc6, 0x4d, 0xa4, 0xbc, 0x16, 0xff,
+       0xe1, 0xee, 0xb8, 0xa9, 0x53, 0xe5, 0xf8, 0x0f, 0x33, 0xa7, 0x4e, 0x81,
+       0x7c, 0x5b, 0x9c, 0xef, 0xef, 0xb8, 0x5e, 0xc5, 0x8a, 0xff, 0xf0, 0x1e,
+       0x4e, 0x96, 0x31, 0x3d, 0xc7, 0x7f, 0x00, 0x38, 0xe6, 0xb8, 0x31, 0xb1,
+       0xe3, 0x3f, 0xe8, 0xe1, 0xc4, 0x8a, 0xff, 0x00, 0x70, 0x12, 0x08, 0x4e,
+       0x8c, 0xf8, 0x0f, 0xdd, 0xf0, 0x89, 0x11, 0xff, 0x01, 0xe0, 0xa4, 0x13,
+       0x9c, 0x18, 0xf1, 0x1f, 0xba, 0xe1, 0x13, 0x23, 0xfe, 0x03, 0xc0, 0xc9,
+       0x22, 0x38, 0x31, 0xe2, 0x3f, 0xe8, 0xe1, 0xc4, 0x8a, 0xff, 0x00, 0x70,
+       0x2e, 0x8a, 0x4b, 0x89, 0x1d, 0xff, 0x41, 0x0f, 0x27, 0x56, 0xfc, 0x07,
+       0x80, 0x33, 0x8a, 0xf0, 0x89, 0x11, 0xff, 0xa1, 0x1b, 0x3e, 0x31, 0xe2,
+       0x3f, 0x00, 0x9c, 0x89, 0x04, 0x27, 0x46, 0xfc, 0x87, 0x6e, 0xf8, 0xc4,
+       0x88, 0xff, 0x00, 0x70, 0xa6, 0xd2, 0xb8, 0x62, 0xc4, 0x7f, 0xd0, 0xc3,
+       0x89, 0x15, 0xff, 0x01, 0xe0, 0xcc, 0x24, 0x7c, 0x62, 0xc4, 0x7f, 0xd0,
+       0xc3, 0x89, 0x15, 0xff, 0x01, 0xe0, 0xcc, 0x25, 0x7c, 0x62, 0xc4, 0x7f,
+       0xe8, 0x86, 0x4f, 0x8c, 0xf8, 0x0f, 0x00, 0xc7, 0x47, 0xf8, 0xc4, 0x88,
+       0xff, 0xd0, 0x0d, 0x9f, 0x18, 0xf1, 0x1f, 0x00, 0xce, 0x72, 0x82, 0x13,
+       0x23, 0xfe, 0x83, 0x1e, 0x4e, 0xac, 0xf8, 0x0f, 0x00, 0x67, 0x15, 0xc1,
+       0x89, 0x11, 0xff, 0x41, 0x0f, 0x27, 0x56, 0xfc, 0x07, 0x80, 0xf3, 0x53,
+       0x82, 0x13, 0x23, 0xfe, 0x43, 0x37, 0x7c, 0x62, 0xc4, 0x7f, 0x00, 0x38,
+       0xb7, 0x12, 0x9c, 0x18, 0xf1, 0x1f, 0xba, 0xe1, 0x13, 0x23, 0xfe, 0x03,
+       0xc0, 0xb9, 0x83, 0xe0, 0xc4, 0x88, 0xff, 0xa0, 0x87, 0x13, 0x2b, 0xfe,
+       0x03, 0xc0, 0xb9, 0x97, 0xe0, 0xc4, 0x88, 0xff, 0xa0, 0x87, 0x13, 0x2b,
+       0xfe, 0x03, 0xc0, 0xf9, 0x15, 0xc1, 0x89, 0x11, 0xff, 0xa1, 0x1b, 0x3e,
+       0x31, 0xe2, 0x3f, 0x00, 0x9c, 0x7a, 0x92, 0xc3, 0x18, 0xf1, 0x1f, 0xba,
+       0xe1, 0xf3, 0x5d, 0xe3, 0x3f, 0xd8, 0x42, 0x03, 0x95, 0x1c, 0x8a, 0xff,
+       0x40, 0x71, 0x22, 0xc3, 0xf1, 0x1f, 0x92, 0xbf, 0x75, 0xfc, 0x87, 0x66,
+       0xc4, 0xf7, 0x7f, 0xe3, 0x3f, 0xfc, 0xcf, 0x8c, 0xff, 0x70, 0xb3, 0xdd,
+       0xf7, 0x75, 0x1c, 0xf9, 0x41, 0xbf, 0x5b, 0xfc, 0x07, 0x5b, 0xfc, 0xb7,
+       0x8b, 0xff, 0x70, 0xb3, 0xbd, 0x28, 0x3e, 0x1e, 0xf7, 0x97, 0xdf, 0x32,
+       0xfe, 0x43, 0x6a, 0xfc, 0xb7, 0x8b, 0xff, 0x00, 0xfd, 0xa4, 0xc7, 0x8f,
+       0x89, 0xdd, 0x4f, 0xac, 0xf8, 0x0f, 0x39, 0xba, 0x7e, 0x7a, 0x8a, 0xff,
+       0x00, 0xfd, 0x0c, 0x3a, 0xef, 0x78, 0x62, 0xc4, 0x7f, 0xf0, 0xe8, 0xe8,
+       0xf6, 0x7d, 0xc5, 0x7f, 0xf8, 0x22, 0xee, 0xfc, 0xf1, 0x1f, 0xfe, 0xe5,
+       0xe2, 0x2c, 0xc0, 0x36, 0x05, 0xcf, 0x7f, 0x8a, 0x49, 0x14, 0xd9, 0xbf,
+       0x4c, 0xdc, 0x85, 0x6b, 0xe3, 0xff, 0xc9, 0x71, 0x17, 0xc8, 0x58, 0xf8,
+       0x57, 0x8a, 0xbb, 0xa0, 0xbd, 0xdf, 0x6f, 0x30, 0xe1, 0x7a, 0xf5, 0xa6,
+       0xe0, 0xfb, 0x6b, 0x42, 0x2e, 0xde, 0x12, 0xf1, 0x17, 0x8e, 0xc5, 0x8c,
+       0xbf, 0x10, 0xbc, 0x8a, 0xfc, 0xa2, 0xcb, 0xe5, 0xf8, 0x0b, 0xd3, 0x05,
+       0x1f, 0xe7, 0xf9, 0x64, 0x79, 0x98, 0xce, 0xf8, 0x79, 0xc3, 0xf4, 0x29,
+       0x59, 0x3c, 0x5e, 0x66, 0x99, 0x2e, 0xfe, 0x42, 0xae, 0x7c, 0x7e, 0x3d,
+       0xc3, 0x77, 0x64, 0x0a, 0x80, 0x63, 0x57, 0x79, 0xe4, 0x71, 0x1c, 0x11,
+       0xf2, 0x30, 0xb3, 0xe4, 0xa3, 0xe7, 0x90, 0x3d, 0x57, 0x8f, 0x8d, 0x1e,
+       0x7f, 0x61, 0x96, 0xe0, 0x47, 0xb1, 0x8e, 0x2e, 0xd3, 0x05, 0xdf, 0x8a,
+       0x45, 0x7a, 0x3d, 0x3e, 0x49, 0x01, 0x79, 0x9e, 0x51, 0x76, 0x44, 0x45,
+       0xba, 0xce, 0x74, 0xb7, 0xaa, 0xe4, 0xd7, 0xfe, 0x81, 0xc6, 0x3f, 0xb7,
+       0xc4, 0xbf, 0xd9, 0x02, 0xae, 0x1e, 0xdf, 0x59, 0x82, 0x7f, 0xb3, 0xae,
+       0xe4, 0xfc, 0xd3, 0xe3, 0xfd, 0x2a, 0xf2, 0xcf, 0x09, 0x69, 0xd9, 0x28,
+       0xe2, 0x9f, 0x1e, 0x6f, 0x3d, 0x9e, 0x7a, 0xfe, 0xb3, 0x48, 0x7e, 0x47,
+       0xc4, 0xcd, 0x28, 0x60, 0x72, 0xdc, 0x85, 0xc9, 0x56, 0x39, 0xee, 0xc2,
+       0x54, 0x97, 0x1c, 0x77, 0xe1, 0x8a, 0x74, 0x39, 0xee, 0xc2, 0x95, 0x6e,
+       0x39, 0xee, 0xc2, 0x0f, 0x72, 0xe5, 0xb8, 0x0b, 0x57, 0x79, 0xe4, 0xb8,
+       0x0b, 0x57, 0x8f, 0x95, 0xe3, 0x2e, 0x14, 0x7b, 0xd7, 0xea, 0xe2, 0x3e,
+       0x6c, 0xd2, 0xc5, 0x7d, 0xb8, 0x4b, 0x17, 0xf7, 0xe1, 0x7e, 0x5d, 0xdc,
+       0x87, 0x6d, 0xba, 0xb8, 0x0f, 0x8f, 0xe8, 0xe2, 0x3e, 0xec, 0xd6, 0xc5,
+       0x7d, 0x78, 0x5a, 0x17, 0xf7, 0x61, 0xbf, 0x94, 0x5f, 0x5c, 0x73, 0x58,
+       0xaa, 0xbf, 0xb4, 0xf6, 0x88, 0x94, 0x5f, 0x56, 0xf7, 0x86, 0x54, 0x7f,
+       0x79, 0xf0, 0xb8, 0x54, 0xbe, 0xa2, 0xfe, 0x03, 0xa9, 0xbc, 0xa2, 0xe1,
+       0x23, 0x29, 0x5f, 0xd5, 0xf4, 0x85, 0x54, 0xbf, 0xb7, 0x71, 0x1f, 0x5e,
+       0x15, 0xef, 0x81, 0x5f, 0x13, 0xef, 0x81, 0x8f, 0x89, 0xf7, 0xc0, 0x6f,
+       0xc6, 0x88, 0xfb, 0xf0, 0xd7, 0x9f, 0x7f, 0x71, 0x5b, 0xe4, 0x7b, 0xfc,
+       0x2f, 0x7f, 0xfe, 0xcd, 0x6d, 0xf8, 0x1e, 0xdf, 0x20, 0xde, 0xc1, 0xc6,
+       0x8a, 0xfb, 0x10, 0x2e, 0x8f, 0x11, 0xf7, 0xa1, 0xab, 0xfd, 0xb7, 0x8f,
+       0xfb, 0x90, 0x92, 0xfc, 0xcf, 0x7f, 0x87, 0x9f, 0x63, 0xe7, 0xe7, 0x9b,
+       0x13, 0xe2, 0x27, 0xe5, 0xd8, 0x53, 0xbe, 0xfb, 0x3b, 0xfc, 0x6b, 0x8b,
+       0xe4, 0xf7, 0xcc, 0x73, 0x4b, 0xe4, 0xf7, 0xcc, 0x39, 0x76, 0xae, 0xcf,
+       0xe7, 0xf9, 0xe4, 0x77, 0xcd, 0xd7, 0x97, 0xc9, 0xef, 0x9a, 0xcb, 0x6c,
+       0xbe, 0x6c, 0xc4, 0x43, 0x1f, 0xf7, 0x61, 0x42, 0xbc, 0x37, 0xc7, 0x8e,
+       0xfa, 0x52, 0xbc, 0xcf, 0x0f, 0xe1, 0xfb, 0x54, 0x58, 0x1b, 0x9f, 0xc5,
+       0xf7, 0xa9, 0x90, 0x3e, 0x87, 0x71, 0x1f, 0x20, 0x3d, 0x88, 0x71, 0x1f,
+       0x20, 0x3d, 0x84, 0x71, 0x1f, 0x20, 0xfd, 0x3d, 0xc6, 0x7d, 0x80, 0xf4,
+       0x25, 0x8c, 0xfb, 0x00, 0xe9, 0xcb, 0x18, 0xf7, 0x41, 0xc5, 0xb8, 0x11,
+       0x01, 0x11, 0x37, 0xa2, 0x46, 0xc4, 0x8d, 0xa8, 0x15, 0x71, 0x23, 0xea,
+       0x44, 0xdc, 0x88, 0xa0, 0x88, 0x1b, 0x51, 0x2f, 0xe2, 0x46, 0x34, 0x88,
+       0xb8, 0x11, 0x4d, 0x22, 0x6e, 0x44, 0x88, 0xe0, 0x9c, 0xf0, 0x1f, 0xa2,
+       0xf4, 0xa4, 0xbf, 0x85, 0xd2, 0x53, 0xfe, 0x63, 0x94, 0x9e, 0xf6, 0xb7,
+       0x52, 0x7a, 0xc6, 0x7f, 0x9a, 0xd2, 0xb3, 0xfe, 0x0e, 0x4a, 0xdb, 0xfc,
+       0x9f, 0x53, 0xda, 0xdb, 0xb8, 0x11, 0x9a, 0x5c, 0xfe, 0x19, 0xed, 0x06,
+       0x33, 0xf6, 0xcf, 0xe5, 0x58, 0x93, 0xd3, 0x19, 0xf6, 0x81, 0x1b, 0x22,
+       0xe5, 0xb4, 0xc8, 0x7e, 0xd1, 0x06, 0x94, 0xd3, 0x58, 0xf1, 0x22, 0xe6,
+       0x22, 0x4d, 0x53, 0x62, 0xc7, 0x8b, 0x08, 0x97, 0xc7, 0x88, 0x17, 0xd1,
+       0xd5, 0x3e, 0x76, 0xbc, 0x88, 0xb4, 0xd1, 0xdf, 0x5f, 0xbc, 0x88, 0x7f,
+       0x8b, 0xe7, 0xf2, 0xfa, 0x8f, 0xc6, 0x8b, 0x98, 0x5f, 0x2d, 0xc7, 0x33,
+       0x58, 0xb0, 0xe6, 0xfc, 0xf1, 0x22, 0xca, 0x6c, 0x45, 0xab, 0x51, 0x2e,
+       0x35, 0x79, 0xfc, 0xb7, 0x78, 0x7e, 0x5e, 0xd5, 0x53, 0xbc, 0x88, 0x6d,
+       0x76, 0x45, 0xac, 0xd7, 0x40, 0x17, 0xb4, 0xbb, 0x80, 0x2e, 0xb4, 0x5e,
+       0xf7, 0xf0, 0xde, 0xfe, 0x39, 0xc7, 0xc3, 0xb9, 0xb8, 0x9f, 0xe8, 0xcc,
+       0xbd, 0xe8, 0xbc, 0x71, 0x0e, 0xf4, 0x72, 0x11, 0x9b, 0xde, 0x3c, 0xae,
+       0xc1, 0x75, 0xdf, 0x73, 0x9c, 0x88, 0x9e, 0xe8, 0xaa, 0xd5, 0x7f, 0xb3,
+       0x9c, 0xc7, 0x2f, 0xf8, 0xb7, 0xf8, 0xf3, 0xc7, 0x2f, 0xe8, 0x16, 0x27,
+       0xa2, 0xa7, 0xf8, 0x02, 0x83, 0x3e, 0x23, 0x3d, 0xd9, 0xdb, 0x38, 0x11,
+       0x3d, 0xad, 0x0b, 0x3d, 0xd1, 0x73, 0xd6, 0xf7, 0x1c, 0x27, 0xa2, 0x27,
+       0xbd, 0xda, 0x93, 0x3e, 0xfd, 0xe3, 0x74, 0x4e, 0xe7, 0x09, 0xf1, 0xe7,
+       0x8f, 0xc7, 0x11, 0x8e, 0x0b, 0x67, 0x6d, 0x39, 0x48, 0x8d, 0x5d, 0x5e,
+       0x9a, 0xda, 0xaa, 0x78, 0x07, 0x5e, 0x30, 0xdb, 0x45, 0xfe, 0x93, 0xf6,
+       0x5d, 0xe2, 0xde, 0x98, 0x97, 0xb9, 0x5d, 0xa9, 0xfc, 0x9d, 0x3a, 0xda,
+       0x9b, 0xed, 0x7b, 0x12, 0x86, 0x33, 0x7a, 0xbf, 0xee, 0x62, 0x5e, 0xe0,
+       0x4f, 0xbc, 0xf8, 0xae, 0xec, 0xda, 0xbf, 0x1f, 0xcf, 0xd3, 0x6f, 0x75,
+       0x32, 0x6f, 0x62, 0x12, 0xc5, 0x83, 0x77, 0x1b, 0x73, 0x70, 0x1f, 0x36,
+       0xd2, 0x8a, 0xfe, 0x94, 0x8a, 0xc6, 0x8f, 0x5e, 0xfe, 0x1d, 0xc0, 0xb5,
+       0x35, 0x1b, 0xe9, 0x3e, 0x59, 0x3b, 0xe0, 0xd0, 0x42, 0x76, 0x9f, 0x37,
+       0x11, 0xf9, 0x16, 0xcf, 0x6e, 0xa7, 0x7d, 0x3a, 0x9e, 0x71, 0x7d, 0xd3,
+       0x27, 0xf2, 0x3d, 0xb3, 0xee, 0xf7, 0x1b, 0xb0, 0x4a, 0xc4, 0xf9, 0xcd,
+       0x54, 0xa3, 0x9d, 0xf6, 0x4d, 0x9d, 0x5b, 0xf9, 0x3d, 0x4f, 0x23, 0xbb,
+       0xe8, 0xbe, 0x89, 0xc9, 0x74, 0x9f, 0x9a, 0x05, 0xdd, 0xc4, 0x3f, 0xb2,
+       0x53, 0x57, 0x08, 0x3c, 0x3b, 0x31, 0xc5, 0xfa, 0x3e, 0x2b, 0xd9, 0x8f,
+       0xcb, 0x0e, 0x3f, 0x91, 0x1f, 0x62, 0xfc, 0xbc, 0x32, 0xd2, 0x6f, 0xd0,
+       0xa7, 0x50, 0xf6, 0xd3, 0xd4, 0xd9, 0x9c, 0xc3, 0xf1, 0x5d, 0x25, 0x0b,
+       0x78, 0x5b, 0xd0, 0xfe, 0x5e, 0x22, 0xe0, 0xa5, 0x14, 0xc9, 0xfe, 0x9b,
+       0x0f, 0x17, 0x15, 0x1e, 0xc2, 0x73, 0xfa, 0x25, 0xbe, 0x52, 0xba, 0x87,
+       0x90, 0x56, 0x22, 0xfb, 0x73, 0x98, 0x78, 0x37, 0x8e, 0xdb, 0xb1, 0xf0,
+       0x7d, 0x39, 0xc0, 0xa7, 0xb4, 0x49, 0x61, 0x0f, 0x28, 0xdd, 0xdf, 0x91,
+       0x97, 0x35, 0xdf, 0xb5, 0x01, 0xf7, 0x39, 0xcb, 0x83, 0x7a, 0xfb, 0x9b,
+       0xe5, 0xa2, 0x9c, 0x95, 0xb3, 0x38, 0x0f, 0xee, 0x7b, 0x57, 0xd4, 0xcb,
+       0xe5, 0x0e, 0x87, 0xb8, 0xcf, 0x61, 0x67, 0xf6, 0x5e, 0xd1, 0xad, 0x75,
+       0xf0, 0x7d, 0x13, 0x47, 0x9f, 0x97, 0x6e, 0x9e, 0x10, 0xd6, 0xdf, 0xe5,
+       0xa0, 0xfb, 0xb0, 0xcb, 0x0e, 0x2f, 0x36, 0x23, 0xb3, 0x2c, 0xe9, 0x32,
+       0xdd, 0x6c, 0x6e, 0x99, 0x6e, 0xf1, 0xb9, 0x32, 0x7d, 0xf4, 0xf4, 0x73,
+       0x78, 0x64, 0xfa, 0xe8, 0xe9, 0x97, 0x30, 0x56, 0xf6, 0x7f, 0x69, 0xf4,
+       0xd3, 0xee, 0x1b, 0xaa, 0x4c, 0xdc, 0x17, 0x0d, 0xf2, 0x7b, 0xa4, 0xdd,
+       0xde, 0xe1, 0x37, 0x6d, 0x23, 0x3c, 0xf5, 0xf4, 0xd3, 0xd3, 0x6b, 0x94,
+       0x43, 0xdc, 0x93, 0xe8, 0xa2, 0x57, 0x91, 0x35, 0x95, 0x54, 0x3e, 0xe1,
+       0x99, 0xa1, 0x86, 0x48, 0xbe, 0xf5, 0xf3, 0x21, 0xd3, 0x1e, 0x52, 0xf0,
+       0xbf, 0xfb, 0x27, 0x07, 0xd7, 0x52, 0x2b, 0x8f, 0x43, 0x45, 0xbd, 0x95,
+       0xce, 0x41, 0x33, 0x65, 0x09, 0x6f, 0x17, 0x8f, 0xf3, 0x01, 0xe3, 0xca,
+       0x32, 0x0f, 0xcd, 0x07, 0xdc, 0xd1, 0xa3, 0x7f, 0x37, 0x9e, 0xfd, 0x59,
+       0xc8, 0xfd, 0xbb, 0xec, 0x1b, 0x48, 0x6f, 0x2a, 0x7e, 0xee, 0xf8, 0x22,
+       0x28, 0xdd, 0x8a, 0xf2, 0x36, 0x82, 0xff, 0xfe, 0x02, 0xf9, 0xab, 0xb4,
+       0xdf, 0x4d, 0x60, 0x1e, 0x17, 0xee, 0xa3, 0x1a, 0xfc, 0x56, 0xf7, 0x12,
+       0x15, 0xcf, 0x05, 0x99, 0x7b, 0xc9, 0x40, 0x3c, 0x0f, 0x74, 0x51, 0x7a,
+       0xa7, 0x78, 0xf7, 0xdb, 0x3e, 0x94, 0xd1, 0xbe, 0xbf, 0x21, 0xf4, 0x49,
+       0x2a, 0x9e, 0xa3, 0xdd, 0x99, 0xd7, 0x31, 0x13, 0xfd, 0x0f, 0x55, 0x4b,
+       0x59, 0x11, 0xae, 0x5f, 0x3f, 0x72, 0xf2, 0x77, 0x17, 0x9b, 0x44, 0x3a,
+       0xc2, 0xc9, 0xfd, 0x33, 0x9b, 0x8b, 0x0c, 0xcc, 0x3b, 0x1a, 0x7f, 0x87,
+       0xc7, 0x18, 0x54, 0xd0, 0xef, 0xea, 0xf2, 0x1e, 0xbe, 0x1c, 0xed, 0xd1,
+       0x66, 0x93, 0x9b, 0xde, 0x11, 0xbb, 0x3a, 0x5e, 0xbe, 0x9e, 0xca, 0x47,
+       0xd1, 0xfb, 0xe8, 0x0c, 0x43, 0xed, 0x48, 0xc4, 0x07, 0xea, 0xd3, 0xfb,
+       0xda, 0xf6, 0xe6, 0x77, 0x9d, 0x8b, 0x23, 0xf4, 0x70, 0x5b, 0xd3, 0xdd,
+       0x43, 0xf0, 0x7e, 0xf1, 0xfd, 0x86, 0xe8, 0xef, 0x7a, 0x4b, 0x1d, 0xda,
+       0xfb, 0x36, 0x7e, 0xbf, 0x63, 0x44, 0x57, 0x9c, 0x81, 0x52, 0xc7, 0x18,
+       0x8a, 0x47, 0x70, 0x67, 0x36, 0xf4, 0x53, 0x59, 0xdc, 0x49, 0x7c, 0xd4,
+       0xe4, 0x72, 0x82, 0xa0, 0xff, 0x73, 0xa5, 0xd3, 0x09, 0xbf, 0x27, 0x9b,
+       0x15, 0x37, 0xfa, 0xeb, 0xa6, 0x19, 0x6f, 0xf8, 0xc1, 0x30, 0xc0, 0x6f,
+       0xdc, 0x51, 0x95, 0xeb, 0x2f, 0x71, 0xaf, 0x7b, 0xb4, 0xa8, 0xff, 0x34,
+       0xf3, 0xa4, 0x23, 0xbe, 0xe3, 0x2e, 0x65, 0x0a, 0xce, 0x9f, 0x71, 0x6f,
+       0x30, 0x4f, 0x00, 0x49, 0x5c, 0x5d, 0x4a, 0xf7, 0xe9, 0x7e, 0xe7, 0x9c,
+       0x76, 0x08, 0xf9, 0x35, 0xa5, 0x19, 0xe4, 0x09, 0xf5, 0xc8, 0x59, 0xbb,
+       0x07, 0xaf, 0xca, 0x8f, 0x69, 0x91, 0xef, 0xcb, 0x25, 0x4e, 0xf1, 0x1d,
+       0xc0, 0xfb, 0x85, 0x97, 0x1c, 0x63, 0xa4, 0xcf, 0x2e, 0x39, 0xa6, 0xea,
+       0xef, 0xc7, 0x18, 0x71, 0xbf, 0x3f, 0xae, 0x55, 0xfe, 0x3e, 0x41, 0xb7,
+       0xff, 0x5c, 0xa7, 0xc9, 0x9d, 0x93, 0xa5, 0xa2, 0xdc, 0x6d, 0xf9, 0xca,
+       0x48, 0x78, 0xb5, 0x77, 0x30, 0xcf, 0x3a, 0x80, 0xdb, 0xbe, 0xa4, 0x2f,
+       0x9d, 0xdb, 0xb6, 0x7f, 0xc2, 0xc8, 0x4e, 0x6c, 0xff, 0xca, 0x58, 0x18,
+       0xed, 0x7e, 0xc9, 0xdd, 0x0e, 0xee, 0xf7, 0xba, 0xdf, 0xcc, 0x48, 0x7f,
+       0xdf, 0x5f, 0x6a, 0xa7, 0x77, 0x0e, 0xcf, 0x96, 0x96, 0x5f, 0x80, 0xf6,
+       0xc5, 0x67, 0x3f, 0xf1, 0x5d, 0x10, 0xcd, 0x4f, 0x19, 0x61, 0xa7, 0x25,
+       0xf0, 0xf7, 0xe7, 0xde, 0x04, 0x36, 0x16, 0xe5, 0xf0, 0x56, 0x85, 0xd3,
+       0xbb, 0x36, 0xa3, 0x28, 0xca, 0xba, 0xa5, 0xc9, 0x9d, 0x26, 0x87, 0x9a,
+       0xfc, 0x65, 0x94, 0xc6, 0xf9, 0xa2, 0xdd, 0xd7, 0x4c, 0x76, 0x72, 0xfb,
+       0x68, 0x52, 0x69, 0xae, 0x62, 0x46, 0xf9, 0xd9, 0xa7, 0x30, 0xa4, 0x6b,
+       0xdb, 0x3a, 0xc0, 0xeb, 0x3c, 0xeb, 0x76, 0x80, 0xad, 0xcb, 0x44, 0x7c,
+       0xaa, 0x9a, 0x3e, 0xa6, 0x7b, 0x58, 0xd6, 0x66, 0x25, 0xea, 0xef, 0xf2,
+       0x3c, 0xe1, 0x70, 0xf2, 0xfb, 0x80, 0xeb, 0x02, 0x6b, 0xf1, 0xfe, 0xc5,
+       0xcd, 0x30, 0x89, 0x50, 0x4f, 0x65, 0x98, 0x6b, 0xb3, 0xa2, 0xc1, 0x0f,
+       0xb0, 0x2d, 0x64, 0x97, 0x3e, 0xe0, 0x70, 0xf3, 0x77, 0x03, 0x56, 0x11,
+       0x47, 0x48, 0xad, 0xcd, 0xc0, 0xfb, 0x08, 0x6d, 0x4d, 0x93, 0xaf, 0xdc,
+       0x00, 0x78, 0x3e, 0x00, 0xf3, 0x01, 0xf9, 0x7b, 0xbf, 0xc9, 0x43, 0x78,
+       0x07, 0x2a, 0x18, 0xa3, 0xfb, 0xa4, 0xc2, 0x5f, 0xd7, 0x6f, 0x26, 0xdb,
+       0xb6, 0x39, 0xc2, 0xfe, 0xdd, 0xeb, 0x28, 0x38, 0x8c, 0x72, 0x7b, 0xd8,
+       0xc1, 0xed, 0xc6, 0x3e, 0x3e, 0x8f, 0x82, 0x78, 0x7b, 0xfe, 0xfe, 0x57,
+       0x27, 0xc2, 0x6f, 0xff, 0xdc, 0x42, 0xfc, 0xeb, 0x2b, 0xec, 0x4d, 0xad,
+       0xdd, 0x49, 0x07, 0xa7, 0x4f, 0x89, 0xd3, 0x7b, 0x00, 0xdb, 0xb3, 0xb2,
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+       0xde, 0x51, 0xec, 0x2b, 0x6d, 0x5d, 0x4f, 0xf2, 0x31, 0x3a, 0x9f, 0x48,
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+       0x8f, 0xef, 0x98, 0xde, 0xfe, 0xd9, 0xc7, 0x0e, 0x7c, 0xd7, 0xf2, 0x17,
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+       0x82, 0x09, 0x45, 0x53, 0x90, 0xae, 0x0b, 0xfc, 0x7f, 0xcf, 0x8f, 0xb4,
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+       0x13, 0xbf, 0xcf, 0xa9, 0xe7, 0xc3, 0x3a, 0xc1, 0x87, 0xe5, 0xbb, 0xb6,
+       0x99, 0x33, 0xdd, 0xd8, 0xbf, 0x6f, 0x0e, 0xf6, 0x7f, 0x5a, 0xec, 0x6f,
+       0x4e, 0x37, 0x3a, 0xe8, 0x3d, 0x85, 0x86, 0xcf, 0xa2, 0x5d, 0x23, 0xcd,
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+       0x4f, 0x43, 0x3f, 0xfa, 0xd2, 0x4d, 0x0a, 0xed, 0xe3, 0xb0, 0xfe, 0x2d,
+       0xb0, 0x4e, 0xf8, 0xd6, 0x6c, 0xa4, 0x77, 0x3c, 0xfa, 0x71, 0x2e, 0x0c,
+       0xc8, 0xfe, 0x1c, 0x7d, 0xbc, 0x46, 0x6d, 0x3f, 0xb0, 0x4c, 0xf0, 0x7f,
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+       0xb4, 0x78, 0x18, 0x5a, 0x7a, 0x56, 0x9c, 0xf7, 0xe3, 0xbd, 0x7e, 0x4c,
+       0x4f, 0xfb, 0x19, 0xa5, 0x53, 0x12, 0xdc, 0x3c, 0x5e, 0x57, 0xf3, 0x91,
+       0x9b, 0x51, 0xae, 0x2a, 0x9b, 0x76, 0x53, 0x7c, 0xc4, 0x7d, 0xc1, 0xf7,
+       0xfa, 0x8c, 0x87, 0x2a, 0x05, 0xcd, 0x5f, 0x18, 0x51, 0xa8, 0x0a, 0x84,
+       0x3d, 0x36, 0x5f, 0xd8, 0x63, 0x7b, 0x18, 0x97, 0x1b, 0xb0, 0xa3, 0x37,
+       0xa3, 0xfc, 0x5f, 0xfe, 0xb9, 0xce, 0x8e, 0x16, 0xe3, 0xbc, 0x41, 0x93,
+       0xfb, 0x43, 0x49, 0x24, 0x37, 0x37, 0xe0, 0xb8, 0x86, 0xe3, 0x77, 0xf5,
+       0x93, 0x68, 0xe3, 0xba, 0x3b, 0x41, 0x7e, 0xff, 0xd5, 0xdb, 0x71, 0x69,
+       0xe3, 0xd1, 0xc6, 0xa7, 0x95, 0x57, 0x88, 0xf7, 0xe7, 0xfa, 0x76, 0x9a,
+       0x9c, 0x4f, 0x11, 0x72, 0xb7, 0x64, 0x47, 0xf1, 0x86, 0xbe, 0x40, 0x8a,
+       0xf5, 0x7b, 0xdf, 0x1f, 0x20, 0xe2, 0xc8, 0x51, 0x9c, 0x2d, 0x4d, 0x8e,
+       0xf4, 0x72, 0xb2, 0x4c, 0xf0, 0x2d, 0x2c, 0x0f, 0xcd, 0x77, 0xd0, 0xb8,
+       0x34, 0xbe, 0x81, 0xbc, 0xa7, 0x8b, 0x77, 0x49, 0xe9, 0xe8, 0xcf, 0xe8,
+       0x49, 0x2e, 0xf4, 0xfc, 0x6f, 0x33, 0xb5, 0x0e, 0xc0, 0xf9, 0xaa, 0xe7,
+       0x7f, 0x5b, 0x8c, 0x73, 0x9f, 0xed, 0x09, 0xfc, 0x5c, 0x63, 0x89, 0xdb,
+       0x3b, 0x0d, 0xfd, 0x2b, 0x60, 0x1e, 0x6e, 0x70, 0x45, 0xd8, 0x0f, 0xa7,
+       0xd5, 0xda, 0x83, 0x3f, 0xc5, 0x79, 0xb4, 0x83, 0xcb, 0x71, 0xe4, 0xba,
+       0x48, 0xc6, 0xd2, 0x8b, 0x26, 0x5a, 0x67, 0x57, 0x39, 0xdc, 0x69, 0x89,
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+       0x57, 0x55, 0x32, 0x78, 0xae, 0x5c, 0xae, 0x99, 0x85, 0xcf, 0xf5, 0x6f,
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+       0x23, 0xb1, 0xa7, 0x52, 0x60, 0xfe, 0xb3, 0x8a, 0xff, 0xbd, 0x08, 0x78,
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+       0xf8, 0xff, 0x32, 0xc7, 0x8c, 0x2f, 0x24, 0x78, 0xdf, 0xfd, 0xed, 0xf2,
+       0x29, 0x73, 0x0e, 0x5e, 0x5d, 0x6d, 0x32, 0xc0, 0xf8, 0xa5, 0x2f, 0x49,
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+       0x78, 0xf4, 0x78, 0xf3, 0x4a, 0xde, 0xcf, 0x32, 0x5c, 0x19, 0x0d, 0xfd,
+       0x4f, 0x9a, 0x6b, 0x78, 0x7f, 0x2a, 0x4c, 0x99, 0xcc, 0xd8, 0xc9, 0xe6,
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+       0x9b, 0x22, 0x39, 0x3f, 0x35, 0x19, 0x81, 0x2f, 0x63, 0x70, 0xbc, 0x4a,
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+       0x6a, 0x1b, 0xc7, 0x35, 0xf2, 0xc3, 0xff, 0xb4, 0xd5, 0xf0, 0x28, 0x5b,
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+       0x10, 0xaf, 0xee, 0xcf, 0x11, 0xaf, 0x79, 0x3d, 0xbd, 0xd3, 0x51, 0x0f,
+       0xb7, 0x7e, 0xf0, 0x49, 0x81, 0x3b, 0x9b, 0xd3, 0x0b, 0xe7, 0xc9, 0xeb,
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+       0x75, 0x49, 0xaa, 0x9d, 0xdd, 0x03, 0x72, 0xd7, 0xe8, 0x64, 0xaa, 0x09,
+       0xd6, 0x95, 0xc8, 0x5e, 0xb2, 0xa3, 0xfd, 0x30, 0x20, 0x7d, 0x40, 0x05,
+       0xb5, 0x32, 0xae, 0x5f, 0x3a, 0xa3, 0x5c, 0x5f, 0xe2, 0x73, 0x6c, 0xa4,
+       0x8f, 0xec, 0x4c, 0xb5, 0xdd, 0xf5, 0x15, 0xbe, 0x5f, 0xd3, 0xcf, 0xac,
+       0x37, 0x66, 0x48, 0x3d, 0xac, 0xd7, 0x57, 0xa6, 0x9c, 0xc7, 0x65, 0x06,
+       0x7c, 0x10, 0x93, 0xd2, 0x76, 0x7c, 0x29, 0xea, 0xf3, 0xdf, 0x9a, 0x1d,
+       0xb7, 0xa8, 0x08, 0x8f, 0x93, 0x3d, 0x0e, 0x70, 0x6c, 0x33, 0x30, 0x85,
+       0xc5, 0x10, 0x7b, 0x64, 0x28, 0x70, 0xdf, 0xca, 0xc2, 0x1d, 0xeb, 0x50,
+       0xde, 0x1d, 0x2c, 0xc9, 0x03, 0xf2, 0x85, 0x68, 0x23, 0xe0, 0xe0, 0x17,
+       0x07, 0xf6, 0xd0, 0x28, 0x64, 0x48, 0x5b, 0x07, 0x3c, 0x5f, 0xca, 0xa0,
+       0x9d, 0x84, 0x70, 0xdd, 0x4a, 0xeb, 0x92, 0x91, 0x9f, 0x26, 0x30, 0x97,
+       0x8c, 0x7a, 0xab, 0x80, 0x79, 0xad, 0xd8, 0xf6, 0x77, 0xbc, 0x95, 0x84,
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+       0x83, 0xf4, 0x46, 0x7e, 0xb4, 0x44, 0xf8, 0x9f, 0x15, 0x63, 0xa4, 0x36,
+       0xdc, 0xd8, 0x32, 0x17, 0xf9, 0x34, 0xfc, 0x12, 0xb3, 0xa3, 0x1f, 0xd0,
+       0xff, 0x0b, 0x93, 0x82, 0xf3, 0x83, 0x60, 0xdc, 0x89, 0xd7, 0x1d, 0xfb,
+       0x0d, 0x0c, 0xe1, 0xfc, 0xb5, 0xd1, 0x6b, 0x8f, 0x82, 0xbe, 0x3f, 0x53,
+       0x51, 0x5f, 0x66, 0x81, 0xf9, 0xfa, 0x05, 0x9d, 0xb5, 0x79, 0x9f, 0x37,
+       0xa9, 0x99, 0xd1, 0xd0, 0xaf, 0x8a, 0x91, 0x08, 0x2f, 0xbf, 0x2e, 0xe2,
+       0xf6, 0xd8, 0xff, 0x85, 0xc9, 0xfb, 0x72, 0x2a, 0xe2, 0xc7, 0xb2, 0xda,
+       0x1b, 0x24, 0x57, 0xe3, 0xa3, 0xf9, 0xb8, 0xba, 0xb8, 0xe2, 0xb1, 0xd1,
+       0xf0, 0x7c, 0x4b, 0x47, 0x38, 0xc3, 0xf7, 0x4f, 0xea, 0x0c, 0x37, 0x20,
+       0xfe, 0x37, 0x6f, 0xc9, 0x0d, 0x43, 0x3e, 0xd8, 0x86, 0xb8, 0x81, 0xf5,
+       0xc7, 0x98, 0xed, 0x8f, 0xe0, 0x7c, 0x31, 0x57, 0x00, 0xde, 0x54, 0xba,
+       0xee, 0x24, 0xbc, 0x2a, 0xea, 0x84, 0x28, 0xc0, 0x6b, 0xe1, 0x4c, 0x9b,
+       0xba, 0x0e, 0xf0, 0xfe, 0xeb, 0xb0, 0x96, 0x99, 0xc8, 0xf7, 0xfe, 0xad,
+       0x06, 0xf6, 0x32, 0xbc, 0x62, 0x9b, 0xc9, 0x31, 0x07, 0xfb, 0xdb, 0x2e,
+       0xab, 0x76, 0xd4, 0xb3, 0xbf, 0x4e, 0x6d, 0x09, 0xa7, 0xf5, 0x6c, 0x35,
+       0xd0, 0x7a, 0xb6, 0x85, 0xfb, 0xc7, 0xad, 0x01, 0xb8, 0xd7, 0x65, 0x28,
+       0x15, 0x08, 0x9f, 0x62, 0x65, 0x0a, 0xea, 0x5f, 0xc5, 0x50, 0xac, 0x3e,
+       0x02, 0xd7, 0xa7, 0x45, 0x73, 0xfd, 0xa8, 0xe9, 0xe3, 0x9a, 0x68, 0x95,
+       0xfa, 0xcf, 0x4b, 0xf0, 0xfe, 0x5c, 0x1c, 0x57, 0x44, 0x72, 0x53, 0x26,
+       0xdb, 0x48, 0xde, 0xfa, 0xfd, 0xcc, 0x6b, 0x86, 0xf7, 0xc4, 0xcf, 0xeb,
+       0x95, 0x91, 0x1e, 0xe1, 0x73, 0x80, 0x95, 0x90, 0xdf, 0x15, 0x9f, 0xcc,
+       0x70, 0x3e, 0x17, 0x12, 0x1a, 0x5a, 0x9b, 0xd1, 0xab, 0x92, 0x9e, 0x75,
+       0xda, 0x96, 0x00, 0xdd, 0xa7, 0x0b, 0x3d, 0x3b, 0xfd, 0x64, 0x4d, 0x25,
+       0x8b, 0xc4, 0x8e, 0xe3, 0xd8, 0x54, 0x98, 0x6f, 0x9f, 0xcd, 0xc8, 0x70,
+       0x5d, 0xb7, 0xb1, 0x3e, 0xd9, 0x02, 0xfd, 0xdb, 0xae, 0x32, 0x87, 0x0f,
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+       0x62, 0x9e, 0x5f, 0x49, 0x4c, 0x89, 0x82, 0x71, 0x45, 0x5f, 0xaa, 0x0a,
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+       0xad, 0xc4, 0xa2, 0xbb, 0x8e, 0xfe, 0x5c, 0x24, 0xb6, 0x4a, 0xe0, 0x3a,
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+       0x91, 0xdf, 0x50, 0x6f, 0x8c, 0xfd, 0x45, 0x5c, 0x2c, 0xea, 0xed, 0x88,
+       0x68, 0xae, 0x4f, 0xb4, 0x56, 0xe3, 0x2f, 0xe4, 0x23, 0x7b, 0x14, 0xe7,
+       0x23, 0xfb, 0xad, 0x01, 0xf9, 0xfb, 0x5e, 0x74, 0x2a, 0x8d, 0xd3, 0xe4,
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+       0xee, 0xd2, 0xe4, 0xab, 0xa6, 0x60, 0xfb, 0xdd, 0x15, 0xc7, 0xe1, 0x2d,
+       0x93, 0xbf, 0x25, 0xbf, 0xfa, 0x62, 0xbb, 0x44, 0xfe, 0x7c, 0x42, 0x3b,
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+       0xc7, 0x94, 0xd5, 0x69, 0xd8, 0xdf, 0xae, 0x70, 0x3d, 0xb2, 0xbd, 0xdd,
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+       0x10, 0xdf, 0x3e, 0x2e, 0xf4, 0x40, 0x8b, 0xd1, 0x37, 0xe5, 0x73, 0xf4,
+       0x7f, 0x0f, 0x70, 0xfa, 0x4e, 0xbe, 0x2b, 0x57, 0x36, 0xc1, 0xb8, 0x11,
+       0x0f, 0x70, 0xb9, 0xce, 0x3f, 0x67, 0xda, 0x28, 0xc3, 0x3c, 0xd5, 0x31,
+       0x45, 0xbe, 0x68, 0x18, 0xdf, 0x17, 0xcd, 0xed, 0x62, 0xdd, 0x19, 0x18,
+       0x05, 0x7c, 0x59, 0x7b, 0xc6, 0x44, 0xfa, 0xed, 0xad, 0xce, 0x23, 0xe5,
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+       0x67, 0xe3, 0x78, 0xce, 0x47, 0xdd, 0xa2, 0xd5, 0xfa, 0x53, 0x70, 0x4d,
+       0x31, 0x64, 0x76, 0x8e, 0x25, 0x01, 0x7e, 0x5d, 0xc2, 0x4e, 0x4c, 0x61,
+       0x5c, 0x0f, 0xb9, 0x90, 0x3f, 0x72, 0x02, 0x7d, 0xe6, 0x34, 0x52, 0x3c,
+       0xa6, 0xf1, 0x41, 0x35, 0x63, 0x59, 0x68, 0x27, 0xe6, 0xf6, 0x39, 0xca,
+       0x90, 0x8d, 0xaa, 0x2a, 0x42, 0xe9, 0x5b, 0xed, 0x9b, 0x49, 0x71, 0xdf,
+       0xfc, 0xe3, 0xce, 0xb2, 0x08, 0x58, 0xd7, 0x7c, 0x97, 0xee, 0xbe, 0xa0,
+       0x7f, 0xb5, 0x8e, 0xfe, 0xe0, 0x07, 0xff, 0x01, 0xe5, 0x64, 0xd5, 0xe6,
+       0xde, 0x4e, 0x1b, 0xf2, 0xad, 0xca, 0xed, 0x69, 0x8b, 0x69, 0x75, 0x16,
+       0xf7, 0x7b, 0x56, 0xa7, 0xa1, 0xff, 0xaf, 0xc9, 0x11, 0xfd, 0x00, 0x4f,
+       0x2d, 0xbf, 0xcf, 0x78, 0x79, 0x5d, 0x90, 0x1d, 0x57, 0x63, 0xf8, 0x3a,
+       0x9f, 0x75, 0x28, 0x74, 0xdf, 0xd3, 0x67, 0xf2, 0xde, 0x02, 0x97, 0xfe,
+       0x37, 0xe3, 0xcf, 0xb5, 0x08, 0x7b, 0xf3, 0xad, 0x90, 0xe3, 0xdc, 0xc7,
+       0xde, 0x58, 0x8c, 0xfc, 0x9b, 0xb7, 0xdc, 0xb9, 0x0f, 0xf1, 0xbf, 0x28,
+       0x4e, 0xa6, 0xeb, 0xff, 0xc9, 0x7c, 0x96, 0x34, 0xa4, 0x8f, 0x43, 0x21,
+       0xff, 0xab, 0xc5, 0xa8, 0x96, 0x7c, 0x2e, 0x05, 0xc6, 0x31, 0xc5, 0x95,
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+       0xa7, 0x37, 0x33, 0x1e, 0x3b, 0x84, 0x26, 0xe7, 0xcd, 0xe4, 0xe5, 0x3b,
+       0x5f, 0x51, 0x03, 0x7e, 0x8e, 0xa6, 0xd7, 0xf6, 0x89, 0x69, 0xb5, 0xf7,
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+       0x8f, 0xc5, 0xfb, 0x14, 0xee, 0xd7, 0x7d, 0x3d, 0x4a, 0x05, 0xbe, 0xa9,
+       0x6c, 0x7f, 0xf7, 0x38, 0xc2, 0x5b, 0x69, 0xb1, 0xf9, 0x30, 0xdf, 0xc2,
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+       0xa3, 0x52, 0xac, 0x63, 0x36, 0xeb, 0x25, 0xb8, 0xd8, 0xb7, 0xd7, 0xae,
+       0x4d, 0x03, 0xfa, 0xcc, 0x12, 0xf8, 0xa8, 0xec, 0x86, 0xb8, 0x30, 0x07,
+       0xef, 0x33, 0x76, 0x17, 0xe0, 0xe1, 0x2e, 0x85, 0xc7, 0x8b, 0x77, 0x39,
+       0x20, 0x3e, 0x0c, 0xe2, 0xa3, 0xd9, 0x93, 0x43, 0xfb, 0xf8, 0x9b, 0x9e,
+       0x10, 0x98, 0xe7, 0x7a, 0xe3, 0xf5, 0xfa, 0x7f, 0xaa, 0xc8, 0x17, 0xfc,
+       0xb3, 0x71, 0xa6, 0xd6, 0x76, 0x83, 0x1d, 0x3a, 0x0d, 0x0c, 0x70, 0xb0,
+       0x9e, 0xc7, 0x34, 0x85, 0xa3, 0x65, 0x8f, 0x82, 0xf1, 0x80, 0x3b, 0xd3,
+       0x80, 0xfc, 0x58, 0x27, 0xec, 0x1a, 0x84, 0xc9, 0x43, 0xdb, 0x23, 0x21,
+       0xaf, 0x85, 0x86, 0xbe, 0x1c, 0x07, 0xe0, 0xb7, 0x6b, 0xcf, 0x37, 0x64,
+       0xff, 0xf6, 0xee, 0xf9, 0xe6, 0x23, 0xf4, 0xe7, 0xa6, 0x7c, 0xa1, 0x30,
+       0x33, 0x3c, 0x5f, 0xf8, 0x45, 0x7e, 0x14, 0xea, 0x07, 0xe6, 0x0a, 0x9d,
+       0xb7, 0xee, 0x8f, 0xad, 0x56, 0xc6, 0xaf, 0x13, 0xff, 0xd4, 0x8a, 0xb5,
+       0xef, 0xaf, 0xc7, 0x8c, 0x18, 0xc2, 0x67, 0xa1, 0xf6, 0x37, 0xe7, 0x9f,
+       0x5f, 0x8f, 0xf3, 0x7d, 0x79, 0x46, 0xe1, 0xbc, 0x2d, 0xde, 0x5f, 0x6e,
+       0x72, 0xa7, 0xdb, 0x6d, 0xd8, 0xf2, 0x78, 0x7f, 0xbf, 0xc4, 0xfd, 0x1d,
+       0xed, 0xfe, 0x7e, 0x23, 0xc0, 0x0d, 0xd7, 0x37, 0xc5, 0x68, 0x71, 0x7f,
+       0xaf, 0x42, 0xf9, 0x19, 0xf8, 0x99, 0x83, 0xe8, 0x7c, 0x17, 0xc6, 0xfb,
+       0xb9, 0x01, 0xba, 0xde, 0x75, 0xae, 0xe2, 0x0b, 0x25, 0x67, 0x30, 0x7d,
+       0xf0, 0xf7, 0xff, 0x23, 0xde, 0xd7, 0xe2, 0xfc, 0xb7, 0x44, 0xfc, 0xc0,
+       0xf6, 0x9d, 0x30, 0xa9, 0x00, 0xd7, 0x8c, 0xd6, 0x47, 0x14, 0xf4, 0xa3,
+       0x67, 0x24, 0xc9, 0xcc, 0x19, 0xf4, 0xde, 0x3b, 0x54, 0x2b, 0x73, 0x06,
+       0xc5, 0xfb, 0x6f, 0xc4, 0xe8, 0xfc, 0x90, 0x7d, 0xaf, 0xad, 0x9f, 0x05,
+       0x76, 0xa4, 0xae, 0x47, 0x76, 0x84, 0xa1, 0xbc, 0xb6, 0x6f, 0x3f, 0x94,
+       0x83, 0xfd, 0x5e, 0xd9, 0x61, 0x1d, 0x82, 0x8f, 0xf4, 0xf8, 0x9d, 0xd1,
+       0xfe, 0x88, 0x82, 0xfc, 0x9f, 0x10, 0xcb, 0xe5, 0xe6, 0x7a, 0xef, 0x2f,
+       0x1c, 0x07, 0x7c, 0x72, 0x2b, 0xd2, 0x9d, 0x91, 0x1f, 0x77, 0xb1, 0x40,
+       0x22, 0x39, 0xd2, 0xd3, 0x77, 0xef, 0x9e, 0x9f, 0xc7, 0xf6, 0x65, 0x0f,
+       0x8f, 0xef, 0xe1, 0xe8, 0xaf, 0xa7, 0xc3, 0x6f, 0xce, 0x17, 0x47, 0x21,
+       0x5e, 0xae, 0x47, 0x0f, 0x3d, 0xdf, 0x76, 0xc2, 0x3a, 0x3d, 0xb0, 0x3e,
+       0x1f, 0xac, 0xd3, 0x03, 0xfe, 0xd6, 0xde, 0x7a, 0x3b, 0xf5, 0xdf, 0xae,
+       0x4f, 0xa2, 0xbe, 0xc6, 0xaf, 0x75, 0x1d, 0xbf, 0x8c, 0x45, 0x7f, 0x4d,
+       0xe3, 0xd3, 0xb2, 0x58, 0xce, 0x37, 0x53, 0x76, 0xaf, 0x8f, 0x65, 0xb6,
+       0x00, 0xbd, 0x34, 0x7c, 0x5d, 0x14, 0x74, 0xab, 0x66, 0x8e, 0xf9, 0xb3,
+       0xe0, 0xcf, 0x5d, 0x92, 0x23, 0x82, 0xf4, 0x84, 0x87, 0xf5, 0x26, 0x15,
+       0x04, 0xec, 0x55, 0xf5, 0xb1, 0x72, 0xf2, 0x33, 0x34, 0x7b, 0x55, 0x2d,
+       0x67, 0x1b, 0x51, 0xff, 0x6a, 0xf6, 0x0a, 0xd3, 0xc2, 0xa8, 0xcf, 0xf4,
+       0xf6, 0x69, 0x7e, 0x7a, 0x91, 0x11, 0xd5, 0xaa, 0xde, 0x2e, 0xc1, 0x02,
+       0x8d, 0xc8, 0xbf, 0xd5, 0x0b, 0x43, 0xaf, 0x57, 0xf4, 0x34, 0x2b, 0x11,
+       0xd4, 0x33, 0x10, 0x9d, 0x24, 0x49, 0xe0, 0x43, 0xf8, 0xd5, 0x1a, 0x3c,
+       0x1f, 0x32, 0x17, 0xc1, 0xab, 0xa7, 0xa7, 0x06, 0x9f, 0x1e, 0x2e, 0xcd,
+       0x9f, 0xae, 0x16, 0x74, 0x83, 0x75, 0x96, 0xe1, 0xd2, 0xe7, 0xaa, 0x45,
+       0xb4, 0x8e, 0x41, 0x76, 0x55, 0xac, 0xf7, 0x46, 0xed, 0xa9, 0x39, 0x36,
+       0x34, 0xce, 0xba, 0x72, 0xae, 0xf4, 0xfd, 0x9c, 0x21, 0xf8, 0x75, 0x38,
+       0xbe, 0xd5, 0xdf, 0xd7, 0xf4, 0x40, 0x39, 0xbe, 0x20, 0x97, 0x5a, 0x0f,
+       0xfa, 0x11, 0x09, 0xb1, 0x09, 0x44, 0xaf, 0xf2, 0xab, 0x26, 0xe6, 0x04,
+       0x7b, 0xc1, 0x46, 0x86, 0xb1, 0xcf, 0x82, 0xf3, 0xef, 0xaf, 0x64, 0x92,
+       0xbd, 0x7b, 0x54, 0xd8, 0xdf, 0xe1, 0xf8, 0xa6, 0xf6, 0xaa, 0x81, 0xb9,
+       0x63, 0x03, 0xfc, 0x63, 0x6c, 0x7b, 0xce, 0x8a, 0xfc, 0xb3, 0x5b, 0x69,
+       0xb6, 0x62, 0xde, 0xf1, 0x36, 0xdb, 0x9c, 0xc6, 0x28, 0xc0, 0x53, 0xe9,
+       0x1f, 0x8b, 0xe7, 0xa1, 0x5f, 0x57, 0xd7, 0x67, 0x60, 0x98, 0x9a, 0x2a,
+       0x6b, 0xbf, 0xb4, 0x0f, 0xe3, 0xf6, 0xba, 0xe3, 0xcc, 0x81, 0xfa, 0xb0,
+       0xb8, 0xbd, 0xab, 0x04, 0xf9, 0xed, 0x6d, 0xa5, 0x57, 0xa6, 0x38, 0xfa,
+       0x4b, 0xc6, 0x9e, 0x0b, 0xf2, 0x0f, 0xdb, 0xda, 0x1b, 0xad, 0xe8, 0x3f,
+       0xb5, 0xc5, 0xc9, 0x14, 0xa7, 0xef, 0x8f, 0xe6, 0xfc, 0xa8, 0xdd, 0x6f,
+       0x89, 0xe5, 0xfc, 0xd7, 0x76, 0xe6, 0xf2, 0x2c, 0xe7, 0x10, 0xf7, 0x3f,
+       0x13, 0xf7, 0x4b, 0x4f, 0xe5, 0x1a, 0xd1, 0x48, 0xf6, 0xc7, 0x47, 0x50,
+       0xbe, 0xa1, 0xfc, 0x69, 0x03, 0xad, 0xbf, 0x54, 0xb2, 0x57, 0x55, 0xa2,
+       0xff, 0x71, 0x87, 0x91, 0xfc, 0x7a, 0x88, 0x5b, 0xfe, 0xf0, 0x7d, 0xcc,
+       0x37, 0xb5, 0x99, 0xb7, 0x63, 0xaa, 0xbe, 0xac, 0xed, 0x87, 0x8f, 0xd8,
+       0x81, 0x10, 0x2d, 0xff, 0xe7, 0xb3, 0x06, 0x33, 0xe6, 0x0f, 0xe6, 0x48,
+       0x8e, 0x97, 0x61, 0x5c, 0xb9, 0xea, 0xef, 0xc2, 0x7e, 0xf9, 0xbc, 0x54,
+       0xda, 0x87, 0x99, 0xf4, 0x7f, 0x65, 0xf2, 0x5f, 0xfd, 0x77, 0x4b, 0x94,
+       0xf7, 0x28, 0x07, 0x76, 0xc1, 0x7e, 0xf9, 0x3d, 0xa9, 0x5e, 0xcc, 0x3f,
+       0xec, 0x91, 0x78, 0xdf, 0xd3, 0xc1, 0xf3, 0xfe, 0xcc, 0xee, 0x89, 0x9d,
+       0x05, 0xef, 0xf9, 0xa0, 0x32, 0x76, 0xc2, 0x3a, 0xe2, 0x29, 0xad, 0x7f,
+       0x4b, 0xee, 0x3a, 0x26, 0x18, 0x38, 0x28, 0x9e, 0x7a, 0x6c, 0x17, 0xdf,
+       0x3f, 0x7a, 0xac, 0x4c, 0xa2, 0xfd, 0xa3, 0x32, 0x7b, 0x0a, 0xf3, 0x04,
+       0xf1, 0x55, 0xf9, 0xd3, 0x40, 0xcf, 0x3c, 0xe0, 0xc7, 0xf6, 0xc4, 0x62,
+       0xe4, 0xdf, 0xaa, 0x0a, 0x99, 0x79, 0x83, 0xf8, 0x7a, 0xbe, 0xcb, 0xca,
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+       0x72, 0x13, 0xd8, 0x3b, 0xb3, 0x7b, 0xbc, 0x34, 0x81, 0xb1, 0x13, 0xf1,
+       0x9f, 0xcf, 0x54, 0xa0, 0x7f, 0x68, 0xc6, 0xa8, 0x7f, 0xff, 0x0b, 0xdc,
+       0xff, 0xdd, 0x4f, 0x2e, 0xac, 0xb3, 0x00, 0x5c, 0xf3, 0x8e, 0xda, 0x5a,
+       0x7b, 0xa0, 0xff, 0xe9, 0x4f, 0x2e, 0xae, 0xb3, 0xa1, 0x9e, 0x3d, 0x14,
+       0x0e, 0xca, 0x0e, 0xf5, 0x46, 0xff, 0x41, 0x90, 0x74, 0x96, 0x87, 0x36,
+       0x3d, 0x99, 0x71, 0x05, 0x3b, 0x19, 0xfa, 0xb1, 0xa2, 0xef, 0xe9, 0x9f,
+       0x59, 0x0a, 0x24, 0x5f, 0x50, 0xd2, 0x97, 0xc5, 0x80, 0xb5, 0xa6, 0xfc,
+       0xc4, 0x3f, 0xd3, 0x02, 0x78, 0x5c, 0x60, 0x75, 0xff, 0x1b, 0xf6, 0x4d,
+       0x9e, 0x97, 0x66, 0x96, 0xde, 0x84, 0x7d, 0xe6, 0xc1, 0x7a, 0x2e, 0xbf,
+       0x64, 0xa4, 0xf8, 0x9e, 0x8d, 0x94, 0xe2, 0xb0, 0x7e, 0x65, 0x99, 0xdd,
+       0x7d, 0x2c, 0x3e, 0xc8, 0x7e, 0x3b, 0xa5, 0x3f, 0xd2, 0xfe, 0x51, 0x81,
+       0x53, 0x62, 0xd1, 0x71, 0x44, 0x57, 0xda, 0xcf, 0x62, 0xf6, 0x53, 0xb1,
+       0xc1, 0xf2, 0xb6, 0xcc, 0x5e, 0x76, 0x0c, 0xe9, 0x71, 0x47, 0x3c, 0xdf,
+       0xbf, 0x9a, 0x38, 0x4d, 0x72, 0x06, 0xd7, 0x49, 0xe8, 0xc7, 0x4d, 0x3c,
+       0xa3, 0x96, 0x22, 0x9d, 0x0a, 0xce, 0x95, 0x37, 0x61, 0x3b, 0xbb, 0x22,
+       0x9a, 0xfa, 0xae, 0x85, 0x93, 0x9a, 0x50, 0x9e, 0x4b, 0x6d, 0xc3, 0x3d,
+       0x5f, 0x42, 0xcf, 0x2f, 0x88, 0x37, 0x12, 0x7f, 0x16, 0x2b, 0x52, 0x48,
+       0x7d, 0x88, 0x7e, 0x5c, 0x1e, 0x30, 0x13, 0xfa, 0xc7, 0xfe, 0x03, 0xe1,
+       0x94, 0x17, 0x98, 0x78, 0xcc, 0xdd, 0x88, 0x75, 0xa3, 0x65, 0x49, 0xa9,
+       0xb9, 0xb2, 0xd0, 0x79, 0x8c, 0xfa, 0xd1, 0x1b, 0x71, 0x1f, 0x6d, 0x62,
+       0xe5, 0x87, 0xa5, 0xb1, 0x28, 0x3f, 0x36, 0xc9, 0x81, 0xe6, 0xa1, 0x80,
+       0xf5, 0x35, 0xc5, 0xc6, 0x61, 0xfd, 0x23, 0x16, 0x44, 0xe1, 0xba, 0x9e,
+       0x2b, 0xc1, 0xfa, 0x9d, 0x89, 0xaa, 0xe4, 0x40, 0xb4, 0x15, 0x39, 0xbb,
+       0x5a, 0xf1, 0xf9, 0x22, 0x47, 0x84, 0xa3, 0x08, 0xfd, 0xf1, 0x63, 0x6a,
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+       0xec, 0xb0, 0xc0, 0x44, 0x47, 0x7d, 0x77, 0x4c, 0xbd, 0x00, 0xfd, 0xa2,
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+       0xee, 0xc7, 0x9f, 0xaa, 0x8a, 0x0e, 0xee, 0x6f, 0xfa, 0xac, 0x0a, 0xef,
+       0x4f, 0x57, 0xd4, 0x46, 0x1b, 0xf0, 0xe3, 0x41, 0x26, 0x39, 0x3c, 0xc8,
+       0x9f, 0x3d, 0xaa, 0x82, 0xfb, 0xcf, 0x25, 0xc7, 0x9c, 0x4d, 0xd8, 0x96,
+       0x9d, 0x74, 0x63, 0x99, 0x29, 0x9b, 0x71, 0xc6, 0xd3, 0x84, 0xed, 0xd4,
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+       0xe2, 0xf9, 0xf3, 0x5a, 0x7b, 0x5a, 0x71, 0x7f, 0x83, 0x7a, 0x11, 0xeb,
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+       0x63, 0xce, 0xee, 0x1f, 0x35, 0x77, 0x3c, 0xef, 0x23, 0x7d, 0x65, 0x39,
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+       0xf1, 0xb7, 0xd0, 0x3b, 0xba, 0xb1, 0x4f, 0xc5, 0xfa, 0x0d, 0xef, 0x4d,
+       0x58, 0x2f, 0x91, 0x91, 0xe8, 0xae, 0x45, 0x3c, 0x2c, 0x32, 0x7b, 0x6f,
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+       0x7b, 0x21, 0x80, 0x04, 0xfa, 0x54, 0x4f, 0xe1, 0xf4, 0xd1, 0xde, 0x0b,
+       0x38, 0xb5, 0xa0, 0x3d, 0xf8, 0x58, 0x9c, 0x03, 0xd1, 0xe0, 0x80, 0xf7,
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+       0x26, 0x6e, 0x45, 0xe1, 0x7b, 0xa6, 0x1c, 0x5e, 0x5a, 0x62, 0x83, 0x36,
+       0xbf, 0x6d, 0x25, 0x8f, 0x73, 0x7b, 0x95, 0x90, 0x3c, 0xd7, 0xa4, 0xe3,
+       0x8a, 0x7e, 0xbf, 0x83, 0xec, 0xd6, 0x54, 0xed, 0x79, 0x5d, 0x9e, 0x71,
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+       0x66, 0xc9, 0xc1, 0x79, 0x80, 0x35, 0x22, 0x6e, 0xb8, 0xdc, 0x33, 0x3a,
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+       0xe3, 0x8f, 0xd9, 0xef, 0x47, 0xb8, 0xc7, 0x1f, 0x63, 0xf7, 0x91, 0x5d,
+       0xd7, 0xe6, 0x1d, 0xc8, 0x2f, 0x70, 0xbc, 0x5c, 0x3e, 0xce, 0xf1, 0x32,
+       0xa1, 0x2f, 0xe3, 0xa7, 0xd3, 0xa0, 0x6f, 0xec, 0x36, 0x32, 0xaf, 0x1a,
+       0x58, 0x4f, 0x21, 0x07, 0x95, 0x5d, 0xc6, 0xff, 0xe0, 0x78, 0xbb, 0xc9,
+       0x8b, 0x75, 0xcb, 0x05, 0x07, 0x7e, 0x99, 0xe7, 0x83, 0x4b, 0xe6, 0x24,
+       0x03, 0x53, 0x83, 0xf0, 0x10, 0xa6, 0x86, 0x33, 0x35, 0x48, 0x2f, 0x5a,
+       0x33, 0x62, 0x42, 0xfa, 0xb2, 0x86, 0x6f, 0x61, 0xcf, 0xf3, 0xc4, 0xfc,
+       0x11, 0x8e, 0xe4, 0x90, 0x79, 0xf6, 0xc4, 0x94, 0x77, 0xa3, 0x7d, 0xcf,
+       0xb3, 0x2d, 0x27, 0xfb, 0x1e, 0x35, 0x79, 0x74, 0xc8, 0x3c, 0xac, 0x47,
+       0x09, 0xb1, 0xf3, 0xb0, 0x28, 0xda, 0xbf, 0x9c, 0x08, 0x40, 0xfd, 0x0c,
+       0xf0, 0x5a, 0x70, 0x4c, 0x09, 0xb1, 0xe7, 0x93, 0xe2, 0x3c, 0xb8, 0x62,
+       0x36, 0xf9, 0xa4, 0xa2, 0xb3, 0xff, 0xcd, 0x32, 0xca, 0x41, 0xe1, 0x99,
+       0xd0, 0xeb, 0x07, 0x86, 0xa3, 0xcb, 0x70, 0xf8, 0x63, 0x39, 0x3f, 0x45,
+       0xff, 0xee, 0x1f, 0xc5, 0x5f, 0xb4, 0x33, 0x14, 0x7f, 0xb1, 0x15, 0xa1,
+       0xf8, 0x8b, 0x77, 0x85, 0xe2, 0x2f, 0x71, 0x61, 0x28, 0x9e, 0x46, 0xb8,
+       0x43, 0xf1, 0x92, 0xb2, 0x7c, 0x5c, 0xc8, 0xfd, 0x9b, 0x56, 0xe7, 0x86,
+       0xf4, 0x6f, 0x7e, 0xbc, 0x30, 0x64, 0x7c, 0x2a, 0x18, 0xa4, 0xe0, 0x7e,
+       0xda, 0xd3, 0x33, 0x43, 0xc6, 0xdf, 0xd2, 0x3c, 0x37, 0xa4, 0x3f, 0x76,
+       0xc3, 0xa2, 0x90, 0xf1, 0x99, 0xde, 0xa5, 0x21, 0xf7, 0xb3, 0x5e, 0x5d,
+       0x71, 0x43, 0xf4, 0x1e, 0xdf, 0xb2, 0x26, 0x64, 0x9c, 0x9e, 0xde, 0xb7,
+       0xb6, 0xfd, 0xaf, 0x90, 0x79, 0x35, 0x7a, 0x7b, 0xe0, 0xdf, 0xbf, 0x82,
+       0xde, 0xe6, 0xc4, 0x50, 0x7a, 0xa7, 0x0a, 0xfd, 0x1a, 0xed, 0xe4, 0xf5,
+       0x65, 0xfd, 0x46, 0xdb, 0xd3, 0x12, 0xe8, 0x23, 0x4c, 0x13, 0xa1, 0x5e,
+       0x8b, 0x6e, 0x7f, 0xf7, 0x6b, 0xcc, 0x43, 0x78, 0x8a, 0x55, 0xaa, 0x9f,
+       0xf3, 0xcc, 0x64, 0xb4, 0x0f, 0xfd, 0x82, 0xec, 0x92, 0x50, 0x0f, 0xa5,
+       0xc0, 0x14, 0x86, 0x34, 0xaa, 0x5f, 0xa7, 0xfa, 0xbb, 0x1f, 0x1b, 0x0c,
+       0x21, 0xfb, 0xe2, 0x89, 0x89, 0xdc, 0xbe, 0x27, 0x26, 0xf2, 0x7c, 0xcd,
+       0xcf, 0x4d, 0xfc, 0xdc, 0x52, 0x0a, 0xf8, 0x8f, 0x64, 0x87, 0x0c, 0x2c,
+       0x10, 0x2f, 0x03, 0x1e, 0x22, 0x31, 0x5e, 0xa6, 0x78, 0xfa, 0xc7, 0xcf,
+       0x60, 0xbc, 0xdc, 0x14, 0xdd, 0x97, 0xa1, 0x42, 0x7c, 0x6c, 0xc6, 0xfe,
+       0x4d, 0x01, 0x7d, 0xb9, 0xc8, 0xac, 0x36, 0xf6, 0x01, 0x3e, 0x26, 0xc8,
+       0x5c, 0x1f, 0x82, 0x9e, 0x4c, 0x4b, 0x84, 0xf9, 0x3f, 0x91, 0x9e, 0x30,
+       0x72, 0x3f, 0xc2, 0x63, 0x44, 0x3f, 0x22, 0xc5, 0xc2, 0x3c, 0x91, 0xb9,
+       0x64, 0x3f, 0x28, 0x7f, 0x1c, 0xcd, 0xe2, 0x24, 0xac, 0xc7, 0x8f, 0x0a,
+       0xe8, 0x69, 0xf5, 0x1a, 0x10, 0x6b, 0xdf, 0x8a, 0x2c, 0x3a, 0x07, 0xf5,
+       0x1e, 0x42, 0x82, 0xfe, 0xaf, 0x25, 0x86, 0xec, 0xe8, 0xdd, 0x9a, 0x7e,
+       0x5a, 0x9e, 0x49, 0xfa, 0xe9, 0xb2, 0x2d, 0xd4, 0x0f, 0xbb, 0xfc, 0x40,
+       0x1a, 0x5d, 0x3f, 0x71, 0xaf, 0x99, 0xf6, 0xfb, 0x4f, 0x88, 0x3a, 0x44,
+       0x6d, 0xfd, 0xe7, 0x84, 0xde, 0xfa, 0x53, 0xbd, 0x85, 0xda, 0xf3, 0xf5,
+       0xf6, 0x10, 0x3d, 0xb6, 0x7c, 0xe3, 0xfa, 0x08, 0xf4, 0x1f, 0x4f, 0x64,
+       0x70, 0x7f, 0x51, 0xbb, 0x5e, 0x82, 0x78, 0x9b, 0x88, 0xad, 0x2c, 0xec,
+       0x9a, 0xc5, 0x8e, 0xf9, 0xac, 0x7b, 0xc0, 0x38, 0x47, 0x01, 0xbe, 0x57,
+       0x75, 0xf7, 0x45, 0x2e, 0x62, 0xe4, 0x37, 0x16, 0xe3, 0xba, 0x6b, 0x37,
+       0x5e, 0xb9, 0xf7, 0x4d, 0xe8, 0xd7, 0x19, 0xfc, 0x09, 0xdc, 0x3e, 0x78,
+       0x78, 0xbd, 0xcc, 0xc7, 0x8c, 0xfc, 0xcf, 0xea, 0x6f, 0x58, 0x88, 0xff,
+       0x34, 0x37, 0x91, 0xc7, 0xe9, 0x73, 0xc5, 0xfc, 0x0b, 0xa0, 0xb1, 0x03,
+       0x9e, 0x16, 0x00, 0xfe, 0xa3, 0xb1, 0x7d, 0x77, 0x5a, 0x39, 0xf2, 0x27,
+       0x5c, 0xa7, 0xf3, 0x69, 0xb3, 0xbb, 0x19, 0xd5, 0x9f, 0xcc, 0x71, 0xa7,
+       0xd2, 0x3e, 0xe3, 0x51, 0xe6, 0xf8, 0x70, 0x17, 0x80, 0xf8, 0x9d, 0x44,
+       0x95, 0xe0, 0x9c, 0xc7, 0x5c, 0xb4, 0x5f, 0xff, 0xd1, 0xbd, 0xab, 0x22,
+       0x70, 0xdc, 0xc0, 0x7c, 0xda, 0x3c, 0xc0, 0x28, 0xe8, 0x6f, 0x7c, 0x1c,
+       0xed, 0x31, 0x26, 0x60, 0xdc, 0x7f, 0x1b, 0xaf, 0x6f, 0x80, 0xf7, 0x59,
+       0xf0, 0xba, 0xeb, 0x9e, 0x94, 0x27, 0xd1, 0x0e, 0x69, 0xef, 0xfb, 0x88,
+       0xb9, 0x2f, 0x7c, 0x88, 0xfb, 0xdd, 0xcc, 0x41, 0xf3, 0x6a, 0xf3, 0x33,
+       0x16, 0x13, 0xa2, 0x9f, 0x76, 0x2c, 0x5f, 0xf9, 0x69, 0x2c, 0xbc, 0x6f,
+       0xcd, 0x01, 0x03, 0xe5, 0x13, 0xd6, 0x74, 0x98, 0x29, 0xee, 0xea, 0x5f,
+       0xf1, 0xd7, 0xad, 0x2f, 0xc2, 0xfd, 0xfb, 0x52, 0xfa, 0x6e, 0x42, 0xbb,
+       0xfc, 0xc9, 0x8a, 0x6f, 0xc6, 0x20, 0x3f, 0xdc, 0xbd, 0x01, 0xf4, 0x10,
+       0xac, 0xb1, 0x30, 0xca, 0xfd, 0x70, 0x62, 0x50, 0x9c, 0x72, 0xe2, 0x81,
+       0x2b, 0x11, 0x78, 0x1f, 0xec, 0xeb, 0xa6, 0x17, 0xd1, 0x38, 0x6e, 0x36,
+       0x53, 0x7d, 0xef, 0x27, 0x2b, 0x36, 0x8f, 0x09, 0xf6, 0x47, 0x1f, 0x4d,
+       0x2c, 0xaa, 0xc5, 0xe7, 0xd8, 0xe4, 0x1b, 0x3b, 0x6f, 0x58, 0xf2, 0x7a,
+       0x66, 0x22, 0xd5, 0x63, 0x09, 0x7e, 0x7a, 0x58, 0xf0, 0xd3, 0x9a, 0xd7,
+       0xc6, 0x92, 0x1f, 0xb5, 0x26, 0x62, 0x80, 0x9f, 0x78, 0x7f, 0x13, 0xaf,
+       0xef, 0xd0, 0xd6, 0xf1, 0xa1, 0xe0, 0xc7, 0x15, 0xaf, 0x7f, 0x5d, 0x10,
+       0x7c, 0xce, 0x74, 0x07, 0xf0, 0x91, 0x3a, 0x86, 0xef, 0x6b, 0xa9, 0x20,
+       0x53, 0x3b, 0x7b, 0x2e, 0xe7, 0xe0, 0xfd, 0x57, 0x14, 0x77, 0x13, 0xc2,
+       0xd7, 0x79, 0xf5, 0x74, 0x24, 0xf6, 0x77, 0xbe, 0xf7, 0x37, 0x82, 0x9f,
+       0xcd, 0xbb, 0x31, 0x78, 0x51, 0x06, 0x3d, 0x05, 0x81, 0xfd, 0x65, 0xed,
+       0xdc, 0xe5, 0xc2, 0xf6, 0xd8, 0x3c, 0xa4, 0x3b, 0xc8, 0x59, 0x33, 0xce,
+       0xbf, 0xe8, 0x37, 0xaf, 0x5d, 0xf8, 0x1d, 0xe2, 0xa7, 0x63, 0xf3, 0xa6,
+       0xef, 0xe3, 0x98, 0x1b, 0x3c, 0x7f, 0xc9, 0x84, 0x7d, 0x71, 0x08, 0x3c,
+       0x80, 0x7d, 0xa1, 0xf8, 0xa0, 0x9f, 0x85, 0xf3, 0x73, 0x1d, 0x42, 0x8f,
+       0x2a, 0xb8, 0x83, 0x9e, 0x86, 0xe7, 0x99, 0x1c, 0x2a, 0xf1, 0xb3, 0x93,
+       0x1d, 0xc2, 0x7d, 0x97, 0xc6, 0x2e, 0x03, 0xc3, 0xba, 0x95, 0x48, 0xdc,
+       0xb4, 0x09, 0xca, 0xb3, 0x45, 0xca, 0x06, 0xcd, 0x08, 0x39, 0x2d, 0x49,
+       0xa0, 0x9f, 0x85, 0x5e, 0x79, 0x25, 0xf1, 0xe4, 0x9d, 0x4d, 0xe4, 0xe7,
+       0x87, 0xfa, 0x3d, 0xf9, 0x6f, 0xaf, 0x08, 0xf1, 0x77, 0x5c, 0xf0, 0x8f,
+       0xfc, 0x9d, 0x97, 0xdc, 0x8d, 0x98, 0x07, 0xba, 0xae, 0xdf, 0xe3, 0x33,
+       0x2c, 0x31, 0x45, 0xdd, 0xb8, 0xff, 0x03, 0x81, 0xb0, 0x53, 0x2a, 0x10,
+       0x5b, 0x38, 0xf0, 0x6b, 0x4b, 0x14, 0xfb, 0x22, 0x42, 0x0f, 0x77, 0xa2,
+       0x1c, 0x61, 0xfd, 0x3f, 0xce, 0x85, 0xf9, 0x7a, 0x5f, 0x38, 0x3f, 0x67,
+       0x0c, 0xa6, 0x02, 0xf5, 0xf8, 0x0f, 0x60, 0x4d, 0xf8, 0xb0, 0x29, 0x45,
+       0xb4, 0xd2, 0xc5, 0x0c, 0x0b, 0xe8, 0xc5, 0xbd, 0x89, 0x7f, 0x78, 0xe6,
+       0x69, 0xd0, 0x93, 0x96, 0x74, 0xbe, 0x5e, 0xec, 0x37, 0xe2, 0xdf, 0xdd,
+       0x9c, 0xdf, 0x06, 0xfc, 0xab, 0xb7, 0xc7, 0x91, 0x9e, 0x62, 0xdf, 0xc2,
+       0xdb, 0x10, 0x0f, 0x22, 0x5f, 0xa1, 0xa7, 0x53, 0x3e, 0xc8, 0x07, 0x8b,
+       0x0d, 0x92, 0x33, 0xf1, 0xbc, 0x6f, 0xff, 0xdf, 0x22, 0x31, 0x4f, 0xbb,
+       0x35, 0x46, 0x7d, 0x1f, 0xe9, 0xe0, 0x3f, 0x20, 0xd3, 0x3e, 0x4d, 0x98,
+       0xd2, 0x67, 0x8a, 0x1e, 0x22, 0x2e, 0x7b, 0x13, 0xf5, 0x9e, 0x89, 0xfb,
+       0x4d, 0x54, 0x6f, 0xde, 0xc6, 0xf3, 0x81, 0x16, 0xd5, 0xc9, 0x30, 0x0e,
+       0x08, 0xb3, 0xdb, 0x27, 0x04, 0x9f, 0xb3, 0x6b, 0x17, 0xfa, 0x6e, 0xd5,
+       0xfe, 0x4f, 0x46, 0x99, 0x80, 0x0e, 0x17, 0x0c, 0x3d, 0x91, 0xd9, 0x30,
+       0x7f, 0xcd, 0xae, 0x1d, 0x91, 0xe8, 0xc6, 0xdf, 0x6b, 0x74, 0x7f, 0x8a,
+       0x7c, 0xb7, 0xf2, 0xc4, 0x07, 0x05, 0x76, 0x3a, 0xcf, 0xb6, 0x71, 0x14,
+       0x9d, 0x03, 0xf0, 0x8d, 0xa6, 0xba, 0x83, 0xf1, 0x0a, 0xf3, 0x28, 0xb9,
+       0x83, 0xe1, 0xa8, 0xdb, 0x90, 0x4b, 0xc6, 0xb8, 0x76, 0x03, 0x25, 0xe3,
+       0xd9, 0xf8, 0xf6, 0xbc, 0x87, 0x50, 0x1f, 0xd5, 0xf9, 0xf8, 0x3a, 0x71,
+       0x6e, 0x2c, 0xfc, 0xcb, 0x6c, 0x63, 0xd4, 0xbf, 0xd8, 0xd6, 0x18, 0x83,
+       0xf3, 0xd5, 0xfd, 0xb6, 0x23, 0x19, 0xe5, 0x67, 0x73, 0x3c, 0x8f, 0x13,
+       0x5f, 0xbf, 0x3a, 0x8e, 0x3f, 0xaf, 0x30, 0x05, 0xc7, 0x7f, 0x99, 0x18,
+       0x2d, 0xf8, 0xd9, 0x6b, 0xc0, 0x38, 0x63, 0xb3, 0x88, 0x4f, 0x2e, 0x5e,
+       0x35, 0xd0, 0x38, 0xed, 0xfd, 0xe3, 0xdb, 0x8a, 0x64, 0x3b, 0xf0, 0x43,
+       0xb6, 0xaf, 0x79, 0x2f, 0xc5, 0x43, 0xed, 0x66, 0x15, 0xe9, 0x1a, 0xf6,
+       0x0a, 0xe3, 0x78, 0x68, 0x0f, 0x23, 0x39, 0xaf, 0xeb, 0x9c, 0xc1, 0x30,
+       0x9f, 0xdf, 0x1f, 0xcd, 0x1c, 0x12, 0xdc, 0xdf, 0x1a, 0xee, 0xff, 0x03,
+       0x9d, 0x33, 0xeb, 0x30, 0xab, 0x98, 0x1f, 0x0d, 0xb3, 0x37, 0xb3, 0x18,
+       0x98, 0x7f, 0xab, 0xd8, 0x0f, 0xcd, 0x04, 0x8e, 0xc2, 0xf3, 0x4a, 0xda,
+       0x75, 0xed, 0x7d, 0x61, 0xed, 0x3f, 0xc5, 0x58, 0x02, 0xf9, 0x81, 0xf2,
+       0xb4, 0x61, 0x4a, 0x33, 0xbb, 0xcd, 0x16, 0x8c, 0xe7, 0x08, 0xc2, 0x73,
+       0x3c, 0xf2, 0x53, 0x3c, 0xbe, 0xc7, 0x67, 0xc0, 0xfc, 0x88, 0xff, 0x16,
+       0xc6, 0x5e, 0x26, 0xb8, 0x02, 0x70, 0x32, 0x7a, 0xaf, 0x06, 0x67, 0x26,
+       0xf9, 0x73, 0x5b, 0x4d, 0xfe, 0xb3, 0x78, 0x7e, 0x05, 0xe0, 0xb2, 0x23,
+       0xfd, 0x33, 0x19, 0x87, 0x93, 0xb5, 0x8f, 0x55, 0x31, 0xbe, 0x0f, 0xb3,
+       0x3b, 0x69, 0x1d, 0x61, 0x76, 0xd5, 0xe1, 0x91, 0x06, 0xc3, 0x55, 0x97,
+       0xc3, 0xbc, 0x68, 0xbf, 0x7f, 0xbc, 0x96, 0x0d, 0xc8, 0x2b, 0xca, 0x6f,
+       0x5d, 0x78, 0xa0, 0x6f, 0x01, 0x19, 0xd8, 0x3a, 0x9a, 0x09, 0xf9, 0xb6,
+       0x3f, 0x5b, 0x3a, 0x2d, 0xb8, 0x0f, 0x8a, 0x64, 0x72, 0xe0, 0xf9, 0x71,
+       0x1b, 0x62, 0x9e, 0x6d, 0x1a, 0x49, 0x71, 0x83, 0x47, 0xc6, 0x38, 0x16,
+       0xda, 0x88, 0x18, 0x5c, 0xa7, 0xca, 0xcf, 0x3b, 0x63, 0x6a, 0x28, 0x97,
+       0xe3, 0x01, 0xf7, 0xc5, 0xad, 0x16, 0x7e, 0x7f, 0x60, 0x3c, 0xf0, 0xb7,
+       0x0d, 0xfb, 0x36, 0x3e, 0xce, 0x11, 0x65, 0xb7, 0xce, 0x94, 0x48, 0x4e,
+       0x28, 0xaf, 0x57, 0x2b, 0xe4, 0xfd, 0x31, 0xc9, 0x77, 0xf6, 0x76, 0x90,
+       0xd3, 0xbf, 0xf8, 0xf6, 0xe6, 0xa8, 0x00, 0x4b, 0xcd, 0xbb, 0x7b, 0x88,
+       0x4f, 0x57, 0x1a, 0xda, 0x5f, 0x1c, 0x0f, 0xf7, 0x37, 0x5a, 0xdc, 0xf9,
+       0x49, 0x80, 0xcf, 0xb7, 0x4e, 0x1a, 0xe8, 0x1c, 0xe9, 0x9f, 0x5e, 0x0b,
+       0xf3, 0x56, 0x62, 0xfc, 0xb8, 0x7b, 0x63, 0x82, 0x73, 0x08, 0xf9, 0xd0,
+       0xcf, 0xff, 0xc3, 0xe3, 0x6b, 0x9f, 0x4f, 0x41, 0xfa, 0xef, 0x96, 0x54,
+       0xcc, 0x9b, 0xf6, 0x1b, 0xfd, 0xa3, 0x10, 0xde, 0xda, 0xf6, 0xcf, 0x4d,
+       0x54, 0x8f, 0xd0, 0x76, 0x8a, 0xea, 0x93, 0x8e, 0x24, 0xb9, 0x9d, 0xf8,
+       0x9e, 0xc9, 0x6d, 0x0d, 0xb4, 0x6f, 0x3c, 0x85, 0x35, 0xd3, 0xbe, 0x71,
+       0x96, 0x38, 0x7f, 0xdd, 0x92, 0xc4, 0xf5, 0xc7, 0xe5, 0x63, 0x63, 0x5e,
+       0x6e, 0x08, 0xc2, 0xff, 0x83, 0x49, 0xdc, 0x0f, 0x63, 0x7e, 0xf7, 0xcd,
+       0x28, 0x37, 0xed, 0x42, 0x3e, 0x3b, 0xd1, 0x2f, 0x81, 0x76, 0x97, 0xf0,
+       0x8f, 0x76, 0x75, 0xdd, 0x9d, 0xa6, 0x06, 0xe5, 0xfd, 0x1a, 0xd8, 0xde,
+       0x14, 0xc4, 0xf7, 0x5a, 0xf6, 0x36, 0xb5, 0xda, 0xf5, 0x7e, 0x2f, 0x3f,
+       0xcf, 0x98, 0xf5, 0x91, 0xe5, 0x3e, 0x67, 0x10, 0xff, 0xb9, 0x93, 0xb8,
+       0x9f, 0xe7, 0x16, 0xef, 0xf3, 0x27, 0xb9, 0x17, 0x24, 0xa1, 0xdc, 0x76,
+       0x9d, 0x36, 0x45, 0xaa, 0x78, 0x5e, 0xa5, 0x65, 0x14, 0xda, 0x91, 0x16,
+       0xf0, 0x9f, 0xec, 0x43, 0xe0, 0x65, 0x40, 0x6e, 0x75, 0x72, 0x54, 0xa7,
+       0xf8, 0x4d, 0x38, 0xbe, 0xee, 0x1c, 0x3f, 0x77, 0x0a, 0x74, 0x6e, 0xc2,
+       0xfa, 0xff, 0xcd, 0x1f, 0xb5, 0x8d, 0x5b, 0x02, 0xd7, 0x77, 0x01, 0xae,
+       0xb1, 0xde, 0xd3, 0x73, 0xc2, 0x4c, 0x75, 0x8f, 0xbb, 0x8c, 0xae, 0x14,
+       0x1c, 0xdf, 0xf0, 0xe1, 0x57, 0x39, 0xa8, 0xb7, 0x2a, 0x10, 0x69, 0xf0,
+       0xbf, 0xaf, 0x3a, 0x56, 0xde, 0x8c, 0x78, 0x03, 0xbe, 0x2f, 0x0e, 0x47,
+       0xf9, 0xda, 0xce, 0x48, 0x8f, 0x69, 0xf2, 0x99, 0x8d, 0xf2, 0x09, 0xcf,
+       0x67, 0x23, 0xdf, 0xe7, 0x63, 0x3f, 0x93, 0xf4, 0xf0, 0x56, 0x53, 0x2f,
+       0x3f, 0xf7, 0xb9, 0x8b, 0x9f, 0xfb, 0x04, 0xbe, 0x27, 0x39, 0x00, 0xbe,
+       0xb7, 0xa3, 0x9f, 0x90, 0x6d, 0x07, 0x39, 0xa0, 0xe7, 0xc7, 0x92, 0x7c,
+       0x6f, 0xed, 0x35, 0xd0, 0xf9, 0x54, 0x0f, 0xe8, 0xf1, 0x5b, 0xa8, 0x5f,
+       0x5c, 0x85, 0xfd, 0xad, 0xbd, 0xa5, 0x76, 0x92, 0x6f, 0xcc, 0xc3, 0xe7,
+       0xa2, 0x9c, 0xfa, 0xf6, 0xd2, 0x3c, 0x2d, 0x10, 0x83, 0x20, 0xe9, 0x24,
+       0xe6, 0x0a, 0xf6, 0x1f, 0xdb, 0x13, 0x23, 0x89, 0x8f, 0x35, 0xfd, 0x78,
+       0x30, 0x91, 0xeb, 0xff, 0x96, 0x0c, 0x35, 0x0a, 0xeb, 0xff, 0xad, 0xb2,
+       0x1c, 0x22, 0x17, 0x41, 0x76, 0x90, 0xf7, 0x85, 0x9d, 0xec, 0xdd, 0x50,
+       0xfc, 0xec, 0x0b, 0xd3, 0xd0, 0xde, 0x09, 0xbb, 0x20, 0xfc, 0x27, 0x76,
+       0x9c, 0xeb, 0xf9, 0x47, 0x85, 0xad, 0x5a, 0xf3, 0x4e, 0xe1, 0xec, 0x2d,
+       0xb0, 0xce, 0x35, 0x87, 0xe5, 0x81, 0x7a, 0x6e, 0xf4, 0x57, 0x7d, 0x82,
+       0x4f, 0xf6, 0x0a, 0xff, 0x15, 0xed, 0x84, 0x9a, 0xc7, 0xeb, 0x67, 0xf0,
+       0xfa, 0xc4, 0x0d, 0xbc, 0xce, 0xb5, 0xc0, 0xb9, 0xba, 0x04, 0xcb, 0x38,
+       0x26, 0x57, 0x34, 0xef, 0xc3, 0xb6, 0xd0, 0xd5, 0x52, 0x82, 0x67, 0x8e,
+       0xa7, 0x2d, 0xec, 0xdd, 0xc7, 0xcf, 0x1e, 0xf3, 0xf3, 0xe3, 0xad, 0x7b,
+       0xef, 0xc8, 0xc2, 0x7d, 0xea, 0xfe, 0x13, 0x66, 0x86, 0xfb, 0x24, 0xad,
+       0x7f, 0xf3, 0xff, 0xe1, 0x75, 0xc0, 0xc3, 0x77, 0x3b, 0x01, 0xff, 0x43,
+       0xd8, 0x25, 0x58, 0x0e, 0xf1, 0x1f, 0x58, 0xea, 0x14, 0x96, 0x34, 0xf8,
+       0x7e, 0xbf, 0xa4, 0xe9, 0x8f, 0xf9, 0x95, 0x28, 0x6f, 0x17, 0x5b, 0xe5,
+       0x40, 0x1f, 0xec, 0x61, 0x2d, 0x30, 0x38, 0xf6, 0x7f, 0x9d, 0x54, 0xf5,
+       0xac, 0x07, 0x00, 0x4b, 0x1b, 0xe1, 0x7c, 0x1d, 0x59, 0xa2, 0x30, 0xd9,
+       0x4d, 0x6d, 0xff, 0x91, 0xbf, 0x25, 0xa0, 0x2d, 0xd8, 0x75, 0x8c, 0xfb,
+       0x4d, 0xad, 0x26, 0x67, 0x16, 0xf2, 0x4f, 0xeb, 0xe8, 0xd0, 0xf3, 0xfa,
+       0x5a, 0xfb, 0x62, 0x12, 0x3f, 0xe7, 0x9c, 0x6f, 0x66, 0x43, 0xe6, 0x25,
+       0x0f, 0x09, 0xbb, 0x37, 0xc6, 0xc3, 0x9e, 0x41, 0x3e, 0xaa, 0x6d, 0x95,
+       0xed, 0x5e, 0xa0, 0xfb, 0x85, 0x56, 0xd9, 0x69, 0x02, 0xff, 0xe6, 0xac,
+       0xd3, 0x9d, 0x80, 0x67, 0x65, 0xce, 0x31, 0xcf, 0x82, 0xa9, 0x68, 0xe7,
+       0x45, 0xdc, 0xa8, 0x7d, 0x4f, 0x65, 0x19, 0xfa, 0x27, 0x60, 0xa7, 0x1e,
+       0x7c, 0x61, 0x50, 0x1e, 0xdf, 0x80, 0x7c, 0xf4, 0x50, 0xbb, 0xc4, 0x7e,
+       0x06, 0x6b, 0x5e, 0xfe, 0xd2, 0xd0, 0xfb, 0x0a, 0x35, 0x62, 0x9e, 0x87,
+       0xdb, 0x36, 0xee, 0x4f, 0x01, 0x3a, 0xae, 0x78, 0x25, 0x74, 0x5c, 0x8d,
+       0xa8, 0x13, 0xab, 0xd1, 0xf9, 0x2f, 0x87, 0x92, 0x44, 0x7c, 0x98, 0xc6,
+       0xd2, 0xd0, 0x2f, 0x01, 0xfe, 0x21, 0xbd, 0x60, 0x54, 0x58, 0xb7, 0x19,
+       0xf8, 0xf5, 0xc1, 0x64, 0x77, 0x07, 0xc6, 0x1b, 0x9b, 0xc5, 0x77, 0x0c,
+       0x40, 0x7f, 0x92, 0x1c, 0x76, 0x08, 0xbe, 0xdc, 0x2a, 0xea, 0x04, 0xfc,
+       0x5b, 0x25, 0xda, 0xd7, 0xcb, 0x7c, 0xd5, 0x2b, 0x1b, 0xe0, 0xf9, 0x42,
+       0xc5, 0x2b, 0xa3, 0x9d, 0x62, 0xd0, 0xe2, 0x3e, 0xc1, 0x64, 0xa7, 0xbb,
+       0x1c, 0xf1, 0x0b, 0xeb, 0x3e, 0x86, 0xfb, 0x35, 0xcb, 0x85, 0x1e, 0x5c,
+       0xae, 0xf9, 0x65, 0x5e, 0xbe, 0x9f, 0x01, 0xe6, 0x96, 0xfc, 0xb2, 0x29,
+       0xcc, 0xdb, 0x18, 0x89, 0xeb, 0x7e, 0x55, 0x72, 0xf8, 0x54, 0xfc, 0x8e,
+       0xc8, 0xa0, 0x3a, 0x5c, 0x5a, 0x77, 0x9d, 0x58, 0x77, 0xcd, 0x86, 0x23,
+       0xfb, 0x31, 0x8c, 0x5b, 0xd5, 0x12, 0x3a, 0xae, 0x4e, 0xac, 0xbb, 0x4e,
+       0xb7, 0x6e, 0x6d, 0x5f, 0xfb, 0xcf, 0x49, 0xba, 0x73, 0xc8, 0x37, 0xb8,
+       0x6f, 0xf1, 0x67, 0x23, 0xf7, 0x13, 0x3e, 0x10, 0xf3, 0x68, 0xf7, 0xcd,
+       0x23, 0xb8, 0x3e, 0xac, 0x05, 0xf0, 0x90, 0x6e, 0x35, 0x5e, 0xd9, 0xeb,
+       0xe5, 0x7e, 0x9d, 0x0d, 0xbf, 0xc3, 0x73, 0xbf, 0x80, 0xf7, 0x7e, 0x41,
+       0xef, 0x3a, 0xe6, 0x33, 0xa5, 0xc0, 0xb8, 0x55, 0x2f, 0xf0, 0x75, 0xb2,
+       0x67, 0x43, 0xeb, 0x3f, 0x1f, 0x6c, 0x7d, 0xc4, 0x84, 0xf1, 0x95, 0x9e,
+       0x2f, 0x96, 0x6f, 0x31, 0x92, 0x3f, 0x0a, 0x88, 0x33, 0xa1, 0xbf, 0xa8,
+       0xe7, 0x8b, 0x15, 0x62, 0xdd, 0x2b, 0x74, 0xeb, 0xae, 0x75, 0x4b, 0x3a,
+       0xb8, 0xb8, 0x9f, 0x3c, 0x18, 0xae, 0x96, 0x05, 0x48, 0xd7, 0x55, 0x5b,
+       0x8c, 0x0c, 0xeb, 0x11, 0xf5, 0x70, 0x2d, 0x6b, 0x59, 0x52, 0x8e, 0x7c,
+       0x36, 0x98, 0x5f, 0x39, 0x5d, 0x56, 0x88, 0xf9, 0x02, 0x70, 0xae, 0xa6,
+       0x73, 0x7c, 0x37, 0x0a, 0xe7, 0xa8, 0x11, 0x82, 0x2f, 0xc7, 0xb1, 0x71,
+       0x44, 0x97, 0x8a, 0xd8, 0x1b, 0xa2, 0x8b, 0xde, 0x8f, 0xdd, 0xbe, 0x7f,
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+       0xd6, 0x9b, 0x0c, 0xe1, 0x04, 0x7a, 0xd6, 0x19, 0xfd, 0x09, 0x14, 0x37,
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+       0xbe, 0xea, 0xbb, 0x9d, 0x0f, 0x8d, 0xa5, 0x3a, 0x5b, 0xb7, 0xfb, 0x56,
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+       0x57, 0x6c, 0x01, 0xff, 0x45, 0x5b, 0x4f, 0x65, 0x32, 0xaf, 0x77, 0xe9,
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+       0x50, 0x7b, 0xce, 0x9d, 0xac, 0xf0, 0x7d, 0x7e, 0x8d, 0x7f, 0x5a, 0x24,
+       0x27, 0xf1, 0xc7, 0x76, 0xde, 0xd6, 0xb4, 0xed, 0xa4, 0xf5, 0xad, 0x34,
+       0xb6, 0x10, 0xbd, 0x1b, 0xb6, 0x18, 0xf9, 0xfd, 0xad, 0xbc, 0xd5, 0xea,
+       0xaa, 0x3d, 0x2c, 0xc6, 0x83, 0xf8, 0x38, 0x84, 0x97, 0x80, 0x0e, 0x33,
+       0x4d, 0x5e, 0xfa, 0x6e, 0xc5, 0xc1, 0x54, 0xee, 0xbf, 0xeb, 0xe9, 0xf1,
+       0x59, 0x32, 0xcf, 0x63, 0x1c, 0x3c, 0xe1, 0xbe, 0x19, 0xf9, 0xe5, 0x60,
+       0x91, 0x7b, 0xac, 0x7d, 0x08, 0xfb, 0xe0, 0x61, 0xc5, 0x3c, 0x3e, 0x95,
+       0x04, 0xbe, 0x5b, 0xf9, 0x79, 0x25, 0xfd, 0xb8, 0x53, 0xc9, 0x3c, 0x8e,
+       0x8f, 0x8c, 0x0d, 0x3d, 0x3f, 0x3a, 0x60, 0x5f, 0x92, 0x39, 0xff, 0xcc,
+       0x34, 0x0d, 0xfd, 0x3d, 0xbd, 0x9f, 0x69, 0xf2, 0xc4, 0xd8, 0x33, 0x06,
+       0xe0, 0x8b, 0xa3, 0x95, 0x46, 0xfb, 0x3a, 0xe1, 0xb7, 0x8f, 0x08, 0xfa,
+       0x5e, 0x42, 0xd5, 0x5d, 0x46, 0xf2, 0x0f, 0x8e, 0x32, 0xfb, 0x3b, 0x58,
+       0x67, 0x38, 0x4b, 0xd3, 0xaf, 0x93, 0xb9, 0x5d, 0xd5, 0xf2, 0xdd, 0xae,
+       0x0d, 0x2a, 0xdf, 0xd7, 0x19, 0x7c, 0xae, 0x91, 0xf4, 0xe4, 0x7c, 0x6d,
+       0x3e, 0xfd, 0x79, 0x69, 0xe1, 0xd7, 0xcc, 0xd7, 0xf9, 0x35, 0xeb, 0x35,
+       0xfd, 0x37, 0x86, 0x8d, 0x41, 0xfd, 0xd7, 0x22, 0xce, 0xb9, 0xad, 0xc9,
+       0x0c, 0xf3, 0x06, 0xe7, 0xa3, 0xf4, 0xed, 0x7e, 0xb1, 0x8f, 0x81, 0xe7,
+       0x75, 0xb0, 0x6d, 0xc8, 0xfc, 0x98, 0xf2, 0x36, 0x07, 0xbb, 0x4e, 0xbc,
+       0x41, 0x75, 0x66, 0x27, 0xc2, 0xd8, 0x68, 0x9e, 0x97, 0xa3, 0xfc, 0xf5,
+       0xaa, 0x61, 0xf2, 0xd7, 0x0d, 0x03, 0xf2, 0x38, 0x2f, 0x84, 0xbf, 0x34,
+       0x7a, 0x5c, 0x10, 0xdf, 0x55, 0xd1, 0xd3, 0xe3, 0x0d, 0x81, 0x77, 0x6d,
+       0x9f, 0x2d, 0x5c, 0xec, 0xb3, 0x9d, 0x56, 0xdc, 0x6f, 0x24, 0x53, 0x5d,
+       0xd6, 0x79, 0x13, 0xff, 0x8e, 0x9a, 0x9f, 0xe2, 0xab, 0x86, 0x4c, 0xee,
+       0x1f, 0x5d, 0x28, 0x93, 0x68, 0x5f, 0x1c, 0xe0, 0x1c, 0x65, 0x0e, 0xd2,
+       0xeb, 0x17, 0x46, 0xf0, 0xb8, 0xea, 0xbb, 0x0b, 0x24, 0xca, 0x9b, 0x76,
+       0xe1, 0x78, 0x8c, 0x9f, 0x5a, 0x24, 0xaa, 0xab, 0x5e, 0xe5, 0xeb, 0x35,
+       0x21, 0x1f, 0x8d, 0x69, 0x5d, 0xf2, 0x24, 0xc9, 0xab, 0x87, 0x1d, 0x63,
+       0x41, 0xdf, 0xa9, 0x98, 0x6d, 0xe1, 0x76, 0x71, 0x80, 0x6e, 0xda, 0xba,
+       0x07, 0xec, 0x56, 0x8c, 0x87, 0xeb, 0xe1, 0x38, 0x6a, 0x71, 0x3c, 0xda,
+       0xc1, 0x59, 0xc2, 0xee, 0xe9, 0xcf, 0x21, 0x8d, 0x65, 0xbd, 0xe5, 0x18,
+       0x57, 0x56, 0x3b, 0x25, 0x07, 0xee, 0xdb, 0xeb, 0xe9, 0x3d, 0x77, 0xe1,
+       0x84, 0x77, 0xe2, 0xff, 0x01, 0x3a, 0x9f, 0x4b, 0x76, 0x1f, 0x21, 0xfd,
+       0xd6, 0x7b, 0x79, 0x01, 0xe6, 0x3f, 0x0f, 0x66, 0x7e, 0x3e, 0x0a, 0xed,
+       0x65, 0xed, 0x30, 0x7c, 0xfb, 0x3b, 0xc1, 0xb7, 0xda, 0xf7, 0x59, 0x1c,
+       0x63, 0xd5, 0x46, 0xfc, 0x3e, 0xc9, 0x8f, 0x12, 0xdd, 0x9f, 0x20, 0x7e,
+       0xfb, 0x0d, 0xdf, 0x46, 0x8e, 0x63, 0xf8, 0x7c, 0xdf, 0x7f, 0xaf, 0x91,
+       0x90, 0x2e, 0x8c, 0xe8, 0x31, 0x9c, 0x9c, 0x9c, 0x12, 0xf3, 0x9d, 0x4a,
+       0x16, 0xdf, 0x25, 0x8c, 0xe3, 0xfb, 0x24, 0xcb, 0xb1, 0x8f, 0xf2, 0x6a,
+       0xf4, 0x8e, 0xa4, 0xfc, 0x42, 0xf6, 0x8d, 0xed, 0x4b, 0x35, 0xec, 0x7e,
+       0x37, 0x07, 0xf5, 0xd6, 0xc5, 0xae, 0x03, 0x39, 0xa6, 0x20, 0x3a, 0x9e,
+       0x5f, 0x03, 0xf2, 0x8e, 0xf6, 0xa3, 0x63, 0x5f, 0x82, 0x6a, 0x0b, 0xe6,
+       0x33, 0x03, 0xf1, 0x97, 0x24, 0x69, 0xfc, 0xa6, 0x08, 0xbb, 0x18, 0xca,
+       0x77, 0xe7, 0x91, 0xef, 0xb2, 0xb1, 0xfd, 0x30, 0x32, 0x1d, 0xf5, 0xee,
+       0xf6, 0xa3, 0x91, 0xb7, 0xe0, 0x7c, 0xbb, 0x78, 0x3b, 0xc0, 0x9f, 0xed,
+       0x32, 0x8d, 0x83, 0x78, 0x67, 0xcc, 0xfc, 0x88, 0x60, 0xf8, 0x9e, 0x24,
+       0xf8, 0x2e, 0xb4, 0xf0, 0x79, 0x18, 0xeb, 0x1b, 0x53, 0x35, 0x3e, 0xf8,
+       0x7e, 0xe3, 0x70, 0x7c, 0x6b, 0x4c, 0xe1, 0xf5, 0x84, 0x21, 0x7c, 0xab,
+       0xad, 0xb7, 0x05, 0xbf, 0x87, 0x83, 0xfe, 0x7d, 0xa7, 0x99, 0xbe, 0x87,
+       0x83, 0xf9, 0xe6, 0xe8, 0x20, 0xb9, 0x48, 0x4d, 0xe1, 0xf2, 0x30, 0x49,
+       0x7c, 0xff, 0x66, 0x0a, 0xf3, 0xd0, 0xf7, 0x00, 0x27, 0x89, 0xef, 0xe0,
+       0x4c, 0x51, 0x98, 0x4f, 0x89, 0xc1, 0x7d, 0x2e, 0x9f, 0xcc, 0xf7, 0x65,
+       0xf9, 0x79, 0x86, 0x02, 0xc1, 0xbf, 0x93, 0x14, 0x5f, 0x17, 0xd6, 0x39,
+       0x4c, 0x11, 0xfb, 0x32, 0x85, 0xac, 0x97, 0xc6, 0x4d, 0x67, 0x7e, 0x6a,
+       0x9d, 0xcc, 0x4e, 0xe7, 0x14, 0x8a, 0x99, 0x83, 0xda, 0xc9, 0x16, 0xdf,
+       0x9d, 0x98, 0x76, 0xc9, 0x6e, 0x69, 0xa1, 0xfa, 0x3f, 0x5f, 0x82, 0x12,
+       0x7d, 0xd6, 0x22, 0xce, 0x43, 0x0c, 0x41, 0xb7, 0xc0, 0xfa, 0x15, 0xfa,
+       0xee, 0x0d, 0xf1, 0xa5, 0x8c, 0xe7, 0x61, 0x86, 0xfe, 0x6e, 0x4a, 0x65,
+       0x0a, 0x97, 0x73, 0xfa, 0x38, 0x07, 0xd2, 0xf7, 0x02, 0xa3, 0xfc, 0x14,
+       0x7e, 0xdf, 0x0c, 0x5f, 0x32, 0x55, 0x61, 0x15, 0x58, 0x77, 0x74, 0x9b,
+       0xc2, 0x2c, 0xe1, 0x00, 0xef, 0xf6, 0xb7, 0x0d, 0x24, 0xbf, 0x9d, 0x7d,
+       0xaa, 0x17, 0xeb, 0x40, 0x1d, 0xb1, 0xe2, 0xb9, 0x2f, 0x18, 0xd5, 0xbb,
+       0x4e, 0x72, 0x72, 0xf9, 0x44, 0xd3, 0x82, 0x75, 0x12, 0xda, 0x7a, 0xf5,
+       0x78, 0x28, 0x84, 0xf9, 0x30, 0x3f, 0x36, 0x49, 0x81, 0xc8, 0x92, 0xf0,
+       0xe8, 0xa3, 0xf7, 0xdd, 0xce, 0xf8, 0x39, 0x8d, 0x22, 0xa6, 0xd2, 0x07,
+       0x56, 0x6e, 0xc7, 0x8f, 0x27, 0x93, 0x5e, 0xf7, 0x53, 0x9c, 0x54, 0x02,
+       0x71, 0x12, 0xea, 0x75, 0x83, 0xc5, 0x43, 0xf8, 0x28, 0xc3, 0xe4, 0xca,
+       0x44, 0xbe, 0xbf, 0x11, 0x09, 0xf3, 0x14, 0x36, 0x4b, 0xec, 0x38, 0xee,
+       0x57, 0xa4, 0xf1, 0xf5, 0x6a, 0xf3, 0x17, 0x02, 0x23, 0xe0, 0xb9, 0xbd,
+       0x32, 0xb1, 0x5e, 0x4c, 0x81, 0x1e, 0x8f, 0xe1, 0xfb, 0x1e, 0x91, 0x54,
+       0x38, 0x5c, 0x6a, 0xe7, 0xdf, 0x09, 0x4a, 0xa0, 0xef, 0x04, 0xdd, 0x28,
+       0x5e, 0xfb, 0x13, 0xf8, 0x77, 0x21, 0x23, 0xef, 0xf7, 0x5f, 0xfc, 0x7e,
+       0x7e, 0x60, 0xff, 0xc7, 0x81, 0xdf, 0x0d, 0x8a, 0x0c, 0x7c, 0x8f, 0xd2,
+       0x81, 0xe7, 0x4c, 0x30, 0x7f, 0xe7, 0x53, 0xce, 0x07, 0xfb, 0xcd, 0x77,
+       0xa7, 0x2c, 0xad, 0x4e, 0x99, 0x18, 0xa8, 0x97, 0x63, 0x6e, 0xa6, 0xa2,
+       0x5f, 0xa1, 0xaf, 0x97, 0x43, 0xf4, 0x9d, 0x0b, 0x3a, 0xdf, 0xac, 0xd5,
+       0x7b, 0xbc, 0xea, 0x9d, 0xab, 0xe2, 0xb9, 0xb9, 0x85, 0x71, 0x16, 0x3a,
+       0x4f, 0x9b, 0x6b, 0x19, 0x95, 0x87, 0x76, 0x2b, 0x23, 0xd1, 0x5d, 0x9d,
+       0x42, 0x75, 0x1f, 0x5b, 0x6e, 0xa1, 0x49, 0x14, 0xef, 0x44, 0x57, 0x44,
+       0x80, 0xcf, 0xad, 0xcc, 0x39, 0x19, 0xf1, 0x1c, 0xa8, 0xd7, 0xe3, 0xdf,
+       0x4f, 0x1a, 0x38, 0xcf, 0x94, 0xc0, 0xe8, 0xfc, 0x9f, 0xd5, 0xcc, 0xeb,
+       0x19, 0x9f, 0x01, 0xb9, 0xc0, 0xef, 0x17, 0x81, 0x54, 0xa9, 0x58, 0xd7,
+       0xc2, 0x9e, 0x28, 0xa1, 0xfa, 0xc7, 0xa7, 0xa2, 0x2d, 0x0e, 0x3c, 0x87,
+       0x60, 0x46, 0x78, 0xad, 0x01, 0x78, 0x1b, 0x2d, 0xa2, 0xee, 0x47, 0x57,
+       0x77, 0xd9, 0x68, 0x33, 0xd0, 0xf7, 0x38, 0x1b, 0x59, 0x38, 0x9d, 0xe7,
+       0x9e, 0x15, 0xe6, 0xfe, 0x1e, 0xae, 0xff, 0xb1, 0x88, 0x62, 0x3a, 0x2f,
+       0x9d, 0xb5, 0x6d, 0x5a, 0x12, 0xf9, 0x83, 0xb0, 0xde, 0x69, 0xda, 0x7a,
+       0x0d, 0x83, 0xeb, 0x10, 0xb1, 0xfe, 0x0f, 0x9f, 0xd3, 0xd7, 0xff, 0x69,
+       0xeb, 0xc2, 0xe3, 0xeb, 0xf8, 0x5e, 0xbb, 0xc0, 0x97, 0xb6, 0x4e, 0xbb,
+       0x76, 0xde, 0xc7, 0xa9, 0x84, 0x9c, 0xf7, 0xd1, 0xd6, 0xff, 0x4c, 0x38,
+       0x5f, 0xa7, 0x11, 0x77, 0xe2, 0xd3, 0xe8, 0x59, 0x15, 0xf5, 0x83, 0x7e,
+       0x7d, 0x1a, 0x3f, 0xfc, 0x3f, 0xdd, 0xfb, 0x35, 0x6d, 0x60, 0x5c, 0x00,
+       0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 xsem_int_table_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xbb, 0x26,
+       0xcb, 0xc0, 0xf0, 0xa3, 0x1e, 0x81, 0x59, 0x64, 0x18, 0x18, 0x26, 0xf1,
+       0xa1, 0x8a, 0xd1, 0x12, 0xcf, 0xe0, 0x66, 0x60, 0x78, 0x04, 0xc4, 0x2c,
+       0x3c, 0x0c, 0x0c, 0x85, 0x40, 0x7b, 0x23, 0x80, 0x74, 0x24, 0x10, 0x1f,
+       0x01, 0xe2, 0xa3, 0x40, 0xac, 0xc2, 0xcb, 0xc0, 0x10, 0x0b, 0xc4, 0x71,
+       0x40, 0x3c, 0x07, 0xc8, 0x9f, 0x0b, 0xc4, 0xa5, 0x40, 0x9c, 0x05, 0x75,
+       0x63, 0x2b, 0x0b, 0x03, 0x43, 0x3b, 0x10, 0x77, 0x02, 0x71, 0x37, 0x10,
+       0xeb, 0x30, 0x33, 0x30, 0xe8, 0x32, 0x13, 0x6f, 0x7f, 0xb1, 0x08, 0x03,
+       0xc3, 0x13, 0x09, 0x04, 0x5f, 0x51, 0x12, 0x68, 0xa7, 0x34, 0xfd, 0xfc,
+       0x3f, 0xd8, 0xf0, 0x0c, 0x7d, 0xfa, 0xda, 0xc7, 0x6d, 0xc0, 0xc0, 0xb0,
+       0xd4, 0x02, 0xc1, 0x17, 0x03, 0xb2, 0x97, 0x59, 0xa0, 0xaa, 0x59, 0x6e,
+       0x81, 0xdf, 0x8c, 0x15, 0x68, 0xf2, 0x2b, 0xd1, 0xf8, 0xab, 0xf0, 0xe8,
+       0xdf, 0xa7, 0x87, 0xca, 0xd7, 0xd3, 0x40, 0x73, 0x9f, 0x16, 0x03, 0x83,
+       0x15, 0x52, 0x98, 0xe8, 0x6b, 0xe0, 0x77, 0x0b, 0x3a, 0xce, 0x04, 0xea,
+       0xcd, 0x02, 0x62, 0x00, 0x9f, 0x30, 0x90, 0xcd, 0x68, 0x03, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 xsem_pram_data_e1[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d,
+       0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73, 0x1e, 0xf3, 0xc8, 0xcc,
+       0x64, 0x12, 0x42, 0x08, 0x10, 0xc2, 0x09, 0x2f, 0xa3, 0x0d, 0x38, 0x21,
+       0x21, 0x05, 0x8a, 0xed, 0x10, 0x20, 0xa2, 0x45, 0x8d, 0x8f, 0x2a, 0x54,
+       0xd4, 0x09, 0x8f, 0x24, 0xe4, 0x35, 0x01, 0x1f, 0x17, 0x6b, 0xdb, 0x0c,
+       0x04, 0x23, 0x20, 0x68, 0xb0, 0x58, 0xa2, 0x46, 0x3b, 0x41, 0x50, 0xf0,
+       0x06, 0x1d, 0x68, 0x90, 0x20, 0x01, 0x07, 0xb0, 0x1a, 0x7a, 0x7d, 0x04,
+       0xaf, 0xf5, 0xd1, 0xf6, 0x7a, 0x83, 0x52, 0x40, 0x08, 0x24, 0xe2, 0x0b,
+       0xbd, 0x6d, 0xfd, 0xf7, 0x5a, 0x7b, 0x9f, 0xcc, 0x39, 0x27, 0x33, 0x40,
+       0xff, 0xf6, 0xff, 0x6f, 0xff, 0xfb, 0xc7, 0xaf, 0x3d, 0xec, 0x73, 0xf6,
+       0x63, 0xed, 0xf5, 0xda, 0x6b, 0xad, 0xbd, 0xf6, 0x1e, 0x99, 0x0c, 0x24,
+       0xd2, 0x0f, 0x08, 0xf9, 0x16, 0xfe, 0xe8, 0x73, 0xa6, 0x44, 0x08, 0x7d,
+       0xd5, 0xf7, 0x74, 0xbe, 0x42, 0x54, 0x92, 0x48, 0x48, 0x7d, 0x0e, 0x2d,
+       0xa7, 0x10, 0x92, 0x3e, 0x8a, 0x84, 0x88, 0x40, 0x48, 0x41, 0x0d, 0x2d,
+       0xe7, 0x11, 0xf2, 0xd0, 0x6d, 0x24, 0x64, 0xcd, 0x24, 0x64, 0xff, 0xeb,
+       0x16, 0xfc, 0xbe, 0xca, 0xcf, 0xca, 0xb4, 0x5d, 0xd8, 0x72, 0x39, 0xfd,
+       0x3e, 0x9a, 0xbd, 0x7f, 0x2c, 0x8b, 0xb6, 0xa3, 0xef, 0x1f, 0x3b, 0x27,
+       0x62, 0xbb, 0xe0, 0x2c, 0x12, 0xda, 0x4c, 0xcb, 0x49, 0x84, 0xf6, 0x36,
+       0x92, 0xd0, 0x21, 0xfc, 0xf8, 0x2c, 0xf0, 0x36, 0xd8, 0xc7, 0xd2, 0xfa,
+       0x4d, 0xb7, 0x59, 0x88, 0x55, 0x25, 0xe4, 0x51, 0x3a, 0x0c, 0x99, 0x44,
+       0x88, 0x8b, 0xf8, 0xec, 0x84, 0x36, 0x5d, 0x35, 0x8a, 0xf5, 0xf7, 0xc8,
+       0x2c, 0xcb, 0x33, 0xa2, 0x00, 0x1f, 0x23, 0x69, 0xf3, 0x69, 0x79, 0xf5,
+       0xf4, 0x92, 0xfc, 0xd5, 0xb4, 0xb4, 0x46, 0x66, 0x70, 0x35, 0xce, 0x29,
+       0x79, 0x26, 0x48, 0xfb, 0xf7, 0x58, 0x46, 0xe2, 0x3c, 0x68, 0xbd, 0xc7,
+       0x9c, 0xb4, 0xde, 0xc3, 0xef, 0x97, 0x92, 0xd5, 0xb4, 0xdd, 0x86, 0xb9,
+       0x16, 0xa1, 0x24, 0x9b, 0xd6, 0x6b, 0x56, 0x66, 0x87, 0xb2, 0xa3, 0xf3,
+       0xd7, 0x9e, 0x73, 0x89, 0xc4, 0xdb, 0x05, 0xad, 0x96, 0x89, 0xf0, 0xf4,
+       0xf1, 0x67, 0x44, 0x81, 0xe7, 0x2f, 0xa6, 0x58, 0x70, 0x9c, 0xb5, 0x35,
+       0x0c, 0x1f, 0xb4, 0x9e, 0x62, 0x49, 0x23, 0xa4, 0xb5, 0xf3, 0x80, 0xcd,
+       0x4f, 0xfb, 0x5b, 0x5b, 0xd9, 0x7a, 0xb8, 0x90, 0x7e, 0x7f, 0x70, 0x94,
+       0xc5, 0x4b, 0x31, 0x48, 0x1e, 0xec, 0x3c, 0x60, 0xbf, 0x84, 0x8e, 0x1f,
+       0xcc, 0xb3, 0x78, 0x47, 0xd3, 0xda, 0xe9, 0x52, 0x44, 0xf0, 0x38, 0xa3,
+       0xe3, 0x4d, 0x22, 0x14, 0xf0, 0x09, 0xb4, 0x9e, 0x77, 0x87, 0x4d, 0x75,
+       0xf6, 0xaf, 0x4f, 0xfb, 0x9d, 0x0a, 0xf3, 0x5e, 0x43, 0xf1, 0x2e, 0x66,
+       0x46, 0xdb, 0x8d, 0x07, 0x38, 0x69, 0xbb, 0xb5, 0x94, 0x64, 0x61, 0x3a,
+       0xee, 0x2f, 0x65, 0xef, 0x21, 0x18, 0xf7, 0x97, 0xd7, 0x24, 0x0b, 0x41,
+       0x12, 0xad, 0x77, 0x15, 0x00, 0x09, 0xf5, 0xe6, 0x5a, 0x48, 0x84, 0xd6,
+       0x23, 0x52, 0xaf, 0x8d, 0xd0, 0x71, 0x56, 0x4f, 0x79, 0xdb, 0x36, 0x9a,
+       0xd6, 0x5f, 0x5d, 0x64, 0x81, 0x49, 0x90, 0xb5, 0x5e, 0xed, 0xbb, 0xd7,
+       0x4e, 0xa0, 0xbf, 0x19, 0x63, 0x0e, 0x8d, 0x02, 0xba, 0x5e, 0x45, 0xbf,
+       0xc3, 0x3c, 0xb2, 0x1f, 0x99, 0x0d, 0xf3, 0x7e, 0x78, 0xba, 0x42, 0x00,
+       0xff, 0xbf, 0x14, 0x68, 0x3d, 0x8a, 0xe2, 0xc6, 0x62, 0xe5, 0x87, 0x00,
+       0x9f, 0xab, 0x86, 0x78, 0xe0, 0x3d, 0x7d, 0xfa, 0x62, 0xe1, 0xb5, 0x4d,
+       0xb0, 0x21, 0x1c, 0x64, 0xcd, 0x06, 0x42, 0xf2, 0x09, 0x80, 0x80, 0x7f,
+       0xab, 0x7d, 0xa1, 0x95, 0x23, 0x80, 0xbf, 0xf2, 0x88, 0x17, 0xca, 0xe9,
+       0x5e, 0xda, 0xde, 0xd9, 0xbf, 0x7d, 0x97, 0x60, 0x45, 0xba, 0x34, 0xca,
+       0xc1, 0xc1, 0x80, 0xbf, 0x78, 0xf4, 0x1b, 0xc5, 0xf1, 0xb9, 0x3a, 0x6b,
+       0x89, 0x1d, 0xe8, 0x41, 0x48, 0x43, 0x5a, 0xd1, 0x58, 0x42, 0xd6, 0x03,
+       0x9e, 0x60, 0x50, 0xc9, 0xaf, 0x5e, 0xef, 0x8a, 0xd6, 0x5f, 0x29, 0x30,
+       0xfc, 0xac, 0x93, 0x89, 0x4f, 0xa0, 0xf3, 0x4b, 0xc8, 0x53, 0x42, 0xcb,
+       0x28, 0x9e, 0x2d, 0xd9, 0x9e, 0x39, 0x30, 0x5f, 0xa7, 0x5f, 0x21, 0x57,
+       0xd2, 0xf2, 0x2a, 0x21, 0x38, 0x58, 0x04, 0xba, 0x8c, 0x55, 0xc8, 0x66,
+       0x15, 0xf9, 0xc2, 0x3e, 0x9a, 0x96, 0xd7, 0x5e, 0x9a, 0xec, 0x05, 0xfe,
+       0xab, 0x17, 0xc2, 0x69, 0x12, 0x7c, 0xbf, 0x86, 0x7e, 0xa7, 0x5d, 0x1e,
+       0x28, 0x1a, 0x3f, 0x07, 0xf8, 0xb3, 0xc9, 0xab, 0x20, 0x3f, 0x53, 0xfe,
+       0x39, 0x04, 0xf8, 0x5e, 0xeb, 0x4f, 0x26, 0xab, 0x55, 0xfc, 0xde, 0x89,
+       0xed, 0x9d, 0xa3, 0x3c, 0x56, 0xc4, 0x04, 0x85, 0x87, 0xe2, 0x65, 0x00,
+       0xe5, 0x25, 0xc0, 0x6b, 0xce, 0x75, 0xf5, 0x57, 0x8d, 0x04, 0xfa, 0x4c,
+       0xb0, 0x78, 0x80, 0x42, 0xab, 0x85, 0xa9, 0xea, 0x7c, 0x90, 0x9f, 0x24,
+       0x9b, 0x07, 0xc6, 0x97, 0x27, 0xdc, 0x80, 0xf4, 0x93, 0x07, 0x26, 0x0b,
+       0x44, 0x47, 0xef, 0x9f, 0x03, 0xbd, 0x29, 0x9e, 0x6a, 0xd5, 0xa2, 0x9f,
+       0xc3, 0xbc, 0x9e, 0xc8, 0xfb, 0x28, 0x69, 0x34, 0xad, 0xbf, 0x26, 0xe7,
+       0xc5, 0x46, 0xa0, 0xd3, 0x93, 0xf7, 0xd8, 0x90, 0x7e, 0x4f, 0x4e, 0xe8,
+       0x5c, 0x0c, 0x72, 0xf5, 0xd8, 0xb9, 0xdc, 0xf7, 0xfd, 0x28, 0x97, 0x8a,
+       0x77, 0x33, 0xed, 0xe7, 0xa9, 0x9c, 0x63, 0x99, 0x84, 0x0e, 0xf8, 0xc8,
+       0xcc, 0x8f, 0x92, 0x00, 0x7f, 0xc3, 0x46, 0x35, 0xdc, 0x49, 0xdc, 0xf4,
+       0x39, 0xab, 0xb7, 0x96, 0x8c, 0xa3, 0xf0, 0x91, 0x86, 0xa2, 0x05, 0x99,
+       0xc8, 0x27, 0xc2, 0x8d, 0x14, 0xaf, 0xc3, 0x96, 0x2a, 0x44, 0xb5, 0x31,
+       0x5a, 0x7e, 0x4b, 0xe0, 0x3b, 0xf1, 0x85, 0xb3, 0x59, 0xd9, 0x49, 0xe7,
+       0x33, 0x8c, 0xd3, 0xb9, 0xb5, 0xf3, 0x6d, 0x5b, 0x31, 0xf4, 0x37, 0x97,
+       0x44, 0xc6, 0xb8, 0xf1, 0xbd, 0x2d, 0x35, 0x39, 0xaa, 0x67, 0x86, 0xe5,
+       0x91, 0x48, 0x2a, 0xed, 0xff, 0xb1, 0x85, 0xaf, 0xa2, 0x9c, 0x3f, 0x79,
+       0x59, 0xaa, 0x97, 0xc9, 0x79, 0x1a, 0xf2, 0x4b, 0x06, 0xef, 0x27, 0x1d,
+       0xea, 0x53, 0xfd, 0x92, 0x66, 0x23, 0xc1, 0x04, 0xfa, 0x1c, 0xd6, 0xd1,
+       0x7b, 0x03, 0xc0, 0x35, 0x2c, 0xeb, 0xd8, 0x5c, 0x80, 0x73, 0xff, 0x1b,
+       0xaf, 0x0a, 0x40, 0xb7, 0xa7, 0xc6, 0xa5, 0xaa, 0xa0, 0x8f, 0x92, 0xfc,
+       0x9d, 0xa4, 0x8b, 0xd2, 0x7d, 0x58, 0xf6, 0xbb, 0xf7, 0x41, 0x3d, 0x97,
+       0x33, 0x94, 0x56, 0x94, 0x8d, 0xf5, 0xff, 0x82, 0xed, 0x4c, 0xf0, 0x3f,
+       0xa9, 0xfa, 0x36, 0x01, 0xde, 0xb6, 0x09, 0x35, 0x87, 0x80, 0x3e, 0xc1,
+       0x1c, 0x8b, 0x97, 0xd1, 0x9b, 0xe9, 0xc1, 0x35, 0x77, 0xa5, 0x86, 0x40,
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+       0x7c, 0x78, 0xd6, 0xdb, 0x88, 0xc7, 0xb5, 0x0b, 0x1e, 0xc1, 0x27, 0x69,
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+       0x6b, 0xfc, 0x96, 0x99, 0x60, 0x77, 0xaf, 0x97, 0x3a, 0x57, 0x8e, 0xa2,
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+       0xfa, 0x31, 0x82, 0x0a, 0x95, 0x42, 0x36, 0x2b, 0xfd, 0xee, 0x04, 0x9a,
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+       0xee, 0x4c, 0x90, 0xaf, 0x75, 0xb7, 0x31, 0xbf, 0xcc, 0x0c, 0xff, 0xdd,
+       0x53, 0x43, 0x1d, 0x16, 0x1c, 0x87, 0xa0, 0x5b, 0xe7, 0x8a, 0x83, 0xd7,
+       0xb9, 0xa0, 0xc1, 0x40, 0xff, 0x78, 0x43, 0x08, 0x97, 0x2b, 0x8b, 0xc1,
+       0x75, 0x54, 0x60, 0xf4, 0x7a, 0xb8, 0xb3, 0xe0, 0x2a, 0xf4, 0x93, 0x8a,
+       0xe8, 0x7b, 0xda, 0xd1, 0x23, 0x9d, 0x23, 0xec, 0x20, 0xdf, 0xfd, 0xec,
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+       0x33, 0xe9, 0xfb, 0xb1, 0xd6, 0xf0, 0xd5, 0xc8, 0x6f, 0xdb, 0x2c, 0xa8,
+       0xa7, 0x08, 0x61, 0x7a, 0x4e, 0x20, 0x16, 0xf5, 0xdb, 0x91, 0xb0, 0x88,
+       0x30, 0xb8, 0x90, 0xf5, 0xa8, 0xfe, 0x5e, 0x21, 0x47, 0xe6, 0x2c, 0xa0,
+       0xf5, 0x57, 0xec, 0x74, 0x12, 0xc0, 0x97, 0xc6, 0x0f, 0xe9, 0xbc, 0xcf,
+       0xd5, 0x35, 0x94, 0x0f, 0x62, 0xcc, 0xbb, 0x43, 0x10, 0xe3, 0xd1, 0x9d,
+       0xd9, 0x19, 0x9c, 0xee, 0x9d, 0x30, 0xde, 0xc0, 0x0b, 0xd3, 0x9f, 0x4a,
+       0xb3, 0x1d, 0xec, 0xb6, 0x70, 0xa8, 0x7e, 0x48, 0x39, 0xf8, 0x1f, 0x35,
+       0xcc, 0xdf, 0x0d, 0x47, 0x0e, 0xa0, 0xfe, 0x49, 0x9f, 0x7e, 0x33, 0xfa,
+       0x29, 0x5b, 0x9a, 0x53, 0xe7, 0x2c, 0x00, 0xbe, 0xca, 0xf2, 0x79, 0x01,
+       0x1d, 0x1a, 0x3c, 0x60, 0x9f, 0xc4, 0xf2, 0x13, 0xaf, 0xb6, 0xd8, 0xce,
+       0xeb, 0xbf, 0xc7, 0xd3, 0xc3, 0x8d, 0x95, 0x2b, 0xd0, 0xef, 0x6d, 0xec,
+       0x8c, 0x3d, 0xff, 0x29, 0x16, 0xe6, 0x6f, 0x87, 0xa9, 0x9e, 0xf4, 0x66,
+       0xc7, 0x1f, 0x3f, 0xdf, 0xc2, 0xec, 0xe8, 0x24, 0x0b, 0xe7, 0xbb, 0x19,
+       0xaf, 0xa6, 0xe9, 0xd7, 0x33, 0x6d, 0x5d, 0xd5, 0xd6, 0xd9, 0x61, 0x12,
+       0x09, 0x8a, 0xba, 0xf5, 0xf0, 0x26, 0x8e, 0x3f, 0xf3, 0xba, 0x49, 0xa4,
+       0x06, 0xdb, 0x18, 0xc6, 0xe7, 0xe8, 0x3f, 0x36, 0x2e, 0x60, 0x71, 0x88,
+       0x0d, 0x53, 0x2c, 0x18, 0x5f, 0xd1, 0xf8, 0x9c, 0xd6, 0x4b, 0x03, 0xbc,
+       0xd2, 0x79, 0xa0, 0x3d, 0x47, 0xf9, 0x30, 0x04, 0xf6, 0xdc, 0xc3, 0xa4,
+       0x01, 0xe5, 0x26, 0x48, 0xdb, 0x6f, 0x26, 0xfd, 0xe1, 0xbe, 0x8d, 0x58,
+       0x2e, 0x6a, 0x7e, 0x93, 0xf9, 0xfc, 0xfa, 0xc6, 0xe3, 0xfe, 0xf5, 0xed,
+       0x5c, 0x5f, 0xad, 0xcb, 0xb9, 0xc7, 0x0e, 0x5d, 0xd1, 0xf1, 0xd2, 0x80,
+       0x3f, 0x02, 0x6e, 0xa6, 0x27, 0xab, 0x5c, 0xcc, 0x8e, 0x9d, 0xb6, 0x53,
+       0x8e, 0xfc, 0x80, 0xc2, 0x51, 0xd5, 0x2c, 0xa0, 0x9d, 0x65, 0xd9, 0x67,
+       0x47, 0x38, 0xcf, 0x6c, 0xa2, 0x65, 0xda, 0x75, 0xc4, 0xa5, 0x60, 0xfd,
+       0xd3, 0x1e, 0x1b, 0x96, 0x03, 0xd6, 0xce, 0x87, 0xbe, 0x47, 0xcb, 0xbd,
+       0x3b, 0x45, 0x82, 0x76, 0x64, 0x96, 0xc3, 0x02, 0xfc, 0x7a, 0x8c, 0xf3,
+       0x2b, 0xc9, 0xa3, 0x65, 0xb0, 0x87, 0xed, 0xac, 0x58, 0xd5, 0xbc, 0xff,
+       0x76, 0xe8, 0xaf, 0xac, 0xcd, 0x4a, 0xec, 0xb4, 0xff, 0xaa, 0xdd, 0xa5,
+       0xd7, 0x7e, 0x8f, 0x96, 0x4b, 0x3b, 0x64, 0x02, 0x55, 0xaa, 0x36, 0x2f,
+       0x53, 0x86, 0xd0, 0xf2, 0xa2, 0x90, 0x10, 0x86, 0x72, 0x4f, 0x01, 0x5d,
+       0xa8, 0x00, 0x2f, 0xc9, 0x4a, 0x08, 0xfc, 0xf6, 0x1e, 0x77, 0x67, 0xea,
+       0x8f, 0xe8, 0xbc, 0x4f, 0xd6, 0xda, 0x88, 0x4a, 0x41, 0xa9, 0x73, 0x75,
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+       0x04, 0xd0, 0x88, 0x74, 0x1e, 0x9b, 0x5f, 0x1d, 0x0c, 0xf3, 0xda, 0x2a,
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+       0xb5, 0x62, 0x8b, 0x68, 0xb4, 0xb3, 0xf9, 0xfa, 0x1f, 0x3c, 0xcc, 0xe8,
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+       0xe9, 0xf4, 0x81, 0xfd, 0xed, 0x6c, 0x49, 0x1a, 0xbf, 0x9a, 0xe8, 0xf9,
+       0xa2, 0xe0, 0x0d, 0x80, 0xc3, 0x45, 0xa5, 0x45, 0xcf, 0x17, 0x89, 0x13,
+       0x1d, 0x06, 0x7e, 0x4c, 0xf2, 0x25, 0x1b, 0xca, 0xb4, 0x27, 0xcf, 0xb1,
+       0xef, 0xf0, 0x32, 0x0c, 0xe2, 0xb6, 0x21, 0x3c, 0xca, 0x10, 0x05, 0xf5,
+       0xc5, 0xd4, 0x21, 0x36, 0x84, 0xf7, 0x9e, 0x7d, 0x76, 0x2c, 0xdf, 0x33,
+       0x99, 0xc1, 0x7b, 0xcf, 0x10, 0x27, 0xca, 0x19, 0xae, 0x2d, 0x94, 0x8e,
+       0xf7, 0x28, 0xfe, 0xcb, 0xf5, 0x76, 0x2b, 0xac, 0x4c, 0x10, 0x4a, 0x7a,
+       0x53, 0xf4, 0x7f, 0x04, 0xf8, 0x8d, 0xbe, 0x57, 0x2d, 0xf0, 0xde, 0x21,
+       0x92, 0x1a, 0xd4, 0xcf, 0x56, 0x82, 0xfa, 0xe8, 0x81, 0xcc, 0xfc, 0xa7,
+       0x83, 0x3a, 0xfc, 0xac, 0x1c, 0x46, 0xe9, 0x4b, 0xcb, 0xa7, 0xc1, 0xfe,
+       0x19, 0x18, 0xc5, 0xeb, 0x03, 0xc3, 0x4a, 0xd2, 0x8a, 0x75, 0xe3, 0xd4,
+       0x0f, 0x53, 0x66, 0x6f, 0xcc, 0x66, 0xef, 0xe7, 0x3b, 0x61, 0xbc, 0xa2,
+       0x1e, 0xc0, 0x43, 0x40, 0xe9, 0x1d, 0x03, 0x76, 0xa5, 0x79, 0x1c, 0xeb,
+       0x88, 0x89, 0x86, 0x71, 0x6c, 0x19, 0x65, 0x38, 0xce, 0x37, 0xa6, 0x71,
+       0xac, 0x19, 0x65, 0xa6, 0x71, 0x6c, 0xb3, 0x37, 0xf2, 0xf7, 0x7c, 0x9c,
+       0x3f, 0xc3, 0xbc, 0xe2, 0x8d, 0xf3, 0xc0, 0x88, 0xc9, 0xc6, 0xf9, 0x64,
+       0x94, 0xe3, 0x38, 0x56, 0xd1, 0x34, 0x9f, 0x8c, 0x72, 0xd3, 0x38, 0x0e,
+       0x36, 0x1f, 0xfa, 0x9e, 0x8f, 0x63, 0x17, 0xcf, 0x37, 0x9f, 0x91, 0x53,
+       0x8c, 0xf3, 0x19, 0x5e, 0x89, 0xe3, 0xa4, 0x88, 0x8a, 0x21, 0x6e, 0x65,
+       0x1d, 0x5e, 0x69, 0x1a, 0xc7, 0x89, 0xe3, 0xc0, 0x7b, 0x18, 0x87, 0xa4,
+       0x33, 0xff, 0x46, 0xb1, 0xf6, 0x96, 0x20, 0xfd, 0x5f, 0xb6, 0x13, 0xb0,
+       0xa7, 0x15, 0xab, 0xff, 0x59, 0xe8, 0x97, 0xfc, 0xc1, 0x4e, 0x50, 0x9f,
+       0xa8, 0x74, 0xdc, 0x41, 0xa0, 0x57, 0x92, 0x71, 0xbf, 0xe0, 0x3f, 0x2c,
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+       0x5d, 0x80, 0xf6, 0xce, 0x42, 0x0e, 0x22, 0x09, 0xd5, 0xa3, 0x7f, 0x5e,
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+       0x53, 0xe6, 0xc7, 0xb0, 0x0b, 0x16, 0x36, 0xc8, 0xc7, 0xba, 0x0c, 0xfc,
+       0xcb, 0xf5, 0x5e, 0x01, 0xc9, 0xaa, 0x01, 0x3f, 0x8b, 0xdb, 0x01, 0x5a,
+       0xf9, 0x18, 0xd5, 0x5f, 0x84, 0xea, 0xad, 0x8f, 0xa8, 0xfe, 0x82, 0xe7,
+       0x71, 0x99, 0xea, 0x69, 0xfa, 0xfe, 0x28, 0xd5, 0x6f, 0x44, 0xd1, 0xc3,
+       0xbb, 0x0c, 0xdb, 0x1d, 0x93, 0x18, 0x1e, 0x8f, 0x35, 0xb1, 0x75, 0xe4,
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+       0x37, 0xf3, 0x69, 0x2c, 0x6c, 0x48, 0x60, 0xbe, 0x02, 0x87, 0x23, 0xc0,
+       0xe9, 0xd1, 0xbb, 0xdb, 0x1a, 0xda, 0x88, 0xf4, 0xf0, 0x0d, 0x05, 0xbb,
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+       0x24, 0x63, 0x71, 0x28, 0xd8, 0x47, 0x3f, 0x5e, 0xb9, 0xfd, 0x37, 0x50,
+       0xed, 0x5d, 0xa1, 0x78, 0xd8, 0x12, 0x3a, 0xdf, 0xd9, 0xad, 0xeb, 0xe4,
+       0xa1, 0xb4, 0x7c, 0x46, 0xee, 0xba, 0xdd, 0xeb, 0xd4, 0xf5, 0x33, 0x5b,
+       0xfe, 0x08, 0xe6, 0x6d, 0xa3, 0xff, 0x41, 0x3f, 0x73, 0xfc, 0xb4, 0xac,
+       0x1b, 0xff, 0xd6, 0x32, 0x63, 0xf9, 0x36, 0x22, 0x45, 0xcb, 0x94, 0x6e,
+       0x33, 0xc4, 0x11, 0x9c, 0x1e, 0x7c, 0x5c, 0x35, 0x24, 0x03, 0xbd, 0x6e,
+       0x4e, 0x65, 0xf0, 0xdc, 0x06, 0xcf, 0xf1, 0xf0, 0xd9, 0x83, 0xf4, 0xba,
+       0xdd, 0xc3, 0xda, 0x6a, 0xf0, 0x04, 0xee, 0x93, 0x49, 0x04, 0xd7, 0xa3,
+       0xae, 0x81, 0xcc, 0xb8, 0x1d, 0x88, 0xf5, 0xfc, 0xda, 0xba, 0x62, 0x82,
+       0xef, 0x76, 0xd9, 0xe6, 0x2b, 0xa2, 0xf4, 0xbc, 0xfd, 0x5e, 0x11, 0xf1,
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+       0xcf, 0x64, 0xf0, 0x2f, 0x2f, 0x04, 0xff, 0x1d, 0x4b, 0x8d, 0xdf, 0x49,
+       0x90, 0x8d, 0xa7, 0xe1, 0x55, 0xe3, 0x83, 0x5b, 0x66, 0x4f, 0x1d, 0x70,
+       0x54, 0x57, 0x6f, 0x8e, 0xff, 0xaa, 0x01, 0x47, 0x75, 0xfc, 0x72, 0x6b,
+       0xd9, 0xf5, 0x86, 0xf2, 0x6d, 0x35, 0x73, 0x0c, 0xf5, 0xef, 0x58, 0x5a,
+       0x6c, 0xf8, 0x5e, 0x1c, 0x5c, 0x64, 0xf8, 0x3e, 0x7f, 0xe5, 0x62, 0x43,
+       0x79, 0x61, 0xc3, 0xbd, 0x86, 0xfa, 0xa5, 0x8d, 0xcb, 0x0c, 0xdf, 0x17,
+       0x85, 0x56, 0x19, 0xbe, 0x57, 0x6c, 0x59, 0x67, 0x28, 0x57, 0x85, 0x1f,
+       0x33, 0xd4, 0x0f, 0xb4, 0x35, 0x1b, 0xbe, 0x5b, 0xf6, 0x5d, 0x7a, 0x1d,
+       0xc8, 0x63, 0xdd, 0xef, 0x44, 0x02, 0xf6, 0xd9, 0x17, 0xce, 0x63, 0x0f,
+       0x81, 0x7d, 0xf5, 0x85, 0x53, 0x42, 0xbf, 0xaa, 0x1a, 0x78, 0x8d, 0xca,
+       0xe1, 0x89, 0xda, 0x34, 0xe4, 0xef, 0x93, 0xb5, 0x2a, 0x3e, 0xcf, 0xb4,
+       0xe5, 0xe2, 0xfe, 0x58, 0xc0, 0x41, 0xe5, 0x99, 0xae, 0xf5, 0x1b, 0xea,
+       0x0e, 0x2d, 0x5b, 0x39, 0x05, 0xf4, 0x08, 0xad, 0x4f, 0x75, 0xf8, 0x13,
+       0x75, 0x6f, 0x2d, 0x0b, 0x52, 0xdf, 0x7d, 0x23, 0x04, 0xa9, 0x29, 0xdf,
+       0x8b, 0x8d, 0x0a, 0x89, 0x0c, 0x00, 0x3f, 0x26, 0xb9, 0x8f, 0xaf, 0x7b,
+       0x45, 0xdd, 0xf7, 0xae, 0x0b, 0x7c, 0x6f, 0xa4, 0x0b, 0x56, 0x6e, 0xff,
+       0xef, 0x62, 0x57, 0xec, 0xf7, 0x3d, 0x42, 0xef, 0x18, 0xb0, 0xef, 0x82,
+       0x1f, 0x58, 0x71, 0xff, 0x26, 0x9e, 0xfd, 0x40, 0xff, 0x86, 0x92, 0x18,
+       0xfe, 0x83, 0xf6, 0xec, 0x86, 0xf8, 0x86, 0x4e, 0xef, 0xbc, 0x2c, 0x32,
+       0xbb, 0xfa, 0x72, 0xb1, 0xe0, 0x65, 0x91, 0x3e, 0x2b, 0x15, 0x26, 0xef,
+       0x95, 0x3b, 0x06, 0x17, 0x40, 0xbc, 0xa0, 0x52, 0x89, 0x8c, 0xa9, 0x89,
+       0x61, 0x67, 0xf7, 0x8d, 0x17, 0xa6, 0xc0, 0x0c, 0x82, 0x7e, 0x98, 0xbc,
+       0x2c, 0x0a, 0x0d, 0x8d, 0xca, 0x2f, 0xd2, 0x6f, 0xa4, 0x41, 0xee, 0xaf,
+       0xb1, 0xf8, 0xf7, 0x81, 0x7e, 0xee, 0xde, 0x2f, 0xb2, 0xfd, 0x81, 0xc8,
+       0xc1, 0x0c, 0xd8, 0xa7, 0xb9, 0x5c, 0xf4, 0xbd, 0x0c, 0xef, 0x49, 0xdb,
+       0x40, 0x5c, 0x1f, 0xdf, 0xad, 0xf5, 0x0d, 0x38, 0x3a, 0x8a, 0x90, 0xf7,
+       0x6b, 0x67, 0xe2, 0xf3, 0xf7, 0xb5, 0x45, 0x03, 0x20, 0x7e, 0xf4, 0xc7,
+       0xda, 0xd9, 0x58, 0xfe, 0xb0, 0xd6, 0x8f, 0xcf, 0xae, 0xda, 0x32, 0x7c,
+       0x7e, 0x54, 0x5b, 0x83, 0xdf, 0x8f, 0xd6, 0x2e, 0xc5, 0xf2, 0xb1, 0xda,
+       0x20, 0x3e, 0x4f, 0xd4, 0xae, 0xc4, 0xe7, 0xc9, 0xda, 0x06, 0xfc, 0xde,
+       0x5d, 0xdb, 0x88, 0xe5, 0x33, 0xb5, 0x21, 0x7c, 0x6a, 0x72, 0xa0, 0xd9,
+       0xa3, 0x24, 0x85, 0xdb, 0x7f, 0xdc, 0x5e, 0xa7, 0x2b, 0x07, 0x96, 0xcf,
+       0xf2, 0x39, 0x88, 0xf4, 0xdf, 0x9d, 0x28, 0xd7, 0xde, 0x34, 0x90, 0xeb,
+       0xb3, 0xce, 0x2f, 0xc7, 0x80, 0x9d, 0x7b, 0xf6, 0x7d, 0x2b, 0x06, 0xd1,
+       0xe3, 0xe1, 0xc9, 0xcc, 0x6f, 0xf1, 0xe9, 0xe7, 0xc3, 0xf5, 0xbe, 0x24,
+       0x44, 0xe9, 0x9f, 0xdb, 0xff, 0xbb, 0xdd, 0xc1, 0xe8, 0x63, 0xb7, 0x90,
+       0x99, 0xe0, 0x9f, 0xad, 0x1a, 0xad, 0x10, 0x88, 0xab, 0x3b, 0x5e, 0xfe,
+       0x0e, 0xda, 0xcb, 0xf4, 0xbd, 0x44, 0x50, 0x5f, 0x86, 0xbc, 0xfa, 0x7d,
+       0xc4, 0xbe, 0xfe, 0x61, 0xce, 0x83, 0x2e, 0x4c, 0x27, 0xad, 0xfe, 0xb1,
+       0xc7, 0xff, 0x2b, 0x7f, 0x5e, 0x36, 0xd0, 0x87, 0xd1, 0xd7, 0x71, 0x50,
+       0xac, 0x61, 0x74, 0x7b, 0xda, 0x0b, 0x74, 0xd3, 0xe1, 0x8f, 0xd9, 0x65,
+       0x3b, 0xb9, 0x3e, 0x37, 0xe1, 0x51, 0xe2, 0x72, 0x67, 0xc6, 0xe7, 0xe9,
+       0x81, 0x1a, 0x3e, 0x3b, 0x33, 0x20, 0xde, 0x52, 0x25, 0x16, 0x59, 0x24,
+       0xfa, 0xee, 0x6c, 0xab, 0x15, 0xe7, 0x75, 0xb6, 0x3d, 0x81, 0xed, 0x63,
+       0x7b, 0x52, 0x2e, 0x2a, 0x9e, 0x57, 0xb1, 0xc5, 0xee, 0xd1, 0xeb, 0x87,
+       0xaa, 0x70, 0x92, 0xc7, 0xa8, 0x2f, 0x06, 0x7b, 0xf4, 0xfa, 0xe2, 0x6c,
+       0xc7, 0xd3, 0x6e, 0x90, 0xfb, 0x25, 0x69, 0x16, 0xcf, 0xd1, 0x5c, 0xe0,
+       0x0f, 0x1f, 0xe7, 0x0f, 0xc6, 0x77, 0x5a, 0xff, 0x55, 0xe1, 0x4c, 0x8f,
+       0xd3, 0xd0, 0x8f, 0xb1, 0x7c, 0xb6, 0x41, 0x98, 0xc9, 0xf6, 0x15, 0xd5,
+       0xc4, 0x9b, 0x62, 0xf8, 0x07, 0xda, 0x73, 0x49, 0x9a, 0xe2, 0x39, 0x4a,
+       0xf5, 0xc2, 0xc9, 0x2d, 0x23, 0x13, 0x61, 0x5c, 0xea, 0xc7, 0x79, 0x60,
+       0x9c, 0xee, 0x5a, 0x8f, 0x87, 0x8d, 0x9b, 0xe6, 0xd1, 0xf3, 0x65, 0xe5,
+       0x52, 0x07, 0xd6, 0xd7, 0xe0, 0x8b, 0xd7, 0xef, 0x3f, 0x1a, 0x3e, 0xd8,
+       0xf1, 0xfb, 0xd8, 0xc6, 0x62, 0x4d, 0x10, 0xa7, 0x89, 0x57, 0x3f, 0x2e,
+       0x3d, 0xa4, 0xcf, 0x15, 0xf0, 0x0f, 0x48, 0xbb, 0xfc, 0x25, 0xac, 0x3b,
+       0x8e, 0x2c, 0x6d, 0xdd, 0x91, 0xb0, 0xac, 0xf5, 0x1b, 0x08, 0x8b, 0x41,
+       0xeb, 0xe5, 0xf0, 0xbe, 0xc5, 0x30, 0x1e, 0x6d, 0xa7, 0x6a, 0x3e, 0x34,
+       0xb4, 0x8b, 0x4f, 0x77, 0x89, 0x1c, 0xd3, 0xe8, 0x49, 0xf5, 0xe4, 0x95,
+       0x3c, 0x3f, 0x84, 0x32, 0x33, 0xd2, 0xd9, 0x4f, 0x7b, 0x4c, 0xa4, 0xfd,
+       0xf5, 0x48, 0xce, 0x95, 0x10, 0xe7, 0xcd, 0x94, 0x54, 0xd4, 0x77, 0x01,
+       0x18, 0x88, 0xf2, 0x53, 0x95, 0xad, 0x4b, 0xf1, 0xab, 0x88, 0xee, 0x4e,
+       0x8c, 0x7b, 0x4e, 0xd4, 0xe4, 0x5e, 0xbd, 0xe5, 0x0f, 0x94, 0xe5, 0x3e,
+       0xf9, 0x37, 0x19, 0xe3, 0x19, 0xe4, 0xcf, 0xb4, 0x77, 0xfa, 0x5d, 0xe6,
+       0x5f, 0x17, 0x90, 0x22, 0x37, 0x38, 0x19, 0xf3, 0x5a, 0x2b, 0x66, 0x81,
+       0x9e, 0xfc, 0xc4, 0xa2, 0xd9, 0x03, 0x0d, 0xf9, 0x30, 0xef, 0xd3, 0xc4,
+       0x82, 0xfb, 0xf9, 0xa7, 0xc9, 0xdb, 0xee, 0x5c, 0x9d, 0x5d, 0x56, 0x26,
+       0xf1, 0xf8, 0xe4, 0x4a, 0xb6, 0x3e, 0x07, 0xe9, 0x7f, 0x30, 0x3f, 0x6a,
+       0xa7, 0x19, 0xd6, 0xeb, 0xd2, 0x46, 0x63, 0xb9, 0x84, 0xdc, 0x90, 0x0a,
+       0xf2, 0x50, 0xb2, 0x5e, 0x86, 0x1d, 0x5b, 0xb2, 0x08, 0xd6, 0x7b, 0xdd,
+       0xbe, 0xc9, 0x6c, 0xc9, 0x83, 0xf3, 0x2e, 0x25, 0x35, 0xf5, 0x60, 0xa7,
+       0xac, 0x96, 0xd9, 0x3e, 0xea, 0x3c, 0x0f, 0x91, 0x86, 0x52, 0xb8, 0xaa,
+       0x76, 0x3d, 0x99, 0x0f, 0xf6, 0x6c, 0x40, 0x62, 0xfa, 0x5e, 0xf3, 0x9f,
+       0x17, 0x25, 0x33, 0xb8, 0xcb, 0x53, 0x42, 0x8a, 0x8f, 0x7e, 0xff, 0xb8,
+       0x35, 0xf7, 0xe6, 0xef, 0x11, 0x68, 0x1f, 0xaa, 0x07, 0xbd, 0x16, 0x74,
+       0x11, 0x6f, 0xac, 0x78, 0xcc, 0xfc, 0x95, 0x46, 0xf8, 0x2e, 0x04, 0xbf,
+       0x19, 0x5e, 0x42, 0x96, 0x1b, 0xe0, 0xd0, 0xfa, 0xd5, 0xe0, 0x10, 0xb7,
+       0x08, 0x31, 0xf3, 0x34, 0x7e, 0x26, 0x09, 0x3c, 0xae, 0xc3, 0xe4, 0x63,
+       0xad, 0x64, 0xb4, 0x5f, 0x1f, 0xe1, 0x78, 0xd0, 0xca, 0x1b, 0x4c, 0xe5,
+       0x26, 0x53, 0x7d, 0x8d, 0x4f, 0x64, 0xce, 0x27, 0x99, 0x92, 0xff, 0x11,
+       0xd0, 0x3f, 0x55, 0xb6, 0xde, 0x42, 0xb4, 0xd3, 0x08, 0xe5, 0x8f, 0xec,
+       0x68, 0x3d, 0x25, 0x5a, 0x6f, 0xc3, 0xf9, 0xea, 0x59, 0xa1, 0x9e, 0x88,
+       0xf5, 0x9a, 0xa4, 0x09, 0xf1, 0xeb, 0xd9, 0xa3, 0xfd, 0x35, 0xc7, 0xea,
+       0xaf, 0x6a, 0xd7, 0xb6, 0x17, 0x83, 0x94, 0x9f, 0xca, 0x5f, 0x78, 0xd4,
+       0x0d, 0x41, 0xdf, 0x4f, 0xa4, 0x86, 0x54, 0x88, 0x7f, 0x55, 0x6e, 0xbe,
+       0xdf, 0x0d, 0x78, 0x3a, 0x21, 0x05, 0xdd, 0x40, 0xef, 0x4f, 0x42, 0x62,
+       0xcc, 0xb8, 0xe0, 0x7b, 0x7d, 0xf8, 0xf2, 0x39, 0x05, 0xf0, 0x23, 0x90,
+       0xb5, 0x29, 0xde, 0x9f, 0x7b, 0xf0, 0x5a, 0xd0, 0xd7, 0x5f, 0x6e, 0x96,
+       0x31, 0x2f, 0x26, 0xb0, 0xc5, 0x1a, 0xb1, 0x52, 0x3e, 0xae, 0x6e, 0x5d,
+       0x34, 0x0b, 0xe2, 0xf7, 0xb4, 0x7c, 0x84, 0x95, 0x1f, 0xf8, 0x14, 0xf6,
+       0x0d, 0x03, 0x6d, 0x46, 0x7a, 0x96, 0x3f, 0xfb, 0x68, 0x2a, 0xc4, 0x89,
+       0x28, 0x26, 0x99, 0xbd, 0x4d, 0x22, 0x68, 0x77, 0x54, 0x6f, 0xfa, 0x53,
+       0x21, 0xe8, 0xf1, 0x00, 0xe9, 0x45, 0x3e, 0x34, 0xb7, 0x83, 0xf1, 0xcf,
+       0x25, 0xa3, 0xdc, 0x17, 0x2b, 0x89, 0xfd, 0xbf, 0x6b, 0xf9, 0x0a, 0x01,
+       0x2e, 0x67, 0x81, 0xd6, 0x07, 0x3f, 0x85, 0xbc, 0x84, 0x80, 0x89, 0x7f,
+       0xca, 0xfa, 0xd6, 0x93, 0x2e, 0x05, 0xe2, 0x08, 0x1d, 0x92, 0x2b, 0x05,
+       0xfd, 0xf2, 0xef, 0x92, 0xef, 0x82, 0x1e, 0xd0, 0xf0, 0x41, 0x42, 0xcc,
+       0x9e, 0xa8, 0xdb, 0xba, 0x61, 0xdc, 0x11, 0x0a, 0x4f, 0xf7, 0xa6, 0x7f,
+       0x73, 0x0b, 0x06, 0xbf, 0x9b, 0xf1, 0xe1, 0xd9, 0xf0, 0xfc, 0x5f, 0xbd,
+       0xa4, 0xc6, 0xd7, 0x33, 0x67, 0xb8, 0x3f, 0x14, 0x6d, 0x17, 0xc2, 0x76,
+       0x6a, 0x1b, 0xb3, 0x7f, 0x48, 0x3b, 0x7b, 0x56, 0xca, 0x11, 0x37, 0xd8,
+       0x9b, 0x95, 0xcd, 0xb2, 0x97, 0x72, 0x28, 0xa9, 0xdc, 0xf6, 0xf4, 0x33,
+       0x8f, 0x83, 0x9f, 0xf6, 0x81, 0x15, 0xfd, 0xb4, 0x8a, 0x6d, 0xbf, 0x79,
+       0x77, 0x32, 0x2d, 0x57, 0x6c, 0x97, 0x53, 0x66, 0xb1, 0xe9, 0x38, 0x85,
+       0xd4, 0x28, 0x5d, 0x02, 0xf4, 0x7f, 0x4b, 0xc7, 0x47, 0xe9, 0x50, 0xfe,
+       0xeb, 0xdf, 0x28, 0xea, 0x58, 0xf6, 0xfe, 0xa7, 0xc9, 0x51, 0x7a, 0x54,
+       0x6c, 0xdf, 0xaf, 0x90, 0xb1, 0xfd, 0xf1, 0x37, 0x2d, 0xbc, 0x5f, 0xe9,
+       0x72, 0xc6, 0xa0, 0x4b, 0xf8, 0x48, 0x21, 0xd8, 0x2b, 0x75, 0x5b, 0xbf,
+       0x52, 0xc0, 0xef, 0xfa, 0x64, 0x9f, 0x40, 0x06, 0x65, 0xf6, 0x6f, 0x5f,
+       0xd6, 0xfc, 0x1b, 0x5c, 0x0f, 0x01, 0x4f, 0x48, 0x47, 0x4e, 0xa7, 0x3e,
+       0xba, 0xf5, 0xa3, 0x57, 0xe4, 0xda, 0x97, 0xf2, 0xb0, 0x9e, 0x07, 0xf4,
+       0x64, 0x3c, 0x7a, 0x3d, 0xc7, 0xf5, 0x72, 0xd5, 0x2e, 0x17, 0x49, 0x82,
+       0xf8, 0xe7, 0xef, 0xad, 0xa1, 0x59, 0x40, 0xc7, 0xe7, 0xef, 0x74, 0xc3,
+       0x3c, 0x8e, 0x4b, 0x35, 0x8c, 0xaf, 0x9f, 0xbc, 0x3f, 0x15, 0xf6, 0xff,
+       0xca, 0xe4, 0x60, 0xaa, 0x07, 0x9f, 0xec, 0x7d, 0xd9, 0x53, 0x77, 0x23,
+       0xbf, 0x95, 0x0a, 0x35, 0xa9, 0x6c, 0x1f, 0xd3, 0x37, 0x98, 0xc7, 0xcb,
+       0x07, 0xc3, 0xfc, 0x16, 0x36, 0xfd, 0x08, 0xe7, 0x57, 0x42, 0xfc, 0xc8,
+       0x77, 0x65, 0x4f, 0x8a, 0x45, 0x10, 0x1f, 0xfe, 0x42, 0x22, 0x33, 0xb7,
+       0xc7, 0x90, 0x8b, 0x6b, 0x64, 0xb6, 0xff, 0x74, 0x7c, 0xa3, 0x15, 0x92,
+       0xfc, 0xc8, 0x71, 0xb0, 0xf3, 0xc1, 0xbe, 0x7e, 0x5b, 0xc4, 0x38, 0x2b,
+       0x21, 0x8b, 0x71, 0x1f, 0xec, 0x6e, 0x2d, 0x8e, 0x4b, 0x96, 0x60, 0xf9,
+       0x0b, 0xbe, 0x2f, 0x35, 0x4a, 0xb6, 0x68, 0xfe, 0xa1, 0xcd, 0xc0, 0xaf,
+       0x9b, 0x1e, 0xe8, 0x04, 0xfa, 0x9c, 0x1c, 0xe6, 0x1b, 0x04, 0x70, 0x52,
+       0x3c, 0x04, 0x39, 0xbe, 0x04, 0xd8, 0xef, 0x17, 0x0f, 0xcf, 0x18, 0xc4,
+       0xe8, 0xc3, 0xf2, 0x0d, 0xb0, 0x1d, 0xd5, 0xff, 0xd3, 0xe0, 0x3d, 0xd4,
+       0xef, 0x94, 0x71, 0x9f, 0x50, 0xd7, 0x8e, 0xeb, 0x4b, 0x36, 0xfe, 0x5d,
+       0x7c, 0x7c, 0x0a, 0xb7, 0x03, 0xd6, 0xb3, 0xe3, 0xa9, 0x6c, 0xbf, 0xd2,
+       0x3c, 0xbf, 0xa5, 0x7c, 0x7e, 0xf4, 0xaf, 0x93, 0xe8, 0xf8, 0x4b, 0x27,
+       0xdf, 0x4c, 0xde, 0x37, 0xad, 0x62, 0xf2, 0xad, 0xc9, 0x7b, 0xe8, 0xfa,
+       0x99, 0xf0, 0xfd, 0xf3, 0x77, 0x98, 0xfc, 0x40, 0x3b, 0x58, 0x3f, 0x28,
+       0x5c, 0x91, 0x41, 0xf8, 0x7d, 0xff, 0x4d, 0x02, 0xea, 0x03, 0x2b, 0x89,
+       0xc4, 0x92, 0xeb, 0x4d, 0x32, 0x97, 0x6b, 0xe3, 0xf7, 0x00, 0x95, 0x53,
+       0x88, 0x0b, 0x50, 0xb8, 0x25, 0xc8, 0x67, 0x88, 0xf2, 0x09, 0xed, 0x3f,
+       0x19, 0xf1, 0x8f, 0x7e, 0x49, 0xc9, 0x7a, 0xda, 0x4e, 0x67, 0x9f, 0x05,
+       0x60, 0x3c, 0xac, 0xa7, 0x44, 0xdf, 0xeb, 0xd6, 0x8f, 0x52, 0xae, 0x07,
+       0x66, 0xca, 0x46, 0xf9, 0x27, 0x4d, 0x03, 0x2f, 0xca, 0x5e, 0xac, 0x94,
+       0x49, 0x10, 0x4c, 0xcb, 0xca, 0x0f, 0xac, 0xe8, 0x77, 0x57, 0x6e, 0x93,
+       0x8b, 0x60, 0xde, 0xa7, 0x5a, 0x0e, 0xbe, 0xfb, 0x63, 0xca, 0xd7, 0xa7,
+       0xc2, 0x9a, 0x9c, 0x1a, 0xf5, 0xa7, 0x59, 0x4e, 0xcb, 0x76, 0x6c, 0x16,
+       0x80, 0x3f, 0xcd, 0x72, 0x7a, 0xaa, 0x8c, 0xae, 0xd6, 0xb1, 0xe4, 0x94,
+       0xbe, 0x8f, 0x29, 0xa7, 0x65, 0x5d, 0xff, 0x57, 0xf4, 0xa7, 0x86, 0xb7,
+       0x80, 0x09, 0x6f, 0x54, 0x0f, 0x0e, 0x4f, 0xb2, 0xc4, 0xc7, 0x9f, 0x59,
+       0x0f, 0xba, 0x64, 0x35, 0xa6, 0x1e, 0xa4, 0x7f, 0xef, 0x90, 0xfc, 0xfe,
+       0x7c, 0xa7, 0xf1, 0x9b, 0xc6, 0x67, 0xd4, 0x42, 0x1b, 0x0e, 0xfa, 0xbb,
+       0x8f, 0x1f, 0x35, 0x7e, 0xeb, 0xe3, 0x47, 0x8d, 0xdf, 0xcc, 0xf3, 0x34,
+       0xe2, 0xcd, 0xfc, 0x7d, 0x32, 0x18, 0x6a, 0x14, 0xae, 0xa2, 0xdd, 0x32,
+       0xfa, 0x25, 0x95, 0xed, 0x6c, 0xff, 0x86, 0xb6, 0x7b, 0x75, 0x68, 0x1e,
+       0xe2, 0xc7, 0x87, 0xcb, 0x17, 0x69, 0x78, 0x75, 0x68, 0x8a, 0xbe, 0x1c,
+       0x32, 0x95, 0xc3, 0xa6, 0xfa, 0x3e, 0x53, 0xb9, 0xc8, 0x54, 0xdf, 0x6f,
+       0x2a, 0xd7, 0x18, 0xea, 0x57, 0xb6, 0x1d, 0x54, 0x58, 0x92, 0x51, 0xc4,
+       0x50, 0xcf, 0xba, 0xf4, 0x71, 0xf2, 0x71, 0x0c, 0xfb, 0x5e, 0x5b, 0x67,
+       0x02, 0xad, 0x9f, 0x2a, 0x41, 0xe0, 0x87, 0xf4, 0x5e, 0x05, 0xf4, 0x9c,
+       0xbc, 0x9c, 0x9a, 0x66, 0x10, 0x3f, 0xdb, 0x2b, 0xa2, 0xbf, 0xd5, 0xa3,
+       0xf6, 0xba, 0x93, 0xe9, 0xfb, 0xfb, 0xed, 0xcc, 0x8f, 0xed, 0xf1, 0xf0,
+       0x72, 0x12, 0x2b, 0xf7, 0x0e, 0x54, 0xea, 0x41, 0xcf, 0x69, 0xef, 0x7b,
+       0xed, 0x2c, 0xce, 0xd9, 0x53, 0xd4, 0xeb, 0x4e, 0xd2, 0xf9, 0xf7, 0x47,
+       0xda, 0x45, 0x37, 0xec, 0x07, 0x77, 0x85, 0x58, 0x3e, 0x6a, 0x7f, 0x78,
+       0xea, 0x50, 0x6e, 0xba, 0x48, 0xbc, 0xef, 0x2c, 0x2e, 0x38, 0x43, 0x74,
+       0x66, 0x2c, 0x05, 0xff, 0xad, 0x41, 0xf4, 0x82, 0x6b, 0xb8, 0x60, 0xd9,
+       0x2d, 0x6e, 0xd8, 0x77, 0xeb, 0x69, 0x1f, 0x79, 0xdd, 0x6c, 0xfa, 0x7e,
+       0xe1, 0x21, 0x11, 0xcc, 0x67, 0xd2, 0xe3, 0x70, 0x8f, 0x03, 0xb8, 0x48,
+       0xd0, 0x27, 0x0d, 0xce, 0xe7, 0xf9, 0x13, 0xf4, 0xef, 0x04, 0x09, 0xfe,
+       0x72, 0x0a, 0xe4, 0x4d, 0xb4, 0x33, 0xfb, 0x7a, 0xc1, 0x1a, 0x93, 0x3d,
+       0xec, 0xbc, 0x4b, 0xc1, 0xfc, 0xb2, 0xf5, 0xba, 0xb8, 0x96, 0x8e, 0xff,
+       0xcb, 0x79, 0x3f, 0x65, 0x4d, 0xc6, 0xef, 0xe5, 0x64, 0x0d, 0xf2, 0x5f,
+       0xb9, 0x49, 0x1e, 0xfc, 0xdc, 0x1f, 0x38, 0xac, 0xc9, 0x43, 0x0e, 0xc9,
+       0x61, 0xfb, 0xdb, 0x84, 0xf9, 0xb1, 0x5c, 0xef, 0xce, 0x10, 0xb3, 0xaf,
+       0x9b, 0x4d, 0xf1, 0xde, 0xd3, 0x21, 0x62, 0xde, 0xec, 0xd9, 0x76, 0x91,
+       0xd4, 0xc3, 0x3c, 0x5b, 0x04, 0xdc, 0xe7, 0x24, 0xc1, 0x81, 0x28, 0x57,
+       0xd5, 0xa4, 0x17, 0xf5, 0x9d, 0x86, 0x97, 0x6e, 0x90, 0x1b, 0x25, 0xbe,
+       0x3e, 0xea, 0xde, 0xf9, 0x1f, 0xf9, 0xf7, 0x01, 0x7f, 0xbc, 0xf8, 0x87,
+       0x71, 0x4f, 0xd0, 0x67, 0xf7, 0x8b, 0x1f, 0x8c, 0xd9, 0x03, 0xe5, 0x5d,
+       0xef, 0x65, 0xfc, 0x81, 0xf4, 0xaf, 0x3f, 0x6d, 0xdf, 0xd7, 0xb8, 0x8f,
+       0xd8, 0xb3, 0xcf, 0x8a, 0x71, 0xae, 0x9e, 0x7d, 0xaf, 0x65, 0xdc, 0x07,
+       0xe5, 0x97, 0xac, 0x18, 0xe7, 0xea, 0x59, 0x6e, 0xc5, 0x7d, 0x94, 0xe0,
+       0x3e, 0x57, 0x68, 0x34, 0x7c, 0x1f, 0xc6, 0xfc, 0x81, 0xba, 0xbd, 0x5f,
+       0x8d, 0x63, 0x79, 0x92, 0x2b, 0x90, 0x4e, 0x7f, 0x96, 0x99, 0x3f, 0x72,
+       0xb6, 0xfd, 0xbf, 0x3e, 0x84, 0xfc, 0x91, 0xb3, 0xed, 0x74, 0x56, 0x60,
+       0x17, 0xec, 0x4b, 0x40, 0xb9, 0x09, 0xbc, 0x64, 0x47, 0xff, 0xbb, 0x67,
+       0xef, 0x57, 0xf9, 0x7e, 0xe7, 0x3f, 0x6e, 0x3e, 0xd5, 0x0a, 0xf1, 0x23,
+       0xff, 0xb9, 0xc8, 0xec, 0x1d, 0xc0, 0xaf, 0x49, 0x2c, 0x1e, 0x1c, 0xd8,
+       0x33, 0xe9, 0x69, 0xc8, 0x6f, 0xae, 0x6a, 0xdd, 0xaf, 0x40, 0x9c, 0x7d,
+       0xda, 0xcb, 0x7f, 0x19, 0x07, 0x7a, 0xb2, 0x67, 0x07, 0xb3, 0x77, 0xce,
+       0xc8, 0x5d, 0x4f, 0xc1, 0x7e, 0x98, 0x55, 0xf9, 0x74, 0xb9, 0x4c, 0xf1,
+       0x7c, 0x06, 0x84, 0x67, 0x08, 0x21, 0x4f, 0x2b, 0xe3, 0xa7, 0x05, 0xb3,
+       0x63, 0xe1, 0x85, 0xe1, 0xa1, 0x87, 0xe2, 0x01, 0xe6, 0x45, 0xf1, 0x52,
+       0x06, 0xfa, 0x3d, 0x1e, 0x3e, 0x32, 0x94, 0x7f, 0x56, 0x7c, 0x7c, 0x7a,
+       0x3b, 0xd3, 0x63, 0xdf, 0xc5, 0x3c, 0xfb, 0x28, 0x5e, 0x04, 0x1f, 0x7b,
+       0xef, 0x0a, 0xd9, 0x04, 0x9c, 0x3f, 0x7b, 0xbf, 0xef, 0xab, 0x71, 0xa0,
+       0x67, 0x4e, 0x85, 0x97, 0xa1, 0x3d, 0x72, 0xa1, 0x79, 0x5f, 0xa1, 0xb0,
+       0x7d, 0x96, 0xff, 0x39, 0xf3, 0x16, 0x22, 0x17, 0x33, 0xef, 0xb9, 0xff,
+       0xb4, 0xf4, 0x66, 0xfc, 0xff, 0x11, 0xac, 0xaf, 0x03, 0xfb, 0xcb, 0x41,
+       0x7f, 0x3e, 0xdf, 0x75, 0x0f, 0x96, 0x9f, 0x77, 0x79, 0x11, 0xde, 0x8b,
+       0x94, 0xff, 0x9f, 0xfe, 0x4f, 0xa3, 0xfb, 0x0e, 0x4a, 0x77, 0xf7, 0x85,
+       0xe9, 0xfe, 0xc4, 0x3f, 0xed, 0xbc, 0x2f, 0x44, 0xf7, 0x43, 0x9c, 0xee,
+       0x2e, 0x0f, 0xec, 0x2f, 0xf7, 0xec, 0xfd, 0x0b, 0xc6, 0x4d, 0xb5, 0xf9,
+       0x5f, 0x68, 0xde, 0x2f, 0xfd, 0x3f, 0x3a, 0x6f, 0xcd, 0x5e, 0x7f, 0xcd,
+       0xa2, 0xbe, 0x93, 0x43, 0xeb, 0x1f, 0x22, 0x0d, 0xef, 0x8c, 0x11, 0x20,
+       0x7f, 0xf1, 0xe0, 0x61, 0x38, 0x02, 0x56, 0x20, 0x90, 0xa2, 0x58, 0xf6,
+       0xc8, 0x49, 0x85, 0xc5, 0x3f, 0x0a, 0x04, 0x96, 0x27, 0x48, 0x92, 0x04,
+       0xee, 0xdf, 0x31, 0xbf, 0x68, 0x28, 0xb7, 0x13, 0x86, 0xde, 0x55, 0x82,
+       0x76, 0xc6, 0xd0, 0xf4, 0xb5, 0x68, 0x1f, 0x10, 0x49, 0x5d, 0x0f, 0xfb,
+       0x71, 0xaf, 0x65, 0xcc, 0xf7, 0xb2, 0x7c, 0xb0, 0xf1, 0x78, 0x0e, 0xe5,
+       0x35, 0xcf, 0x15, 0xbc, 0x6c, 0xf4, 0x0f, 0x9f, 0x10, 0x88, 0x0f, 0xf2,
+       0x86, 0x87, 0x66, 0xfc, 0xb0, 0x03, 0xec, 0xd5, 0xf4, 0x74, 0x11, 0xed,
+       0x59, 0xfa, 0x44, 0x3b, 0xf6, 0x15, 0xf7, 0x4c, 0xf6, 0xbe, 0x52, 0x31,
+       0xf8, 0x45, 0x57, 0x11, 0x5d, 0x99, 0xce, 0xab, 0x30, 0xc5, 0xe8, 0xff,
+       0x4c, 0xe7, 0xfd, 0xcd, 0x20, 0x23, 0xde, 0xc9, 0xa1, 0xf0, 0xcf, 0xb0,
+       0xc9, 0x9e, 0x10, 0x45, 0xd1, 0x55, 0x53, 0xfd, 0x12, 0xcc, 0xe7, 0xaa,
+       0xc1, 0x02, 0x69, 0xd0, 0xed, 0x07, 0x4d, 0x37, 0xf9, 0x49, 0xaf, 0x82,
+       0x5f, 0xab, 0x8b, 0x97, 0xfd, 0xad, 0xf8, 0x4b, 0xb7, 0x32, 0x3f, 0xb2,
+       0x40, 0x18, 0xb1, 0xbe, 0x08, 0xf0, 0x37, 0x4c, 0xc4, 0x78, 0xe0, 0x05,
+       0xf1, 0x47, 0x58, 0xfe, 0xd7, 0x6b, 0x9e, 0x1c, 0x96, 0xd7, 0x2a, 0x79,
+       0x19, 0xfe, 0x92, 0xab, 0xbc, 0x18, 0x4f, 0xe5, 0x7e, 0x33, 0x84, 0x05,
+       0xc0, 0x5e, 0x91, 0x9c, 0xf5, 0x9d, 0x20, 0xb7, 0x12, 0xa1, 0x7e, 0x2f,
+       0x83, 0x1f, 0xfd, 0x65, 0xcd, 0xef, 0x8d, 0x87, 0x67, 0xc2, 0xfd, 0x68,
+       0x89, 0x0f, 0xa9, 0xe1, 0x5d, 0x4a, 0x17, 0x31, 0x5f, 0x55, 0xd7, 0x1f,
+       0xe2, 0x43, 0xa3, 0xc7, 0xdf, 0x4a, 0x07, 0x8d, 0x7e, 0x7f, 0x2f, 0x3d,
+       0xce, 0x98, 0xe8, 0x91, 0xfe, 0xb9, 0x47, 0x02, 0xf9, 0x9c, 0xc6, 0xed,
+       0xff, 0xe9, 0x9f, 0x77, 0x8a, 0x58, 0x4e, 0xf7, 0x4a, 0xb8, 0x1f, 0xc5,
+       0xed, 0xff, 0xa9, 0xce, 0x24, 0x09, 0xec, 0xff, 0x2b, 0xa4, 0xc3, 0x22,
+       0xc8, 0x65, 0xa9, 0xad, 0xed, 0x6a, 0x88, 0xd3, 0xdb, 0xbc, 0x02, 0xf2,
+       0xf5, 0x25, 0xdd, 0x16, 0xf4, 0x6f, 0x6c, 0x79, 0x02, 0xe2, 0x3d, 0xab,
+       0x51, 0xc2, 0xf2, 0x61, 0x8b, 0x67, 0x02, 0x18, 0xda, 0xd7, 0x7e, 0x6f,
+       0xd7, 0xa9, 0x7b, 0x09, 0xc4, 0x87, 0x7d, 0x0a, 0x1a, 0xde, 0xa4, 0x88,
+       0xc5, 0xe7, 0xff, 0xfc, 0xed, 0xb7, 0x53, 0xb4, 0xf3, 0x1a, 0xf8, 0x9d,
+       0x90, 0x6b, 0xa8, 0xff, 0xb5, 0xa0, 0x89, 0x44, 0x1c, 0x14, 0x4f, 0x0b,
+       0x25, 0x12, 0x4c, 0x4c, 0x86, 0xf8, 0xae, 0x40, 0x3e, 0x32, 0xc4, 0x77,
+       0x8d, 0x65, 0xf8, 0xfb, 0x7e, 0x6a, 0xb4, 0x9f, 0x0b, 0xd5, 0x8f, 0xa7,
+       0x47, 0xfe, 0xd1, 0xcf, 0x5d, 0x54, 0x6f, 0x7d, 0x44, 0x99, 0x63, 0x37,
+       0x3c, 0x71, 0x5f, 0x85, 0xb2, 0x84, 0xce, 0x3f, 0xfe, 0x6e, 0x3b, 0xc3,
+       0x57, 0xe0, 0x75, 0x12, 0x1a, 0x81, 0x71, 0x05, 0x9f, 0x58, 0xa4, 0xdb,
+       0x37, 0x7b, 0xd0, 0xca, 0xf4, 0xc7, 0xae, 0x3f, 0xee, 0xc8, 0x85, 0xb8,
+       0xd8, 0xd4, 0x9e, 0xec, 0x44, 0xa6, 0x4f, 0x47, 0xa1, 0x5f, 0x10, 0xe0,
+       0x7e, 0xc1, 0x59, 0xa2, 0x26, 0x42, 0xfe, 0xc1, 0xd9, 0xf6, 0x91, 0x89,
+       0xb8, 0x2f, 0xd8, 0x21, 0xba, 0xfc, 0x31, 0xe2, 0x32, 0x5b, 0xb9, 0xff,
+       0xfc, 0xaf, 0x90, 0x4f, 0x41, 0x9f, 0x3d, 0x9b, 0x48, 0x03, 0x9c, 0xc3,
+       0xe8, 0x21, 0xbd, 0x18, 0x8f, 0x0d, 0x6e, 0xb2, 0xc5, 0xdc, 0xdf, 0xbd,
+       0xc7, 0xaa, 0xc5, 0x9b, 0x38, 0xdd, 0xe8, 0x9f, 0xa8, 0x9d, 0x37, 0x52,
+       0x31, 0x5f, 0x24, 0x98, 0xa8, 0xa7, 0x5b, 0xf7, 0xac, 0x4f, 0xa4, 0x71,
+       0xfd, 0xe9, 0x00, 0x7f, 0x1f, 0xe9, 0xf6, 0x4b, 0xfe, 0x5e, 0xfc, 0x82,
+       0xbf, 0x0e, 0xf8, 0xdd, 0x6a, 0xef, 0x2a, 0x8c, 0x75, 0x1e, 0x6c, 0x25,
+       0xc7, 0xdf, 0xb5, 0x07, 0xbe, 0xc6, 0x38, 0xe6, 0x65, 0xed, 0xcd, 0x16,
+       0xe0, 0xdf, 0xcb, 0x36, 0x59, 0x0c, 0xfb, 0x8d, 0x41, 0x2b, 0xf7, 0xbb,
+       0xc6, 0x93, 0xf1, 0x00, 0xd7, 0xb5, 0x07, 0xec, 0xae, 0x3c, 0xa0, 0x4b,
+       0x87, 0xe8, 0x85, 0xfc, 0xc1, 0x40, 0xfb, 0xa7, 0x8a, 0x3f, 0xc6, 0xbe,
+       0x95, 0x19, 0x9f, 0xd0, 0x3f, 0xc4, 0xc5, 0xf7, 0x59, 0x59, 0x9c, 0x7f,
+       0x8f, 0x1c, 0x9e, 0x0f, 0x78, 0xdd, 0x73, 0xda, 0x86, 0xf9, 0x39, 0xbb,
+       0x95, 0x86, 0x8a, 0x58, 0x70, 0x5e, 0x62, 0x67, 0x7a, 0x6e, 0x21, 0x09,
+       0xdf, 0x39, 0x2e, 0xf3, 0x9f, 0x0f, 0xbf, 0x53, 0x7b, 0x9c, 0x91, 0x02,
+       0xf0, 0x33, 0x37, 0x11, 0x1e, 0xc7, 0x30, 0xf3, 0x1f, 0x41, 0x3e, 0x3e,
+       0xbb, 0x85, 0xe0, 0xf9, 0x50, 0xf0, 0x4b, 0x41, 0x2f, 0x9c, 0x6d, 0x61,
+       0xe7, 0x80, 0x29, 0x4a, 0xd6, 0x82, 0x3f, 0x4d, 0xe5, 0xfd, 0x07, 0xfa,
+       0xb8, 0xcc, 0x25, 0x6d, 0xdb, 0xff, 0x15, 0xec, 0x80, 0xea, 0x76, 0xc1,
+       0x03, 0xa9, 0xb3, 0xd5, 0x52, 0x97, 0x02, 0xf1, 0xd6, 0x40, 0x5b, 0x92,
+       0x08, 0xeb, 0x6e, 0x8e, 0xaa, 0xe5, 0x55, 0x7a, 0xc6, 0xde, 0xa4, 0x93,
+       0x8b, 0x7d, 0x56, 0x96, 0x6f, 0x7c, 0x70, 0xf2, 0x9e, 0x5b, 0x61, 0xdc,
+       0xcf, 0xba, 0x15, 0x02, 0xf6, 0x88, 0xef, 0x95, 0x5e, 0x37, 0xac, 0xdb,
+       0x9f, 0xb5, 0xe7, 0x26, 0xc6, 0xca, 0x9b, 0xd7, 0x9e, 0xbf, 0xae, 0x25,
+       0x57, 0x4f, 0x97, 0xa0, 0x1f, 0x82, 0x78, 0x37, 0xf3, 0x43, 0x76, 0x8b,
+       0xc3, 0x50, 0xfe, 0x9e, 0xe8, 0x1f, 0x02, 0xf2, 0x75, 0xad, 0xb5, 0xeb,
+       0x2e, 0x6f, 0x0c, 0xfa, 0xf9, 0x6d, 0x8c, 0xcf, 0x2e, 0x5a, 0xbf, 0x85,
+       0xfe, 0x3f, 0xd3, 0x6f, 0xef, 0x68, 0xfa, 0xcd, 0x2f, 0x16, 0xe9, 0xe4,
+       0x28, 0xcb, 0xd6, 0x4f, 0xbf, 0x0d, 0x8a, 0xa5, 0xdf, 0x96, 0x08, 0xea,
+       0x20, 0xc0, 0xfb, 0x92, 0xbd, 0x23, 0x07, 0x01, 0x5d, 0x97, 0x1c, 0x92,
+       0x07, 0xc6, 0xd2, 0x6f, 0xdb, 0x6a, 0xd9, 0x7e, 0xde, 0x0b, 0x3c, 0x1f,
+       0xb6, 0xa7, 0x95, 0xea, 0xb7, 0xcb, 0x75, 0xfa, 0xad, 0xd5, 0x86, 0x79,
+       0x71, 0xe6, 0x76, 0xc9, 0x36, 0x0b, 0x5f, 0x17, 0x2f, 0xa0, 0xdf, 0x42,
+       0xff, 0x3d, 0xf2, 0xb7, 0x0d, 0xf4, 0x5b, 0x8c, 0xf9, 0x8e, 0xb6, 0x31,
+       0xbd, 0xa1, 0xe9, 0xb7, 0x71, 0xed, 0x47, 0x50, 0xbf, 0x8d, 0x6b, 0xb5,
+       0x18, 0xf2, 0x46, 0xd3, 0x6d, 0x17, 0xd2, 0x6f, 0xc2, 0xc0, 0x9b, 0xc0,
+       0x1e, 0xee, 0x90, 0xbd, 0x09, 0x31, 0xf8, 0x67, 0x1b, 0xb7, 0xbf, 0x5f,
+       0xe0, 0x79, 0x78, 0x30, 0x0e, 0xe8, 0xb9, 0x5b, 0x6d, 0x6c, 0x7f, 0xf3,
+       0x62, 0xf5, 0x5c, 0xb6, 0x9d, 0xd1, 0xfb, 0x82, 0x7a, 0xee, 0xbf, 0x09,
+       0xcf, 0x9a, 0x9e, 0x5b, 0xb2, 0x53, 0x3b, 0xe7, 0x68, 0xe6, 0x43, 0xa6,
+       0xe7, 0x96, 0xec, 0xa6, 0x7a, 0x4e, 0x00, 0x7e, 0x64, 0x7a, 0x6e, 0xc9,
+       0x5e, 0x76, 0x8f, 0x83, 0x59, 0xbf, 0x65, 0xf5, 0xd3, 0x6f, 0x04, 0xeb,
+       0x57, 0x47, 0x58, 0xfb, 0x40, 0x5b, 0xe6, 0x86, 0xb9, 0xb4, 0xbf, 0xf1,
+       0x3e, 0xd9, 0x6b, 0xa3, 0xf5, 0xc7, 0x47, 0xf5, 0xdd, 0x04, 0xbd, 0xbe,
+       0xbb, 0xd5, 0xc6, 0xee, 0x5d, 0xe8, 0xa7, 0xef, 0x3a, 0x2e, 0x4e, 0xdf,
+       0xed, 0xe4, 0xfa, 0x8e, 0xea, 0xb1, 0x11, 0xa0, 0x5f, 0xcd, 0xfc, 0xe1,
+       0x6d, 0x37, 0xe6, 0x1d, 0xef, 0x99, 0x74, 0xbc, 0xe5, 0xd7, 0x20, 0x2f,
+       0x6f, 0x88, 0xb8, 0x6f, 0x78, 0x98, 0x9f, 0x4b, 0x7b, 0x73, 0xd2, 0xf1,
+       0x3c, 0xe0, 0xaf, 0x16, 0x1b, 0xd3, 0xbf, 0x75, 0x9c, 0xff, 0xce, 0xd4,
+       0x06, 0xb1, 0xff, 0x69, 0xaf, 0xb0, 0xf9, 0x55, 0x39, 0x59, 0x3e, 0x72,
+       0x75, 0x2b, 0xb3, 0x0f, 0xab, 0x5b, 0x84, 0x90, 0x4a, 0xff, 0x59, 0x38,
+       0xf9, 0x6b, 0x05, 0xe0, 0x5f, 0xb4, 0x57, 0x20, 0x83, 0x68, 0xf9, 0x7a,
+       0x2b, 0xab, 0x4f, 0x9e, 0xd5, 0xf6, 0xbd, 0xc8, 0xac, 0x1c, 0x1d, 0x3f,
+       0x2c, 0x98, 0x58, 0x81, 0x71, 0xfb, 0x05, 0x12, 0xb1, 0x41, 0x5c, 0xbe,
+       0xc2, 0x59, 0xf8, 0x09, 0xd8, 0xbf, 0x15, 0x13, 0x59, 0x1c, 0xbf, 0x82,
+       0xbf, 0x5f, 0x74, 0xa8, 0xab, 0x1e, 0xe2, 0xd9, 0x8b, 0x1e, 0x13, 0x70,
+       0xdf, 0x93, 0xf0, 0x7c, 0x00, 0x2d, 0xbf, 0xb1, 0xb4, 0x7d, 0x19, 0xc6,
+       0x6b, 0xcd, 0x79, 0x01, 0x9a, 0x3e, 0x5f, 0x14, 0x32, 0xbe, 0xaf, 0x30,
+       0xe5, 0x33, 0x36, 0xf3, 0x79, 0x5e, 0x2f, 0x76, 0x21, 0x5e, 0xc8, 0x5b,
+       0x62, 0xcc, 0xbc, 0x84, 0x66, 0x33, 0x3e, 0x3a, 0x38, 0x3e, 0x36, 0x89,
+       0xb8, 0x6e, 0xf6, 0xe1, 0x83, 0xe2, 0x47, 0xcd, 0xec, 0x8f, 0x0f, 0x4a,
+       0xd1, 0x59, 0x39, 0xa9, 0xd1, 0xf9, 0x2f, 0x7a, 0x83, 0xce, 0x2b, 0x2f,
+       0x3a, 0x2f, 0x0d, 0x1f, 0xe6, 0xf9, 0x69, 0x71, 0xe7, 0x0a, 0xde, 0x2e,
+       0xde, 0x7c, 0x35, 0xfc, 0xf5, 0x9b, 0xaf, 0x86, 0x4f, 0xd3, 0xbc, 0x9f,
+       0x06, 0xbd, 0x01, 0x0a, 0x21, 0x87, 0xe4, 0x42, 0x5e, 0x0c, 0xe5, 0x03,
+       0xd4, 0x1b, 0xc1, 0xdf, 0x8a, 0x78, 0x7e, 0xbf, 0x68, 0xea, 0xe8, 0x41,
+       0x7a, 0x3d, 0xbc, 0x95, 0xeb, 0xf3, 0xdc, 0x86, 0xa9, 0xd3, 0x06, 0x13,
+       0xc0, 0x17, 0xa9, 0x01, 0xbe, 0x29, 0x69, 0x5c, 0xfc, 0xea, 0x60, 0x3a,
+       0xef, 0x09, 0xef, 0xab, 0xe3, 0x61, 0x79, 0xfc, 0xde, 0x64, 0xab, 0x1f,
+       0xf6, 0x47, 0xb7, 0xda, 0x7b, 0x51, 0xaf, 0x69, 0x7c, 0xf5, 0x0d, 0xe7,
+       0xab, 0x77, 0x39, 0x1e, 0xf7, 0x0c, 0xa9, 0xc1, 0x73, 0xaa, 0x81, 0x36,
+       0xc1, 0x03, 0x76, 0x45, 0x20, 0x62, 0x47, 0xfc, 0x05, 0x28, 0xfe, 0xe0,
+       0xfc, 0x4a, 0x80, 0x9f, 0x5f, 0x0c, 0x50, 0xfe, 0x02, 0x79, 0x3a, 0xf8,
+       0xd8, 0x97, 0x0c, 0x5f, 0x7b, 0x05, 0x15, 0xe2, 0xe3, 0x85, 0xda, 0xfa,
+       0x03, 0xf8, 0xa7, 0xf5, 0x73, 0xdb, 0x19, 0xfe, 0x03, 0x21, 0x01, 0xf1,
+       0x9f, 0x47, 0x7a, 0x71, 0x7f, 0xa4, 0xba, 0x51, 0xf0, 0x46, 0x68, 0xfd,
+       0xea, 0xb6, 0xc5, 0x98, 0xf7, 0xa0, 0xe9, 0x5b, 0xfa, 0xe7, 0xd4, 0xd3,
+       0x43, 0xc7, 0x8f, 0x52, 0x2c, 0x7e, 0xc4, 0x4a, 0xba, 0xf5, 0xaf, 0x82,
+       0xd7, 0xbb, 0xd6, 0xda, 0xf0, 0x2e, 0xf0, 0xe7, 0xb5, 0xcf, 0xca, 0xa4,
+       0x59, 0xc7, 0x9f, 0x59, 0xf4, 0xbf, 0x6f, 0x63, 0xd0, 0x49, 0xc3, 0xe7,
+       0x85, 0xf8, 0xf2, 0x1c, 0xc7, 0xd3, 0x36, 0xc0, 0xa3, 0x13, 0xf0, 0xd5,
+       0xcb, 0xec, 0xa7, 0xc8, 0xd7, 0x78, 0x8e, 0x46, 0xfb, 0x1e, 0x90, 0x82,
+       0x06, 0x3c, 0x4e, 0x7b, 0xfc, 0xdc, 0x79, 0xf1, 0x34, 0x41, 0xc3, 0x13,
+       0xf0, 0x29, 0xe8, 0xa9, 0xf6, 0x62, 0x11, 0xca, 0x25, 0x6d, 0x02, 0x19,
+       0x90, 0xd9, 0x7f, 0x9e, 0xb0, 0x3f, 0xa9, 0x97, 0xdb, 0x45, 0x7b, 0x8f,
+       0xb0, 0xfe, 0x9f, 0x14, 0xf0, 0xde, 0x12, 0x33, 0xdf, 0x6a, 0xf3, 0xee,
+       0xc7, 0xb7, 0x71, 0xf8, 0x15, 0xce, 0xa5, 0x81, 0x5f, 0x74, 0xb1, 0x7c,
+       0xfb, 0x8d, 0x89, 0x6f, 0xdf, 0xb4, 0xf7, 0xbe, 0x9e, 0x0b, 0x7c, 0xbb,
+       0x57, 0x60, 0xf1, 0x83, 0xf6, 0x24, 0xc3, 0xfe, 0xe2, 0x10, 0x3b, 0x5b,
+       0xff, 0xb7, 0xda, 0x29, 0x7f, 0xc3, 0xbe, 0xd6, 0x21, 0xd9, 0xbb, 0x51,
+       0xed, 0x2f, 0xdf, 0x09, 0x7c, 0xfd, 0x02, 0xbb, 0x5f, 0x7f, 0x2e, 0xe9,
+       0x52, 0x98, 0x08, 0xe4, 0x3d, 0x6e, 0xb1, 0x61, 0x1e, 0x19, 0xc2, 0x31,
+       0x82, 0xd9, 0x95, 0x7a, 0xbd, 0xba, 0xcd, 0x4e, 0x06, 0xde, 0x94, 0x17,
+       0xbf, 0xff, 0xc1, 0xbc, 0xff, 0x78, 0x76, 0x8d, 0x56, 0x1e, 0x0b, 0xe3,
+       0x41, 0xbe, 0x57, 0x1b, 0x1d, 0x2f, 0x2b, 0x3a, 0x9e, 0x59, 0xaf, 0x6b,
+       0x7e, 0xfe, 0x85, 0xe6, 0x35, 0xe6, 0xef, 0x9c, 0x57, 0x5f, 0x1e, 0x26,
+       0xe9, 0xc4, 0x7d, 0xa7, 0x4c, 0xc9, 0xff, 0xb0, 0x55, 0x97, 0x07, 0x77,
+       0x33, 0xcf, 0x33, 0xa2, 0x10, 0xa0, 0x7d, 0xa5, 0xab, 0x97, 0x6d, 0x3b,
+       0x4f, 0x3d, 0x92, 0xe6, 0xc1, 0xf3, 0x4f, 0x77, 0x7a, 0x34, 0x3e, 0x63,
+       0xf9, 0xee, 0x45, 0x3c, 0x8f, 0x7d, 0x86, 0x38, 0xe5, 0x3d, 0x58, 0x3f,
+       0x3f, 0xf3, 0xb1, 0x7d, 0xbe, 0x3c, 0x0b, 0xf9, 0xdd, 0x14, 0xd0, 0xcf,
+       0x05, 0x32, 0x9e, 0xe3, 0xfb, 0xec, 0x75, 0x19, 0xe3, 0xb5, 0x9f, 0x4d,
+       0x67, 0x79, 0x9c, 0xd7, 0xbd, 0x71, 0x50, 0x82, 0x38, 0xcd, 0x75, 0xa0,
+       0x9c, 0x28, 0x3e, 0xae, 0x9b, 0x20, 0xa0, 0xbf, 0x02, 0xc7, 0xb0, 0x60,
+       0xdf, 0x6c, 0x17, 0xb5, 0x6f, 0x7c, 0x63, 0x70, 0x3e, 0xb9, 0x70, 0x8e,
+       0x2b, 0x67, 0x53, 0xc3, 0x34, 0x38, 0x7f, 0x3c, 0x7e, 0x4b, 0xa8, 0x0e,
+       0x9e, 0xde, 0x69, 0xbd, 0x29, 0x6f, 0x02, 0x1e, 0xa7, 0x8a, 0x04, 0xf0,
+       0xd8, 0xe9, 0x1b, 0x30, 0x0d, 0xee, 0x4f, 0xba, 0xf3, 0x4f, 0x04, 0xef,
+       0x0f, 0xa1, 0xeb, 0x2c, 0xb6, 0x1f, 0xdf, 0x41, 0x06, 0x42, 0xbd, 0xc9,
+       0xbe, 0x81, 0xe8, 0x0e, 0x4c, 0x6a, 0x5d, 0x3f, 0x0d, 0xe2, 0xa3, 0xd7,
+       0x1f, 0x74, 0x3a, 0xe1, 0x7e, 0x96, 0xac, 0x26, 0x0b, 0xf5, 0x19, 0xa2,
+       0xf8, 0x9b, 0x4c, 0x42, 0x75, 0xb0, 0xdf, 0x3e, 0xe9, 0xa8, 0xef, 0x46,
+       0x80, 0xb7, 0x8c, 0xda, 0x0b, 0x10, 0x77, 0x2e, 0x6b, 0x6f, 0xae, 0x73,
+       0x43, 0xb9, 0x49, 0xf0, 0xaa, 0xb4, 0xff, 0x40, 0xd0, 0x5f, 0xe8, 0xa6,
+       0xf3, 0xd8, 0xd6, 0xf8, 0x69, 0xe1, 0x77, 0x40, 0x1e, 0x69, 0x3d, 0xe8,
+       0x26, 0xd0, 0xc4, 0xea, 0x05, 0x36, 0xc1, 0xc5, 0x43, 0xf0, 0x7e, 0x1d,
+       0xe6, 0xd9, 0x94, 0x6c, 0x12, 0xf0, 0xe0, 0xd7, 0xb6, 0x90, 0x40, 0x6c,
+       0xac, 0xdf, 0x90, 0x8d, 0xf6, 0xbb, 0xad, 0x89, 0xb6, 0xcf, 0x83, 0x75,
+       0x82, 0xb6, 0x87, 0x7e, 0x37, 0x7d, 0xfa, 0xce, 0x8d, 0x20, 0xef, 0xaf,
+       0x8b, 0xac, 0x7d, 0x0b, 0xdb, 0xa7, 0x2e, 0xa1, 0xed, 0x54, 0xe0, 0xdb,
+       0x4d, 0x8b, 0xb1, 0xbf, 0x45, 0x4d, 0x02, 0x49, 0xa3, 0xfd, 0x95, 0xb5,
+       0xb0, 0x75, 0xa0, 0xec, 0x75, 0xd9, 0x0b, 0xdf, 0x5b, 0xf7, 0x3f, 0x86,
+       0xeb, 0xd8, 0x2c, 0x3a, 0xde, 0xe0, 0x4c, 0xd0, 0xfb, 0x91, 0xe9, 0x50,
+       0x26, 0xb9, 0x82, 0x07, 0xcf, 0xa1, 0x54, 0x8e, 0x41, 0xba, 0xf5, 0x70,
+       0x39, 0x27, 0x53, 0x46, 0x33, 0xfd, 0x21, 0xf0, 0x32, 0xf7, 0x1b, 0x34,
+       0xbb, 0xe9, 0x5d, 0x3b, 0xcb, 0xf7, 0x2d, 0xf1, 0x2e, 0x53, 0x06, 0xd0,
+       0x7e, 0xde, 0x9c, 0x38, 0x30, 0x13, 0xd2, 0x02, 0x02, 0x6d, 0x9f, 0xe2,
+       0xfe, 0xf3, 0x51, 0x8a, 0x67, 0x3f, 0xed, 0xf2, 0x30, 0xcf, 0xdb, 0x38,
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+       0x2d, 0x68, 0x9b, 0x8a, 0xf9, 0x0c, 0x0b, 0x49, 0x11, 0xe6, 0x33, 0x5c,
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+       0xcc, 0xeb, 0xa9, 0x5b, 0xc6, 0xf3, 0x80, 0x7e, 0xe6, 0xc5, 0x7b, 0x45,
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+       0xf8, 0x76, 0xb5, 0x56, 0xf6, 0xff, 0x54, 0x34, 0xc4, 0x33, 0xaa, 0xad,
+       0xbd, 0x1f, 0x82, 0x7d, 0x4e, 0x5e, 0xb6, 0xe3, 0x7e, 0xb8, 0xb8, 0xcf,
+       0x1e, 0xc4, 0xf8, 0xd8, 0x53, 0xec, 0x5e, 0x8d, 0x83, 0x3b, 0xbf, 0x7a,
+       0x06, 0xef, 0xe5, 0xf9, 0x95, 0x95, 0x70, 0xbb, 0x50, 0x00, 0x7d, 0x50,
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+       0xbd, 0xdf, 0xb3, 0x23, 0x71, 0x1c, 0xc4, 0x01, 0x4a, 0x5f, 0xbe, 0xef,
+       0x5a, 0xd0, 0x17, 0xa5, 0xa0, 0xfb, 0xc0, 0xce, 0x7c, 0x61, 0x50, 0xa8,
+       0x8e, 0xf6, 0x77, 0x6c, 0x20, 0x2b, 0x1f, 0xdb, 0x36, 0x0c, 0xcf, 0x05,
+       0x54, 0xec, 0x70, 0x61, 0x3e, 0xe1, 0xc1, 0x9d, 0xbb, 0xaa, 0x41, 0xdf,
+       0x9f, 0x79, 0x21, 0x81, 0x80, 0xbe, 0x3f, 0x2d, 0x77, 0xfd, 0x15, 0xca,
+       0x81, 0x3d, 0x89, 0xa4, 0x59, 0x45, 0xbb, 0x4f, 0xd5, 0xaf, 0xab, 0x8b,
+       0x88, 0xa4, 0xea, 0xed, 0xb9, 0x0a, 0x28, 0x1b, 0xf2, 0x5b, 0x08, 0xe6,
+       0xb7, 0x60, 0xfc, 0x8d, 0xf2, 0x73, 0x45, 0x5b, 0x22, 0x9e, 0xff, 0xd0,
+       0xd5, 0xe3, 0xf2, 0x1c, 0x1c, 0xc2, 0xef, 0x89, 0x1a, 0x02, 0x72, 0x47,
+       0xed, 0x46, 0xd5, 0x98, 0xf7, 0xcc, 0xbe, 0x2f, 0x48, 0x60, 0xfa, 0x2b,
+       0x60, 0xed, 0xbd, 0x87, 0xdd, 0x87, 0xc0, 0xea, 0x07, 0x94, 0xde, 0x12,
+       0x56, 0x6e, 0x18, 0xc2, 0xe4, 0xb6, 0x13, 0xeb, 0x2f, 0xd6, 0xf8, 0x95,
+       0x7f, 0xef, 0xdf, 0x2f, 0xab, 0x1f, 0x48, 0x60, 0xf1, 0x80, 0x68, 0x3f,
+       0xac, 0x7d, 0xb5, 0x95, 0xdd, 0xaf, 0x61, 0xa6, 0xef, 0x4f, 0x13, 0x04,
+       0x7e, 0x1e, 0xf7, 0x2f, 0x97, 0xc4, 0xba, 0x7f, 0x22, 0x06, 0xfc, 0xec,
+       0x5e, 0x2e, 0x81, 0x04, 0xe1, 0xfe, 0x55, 0xb2, 0xdd, 0x8e, 0xf7, 0xf1,
+       0x54, 0x2a, 0x91, 0x31, 0x90, 0xaf, 0xfe, 0xa2, 0xc2, 0xf6, 0x3f, 0x2a,
+       0xdd, 0x91, 0x31, 0x90, 0xaf, 0xbe, 0x87, 0xeb, 0xbf, 0x4a, 0x07, 0x2d,
+       0xd3, 0xf7, 0x43, 0x38, 0x1c, 0x50, 0x1f, 0xca, 0xc4, 0xd6, 0xf5, 0x3c,
+       0xde, 0xeb, 0xb4, 0xcb, 0x8e, 0xf7, 0xe1, 0x55, 0xbd, 0xec, 0xf2, 0xa1,
+       0x9f, 0xf0, 0xe2, 0x57, 0xc7, 0x9e, 0xc8, 0x83, 0x7c, 0xb5, 0x04, 0xcc,
+       0x93, 0xae, 0x7a, 0xf9, 0x5f, 0x90, 0xfe, 0x55, 0xd6, 0xc8, 0xed, 0xc0,
+       0xff, 0xbd, 0xdb, 0xad, 0x78, 0x3f, 0x69, 0xf7, 0xf6, 0x43, 0x19, 0x60,
+       0x37, 0x74, 0xcb, 0x91, 0x8c, 0xe4, 0xf3, 0xec, 0xeb, 0x54, 0x85, 0xad,
+       0x86, 0x7d, 0x6a, 0x6d, 0x1e, 0x27, 0x6b, 0x97, 0x4e, 0x86, 0x73, 0xbc,
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+       0x9c, 0xe0, 0xfb, 0x15, 0xd3, 0x73, 0xc6, 0xfb, 0x65, 0x4e, 0xd6, 0xce,
+       0x36, 0xdc, 0x9b, 0x58, 0x6e, 0x8b, 0xad, 0xc7, 0x5a, 0x40, 0x2f, 0xe8,
+       0xe2, 0x78, 0x62, 0xf4, 0x5c, 0x61, 0x0b, 0xf4, 0x7b, 0x9a, 0x74, 0xd5,
+       0x0f, 0xa1, 0x24, 0xa9, 0x12, 0x7a, 0x71, 0x7f, 0xbc, 0x7c, 0x4b, 0x66,
+       0x3a, 0xf8, 0xbb, 0x07, 0xec, 0x97, 0xe0, 0xbe, 0xd5, 0x01, 0x59, 0x45,
+       0x7f, 0x10, 0x9e, 0x7a, 0x7d, 0x7c, 0xa2, 0xd6, 0x9b, 0x2b, 0xe1, 0x79,
+       0xfa, 0xac, 0x5c, 0x89, 0xc2, 0xd1, 0xd3, 0xfc, 0x69, 0xc9, 0x10, 0x02,
+       0xf9, 0x81, 0xf6, 0xd9, 0xb1, 0xf4, 0xd3, 0xde, 0x84, 0x04, 0xe4, 0xa7,
+       0x72, 0x9b, 0x35, 0xe6, 0xf9, 0xcd, 0xdf, 0x72, 0x7e, 0xdb, 0x06, 0xf2,
+       0x36, 0x81, 0x8d, 0xe7, 0xcd, 0x8e, 0x8e, 0x7b, 0x40, 0x0e, 0x29, 0x00,
+       0xc7, 0x14, 0xa7, 0x8a, 0xf3, 0x29, 0xa7, 0x7e, 0x00, 0xbb, 0x27, 0x6a,
+       0x4e, 0xae, 0xfe, 0xdc, 0xf6, 0x22, 0xa9, 0x01, 0xeb, 0x51, 0xf9, 0x42,
+       0x7c, 0x2c, 0x22, 0xeb, 0x95, 0x3c, 0x67, 0x7f, 0xbd, 0xb2, 0x68, 0x69,
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+       0x22, 0xc1, 0x14, 0xb4, 0x93, 0x24, 0x4e, 0x43, 0xb2, 0x7e, 0xb0, 0x21,
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+       0x48, 0xdd, 0x80, 0x72, 0xea, 0x20, 0x61, 0x7c, 0x3a, 0xa9, 0x19, 0xc2,
+       0xd6, 0xa1, 0x1a, 0x02, 0xf1, 0xf1, 0x13, 0x7c, 0x7f, 0xd6, 0x2a, 0xa9,
+       0x0f, 0xe3, 0x7d, 0x33, 0x1d, 0x22, 0xea, 0xf3, 0x0b, 0xe1, 0xed, 0xbd,
+       0x04, 0x37, 0xc2, 0x6d, 0x95, 0x6a, 0x88, 0x17, 0xed, 0x8d, 0x59, 0x1e,
+       0xb0, 0xc7, 0x84, 0xa0, 0x9f, 0x7c, 0x4b, 0xf9, 0xa1, 0xae, 0x76, 0x66,
+       0x2e, 0x3b, 0x17, 0x4e, 0x7c, 0x90, 0xef, 0xe6, 0x26, 0x0c, 0x3e, 0xb7,
+       0xe7, 0xd5, 0xaf, 0xc1, 0x3e, 0xa0, 0x7c, 0xc6, 0xee, 0xb1, 0xfa, 0x3e,
+       0x09, 0xd5, 0xd1, 0xf1, 0xe0, 0x98, 0x31, 0xc6, 0xff, 0x0a, 0xd8, 0x7d,
+       0xf6, 0xe6, 0xf1, 0xfe, 0xcc, 0xe9, 0x40, 0x82, 0xfb, 0x0d, 0xf7, 0x9d,
+       0xc3, 0x5f, 0xaf, 0x76, 0x7f, 0x1e, 0xf8, 0xeb, 0x89, 0x7f, 0x9d, 0x08,
+       0xfb, 0x31, 0x4e, 0x0f, 0x89, 0x80, 0xbd, 0x94, 0xe0, 0x24, 0x91, 0x84,
+       0x71, 0x70, 0x4f, 0x9e, 0x74, 0x52, 0x2f, 0xbf, 0x6e, 0xc2, 0xca, 0x23,
+       0x28, 0x3b, 0x83, 0x5e, 0xf3, 0x4c, 0x31, 0x7e, 0x37, 0xf3, 0x35, 0xf1,
+       0x4a, 0x9f, 0xf7, 0xe9, 0x45, 0x11, 0xdb, 0x7f, 0x6e, 0x6a, 0xff, 0xf9,
+       0xf9, 0xda, 0x6b, 0xf8, 0x08, 0xd8, 0x36, 0x7a, 0x8f, 0xe6, 0x46, 0xf1,
+       0xe2, 0xe0, 0x73, 0x08, 0x16, 0x78, 0xcf, 0x75, 0x01, 0x3e, 0xc6, 0xb9,
+       0xbd, 0x75, 0x40, 0x47, 0xa5, 0xf7, 0xc3, 0xfb, 0x00, 0x1f, 0xe3, 0x9c,
+       0xcc, 0x1f, 0x4c, 0x69, 0x24, 0x7a, 0x7f, 0x2d, 0xd7, 0xc9, 0xf4, 0xd5,
+       0x0a, 0x7e, 0xff, 0x34, 0xfd, 0x2b, 0x72, 0xea, 0xfa, 0x23, 0x1e, 0x1b,
+       0xc6, 0x47, 0x57, 0x71, 0xbc, 0xf7, 0xd5, 0xd7, 0xe2, 0x26, 0xfd, 0xea,
+       0xdb, 0x25, 0xc0, 0x6b, 0xbf, 0xfa, 0xf6, 0x78, 0xf5, 0x1d, 0xb1, 0xeb,
+       0xbb, 0xe2, 0xc1, 0x93, 0x10, 0x1b, 0x9e, 0xa4, 0x38, 0xfd, 0x07, 0x63,
+       0xd7, 0xaf, 0x7e, 0xf9, 0xbd, 0x37, 0x23, 0x2a, 0xbc, 0x64, 0x7a, 0x03,
+       0x82, 0xf3, 0xfc, 0xdc, 0x72, 0xae, 0x13, 0xfc, 0xab, 0xc4, 0x0f, 0x53,
+       0x8b, 0x19, 0x57, 0xb0, 0xfd, 0x00, 0x13, 0xdd, 0x1c, 0xc0, 0x7f, 0x94,
+       0x1f, 0x1c, 0xa3, 0x74, 0xef, 0xe1, 0xff, 0xb2, 0x75, 0xf4, 0x1b, 0x11,
+       0x83, 0xfe, 0x24, 0x82, 0x7c, 0x57, 0xcc, 0xe1, 0xa1, 0x65, 0xe7, 0x60,
+       0x0a, 0xdf, 0x8f, 0x39, 0xb8, 0xd3, 0x37, 0xb1, 0xfd, 0xca, 0xb9, 0x77,
+       0xb1, 0x38, 0xd1, 0x8f, 0x6d, 0xa5, 0xe8, 0xef, 0x1e, 0xe1, 0xf7, 0x01,
+       0xcd, 0x6d, 0x64, 0x7e, 0xf5, 0xdc, 0xa5, 0x6c, 0x1f, 0x91, 0x94, 0xb1,
+       0x73, 0x3e, 0x1e, 0xfa, 0x1f, 0x8c, 0x77, 0x1b, 0x74, 0x42, 0xe9, 0x7d,
+       0x5b, 0x83, 0x10, 0x8a, 0x64, 0xc2, 0xbd, 0x35, 0x26, 0xfb, 0xb5, 0xef,
+       0x7e, 0x9c, 0x45, 0x0a, 0xd4, 0x2f, 0x36, 0xc5, 0x5d, 0x34, 0x7e, 0xd2,
+       0xce, 0x23, 0xcd, 0xe7, 0xf6, 0x75, 0x26, 0xe7, 0xcf, 0x85, 0xa4, 0xd7,
+       0x05, 0x72, 0x6f, 0x3e, 0xf7, 0xfe, 0x0a, 0xd7, 0x6b, 0x9a, 0xde, 0x0f,
+       0xae, 0x23, 0x59, 0x70, 0x6e, 0x5f, 0xb4, 0x38, 0xbc, 0xb0, 0x3f, 0x2a,
+       0xf2, 0x73, 0xa6, 0xc4, 0xcd, 0xee, 0xf3, 0x23, 0xbe, 0x61, 0xec, 0x7e,
+       0x39, 0x2d, 0x8f, 0x2b, 0x4b, 0x4d, 0x84, 0xf5, 0x8d, 0x84, 0xf9, 0x7b,
+       0xbe, 0xcf, 0xb2, 0xe4, 0x2a, 0x75, 0x90, 0xfe, 0x9c, 0x96, 0x74, 0xce,
+       0x81, 0xf7, 0x83, 0xd4, 0xc9, 0xde, 0x34, 0xd0, 0x83, 0xf2, 0x39, 0x6a,
+       0xd7, 0x51, 0x57, 0x4d, 0x39, 0x37, 0x82, 0xa8, 0xba, 0x73, 0x64, 0xd4,
+       0x9e, 0x43, 0xe1, 0x96, 0x3d, 0xec, 0xbe, 0x44, 0xc9, 0x53, 0x44, 0x4a,
+       0xc1, 0x0e, 0xe4, 0xf7, 0x03, 0x90, 0x94, 0xab, 0xfb, 0xec, 0xae, 0xb7,
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+       0x7f, 0xe1, 0x2a, 0xba, 0xd3, 0x39, 0x01, 0xec, 0xcb, 0x89, 0x5e, 0x76,
+       0xcf, 0xad, 0x91, 0x8e, 0xc1, 0x9d, 0x6c, 0x7e, 0x75, 0x30, 0xbf, 0xcc,
+       0xfe, 0x70, 0xd7, 0x29, 0x5e, 0x2f, 0xda, 0x9d, 0x57, 0x53, 0x8b, 0x01,
+       0xe3, 0x38, 0x5e, 0xfc, 0x7d, 0x07, 0xd1, 0xaa, 0xbe, 0xa7, 0x82, 0x3c,
+       0xfe, 0x9b, 0xcc, 0x7e, 0xaf, 0xa0, 0x1f, 0x1e, 0x18, 0xfd, 0xce, 0xa6,
+       0x24, 0xe3, 0xbd, 0xec, 0x0b, 0xdc, 0xab, 0x3f, 0x04, 0x3e, 0x5d, 0xc3,
+       0xef, 0x23, 0x5c, 0x59, 0x9b, 0x85, 0xcf, 0xd5, 0xb5, 0x69, 0x68, 0x77,
+       0xd6, 0xd7, 0x7a, 0xf1, 0xa9, 0xe1, 0xc5, 0xe6, 0x6d, 0xc0, 0x7b, 0xdf,
+       0x6c, 0xa3, 0x58, 0x7f, 0x36, 0x8f, 0x9f, 0xd9, 0x15, 0xd4, 0x96, 0x81,
+       0x7c, 0x0a, 0xc9, 0x53, 0x13, 0x81, 0xb2, 0x2d, 0xbd, 0x86, 0x80, 0xbd,
+       0x6b, 0xef, 0xc3, 0x4f, 0x03, 0xe2, 0x47, 0xe9, 0x2b, 0xfb, 0xb1, 0x6c,
+       0xf5, 0xb0, 0xdf, 0x8d, 0x90, 0x1b, 0x67, 0x21, 0x9e, 0x69, 0x7b, 0x52,
+       0x4a, 0xbf, 0x2f, 0x71, 0xf9, 0x1f, 0x07, 0x39, 0xb1, 0xab, 0x97, 0x19,
+       0xee, 0x91, 0xb3, 0xa6, 0x8d, 0x37, 0xdd, 0x37, 0x68, 0xc2, 0x9b, 0xc6,
+       0x1f, 0xdb, 0x18, 0xfe, 0xd6, 0x0a, 0x8c, 0x3f, 0xcc, 0xf8, 0x5b, 0x2b,
+       0x77, 0xaa, 0xb0, 0xaf, 0xbc, 0xf6, 0xaa, 0xbe, 0x7b, 0x67, 0x10, 0x7f,
+       0xd4, 0xbc, 0x67, 0xf8, 0xfb, 0x2d, 0xdb, 0x67, 0x8b, 0x8b, 0x3f, 0x4f,
+       0x32, 0xda, 0xaf, 0x0b, 0xf2, 0xeb, 0x6f, 0xaf, 0xa3, 0xaf, 0x1e, 0xe4,
+       0xfb, 0x8b, 0x0f, 0xd4, 0x4e, 0x44, 0x7c, 0xad, 0xe2, 0xf7, 0x48, 0xde,
+       0x5f, 0xeb, 0xc3, 0xa7, 0x08, 0xf8, 0xa3, 0xf3, 0xb3, 0x66, 0x07, 0x09,
+       0xdc, 0x8f, 0xce, 0x7e, 0x1b, 0x82, 0x3e, 0x9d, 0x45, 0x3e, 0xb8, 0x7f,
+       0x16, 0x78, 0x17, 0xf0, 0x27, 0x3a, 0x19, 0x3e, 0xad, 0x69, 0x35, 0xb8,
+       0xbf, 0x66, 0x73, 0x32, 0x7c, 0x89, 0xce, 0x20, 0xe2, 0x45, 0x76, 0x32,
+       0x7c, 0x89, 0x4e, 0xc6, 0x6f, 0x0a, 0x2f, 0x4b, 0x80, 0xbf, 0x5c, 0x6c,
+       0x8f, 0xef, 0x29, 0xfe, 0x0e, 0x00, 0x7f, 0xd9, 0xd2, 0x27, 0x1b, 0xf0,
+       0xa5, 0xa4, 0x14, 0x5c, 0x1c, 0xfe, 0x1e, 0xa3, 0xf8, 0xa3, 0x70, 0xa4,
+       0x70, 0xf9, 0x32, 0xe3, 0x21, 0x45, 0x61, 0xf7, 0x53, 0x6a, 0x72, 0x15,
+       0xcf, 0x8e, 0x7b, 0x94, 0xce, 0x1f, 0xd6, 0xed, 0x0d, 0xb5, 0x04, 0x9f,
+       0x03, 0xe3, 0xf8, 0x8b, 0x23, 0x5c, 0x6c, 0xdd, 0x4c, 0xb1, 0xd4, 0xec,
+       0x97, 0x01, 0x1f, 0xc9, 0x84, 0xaf, 0x27, 0x41, 0x92, 0x9e, 0x4f, 0x58,
+       0xea, 0x21, 0xfc, 0xa5, 0x05, 0x89, 0x0a, 0x65, 0x81, 0xc1, 0x41, 0x1a,
+       0x86, 0x19, 0xee, 0x95, 0x14, 0x3d, 0x92, 0xe9, 0x5e, 0x36, 0x75, 0x03,
+       0xf0, 0xc1, 0xfa, 0x43, 0xb2, 0x05, 0xee, 0xa3, 0x13, 0x97, 0x5e, 0x6d,
+       0x38, 0x0f, 0x2a, 0xce, 0xf6, 0x25, 0xa9, 0x88, 0x4f, 0x3f, 0xde, 0xd3,
+       0xfc, 0x60, 0xad, 0x8a, 0xf4, 0x5b, 0x07, 0x74, 0x84, 0x7b, 0x40, 0xb9,
+       0xff, 0x75, 0x3f, 0xa7, 0xe7, 0x03, 0xfc, 0x1e, 0xca, 0x55, 0x5c, 0x3e,
+       0xd6, 0x72, 0x79, 0x79, 0x98, 0xcb, 0x49, 0x1d, 0xbf, 0x37, 0x79, 0xcd,
+       0x4c, 0x96, 0x67, 0x95, 0x92, 0x63, 0xe1, 0xf7, 0x95, 0x45, 0x88, 0x3e,
+       0x8f, 0x29, 0xc9, 0x1b, 0x26, 0x0a, 0x85, 0x0b, 0x6d, 0x6a, 0x15, 0x9f,
+       0x78, 0xcf, 0x22, 0x79, 0xdf, 0x1a, 0x1a, 0x4d, 0xdb, 0x25, 0x64, 0x13,
+       0x1f, 0xf0, 0x49, 0xd2, 0xfb, 0xf7, 0x86, 0xd8, 0x7d, 0x8d, 0x45, 0x83,
+       0xc1, 0x0e, 0x4a, 0xd2, 0xee, 0x5f, 0x9c, 0xa2, 0x26, 0xcd, 0xc1, 0x83,
+       0xb0, 0x11, 0x89, 0xf9, 0x1d, 0x54, 0x15, 0xa2, 0x1f, 0xd3, 0x69, 0x89,
+       0x75, 0x4f, 0x55, 0x9d, 0xf7, 0x80, 0x0d, 0xe2, 0xa1, 0xf1, 0xe0, 0x49,
+       0xf0, 0xfa, 0x32, 0xef, 0xa7, 0xe3, 0x25, 0x34, 0xba, 0xd0, 0x7e, 0x1f,
+       0xe0, 0x2f, 0x9a, 0xb3, 0x90, 0x96, 0x9d, 0x8d, 0x09, 0x18, 0xff, 0x4b,
+       0xe0, 0xbf, 0xcf, 0xe2, 0xa4, 0x70, 0x97, 0xea, 0xe8, 0x1d, 0xef, 0x1e,
+       0xea, 0x8d, 0xae, 0xab, 0x12, 0x5d, 0x94, 0x9e, 0x1e, 0x80, 0x91, 0x3e,
+       0x1f, 0x69, 0x1c, 0x89, 0xbf, 0xcb, 0xf2, 0xa8, 0x5c, 0x84, 0xbf, 0xe3,
+       0xf2, 0x28, 0x5f, 0x4f, 0xb5, 0x7b, 0xce, 0xb5, 0x76, 0xdf, 0x70, 0xfd,
+       0xe8, 0xce, 0xbb, 0xcc, 0xe0, 0xb7, 0xae, 0x97, 0x7d, 0xd8, 0xce, 0x33,
+       0xc5, 0x28, 0xff, 0xeb, 0xb9, 0xbe, 0x4d, 0x9e, 0x6e, 0xe4, 0x73, 0x4d,
+       0xdf, 0x1e, 0xed, 0xd3, 0xb7, 0xfe, 0x11, 0x00, 0x4f, 0xea, 0xb9, 0xe9,
+       0xa8, 0xc7, 0x52, 0x6e, 0x88, 0xad, 0x77, 0xeb, 0x64, 0x05, 0xef, 0x2d,
+       0xaf, 0x1b, 0xcb, 0xe4, 0x3c, 0x58, 0xac, 0xb0, 0xfb, 0x4b, 0xfb, 0xeb,
+       0x01, 0x8c, 0x53, 0x9f, 0xf5, 0x8f, 0xd9, 0x08, 0x7a, 0x54, 0xe3, 0xab,
+       0xe5, 0x84, 0xe9, 0x9d, 0x20, 0x71, 0x78, 0x71, 0x1d, 0xe2, 0xf7, 0xdb,
+       0x68, 0x76, 0xf0, 0x4a, 0xb8, 0x07, 0x90, 0xeb, 0x57, 0x78, 0x8a, 0xa3,
+       0xd8, 0xef, 0x0f, 0xa4, 0xce, 0x65, 0xf7, 0xf9, 0xae, 0xe1, 0xf7, 0x58,
+       0x3d, 0x44, 0xf9, 0x8a, 0xe0, 0xbd, 0xa7, 0x5e, 0x7c, 0x5e, 0xed, 0x62,
+       0xfb, 0x13, 0xcb, 0x6d, 0xe3, 0xf1, 0x3e, 0xb5, 0x3a, 0xa7, 0x05, 0xf5,
+       0x84, 0xf4, 0x81, 0x35, 0x04, 0x26, 0x87, 0xb4, 0x7f, 0x92, 0x07, 0xe2,
+       0x05, 0x92, 0xec, 0xed, 0xf4, 0x41, 0xbc, 0xcf, 0x25, 0x85, 0xe1, 0xde,
+       0xdc, 0x3a, 0x67, 0x1e, 0xde, 0xfb, 0x2e, 0x24, 0xe5, 0x79, 0x80, 0xfe,
+       0x5f, 0xba, 0x16, 0x0c, 0x3f, 0x5f, 0x3e, 0x1d, 0x9d, 0x28, 0xde, 0x97,
+       0xe9, 0x49, 0x29, 0x22, 0x1f, 0x65, 0xe3, 0x6e, 0x00, 0x9e, 0x47, 0x96,
+       0x3d, 0x37, 0x10, 0x88, 0x1b, 0x6e, 0x48, 0xa9, 0xb1, 0x03, 0xde, 0x26,
+       0xb9, 0x58, 0x5c, 0xbf, 0xb1, 0x38, 0x1f, 0xf1, 0x48, 0xf1, 0x7b, 0x9d,
+       0x6b, 0x60, 0xb4, 0x9f, 0x41, 0xb3, 0xaf, 0xee, 0xbb, 0x07, 0x0b, 0xba,
+       0xdd, 0x10, 0xe7, 0x5c, 0xf3, 0xad, 0x2e, 0x66, 0x2f, 0x91, 0xf4, 0x20,
+       0x19, 0xa5, 0x93, 0xf3, 0x46, 0xed, 0x77, 0x4e, 0xd4, 0x20, 0xc9, 0xd2,
+       0xc9, 0xfb, 0xf2, 0xd1, 0x85, 0x04, 0xf6, 0x87, 0xfa, 0xcb, 0x79, 0x1c,
+       0x3d, 0xb6, 0x99, 0xe9, 0xb1, 0x15, 0x42, 0x6c, 0x3d, 0xa6, 0xd9, 0x99,
+       0x9a, 0x1e, 0x93, 0x4d, 0xfa, 0x41, 0x7b, 0xd6, 0x0f, 0x9f, 0x69, 0x38,
+       0xa7, 0xa5, 0xa4, 0x78, 0x81, 0x77, 0xe1, 0x19, 0xb4, 0x78, 0xc1, 0xbe,
+       0x7b, 0xb1, 0xfe, 0xd6, 0x24, 0xc4, 0x43, 0x0d, 0xe0, 0x81, 0xa4, 0x5d,
+       0xdd, 0xe7, 0xbf, 0xfe, 0x60, 0x04, 0xd8, 0x8f, 0xf9, 0x31, 0xf9, 0xcd,
+       0xac, 0xbf, 0x16, 0xf4, 0xad, 0xe7, 0xbe, 0x54, 0xa0, 0xd3, 0x09, 0x59,
+       0x1d, 0x34, 0x07, 0xf8, 0xe9, 0x50, 0xec, 0xf5, 0x7c, 0xea, 0x23, 0x97,
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+       0xb7, 0x12, 0xd7, 0xd3, 0x92, 0x73, 0x13, 0xf1, 0x59, 0xd6, 0x38, 0x13,
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+       0x52, 0xa6, 0xb0, 0x7a, 0x25, 0x0d, 0x77, 0x2b, 0xa0, 0x4f, 0x4a, 0x9a,
+       0x92, 0x92, 0x05, 0xdd, 0xbc, 0x4a, 0x1b, 0x2b, 0x0c, 0x79, 0x18, 0xa5,
+       0x4d, 0xc5, 0xca, 0x3c, 0x5d, 0xbf, 0x51, 0x3a, 0x38, 0x5e, 0x9b, 0x3a,
+       0x2a, 0x4a, 0x87, 0xcc, 0x87, 0xe4, 0x2b, 0x97, 0x3b, 0x61, 0xbd, 0x2f,
+       0x72, 0xb9, 0x61, 0xbc, 0x8d, 0x8b, 0xf2, 0x7f, 0xa2, 0x42, 0x7f, 0x4c,
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+       0x9d, 0x9c, 0xa7, 0xa3, 0x8f, 0x46, 0x17, 0x73, 0xfb, 0x63, 0xcd, 0xa5,
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+       0xba, 0x30, 0xde, 0xbe, 0x63, 0xc8, 0xfb, 0xe9, 0x87, 0x37, 0x4e, 0x5f,
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+       0xfa, 0x4a, 0x22, 0x83, 0xdb, 0x0e, 0x71, 0x6b, 0x11, 0xd6, 0xd5, 0x08,
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+       0xf2, 0xa3, 0xa4, 0xbb, 0x97, 0x75, 0x94, 0xe4, 0xb3, 0x00, 0xbf, 0x8c,
+       0x6e, 0xa0, 0xef, 0xf5, 0xf4, 0x8b, 0x11, 0x57, 0x4b, 0x76, 0xe2, 0xf5,
+       0xb7, 0x31, 0xf7, 0x61, 0x34, 0xf8, 0xe8, 0xb8, 0x04, 0xf0, 0x27, 0x9e,
+       0x2b, 0x64, 0xeb, 0xab, 0x89, 0x0f, 0xf6, 0x08, 0x0c, 0xfe, 0xa0, 0x8b,
+       0xfb, 0x5b, 0x24, 0x28, 0x02, 0x3d, 0xe7, 0x68, 0xf7, 0x05, 0x4b, 0x2b,
+       0x58, 0x59, 0xfb, 0xbd, 0x08, 0xa0, 0x22, 0x85, 0xe3, 0x03, 0x6d, 0x7f,
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+       0x87, 0xfd, 0xa9, 0x39, 0xce, 0x31, 0x7f, 0x82, 0xe7, 0x1e, 0xb9, 0xf7,
+       0x40, 0x02, 0xd8, 0x81, 0x77, 0x0b, 0x78, 0xfe, 0xe3, 0xc7, 0xbf, 0x7b,
+       0x45, 0x4e, 0xa0, 0xcf, 0x9d, 0xef, 0x6c, 0xc4, 0xf3, 0xc6, 0xa7, 0xb9,
+       0xdc, 0xdd, 0x4e, 0x7a, 0xf1, 0x1e, 0x76, 0x3f, 0xf1, 0xf0, 0x7d, 0xf2,
+       0x10, 0xbe, 0x9f, 0x07, 0x3f, 0x30, 0x87, 0xe5, 0xb0, 0x0c, 0x7e, 0xfa,
+       0xdc, 0x48, 0xe8, 0x47, 0xd7, 0xd0, 0xd2, 0x6d, 0xaf, 0x84, 0xae, 0x01,
+       0xb3, 0xed, 0xf6, 0x8e, 0xde, 0xdf, 0x80, 0x1a, 0xf0, 0x87, 0x3d, 0x85,
+       0xb8, 0x07, 0xa0, 0xb5, 0x6b, 0xf3, 0xbe, 0xca, 0xca, 0xac, 0x5d, 0x14,
+       0x0f, 0x36, 0x6e, 0x8f, 0xda, 0x70, 0x5e, 0xd1, 0x79, 0xdb, 0x10, 0x0f,
+       0x1f, 0xf4, 0xe5, 0x8d, 0x07, 0x91, 0x1e, 0x7d, 0x78, 0xe2, 0xf7, 0x2a,
+       0x69, 0x78, 0xe9, 0x9b, 0x77, 0xe2, 0xcd, 0x57, 0x43, 0x9c, 0x37, 0x9e,
+       0x3e, 0x9b, 0xe3, 0xcc, 0xfa, 0x13, 0xdb, 0xfc, 0x60, 0x70, 0x99, 0xf1,
+       0xf4, 0x39, 0x7c, 0xa2, 0x76, 0xe4, 0xe7, 0x6e, 0x9f, 0x3d, 0x91, 0xea,
+       0xb7, 0x8f, 0xdd, 0x3e, 0x07, 0x3c, 0x2b, 0x6d, 0xbd, 0x19, 0xd2, 0x08,
+       0x94, 0x17, 0x37, 0x94, 0xab, 0x45, 0xff, 0xf0, 0x54, 0x8a, 0x87, 0xd3,
+       0xc3, 0xfc, 0x97, 0x0c, 0x04, 0x7c, 0x74, 0x0e, 0xb8, 0x28, 0x3d, 0xfa,
+       0xa1, 0x9d, 0xe9, 0x01, 0x92, 0x97, 0x81, 0xf3, 0xd1, 0xee, 0x7d, 0x3f,
+       0x78, 0xef, 0x71, 0x17, 0xd8, 0x9d, 0xf5, 0x3b, 0xdf, 0xcb, 0x80, 0x67,
+       0x95, 0xd8, 0xb5, 0xf6, 0x16, 0x8c, 0x6f, 0x8a, 0xe8, 0x0f, 0x9d, 0x6d,
+       0xbd, 0xe4, 0xbc, 0xe7, 0xc3, 0x3e, 0x84, 0xb8, 0x13, 0x5d, 0xff, 0x46,
+       0x27, 0x6a, 0x7c, 0xc8, 0xe6, 0x77, 0x07, 0x3f, 0x5f, 0x73, 0x47, 0x6b,
+       0x02, 0x9e, 0xaf, 0xb9, 0x63, 0xa9, 0x68, 0xb8, 0xb7, 0xf9, 0x8e, 0xa5,
+       0x2c, 0xef, 0x8e, 0x48, 0x9d, 0xe3, 0x6e, 0x32, 0xd8, 0xeb, 0x2b, 0xe2,
+       0xf6, 0x03, 0x71, 0x00, 0x73, 0x3f, 0xf3, 0x97, 0x16, 0x90, 0x8f, 0x07,
+       0xc0, 0x3e, 0xab, 0x67, 0x2a, 0xc6, 0x05, 0x9e, 0x62, 0xfc, 0x35, 0x7f,
+       0xba, 0x4f, 0x84, 0x7c, 0xe4, 0xc9, 0x2b, 0x05, 0x8c, 0xb7, 0x4c, 0x3a,
+       0xaa, 0xb6, 0x75, 0xd1, 0xf2, 0xfc, 0x50, 0x12, 0xfe, 0xde, 0xd1, 0xfc,
+       0x7b, 0x97, 0xe4, 0xc2, 0x3d, 0x04, 0xd5, 0x9d, 0x2c, 0xbe, 0x37, 0x48,
+       0x5c, 0x9c, 0xf3, 0x33, 0x88, 0x9f, 0x1c, 0x60, 0xeb, 0x38, 0x94, 0x17,
+       0x83, 0x7c, 0x3b, 0x7d, 0xaa, 0x53, 0x17, 0xef, 0xef, 0x96, 0x6b, 0x72,
+       0xe0, 0xde, 0xbd, 0xe0, 0x6d, 0x4e, 0x1f, 0xf0, 0x4f, 0xf1, 0x4d, 0xbe,
+       0x0f, 0xf0, 0xf7, 0x12, 0x79, 0x1c, 0x42, 0x5b, 0x57, 0x77, 0x35, 0x16,
+       0x63, 0x1e, 0x6b, 0xf1, 0x5c, 0x75, 0x22, 0xd0, 0xbd, 0x38, 0x6c, 0xc7,
+       0xdf, 0x1f, 0x2c, 0xb6, 0x11, 0xc9, 0x41, 0xf5, 0x58, 0xb1, 0x44, 0x6c,
+       0xf0, 0x1c, 0xa4, 0x10, 0xc9, 0x0e, 0x4f, 0x07, 0xb1, 0xc1, 0x33, 0x7f,
+       0x39, 0xbb, 0x27, 0xbb, 0xa4, 0xf1, 0x7a, 0xb4, 0x0f, 0xdc, 0x13, 0x8b,
+       0x14, 0xb8, 0xff, 0xb6, 0xb8, 0xfd, 0xd9, 0x2f, 0xa0, 0x7d, 0xa9, 0x14,
+       0xd9, 0xcf, 0xce, 0xb5, 0x30, 0xfc, 0x14, 0xb7, 0x1f, 0xfa, 0x1a, 0xf8,
+       0x67, 0xa1, 0xaf, 0x08, 0xf3, 0x0e, 0xbf, 0xb3, 0x45, 0x31, 0xf8, 0x7f,
+       0x63, 0xc3, 0xc6, 0xf2, 0xe5, 0x6d, 0xc6, 0x72, 0x4e, 0xc4, 0x58, 0xce,
+       0xed, 0x30, 0x96, 0xb7, 0xc2, 0x1d, 0x67, 0x3a, 0x3b, 0xe2, 0xc0, 0x5e,
+       0x2b, 0xae, 0x13, 0x15, 0xa7, 0xd8, 0x39, 0xbd, 0x97, 0x04, 0x58, 0x9b,
+       0x20, 0x1e, 0x6c, 0x45, 0x79, 0x9a, 0x56, 0xd1, 0x9e, 0x0f, 0xfb, 0xd1,
+       0xa7, 0x9e, 0x77, 0x59, 0xe0, 0xfb, 0x9e, 0xbf, 0x30, 0xbf, 0xb7, 0x77,
+       0xab, 0x1d, 0xef, 0x7b, 0xdb, 0xff, 0x7b, 0x07, 0x71, 0x40, 0x5e, 0xe1,
+       0x0b, 0xf6, 0x8d, 0xf0, 0xfd, 0x94, 0x23, 0x9c, 0x0f, 0x71, 0x38, 0x5a,
+       0x9f, 0xfd, 0xce, 0x56, 0x51, 0x78, 0x0c, 0xf8, 0x6f, 0x2f, 0x5e, 0xa6,
+       0xf9, 0xe9, 0xa1, 0x71, 0x30, 0xaf, 0x17, 0xff, 0xca, 0xf2, 0x64, 0x7a,
+       0xb7, 0x5a, 0xf1, 0xf7, 0x53, 0x4e, 0xed, 0x7e, 0xf6, 0x79, 0xd8, 0x17,
+       0x3b, 0xb5, 0x75, 0x28, 0xda, 0x59, 0x2f, 0x09, 0x41, 0x0b, 0xf4, 0x1b,
+       0x5c, 0xc5, 0xe8, 0x6f, 0xe6, 0xd3, 0x8a, 0x2d, 0x46, 0xbf, 0xf8, 0x9e,
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+       0x34, 0x64, 0x2c, 0xff, 0x3c, 0x91, 0xf9, 0x53, 0xf3, 0x88, 0xee, 0x7d,
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+       0x8a, 0xa3, 0xf7, 0x6f, 0x25, 0x8d, 0x3c, 0xae, 0x4a, 0xdf, 0xcd, 0x17,
+       0x74, 0x2c, 0x98, 0x4a, 0xe4, 0x9b, 0xed, 0xb7, 0x21, 0x7c, 0x86, 0xd6,
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+       0x5e, 0x7f, 0x96, 0xb1, 0x9a, 0x3e, 0x6b, 0xac, 0xbd, 0xda, 0xdf, 0x99,
+       0x3a, 0x03, 0x0b, 0x13, 0xdc, 0x87, 0xa8, 0x5f, 0x84, 0x4b, 0x10, 0x78,
+       0xdb, 0xb6, 0x81, 0x2f, 0x0c, 0x1e, 0x28, 0x37, 0x0c, 0x1c, 0x24, 0xb8,
+       0xa8, 0xf4, 0x10, 0x0f, 0x9f, 0x60, 0x1c, 0xdf, 0x48, 0xef, 0x18, 0x0c,
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+       0xa4, 0xee, 0xdf, 0x35, 0x5d, 0xbe, 0x99, 0x50, 0x2f, 0xeb, 0x34, 0xfb,
+       0xd9, 0x52, 0x1e, 0xdd, 0xdf, 0xc4, 0x56, 0x1e, 0xd5, 0xc9, 0x82, 0x1f,
+       0x34, 0x74, 0x55, 0xcf, 0x8c, 0x2f, 0xf3, 0xf6, 0xb1, 0xef, 0x1b, 0x6b,
+       0xaa, 0x61, 0xff, 0x97, 0x97, 0xf0, 0xef, 0x8f, 0xda, 0x9b, 0x8e, 0xdc,
+       0xa7, 0xc4, 0xf8, 0x11, 0xac, 0x23, 0x17, 0xe1, 0x12, 0x2d, 0x9b, 0x12,
+       0xca, 0x56, 0x28, 0x4f, 0x8e, 0x2b, 0xdb, 0x13, 0xea, 0x5d, 0x09, 0xf5,
+       0xee, 0x84, 0x72, 0x36, 0x6f, 0xff, 0xb9, 0x2d, 0x9c, 0x2b, 0x7b, 0x19,
+       0xfb, 0xd4, 0xbe, 0xb6, 0x46, 0x01, 0xfe, 0xf2, 0x79, 0x66, 0x78, 0x91,
+       0x04, 0xe5, 0x8d, 0x1d, 0x77, 0xd5, 0x54, 0x03, 0x9f, 0x6b, 0x2c, 0x1f,
+       0xf4, 0xc9, 0xc8, 0x3f, 0x07, 0x24, 0xaf, 0xc4, 0x62, 0xf0, 0x6b, 0xf2,
+       0x32, 0x5f, 0x08, 0xe0, 0x67, 0xf5, 0x46, 0x0c, 0x4b, 0x4b, 0x10, 0x0e,
+       0x83, 0x6f, 0xe2, 0xfe, 0x6f, 0xe8, 0x97, 0xec, 0x12, 0xd0, 0xb9, 0xb5,
+       0x6f, 0x5f, 0x98, 0xca, 0xf8, 0x9d, 0x27, 0xee, 0xbb, 0x3e, 0x89, 0xbe,
+       0x6b, 0xe8, 0xfb, 0x98, 0xbe, 0x1b, 0xb5, 0xff, 0x62, 0x1d, 0xed, 0xe3,
+       0x0d, 0xc5, 0xc7, 0xa8, 0x1d, 0x00, 0xc0, 0x7e, 0x02, 0xf0, 0x74, 0x13,
+       0x93, 0x58, 0x0a, 0x80, 0x34, 0x5f, 0x09, 0xfc, 0x11, 0xf9, 0x64, 0x63,
+       0xdf, 0x27, 0x5c, 0xee, 0xb2, 0x21, 0x03, 0x5f, 0x1f, 0xe7, 0x83, 0x67,
+       0x32, 0x7d, 0xaf, 0x13, 0x1f, 0x3c, 0x20, 0xd9, 0x71, 0xdf, 0x45, 0xe9,
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+       0xc6, 0x6e, 0x2c, 0x77, 0x7d, 0xd1, 0xae, 0x40, 0xfb, 0x7f, 0x6b, 0xfc,
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+       0x1d, 0xd7, 0x9d, 0x86, 0x7a, 0x00, 0xc8, 0x7d, 0x58, 0x6f, 0x9b, 0x33,
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+       0xfe, 0x78, 0x8b, 0x3d, 0xf0, 0x00, 0xf6, 0xaf, 0x8e, 0xbf, 0xe8, 0xde,
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+       0xf0, 0x7d, 0x96, 0xa8, 0x97, 0x1d, 0xfd, 0xd0, 0xb4, 0x91, 0x81, 0x1c,
+       0x3b, 0x6a, 0xe8, 0x23, 0xbe, 0x78, 0x74, 0x1e, 0xf3, 0xb6, 0x23, 0xff,
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+       0x23, 0xc2, 0x14, 0xac, 0xbf, 0xc2, 0x63, 0x87, 0x99, 0x20, 0x9e, 0x09,
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+       0xaa, 0x5c, 0x7c, 0xcc, 0x0c, 0xfb, 0x07, 0xe8, 0x6e, 0x8b, 0x24, 0x11,
+       0xbd, 0x6e, 0xb9, 0xdb, 0x42, 0x72, 0x8e, 0x99, 0x38, 0x9e, 0x9b, 0x57,
+       0x27, 0x79, 0x90, 0x7e, 0xb7, 0x19, 0x86, 0x9e, 0xa6, 0x7d, 0xf5, 0xaa,
+       0x91, 0x21, 0xde, 0xcf, 0x9a, 0x87, 0x5e, 0x22, 0x7e, 0x55, 0xc8, 0xfd,
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+       0xa4, 0x61, 0xfc, 0xe6, 0xe0, 0x7f, 0xb6, 0x31, 0x80, 0xef, 0x71, 0x1d,
+       0xb7, 0x93, 0x9b, 0xfb, 0xb5, 0xf6, 0xf0, 0x19, 0xf8, 0x57, 0x5f, 0x16,
+       0xe3, 0x1b, 0x67, 0x19, 0x1f, 0x27, 0xd8, 0xcf, 0xf9, 0x04, 0xac, 0x74,
+       0x15, 0x8d, 0x73, 0x6b, 0x12, 0xdb, 0x00, 0xfd, 0x36, 0xe9, 0x24, 0x1f,
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+       0x35, 0x88, 0x29, 0x35, 0xe9, 0xc0, 0x2e, 0x2c, 0x8b, 0xed, 0xff, 0x26,
+       0xdd, 0xb1, 0x22, 0xb4, 0xab, 0x1a, 0x4c, 0x1b, 0x07, 0xe5, 0x64, 0xaa,
+       0x3f, 0x8c, 0xf6, 0x18, 0x43, 0x7b, 0x0a, 0xbe, 0x5b, 0x8d, 0x1f, 0xe5,
+       0x0f, 0x87, 0x7f, 0xd3, 0xc6, 0xdf, 0xfe, 0x19, 0xe7, 0xdd, 0xb4, 0x5f,
+       0x4b, 0x17, 0x0d, 0x31, 0xfa, 0x91, 0x2e, 0x4a, 0xf8, 0x7d, 0x1c, 0x3d,
+       0xe5, 0xc7, 0xe8, 0x84, 0xf4, 0x6f, 0xe4, 0x1f, 0xd5, 0x2c, 0x34, 0x4e,
+       0xe2, 0x7e, 0x1a, 0x2c, 0x5b, 0x6a, 0x06, 0x43, 0xe8, 0xa7, 0x69, 0x16,
+       0xfe, 0x8b, 0xb4, 0x43, 0x91, 0x39, 0x48, 0x3f, 0xb6, 0xf2, 0x3e, 0xb6,
+       0x04, 0x9e, 0xcd, 0xa7, 0xb8, 0xfe, 0x31, 0x63, 0x60, 0xd7, 0xeb, 0x68,
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+       0x98, 0x1a, 0xc3, 0xaf, 0x3a, 0xcf, 0x2b, 0x06, 0x36, 0xc9, 0x68, 0xdf,
+       0xa9, 0x7a, 0x4b, 0x9c, 0x7d, 0x39, 0x61, 0xc1, 0xe4, 0xf8, 0xe7, 0x7d,
+       0xf4, 0x1d, 0xda, 0xab, 0x38, 0x5e, 0x04, 0x5f, 0xe1, 0xbe, 0x51, 0xb8,
+       0xbc, 0xdb, 0x2c, 0xe4, 0x1d, 0xc8, 0x45, 0xe2, 0xcb, 0xcb, 0x7b, 0xc6,
+       0x93, 0x5c, 0x44, 0xb9, 0x85, 0xfc, 0x4d, 0xb5, 0x77, 0x91, 0xdf, 0x21,
+       0x7f, 0x79, 0xc6, 0x59, 0x75, 0x9b, 0x13, 0xd6, 0xe9, 0x4d, 0xad, 0xba,
+       0xc9, 0x39, 0x8d, 0x8f, 0x43, 0x7a, 0x3e, 0x1a, 0x49, 0x57, 0x0c, 0x87,
+       0x67, 0xa2, 0xdc, 0x51, 0xdb, 0xa1, 0xdd, 0xdb, 0x62, 0x1d, 0xbd, 0x5d,
+       0xd4, 0x0f, 0xb4, 0x35, 0x85, 0xf3, 0x0f, 0x45, 0xa2, 0xf2, 0x8a, 0x5f,
+       0xe8, 0x77, 0x6d, 0xa0, 0xf9, 0x29, 0x44, 0x2f, 0x6b, 0x77, 0xe4, 0x13,
+       0x3f, 0x56, 0xfd, 0x35, 0x0d, 0xc2, 0x4f, 0xb5, 0x42, 0xf8, 0x77, 0x56,
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+       0xbc, 0x5f, 0xa7, 0x9a, 0x85, 0x6d, 0x58, 0x8f, 0xfe, 0x1d, 0x7c, 0xf6,
+       0x69, 0xbf, 0x6f, 0x66, 0xa1, 0x59, 0x0a, 0xe2, 0xb7, 0xff, 0xa2, 0x31,
+       0xfe, 0x3d, 0xeb, 0xe5, 0xeb, 0xbd, 0x5d, 0xe0, 0x7d, 0xab, 0x99, 0xfb,
+       0x75, 0x66, 0xac, 0xdb, 0x25, 0x73, 0x67, 0x15, 0x5f, 0x6f, 0x4a, 0x99,
+       0x2f, 0xff, 0x7e, 0x94, 0x23, 0x6f, 0xe9, 0xc9, 0xff, 0xf0, 0x1f, 0x02,
+       0x4f, 0x2a, 0x5c, 0x2c, 0xce, 0xaa, 0xc5, 0x08, 0xef, 0x24, 0xb4, 0xd7,
+       0xb0, 0xdd, 0xfd, 0x46, 0x82, 0xcb, 0x09, 0x90, 0xd7, 0xfb, 0x84, 0xdf,
+       0x63, 0x01, 0xda, 0xa1, 0x6d, 0x81, 0xcc, 0xc2, 0x42, 0x04, 0x8f, 0x3d,
+       0x77, 0x81, 0x6d, 0x38, 0x7c, 0x37, 0xbc, 0x6a, 0xae, 0x47, 0x7a, 0xe9,
+       0x71, 0x72, 0xbd, 0x45, 0x7d, 0x3f, 0xc7, 0xa9, 0xa7, 0x32, 0xf9, 0x83,
+       0x10, 0xee, 0xed, 0x16, 0xd2, 0xbb, 0x01, 0xcc, 0x53, 0x90, 0x8e, 0x2a,
+       0x0a, 0x54, 0x39, 0xca, 0xa6, 0xa0, 0x1f, 0xea, 0x63, 0x3d, 0xe8, 0x63,
+       0x50, 0x6e, 0xba, 0xd1, 0x1a, 0xc0, 0xfe, 0x22, 0xa8, 0x37, 0x40, 0x79,
+       0x87, 0xe0, 0x5f, 0x3b, 0x9c, 0x06, 0xea, 0x4f, 0x2d, 0x47, 0xed, 0x3c,
+       0x41, 0x2f, 0x30, 0x0e, 0xf5, 0x87, 0x7e, 0x19, 0x7f, 0x1c, 0x1d, 0x3c,
+       0x15, 0x6d, 0xbf, 0x49, 0xe8, 0x93, 0x9c, 0x2f, 0x6c, 0x5e, 0x95, 0x44,
+       0xfc, 0x28, 0x46, 0xb7, 0x3a, 0x46, 0x74, 0x5b, 0xe2, 0x37, 0xa0, 0x3f,
+       0xe9, 0x55, 0xc1, 0x47, 0x5e, 0x05, 0x80, 0x92, 0x9d, 0xd5, 0x67, 0xe6,
+       0x7c, 0x44, 0xe1, 0xfc, 0xe9, 0xd5, 0x53, 0x13, 0x89, 0xef, 0x1d, 0xf9,
+       0x6c, 0x35, 0xf1, 0x95, 0x73, 0x75, 0x49, 0xcc, 0x28, 0x51, 0x7b, 0x9f,
+       0x84, 0xf5, 0x2f, 0x1a, 0x43, 0xf7, 0x41, 0x79, 0x99, 0xf0, 0xb3, 0xbe,
+       0x2a, 0x71, 0x3d, 0x31, 0x78, 0xc0, 0x46, 0xfd, 0x34, 0x18, 0x02, 0x5b,
+       0xd1, 0xef, 0xd0, 0xf0, 0xc2, 0x38, 0x2f, 0x60, 0x8c, 0xbd, 0x64, 0x08,
+       0xfd, 0xe8, 0x69, 0xac, 0x7f, 0xcd, 0x4c, 0x7e, 0xad, 0x86, 0x64, 0x3e,
+       0xcf, 0x86, 0x57, 0xc7, 0x10, 0x9f, 0xfc, 0xa9, 0x3e, 0xf4, 0xec, 0x8f,
+       0xc9, 0x4f, 0x61, 0x24, 0xfd, 0xad, 0x21, 0xc9, 0x93, 0x42, 0xf5, 0x3f,
+       0x4f, 0x65, 0x58, 0xdf, 0x65, 0x09, 0x84, 0x71, 0x1f, 0x65, 0x19, 0xb9,
+       0x5e, 0xd9, 0x60, 0x08, 0x17, 0x39, 0x00, 0x8e, 0xc7, 0x42, 0x5c, 0x3f,
+       0x3e, 0x86, 0x8c, 0x06, 0xfb, 0x1f, 0xb0, 0x91, 0xde, 0x03, 0xd3, 0xcc,
+       0xc4, 0xf1, 0x8f, 0x77, 0x67, 0x78, 0x37, 0x78, 0x62, 0x70, 0x39, 0xfe,
+       0xe0, 0x24, 0xa2, 0xff, 0xcd, 0x7a, 0x8e, 0xb7, 0xe0, 0x2b, 0xdc, 0xef,
+       0x79, 0x4c, 0xef, 0x9f, 0x93, 0x09, 0xe5, 0x63, 0x2f, 0x96, 0x7a, 0xc1,
+       0xb2, 0x64, 0x67, 0xfd, 0x86, 0xb0, 0x01, 0xe6, 0xd8, 0xfc, 0x30, 0xd7,
+       0xe7, 0x96, 0xea, 0x3c, 0x3b, 0x5b, 0x91, 0x37, 0xbd, 0x66, 0xf1, 0x6a,
+       0xec, 0xd1, 0x87, 0x56, 0xd6, 0x62, 0x7d, 0xf3, 0xea, 0x75, 0xd7, 0x21,
+       0x1f, 0x1c, 0x6d, 0x3f, 0x23, 0x3f, 0x8f, 0xf7, 0xe7, 0x9e, 0x61, 0x43,
+       0xb9, 0x64, 0x8f, 0xd6, 0x17, 0xf4, 0x85, 0x61, 0xdc, 0x33, 0x03, 0x13,
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+       0xe8, 0x01, 0xde, 0x48, 0x5f, 0x07, 0xf4, 0x44, 0xbf, 0x97, 0xda, 0x3f,
+       0xae, 0x17, 0xed, 0x43, 0x94, 0x2f, 0x38, 0x4e, 0x33, 0xf0, 0xdf, 0xa8,
+       0x9f, 0x99, 0xf8, 0x6f, 0x5c, 0x59, 0x1e, 0xa9, 0xcc, 0xf1, 0xd9, 0xfc,
+       0x6a, 0x86, 0xd0, 0xdf, 0xb4, 0xf5, 0xb7, 0xa6, 0x04, 0xce, 0xe1, 0xfe,
+       0x6a, 0xfa, 0x87, 0xdf, 0x1f, 0x6d, 0x25, 0xf8, 0x0e, 0x11, 0xff, 0x63,
+       0x3d, 0xdc, 0x7f, 0x7e, 0x42, 0xef, 0x5b, 0x84, 0x74, 0xea, 0xa8, 0x0e,
+       0x1b, 0x96, 0xc4, 0xc9, 0xed, 0xa4, 0x54, 0x2e, 0xcf, 0x97, 0x1a, 0x85,
+       0x9e, 0xc7, 0xc2, 0x86, 0xf8, 0x7d, 0xa7, 0xd6, 0x57, 0x54, 0x69, 0xe9,
+       0x5c, 0x7d, 0x9a, 0x53, 0x39, 0xbd, 0xdb, 0x06, 0x39, 0x1f, 0x1f, 0x5e,
+       0xaf, 0x13, 0xfb, 0xe1, 0x3b, 0x46, 0x94, 0x5b, 0xdc, 0xb5, 0x03, 0xf6,
+       0xf6, 0x29, 0xee, 0xef, 0x48, 0x4a, 0xf5, 0x50, 0xfd, 0x8c, 0x53, 0x61,
+       0xc3, 0x52, 0x28, 0xe7, 0xad, 0x0b, 0x1b, 0x56, 0x88, 0x27, 0xee, 0x0b,
+       0x80, 0x77, 0xd8, 0x04, 0xeb, 0x3e, 0xb1, 0xd5, 0xc6, 0xf7, 0x33, 0x80,
+       0x01, 0xfb, 0x59, 0x31, 0x9d, 0x91, 0xbe, 0xb2, 0x42, 0x06, 0x3d, 0xb5,
+       0x0c, 0xdf, 0x7b, 0xfa, 0x23, 0x80, 0x97, 0x93, 0x2f, 0x3a, 0x38, 0x7d,
+       0xfd, 0x09, 0xa0, 0x02, 0xf0, 0x5e, 0xcc, 0x44, 0x3b, 0x23, 0xe8, 0xb5,
+       0xc0, 0xb7, 0x5e, 0xee, 0x94, 0xc2, 0xa8, 0xf7, 0x2f, 0xde, 0x62, 0xdc,
+       0x6d, 0xce, 0xc7, 0x7d, 0xec, 0x93, 0x6d, 0x88, 0xcf, 0x1d, 0x12, 0xf1,
+       0xad, 0xc5, 0x9d, 0x95, 0x45, 0x5b, 0xa1, 0xbc, 0x7a, 0xff, 0x64, 0xc2,
+       0x7f, 0xf2, 0x74, 0x4e, 0x97, 0xab, 0x43, 0x0e, 0x92, 0x7f, 0x33, 0x04,
+       0x1f, 0x5c, 0x6a, 0x0c, 0x19, 0x48, 0xcf, 0x7e, 0x96, 0xfb, 0xf1, 0xa0,
+       0x7f, 0xd2, 0x97, 0x1b, 0xe0, 0xa3, 0xcc, 0xb2, 0xe1, 0x70, 0x40, 0xfe,
+       0xad, 0xa1, 0x87, 0x90, 0x36, 0x0e, 0x31, 0xa3, 0x4f, 0xf0, 0xd3, 0xbd,
+       0x71, 0xf1, 0x87, 0x82, 0x38, 0xbe, 0xde, 0x97, 0xf0, 0x3d, 0xe8, 0x79,
+       0x5a, 0xfa, 0x08, 0xaa, 0x72, 0x87, 0xf3, 0x39, 0xe6, 0xc9, 0x40, 0x3e,
+       0xa7, 0xf2, 0x61, 0x8b, 0xd3, 0x3f, 0x2d, 0x95, 0xf0, 0x50, 0x98, 0x81,
+       0xf8, 0x05, 0x7c, 0x72, 0x3e, 0xb9, 0x4f, 0x22, 0xb8, 0x36, 0xb2, 0x16,
+       0x2e, 0x37, 0x04, 0xbf, 0x8f, 0x8e, 0x2b, 0xe4, 0xc5, 0x49, 0x39, 0xc8,
+       0xe5, 0x92, 0x71, 0x13, 0x3d, 0xe7, 0xa5, 0xe6, 0x13, 0xde, 0x56, 0xa3,
+       0xbc, 0x21, 0xbf, 0x3a, 0xb7, 0xff, 0x46, 0xa3, 0x83, 0x79, 0xa9, 0x3a,
+       0x61, 0x27, 0x8c, 0x4c, 0x07, 0xd7, 0x0a, 0x3a, 0x68, 0x38, 0xc5, 0xc2,
+       0x57, 0xc2, 0x78, 0x0d, 0xeb, 0x58, 0xb8, 0x71, 0x0a, 0x7f, 0xda, 0xa6,
+       0x90, 0x1c, 0xe4, 0xf2, 0xd0, 0x24, 0xe2, 0x1d, 0x26, 0x1e, 0x0f, 0xf9,
+       0x26, 0xb9, 0x98, 0x28, 0x07, 0x87, 0xc9, 0xbd, 0x04, 0x79, 0x97, 0x61,
+       0x10, 0xf2, 0x4d, 0xe0, 0x39, 0xde, 0xdf, 0x8d, 0xf2, 0x7e, 0xc6, 0xba,
+       0x90, 0x8c, 0x7e, 0xcf, 0x5c, 0xbb, 0xaf, 0x32, 0x63, 0x5a, 0x4c, 0x7f,
+       0x69, 0x7e, 0xdf, 0x64, 0xf2, 0x5c, 0x86, 0x65, 0x3f, 0x2b, 0xb0, 0xa2,
+       0xff, 0xa6, 0xf2, 0x59, 0x37, 0xfa, 0x7f, 0xc1, 0x5e, 0xc7, 0x7d, 0x65,
+       0x01, 0xb8, 0xec, 0x42, 0xf9, 0xa2, 0xea, 0xb7, 0x6e, 0xbe, 0x5e, 0xb7,
+       0x81, 0xd3, 0xaf, 0x5e, 0xf1, 0xb3, 0x52, 0x2b, 0xe2, 0x65, 0x90, 0xec,
+       0xd9, 0xa1, 0x34, 0x66, 0x47, 0x7a, 0x54, 0xe1, 0xb9, 0xc3, 0x06, 0xdf,
+       0x95, 0xe1, 0x77, 0x7c, 0xbf, 0x45, 0xbf, 0x37, 0xb1, 0xce, 0xa4, 0xb8,
+       0xef, 0xab, 0x5e, 0x35, 0x13, 0x5f, 0x3d, 0xff, 0x8a, 0x2d, 0x64, 0x24,
+       0xbd, 0x23, 0x90, 0xe7, 0x80, 0xfe, 0xd2, 0x3f, 0x32, 0x92, 0x1e, 0x7a,
+       0xe6, 0x55, 0x1b, 0xc9, 0xcf, 0x33, 0x42, 0xfe, 0xb9, 0x54, 0xbf, 0x00,
+       0x5b, 0x4f, 0xf8, 0x59, 0x27, 0xf0, 0x1a, 0x64, 0x55, 0x63, 0xd0, 0xbf,
+       0xca, 0xa4, 0x79, 0x63, 0x90, 0x05, 0xaa, 0x7a, 0x58, 0xa3, 0x63, 0x34,
+       0x7f, 0xb7, 0xa8, 0xcf, 0x1f, 0xbc, 0x91, 0xd3, 0x95, 0x91, 0xec, 0xc9,
+       0xf3, 0x8e, 0xc8, 0xf7, 0xb1, 0x0c, 0xf3, 0x61, 0xa8, 0x5f, 0xdf, 0x25,
+       0xf0, 0xdc, 0xbc, 0x7f, 0x56, 0xe9, 0xbd, 0xf0, 0xbe, 0xd9, 0x6f, 0xf5,
+       0x72, 0xe8, 0x07, 0x4a, 0x91, 0x5e, 0x8d, 0xf2, 0x5d, 0x37, 0xa2, 0xdf,
+       0x65, 0x8e, 0xbc, 0x6e, 0xe8, 0x6e, 0x58, 0x47, 0x63, 0x8e, 0xd5, 0x6e,
+       0x84, 0x4f, 0xaa, 0xf3, 0xfe, 0xf5, 0x37, 0x37, 0x43, 0xf9, 0xd3, 0xfd,
+       0x7a, 0x66, 0x44, 0x3c, 0xef, 0x99, 0x55, 0xc7, 0x0a, 0x46, 0xe7, 0xbf,
+       0xab, 0x42, 0xfa, 0x63, 0x91, 0xb8, 0xfd, 0xb2, 0x66, 0xaf, 0xb6, 0xdc,
+       0xd8, 0xa7, 0x2d, 0x37, 0x33, 0xe5, 0x58, 0x24, 0x8e, 0x1f, 0x3f, 0x9e,
+       0x6a, 0x73, 0x9d, 0x9c, 0x44, 0xbc, 0xc3, 0x7b, 0x11, 0xe8, 0xdb, 0x68,
+       0x6c, 0x39, 0xb5, 0x0b, 0xe6, 0x6b, 0xfc, 0xa9, 0x91, 0xe4, 0x51, 0x4b,
+       0x6a, 0x20, 0x94, 0x9a, 0x86, 0x7a, 0xf9, 0xd0, 0x9b, 0x08, 0x67, 0x63,
+       0xde, 0xe7, 0x53, 0xd0, 0x8f, 0x51, 0x95, 0xf7, 0x27, 0x8a, 0xfb, 0x9c,
+       0xff, 0x01, 0xf3, 0xe2, 0xbc, 0xcf, 0x9b, 0x2b, 0x49, 0x7e, 0x9f, 0xdf,
+       0x6a, 0xf6, 0x04, 0xe3, 0xf8, 0x57, 0xb3, 0xa0, 0xff, 0xde, 0xdc, 0x5a,
+       0xaa, 0xef, 0xdd, 0x66, 0xf4, 0x48, 0xbc, 0xbe, 0x76, 0x5a, 0x05, 0xea,
+       0x83, 0x34, 0x36, 0xfe, 0x99, 0x74, 0x00, 0xff, 0xe6, 0x2d, 0x73, 0x3f,
+       0x25, 0xbb, 0x09, 0xb5, 0x76, 0x28, 0xf7, 0xa2, 0x7e, 0x89, 0xdf, 0xbd,
+       0x20, 0x85, 0xda, 0x51, 0x7f, 0xdc, 0xc2, 0xe5, 0xde, 0x69, 0xd0, 0x1f,
+       0x4d, 0x30, 0x9f, 0x93, 0x08, 0x67, 0x8c, 0x7b, 0xc8, 0x03, 0x73, 0x4c,
+       0xf0, 0x9f, 0xbd, 0xce, 0x9a, 0x09, 0xc8, 0x5f, 0x94, 0x3f, 0x2b, 0x7e,
+       0xc4, 0xff, 0x03, 0xd8, 0x55, 0x9c, 0xbe, 0x7b, 0x20, 0xca, 0xa7, 0xb9,
+       0x9f, 0xe7, 0x5a, 0xf4, 0xf3, 0x8c, 0x25, 0x3f, 0xcf, 0x01, 0xe4, 0x1b,
+       0x8d, 0xa6, 0x88, 0xa1, 0x12, 0xfa, 0xb9, 0xfa, 0xcf, 0x5f, 0x11, 0x5f,
+       0x5e, 0xd9, 0xba, 0x84, 0xf4, 0xfa, 0x98, 0x9e, 0x6b, 0x24, 0x3e, 0xb2,
+       0xf2, 0xee, 0x00, 0xbd, 0x7f, 0x7d, 0xeb, 0x35, 0xb4, 0xae, 0x93, 0xb0,
+       0x6e, 0x84, 0xcf, 0xc9, 0x1d, 0xdc, 0x9e, 0x5b, 0x99, 0x6d, 0x0d, 0xe1,
+       0xfc, 0xae, 0x76, 0x70, 0xfd, 0x77, 0x25, 0x7c, 0x27, 0x49, 0xc3, 0xe1,
+       0x92, 0x08, 0x87, 0x4f, 0xb6, 0x5f, 0xe3, 0x46, 0x7c, 0x7f, 0xc2, 0xf8,
+       0x78, 0xc1, 0x3e, 0xae, 0x27, 0x7c, 0x62, 0x1f, 0x4c, 0x26, 0xfe, 0xe3,
+       0x69, 0x49, 0x46, 0x3d, 0xaf, 0x79, 0xcb, 0x35, 0x9f, 0x22, 0xdf, 0x5a,
+       0xb9, 0x43, 0xf6, 0xa2, 0x1c, 0x67, 0x07, 0x6c, 0xe4, 0x17, 0x59, 0xb9,
+       0x63, 0xf6, 0x84, 0xe5, 0x56, 0xec, 0xe7, 0xcb, 0xd4, 0x4a, 0x84, 0xdb,
+       0xce, 0xd9, 0x76, 0x99, 0xde, 0xcb, 0xfe, 0x10, 0xf7, 0xaf, 0x0c, 0x5e,
+       0x0d, 0xef, 0x95, 0x9d, 0x97, 0x7b, 0x70, 0x9f, 0x1c, 0xde, 0x61, 0xe4,
+       0xf3, 0x73, 0x98, 0x9e, 0xc6, 0xf9, 0x5f, 0xfd, 0x67, 0x99, 0xe8, 0x5e,
+       0xd1, 0xb1, 0x00, 0xea, 0xab, 0xbd, 0x06, 0xdf, 0x04, 0xdc, 0x6f, 0x9e,
+       0xed, 0x7b, 0xe6, 0x20, 0x5c, 0x3f, 0x99, 0x9f, 0xa5, 0xa3, 0xf6, 0xcf,
+       0x4b, 0xcc, 0x8e, 0x70, 0x70, 0xb4, 0xa6, 0xe3, 0xfb, 0x95, 0x92, 0xe2,
+       0xc7, 0xfd, 0x55, 0xbf, 0x65, 0x55, 0x6d, 0xbc, 0x3e, 0xd2, 0x95, 0x2a,
+       0x13, 0x7e, 0x2a, 0xf3, 0xd6, 0xa5, 0x47, 0xac, 0x44, 0xef, 0x37, 0xa2,
+       0x9c, 0x6b, 0xdc, 0xa1, 0x27, 0xbd, 0xee, 0xf0, 0x82, 0x0f, 0x7f, 0x73,
+       0xb3, 0x2b, 0x46, 0xef, 0x2b, 0xe5, 0x9e, 0x1b, 0x67, 0xc4, 0xe9, 0x1b,
+       0xcd, 0xdb, 0xbf, 0x2d, 0xe8, 0x01, 0x24, 0x36, 0xc0, 0x69, 0xa5, 0x80,
+       0x93, 0x31, 0x6f, 0x5d, 0x11, 0x8e, 0xfb, 0x4d, 0xf4, 0xbf, 0xf2, 0xbe,
+       0x96, 0x22, 0x1e, 0xaf, 0xf9, 0xfa, 0x7d, 0x10, 0xdd, 0xdf, 0xdb, 0xf9,
+       0x7e, 0xf8, 0x33, 0xc8, 0xfb, 0x8b, 0xe8, 0xef, 0xcb, 0x76, 0x6a, 0xf4,
+       0xfb, 0xd1, 0xec, 0x20, 0xd5, 0x1f, 0x6d, 0xf2, 0x32, 0xdf, 0x1e, 0x2b,
+       0xc5, 0x15, 0x7d, 0x68, 0xe7, 0x16, 0xb8, 0x14, 0xaa, 0x2f, 0x40, 0x02,
+       0x02, 0xfa, 0x52, 0xfe, 0xb0, 0x76, 0xef, 0x3b, 0x30, 0xff, 0xfd, 0xa9,
+       0x01, 0x8b, 0x0b, 0xca, 0x79, 0xcc, 0x57, 0x8a, 0x78, 0xf5, 0x0c, 0xd9,
+       0xab, 0x40, 0x9d, 0xc4, 0x25, 0x91, 0xfe, 0xc3, 0xb6, 0x1b, 0xb9, 0x3e,
+       0xa9, 0x70, 0xbf, 0xdc, 0xe6, 0x34, 0xf6, 0xf4, 0x86, 0xb8, 0x79, 0xe6,
+       0x8a, 0xfe, 0x60, 0x7f, 0xba, 0xb0, 0x9f, 0x33, 0x1f, 0xfc, 0xe9, 0x4d,
+       0x84, 0x5f, 0x53, 0xee, 0xe7, 0x53, 0x78, 0xbc, 0xed, 0x2b, 0x8a, 0x5f,
+       0x59, 0x07, 0x78, 0x5c, 0xd3, 0xea, 0xf5, 0x33, 0xa4, 0x8b, 0xe6, 0x81,
+       0xf9, 0x6c, 0x59, 0x49, 0x8c, 0x1f, 0x36, 0x7b, 0x39, 0xbf, 0x1e, 0xc6,
+       0x57, 0x5c, 0x7a, 0xce, 0xbf, 0x5c, 0x43, 0xd4, 0x4f, 0x4d, 0x1a, 0xe7,
+       0x67, 0xaa, 0x3f, 0x78, 0x5b, 0x6b, 0x12, 0xf9, 0xfd, 0xb6, 0xb9, 0x42,
+       0x66, 0x6e, 0xdf, 0x06, 0x19, 0xf2, 0xf3, 0xeb, 0xca, 0x65, 0x1e, 0x8f,
+       0x11, 0x7a, 0x89, 0x5f, 0xf8, 0xd1, 0x4c, 0xbe, 0xd7, 0x19, 0xc6, 0x6b,
+       0x98, 0x57, 0xf6, 0x8e, 0x83, 0xf2, 0xa0, 0xef, 0x78, 0x67, 0x2a, 0x94,
+       0xdf, 0x29, 0x9f, 0xed, 0x95, 0xa1, 0x6c, 0xf5, 0x3d, 0xd9, 0x55, 0x80,
+       0xeb, 0xf6, 0xea, 0x45, 0xfd, 0x58, 0xf2, 0x27, 0xbe, 0x3d, 0xb3, 0x92,
+       0xf4, 0x93, 0xeb, 0x7c, 0x32, 0x8d, 0xcb, 0xea, 0x93, 0xc9, 0x5e, 0x1f,
+       0xf4, 0xbd, 0xe7, 0x5a, 0x06, 0xe3, 0x5e, 0xcf, 0x7c, 0xa9, 0x27, 0x60,
+       0x8c, 0x1a, 0x10, 0xd6, 0x88, 0xc7, 0x41, 0x1c, 0x1b, 0xf0, 0x65, 0x54,
+       0x02, 0xd3, 0x5d, 0x71, 0x76, 0xd3, 0xb7, 0xbd, 0x73, 0x53, 0x4f, 0xc4,
+       0xcb, 0x4b, 0x1f, 0x97, 0xff, 0x68, 0x8f, 0xf7, 0x89, 0xb8, 0xc2, 0x48,
+       0x70, 0xf0, 0xa6, 0x56, 0x5e, 0x85, 0xf0, 0xbd, 0xfa, 0x2a, 0x8e, 0x87,
+       0xcf, 0x9e, 0xe7, 0xf6, 0xc7, 0x67, 0x66, 0xee, 0xe7, 0x56, 0xdb, 0x7d,
+       0x66, 0xe3, 0x72, 0xc6, 0xef, 0x52, 0xfd, 0x84, 0x7d, 0xb9, 0xc8, 0xe7,
+       0xa3, 0xe5, 0xdb, 0x8a, 0x35, 0x71, 0x62, 0x97, 0xa1, 0x2f, 0x17, 0xf7,
+       0xd9, 0x6f, 0x25, 0x6d, 0x3f, 0xab, 0xbb, 0x74, 0x14, 0xbf, 0x5d, 0xd5,
+       0xc5, 0x28, 0x5e, 0xfb, 0xd9, 0x8f, 0x5e, 0xce, 0x45, 0x7e, 0xfb, 0xe9,
+       0x9e, 0x97, 0x73, 0x97, 0xc4, 0xcd, 0x2f, 0xf1, 0x3b, 0xf5, 0x79, 0x8b,
+       0x3a, 0x9e, 0xf0, 0x4b, 0xa9, 0x7e, 0x4a, 0x97, 0x88, 0x5b, 0x2f, 0xf1,
+       0x1a, 0xb9, 0x3f, 0x70, 0x14, 0x3f, 0xa5, 0xda, 0x9e, 0x6d, 0xe1, 0xf6,
+       0xd8, 0x59, 0xe0, 0xee, 0x48, 0x77, 0xea, 0x77, 0x67, 0xeb, 0x93, 0x7c,
+       0xa8, 0x57, 0x9e, 0x65, 0x26, 0xe2, 0x67, 0x4b, 0x06, 0x84, 0xdf, 0xd3,
+       0xe7, 0x2b, 0x74, 0xa1, 0xfd, 0xa0, 0x7e, 0x9f, 0xd0, 0xff, 0x23, 0x82,
+       0x7e, 0xa4, 0x7e, 0x89, 0xec, 0x73, 0x4b, 0xc9, 0x10, 0xf1, 0xd7, 0x55,
+       0x26, 0xff, 0x9b, 0x63, 0x3c, 0x98, 0xb7, 0xe2, 0x23, 0xfc, 0xcc, 0x45,
+       0x3c, 0x4a, 0x48, 0xaf, 0x3e, 0x03, 0xae, 0x5b, 0x11, 0x76, 0x9e, 0x51,
+       0xf1, 0xdf, 0x81, 0x78, 0x58, 0xde, 0xa3, 0xc5, 0x63, 0x8e, 0x4b, 0xc4,
+       0x33, 0xec, 0x2e, 0xc2, 0xbb, 0xa1, 0xc9, 0xaa, 0xa0, 0x7c, 0x48, 0xef,
+       0x10, 0xfc, 0xfa, 0x7b, 0x3a, 0xb2, 0x5f, 0x0c, 0x59, 0x6e, 0x2b, 0xf2,
+       0xa5, 0xab, 0x8b, 0x92, 0x3a, 0x31, 0x2e, 0xef, 0x4a, 0x4a, 0x9e, 0x82,
+       0x7e, 0xf5, 0x9c, 0xac, 0x62, 0x6a, 0x1f, 0xac, 0xe2, 0x74, 0x1d, 0x4c,
+       0x67, 0xe4, 0xb7, 0xca, 0x64, 0x2d, 0x12, 0xf1, 0x5b, 0x3b, 0xf7, 0x83,
+       0x67, 0x4f, 0x67, 0x76, 0xcc, 0x03, 0xf9, 0xa9, 0x8b, 0xeb, 0x0d, 0x6e,
+       0xe6, 0xdd, 0x22, 0x93, 0x3e, 0xd8, 0x27, 0x51, 0x3c, 0x40, 0xac, 0x5f,
+       0xe5, 0xeb, 0x48, 0x2f, 0xc8, 0xe7, 0x3e, 0x93, 0x4c, 0x44, 0x2f, 0xd2,
+       0x80, 0x44, 0xfa, 0x9d, 0xac, 0xeb, 0x5b, 0x84, 0xfd, 0x8e, 0x46, 0x3f,
+       0x5b, 0x5c, 0xaa, 0x5d, 0xcd, 0xe9, 0x27, 0x5a, 0xfe, 0x1b, 0xd1, 0xcf,
+       0x6e, 0x75, 0xbc, 0x61, 0xf4, 0x13, 0xa0, 0x38, 0xde, 0x12, 0xb7, 0x69,
+       0x64, 0xfa, 0x11, 0x7e, 0xd7, 0x4b, 0x6e, 0x3f, 0x5a, 0x1c, 0xf1, 0x7b,
+       0x26, 0xd5, 0x0f, 0x2d, 0xe1, 0x7a, 0x6b, 0x45, 0x7f, 0xb5, 0x26, 0x6b,
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+       0x73, 0xa1, 0x81, 0xf4, 0xce, 0xe6, 0x7e, 0x29, 0x88, 0x78, 0x6e, 0xf2,
+       0x1b, 0x42, 0xa6, 0x7c, 0x8a, 0xbb, 0x2c, 0x26, 0xb9, 0xfd, 0xa0, 0xd9,
+       0xc3, 0xe3, 0x28, 0x9e, 0x76, 0x8a, 0xa3, 0xfc, 0xc0, 0xc3, 0xe3, 0x2c,
+       0x51, 0x3f, 0x6a, 0x64, 0xe7, 0xbd, 0x48, 0x6f, 0xf5, 0x56, 0xf2, 0x3b,
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+       0xf1, 0xe2, 0xe7, 0xa7, 0x24, 0xf4, 0xaf, 0x87, 0xfe, 0xad, 0x1e, 0xd1,
+       0x3e, 0xf8, 0xe3, 0xb9, 0xb3, 0x0b, 0x29, 0x6e, 0x29, 0xea, 0xa5, 0x0d,
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+       0xd4, 0xf1, 0x0e, 0x67, 0xd4, 0xfc, 0x70, 0xe3, 0xcc, 0x98, 0xdc, 0x07,
+       0x3d, 0xc0, 0x9a, 0x36, 0x2d, 0x26, 0xff, 0x1f, 0xf8, 0xb0, 0xb6, 0xe7,
+       0x32, 0x18, 0xcb, 0x62, 0xff, 0xd2, 0x80, 0x72, 0x55, 0x95, 0xe3, 0xcd,
+       0x2e, 0x9e, 0xff, 0x90, 0xb8, 0x5f, 0xd3, 0xd3, 0x38, 0xbf, 0x07, 0xfd,
+       0x35, 0x3d, 0x8d, 0xe4, 0x0e, 0xd7, 0x6b, 0x6b, 0x45, 0xfc, 0x12, 0xf4,
+       0xd9, 0x39, 0xb8, 0xb5, 0x9a, 0xd7, 0xf9, 0x19, 0xc6, 0x2f, 0x41, 0x5f,
+       0xc8, 0x4a, 0x23, 0x7d, 0xe1, 0xf3, 0x93, 0x07, 0x11, 0x7f, 0x0b, 0x3e,
+       0x23, 0x7d, 0xbe, 0xf9, 0x82, 0xc2, 0xfd, 0x2e, 0xa0, 0x77, 0xa0, 0x7e,
+       0x6e, 0x12, 0x74, 0xce, 0xfa, 0xf5, 0x24, 0x6f, 0x55, 0x3a, 0x58, 0x2d,
+       0xf8, 0x4f, 0xaf, 0x03, 0xe4, 0x3d, 0xd2, 0xeb, 0x01, 0x69, 0x5a, 0x90,
+       0xe8, 0xa2, 0x25, 0xf7, 0x06, 0xc0, 0xc1, 0xdf, 0xa7, 0xf9, 0x0a, 0x71,
+       0x1e, 0xaa, 0xdd, 0x95, 0x38, 0xdf, 0x2b, 0xd3, 0xb8, 0x7d, 0xdc, 0x5c,
+       0x5c, 0xb5, 0xb5, 0x08, 0xfb, 0x7f, 0x4a, 0x62, 0x28, 0xef, 0x37, 0x14,
+       0x1f, 0x4b, 0x47, 0xbd, 0xa4, 0x79, 0xe0, 0xe3, 0xf4, 0xe5, 0x71, 0xdf,
+       0xad, 0xea, 0x7f, 0x94, 0xe0, 0xb0, 0x6a, 0xaf, 0x7e, 0xc4, 0xf5, 0x5f,
+       0x99, 0xc6, 0xe3, 0x9d, 0x4d, 0xaf, 0xbc, 0x48, 0xfe, 0xc1, 0xcf, 0x42,
+       0x12, 0xed, 0xe5, 0x7a, 0x25, 0xd4, 0x3d, 0x03, 0xca, 0xf5, 0xf5, 0x3a,
+       0xd4, 0xd0, 0x58, 0x79, 0x68, 0xf1, 0xcd, 0xe4, 0xef, 0xaf, 0x33, 0xb0,
+       0x71, 0xb0, 0xbe, 0xb1, 0x28, 0x8f, 0x70, 0x1e, 0x7b, 0xbf, 0x13, 0x9c,
+       0x81, 0xf6, 0x19, 0xfc, 0x93, 0xe0, 0xd5, 0x36, 0xff, 0x0a, 0x92, 0x7b,
+       0xdb, 0xea, 0x4c, 0x56, 0x8c, 0x3b, 0x34, 0x17, 0x2f, 0xb9, 0x83, 0xe0,
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+       0xf3, 0xe7, 0xd8, 0x29, 0x4e, 0x00, 0xfa, 0x15, 0xd6, 0x37, 0xdd, 0x7d,
+       0x0b, 0xf9, 0x4d, 0xd4, 0x79, 0x6d, 0xe8, 0xd7, 0xd7, 0xa0, 0xde, 0x55,
+       0x01, 0x7a, 0xd6, 0x3f, 0xc1, 0xbc, 0x73, 0x9c, 0xf3, 0x6a, 0xbc, 0xb0,
+       0xff, 0xc6, 0xc8, 0xfb, 0x4a, 0xef, 0xb4, 0x62, 0xdc, 0x78, 0x64, 0xfe,
+       0xfb, 0x5e, 0x3a, 0xc7, 0x67, 0xa7, 0xe4, 0x0f, 0x5e, 0x5f, 0x4e, 0x7e,
+       0x42, 0x16, 0xef, 0xf7, 0xcb, 0xeb, 0xe7, 0xfa, 0xdc, 0x0d, 0x69, 0x06,
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+       0x69, 0xef, 0x35, 0x25, 0x62, 0x41, 0xbd, 0xb7, 0x99, 0xf9, 0xbe, 0x40,
+       0xfb, 0x92, 0xf9, 0xad, 0x9e, 0x3d, 0x84, 0x27, 0xce, 0x47, 0x5c, 0x6d,
+       0x1e, 0xf2, 0x1f, 0x99, 0x5c, 0x91, 0x1f, 0x5e, 0x86, 0xf5, 0x33, 0x15,
+       0xb2, 0x1f, 0x98, 0x12, 0x79, 0x04, 0xc7, 0x3d, 0xd3, 0xed, 0xf2, 0x6e,
+       0x60, 0x82, 0x7e, 0xb1, 0x7c, 0x77, 0x49, 0x08, 0xf9, 0xe8, 0xeb, 0x69,
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+       0xf4, 0xb3, 0xa9, 0xfa, 0x51, 0xf7, 0x2e, 0x73, 0x08, 0xe3, 0x84, 0xdd,
+       0x36, 0xcf, 0x3f, 0xd4, 0x20, 0x1f, 0xfc, 0x83, 0xc2, 0xe3, 0xe2, 0xa6,
+       0xa1, 0xc1, 0x59, 0x88, 0x8f, 0x3f, 0x3a, 0xa9, 0xdf, 0x6e, 0x73, 0xa8,
+       0x1b, 0xf1, 0x1f, 0xdc, 0xa4, 0xa7, 0xfa, 0x57, 0x6c, 0x81, 0x46, 0xa4,
+       0xcb, 0x53, 0xf3, 0x6b, 0x8a, 0x28, 0x2f, 0xc7, 0x1a, 0x2c, 0xc2, 0x38,
+       0xb0, 0xde, 0xd5, 0xc3, 0x50, 0x4f, 0x00, 0x73, 0x81, 0xfc, 0x09, 0x26,
+       0x97, 0x9f, 0x61, 0xbc, 0x74, 0x56, 0x70, 0xb1, 0x22, 0x21, 0x9f, 0x4f,
+       0xd0, 0x3b, 0x66, 0x89, 0xfc, 0x52, 0x62, 0x9e, 0xf0, 0xbe, 0x4a, 0xb0,
+       0xb1, 0x71, 0x40, 0x05, 0x27, 0x4d, 0xb4, 0x05, 0x3a, 0x2f, 0xa6, 0xc6,
+       0xf4, 0x90, 0x23, 0x7f, 0x5a, 0xa8, 0xe0, 0x4b, 0x55, 0x3f, 0xd1, 0x99,
+       0x78, 0x3c, 0xab, 0xba, 0x2e, 0x89, 0xc9, 0x48, 0xf7, 0xeb, 0x87, 0xde,
+       0xd4, 0xa1, 0xff, 0xda, 0x35, 0x48, 0xfa, 0x6b, 0x63, 0x9f, 0x44, 0xe3,
+       0x34, 0x16, 0xbf, 0x40, 0xf9, 0x62, 0x6b, 0x44, 0x5e, 0x52, 0x34, 0x3f,
+       0x48, 0x89, 0x50, 0xbe, 0xd4, 0xfa, 0x34, 0x8b, 0xd0, 0x03, 0x3b, 0xb9,
+       0x1e, 0xcd, 0x06, 0xc9, 0x5e, 0x66, 0xcf, 0x71, 0x7c, 0x32, 0x16, 0xa1,
+       0x3c, 0xaa, 0x98, 0x1d, 0xd1, 0x4e, 0xed, 0xd4, 0xfe, 0x0c, 0xc2, 0xef,
+       0xde, 0x28, 0xfc, 0x2e, 0x20, 0xc1, 0xa8, 0x7e, 0x53, 0x9a, 0xaa, 0x5f,
+       0xde, 0xa7, 0xf5, 0xd7, 0x8b, 0x71, 0x37, 0x4b, 0x83, 0x3e, 0x19, 0xe1,
+       0x5a, 0x2a, 0x69, 0xfc, 0xc5, 0xea, 0x73, 0xaf, 0xf8, 0x3e, 0xe5, 0xd0,
+       0xd0, 0x1c, 0xdc, 0xbf, 0x43, 0xaf, 0xa8, 0x79, 0x9c, 0x3c, 0x4f, 0x73,
+       0xeb, 0xb4, 0x89, 0x5e, 0x54, 0x9d, 0x86, 0xe5, 0x71, 0xf6, 0x7f, 0x31,
+       0x07, 0xe9, 0x06, 0x14, 0x6d, 0xda, 0xaf, 0x4d, 0xfd, 0x97, 0x96, 0xc7,
+       0xf9, 0xbc, 0xd8, 0x67, 0xff, 0xe3, 0x79, 0x9c, 0x5e, 0xc9, 0xb7, 0x1b,
+       0x9e, 0x2f, 0xa7, 0x39, 0xb4, 0x79, 0x9c, 0x5e, 0x0e, 0x3f, 0x35, 0xce,
+       0x96, 0x98, 0xbf, 0x79, 0x26, 0x33, 0xac, 0xf0, 0x7c, 0xac, 0xc8, 0xce,
+       0x3d, 0x48, 0x9f, 0xfd, 0x46, 0xca, 0xf3, 0xaa, 0xed, 0xff, 0xd9, 0xfb,
+       0x28, 0x1f, 0x6b, 0x4d, 0xac, 0x0f, 0xe3, 0x90, 0x89, 0x7a, 0x46, 0x9b,
+       0xfd, 0x3b, 0x61, 0xa4, 0xfb, 0xb3, 0xa7, 0x4f, 0xee, 0xbc, 0x9f, 0x61,
+       0x1e, 0xef, 0x4b, 0x5e, 0xca, 0xe7, 0x48, 0xd0, 0x1f, 0x12, 0xed, 0x84,
+       0xdd, 0xd8, 0x24, 0x73, 0x74, 0x7d, 0xef, 0x37, 0x51, 0x7c, 0x72, 0x7d,
+       0x2f, 0x5a, 0xfe, 0x1f, 0xd7, 0xf7, 0xb8, 0x3e, 0x1f, 0xdc, 0xc3, 0xf3,
+       0x07, 0x54, 0x7e, 0xde, 0x2c, 0xec, 0xb3, 0xb3, 0xf5, 0xe7, 0x92, 0x51,
+       0xce, 0x1c, 0x4b, 0x53, 0xf5, 0xcf, 0x84, 0x3c, 0x87, 0xa7, 0x44, 0x9e,
+       0xc3, 0xc0, 0xc8, 0x79, 0x0e, 0x8a, 0xc8, 0x17, 0x02, 0x7d, 0x3d, 0x48,
+       0x74, 0xb2, 0x8f, 0xc7, 0x75, 0x8e, 0x3c, 0x6d, 0x21, 0xfe, 0x71, 0xce,
+       0xae, 0xec, 0x46, 0x7d, 0xe9, 0xb4, 0x6d, 0xe8, 0xfb, 0x08, 0x2c, 0x45,
+       0xe8, 0x49, 0x9d, 0x07, 0x8c, 0x1e, 0xe4, 0x17, 0xc0, 0xef, 0x88, 0x7f,
+       0x07, 0xf7, 0xe9, 0x79, 0x9c, 0x06, 0xe3, 0x36, 0x18, 0xc7, 0x79, 0x6d,
+       0x82, 0x88, 0xe3, 0x88, 0x78, 0xd1, 0xab, 0x16, 0xd2, 0x5b, 0x1a, 0x92,
+       0x3d, 0x29, 0xf8, 0xbd, 0x1a, 0xa7, 0xf9, 0xa9, 0x90, 0x37, 0x0d, 0x49,
+       0x3c, 0x3e, 0xd3, 0x65, 0x09, 0xfc, 0x3e, 0x6d, 0x84, 0xb8, 0xcd, 0x2e,
+       0xa1, 0x7f, 0xed, 0x82, 0xae, 0xec, 0xd8, 0xdf, 0xfb, 0x46, 0x11, 0xc7,
+       0x06, 0x06, 0x81, 0xf6, 0xce, 0x83, 0x39, 0x3c, 0xee, 0x20, 0xe2, 0x36,
+       0x67, 0x45, 0xdc, 0xe6, 0x78, 0xb1, 0x2e, 0x6c, 0xe0, 0x7e, 0x08, 0xf2,
+       0x53, 0x79, 0xba, 0x14, 0x96, 0x09, 0xf5, 0x9e, 0xf7, 0xcd, 0x21, 0x0f,
+       0xf7, 0x67, 0x99, 0x74, 0x20, 0xf7, 0x97, 0xaa, 0x71, 0x9b, 0xd7, 0xb8,
+       0x9f, 0x6a, 0xa9, 0x88, 0xcf, 0x1c, 0x5f, 0x30, 0x87, 0xf2, 0x87, 0x96,
+       0x63, 0x7e, 0xbc, 0x8c, 0x7e, 0x0c, 0xee, 0x67, 0x8e, 0xe6, 0xeb, 0x33,
+       0xbb, 0x0e, 0xd7, 0xb3, 0x06, 0xd8, 0xc5, 0x36, 0x64, 0x31, 0x41, 0x80,
+       0xfa, 0xe5, 0xf0, 0x5a, 0xd2, 0x49, 0xa8, 0x4f, 0x78, 0x3a, 0xa1, 0x4c,
+       0xca, 0xb2, 0xaf, 0xa7, 0x06, 0xc6, 0x5d, 0xd2, 0xa9, 0x23, 0x7b, 0x64,
+       0x69, 0x97, 0xd6, 0x5f, 0x7e, 0x7e, 0xc3, 0x1d, 0x35, 0x28, 0xbf, 0x1f,
+       0xe8, 0xe4, 0xf1, 0xc7, 0x60, 0x97, 0x44, 0xf2, 0x7b, 0x29, 0xf3, 0xb9,
+       0x51, 0xdf, 0x50, 0xe9, 0x61, 0x5c, 0x7a, 0x2a, 0xd1, 0x59, 0xb0, 0x53,
+       0xe7, 0xc3, 0x71, 0xae, 0x4c, 0xe7, 0xfe, 0x04, 0x00, 0x7d, 0x88, 0xd6,
+       0x27, 0x9e, 0x9d, 0x7a, 0xe1, 0x67, 0x17, 0xf3, 0x68, 0x67, 0xba, 0x30,
+       0x3e, 0x75, 0x12, 0x7f, 0x3e, 0x60, 0x57, 0x6a, 0x46, 0x94, 0xcb, 0xa2,
+       0xbf, 0x4e, 0x7d, 0x8b, 0xa9, 0x12, 0xf5, 0xd8, 0x1c, 0x1d, 0xf9, 0x79,
+       0xcf, 0x1b, 0x7c, 0x75, 0xe4, 0x27, 0x75, 0x16, 0x11, 0xde, 0x3a, 0x6d,
+       0x2d, 0x5d, 0x35, 0xbc, 0x9e, 0xf6, 0xca, 0x79, 0xf3, 0x90, 0x9f, 0xea,
+       0xaf, 0x54, 0xb8, 0xa2, 0xc7, 0x3c, 0x4e, 0xe4, 0x93, 0x63, 0xd2, 0x45,
+       0xfc, 0x26, 0x61, 0xbd, 0xcb, 0x7b, 0xb4, 0xe5, 0xc4, 0xf8, 0xc3, 0xaa,
+       0x90, 0xb6, 0xbc, 0x94, 0x05, 0xc6, 0x67, 0xe2, 0x39, 0x85, 0xbd, 0xda,
+       0xf7, 0x63, 0xd2, 0x39, 0xff, 0x3f, 0xbf, 0x21, 0x5f, 0xf8, 0xf9, 0xbd,
+       0xe4, 0xe7, 0xef, 0xd4, 0x7b, 0x7e, 0x95, 0x8f, 0x7c, 0xaa, 0x5b, 0x21,
+       0x3e, 0xd9, 0x9e, 0xcd, 0xe1, 0xa5, 0xcb, 0xe1, 0xcf, 0x02, 0x47, 0x75,
+       0x1d, 0xe9, 0x07, 0x0e, 0xd0, 0x2b, 0x68, 0xbe, 0x7c, 0xfe, 0x05, 0x57,
+       0xba, 0x24, 0x94, 0x97, 0x9d, 0x0e, 0x4e, 0x97, 0xff, 0xdd, 0x79, 0x27,
+       0xce, 0x77, 0x76, 0x7a, 0x11, 0xd7, 0x13, 0x50, 0xb9, 0xc3, 0x7d, 0xd4,
+       0x2d, 0x85, 0x38, 0xbc, 0xf8, 0xbc, 0x2f, 0xd5, 0x5f, 0xb1, 0x22, 0x5d,
+       0x6b, 0x6f, 0x46, 0xcb, 0xff, 0xf3, 0xf6, 0x26, 0xa7, 0xc7, 0x6e, 0x59,
+       0xec, 0x37, 0x3b, 0xf1, 0x9f, 0x25, 0x22, 0xde, 0x78, 0x5c, 0xf2, 0x3e,
+       0x1d, 0xc6, 0xf7, 0x56, 0xd0, 0x0b, 0x60, 0xde, 0x4b, 0xbb, 0xe5, 0x32,
+       0xd4, 0x4f, 0x66, 0x7d, 0xc7, 0x4a, 0xeb, 0x68, 0x7a, 0xcd, 0x1c, 0x32,
+       0x42, 0x7d, 0xe3, 0xba, 0x48, 0x2e, 0xee, 0xa3, 0xa6, 0xaa, 0x48, 0x51,
+       0xcb, 0x08, 0x70, 0xc5, 0xd9, 0x2a, 0x2a, 0xdf, 0x82, 0x76, 0x4b, 0x5c,
+       0x60, 0x1f, 0xe0, 0xbe, 0xed, 0xd2, 0xc6, 0xa1, 0x86, 0xc7, 0x15, 0x7d,
+       0xf7, 0xa6, 0xa7, 0xa1, 0x1d, 0x72, 0x7c, 0xdf, 0xcf, 0x10, 0xdf, 0xfb,
+       0xcc, 0x24, 0x97, 0xe0, 0xbf, 0x0e, 0x1a, 0xd1, 0xdf, 0xf1, 0x4a, 0x3e,
+       0xe9, 0x4b, 0x53, 0x52, 0x02, 0x1d, 0xe9, 0x28, 0xcf, 0x93, 0xc2, 0x3b,
+       0x9f, 0xc9, 0x47, 0xfd, 0x84, 0xeb, 0x47, 0x8d, 0x03, 0xc6, 0x5d, 0xa8,
+       0xff, 0x2d, 0xe9, 0xd4, 0x9e, 0xab, 0x61, 0x1b, 0xb5, 0x71, 0x2e, 0xd6,
+       0xe5, 0x24, 0x7f, 0x06, 0xeb, 0xd5, 0xbe, 0xc7, 0xf3, 0x2b, 0x9a, 0xef,
+       0x86, 0xc5, 0xbd, 0xb8, 0x9c, 0xdf, 0x6c, 0x08, 0x4c, 0x40, 0xbd, 0xee,
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+       0xc8, 0x6b, 0x16, 0x7e, 0xec, 0xc4, 0xfd, 0xaf, 0xee, 0xfb, 0xe8, 0x39,
+       0xc7, 0x5b, 0x4d, 0x14, 0x77, 0x56, 0xf9, 0xc2, 0x66, 0x3d, 0x0b, 0xa0,
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+       0x3f, 0xca, 0xa8, 0xf8, 0xbf, 0x8b, 0xed, 0xd9, 0xba, 0x9a, 0x58, 0x7c,
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+       0x80, 0x6e, 0x10, 0x3f, 0x33, 0x87, 0x06, 0x67, 0xe1, 0x79, 0xa2, 0xc2,
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+       0xc7, 0xa3, 0x9f, 0xc4, 0xfe, 0xeb, 0x2b, 0x11, 0x2f, 0x9e, 0x1e, 0x7b,
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+       0xb4, 0x1b, 0xab, 0xfe, 0x59, 0xcf, 0xf3, 0xfc, 0x0e, 0x58, 0xc8, 0xfe,
+       0xef, 0xcd, 0x6d, 0xa0, 0x3c, 0xbf, 0x33, 0x1f, 0x1a, 0x47, 0x3c, 0x17,
+       0xa2, 0x3e, 0x83, 0xec, 0x3e, 0xca, 0xeb, 0x2b, 0xe8, 0x7f, 0x8f, 0xfc,
+       0xf4, 0xb6, 0xfd, 0xd2, 0x88, 0xf9, 0x9a, 0x5d, 0x6e, 0x2b, 0x8f, 0x1f,
+       0x05, 0x07, 0x29, 0x7f, 0x8c, 0xcd, 0x74, 0xf1, 0xf3, 0x84, 0x07, 0x3e,
+       0xa2, 0xb8, 0xae, 0xd2, 0xad, 0x90, 0x87, 0xa2, 0x53, 0xef, 0xd3, 0xe1,
+       0x39, 0xa8, 0x60, 0x3b, 0x23, 0xff, 0xe4, 0xb8, 0x5e, 0xbb, 0x0e, 0xf1,
+       0x92, 0x27, 0xf2, 0x47, 0xce, 0xbe, 0xf6, 0x9f, 0x53, 0x02, 0x64, 0x87,
+       0xa8, 0x7e, 0xf9, 0x10, 0xcf, 0xf7, 0xd1, 0x47, 0xd6, 0xa3, 0x5d, 0xa5,
+       0xb4, 0x47, 0xae, 0x82, 0x1d, 0xcc, 0x1a, 0xf7, 0x3b, 0x74, 0x4d, 0x25,
+       0xd8, 0xdf, 0x50, 0x13, 0xcf, 0x5b, 0xb7, 0x30, 0xa4, 0x93, 0xbc, 0xfe,
+       0xb1, 0xf7, 0x7d, 0x0b, 0xca, 0x79, 0x5d, 0x76, 0x26, 0x21, 0xff, 0x79,
+       0x75, 0x4d, 0x1e, 0xf9, 0x43, 0x61, 0x9d, 0xe3, 0x46, 0x58, 0xe7, 0x1d,
+       0x6e, 0x9e, 0x9f, 0xa3, 0x1c, 0xb0, 0xe8, 0x50, 0x6e, 0x29, 0x9b, 0x18,
+       0xe5, 0x17, 0x2a, 0x8e, 0xf4, 0x2a, 0x9a, 0xf7, 0xa3, 0x50, 0x86, 0x7e,
+       0xd6, 0x08, 0xba, 0x51, 0xe3, 0x8d, 0x30, 0x5d, 0x37, 0xca, 0xa3, 0xdb,
+       0xdd, 0x81, 0x1d, 0x88, 0xef, 0xe8, 0x39, 0x98, 0xd6, 0x24, 0x7e, 0x0e,
+       0x46, 0x9c, 0xbb, 0xb4, 0xb5, 0x7e, 0xf8, 0x3c, 0x9e, 0x2f, 0xd9, 0x69,
+       0xe0, 0xe7, 0x0c, 0x0f, 0xbd, 0x36, 0x69, 0x01, 0xf9, 0xe5, 0xba, 0x15,
+       0x09, 0xf1, 0x70, 0xde, 0xb1, 0x38, 0xcf, 0x0e, 0xef, 0xf7, 0x8a, 0x7d,
+       0x6b, 0x53, 0x06, 0x99, 0xdd, 0x1a, 0x0f, 0xff, 0x43, 0x94, 0x4f, 0x59,
+       0x70, 0x80, 0xe7, 0x9d, 0x29, 0x7a, 0x4e, 0x27, 0x4a, 0xb7, 0x6b, 0x17,
+       0xfa, 0xfd, 0x2e, 0xa4, 0x04, 0x28, 0x6f, 0xf4, 0xca, 0xce, 0xb0, 0x4c,
+       0xf1, 0x2a, 0xfb, 0x89, 0x47, 0x6a, 0x3c, 0x71, 0x76, 0xcb, 0x16, 0x2e,
+       0x47, 0x9a, 0xf6, 0x72, 0x7b, 0x39, 0xd1, 0x4e, 0xf9, 0x26, 0xf9, 0x71,
+       0xd0, 0xad, 0xd5, 0x4b, 0xa2, 0xe5, 0xbf, 0x91, 0x5e, 0xf2, 0x76, 0x82,
+       0xdc, 0xf8, 0xab, 0xed, 0x0f, 0xa6, 0xb5, 0xdb, 0x12, 0xf5, 0x93, 0x44,
+       0x3b, 0x6d, 0x98, 0x5e, 0x9d, 0xd0, 0xdf, 0x68, 0x7a, 0x8a, 0x9a, 0xb7,
+       0x51, 0x15, 0x1b, 0x87, 0xe8, 0xe1, 0x75, 0x9b, 0xaa, 0x07, 0x05, 0x35,
+       0x79, 0x2d, 0x55, 0x56, 0x71, 0xae, 0xcd, 0xa4, 0xed, 0x7f, 0xaf, 0x8b,
+       0xf3, 0x09, 0x35, 0xcf, 0x25, 0xbd, 0xc3, 0xd3, 0x8e, 0x79, 0xe3, 0x43,
+       0x3f, 0x60, 0xe4, 0x47, 0x53, 0xf3, 0x6d, 0x82, 0x55, 0xdc, 0x2e, 0x08,
+       0xea, 0x4c, 0x74, 0xde, 0xcd, 0xcd, 0x7a, 0x28, 0xcf, 0x66, 0x0c, 0x0b,
+       0x4b, 0x12, 0xe9, 0xf7, 0x11, 0x3a, 0xd7, 0x99, 0x81, 0xf9, 0x36, 0xf0,
+       0xdd, 0x07, 0xee, 0x02, 0x7e, 0x3e, 0x85, 0x79, 0xbb, 0x64, 0xe2, 0x87,
+       0x1e, 0x09, 0xe7, 0x6d, 0xc6, 0x3c, 0x0d, 0xca, 0xcb, 0x0c, 0x6d, 0x5d,
+       0x81, 0xe3, 0xdc, 0x60, 0xa5, 0x71, 0xcc, 0x98, 0xa7, 0x31, 0x15, 0x43,
+       0xed, 0xbe, 0xad, 0xc8, 0x3f, 0x67, 0xd5, 0xf3, 0x38, 0x43, 0x16, 0xc8,
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+       0x2d, 0x59, 0xe8, 0x0f, 0x28, 0xf1, 0xe5, 0x4a, 0x40, 0x3f, 0x4b, 0x0d,
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+       0xa2, 0xaf, 0x49, 0x5f, 0xf0, 0x7b, 0x05, 0x63, 0xf4, 0xb5, 0x98, 0xd3,
+       0x57, 0x90, 0x98, 0x92, 0x4a, 0x5f, 0x51, 0xba, 0x2a, 0x4e, 0xcc, 0x9f,
+       0x0a, 0xac, 0xc6, 0xf6, 0xbd, 0x8e, 0xbe, 0x8f, 0x9a, 0x50, 0x4f, 0x1d,
+       0x30, 0x12, 0x5e, 0xd4, 0x3c, 0xb8, 0xc4, 0x7d, 0x1c, 0x37, 0x9f, 0x13,
+       0x7a, 0x3e, 0x1f, 0x97, 0x2c, 0xd3, 0x7c, 0xd6, 0x8e, 0x34, 0x9f, 0x4b,
+       0xa1, 0xf3, 0x78, 0xfa, 0xca, 0x60, 0x9c, 0x9e, 0x47, 0xa3, 0xf7, 0x0c,
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+       0x84, 0xf1, 0xe7, 0x8b, 0xf1, 0x6f, 0xec, 0xe6, 0x74, 0x74, 0xa3, 0xcd,
+       0x40, 0x74, 0x37, 0x7f, 0xa0, 0x91, 0xf2, 0x85, 0x58, 0x35, 0x8f, 0x2b,
+       0x78, 0xe1, 0x7f, 0xdc, 0x0e, 0xf4, 0x11, 0x7c, 0xeb, 0xc4, 0x77, 0x0b,
+       0x5d, 0xa5, 0x7a, 0x24, 0xd9, 0x85, 0xb5, 0xda, 0xf8, 0x43, 0x9d, 0x55,
+       0x8d, 0x6f, 0xf8, 0xf5, 0xb8, 0x1f, 0x6f, 0x5c, 0xa8, 0x3f, 0x16, 0x2f,
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+       0x58, 0xd8, 0xe9, 0x67, 0x81, 0xbe, 0x91, 0xfe, 0xdf, 0x48, 0x5b, 0xb9,
+       0xfd, 0x0e, 0xa0, 0xdb, 0xf1, 0x8f, 0x97, 0x94, 0xa1, 0x3f, 0x67, 0x76,
+       0xfa, 0xaa, 0xa7, 0x36, 0x41, 0xf9, 0x99, 0x6d, 0x13, 0xa9, 0xfc, 0x46,
+       0xfa, 0xad, 0x77, 0xbd, 0x8b, 0xf5, 0x3b, 0x8b, 0xa8, 0x5c, 0x8d, 0x97,
+       0xb8, 0xa0, 0xbd, 0xd1, 0xc8, 0xbf, 0x2f, 0xae, 0xb8, 0x79, 0x5e, 0x3e,
+       0x8c, 0x7b, 0xd8, 0x2c, 0xfa, 0xc5, 0x7d, 0x85, 0x76, 0x5f, 0x52, 0xa0,
+       0x77, 0x3e, 0xb4, 0x73, 0x4f, 0x29, 0x28, 0xc3, 0x7c, 0xc3, 0x6a, 0xc1,
+       0x1f, 0xce, 0xde, 0xc1, 0xf3, 0xdd, 0xaf, 0xbd, 0xcc, 0xc6, 0x53, 0x38,
+       0x57, 0x7a, 0xc8, 0x6f, 0x54, 0x9d, 0x24, 0xea, 0xbf, 0xcb, 0xfb, 0x7d,
+       0xbb, 0xf4, 0x5f, 0xca, 0x30, 0xef, 0xb4, 0xba, 0x80, 0xdf, 0xe3, 0xf2,
+       0x76, 0xd9, 0x4f, 0x27, 0x62, 0xf9, 0xb0, 0xf4, 0xc5, 0xa2, 0x91, 0xe2,
+       0xdf, 0x93, 0x8a, 0xa5, 0xf0, 0x04, 0x80, 0x4f, 0xb5, 0x93, 0xb7, 0xaf,
+       0x2d, 0xfb, 0x51, 0x16, 0xda, 0xf1, 0xd5, 0x55, 0xbc, 0x3c, 0xc9, 0x5b,
+       0xd9, 0x3d, 0x16, 0xeb, 0x75, 0xe7, 0x16, 0x8d, 0x74, 0xee, 0xf3, 0x17,
+       0x62, 0x3f, 0x45, 0xcf, 0x35, 0x89, 0x7d, 0xfa, 0xb2, 0xef, 0x63, 0x3a,
+       0xc7, 0xe4, 0x37, 0x49, 0x5e, 0x5c, 0xa2, 0x7f, 0xfa, 0xc7, 0xfc, 0x5e,
+       0x22, 0xab, 0x64, 0x47, 0xff, 0xa3, 0xdf, 0x97, 0xaf, 0xa0, 0x9f, 0x74,
+       0x96, 0x8f, 0xe7, 0x25, 0x56, 0x99, 0xda, 0x33, 0xd1, 0xfe, 0xbd, 0x2e,
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+       0xd3, 0x2b, 0xa7, 0x21, 0x7e, 0x67, 0x99, 0x98, 0x1e, 0xe5, 0x12, 0xd0,
+       0xf9, 0xff, 0x21, 0x3a, 0xbf, 0xfc, 0x8b, 0xdc, 0x64, 0x24, 0x2e, 0xab,
+       0x96, 0xce, 0x55, 0x3a, 0x9a, 0xaf, 0xd2, 0x77, 0xb5, 0x96, 0x8e, 0x61,
+       0x7f, 0xfe, 0x73, 0x56, 0xda, 0x37, 0xf3, 0xd7, 0xd1, 0xe8, 0x18, 0xc6,
+       0xff, 0x77, 0xe4, 0x13, 0x75, 0xdf, 0xd2, 0xca, 0x95, 0x68, 0x7f, 0x09,
+       0xfb, 0x2d, 0xb1, 0xff, 0xd1, 0xf8, 0x00, 0xfe, 0xc5, 0xf3, 0xb9, 0xd8,
+       0x3c, 0xfa, 0x68, 0x5f, 0x65, 0x63, 0xd6, 0xd7, 0x58, 0xdc, 0x77, 0x3d,
+       0xea, 0xbe, 0x1b, 0xc2, 0x75, 0x18, 0x74, 0x83, 0x74, 0xae, 0x23, 0x4f,
+       0xf2, 0x4e, 0xa4, 0x03, 0x8d, 0xa3, 0xc8, 0x7f, 0x75, 0x7e, 0x39, 0xc0,
+       0xdb, 0x58, 0xd9, 0xf0, 0x79, 0xe1, 0x9f, 0xa2, 0xea, 0x65, 0xfc, 0xcf,
+       0x85, 0x76, 0x6e, 0xb6, 0xa8, 0x87, 0xef, 0x7c, 0xcc, 0x19, 0x9b, 0x17,
+       0x8c, 0xcf, 0xc6, 0xa0, 0xdc, 0x5f, 0xcf, 0xe7, 0xb3, 0x43, 0x6a, 0xe1,
+       0x7c, 0x43, 0xe8, 0xc5, 0xaa, 0x7d, 0xdc, 0xa4, 0xae, 0xb7, 0x5f, 0xbb,
+       0xde, 0x8a, 0x24, 0x7e, 0x9e, 0xd9, 0x8d, 0xfe, 0x0b, 0xfc, 0xce, 0x55,
+       0x3a, 0xf1, 0xeb, 0xe6, 0xdd, 0x2c, 0xe4, 0xe6, 0x42, 0x93, 0xff, 0x41,
+       0x23, 0xac, 0xe1, 0x06, 0xc7, 0x52, 0xa2, 0x87, 0x9b, 0x58, 0xf0, 0x45,
+       0xd4, 0x4f, 0x8c, 0x29, 0x01, 0xe7, 0x98, 0x34, 0xb4, 0xbb, 0x82, 0x07,
+       0x22, 0xf9, 0xe4, 0xcf, 0xa5, 0xbc, 0x00, 0xc0, 0x77, 0xea, 0x98, 0x38,
+       0xfd, 0x44, 0x9d, 0x57, 0x22, 0x3c, 0x9a, 0x46, 0xe1, 0x87, 0x89, 0xf3,
+       0x4e, 0x84, 0x43, 0x0c, 0x3f, 0x83, 0xa4, 0x5f, 0xa9, 0xe7, 0xa3, 0xa2,
+       0xeb, 0x4a, 0x58, 0x8f, 0x2a, 0xff, 0x5d, 0x06, 0xad, 0x1f, 0xc8, 0x29,
+       0xfc, 0x36, 0x4e, 0xe1, 0xa7, 0x41, 0x0a, 0x41, 0x39, 0x58, 0xcb, 0x92,
+       0x28, 0x6f, 0x61, 0x96, 0x57, 0x22, 0x39, 0x5e, 0xcb, 0x4c, 0xc4, 0x3f,
+       0x6b, 0x6b, 0xb8, 0xdc, 0x74, 0x5a, 0xb9, 0x9c, 0x57, 0xe5, 0xeb, 0x68,
+       0x74, 0x7d, 0xf5, 0x55, 0x9c, 0xcf, 0xd4, 0x36, 0x30, 0x71, 0xee, 0x8a,
+       0xcf, 0x3f, 0x91, 0xae, 0x32, 0x58, 0xe4, 0x7b, 0xf8, 0xac, 0x35, 0x79,
+       0xb6, 0x2e, 0xc3, 0xfd, 0x8a, 0xfa, 0x80, 0x27, 0xb6, 0xdf, 0x6b, 0xad,
+       0xdc, 0xaf, 0x3b, 0x77, 0x8c, 0xf0, 0x1b, 0xb2, 0xc8, 0x34, 0xb4, 0x6f,
+       0xa3, 0xe5, 0x61, 0x7e, 0xc4, 0xc8, 0x34, 0xe4, 0x1b, 0x89, 0xf7, 0x45,
+       0xd5, 0x5e, 0xe0, 0x7e, 0x44, 0xa7, 0xb8, 0x97, 0xb5, 0xd6, 0xfb, 0xf1,
+       0x34, 0xb4, 0xd7, 0x9d, 0x35, 0x91, 0x69, 0xc8, 0x7f, 0x1e, 0x74, 0xf8,
+       0xe6, 0x21, 0xde, 0xd4, 0xfb, 0xdc, 0x12, 0xf9, 0xce, 0x8d, 0x63, 0x74,
+       0xaa, 0x1f, 0xf1, 0x92, 0xe8, 0x2d, 0x11, 0x0f, 0x6a, 0xdc, 0x28, 0x35,
+       0xc5, 0x5f, 0x87, 0xe3, 0x9c, 0x96, 0x06, 0x2b, 0xb0, 0xf2, 0x91, 0x34,
+       0xe1, 0xd7, 0x67, 0x81, 0x7c, 0xa4, 0x47, 0x87, 0x3d, 0xbf, 0x12, 0xfd,
+       0x01, 0xc0, 0xdf, 0x2e, 0x5e, 0x44, 0xa3, 0x0a, 0xab, 0x00, 0x5e, 0xd3,
+       0x9d, 0x81, 0x00, 0xd2, 0xdb, 0x4d, 0xcc, 0x3f, 0x1b, 0xcf, 0xe2, 0x39,
+       0x6b, 0x02, 0x7a, 0xee, 0xe7, 0x66, 0xb4, 0xfe, 0xb5, 0x62, 0xfd, 0xb3,
+       0x85, 0xdc, 0x3b, 0xb7, 0x5d, 0x26, 0x3f, 0x7d, 0xb5, 0xaf, 0xf8, 0x31,
+       0x74, 0xa5, 0x37, 0x1f, 0xd1, 0xb3, 0x10, 0xed, 0x3b, 0x1f, 0xc9, 0xb1,
+       0x35, 0x62, 0xfe, 0xe7, 0x18, 0xc7, 0xd3, 0x39, 0x2b, 0x97, 0x7f, 0x2b,
+       0xdf, 0xfa, 0xa7, 0x0a, 0xa0, 0x5c, 0x36, 0x7e, 0x8b, 0x2e, 0x76, 0x8f,
+       0x01, 0xfc, 0x9b, 0x10, 0x4a, 0xd2, 0xdc, 0x63, 0x30, 0x69, 0xaf, 0x53,
+       0x53, 0x9e, 0xdc, 0x97, 0xa5, 0x69, 0x7f, 0x59, 0x7f, 0x81, 0xa6, 0xbe,
+       0x34, 0x3c, 0x51, 0x53, 0x3f, 0xf5, 0x48, 0x99, 0xa6, 0x3c, 0x6d, 0x70,
+       0x86, 0xa6, 0xfd, 0xe5, 0xef, 0x57, 0x69, 0xca, 0x57, 0x44, 0xe6, 0x69,
+       0xda, 0x7f, 0xeb, 0xd4, 0x02, 0x4d, 0xf9, 0xca, 0xa1, 0x5b, 0x34, 0xed,
+       0x8f, 0x0b, 0xfb, 0x94, 0x05, 0x7d, 0x83, 0xc5, 0xe9, 0x78, 0xcf, 0xb7,
+       0xa0, 0xcb, 0x0b, 0x4b, 0x34, 0xdf, 0xfd, 0x36, 0x79, 0xce, 0x11, 0xa4,
+       0xcb, 0x65, 0x1b, 0x79, 0x9e, 0x70, 0x25, 0x40, 0x46, 0x73, 0x9f, 0x43,
+       0x0f, 0x97, 0xef, 0x2d, 0xf0, 0x3f, 0x8e, 0x57, 0xbf, 0x82, 0xf0, 0x5a,
+       0x01, 0x7a, 0x2f, 0xe6, 0x07, 0xaf, 0xdc, 0xa2, 0x95, 0xff, 0xf5, 0x03,
+       0x9b, 0xd6, 0x23, 0x4f, 0x4b, 0xcc, 0x5f, 0x58, 0xcd, 0x5a, 0xaa, 0xf0,
+       0x6a, 0xb8, 0xc4, 0xfc, 0x85, 0x6a, 0xfb, 0x62, 0x1d, 0xd2, 0xe1, 0xe3,
+       0x63, 0x44, 0x9e, 0xc2, 0xe5, 0xec, 0x72, 0x71, 0xff, 0xca, 0xd7, 0xe2,
+       0xb5, 0x88, 0x15, 0xfe, 0x97, 0xf0, 0x6a, 0x74, 0x6b, 0xf1, 0x6a, 0xf6,
+       0x68, 0xf1, 0x6a, 0x29, 0xd6, 0xe2, 0xd5, 0xe6, 0xd5, 0xe2, 0x35, 0x65,
+       0xba, 0x16, 0xaf, 0x0e, 0x9f, 0x16, 0xaf, 0xa9, 0x35, 0x5a, 0xbc, 0xa6,
+       0xf9, 0xb5, 0x78, 0xcd, 0xa8, 0xd3, 0xe2, 0x35, 0x33, 0xa0, 0xc5, 0xeb,
+       0x98, 0x7a, 0x2d, 0x5e, 0x73, 0x5a, 0xb4, 0x78, 0xcd, 0x6b, 0xd5, 0xe2,
+       0x2f, 0x3f, 0xb8, 0x5a, 0x8b, 0xaf, 0x04, 0x7c, 0xab, 0xfc, 0x6f, 0x6c,
+       0xd7, 0x5a, 0x4d, 0xbb, 0x28, 0xde, 0xfd, 0xf5, 0x94, 0x77, 0x32, 0xae,
+       0xe7, 0x1e, 0x4d, 0xbf, 0x2a, 0xde, 0x83, 0xf0, 0x3f, 0x8e, 0xf7, 0x16,
+       0xca, 0x0b, 0xff, 0x6b, 0xf1, 0x0e, 0xdc, 0x86, 0xfc, 0xa0, 0x89, 0x78,
+       0xff, 0x20, 0x01, 0xdf, 0x20, 0x37, 0x3e, 0x44, 0xbe, 0x00, 0xf2, 0xfe,
+       0xdf, 0xf0, 0x59, 0x37, 0x5e, 0xe8, 0xd5, 0xfe, 0x91, 0xe5, 0xbd, 0xca,
+       0x7f, 0xe2, 0xe5, 0x6b, 0xbc, 0xfd, 0x38, 0x1a, 0x5f, 0x1a, 0x26, 0x4f,
+       0x84, 0x3d, 0x39, 0xaa, 0x3c, 0x49, 0xb0, 0x27, 0x3f, 0xc0, 0xec, 0x18,
+       0xd2, 0x53, 0x36, 0x92, 0xbf, 0xe5, 0x66, 0x41, 0x9f, 0x5f, 0xe2, 0xab,
+       0x2b, 0xd0, 0x9f, 0xf9, 0x63, 0x92, 0x93, 0x1f, 0xc0, 0x44, 0xa6, 0xc3,
+       0xbc, 0x3e, 0xc0, 0x79, 0xc3, 0x38, 0x1f, 0x24, 0x4d, 0x22, 0x7b, 0xff,
+       0x56, 0x16, 0xd6, 0xd3, 0xfd, 0xbb, 0x98, 0xf1, 0x07, 0x9d, 0xde, 0x8e,
+       0x09, 0xc0, 0x32, 0xde, 0x9b, 0xe3, 0xa1, 0xe7, 0x52, 0x21, 0x47, 0x97,
+       0x0b, 0x7f, 0x80, 0xcf, 0x12, 0xb8, 0x38, 0x86, 0xfb, 0x01, 0xf2, 0xd2,
+       0x71, 0xdc, 0xec, 0x41, 0x7e, 0x0f, 0xf2, 0xdb, 0xa9, 0x97, 0x74, 0x1f,
+       0xc0, 0x31, 0xf4, 0x87, 0x2b, 0x8c, 0x9d, 0x40, 0x7f, 0x38, 0x3c, 0xcf,
+       0x98, 0x39, 0x3d, 0x9c, 0x54, 0xf9, 0x83, 0x8f, 0x79, 0x5c, 0x71, 0x70,
+       0x5b, 0x32, 0x4b, 0x2a, 0x26, 0xbd, 0x51, 0x4e, 0xa2, 0xbc, 0x9c, 0x25,
+       0x37, 0x49, 0x24, 0x47, 0x96, 0xfc, 0x9e, 0x3f, 0xd3, 0xb3, 0xb9, 0xfe,
+       0x99, 0xf8, 0xec, 0x68, 0x55, 0xe1, 0xc6, 0xed, 0x92, 0x99, 0xd9, 0x1e,
+       0xe2, 0xeb, 0xd9, 0xac, 0x4f, 0xc8, 0x3b, 0x16, 0xb0, 0x8e, 0xa5, 0x7e,
+       0xb8, 0xff, 0xfa, 0x49, 0x7e, 0x0f, 0xe8, 0xf3, 0x12, 0x53, 0xa6, 0x3b,
+       0xe9, 0x38, 0x12, 0xe1, 0x31, 0xc3, 0xc4, 0xe7, 0xf5, 0xbc, 0x9e, 0x99,
+       0x10, 0x7e, 0xcf, 0xb2, 0x80, 0x07, 0xe1, 0xf2, 0x43, 0x05, 0x58, 0x13,
+       0xcf, 0x87, 0x9f, 0x88, 0xf4, 0xb0, 0xe4, 0xf7, 0xef, 0x16, 0xa0, 0x3f,
+       0x49, 0xee, 0xb0, 0x5f, 0x87, 0xf7, 0x3c, 0x4f, 0xc0, 0xf1, 0x60, 0x1e,
+       0xb3, 0x6f, 0x6b, 0x91, 0xd0, 0xbf, 0x9a, 0xe1, 0x6e, 0x91, 0xd0, 0x7f,
+       0x33, 0xec, 0xfd, 0xfe, 0x7b, 0x24, 0x3c, 0xc7, 0x17, 0x2d, 0x33, 0xde,
+       0x0e, 0xff, 0x10, 0x0e, 0xaa, 0x9f, 0xac, 0x58, 0xc7, 0xe3, 0xc5, 0x43,
+       0x77, 0x70, 0x3d, 0xff, 0xa9, 0xef, 0x32, 0xf2, 0xff, 0x74, 0xb4, 0x06,
+       0x2b, 0x83, 0x18, 0x27, 0x92, 0xc1, 0x20, 0xc3, 0x7c, 0x12, 0x3d, 0x3f,
+       0xf7, 0x3b, 0x33, 0x9b, 0xfb, 0xbf, 0x32, 0xd9, 0x20, 0xdd, 0x2f, 0xca,
+       0xde, 0x14, 0xfa, 0x99, 0xb8, 0x97, 0xbd, 0x44, 0xe4, 0x97, 0x9f, 0x11,
+       0xf1, 0x96, 0x15, 0xbb, 0x4c, 0x0c, 0xf3, 0x15, 0x4a, 0xf6, 0x1d, 0x74,
+       0x62, 0x7c, 0x65, 0x05, 0xe0, 0x72, 0x10, 0xe5, 0x99, 0x12, 0xa0, 0x7b,
+       0x2c, 0x4a, 0xb6, 0xbe, 0xe1, 0xe4, 0xf7, 0x7d, 0xeb, 0x1d, 0x78, 0x5e,
+       0x4c, 0x95, 0xa3, 0xa3, 0xe3, 0x5b, 0x61, 0x27, 0xe3, 0xf2, 0xb4, 0x01,
+       0x8f, 0x23, 0xde, 0x17, 0x79, 0x5b, 0x0e, 0x97, 0xe3, 0x1d, 0x6d, 0x35,
+       0x33, 0x31, 0x3e, 0xa2, 0xce, 0xe7, 0xfe, 0x36, 0xdf, 0x4c, 0xa4, 0x0f,
+       0x59, 0xf1, 0x52, 0x9e, 0x17, 0xde, 0x6f, 0xe3, 0x88, 0xfb, 0xde, 0xe0,
+       0x82, 0xfa, 0xb8, 0xfd, 0xab, 0x58, 0x6b, 0x34, 0x65, 0xbd, 0xd5, 0x4f,
+       0x97, 0x46, 0xac, 0x6f, 0x6b, 0x21, 0x3a, 0xd3, 0x8b, 0x7b, 0x78, 0x1e,
+       0xc8, 0x5e, 0x6b, 0x8f, 0xbf, 0xbf, 0xff, 0xd6, 0x6c, 0xa1, 0x47, 0x98,
+       0x82, 0xcc, 0x9e, 0xce, 0x84, 0x0a, 0x8b, 0x4f, 0xe5, 0x24, 0xf2, 0x87,
+       0x3f, 0x32, 0x6e, 0x0f, 0x1a, 0xdd, 0xd0, 0x4f, 0x3c, 0x5f, 0xbb, 0x2b,
+       0x97, 0xc5, 0xfb, 0x77, 0xbb, 0xda, 0xfc, 0x34, 0xdf, 0xf5, 0x52, 0x20,
+       0x80, 0x9d, 0x18, 0x0b, 0x59, 0xd8, 0x9c, 0x8c, 0xf9, 0x03, 0x78, 0xc6,
+       0x11, 0xde, 0x6f, 0xbd, 0xe6, 0x08, 0xe6, 0xb3, 0x18, 0x6c, 0x6b, 0xbd,
+       0x61, 0xcf, 0xe8, 0x70, 0x33, 0xba, 0x95, 0xf3, 0xf1, 0x7c, 0xa9, 0x21,
+       0x5b, 0xcb, 0x97, 0xfe, 0xa1, 0xed, 0x14, 0xc1, 0xa9, 0xa3, 0xad, 0x8e,
+       0xc6, 0x3b, 0x83, 0xba, 0x1c, 0xfa, 0x77, 0x32, 0xb9, 0x7f, 0xa7, 0xa3,
+       0x6d, 0x31, 0xbd, 0xd7, 0xd5, 0x78, 0x88, 0x9e, 0x5e, 0xdf, 0x3a, 0xfe,
+       0xa0, 0x07, 0xea, 0x8f, 0xc2, 0x3f, 0xbc, 0x8f, 0xc6, 0xe8, 0xe2, 0xf3,
+       0x62, 0xe5, 0xb9, 0x24, 0x9f, 0x16, 0x09, 0x3a, 0x40, 0xdf, 0x51, 0x0e,
+       0xd0, 0xcf, 0xd1, 0x56, 0x3d, 0xd1, 0xd9, 0x9d, 0x39, 0xd6, 0x10, 0x6e,
+       0xc2, 0x3b, 0xdf, 0x19, 0x77, 0x10, 0xef, 0xd3, 0x34, 0x00, 0x8c, 0xe4,
+       0xbf, 0x62, 0xde, 0xd1, 0x71, 0x04, 0x9c, 0x0c, 0x82, 0x2f, 0x01, 0x3d,
+       0xf9, 0x71, 0xbf, 0x19, 0xb2, 0x14, 0xf2, 0xc3, 0x3a, 0xed, 0x0b, 0x08,
+       0x4f, 0xff, 0xd5, 0xfe, 0x54, 0xf8, 0x1a, 0xcc, 0x8c, 0xee, 0x7b, 0x31,
+       0xe4, 0x58, 0xc9, 0x7f, 0x72, 0xa9, 0xf3, 0xdc, 0x92, 0x2d, 0xec, 0x7c,
+       0x55, 0xce, 0x97, 0xe7, 0x12, 0x1f, 0xbd, 0x53, 0xc0, 0xe5, 0xf5, 0xad,
+       0x3c, 0xff, 0xe7, 0xe8, 0x5d, 0x8c, 0xf4, 0xee, 0x3b, 0xef, 0xe6, 0x7e,
+       0xb0, 0x3b, 0xc1, 0x8e, 0xc7, 0x7d, 0xc9, 0x5a, 0xe1, 0xaf, 0x22, 0x46,
+       0x37, 0x2a, 0xbf, 0x4e, 0xc3, 0x1b, 0x37, 0xe0, 0x65, 0x4f, 0x1b, 0x30,
+       0x9a, 0x22, 0xc6, 0x1e, 0x6a, 0x33, 0xe1, 0x09, 0x27, 0x66, 0x41, 0x7f,
+       0xd5, 0xd8, 0x18, 0x1e, 0x7b, 0x7c, 0x8a, 0x03, 0xdd, 0xe2, 0x9b, 0xaa,
+       0x5d, 0xf3, 0xf1, 0xf9, 0xd0, 0xf4, 0x13, 0x3d, 0xc8, 0x56, 0x1e, 0x9e,
+       0xf9, 0xd5, 0x20, 0x3e, 0xd1, 0xd7, 0x8c, 0xe3, 0xdb, 0x5b, 0x58, 0x08,
+       0xf5, 0x4c, 0x8a, 0x89, 0xc2, 0xf8, 0x8e, 0x7a, 0x28, 0xc3, 0xf8, 0xc9,
+       0xa2, 0x3e, 0x39, 0xc0, 0xcb, 0x29, 0xa2, 0x3e, 0xa5, 0x8e, 0x97, 0x73,
+       0x7c, 0x2f, 0x48, 0xd5, 0x38, 0xb1, 0x84, 0x78, 0x44, 0x8e, 0xd5, 0x39,
+       0xb7, 0x10, 0xf9, 0xde, 0x32, 0xc6, 0xcf, 0xb7, 0x8a, 0xf3, 0xed, 0x3b,
+       0x04, 0xdf, 0x1d, 0x63, 0x75, 0xce, 0xaf, 0xc6, 0xfa, 0xdb, 0x18, 0xe5,
+       0xbd, 0xab, 0xf5, 0x8f, 0x8b, 0xfa, 0x4c, 0xeb, 0xb1, 0xae, 0xb1, 0xc8,
+       0x97, 0x17, 0x6a, 0xbf, 0xdf, 0x2a, 0xe0, 0x90, 0x61, 0x3d, 0xd6, 0x33,
+       0x8b, 0xe2, 0x16, 0xda, 0x7a, 0x35, 0xce, 0x90, 0x66, 0x3d, 0x77, 0x84,
+       0xbe, 0x2f, 0xd1, 0xd6, 0x3f, 0x2a, 0xbe, 0xb7, 0x59, 0xcf, 0x0d, 0xce,
+       0xc2, 0xfa, 0x42, 0xed, 0xf8, 0x0f, 0x8a, 0x7a, 0x8b, 0x95, 0xf3, 0x43,
+       0xe6, 0xe7, 0xf7, 0x94, 0xaa, 0xf5, 0x3f, 0x14, 0xf5, 0x66, 0x2b, 0x3f,
+       0xe7, 0x05, 0x3c, 0x59, 0x53, 0xdf, 0x2d, 0xc6, 0xef, 0x90, 0x42, 0x84,
+       0x1f, 0xba, 0x8b, 0x15, 0xf7, 0x4f, 0x1a, 0xf7, 0x5b, 0xee, 0x6c, 0x63,
+       0x57, 0xe2, 0xfe, 0xe9, 0x69, 0x1b, 0xa2, 0x7d, 0xf4, 0x50, 0xdb, 0x05,
+       0xc2, 0xd3, 0x39, 0xcc, 0xf3, 0x99, 0x16, 0xdb, 0x57, 0xf6, 0x56, 0x36,
+       0xe2, 0xb9, 0xeb, 0x73, 0x82, 0x9f, 0x24, 0x7b, 0x22, 0x3e, 0xdf, 0x08,
+       0xfc, 0x4e, 0xad, 0x77, 0xda, 0xf9, 0xb9, 0x72, 0xd9, 0x6d, 0x20, 0x3a,
+       0x32, 0x5a, 0x05, 0xbf, 0x10, 0xfb, 0x30, 0xca, 0x2f, 0xa4, 0x16, 0x2f,
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+       0x8b, 0x5c, 0xf8, 0x43, 0x7a, 0xce, 0xbe, 0x4b, 0xc7, 0x02, 0x71, 0x7c,
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+       0xc3, 0x40, 0x77, 0x05, 0xc0, 0x47, 0x90, 0x2f, 0x15, 0xdb, 0x36, 0x3a,
+       0x71, 0x9f, 0xef, 0xee, 0x2a, 0x27, 0xfa, 0xef, 0xa8, 0xe0, 0xf1, 0x1d,
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+       0x29, 0xe6, 0xdb, 0x9b, 0xcb, 0xf3, 0xa9, 0x8d, 0x6e, 0x77, 0x5a, 0x6d,
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+       0x55, 0xe8, 0x5e, 0x2c, 0xd9, 0xc6, 0xe5, 0xc0, 0x9c, 0x9f, 0xcc, 0xb4,
+       0xa3, 0x9e, 0xd5, 0xc9, 0x02, 0x83, 0x3e, 0xfc, 0xde, 0xad, 0x90, 0xfe,
+       0x7e, 0xb0, 0xab, 0xcc, 0x8e, 0x7c, 0xcf, 0x60, 0x5b, 0x66, 0xc7, 0xfd,
+       0xbb, 0xd6, 0xc3, 0xf7, 0x7f, 0x75, 0x53, 0x71, 0x12, 0xf2, 0x6b, 0xf9,
+       0x41, 0x1d, 0xf1, 0xef, 0xc3, 0x76, 0xbe, 0xdf, 0x77, 0xba, 0x75, 0xe4,
+       0xb7, 0x00, 0xb9, 0x42, 0xe7, 0x4a, 0x80, 0x5f, 0x7b, 0x51, 0x46, 0x8c,
+       0x67, 0xe1, 0x76, 0x3a, 0xa7, 0xf0, 0xd0, 0x4b, 0x8b, 0xb9, 0x5f, 0x8f,
+       0xd9, 0x4a, 0x2b, 0xe8, 0xdc, 0x86, 0x1a, 0x0f, 0x96, 0x94, 0x38, 0xfd,
+       0xff, 0x04, 0xc2, 0x07, 0xcf, 0x4b, 0x08, 0x39, 0xa2, 0xa0, 0x7c, 0x81,
+       0xe7, 0x93, 0xe5, 0xe2, 0xbc, 0x41, 0x90, 0xfb, 0x9f, 0xf2, 0x14, 0xe6,
+       0x1e, 0x13, 0x77, 0x6e, 0xf2, 0x44, 0xae, 0xcc, 0xcf, 0x63, 0x28, 0x08,
+       0x23, 0xe8, 0x4b, 0xae, 0xa5, 0xfb, 0x81, 0x72, 0xd7, 0x29, 0x1a, 0xff,
+       0x7b, 0xf6, 0x5d, 0xda, 0xb2, 0x21, 0x41, 0x6e, 0x28, 0x09, 0x72, 0x65,
+       0x6c, 0x17, 0xf0, 0xc9, 0x38, 0xb9, 0x93, 0x1f, 0xb4, 0x6b, 0xca, 0xef,
+       0xe5, 0x0a, 0xbf, 0x99, 0x97, 0x79, 0x51, 0x7f, 0x9d, 0xf3, 0x93, 0x8d,
+       0xc4, 0x0f, 0xcf, 0xa1, 0x7c, 0x93, 0x46, 0xe7, 0x7b, 0x51, 0xfe, 0x2b,
+       0xf8, 0xf1, 0x93, 0xe2, 0xbe, 0x9b, 0x27, 0x83, 0xfc, 0xbc, 0xee, 0xc1,
+       0x8d, 0x65, 0x3f, 0x47, 0x7c, 0xaf, 0xed, 0xd6, 0xd1, 0xfd, 0xce, 0x97,
+       0xca, 0x47, 0xb7, 0xe7, 0x32, 0x82, 0xc3, 0xb8, 0x00, 0xc8, 0x1d, 0xd4,
+       0x67, 0x14, 0x96, 0x85, 0xf6, 0xd2, 0x37, 0xc1, 0x61, 0x9c, 0xde, 0xef,
+       0xa4, 0xfb, 0x0b, 0xbe, 0x01, 0x1e, 0xe3, 0x1e, 0x2d, 0x77, 0x22, 0xbf,
+       0x1d, 0x17, 0x50, 0x48, 0xee, 0x0c, 0x93, 0x1b, 0xdf, 0x00, 0xaf, 0xe7,
+       0x25, 0xef, 0xfb, 0x01, 0xc4, 0xa3, 0x23, 0x89, 0xeb, 0xd5, 0x76, 0xbe,
+       0xee, 0xce, 0x74, 0x17, 0xbf, 0xf7, 0x47, 0x9c, 0x03, 0x94, 0x85, 0xbe,
+       0x76, 0xbf, 0xf0, 0x83, 0x2b, 0x29, 0x73, 0x3c, 0xf8, 0x53, 0x1c, 0x9d,
+       0x8e, 0x16, 0x2a, 0xaf, 0x97, 0xbc, 0x19, 0xd7, 0x42, 0xfb, 0x07, 0xa4,
+       0x80, 0x1d, 0xcb, 0x47, 0x9c, 0x49, 0x5c, 0xee, 0xe4, 0x24, 0x11, 0x1d,
+       0xee, 0x45, 0x5d, 0x86, 0xee, 0x2f, 0xcc, 0xf4, 0xa3, 0x7f, 0xa4, 0x2f,
+       0x64, 0x50, 0xef, 0x03, 0x0c, 0xe3, 0xff, 0xed, 0xc3, 0x3c, 0x19, 0xf5,
+       0xbe, 0x41, 0x37, 0xe9, 0x67, 0xa2, 0xfc, 0xe0, 0xf5, 0xd5, 0xd8, 0x5e,
+       0xb1, 0x4f, 0x42, 0x95, 0xb3, 0x28, 0xaf, 0xe7, 0x61, 0xfd, 0x95, 0xd0,
+       0xde, 0xc0, 0xa2, 0xed, 0xf1, 0x5c, 0xd3, 0xb3, 0x87, 0x75, 0xa2, 0xbf,
+       0xcd, 0x0f, 0xa3, 0xbe, 0xba, 0x2f, 0x89, 0x69, 0xee, 0x5b, 0xdc, 0x87,
+       0x7e, 0x74, 0x2a, 0x6f, 0x7d, 0x18, 0xef, 0x4f, 0x84, 0xf1, 0xae, 0x95,
+       0xc1, 0x06, 0x9b, 0xfe, 0xc4, 0x13, 0x0f, 0x5b, 0xaf, 0x88, 0xcd, 0x67,
+       0x6a, 0xe8, 0xa9, 0x87, 0xdb, 0x29, 0x5f, 0x95, 0xdb, 0x25, 0x0e, 0xc6,
+       0xef, 0xc3, 0x3e, 0xed, 0x89, 0x24, 0xe3, 0x76, 0x01, 0xfb, 0xc4, 0x93,
+       0x87, 0x76, 0xf9, 0xae, 0x13, 0xe9, 0x9a, 0xdf, 0x3f, 0x13, 0xed, 0x53,
+       0x44, 0xfb, 0xa6, 0x81, 0xa1, 0xa6, 0xe7, 0x3c, 0xd4, 0xbe, 0x88, 0xda,
+       0xf7, 0x0f, 0x25, 0x97, 0xd0, 0xfe, 0x1a, 0xaa, 0x88, 0x6f, 0x9f, 0x2c,
+       0xec, 0xfd, 0xb8, 0xf6, 0x25, 0x5f, 0xd7, 0xbe, 0x58, 0x9d, 0xcf, 0x73,
+       0xbf, 0xba, 0xb1, 0x84, 0xb7, 0x2f, 0xc3, 0xf6, 0x67, 0x3c, 0x91, 0x74,
+       0xca, 0x3d, 0x49, 0x98, 0x4f, 0xea, 0xf0, 0xfe, 0xa7, 0x7f, 0x5d, 0xff,
+       0x13, 0x45, 0xfb, 0xd3, 0xe1, 0x5f, 0x51, 0xfb, 0x33, 0x2c, 0x92, 0x3e,
+       0x39, 0x9f, 0xbe, 0xbb, 0x3a, 0x0f, 0xe8, 0xf8, 0xec, 0xdb, 0xbf, 0xaa,
+       0x10, 0xeb, 0x4e, 0x47, 0x3d, 0x19, 0xb8, 0xa2, 0x0f, 0xdf, 0x27, 0x7b,
+       0x98, 0xb8, 0x77, 0xad, 0x85, 0xf4, 0xe7, 0x3e, 0x53, 0x8f, 0x1d, 0xf5,
+       0x35, 0xb3, 0xbe, 0xc7, 0x8f, 0x7c, 0xb7, 0x10, 0xef, 0x4f, 0x9a, 0x1e,
+       0x7b, 0xce, 0xca, 0x2b, 0xe4, 0x7a, 0x55, 0xc2, 0xfb, 0x3e, 0x13, 0x4b,
+       0xad, 0x45, 0x7a, 0x6c, 0xd5, 0x91, 0xfd, 0xd2, 0x67, 0x1a, 0x2c, 0x2b,
+       0x41, 0x7d, 0xfa, 0x65, 0x2b, 0x6b, 0x87, 0x31, 0x74, 0x79, 0xeb, 0xbc,
+       0xc8, 0x07, 0xfb, 0x23, 0x6b, 0xbd, 0x25, 0xd0, 0x6e, 0x67, 0xf6, 0x4c,
+       0xb2, 0x2b, 0xf6, 0x19, 0x5a, 0xfa, 0xe8, 0x9c, 0xed, 0x62, 0x2b, 0x9d,
+       0x03, 0xdd, 0x69, 0xef, 0xb1, 0xe3, 0xfe, 0x31, 0x3b, 0x7a, 0xec, 0x18,
+       0x47, 0x90, 0xef, 0xe6, 0xfa, 0x93, 0xb2, 0xc4, 0x1a, 0x78, 0x0a, 0xe9,
+       0x29, 0xbc, 0xb6, 0x78, 0x79, 0xdc, 0xfe, 0x9d, 0xea, 0xe1, 0xbf, 0x23,
+       0xd3, 0xfd, 0x86, 0x75, 0x23, 0xda, 0x01, 0xdd, 0x7a, 0x6f, 0xcf, 0x78,
+       0xd4, 0xb3, 0x6d, 0x0a, 0xe5, 0x81, 0x2b, 0x4b, 0x06, 0xe6, 0xd1, 0xb9,
+       0xbd, 0x1f, 0xeb, 0x18, 0xf1, 0x77, 0x58, 0x57, 0x15, 0x94, 0x3b, 0x1b,
+       0x75, 0x74, 0x2f, 0x7c, 0x9b, 0x67, 0xc9, 0x32, 0x84, 0x2b, 0x53, 0xfc,
+       0xfe, 0x2a, 0xf8, 0x2e, 0x37, 0x4d, 0x91, 0xf0, 0x1c, 0xc4, 0xfd, 0x8a,
+       0xdf, 0x84, 0xf1, 0x0b, 0xa3, 0xd0, 0xdb, 0x76, 0x7a, 0xf9, 0xef, 0xae,
+       0xaa, 0xe3, 0x6e, 0xc8, 0xe3, 0xf2, 0x69, 0x43, 0x1e, 0xbf, 0x1f, 0xaa,
+       0x7b, 0xf1, 0x73, 0xc5, 0x6f, 0xc2, 0x77, 0x3b, 0x5b, 0xd7, 0xf6, 0xe1,
+       0x78, 0xe6, 0x09, 0x26, 0x86, 0xf9, 0x5e, 0x3b, 0xb3, 0x4f, 0x76, 0xe3,
+       0xb9, 0xcd, 0xc7, 0xdd, 0x60, 0xf1, 0x02, 0x1c, 0xac, 0x0d, 0x3a, 0xfa,
+       0x5d, 0x94, 0xc7, 0x6b, 0xa1, 0x4d, 0x0a, 0xfa, 0x33, 0x0c, 0x1a, 0x7f,
+       0xc5, 0xf3, 0x52, 0x1f, 0xb5, 0x0f, 0x36, 0xea, 0xc8, 0x4e, 0xb0, 0x96,
+       0x18, 0x34, 0xfe, 0x8d, 0xd4, 0x06, 0x9d, 0x0f, 0xfd, 0x8e, 0x3b, 0x3c,
+       0x81, 0x7b, 0x71, 0xde, 0x53, 0xdf, 0x51, 0xae, 0xc5, 0xf1, 0xdc, 0xe3,
+       0x14, 0x3b, 0xca, 0xa7, 0x07, 0xdd, 0xbf, 0x36, 0xe9, 0x60, 0x9e, 0xc9,
+       0xe5, 0xda, 0x7e, 0xed, 0x33, 0xb5, 0xfd, 0x38, 0xab, 0xb5, 0xf5, 0xae,
+       0x5a, 0x6d, 0x7d, 0xfa, 0x42, 0x6d, 0xbd, 0xfb, 0x36, 0x43, 0x82, 0xbf,
+       0x46, 0x5b, 0xbe, 0x88, 0x82, 0x08, 0xe1, 0x08, 0x3c, 0xc0, 0x0a, 0x72,
+       0x28, 0x89, 0x57, 0xb1, 0x24, 0xeb, 0x79, 0xfa, 0x5d, 0xae, 0xee, 0xc0,
+       0xf6, 0x9e, 0xf1, 0xb0, 0x1e, 0xa3, 0x25, 0x58, 0xfa, 0x26, 0xcc, 0x37,
+       0x69, 0x62, 0x12, 0xd9, 0xfb, 0x0f, 0xbc, 0x91, 0x84, 0x9b, 0x0f, 0xf8,
+       0x0f, 0x23, 0xbe, 0xf3, 0xc0, 0x64, 0x46, 0xf9, 0xa7, 0x87, 0x72, 0xbe,
+       0xef, 0x46, 0x79, 0x9a, 0x08, 0x9f, 0x9d, 0xd9, 0x06, 0x5a, 0xaf, 0xb5,
+       0x10, 0xe0, 0x99, 0x8f, 0xf6, 0xfa, 0x29, 0xfa, 0xfd, 0x2c, 0x2b, 0x8b,
+       0x6b, 0x97, 0x8f, 0xf0, 0xf1, 0x6d, 0xcf, 0x9b, 0xc6, 0xcb, 0xee, 0x0a,
+       0xf4, 0xcf, 0x31, 0xe2, 0x83, 0xcf, 0xab, 0xfe, 0xe3, 0x1b, 0xf8, 0xb9,
+       0xa6, 0x9d, 0xad, 0xdc, 0x2f, 0xfd, 0x60, 0x1d, 0xcf, 0xcf, 0xa3, 0x15,
+       0x54, 0xe0, 0xfe, 0xe6, 0xed, 0x93, 0xf1, 0xf7, 0xbc, 0xa6, 0xa0, 0xdf,
+       0xbe, 0xeb, 0x0e, 0xcc, 0x3b, 0x4c, 0x84, 0x6b, 0x06, 0xe6, 0xe3, 0xc8,
+       0x31, 0xfa, 0x58, 0xaf, 0x9e, 0x23, 0xc1, 0x53, 0x8c, 0x15, 0x9c, 0x2d,
+       0xe3, 0xbe, 0x3b, 0xee, 0xe1, 0x74, 0xf2, 0x93, 0x3c, 0x2e, 0xff, 0xf7,
+       0x89, 0x7b, 0x0f, 0xa2, 0xed, 0x71, 0x1f, 0xa6, 0x33, 0x6e, 0xca, 0x42,
+       0x7f, 0xaf, 0xe6, 0xa9, 0xfe, 0x07, 0x9e, 0x97, 0xbf, 0x59, 0x8d, 0xc7,
+       0x88, 0x32, 0x5e, 0x17, 0x88, 0xe5, 0x7d, 0x87, 0x9d, 0xd7, 0xe2, 0x7e,
+       0xda, 0xbc, 0xd0, 0x59, 0x86, 0xfb, 0xe9, 0x01, 0xa1, 0x97, 0xa5, 0x64,
+       0x1b, 0x7c, 0x13, 0x60, 0xbe, 0x8f, 0x1c, 0x31, 0x04, 0xa5, 0xcb, 0xa0,
+       0xac, 0xb0, 0xc3, 0x7a, 0x90, 0xe7, 0xfb, 0x9c, 0x7c, 0x5c, 0xc3, 0x5b,
+       0x49, 0x41, 0x3c, 0xd7, 0xf4, 0x88, 0xbb, 0x9c, 0xce, 0x49, 0x7d, 0x24,
+       0xe6, 0xf5, 0x42, 0xa5, 0xf7, 0xbd, 0x5a, 0xda, 0x8f, 0x0a, 0xe5, 0x39,
+       0x3d, 0xe2, 0xf2, 0x9a, 0xcb, 0xb8, 0xbe, 0x81, 0x77, 0x4a, 0x33, 0xfa,
+       0x49, 0x54, 0x50, 0x2d, 0x0e, 0xd6, 0x96, 0x91, 0x9d, 0xfa, 0x88, 0xcf,
+       0x6b, 0xc6, 0xfd, 0xfa, 0x48, 0xb6, 0xd7, 0x8c, 0x79, 0xc2, 0xe6, 0x4c,
+       0xc5, 0x8e, 0xfb, 0xd8, 0xe9, 0x56, 0xe8, 0xbe, 0xaa, 0x47, 0x4c, 0x01,
+       0x3b, 0xea, 0x2d, 0x4e, 0x10, 0x80, 0xf8, 0x3b, 0x6d, 0x86, 0x9c, 0x9e,
+       0xb9, 0x74, 0x3e, 0x08, 0x60, 0xa8, 0xab, 0xe0, 0x21, 0x01, 0x26, 0xf2,
+       0xe9, 0x30, 0x9f, 0x2d, 0x55, 0xc0, 0x6b, 0xa7, 0x7b, 0x99, 0x1d, 0xcf,
+       0x91, 0xbb, 0x0a, 0xf7, 0xff, 0x1d, 0xfa, 0xd5, 0x53, 0xb1, 0xbf, 0x64,
+       0xfe, 0x1d, 0xc2, 0xc9, 0x21, 0xe0, 0x74, 0x3c, 0xcf, 0xc3, 0xf3, 0x83,
+       0x45, 0xff, 0xa9, 0xcb, 0x5e, 0xa0, 0xf6, 0xf8, 0xd7, 0x59, 0x11, 0xd7,
+       0x9f, 0x97, 0xd3, 0x97, 0x61, 0x2e, 0x0b, 0xd1, 0xef, 0x8d, 0x89, 0xf1,
+       0xd5, 0x7e, 0xa2, 0xfd, 0x33, 0x1f, 0xf9, 0xed, 0xd7, 0xff, 0x9c, 0xc3,
+       0xad, 0x3d, 0x87, 0xdf, 0xd3, 0x63, 0x58, 0xc3, 0xc8, 0x0e, 0x7b, 0xa1,
+       0x32, 0xb0, 0xf7, 0x20, 0xc2, 0x27, 0x33, 0x89, 0xec, 0xec, 0x2c, 0x77,
+       0x56, 0x15, 0xd2, 0x47, 0xd6, 0x91, 0x6d, 0x0b, 0xf0, 0x3c, 0xc0, 0xfa,
+       0x9f, 0x73, 0xf9, 0x69, 0x58, 0xce, 0xe3, 0x4d, 0x59, 0x0a, 0x33, 0x5d,
+       0x85, 0xeb, 0x4e, 0x0b, 0xd8, 0x11, 0x8e, 0x89, 0xfb, 0x30, 0xf3, 0x70,
+       0xcf, 0x7c, 0x24, 0x36, 0x15, 0x2f, 0x89, 0xfb, 0x32, 0x53, 0x61, 0x5d,
+       0xb2, 0x73, 0xf8, 0xfe, 0xcc, 0x74, 0xbb, 0xaa, 0x8a, 0xa6, 0x8c, 0xb0,
+       0x4f, 0x13, 0xf6, 0x41, 0xe6, 0x91, 0xa1, 0xef, 0x61, 0xff, 0x89, 0xfb,
+       0x75, 0x87, 0xe5, 0x68, 0x29, 0xc2, 0xe5, 0xff, 0x02, 0x9f, 0x8b, 0xfa,
+       0xf4, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00,
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd5, 0x7d, 0x0b, 0x7c, 0x94, 0xc5,
+       0xd5, 0xf7, 0x3c, 0x7b, 0xcb, 0x26, 0xd9, 0x24, 0x9b, 0x04, 0x42, 0x42,
+       0x48, 0xd8, 0xcd, 0x8d, 0x40, 0x2e, 0x6c, 0xc2, 0xc5, 0x88, 0xa8, 0x4b,
+       0x48, 0x10, 0x2d, 0xe2, 0x22, 0x72, 0x35, 0xe2, 0x13, 0x12, 0x20, 0x40,
+       0x02, 0x01, 0xf4, 0x6b, 0x6c, 0xa9, 0x59, 0x0c, 0x37, 0x2d, 0xd6, 0xf0,
+       0x36, 0x0a, 0x5a, 0xd4, 0x8d, 0x05, 0x8a, 0x8a, 0x36, 0x28, 0x20, 0x56,
+       0x6c, 0x97, 0x8b, 0x8a, 0xd5, 0x6a, 0x5a, 0xf5, 0x2d, 0x55, 0x4b, 0x13,
+       0xa1, 0x8a, 0x72, 0x8b, 0xa1, 0x7d, 0x3f, 0xda, 0xfa, 0xb6, 0xdf, 0xfc,
+       0xcf, 0xcc, 0x24, 0xfb, 0x2c, 0x89, 0xd2, 0x7e, 0x6f, 0x7f, 0xbf, 0xef,
+       0x4b, 0x7f, 0x75, 0x98, 0xe7, 0x99, 0x67, 0xe6, 0xcc, 0x39, 0x67, 0xce,
+       0x9c, 0xdb, 0xcc, 0x32, 0x66, 0x63, 0x2e, 0x3b, 0xa3, 0xbf, 0x7f, 0x98,
+       0xf1, 0xdf, 0xaf, 0xaf, 0xaf, 0xd5, 0x3a, 0xee, 0x1f, 0x36, 0x9a, 0x31,
+       0x7f, 0x8a, 0xc5, 0xb3, 0xc3, 0xc5, 0x58, 0x5a, 0xe8, 0x7b, 0x37, 0xfe,
+       0xfb, 0xf7, 0x08, 0xd4, 0x35, 0x66, 0x72, 0xfd, 0x23, 0x93, 0xb1, 0x51,
+       0xae, 0x78, 0xc6, 0x06, 0xe2, 0x79, 0xbd, 0xcb, 0x57, 0xc0, 0xd8, 0x1e,
+       0x9b, 0x73, 0xa2, 0x63, 0x00, 0x63, 0x5d, 0x2b, 0x98, 0xe7, 0x29, 0xfe,
+       0x7d, 0xe9, 0x4b, 0x9b, 0xe6, 0xbe, 0xc5, 0xeb, 0xff, 0x95, 0xe6, 0x70,
+       0x46, 0xf0, 0x56, 0xa9, 0xc7, 0x9a, 0xdb, 0xf3, 0xf9, 0x73, 0x76, 0x40,
+       0x1f, 0x86, 0xf6, 0xdb, 0x2c, 0xfa, 0x93, 0xd1, 0xfc, 0xfd, 0xb6, 0xe3,
+       0x83, 0x98, 0x5f, 0x63, 0x2c, 0x22, 0x9a, 0xd5, 0xb7, 0x39, 0x38, 0x54,
+       0x26, 0xa6, 0xa3, 0xfc, 0x07, 0xfe, 0xae, 0xc7, 0x38, 0x56, 0x1a, 0x67,
+       0x94, 0xcb, 0xc4, 0xd8, 0x18, 0xc6, 0x78, 0x17, 0x01, 0x53, 0xf2, 0xbf,
+       0x5e, 0xb6, 0x0d, 0x19, 0x92, 0xe7, 0xf4, 0xf0, 0xfe, 0x02, 0x29, 0xed,
+       0x76, 0xde, 0x6f, 0x9b, 0xc5, 0x99, 0x67, 0xe1, 0xf5, 0x9c, 0xa1, 0xcd,
+       0x0f, 0x59, 0xaf, 0xc5, 0x3c, 0x38, 0x8c, 0xe3, 0x68, 0xda, 0x5e, 0x56,
+       0xc2, 0xd8, 0xb3, 0x47, 0xf9, 0xb8, 0x83, 0x51, 0x7d, 0xe4, 0xa1, 0x32,
+       0x0b, 0x7f, 0x1f, 0xd5, 0xf3, 0xde, 0x8f, 0xf7, 0x7b, 0x4c, 0x26, 0x59,
+       0x7f, 0xf4, 0xa1, 0xb2, 0x21, 0x8c, 0x0d, 0x39, 0xda, 0xb6, 0xc6, 0xe1,
+       0xe4, 0xf3, 0x1f, 0xda, 0xfa, 0x90, 0x9d, 0xe3, 0x2d, 0xf2, 0x57, 0xe2,
+       0xfd, 0x04, 0x5e, 0xf7, 0x67, 0x01, 0x2f, 0xb5, 0x43, 0x3b, 0xf8, 0xfc,
+       0x0e, 0xa7, 0x2f, 0xa1, 0xf9, 0x37, 0xfd, 0x2e, 0x82, 0x45, 0xf0, 0x76,
+       0x05, 0x66, 0xcf, 0x56, 0xd4, 0xd9, 0x47, 0x91, 0x6c, 0x07, 0xaf, 0xef,
+       0xda, 0x37, 0x7e, 0xb6, 0x8b, 0xb7, 0x6b, 0x8a, 0x19, 0xeb, 0xd2, 0xf3,
+       0x19, 0x2b, 0x73, 0x69, 0x34, 0xff, 0x52, 0x59, 0x86, 0xcf, 0xcb, 0x6c,
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+       0x1c, 0x88, 0xe0, 0xb0, 0x4c, 0x9e, 0xb0, 0x22, 0x19, 0xf3, 0x7d, 0x63,
+       0x0d, 0xfb, 0xd5, 0x28, 0x4e, 0xbf, 0x37, 0x26, 0x98, 0x59, 0x13, 0xb5,
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+       0x8e, 0xe3, 0x67, 0xaa, 0x79, 0xf7, 0x5a, 0xae, 0x71, 0xb3, 0xc9, 0x43,
+       0xac, 0x9f, 0x74, 0x84, 0xc8, 0xb5, 0x1b, 0x07, 0xec, 0xb1, 0x30, 0xae,
+       0xbf, 0xdc, 0x94, 0x65, 0x7c, 0x3e, 0x25, 0x9f, 0xd7, 0x43, 0xe4, 0xee,
+       0x54, 0x66, 0xe9, 0x7d, 0xcf, 0xe9, 0x7f, 0x08, 0xf8, 0x81, 0xdc, 0x61,
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+       0x57, 0x7e, 0xd2, 0xc8, 0xc0, 0x79, 0xec, 0x14, 0xd7, 0x0f, 0xbd, 0x39,
+       0x8c, 0x7d, 0xca, 0xf5, 0x0b, 0xd4, 0x4f, 0x37, 0x26, 0x53, 0xf9, 0x05,
+       0xd7, 0x07, 0x50, 0x9e, 0x6d, 0xcc, 0xa5, 0xf7, 0xe7, 0x1b, 0x3d, 0x54,
+       0xff, 0xc4, 0xed, 0xdb, 0x8a, 0x7e, 0xe7, 0x6f, 0xfc, 0xd2, 0x82, 0x7d,
+       0x69, 0x43, 0xa4, 0xc2, 0xb7, 0x80, 0x63, 0x95, 0xe4, 0xbb, 0x0d, 0x69,
+       0x63, 0xb7, 0xfc, 0x95, 0xe3, 0x75, 0xc3, 0xdb, 0x7c, 0x61, 0x70, 0x78,
+       0x6a, 0xda, 0x9a, 0x27, 0x71, 0x35, 0x8b, 0xad, 0x4a, 0xfb, 0xe4, 0x3e,
+       0xe8, 0xcf, 0xab, 0x9e, 0xd6, 0x3c, 0x68, 0xb7, 0xf4, 0xa0, 0xd7, 0xe6,
+       0xe0, 0xf0, 0x2c, 0x38, 0xaa, 0xaf, 0x07, 0x99, 0x17, 0xbd, 0xdd, 0x31,
+       0x15, 0x62, 0xa2, 0x0e, 0xfa, 0x2b, 0xd7, 0x1b, 0xee, 0xb7, 0xfa, 0x76,
+       0x62, 0xbc, 0x31, 0x1f, 0x9c, 0x4a, 0xd2, 0x79, 0x03, 0xef, 0xc1, 0xce,
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+       0x04, 0xd7, 0x99, 0xc6, 0xc9, 0x54, 0xfe, 0xcd, 0xed, 0xdb, 0x8d, 0xf6,
+       0x5e, 0xf6, 0xa5, 0x0d, 0xed, 0x6f, 0xde, 0xdd, 0x69, 0x49, 0xe5, 0xed,
+       0xcb, 0xbd, 0x9a, 0x17, 0xeb, 0xf1, 0x3a, 0x2f, 0x0b, 0x04, 0x38, 0x3c,
+       0x5b, 0xad, 0x42, 0xbe, 0x6f, 0xe5, 0xf2, 0x1d, 0xeb, 0x73, 0x42, 0xc1,
+       0xad, 0x8f, 0xdf, 0x05, 0x71, 0xe1, 0xd6, 0xf7, 0x83, 0x0f, 0x67, 0x24,
+       0x54, 0x95, 0x27, 0xf2, 0xe7, 0x53, 0x4b, 0x2a, 0x2d, 0x68, 0x37, 0xeb,
+       0x2b, 0x2e, 0xd3, 0xdc, 0xbd, 0x7c, 0xf8, 0xcd, 0xeb, 0x50, 0xe0, 0xa3,
+       0x4e, 0xd2, 0xe5, 0xdc, 0xcf, 0x35, 0xc2, 0xd3, 0xb9, 0xfd, 0x79, 0xb7,
+       0x5c, 0xc3, 0xfb, 0xfb, 0xf9, 0x31, 0x33, 0x33, 0x73, 0xb8, 0xba, 0x2f,
+       0x99, 0x08, 0xae, 0xee, 0xe3, 0x51, 0x01, 0x28, 0xad, 0xaa, 0xdd, 0xca,
+       0x7d, 0x66, 0xd2, 0x27, 0x57, 0xa6, 0xd9, 0x02, 0xc0, 0xdf, 0xca, 0x7d,
+       0x79, 0x83, 0xa0, 0x4f, 0x9d, 0xe1, 0x74, 0x63, 0x39, 0xbd, 0xe3, 0x9d,
+       0x79, 0xee, 0xdb, 0x2e, 0x3d, 0x44, 0x8e, 0x9e, 0x49, 0x68, 0xfb, 0xaf,
+       0x0f, 0x21, 0xa7, 0x7e, 0x2f, 0xe4, 0x14, 0xd7, 0x37, 0x3f, 0x7d, 0x0c,
+       0x72, 0x6c, 0xc8, 0x60, 0x0f, 0xe8, 0x7e, 0xde, 0xca, 0xf5, 0x72, 0x20,
+       0x9a, 0xd5, 0x47, 0x63, 0x1f, 0x5b, 0x66, 0x93, 0xeb, 0x8b, 0xcb, 0x19,
+       0xd4, 0xcf, 0x44, 0x31, 0xd2, 0x47, 0xc7, 0x3e, 0x9f, 0x5a, 0x8a, 0xf5,
+       0x82, 0xf1, 0x5c, 0xb6, 0x5e, 0x39, 0x94, 0xf3, 0xfc, 0x96, 0x8c, 0xef,
+       0xba, 0x7a, 0xc7, 0xdb, 0xd5, 0xb6, 0xe0, 0xc3, 0xc7, 0x78, 0xfd, 0x5c,
+       0xc0, 0xe4, 0xb7, 0xf2, 0x7d, 0xe6, 0x1c, 0x6b, 0x3b, 0xff, 0x33, 0xc8,
+       0xd1, 0xed, 0x0e, 0x0f, 0xec, 0x83, 0x0d, 0x1a, 0x87, 0x07, 0xfb, 0xe8,
+       0x8e, 0xc1, 0x54, 0xcf, 0xd5, 0x2c, 0x51, 0x0d, 0xc4, 0xcf, 0x01, 0x5a,
+       0xaf, 0xb9, 0x9a, 0xcb, 0xd2, 0xc0, 0xe5, 0x4f, 0xed, 0x0b, 0x8f, 0x0e,
+       0x06, 0x3f, 0xbd, 0xc2, 0x71, 0x50, 0xc2, 0xdf, 0xbf, 0xb2, 0x39, 0x9a,
+       0xe4, 0xd3, 0x2b, 0x56, 0xcf, 0x89, 0x06, 0xf4, 0xf7, 0xb8, 0xe8, 0xef,
+       0x27, 0x3f, 0xb8, 0xe7, 0x93, 0x03, 0x28, 0x1f, 0xac, 0x2b, 0xbe, 0x87,
+       0x97, 0x17, 0xdd, 0x09, 0xd4, 0x4f, 0xf5, 0x7f, 0x2c, 0x1e, 0x81, 0xef,
+       0xf9, 0x3e, 0xcd, 0x52, 0x78, 0x7f, 0xcf, 0xbe, 0xa4, 0x05, 0x23, 0xf9,
+       0xfa, 0x2c, 0x68, 0x39, 0x74, 0x5f, 0x0a, 0x87, 0x6f, 0xe4, 0xb6, 0x4e,
+       0xd3, 0x60, 0x5e, 0x16, 0x6d, 0xd7, 0x9a, 0x50, 0xe6, 0xa5, 0xdd, 0x74,
+       0xcc, 0xcc, 0xdf, 0xff, 0xc5, 0xed, 0x12, 0x76, 0xeb, 0x6e, 0xb7, 0x39,
+       0x15, 0xcb, 0x6a, 0x70, 0xe0, 0xc3, 0xeb, 0x69, 0xff, 0x36, 0xee, 0xeb,
+       0xf9, 0x2d, 0x5f, 0x96, 0xc2, 0xbc, 0x54, 0xfb, 0xfb, 0x08, 0xad, 0xed,
+       0x8b, 0x56, 0xd8, 0xc3, 0xe9, 0xc7, 0x8b, 0x75, 0xc2, 0x5f, 0x33, 0xc1,
+       0xb1, 0xef, 0xe0, 0xf4, 0xf7, 0x6e, 0x67, 0x98, 0x07, 0xd7, 0x1c, 0x00,
+       0x77, 0xa5, 0xcd, 0x43, 0xfb, 0x49, 0xc0, 0xdf, 0x0a, 0x3a, 0x9f, 0xd3,
+       0x73, 0x3d, 0x0f, 0x60, 0x4d, 0xfb, 0xfc, 0x8f, 0x82, 0xbe, 0xe7, 0xf4,
+       0x24, 0x0f, 0xf6, 0x97, 0xfd, 0x26, 0x7f, 0xec, 0x38, 0xb4, 0x3f, 0x61,
+       0xa1, 0x79, 0xbe, 0xb4, 0xfd, 0xd7, 0xb1, 0x56, 0x5e, 0x8f, 0xdb, 0x6b,
+       0x65, 0x91, 0xfc, 0x7d, 0x5d, 0x51, 0xd7, 0x24, 0xb4, 0xaf, 0x4b, 0x73,
+       0x91, 0x1d, 0x9e, 0xf6, 0xc4, 0x0d, 0x93, 0x81, 0x9f, 0x65, 0x7b, 0xf7,
+       0xb5, 0x52, 0x3f, 0xb5, 0x76, 0x8f, 0x86, 0x75, 0xb6, 0xef, 0xe2, 0xeb,
+       0xa9, 0xb0, 0x87, 0x6e, 0x64, 0x9e, 0x6c, 0xf0, 0xdd, 0x5e, 0x51, 0xff,
+       0x7e, 0x99, 0xd7, 0x03, 0x7e, 0xab, 0x69, 0xfd, 0xb3, 0xa8, 0xb7, 0xfb,
+       0xa8, 0xee, 0x33, 0xfb, 0xdd, 0x16, 0xb4, 0xaf, 0x12, 0x7a, 0xce, 0x16,
+       0xb9, 0x8f, 0xb1, 0x8e, 0x42, 0x92, 0x77, 0xc4, 0xca, 0xae, 0x5e, 0x7a,
+       0x7d, 0x9f, 0xbf, 0xc6, 0xfb, 0xad, 0x6e, 0x7f, 0x4a, 0xbd, 0xa3, 0x77,
+       0xff, 0xe3, 0xfb, 0xd6, 0x90, 0x0c, 0xfe, 0x3e, 0xc5, 0x26, 0xbf, 0x77,
+       0x4e, 0x4f, 0xf7, 0xfd, 0x13, 0xfb, 0x96, 0x4d, 0xee, 0x43, 0xaa, 0xbf,
+       0x2d, 0x36, 0xe6, 0x8f, 0xe4, 0xfd, 0xa4, 0xf1, 0xe7, 0x1a, 0xf6, 0x55,
+       0x9b, 0xd8, 0x6f, 0x77, 0x70, 0xf9, 0x02, 0x7e, 0x51, 0xfb, 0x2d, 0x1f,
+       0x37, 0x1f, 0xe3, 0xf2, 0xef, 0xbd, 0x90, 0x93, 0xa9, 0x7c, 0x73, 0x2d,
+       0xe2, 0xf3, 0x49, 0xdd, 0x12, 0x11, 0xa0, 0x3d, 0xfd, 0x0a, 0xc7, 0x57,
+       0x7a, 0xd2, 0xf2, 0x28, 0x21, 0xcf, 0x94, 0xfe, 0x31, 0x3b, 0xb1, 0xe9,
+       0xd5, 0x0e, 0x8e, 0xd7, 0x3f, 0xc5, 0xea, 0x25, 0x19, 0xbc, 0xdd, 0x02,
+       0xb9, 0x5f, 0x33, 0x8b, 0x27, 0x19, 0xf3, 0x3b, 0x19, 0xeb, 0xbd, 0x3a,
+       0x83, 0xf6, 0xbf, 0xae, 0x74, 0xcc, 0x81, 0xef, 0x87, 0xd7, 0xa2, 0xbe,
+       0xcc, 0xcc, 0xf5, 0xa7, 0xcc, 0x10, 0xfd, 0xc9, 0x7e, 0x65, 0xfb, 0x61,
+       0x44, 0x9c, 0x77, 0x22, 0xbe, 0xbf, 0xd2, 0xf6, 0xe3, 0xa3, 0xfa, 0x96,
+       0xbf, 0xe3, 0xbb, 0x4b, 0x48, 0xfe, 0xbe, 0x2a, 0xe5, 0xef, 0xaa, 0x3f,
+       0x9b, 0x58, 0x11, 0xaf, 0xaf, 0x7a, 0x38, 0x82, 0xe4, 0x09, 0xed, 0x69,
+       0x7d, 0xe0, 0xe5, 0x55, 0xbe, 0xde, 0x75, 0x2e, 0x5f, 0x7e, 0x01, 0xbf,
+       0x01, 0x2f, 0xaf, 0xfd, 0x53, 0x87, 0x99, 0xec, 0x8f, 0xa3, 0xa6, 0xda,
+       0xd7, 0xf9, 0x7e, 0x4a, 0x43, 0x67, 0xe0, 0x3f, 0x5d, 0x4d, 0x71, 0xa3,
+       0xa9, 0xee, 0x05, 0x99, 0xaf, 0xfb, 0x93, 0xa9, 0x4f, 0xfb, 0x50, 0x95,
+       0x9c, 0x4e, 0x95, 0xa0, 0x93, 0xf7, 0x2b, 0xa3, 0xbf, 0xe1, 0xfa, 0xaf,
+       0x9c, 0x36, 0xea, 0xdf, 0x91, 0x70, 0x45, 0xf3, 0x35, 0xf7, 0x33, 0x5f,
+       0x73, 0xac, 0x98, 0xef, 0x41, 0xcc, 0x97, 0xd3, 0x6e, 0xd5, 0x97, 0xc5,
+       0x24, 0x2f, 0x0f, 0x5e, 0xe1, 0x3c, 0xd3, 0x22, 0xbc, 0x2b, 0x01, 0x5f,
+       0xf8, 0x3c, 0x38, 0xdc, 0x0d, 0xa0, 0x47, 0x38, 0xdc, 0x3d, 0xfc, 0xdd,
+       0x75, 0x65, 0x70, 0xdf, 0xad, 0x31, 0xbf, 0x09, 0xeb, 0xec, 0x4b, 0x5b,
+       0x00, 0xeb, 0xec, 0x20, 0x07, 0x13, 0xeb, 0xf6, 0xe0, 0xe2, 0xfc, 0x00,
+       0xd6, 0xf3, 0x7e, 0x9b, 0xa8, 0xfb, 0x63, 0x6d, 0xa4, 0x7f, 0x1e, 0x8c,
+       0x61, 0x7e, 0xc8, 0x8f, 0x83, 0xd3, 0x92, 0x02, 0x7e, 0xec, 0xe7, 0x68,
+       0x0f, 0xf9, 0x30, 0x90, 0x89, 0xf7, 0x91, 0xf2, 0xfb, 0x39, 0x49, 0xf4,
+       0xfd, 0xe0, 0x08, 0xce, 0xff, 0xbc, 0xce, 0x6e, 0x8f, 0x92, 0xfd, 0xd7,
+       0xbf, 0x55, 0x80, 0xf7, 0x6b, 0x52, 0x3d, 0x1c, 0x02, 0xae, 0xdf, 0x06,
+       0x36, 0x66, 0x90, 0x7e, 0x6b, 0x26, 0xbf, 0xe1, 0x71, 0x29, 0xaf, 0x5b,
+       0xe2, 0x83, 0xb7, 0x9b, 0xf9, 0xf3, 0x96, 0x2f, 0x73, 0x18, 0xc6, 0x39,
+       0xce, 0x82, 0xa9, 0xcb, 0xd1, 0xae, 0x26, 0x8a, 0xe4, 0x50, 0x4b, 0xbc,
+       0x37, 0x25, 0x81, 0xe3, 0x71, 0xff, 0xdf, 0xcd, 0xb4, 0x2f, 0xb4, 0x14,
+       0xf1, 0xba, 0x83, 0xe4, 0x34, 0xf9, 0x77, 0x5a, 0xa6, 0x79, 0x53, 0xe2,
+       0x79, 0x7d, 0xae, 0xa4, 0x4b, 0x4b, 0x6b, 0x60, 0xc7, 0x23, 0xe8, 0x6f,
+       0x5a, 0xae, 0xc7, 0xcf, 0xc7, 0x19, 0x6c, 0x66, 0xf5, 0xd4, 0xce, 0x2d,
+       0xfa, 0xf9, 0xd0, 0x2a, 0xbe, 0xfb, 0x9d, 0xa4, 0x0b, 0x5f, 0xc7, 0xb4,
+       0xce, 0x8f, 0x66, 0xcc, 0xdf, 0x03, 0xfc, 0xeb, 0x53, 0xa3, 0x2d, 0xf0,
+       0x8b, 0x70, 0x8c, 0xa7, 0x68, 0x1c, 0xfe, 0xc7, 0xaa, 0xb3, 0x19, 0xc9,
+       0x4b, 0xe9, 0xf7, 0x9a, 0x2d, 0x69, 0x30, 0xb7, 0x97, 0x0f, 0xbc, 0xf6,
+       0xb1, 0xd0, 0x6b, 0xc5, 0xdf, 0x9c, 0x05, 0x3b, 0x22, 0x21, 0x8f, 0x67,
+       0xd4, 0x44, 0x92, 0x5f, 0xea, 0x78, 0xcd, 0x7d, 0x31, 0x2e, 0x3e, 0xde,
+       0x0c, 0xdd, 0x1c, 0x8c, 0x80, 0xfe, 0x77, 0x5b, 0xb9, 0xc1, 0xef, 0x74,
+       0x34, 0xc3, 0x4b, 0xe3, 0x72, 0xc3, 0x42, 0xda, 0x09, 0xc1, 0x2a, 0xe0,
+       0xf1, 0xe7, 0x5d, 0x76, 0x06, 0xb9, 0xdc, 0x1f, 0x3d, 0xeb, 0xda, 0x26,
+       0x24, 0x9e, 0x0a, 0xe1, 0x87, 0x1a, 0x9b, 0x90, 0x1f, 0xa7, 0xa5, 0x3e,
+       0xf4, 0x72, 0x8c, 0xfe, 0x0b, 0xf0, 0xcd, 0xf2, 0x03, 0x37, 0x26, 0x9e,
+       0x0a, 0xd1, 0xf7, 0xaa, 0x17, 0x94, 0xe7, 0x40, 0x7f, 0x56, 0xe3, 0x7d,
+       0x13, 0xdf, 0x34, 0x81, 0x4e, 0x23, 0x69, 0xbd, 0xfa, 0x4d, 0xe0, 0x8f,
+       0xb6, 0x48, 0xa2, 0xff, 0xe4, 0x5b, 0xed, 0x44, 0xef, 0x6e, 0x87, 0xe9,
+       0x29, 0xf8, 0x25, 0xef, 0x94, 0xf2, 0xaa, 0x09, 0x86, 0x30, 0x7f, 0xde,
+       0xb4, 0x2f, 0x22, 0x70, 0x1f, 0x7f, 0xb6, 0x3c, 0x22, 0x38, 0x13, 0xf2,
+       0x8a, 0xd3, 0xff, 0xe9, 0x9d, 0xa0, 0xeb, 0xab, 0x91, 0x44, 0xff, 0x5a,
+       0x9b, 0xe0, 0xa7, 0xda, 0x9f, 0xe5, 0x11, 0x7f, 0xed, 0xb7, 0x79, 0xdd,
+       0xeb, 0xd0, 0xff, 0xcf, 0x23, 0x88, 0xee, 0xb5, 0xb1, 0xae, 0x38, 0x7a,
+       0xff, 0xcb, 0x44, 0x26, 0xf9, 0x8f, 0xf4, 0x86, 0xda, 0xa8, 0x60, 0x4e,
+       0x3c, 0xc7, 0xe7, 0xc6, 0x68, 0xfd, 0x43, 0xe0, 0x8d, 0xf3, 0x1d, 0xf9,
+       0x83, 0x6b, 0x6d, 0xe2, 0xf9, 0x09, 0xc9, 0x57, 0x27, 0x78, 0x1f, 0x80,
+       0xc3, 0x5f, 0x1f, 0x43, 0xfc, 0xc8, 0x64, 0x5d, 0xff, 0x6e, 0x22, 0xd9,
+       0x53, 0x5c, 0x1f, 0x25, 0xfe, 0xd5, 0x1f, 0xca, 0xa3, 0xba, 0x6e, 0xf3,
+       0xa6, 0x2c, 0xc0, 0xfa, 0x58, 0x19, 0x4d, 0xf0, 0x9d, 0x90, 0xfe, 0xb4,
+       0x13, 0xb5, 0xf1, 0xc4, 0xdf, 0x15, 0x0f, 0x2d, 0x7d, 0x9b, 0x71, 0x7a,
+       0x9e, 0xf0, 0xed, 0xbc, 0x3f, 0x87, 0xb7, 0x3b, 0x71, 0xd0, 0xea, 0xc1,
+       0xbe, 0xf4, 0x71, 0x83, 0x39, 0x68, 0xe3, 0x74, 0x3d, 0xbf, 0xfa, 0xe4,
+       0xd8, 0xad, 0xbc, 0xde, 0x71, 0xdf, 0x47, 0xe9, 0x7a, 0x88, 0x1f, 0xad,
+       0xe2, 0xbe, 0xba, 0x29, 0xf8, 0xae, 0x62, 0xc9, 0xea, 0xa9, 0xd8, 0x2f,
+       0xfb, 0xc3, 0x77, 0x45, 0x6d, 0x04, 0x97, 0xb9, 0xbd, 0x74, 0xb2, 0x66,
+       0x7a, 0xff, 0x04, 0xfa, 0xb9, 0x33, 0xf5, 0xff, 0x8d, 0x79, 0x2e, 0xcf,
+       0xef, 0x58, 0x08, 0xb9, 0x77, 0xde, 0xd6, 0xfe, 0x04, 0xec, 0x83, 0x0f,
+       0xe3, 0xf4, 0xbf, 0xe2, 0xfd, 0x85, 0x97, 0x3f, 0xdb, 0x49, 0xf2, 0xd0,
+       0xd2, 0x95, 0x03, 0xfd, 0x7c, 0x99, 0x85, 0xf3, 0x01, 0xf8, 0x52, 0xee,
+       0x9f, 0xcb, 0x25, 0x5f, 0x06, 0x32, 0x75, 0x96, 0x39, 0x86, 0xf0, 0x47,
+       0xfa, 0x78, 0x74, 0x7e, 0xbb, 0x90, 0x7b, 0xab, 0xaf, 0x4c, 0xce, 0x7f,
+       0x71, 0x70, 0xc7, 0x7e, 0x8d, 0x8f, 0xb3, 0x34, 0xea, 0xe0, 0x32, 0x2a,
+       0xcd, 0x81, 0x42, 0xf4, 0x73, 0x46, 0x0b, 0xc6, 0x6a, 0x99, 0xc0, 0x1f,
+       0xd7, 0xe3, 0x78, 0x7f, 0x67, 0x9d, 0xc1, 0x58, 0xd0, 0x41, 0x97, 0x76,
+       0xd3, 0xd2, 0x5d, 0xc6, 0x79, 0xe1, 0x0f, 0x7e, 0x95, 0xa5, 0xf8, 0x07,
+       0xff, 0x6e, 0x69, 0x9b, 0x99, 0xfc, 0x2a, 0x1c, 0x42, 0x1b, 0xe0, 0x5f,
+       0x0a, 0x4f, 0xaf, 0x21, 0x9e, 0x20, 0xe4, 0x0a, 0xef, 0xe7, 0x29, 0x5a,
+       0x87, 0x8e, 0x8f, 0xe7, 0x7d, 0x97, 0xe3, 0x7f, 0xc9, 0xd3, 0xc3, 0x8b,
+       0xa1, 0x4f, 0x2e, 0x8d, 0x3f, 0xf0, 0x83, 0x6b, 0xa8, 0x1d, 0xff, 0x4e,
+       0xf1, 0xb9, 0xf9, 0xf2, 0xba, 0x9a, 0xcf, 0xe5, 0xf0, 0x88, 0xf9, 0x9d,
+       0x95, 0x7c, 0x7e, 0x96, 0x49, 0x39, 0x38, 0xdb, 0xd6, 0x63, 0x87, 0x43,
+       0x0f, 0x3a, 0xff, 0xdc, 0x20, 0x03, 0xdf, 0x9c, 0x7f, 0x7a, 0x38, 0xd5,
+       0xbf, 0xd0, 0xba, 0xb4, 0x28, 0x0e, 0xd7, 0x79, 0x29, 0x8f, 0x98, 0xa7,
+       0x6d, 0xec, 0x34, 0x18, 0x10, 0xde, 0xb6, 0xb1, 0xd0, 0x67, 0x1f, 0x91,
+       0xcf, 0x97, 0x26, 0xb6, 0x8d, 0x85, 0xfc, 0x51, 0xf2, 0x88, 0xd9, 0xdb,
+       0x0a, 0xc9, 0xae, 0xce, 0x6d, 0x2b, 0x84, 0x3d, 0xa9, 0xe4, 0x19, 0xf3,
+       0xb5, 0xe5, 0xd0, 0xf3, 0x40, 0x5b, 0x0e, 0xbe, 0xdf, 0x6f, 0x12, 0x7e,
+       0x0a, 0xfa, 0xc3, 0xbc, 0x9f, 0x4d, 0x6d, 0x25, 0x3c, 0xd8, 0xc5, 0x7a,
+       0x5c, 0xf2, 0x6c, 0x1e, 0xe1, 0x45, 0x8d, 0x13, 0x4e, 0xbf, 0xf0, 0xf9,
+       0x5e, 0x9f, 0x29, 0xfc, 0xdc, 0x1c, 0xde, 0x3b, 0x7d, 0xbc, 0xfd, 0xb0,
+       0xad, 0x36, 0xc3, 0xfb, 0xe1, 0x01, 0x63, 0xfd, 0x06, 0xd9, 0x7e, 0x68,
+       0x18, 0x5d, 0x06, 0x9b, 0xbb, 0x0e, 0x45, 0x40, 0xde, 0xff, 0x98, 0xd1,
+       0x7a, 0x0d, 0x1f, 0x77, 0xaa, 0xfc, 0xee, 0x99, 0x67, 0x7a, 0xe8, 0x60,
+       0x96, 0xf6, 0x22, 0x73, 0x29, 0xfa, 0xbb, 0x84, 0xbe, 0x6d, 0x05, 0xbe,
+       0x7f, 0xd7, 0x83, 0xef, 0xbb, 0x52, 0xb9, 0x3c, 0x5d, 0x8a, 0x39, 0x66,
+       0xf4, 0xce, 0x7f, 0x7f, 0x91, 0x9e, 0x0a, 0xb9, 0x7f, 0xde, 0x24, 0xfc,
+       0xd4, 0xfb, 0xe3, 0x79, 0x3d, 0x1f, 0x7a, 0x8e, 0xc0, 0xa7, 0xaa, 0x2b,
+       0x3c, 0x86, 0xf3, 0xd1, 0x7d, 0xbf, 0x5b, 0x98, 0x8a, 0x78, 0xca, 0x3d,
+       0x99, 0x26, 0xa9, 0x54, 0x7a, 0x06, 0x81, 0xdf, 0x9a, 0x20, 0x2f, 0xb9,
+       0xbc, 0x68, 0xb2, 0x0a, 0x7c, 0x7c, 0xd1, 0x58, 0x33, 0xea, 0x94, 0x05,
+       0xf6, 0x68, 0x7d, 0x4a, 0xb5, 0xa5, 0x77, 0x3e, 0x0b, 0xb7, 0x16, 0xd9,
+       0xb1, 0x5e, 0x16, 0x6d, 0x2b, 0xb2, 0xcf, 0x0f, 0xb1, 0x77, 0x9a, 0x76,
+       0x8d, 0x3a, 0xe6, 0xe2, 0x74, 0x39, 0xbb, 0xcb, 0x42, 0x6e, 0x83, 0x26,
+       0x4b, 0xe0, 0x07, 0xd0, 0xa3, 0x9b, 0x76, 0x99, 0xdb, 0xfc, 0x8c, 0xde,
+       0xdb, 0xbd, 0xbc, 0xfd, 0x59, 0xc7, 0xe1, 0x77, 0xd0, 0x6e, 0xe1, 0xb6,
+       0xf8, 0x62, 0xe8, 0xbd, 0xea, 0xfb, 0x45, 0x5b, 0xef, 0x4e, 0xa9, 0x0e,
+       0xc1, 0x77, 0xde, 0x2e, 0x23, 0xfe, 0x0b, 0xda, 0x8c, 0x75, 0xf8, 0xa3,
+       0x43, 0xeb, 0x4d, 0xd0, 0x05, 0xc7, 0xfc, 0xf3, 0xdf, 0x15, 0x05, 0x8d,
+       0xf5, 0x51, 0xc7, 0x8c, 0xf5, 0xcf, 0xde, 0xbf, 0x6b, 0x26, 0xd8, 0xf8,
+       0xa5, 0x12, 0xc1, 0xef, 0xa7, 0x03, 0x31, 0x01, 0xc4, 0xa9, 0x6a, 0x3e,
+       0x9a, 0x74, 0x0c, 0xfb, 0xda, 0xe9, 0xfd, 0x2f, 0xc5, 0x82, 0x3e, 0x4b,
+       0x7f, 0x5f, 0xfd, 0x3a, 0xec, 0x96, 0x45, 0x5b, 0x8d, 0x7c, 0xc6, 0xe9,
+       0xa6, 0x41, 0xaf, 0xf7, 0xef, 0xd4, 0x88, 0x3f, 0x16, 0x07, 0xc2, 0xd7,
+       0x9d, 0x5c, 0xef, 0x97, 0xad, 0xc7, 0x35, 0xca, 0xaf, 0x99, 0x1b, 0xca,
+       0x27, 0xe1, 0xf4, 0x3c, 0xc3, 0xda, 0x66, 0x7a, 0x39, 0x3f, 0xd5, 0x36,
+       0xac, 0x1c, 0x85, 0x78, 0x48, 0xcd, 0x14, 0xce, 0xb8, 0x1c, 0x9e, 0xab,
+       0xdb, 0x36, 0xdb, 0x10, 0x37, 0x08, 0x1f, 0xaf, 0xbf, 0x75, 0xcf, 0x1c,
+       0x5e, 0x17, 0xfc, 0x55, 0x95, 0x25, 0xe2, 0xdd, 0xb8, 0x86, 0x52, 0x76,
+       0x12, 0x4e, 0xdf, 0x4d, 0xbf, 0x9e, 0x84, 0xf5, 0x56, 0xf9, 0x7d, 0x8d,
+       0xf6, 0xff, 0xca, 0x17, 0x87, 0x1d, 0x85, 0xfc, 0xee, 0xdc, 0x33, 0xe7,
+       0x26, 0x2a, 0x67, 0x4e, 0x26, 0x3c, 0x28, 0xff, 0xd9, 0xa2, 0x83, 0x5a,
+       0x30, 0x86, 0xd7, 0x9d, 0x25, 0xae, 0x03, 0x1d, 0xfc, 0xbb, 0x05, 0x01,
+       0x8d, 0xf6, 0x87, 0xf9, 0x6b, 0x23, 0x7a, 0xe5, 0x10, 0xff, 0x7f, 0xf5,
+       0xa6, 0x30, 0x38, 0x5a, 0x42, 0xde, 0x73, 0xf8, 0x17, 0x1d, 0x38, 0xf4,
+       0x17, 0x8d, 0xf7, 0x5f, 0xb3, 0xcd, 0xf8, 0xdd, 0x62, 0x8e, 0x2f, 0xc8,
+       0xfd, 0x25, 0xdb, 0xff, 0x11, 0x11, 0xfa, 0x5c, 0xd9, 0x7d, 0xe3, 0x0e,
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+       0x63, 0xa3, 0x9f, 0x27, 0x35, 0xb2, 0x7f, 0xea, 0xe0, 0x6c, 0x44, 0xfd,
+       0xc7, 0xa2, 0xbe, 0x98, 0x05, 0x69, 0x1e, 0xe0, 0x17, 0x6f, 0xe8, 0xfc,
+       0x02, 0xc6, 0x3a, 0x6b, 0x16, 0x76, 0x53, 0xad, 0x25, 0x78, 0x08, 0xf8,
+       0x58, 0xc2, 0x3a, 0x84, 0xdd, 0xc3, 0xe9, 0xe8, 0x0d, 0x89, 0xc7, 0xd5,
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+       0x39, 0x65, 0x57, 0x9a, 0x6d, 0xcc, 0x0b, 0xfd, 0xd8, 0x7c, 0x6f, 0x14,
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+       0x37, 0x85, 0xe8, 0xa5, 0xce, 0x2c, 0x21, 0xe7, 0xc7, 0x96, 0x7a, 0x77,
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+       0xf5, 0x23, 0x26, 0x57, 0x93, 0xbb, 0x17, 0xef, 0xcc, 0xeb, 0xcd, 0xc1,
+       0xfc, 0x4f, 0x6d, 0x8e, 0x2c, 0x06, 0x9f, 0x8d, 0x2d, 0x15, 0xfe, 0x9e,
+       0x13, 0x45, 0x42, 0x6e, 0x47, 0x8f, 0x66, 0xde, 0x00, 0x2f, 0x53, 0x64,
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+       0x92, 0xdf, 0xe1, 0xf3, 0xc8, 0x96, 0xfd, 0x54, 0xdb, 0x7c, 0xbf, 0xbc,
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+       0x4f, 0x09, 0xb8, 0x38, 0x5d, 0x79, 0x7d, 0xec, 0x7f, 0x44, 0x92, 0x7f,
+       0xee, 0x94, 0xdc, 0x57, 0x14, 0xfe, 0x39, 0xdf, 0x8c, 0xa1, 0x7d, 0x5a,
+       0xc5, 0x49, 0x25, 0x9f, 0x6c, 0x06, 0xfd, 0xb1, 0x9f, 0x2d, 0x16, 0x76,
+       0x50, 0x2f, 0x9f, 0x18, 0xf9, 0x60, 0xae, 0x26, 0xf0, 0xca, 0x1e, 0x14,
+       0xfa, 0x69, 0x4b, 0xbc, 0xa8, 0x2b, 0x3e, 0xe0, 0xf6, 0x0e, 0xfb, 0x2b,
+       0xf8, 0xa4, 0x9c, 0x11, 0xde, 0xfb, 0xb3, 0x7b, 0xd4, 0x3c, 0x5b, 0x5a,
+       0xc5, 0x7b, 0x4e, 0xef, 0x6b, 0xb3, 0xc6, 0x5c, 0x6e, 0xf7, 0x28, 0x7a,
+       0x33, 0x4b, 0x60, 0x0c, 0xec, 0xc6, 0xfe, 0xe8, 0x3d, 0xbf, 0x24, 0x7e,
+       0xac, 0x66, 0xa2, 0xb8, 0xb5, 0x1f, 0x71, 0x6b, 0xec, 0x75, 0x84, 0x97,
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+       0xc1, 0x5f, 0x5c, 0x2a, 0xfb, 0xa3, 0x8a, 0xa9, 0xbd, 0xd7, 0xc6, 0xeb,
+       0x95, 0x3f, 0x5c, 0xc4, 0xbc, 0xbc, 0x7d, 0x65, 0x2a, 0x23, 0x7f, 0x10,
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+       0x6b, 0xae, 0x79, 0xfb, 0xf8, 0x83, 0xf9, 0x33, 0x8e, 0xd8, 0x92, 0xf9,
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+       0xed, 0x93, 0xfc, 0xde, 0x34, 0x41, 0xdb, 0x06, 0xbd, 0x66, 0xe8, 0x44,
+       0xb1, 0xbe, 0x54, 0x7b, 0xf4, 0x83, 0x7e, 0x5f, 0xc9, 0x12, 0x7a, 0xd0,
+       0x7d, 0xb2, 0x54, 0x75, 0x8e, 0x57, 0x6a, 0x5f, 0xbd, 0x31, 0xa2, 0x33,
+       0x33, 0x16, 0xa5, 0x35, 0x38, 0x0c, 0xfb, 0x5d, 0x4e, 0xe9, 0x7a, 0xf0,
+       0xd5, 0x94, 0x0c, 0x36, 0x69, 0x2b, 0xf0, 0x7e, 0x8f, 0x19, 0xb9, 0x0a,
+       0x1c, 0xde, 0xae, 0x4a, 0x5a, 0xf7, 0x31, 0x39, 0x2e, 0xf0, 0xa9, 0xce,
+       0x58, 0x90, 0xf2, 0x23, 0x02, 0xc3, 0x89, 0xaf, 0x3b, 0x27, 0x74, 0x75,
+       0x6e, 0xe0, 0xf5, 0xce, 0xd6, 0x61, 0x1e, 0xf2, 0xf9, 0x48, 0x3b, 0x7a,
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+       0x47, 0x0c, 0xf1, 0xab, 0xb4, 0xab, 0xab, 0x24, 0x6b, 0xfc, 0xb1, 0x61,
+       0xe2, 0x23, 0x57, 0xf1, 0xf6, 0x55, 0x0e, 0x5b, 0x27, 0xf6, 0x83, 0x05,
+       0x0f, 0x4f, 0x8f, 0x45, 0x9e, 0x49, 0x55, 0x8b, 0x59, 0xe4, 0x73, 0x6c,
+       0x32, 0xda, 0xd5, 0xdc, 0xfe, 0x0d, 0x00, 0xde, 0x70, 0x3b, 0x39, 0xdc,
+       0x1e, 0x06, 0xcf, 0x80, 0x8f, 0xaa, 0x37, 0x69, 0xc4, 0x87, 0x43, 0x9b,
+       0x3c, 0xb6, 0x14, 0x92, 0x63, 0x9a, 0x13, 0xf3, 0xab, 0x76, 0x04, 0xb3,
+       0x20, 0xdf, 0xab, 0x3d, 0x91, 0x1e, 0xbc, 0x3f, 0xdb, 0xe8, 0x4d, 0x3c,
+       0x95, 0x85, 0x78, 0xc4, 0x64, 0x2a, 0xd9, 0x57, 0x1c, 0xef, 0x63, 0xe1,
+       0x8f, 0x65, 0x94, 0xc4, 0xf1, 0x62, 0xb6, 0xfe, 0x1c, 0xf8, 0xa1, 0xb2,
+       0xb9, 0x92, 0xec, 0xc5, 0xe8, 0x7c, 0x9d, 0xe4, 0xd3, 0xd9, 0x2c, 0xc1,
+       0x77, 0x53, 0xe0, 0x4f, 0x84, 0xbc, 0xb1, 0x74, 0xa4, 0x60, 0x1d, 0xce,
+       0x53, 0xcf, 0x13, 0x9c, 0x39, 0x0e, 0xe2, 0xe7, 0x48, 0x06, 0x3c, 0x74,
+       0x5a, 0x9d, 0x39, 0x80, 0xab, 0x73, 0x5d, 0xa4, 0x09, 0xfb, 0xe6, 0x94,
+       0xfb, 0x04, 0x5f, 0xf3, 0x75, 0x66, 0xb7, 0xf0, 0xef, 0xef, 0xb7, 0xb0,
+       0x28, 0xac, 0xf7, 0xef, 0xe2, 0x7b, 0x3e, 0x5e, 0xc5, 0x1a, 0x8b, 0xaf,
+       0x95, 0xd7, 0x87, 0xd8, 0x99, 0x25, 0x26, 0x01, 0x7c, 0x55, 0x44, 0x7c,
+       0x9d, 0x39, 0x4c, 0xbf, 0x0f, 0xf0, 0x9c, 0xfe, 0x1e, 0x2b, 0xc1, 0xfe,
+       0x5f, 0xb5, 0x69, 0x33, 0xc1, 0xa3, 0xf8, 0x82, 0x59, 0xda, 0xcb, 0x12,
+       0xa1, 0xdf, 0xed, 0x70, 0x17, 0x3f, 0xc0, 0x7a, 0xf9, 0x28, 0x73, 0x58,
+       0xe9, 0x51, 0xe0, 0xaf, 0x87, 0x1f, 0x6e, 0xd3, 0x88, 0x0f, 0x78, 0x79,
+       0x28, 0x93, 0xf8, 0xe1, 0xd6, 0x37, 0x89, 0x1f, 0x4a, 0x83, 0x59, 0x2b,
+       0xf3, 0x11, 0xc7, 0xaa, 0x65, 0x5e, 0xc4, 0x11, 0x92, 0x99, 0x07, 0xfe,
+       0x80, 0x6e, 0xd6, 0x45, 0xfa, 0x44, 0x37, 0xd7, 0x27, 0x20, 0xcf, 0x94,
+       0x3c, 0x51, 0x72, 0x83, 0xf3, 0x81, 0x17, 0x79, 0x3d, 0x8a, 0xbe, 0x4a,
+       0x7e, 0xec, 0x6c, 0xe4, 0x20, 0x71, 0xbc, 0xee, 0x6a, 0xb4, 0x53, 0xf9,
+       0x4c, 0xa3, 0x93, 0x59, 0xb8, 0x0c, 0xd8, 0xdd, 0x98, 0x4c, 0xf5, 0xe7,
+       0x1b, 0x5d, 0x54, 0xb6, 0x35, 0xe6, 0xd2, 0xf3, 0x17, 0x1a, 0x3d, 0x54,
+       0xdf, 0xdb, 0x58, 0x42, 0xf5, 0xfd, 0x8d, 0x5e, 0xaa, 0x1f, 0x68, 0x9c,
+       0x4c, 0xe5, 0xcf, 0x1a, 0x7d, 0xf4, 0x9c, 0xe3, 0x85, 0xe4, 0x90, 0x92,
+       0x2b, 0x4a, 0x1e, 0x29, 0x7e, 0x52, 0x72, 0x29, 0x9c, 0x8f, 0xe6, 0x71,
+       0xf4, 0x5e, 0x57, 0x4c, 0xdf, 0x93, 0xdc, 0x53, 0xf2, 0x0e, 0xf3, 0x30,
+       0x15, 0xf7, 0xca, 0x23, 0x45, 0xdf, 0x0c, 0xcd, 0xe7, 0x4f, 0x76, 0x43,
+       0x8e, 0x75, 0xcc, 0x81, 0xbc, 0x28, 0x37, 0x9f, 0x7d, 0xee, 0x25, 0xf8,
+       0x49, 0x6a, 0x1c, 0x9e, 0x08, 0x17, 0xf0, 0x22, 0xe4, 0x5e, 0xb7, 0xc3,
+       0x4e, 0x72, 0x3e, 0xdd, 0xc6, 0x0e, 0xc0, 0x5e, 0x6f, 0x5a, 0xe1, 0xed,
+       0xdc, 0x10, 0xb2, 0xaf, 0xde, 0x5e, 0xa3, 0x31, 0x4b, 0x08, 0x9f, 0xde,
+       0x51, 0x1f, 0xc9, 0x2c, 0x21, 0x7c, 0x7c, 0x67, 0x43, 0xbc, 0xa1, 0x5e,
+       0xd1, 0xf0, 0xde, 0x6b, 0x83, 0x78, 0xff, 0x5a, 0xbc, 0xfe, 0xdf, 0xa0,
+       0xcb, 0x89, 0x7b, 0x3f, 0x7d, 0xfc, 0xb7, 0xfc, 0xf9, 0x93, 0xf7, 0x7e,
+       0x91, 0x0d, 0x7a, 0x73, 0x38, 0x76, 0x6c, 0xc1, 0xb8, 0xab, 0xa3, 0x7a,
+       0xe0, 0x48, 0x40, 0x7d, 0xad, 0x95, 0xf4, 0x87, 0xa1, 0x51, 0xc2, 0x0e,
+       0xc2, 0x1f, 0xe8, 0x32, 0x9f, 0x89, 0xf5, 0xf9, 0xe4, 0xbd, 0x7f, 0xa5,
+       0xf5, 0xdd, 0xd9, 0x10, 0xe1, 0x32, 0xf3, 0x76, 0xf3, 0x1b, 0x22, 0x08,
+       0x5f, 0x1f, 0x82, 0x4e, 0x1c, 0xaf, 0x1f, 0x4b, 0x3a, 0x55, 0xae, 0x3b,
+       0xf9, 0xdc, 0x4b, 0x58, 0xe7, 0xab, 0x6d, 0x24, 0xe7, 0xe6, 0xaf, 0x95,
+       0xeb, 0x72, 0x23, 0xc7, 0x67, 0x88, 0xbe, 0xf6, 0x49, 0x0a, 0x23, 0xbd,
+       0x4c, 0xf3, 0x32, 0x86, 0x38, 0xcc, 0x27, 0xdf, 0xb3, 0x05, 0xf9, 0x9e,
+       0xcf, 0x3e, 0xd1, 0xec, 0x01, 0x0d, 0xba, 0x0f, 0x37, 0x92, 0x2a, 0xf8,
+       0x73, 0x7d, 0xe3, 0x1b, 0x94, 0x7f, 0xa5, 0x35, 0x1c, 0x23, 0x7d, 0x58,
+       0x47, 0x5e, 0x16, 0xfc, 0x04, 0x7e, 0xab, 0x21, 0x1f, 0x4b, 0x6b, 0x90,
+       0x79, 0x5a, 0x1d, 0x43, 0x0c, 0x79, 0x54, 0xd1, 0xa3, 0xbd, 0x36, 0xc8,
+       0x07, 0xf0, 0x34, 0xe8, 0x36, 0x3f, 0xf7, 0x30, 0xc3, 0xba, 0x66, 0xcd,
+       0x9a, 0x13, 0x5b, 0x40, 0xb5, 0x7c, 0x5e, 0xbd, 0x51, 0x23, 0x7d, 0xa3,
+       0x47, 0x5f, 0xc8, 0x36, 0x13, 0x1d, 0x2b, 0xb3, 0x2c, 0x54, 0xfe, 0x02,
+       0x6b, 0x9c, 0xec, 0xc5, 0x66, 0xda, 0x9f, 0x14, 0xbf, 0x72, 0x79, 0xe1,
+       0x0d, 0x60, 0x5d, 0x34, 0x17, 0xd9, 0x16, 0x86, 0xc8, 0xe1, 0xf9, 0xf2,
+       0x79, 0x55, 0xae, 0x89, 0x4a, 0xf5, 0xbc, 0x32, 0xcb, 0x46, 0xfd, 0xfc,
+       0x02, 0x8b, 0x91, 0xf7, 0xfb, 0x40, 0x6e, 0x86, 0x6d, 0x01, 0xc9, 0x39,
+       0x97, 0x0d, 0x72, 0x40, 0xb5, 0x9f, 0x9f, 0x5b, 0xbc, 0x3e, 0x63, 0x34,
+       0xfa, 0x99, 0x30, 0x80, 0x85, 0xac, 0xc7, 0xa2, 0x6c, 0x0b, 0x7d, 0x5f,
+       0x89, 0x44, 0x2f, 0xec, 0x5f, 0x76, 0xe1, 0xff, 0xaf, 0xed, 0x67, 0x1f,
+       0x50, 0x7a, 0xc9, 0x69, 0xfc, 0xf3, 0x6a, 0x82, 0x9f, 0xec, 0xad, 0x25,
+       0xcf, 0x3f, 0xfb, 0x3c, 0xe2, 0x63, 0x4b, 0x3e, 0x8a, 0x20, 0x3a, 0x2d,
+       0x19, 0x29, 0xfd, 0x11, 0xf9, 0x81, 0xb1, 0xd3, 0x49, 0x9f, 0xf1, 0x3a,
+       0x34, 0x3e, 0xcf, 0x65, 0x92, 0xfe, 0x65, 0xcf, 0xfe, 0x3e, 0xb6, 0x83,
+       0xbf, 0x5f, 0xbe, 0x57, 0xf8, 0x2f, 0x79, 0xd9, 0x89, 0x72, 0xd9, 0xea,
+       0x1a, 0xf2, 0x6b, 0x2d, 0xf3, 0xf0, 0xf5, 0x91, 0x00, 0xb9, 0x6a, 0x8c,
+       0x23, 0x1f, 0x7d, 0xfe, 0xa3, 0xd8, 0x0e, 0xb2, 0x2b, 0xfc, 0xa9, 0xc8,
+       0x2f, 0xe4, 0xdb, 0x42, 0x2a, 0x4b, 0x46, 0xbc, 0xe8, 0xe4, 0x24, 0xf8,
+       0xc5, 0x97, 0xb3, 0xae, 0xf5, 0xc8, 0xeb, 0x0a, 0xff, 0x6e, 0xb9, 0xf6,
+       0x55, 0xac, 0xf0, 0xef, 0x8b, 0x38, 0xb9, 0x8a, 0x5f, 0x96, 0xbf, 0xfa,
+       0xe7, 0x24, 0x82, 0x63, 0xdf, 0xc5, 0x24, 0xc8, 0xb5, 0xe5, 0xaf, 0xae,
+       0x4b, 0xd2, 0xfb, 0x98, 0xf7, 0xf2, 0xb0, 0xf8, 0xb5, 0x8a, 0x9b, 0x2b,
+       0x3f, 0xd8, 0x72, 0xb6, 0xe9, 0x4b, 0xc4, 0xdd, 0xc2, 0xdb, 0x55, 0x65,
+       0xc7, 0x0c, 0x00, 0xff, 0xb0, 0xab, 0xd8, 0x55, 0xe4, 0xa7, 0xb0, 0x30,
+       0xca, 0x63, 0x58, 0x69, 0x17, 0x78, 0xe8, 0x0e, 0x64, 0xc7, 0xb1, 0x3e,
+       0xc6, 0xeb, 0x19, 0x77, 0x2b, 0x17, 0xec, 0xdc, 0x0e, 0xed, 0xb6, 0xb8,
+       0xe2, 0x3c, 0x1c, 0xce, 0x0b, 0xfd, 0xe4, 0xf1, 0xed, 0xca, 0x16, 0xfb,
+       0xf9, 0x39, 0x19, 0x47, 0xbd, 0xb0, 0xdb, 0x4c, 0x7a, 0xe1, 0x85, 0xdd,
+       0x31, 0xc4, 0xff, 0xcb, 0x76, 0xff, 0xf0, 0xf5, 0x6b, 0x78, 0x7d, 0xd9,
+       0x76, 0x0d, 0xc3, 0xb2, 0x3a, 0xd6, 0x4e, 0x78, 0x5a, 0xb6, 0xd7, 0xcc,
+       0xec, 0xa1, 0xf6, 0x0d, 0xfc, 0x36, 0x89, 0xfd, 0xc3, 0xb9, 0xf4, 0xd9,
+       0x98, 0x7a, 0xf0, 0xd3, 0xe2, 0x36, 0xcd, 0xbb, 0x23, 0x1f, 0x71, 0x79,
+       0x57, 0xdc, 0xc0, 0x10, 0x78, 0xd6, 0x49, 0x7e, 0x5a, 0x1a, 0xd1, 0x36,
+       0x96, 0xe8, 0x20, 0xe1, 0xff, 0xae, 0xd4, 0x8f, 0x54, 0xbb, 0xc5, 0x07,
+       0x7f, 0x68, 0x03, 0xbd, 0x78, 0xbb, 0xf3, 0xa4, 0xb7, 0xfc, 0x34, 0x1a,
+       0xba, 0x36, 0xff, 0xeb, 0x7a, 0x07, 0x70, 0x9e, 0xd9, 0x36, 0x8a, 0xe2,
+       0xba, 0x8b, 0xdb, 0xf6, 0x2c, 0xa3, 0x7d, 0x7f, 0x77, 0xb4, 0x13, 0x53,
+       0xfc, 0xc2, 0x6a, 0xf4, 0x47, 0x6d, 0x96, 0xe3, 0x6d, 0xce, 0x16, 0x7a,
+       0xc6, 0x19, 0xe9, 0xff, 0x3d, 0xf3, 0xbc, 0x99, 0xe4, 0x0f, 0xe0, 0xc4,
+       0x3a, 0xfc, 0x42, 0x13, 0x7e, 0x5e, 0xf5, 0xdd, 0x16, 0xf9, 0xdd, 0x16,
+       0x89, 0xb7, 0xeb, 0x10, 0x54, 0x1c, 0xd3, 0xdb, 0x7e, 0x71, 0x5b, 0x67,
+       0x6c, 0x16, 0x6f, 0xff, 0xd9, 0x81, 0xf7, 0xa8, 0x6c, 0x95, 0xed, 0x17,
+       0x3b, 0xda, 0x0b, 0xb1, 0x5f, 0x7e, 0xb6, 0x37, 0x7a, 0x72, 0x80, 0xca,
+       0x1f, 0x4d, 0x7a, 0x85, 0x8f, 0x77, 0xae, 0x6d, 0xc2, 0x00, 0x2d, 0x64,
+       0x5d, 0x3d, 0x9f, 0x6d, 0xa5, 0xfe, 0xce, 0x6d, 0x33, 0x4f, 0x06, 0xbe,
+       0x58, 0x40, 0xe5, 0x19, 0xb5, 0xd1, 0x7c, 0xce, 0xec, 0x4e, 0xd5, 0xc8,
+       0xae, 0x05, 0xbe, 0x39, 0x7e, 0xce, 0xec, 0x7d, 0x31, 0xd6, 0x44, 0xeb,
+       0xd6, 0x6f, 0xa0, 0xa3, 0xc9, 0x2e, 0xfc, 0xa9, 0x6e, 0x8b, 0x4b, 0xea,
+       0x97, 0x76, 0x27, 0xf4, 0x8c, 0xb9, 0x5c, 0xab, 0x8b, 0xe3, 0xf2, 0xae,
+       0x6e, 0xaf, 0xc8, 0x07, 0x08, 0x7f, 0xae, 0xda, 0xd3, 0x7a, 0x4b, 0x01,
+       0xbf, 0x77, 0xd9, 0x04, 0xff, 0xcb, 0xf8, 0xbd, 0x8c, 0x2f, 0x21, 0x4f,
+       0x84, 0xe2, 0xf1, 0x31, 0xb6, 0x00, 0xf6, 0xd7, 0x79, 0x23, 0x5d, 0xb3,
+       0x6e, 0x87, 0x3c, 0x7b, 0xcb, 0x2a, 0xe8, 0x31, 0xc4, 0xb5, 0x05, 0x76,
+       0xd5, 0xbc, 0x77, 0x13, 0xc9, 0x5f, 0xb1, 0xd2, 0xea, 0x1a, 0x84, 0xfa,
+       0x9f, 0xde, 0xb6, 0x92, 0xff, 0x7c, 0xde, 0x28, 0xb9, 0xce, 0x93, 0x3b,
+       0xc6, 0xc0, 0x3f, 0xd9, 0xe9, 0x16, 0xfb, 0x7a, 0xed, 0x46, 0xbe, 0x42,
+       0xf8, 0x94, 0x07, 0x73, 0xfa, 0xfb, 0xf9, 0xfc, 0x6a, 0x03, 0x26, 0xca,
+       0xa7, 0x7c, 0x3f, 0x3b, 0x83, 0xe6, 0xf7, 0x58, 0x8d, 0xc9, 0x6b, 0xa3,
+       0x38, 0x47, 0x30, 0x07, 0x7e, 0xca, 0x13, 0x36, 0xe6, 0x37, 0x43, 0x4f,
+       0x7e, 0x21, 0x92, 0xf4, 0xbb, 0xda, 0x0c, 0xe1, 0x77, 0x7f, 0x0c, 0xfc,
+       0xce, 0xcb, 0xda, 0x84, 0x60, 0x4e, 0x22, 0xf4, 0x1d, 0x49, 0xc7, 0xda,
+       0x5b, 0xf9, 0xfb, 0x10, 0x7a, 0xd6, 0x3e, 0x15, 0xcc, 0x81, 0xde, 0x72,
+       0xd6, 0x26, 0xfc, 0x78, 0x78, 0xef, 0x44, 0x59, 0x2c, 0xda, 0x35, 0x49,
+       0xbe, 0x41, 0x3f, 0xe8, 0xb7, 0xd3, 0xed, 0x3c, 0x4f, 0xfa, 0xe5, 0xbe,
+       0x18, 0x06, 0x3d, 0xdf, 0xf4, 0x52, 0x8c, 0xf0, 0x27, 0xfc, 0x24, 0x92,
+       0xe2, 0x0e, 0xaa, 0xdf, 0x53, 0xd9, 0x42, 0xbf, 0x6f, 0x92, 0x71, 0x2e,
+       0xff, 0x0e, 0x01, 0x1f, 0xe0, 0x82, 0xde, 0xbc, 0xd8, 0xd6, 0x9c, 0x03,
+       0xbd, 0x52, 0x8d, 0xbb, 0x38, 0xb6, 0x99, 0xc6, 0x3b, 0x2b, 0xc7, 0x5b,
+       0x1c, 0xd5, 0x2c, 0xe2, 0x07, 0x32, 0x2f, 0x0c, 0xed, 0x69, 0x7c, 0x2b,
+       0xf3, 0xc2, 0x1e, 0xef, 0x7a, 0x3a, 0x82, 0xf4, 0xd3, 0x2f, 0x52, 0xda,
+       0xf7, 0x63, 0xfc, 0x2f, 0x9e, 0x1e, 0x4e, 0x71, 0xf0, 0x4e, 0x77, 0x60,
+       0xe1, 0x01, 0x7a, 0xcf, 0xf5, 0x36, 0x4e, 0x87, 0x25, 0xcf, 0x44, 0x04,
+       0x01, 0xef, 0xe7, 0x4f, 0xc7, 0x50, 0x9c, 0xf3, 0x73, 0xab, 0xd0, 0x83,
+       0x3e, 0x8f, 0x49, 0x22, 0x3d, 0xe8, 0x58, 0xcc, 0x23, 0xf3, 0xd0, 0x5f,
+       0xf7, 0xf6, 0x08, 0x0d, 0xfe, 0x94, 0xcf, 0x35, 0x66, 0x4b, 0xc6, 0xfb,
+       0x1d, 0x03, 0x29, 0x5e, 0xb5, 0xa4, 0xb1, 0x81, 0xe2, 0x04, 0x4b, 0xf8,
+       0x72, 0x47, 0x3c, 0x9a, 0x97, 0x93, 0x11, 0x57, 0xfe, 0x7c, 0xc7, 0x70,
+       0xf2, 0xb3, 0x7c, 0xfe, 0xa6, 0x99, 0xe2, 0x8b, 0xfc, 0xf9, 0x46, 0x3c,
+       0xd7, 0x59, 0xf3, 0xbc, 0xef, 0x60, 0xdd, 0xed, 0x8a, 0x26, 0x3f, 0xdb,
+       0x17, 0xcf, 0xfc, 0x6d, 0x78, 0x68, 0xfc, 0x41, 0x95, 0x4b, 0xb6, 0x1b,
+       0xfd, 0x49, 0x8a, 0xfe, 0xea, 0xbd, 0x35, 0x47, 0xd8, 0x0d, 0xd6, 0x1c,
+       0x81, 0xc7, 0xc8, 0x1c, 0xb1, 0xcf, 0xd4, 0x45, 0xb7, 0x3d, 0x92, 0x41,
+       0xf3, 0x14, 0xeb, 0x95, 0xd3, 0x81, 0xec, 0x2d, 0xbe, 0x3e, 0x92, 0xe0,
+       0x9f, 0x3e, 0xd1, 0xf6, 0x72, 0x92, 0xe6, 0x00, 0x9e, 0x83, 0x39, 0x3f,
+       0x02, 0xde, 0x77, 0x09, 0xbb, 0xe6, 0x8b, 0xdd, 0x56, 0x8a, 0x8b, 0x2c,
+       0x79, 0x29, 0xc6, 0x4b, 0xfe, 0x9b, 0x0d, 0x57, 0x99, 0xb0, 0x5f, 0x2c,
+       0x31, 0x0b, 0xfd, 0x77, 0x09, 0x67, 0x37, 0x51, 0x0a, 0xff, 0xd0, 0x92,
+       0xd8, 0x1c, 0xf2, 0x0f, 0x71, 0x7c, 0x93, 0xfd, 0xd8, 0xb5, 0xc3, 0x2c,
+       0xc7, 0x11, 0xe3, 0x7e, 0xbe, 0x33, 0x4d, 0xf8, 0xdf, 0x83, 0xb2, 0xbe,
+       0xbf, 0x20, 0x00, 0x3e, 0x9f, 0x92, 0xc0, 0xee, 0xbc, 0x95, 0xf4, 0x9b,
+       0x6d, 0x85, 0xc0, 0xeb, 0xc5, 0xed, 0xd1, 0x26, 0xf0, 0x05, 0x1f, 0xc7,
+       0x8b, 0xb8, 0xfd, 0x92, 0xef, 0x7c, 0x57, 0xe0, 0x33, 0x6e, 0x21, 0xe9,
+       0xe3, 0x0c, 0x79, 0xd0, 0x63, 0x11, 0x2f, 0x17, 0xf2, 0xb2, 0x6e, 0xc3,
+       0x35, 0x71, 0xc8, 0x87, 0x61, 0xef, 0x9a, 0x19, 0x44, 0xdf, 0x45, 0x8b,
+       0x67, 0x10, 0xe4, 0x61, 0x38, 0xbe, 0x66, 0xe7, 0x48, 0x79, 0xb9, 0xff,
+       0x71, 0x1b, 0xe2, 0x67, 0xb5, 0x7c, 0xbd, 0x20, 0x3f, 0x68, 0xa9, 0x8c,
+       0x9b, 0x2e, 0x7d, 0x46, 0x23, 0x7d, 0x6e, 0xe9, 0xfa, 0x6b, 0xb6, 0x90,
+       0x1c, 0x7c, 0xc7, 0xca, 0xb2, 0x39, 0x1c, 0x67, 0xdb, 0x7e, 0x18, 0x1b,
+       0x4a, 0x8f, 0xd2, 0x1c, 0xa1, 0x57, 0xf4, 0x7e, 0xef, 0xa1, 0xf6, 0x4b,
+       0x79, 0x7b, 0xf1, 0xfd, 0x5b, 0xb1, 0x04, 0xcf, 0x4e, 0xab, 0x07, 0xf0,
+       0x84, 0xd3, 0xf1, 0x8a, 0xbf, 0x7f, 0xc6, 0x7c, 0x45, 0xdf, 0xf7, 0xf0,
+       0x47, 0x1b, 0xdf, 0xd7, 0x0b, 0x2f, 0x9f, 0xf7, 0x45, 0xd6, 0xfe, 0xbf,
+       0x3e, 0x82, 0x1c, 0xd9, 0x1d, 0xe9, 0xf1, 0xd3, 0xd3, 0x36, 0x8a, 0x3b,
+       0x9f, 0xb1, 0xb6, 0x2d, 0xc4, 0xbc, 0xcf, 0x3c, 0x17, 0x49, 0xf2, 0xe5,
+       0x4c, 0xbc, 0x58, 0xef, 0x9f, 0x71, 0x79, 0xe8, 0xb7, 0x01, 0x8e, 0x6f,
+       0x3d, 0x44, 0xfe, 0x8d, 0xdf, 0x4c, 0x67, 0x10, 0xdd, 0x8b, 0x02, 0xc6,
+       0x7e, 0xd5, 0xb8, 0x37, 0xe4, 0x88, 0x73, 0x1b, 0x75, 0x89, 0x9e, 0x38,
+       0xc4, 0x33, 0xea, 0x38, 0x1d, 0xd0, 0x1f, 0xa7, 0xcb, 0x2d, 0xf4, 0xfd,
+       0xbb, 0x56, 0xfa, 0x3e, 0x7c, 0x1e, 0x39, 0x39, 0x42, 0x6e, 0xf7, 0xac,
+       0xcf, 0xe7, 0xa2, 0x89, 0x5f, 0xce, 0x0c, 0x16, 0xf4, 0x38, 0xf3, 0xfc,
+       0x30, 0xda, 0x57, 0x3a, 0xe3, 0x05, 0x9f, 0x73, 0x78, 0xd3, 0x61, 0xa7,
+       0x9c, 0x89, 0x17, 0x25, 0x83, 0x32, 0xc2, 0xf9, 0x60, 0x89, 0xb4, 0x43,
+       0xcf, 0x4c, 0x68, 0x23, 0xbb, 0xfb, 0x8c, 0xb6, 0x87, 0xca, 0x4e, 0xab,
+       0xf8, 0x6e, 0x49, 0x83, 0x8c, 0xdb, 0x72, 0xbe, 0x4b, 0x06, 0xdf, 0x80,
+       0x27, 0x11, 0xb7, 0xb2, 0x6f, 0x6a, 0x87, 0x1e, 0x01, 0xff, 0xf4, 0xd8,
+       0x62, 0x2a, 0x83, 0x11, 0x09, 0x97, 0xfb, 0x99, 0xc1, 0x9f, 0xd8, 0x87,
+       0x9e, 0x94, 0xeb, 0x0b, 0x6a, 0x0d, 0xe4, 0x3a, 0xc5, 0x37, 0x48, 0x3f,
+       0x69, 0xb3, 0x41, 0x1e, 0xeb, 0x52, 0x8f, 0xab, 0xdd, 0x7d, 0x79, 0xbc,
+       0x8c, 0xe2, 0xa0, 0xbb, 0x35, 0x8a, 0xfb, 0xdc, 0xab, 0xfa, 0xe1, 0x50,
+       0x0f, 0x50, 0xfe, 0x71, 0xce, 0x8f, 0x4b, 0xfd, 0x9a, 0x17, 0xf9, 0x46,
+       0x4b, 0xd7, 0xae, 0x58, 0x0c, 0x7e, 0x5f, 0x5a, 0xbf, 0xf9, 0x76, 0xf0,
+       0xbb, 0x9a, 0xc7, 0x52, 0x0b, 0x9b, 0x0c, 0xfb, 0xaa, 0x53, 0x33, 0x13,
+       0x3c, 0x9d, 0x91, 0x7c, 0xdd, 0x00, 0x0f, 0xa1, 0xe3, 0x65, 0xf4, 0xe2,
+       0xf7, 0xfe, 0x1c, 0xad, 0x27, 0x0f, 0xda, 0x99, 0x44, 0x7a, 0x26, 0x29,
+       0xd7, 0x0f, 0xe6, 0x88, 0xfd, 0x0a, 0xf5, 0x66, 0xde, 0x5f, 0xed, 0x5a,
+       0x6d, 0x13, 0x8d, 0xe3, 0x56, 0xf6, 0xa4, 0x98, 0x9f, 0xc2, 0x13, 0x47,
+       0x8b, 0x0d, 0x7e, 0x32, 0x6e, 0xe7, 0x8b, 0xf7, 0xfd, 0xcc, 0x5f, 0xc1,
+       0x19, 0x3e, 0x7f, 0x05, 0x4f, 0x6b, 0x8e, 0xd0, 0x1b, 0x3a, 0xdd, 0xae,
+       0x87, 0xc6, 0x83, 0xde, 0xbf, 0x32, 0x93, 0xff, 0xf4, 0xe2, 0x57, 0xa3,
+       0xe2, 0x12, 0xbe, 0x46, 0x2f, 0x83, 0xc5, 0xd6, 0xe3, 0x2f, 0xe6, 0xf0,
+       0x3f, 0xcf, 0xf7, 0x6a, 0xc0, 0xbf, 0x42, 0xca, 0xb7, 0xa5, 0xf0, 0x47,
+       0x73, 0x38, 0x73, 0xb6, 0x19, 0xe3, 0x1f, 0xb9, 0xdb, 0x8d, 0xf5, 0x11,
+       0xbb, 0x8d, 0xf5, 0xfc, 0xbd, 0xc6, 0x7a, 0xe1, 0x41, 0x63, 0xdd, 0x73,
+       0xd4, 0x58, 0x7f, 0x04, 0xe3, 0x0e, 0xec, 0xc5, 0x13, 0xec, 0x5c, 0xe4,
+       0xb5, 0xc1, 0xce, 0x45, 0x09, 0x3b, 0xd7, 0x95, 0x23, 0xec, 0x5c, 0xd4,
+       0x61, 0xe7, 0xa2, 0x84, 0x9d, 0x8b, 0xe7, 0xb0, 0x73, 0x51, 0x87, 0x9d,
+       0x8b, 0x3a, 0xec, 0x5c, 0xd4, 0x61, 0xe7, 0xa2, 0x84, 0x9d, 0x8b, 0xe7,
+       0x7f, 0x90, 0x78, 0xaa, 0x95, 0x7e, 0x47, 0xd0, 0x81, 0xf2, 0xab, 0x5e,
+       0x8e, 0x54, 0x71, 0x70, 0x5a, 0x2f, 0x17, 0xe6, 0x24, 0x91, 0xfc, 0x54,
+       0xf1, 0xcc, 0x0b, 0x8b, 0xf3, 0xa9, 0xde, 0xe3, 0xcf, 0x99, 0x66, 0x27,
+       0x7f, 0x8e, 0xca, 0xd3, 0xb9, 0x3d, 0x4e, 0x7f, 0x33, 0x87, 0xe2, 0x86,
+       0xed, 0xeb, 0x53, 0x40, 0x37, 0x4b, 0x07, 0xf9, 0x71, 0x97, 0xff, 0x4c,
+       0xf8, 0x71, 0x6b, 0x8b, 0x23, 0x1d, 0xf0, 0x2f, 0x74, 0xac, 0xfb, 0x6c,
+       0x3d, 0xd4, 0xa7, 0xc2, 0x38, 0xfd, 0x1d, 0xb4, 0xbf, 0x60, 0xed, 0xda,
+       0x29, 0xf2, 0x95, 0x82, 0x24, 0x37, 0x3a, 0xd6, 0xb8, 0xde, 0xbd, 0x5e,
+       0xd0, 0x8f, 0xfc, 0x1c, 0x2a, 0xef, 0xa6, 0x12, 0xfb, 0x5d, 0x42, 0xff,
+       0x74, 0x0c, 0x8f, 0xa3, 0xb0, 0x4d, 0xc6, 0xb8, 0x49, 0x78, 0x1c, 0x25,
+       0x3c, 0x7e, 0x12, 0xce, 0x07, 0x2a, 0x6e, 0xf2, 0xa4, 0xb5, 0x2b, 0x05,
+       0xf2, 0xfe, 0xe4, 0xd3, 0xf6, 0x4d, 0x80, 0xff, 0xa4, 0xf4, 0x8f, 0xb1,
+       0xd9, 0x4e, 0xd2, 0xbf, 0x94, 0x5e, 0xdd, 0xa3, 0x7f, 0x3d, 0xa8, 0x3d,
+       0x85, 0x7d, 0xfb, 0x42, 0x8e, 0xc8, 0xfb, 0xeb, 0x3e, 0xc6, 0xf5, 0xed,
+       0x3e, 0xf6, 0x5b, 0x55, 0x56, 0x5d, 0x2a, 0x26, 0xbd, 0xb1, 0xa7, 0xbe,
+       0x49, 0x33, 0x51, 0xde, 0x48, 0x72, 0x2c, 0xed, 0x43, 0xab, 0x24, 0x4c,
+       0xe9, 0x5a, 0x57, 0xe7, 0x06, 0xc8, 0xbb, 0x18, 0x13, 0xed, 0xe3, 0x17,
+       0x1d, 0x26, 0xb2, 0x0b, 0x2e, 0xbe, 0x6f, 0x26, 0x3d, 0x62, 0x18, 0xf4,
+       0xf3, 0x90, 0xf9, 0x0c, 0x0f, 0x44, 0x19, 0xf8, 0x2b, 0x6f, 0x57, 0x42,
+       0x58, 0xfc, 0x6f, 0xb0, 0xa1, 0xfd, 0xc8, 0x03, 0x19, 0x61, 0xf1, 0xbf,
+       0x11, 0xc6, 0xb8, 0xd4, 0x6d, 0x6b, 0x0e, 0xc1, 0xbe, 0x9e, 0xbe, 0x69,
+       0x94, 0xa1, 0x5d, 0xb5, 0xef, 0x9a, 0x30, 0x3c, 0x4a, 0xb8, 0xa5, 0x5e,
+       0xda, 0xb4, 0x7a, 0x6b, 0x3a, 0xe4, 0xcf, 0xaa, 0x98, 0x6e, 0x82, 0x7f,
+       0xd5, 0xbe, 0x48, 0xca, 0xab, 0xad, 0xe6, 0xf0, 0x7a, 0x11, 0x97, 0x43,
+       0x85, 0xa3, 0xa0, 0xc6, 0xee, 0x9d, 0x0a, 0xfc, 0xd5, 0xb4, 0x59, 0xe3,
+       0xb1, 0xcf, 0x57, 0xc9, 0xfd, 0x87, 0x35, 0x18, 0xf7, 0xe3, 0x1a, 0x0b,
+       0xf3, 0x3b, 0x13, 0x7a, 0xf9, 0xae, 0xc6, 0xc9, 0xbc, 0xf1, 0xfc, 0xfb,
+       0x73, 0x45, 0xcd, 0x3b, 0x4d, 0x9c, 0x6e, 0xe7, 0x4c, 0xdb, 0x1e, 0x19,
+       0xef, 0x42, 0x5c, 0xa9, 0x35, 0xdd, 0xc9, 0xf9, 0xea, 0x2e, 0xad, 0x2d,
+       0xe9, 0x6a, 0xde, 0xdf, 0xdf, 0x2c, 0x7a, 0xda, 0x30, 0x4e, 0x8f, 0x74,
+       0x6b, 0xf0, 0x07, 0x15, 0x90, 0x97, 0x7b, 0x32, 0xd9, 0x1a, 0xde, 0xee,
+       0xe4, 0xa6, 0x17, 0x63, 0x49, 0xef, 0x96, 0x7c, 0x96, 0x6e, 0x75, 0x46,
+       0x81, 0xde, 0xad, 0xcd, 0x66, 0xb2, 0x0b, 0xe0, 0x97, 0x32, 0x27, 0xf4,
+       0xf2, 0x43, 0x6b, 0x73, 0x62, 0x54, 0x96, 0xa3, 0x77, 0x9e, 0xbd, 0xf4,
+       0xff, 0x8a, 0xe6, 0xc7, 0xe9, 0xe2, 0xc1, 0x39, 0xc5, 0x6e, 0xc7, 0xe1,
+       0x21, 0xab, 0xa0, 0xc7, 0xb5, 0x89, 0xf9, 0xd6, 0x4c, 0xd0, 0xfc, 0xa4,
+       0x27, 0xcb, 0xf9, 0xac, 0x94, 0xfb, 0x0a, 0xcb, 0x12, 0xfd, 0xdc, 0x25,
+       0xeb, 0xa7, 0xa4, 0xbd, 0xa0, 0xe6, 0x77, 0x76, 0xf8, 0xa1, 0x42, 0x17,
+       0xe2, 0x98, 0x8d, 0x07, 0xd2, 0xcd, 0x90, 0xe3, 0xa6, 0xdd, 0x3b, 0x71,
+       0x7e, 0xe0, 0xde, 0x28, 0xbd, 0x64, 0xd8, 0x40, 0xe4, 0x4b, 0x66, 0xff,
+       0x76, 0x3c, 0x1f, 0x77, 0xc9, 0x07, 0x22, 0x5f, 0xf7, 0x8f, 0x2d, 0x13,
+       0x63, 0xaf, 0x86, 0xfe, 0xf9, 0x9c, 0xd5, 0x33, 0x85, 0xd7, 0x37, 0x34,
+       0xff, 0xd8, 0x06, 0xbb, 0x78, 0x89, 0x25, 0x60, 0x83, 0xdd, 0x59, 0xf3,
+       0x74, 0xab, 0xcd, 0xcb, 0xcb, 0x1b, 0x76, 0xb5, 0xd2, 0xf3, 0x85, 0xbb,
+       0x2a, 0xc9, 0xde, 0x5e, 0xc4, 0xea, 0xc9, 0x8e, 0x3c, 0xad, 0xf2, 0x6f,
+       0x25, 0x3e, 0x6a, 0x4a, 0xb5, 0x6d, 0x4e, 0x0e, 0xf7, 0x93, 0xc3, 0x84,
+       0xdc, 0xa8, 0x89, 0x12, 0x79, 0x1b, 0xe5, 0xe6, 0xf1, 0xaf, 0x21, 0x2f,
+       0xfd, 0xe2, 0x2e, 0xad, 0x08, 0xf3, 0xbd, 0xcd, 0xb7, 0xc7, 0x56, 0xc9,
+       0x9f, 0xdf, 0x3a, 0x4c, 0x9e, 0x3b, 0x09, 0x5b, 0x1f, 0xdd, 0x6f, 0x4f,
+       0x2f, 0x1f, 0x08, 0x7f, 0x52, 0x9b, 0x88, 0x7b, 0xf6, 0xb7, 0x1e, 0x66,
+       0x04, 0x73, 0x69, 0x3d, 0x4c, 0xbf, 0xe4, 0xa2, 0xf2, 0xb6, 0x4b, 0x23,
+       0xc8, 0x8e, 0xfd, 0x80, 0xf9, 0x0a, 0x48, 0x4e, 0xe4, 0x87, 0xd9, 0xb3,
+       0x6f, 0x8b, 0x3c, 0xe4, 0xee, 0x83, 0x62, 0x1d, 0xd4, 0xd8, 0x82, 0x03,
+       0xa6, 0x63, 0x9d, 0xfc, 0xdc, 0x4a, 0xeb, 0xa4, 0x8e, 0xcb, 0xaf, 0x92,
+       0x62, 0xd8, 0xc9, 0x8c, 0x8d, 0xe3, 0xa5, 0x6f, 0xbc, 0xd9, 0xc0, 0xaf,
+       0xcb, 0xcb, 0xa2, 0x0d, 0xfc, 0x3c, 0x9b, 0x25, 0x18, 0xe2, 0xc8, 0x33,
+       0x71, 0x68, 0x33, 0xa4, 0x7e, 0xdb, 0x94, 0x4c, 0x43, 0xfb, 0x59, 0xb7,
+       0xe5, 0x85, 0xf1, 0x7f, 0x71, 0xef, 0x7b, 0x92, 0x23, 0xe3, 0x0c, 0x79,
+       0x26, 0x75, 0xab, 0xfd, 0x2e, 0x8d, 0xf2, 0x59, 0x4a, 0x8d, 0xcf, 0x79,
+       0xb9, 0x9a, 0xf8, 0xec, 0x26, 0xc3, 0xf7, 0x75, 0xec, 0xd6, 0xde, 0x76,
+       0xb0, 0x83, 0xb7, 0xff, 0x9a, 0xf0, 0xcc, 0x58, 0xbb, 0x0d, 0xf6, 0x56,
+       0x8d, 0x49, 0xe4, 0xd5, 0xcc, 0xd6, 0x3b, 0xe5, 0xf3, 0x0e, 0x7a, 0xce,
+       0x27, 0x62, 0x58, 0x87, 0x43, 0x33, 0x3d, 0xbf, 0x15, 0xfb, 0xa2, 0x95,
+       0xfc, 0xf2, 0xca, 0x2f, 0x3d, 0x1b, 0xff, 0xce, 0xec, 0x6b, 0x5f, 0xe4,
+       0x84, 0x96, 0xe3, 0x22, 0x3f, 0x14, 0xfe, 0x05, 0x43, 0x7e, 0x21, 0x07,
+       0x80, 0xec, 0x4f, 0x26, 0xe8, 0x50, 0x27, 0xfd, 0x3d, 0x75, 0xb9, 0xc2,
+       0xdf, 0x53, 0xe7, 0x6f, 0xb7, 0x21, 0xff, 0x96, 0xe3, 0xdf, 0x92, 0xca,
+       0x51, 0xb2, 0xac, 0x59, 0x23, 0x7f, 0x1e, 0x6f, 0x6f, 0x4f, 0x4d, 0x10,
+       0xf5, 0xd5, 0x78, 0xbe, 0xd7, 0x78, 0xde, 0x00, 0xfd, 0x5d, 0xc2, 0xfb,
+       0x63, 0xe6, 0x4a, 0xac, 0x97, 0xf0, 0xf7, 0xcb, 0xf8, 0xbc, 0xa1, 0x67,
+       0x2c, 0x83, 0x9f, 0x06, 0x7e, 0x26, 0xd5, 0xbf, 0xec, 0x57, 0xf1, 0xe7,
+       0xa2, 0xad, 0x46, 0xbf, 0xd1, 0x32, 0xf8, 0x73, 0x42, 0xe8, 0xf8, 0xc9,
+       0x30, 0x17, 0xf1, 0xf3, 0x92, 0x5d, 0x7b, 0x5e, 0x1f, 0xcc, 0xf1, 0x32,
+       0xdd, 0x17, 0x5f, 0x84, 0xf5, 0x53, 0xdb, 0x36, 0xcd, 0x5a, 0x99, 0x7f,
+       0x39, 0x9f, 0x29, 0xf9, 0x7e, 0xb1, 0xc6, 0x44, 0x71, 0xee, 0xee, 0xb7,
+       0x8f, 0x10, 0x9f, 0x75, 0xd7, 0x58, 0x88, 0x9f, 0xbf, 0x09, 0x1f, 0xcb,
+       0xbc, 0xc2, 0x9f, 0x19, 0xce, 0x7f, 0x0b, 0xf9, 0x7c, 0x10, 0x97, 0x5d,
+       0xb8, 0x57, 0xf3, 0x04, 0x34, 0xd1, 0x0e, 0x78, 0x19, 0x0c, 0xbe, 0x0c,
+       0xc3, 0x4b, 0x6a, 0x1f, 0xf8, 0x52, 0x78, 0xea, 0xc1, 0x5b, 0xd8, 0xfb,
+       0x45, 0xf8, 0xc7, 0x68, 0xe4, 0x0d, 0x68, 0x81, 0xa0, 0xbb, 0x2f, 0xbc,
+       0x48, 0x3c, 0xaa, 0xfe, 0xc3, 0xf0, 0xc4, 0x4a, 0x8c, 0x78, 0x58, 0xa8,
+       0xbb, 0xde, 0x85, 0xbc, 0x59, 0x78, 0xcc, 0xcc, 0x02, 0x57, 0x30, 0xef,
+       0x45, 0x98, 0x1f, 0xc6, 0xe7, 0xf3, 0xc3, 0xf8, 0xb7, 0x5e, 0x12, 0x7e,
+       0x12, 0x15, 0x37, 0x98, 0x79, 0xc9, 0x42, 0xf5, 0x1e, 0x3e, 0xf1, 0x89,
+       0xfc, 0xe9, 0xdb, 0xa6, 0x18, 0xd7, 0x65, 0x0f, 0xdf, 0xf8, 0xc4, 0x3a,
+       0x99, 0x71, 0x29, 0x89, 0xbe, 0xfb, 0x9f, 0xe6, 0x9f, 0x6f, 0xe2, 0x1b,
+       0x05, 0x77, 0x78, 0x7e, 0xb2, 0x3a, 0xdf, 0x73, 0x7a, 0x98, 0x3c, 0xff,
+       0x32, 0x86, 0x8d, 0xa1, 0xf5, 0x7f, 0x85, 0x79, 0xc3, 0x6a, 0xbf, 0x57,
+       0x78, 0x1e, 0x7a, 0x6f, 0x09, 0xe5, 0x13, 0x75, 0x3b, 0x32, 0x48, 0x7f,
+       0xe8, 0xd9, 0x6f, 0x9c, 0xc6, 0xf7, 0x2b, 0x63, 0x32, 0x28, 0x8f, 0x58,
+       0x97, 0xfe, 0x39, 0x25, 0x77, 0x75, 0xd9, 0x4e, 0x8d, 0x53, 0xc9, 0xdf,
+       0xbb, 0x46, 0x81, 0x8f, 0x87, 0x24, 0xc1, 0xef, 0xba, 0x7e, 0x6d, 0x66,
+       0x7a, 0x47, 0x88, 0x5e, 0xa2, 0xaf, 0xb3, 0x92, 0xdf, 0x34, 0x7d, 0x4d,
+       0x22, 0x95, 0x95, 0x91, 0xce, 0x24, 0xec, 0x17, 0x95, 0x6b, 0xcc, 0x3e,
+       0xec, 0x83, 0x9f, 0xdc, 0x3f, 0x28, 0xa9, 0x04, 0x7e, 0xf8, 0x75, 0xd6,
+       0x01, 0x53, 0x78, 0xd7, 0x9f, 0xdc, 0x33, 0x3a, 0x9d, 0x15, 0xa0, 0x5e,
+       0x4e, 0xe5, 0xc9, 0xcd, 0x11, 0xb3, 0x43, 0xfd, 0xd9, 0xaa, 0x8c, 0xcf,
+       0x15, 0xfb, 0x46, 0xdd, 0xbd, 0xc7, 0x69, 0xff, 0x3a, 0x67, 0x7a, 0x3b,
+       0x76, 0x36, 0xd6, 0xd9, 0xba, 0x7d, 0xb1, 0x48, 0xa9, 0x59, 0xba, 0xee,
+       0xbd, 0xb1, 0x4e, 0xae, 0x7a, 0xb4, 0x5a, 0x74, 0x67, 0x2e, 0xc5, 0x49,
+       0x5b, 0x77, 0x3a, 0x81, 0x37, 0x67, 0x6b, 0x21, 0xfc, 0xd1, 0x74, 0xf6,
+       0x72, 0x60, 0xaf, 0x9e, 0xb0, 0x64, 0x5d, 0xf9, 0x20, 0xf8, 0xbf, 0x6a,
+       0xff, 0x7e, 0xe4, 0x09, 0xec, 0xef, 0xfa, 0x1a, 0x6b, 0x12, 0xf4, 0xcc,
+       0xcf, 0xdf, 0xe7, 0xfb, 0x9f, 0x46, 0xfb, 0x17, 0xe9, 0x07, 0xa7, 0x91,
+       0x7f, 0x3c, 0x00, 0x71, 0xab, 0x68, 0x3a, 0xdf, 0x76, 0x5a, 0x63, 0x5e,
+       0xc4, 0x6f, 0x16, 0x9b, 0x0f, 0x15, 0x3a, 0x0d, 0xfb, 0xe9, 0xc1, 0x99,
+       0x80, 0xe3, 0xe5, 0x28, 0xdd, 0x95, 0x3b, 0x06, 0xe3, 0x07, 0x76, 0x26,
+       0x63, 0x7c, 0x8f, 0x9f, 0xf2, 0x25, 0xf5, 0x35, 0xd9, 0x71, 0x7d, 0xf9,
+       0x4b, 0x54, 0xb9, 0x7c, 0xab, 0xd0, 0xdf, 0x76, 0x2a, 0x7f, 0xad, 0xf4,
+       0xeb, 0x42, 0x6f, 0x47, 0x1d, 0x7a, 0x3b, 0x82, 0x42, 0xd0, 0xdb, 0x51,
+       0x87, 0xde, 0x8e, 0x12, 0x7a, 0x3b, 0x9e, 0x97, 0xc2, 0x5f, 0x8f, 0xb8,
+       0x6a, 0x53, 0x57, 0x11, 0xec, 0x4e, 0x7f, 0x29, 0xcb, 0xad, 0xa7, 0xfd,
+       0xd5, 0x91, 0x0b, 0xbd, 0x7c, 0x95, 0x16, 0xe5, 0x81, 0xbc, 0x59, 0xa5,
+       0x79, 0x06, 0xc1, 0x0f, 0xc6, 0xb6, 0xa7, 0x88, 0x7d, 0x35, 0x8c, 0xbe,
+       0xaa, 0xbc, 0xb6, 0x8b, 0xeb, 0x56, 0x21, 0xfc, 0x7e, 0xfd, 0x25, 0x3b,
+       0x0b, 0xcd, 0x1f, 0x9b, 0xc0, 0xe2, 0x0d, 0xf5, 0x89, 0xf6, 0x14, 0x43,
+       0xfb, 0x72, 0xa7, 0xdb, 0xf0, 0xfe, 0x86, 0xe4, 0xe1, 0x86, 0xf7, 0x37,
+       0xba, 0x8a, 0x0c, 0xf5, 0x6f, 0xe5, 0x5e, 0x6d, 0x68, 0x7f, 0xb3, 0x67,
+       0x82, 0xa1, 0x7e, 0x4b, 0xc9, 0x8d, 0x86, 0xf6, 0xd3, 0xbc, 0xd3, 0x0c,
+       0xf5, 0xe9, 0x93, 0xe7, 0x18, 0xda, 0xcf, 0xf0, 0x55, 0x1a, 0xde, 0xcf,
+       0x9a, 0xbd, 0xd8, 0xf0, 0x7e, 0x8e, 0xbe, 0xc2, 0x50, 0xbf, 0xbd, 0xe6,
+       0x1e, 0x43, 0xfb, 0x3b, 0xea, 0xd7, 0x18, 0xde, 0x7b, 0x99, 0xd3, 0x82,
+       0xfd, 0xed, 0x20, 0xec, 0x29, 0x8e, 0xf7, 0x9f, 0xc3, 0x9e, 0xe2, 0xe5,
+       0xaa, 0x5f, 0x65, 0x3b, 0x42, 0xe9, 0x3a, 0x7e, 0xa2, 0xa9, 0xbe, 0x2f,
+       0x7f, 0xfc, 0xa2, 0x5c, 0xa1, 0xcf, 0xdc, 0x3f, 0xdc, 0x3b, 0x1f, 0xfc,
+       0x91, 0x26, 0xcf, 0x81, 0xa4, 0xc9, 0xf3, 0x1c, 0x77, 0xe7, 0xba, 0x44,
+       0xde, 0x00, 0xce, 0xed, 0x93, 0x3d, 0xdb, 0x9e, 0x02, 0xbe, 0x09, 0x6f,
+       0x17, 0xfe, 0x7e, 0x7c, 0xf4, 0xe1, 0x8b, 0x2e, 0x4e, 0xc3, 0xf6, 0xdc,
+       0x5b, 0x6e, 0xb3, 0x70, 0xf9, 0x30, 0xfe, 0xaa, 0xc3, 0xa3, 0x32, 0x79,
+       0xdd, 0xfc, 0x74, 0xd3, 0x6d, 0x16, 0x2e, 0x57, 0xc6, 0x5f, 0x73, 0xf8,
+       0xc5, 0x0c, 0x5e, 0x8f, 0x7e, 0xfa, 0x55, 0x51, 0x1f, 0x79, 0xf8, 0x22,
+       0xde, 0xaf, 0x7e, 0x7a, 0x83, 0xa8, 0x4f, 0x67, 0xa4, 0x5a, 0x24, 0x3e,
+       0x3d, 0xee, 0x36, 0x3f, 0x9f, 0xc7, 0xf8, 0xeb, 0x33, 0x36, 0x79, 0x84,
+       0x3f, 0xa4, 0xcf, 0x7c, 0x4b, 0x55, 0x02, 0x0f, 0xc8, 0x5b, 0x04, 0x1e,
+       0x50, 0x06, 0x39, 0x7f, 0xa2, 0x3c, 0xcc, 0xf9, 0x13, 0xe5, 0x51, 0xce,
+       0x9f, 0xd5, 0x59, 0x8c, 0xbd, 0xce, 0xf9, 0x13, 0xe5, 0x31, 0x6e, 0x57,
+       0xe2, 0xf9, 0x2f, 0xb9, 0x5d, 0x89, 0xf2, 0x6d, 0x6e, 0x57, 0xa2, 0x7c,
+       0x87, 0xdb, 0x95, 0x28, 0xdb, 0xb9, 0x5d, 0x89, 0xf2, 0x37, 0x8d, 0xb3,
+       0xa9, 0x7c, 0xbf, 0x51, 0xa7, 0xef, 0xfe, 0xb3, 0xb1, 0x86, 0xca, 0xe3,
+       0x8d, 0xf5, 0xf4, 0xfc, 0xc3, 0xc6, 0x06, 0x2a, 0x3f, 0x6e, 0xf4, 0xd3,
+       0xf3, 0xcd, 0xb9, 0xca, 0x4f, 0x11, 0x24, 0x3f, 0x8b, 0x8a, 0x27, 0x2d,
+       0x43, 0x1c, 0x0f, 0x7e, 0xb8, 0x03, 0xd6, 0xb3, 0xa1, 0x71, 0x56, 0x15,
+       0x0f, 0x54, 0xf1, 0xbf, 0xa6, 0x7a, 0xd6, 0x11, 0x8d, 0x75, 0xda, 0x61,
+       0x89, 0xff, 0xd4, 0xde, 0x1b, 0xd7, 0xeb, 0x5f, 0xce, 0x5a, 0xd8, 0xa7,
+       0x21, 0xfa, 0x56, 0x6b, 0xb4, 0x77, 0x5b, 0x2e, 0xf9, 0x2f, 0x86, 0x38,
+       0x29, 0xae, 0x23, 0x9f, 0x97, 0x6a, 0xd3, 0xd3, 0x8a, 0x79, 0xf9, 0x85,
+       0x4b, 0x7f, 0x0a, 0xef, 0x67, 0x14, 0x57, 0xad, 0x8b, 0x73, 0xe3, 0x1c,
+       0x48, 0xbd, 0x15, 0xfc, 0xf2, 0x81, 0xa9, 0xef, 0x73, 0xc1, 0x77, 0x4b,
+       0x3e, 0xa9, 0x1a, 0xee, 0xfd, 0x09, 0xbe, 0x53, 0x71, 0x6c, 0x15, 0x47,
+       0xee, 0xc9, 0x4f, 0x09, 0x89, 0x73, 0x9b, 0x42, 0xf2, 0x62, 0xe8, 0x2f,
+       0x24, 0xbf, 0x45, 0xc5, 0x9b, 0x55, 0x3e, 0xcd, 0x75, 0x76, 0x91, 0x9f,
+       0xa7, 0xe2, 0xc9, 0x2a, 0x6f, 0x46, 0xf5, 0x57, 0x7e, 0x89, 0x91, 0xbc,
+       0xbb, 0x76, 0xa3, 0x85, 0xf4, 0x93, 0x18, 0x0b, 0x0b, 0xa2, 0x7f, 0x95,
+       0x1f, 0x73, 0xad, 0xbd, 0xad, 0x08, 0xf9, 0x02, 0xd7, 0xd6, 0x3a, 0x28,
+       0x0f, 0x6d, 0x10, 0x7f, 0x6e, 0x2b, 0xa6, 0x76, 0x5e, 0x33, 0x2f, 0xb7,
+       0xff, 0x99, 0xb7, 0x2f, 0xec, 0x8d, 0x5f, 0x0f, 0x92, 0xf0, 0xf3, 0xf7,
+       0x04, 0x7f, 0xf9, 0x25, 0x9d, 0xfc, 0xae, 0xd7, 0xca, 0xf8, 0x3d, 0xbe,
+       0xb7, 0x8b, 0xf7, 0x7e, 0x7c, 0x8f, 0xdc, 0x29, 0xe8, 0x19, 0xbc, 0x24,
+       0xbf, 0xda, 0xe3, 0xc8, 0x73, 0x2a, 0xee, 0x8d, 0xa7, 0xa3, 0x7d, 0xb4,
+       0x68, 0x1f, 0x44, 0x7f, 0x59, 0xff, 0xc5, 0xc7, 0x8b, 0xed, 0x5d, 0x3f,
+       0x69, 0x09, 0x6d, 0x45, 0xc8, 0xa7, 0x4a, 0x5b, 0xe6, 0xa0, 0x7c, 0xaa,
+       0x6d, 0x13, 0x82, 0x74, 0x7e, 0x4b, 0x77, 0xeb, 0xef, 0x01, 0x9f, 0xbe,
+       0x08, 0xe7, 0xef, 0xa3, 0x69, 0xfd, 0x64, 0xa6, 0xc1, 0x4f, 0x30, 0x4d,
+       0xea, 0xbd, 0x5f, 0x43, 0x87, 0xe3, 0x58, 0xaf, 0x0a, 0x3f, 0x0a, 0xcf,
+       0x8a, 0x2e, 0x0a, 0xbf, 0x21, 0x79, 0x47, 0x84, 0xd7, 0xfe, 0xe8, 0x14,
+       0x4e, 0x9f, 0x70, 0xba, 0x28, 0x7a, 0x94, 0x5f, 0xea, 0xc5, 0x33, 0xf0,
+       0x74, 0x39, 0x1d, 0x7a, 0xe9, 0x04, 0x7f, 0xec, 0xff, 0x2b, 0x74, 0x18,
+       0x6d, 0x69, 0xa3, 0xf3, 0x7f, 0x11, 0xb5, 0x76, 0x0f, 0xe0, 0xfa, 0x26,
+       0xba, 0xdc, 0xd9, 0xc5, 0x26, 0xe1, 0x3c, 0x71, 0x72, 0x86, 0x7e, 0x37,
+       0xe8, 0x53, 0x79, 0xc9, 0xf5, 0x3a, 0xea, 0x55, 0x6c, 0xc2, 0x24, 0x6c,
+       0x4d, 0xea, 0xbd, 0xfb, 0x1b, 0xde, 0x4f, 0xfe, 0x86, 0xf7, 0x0b, 0xfb,
+       0x79, 0xff, 0x56, 0xa4, 0xca, 0x47, 0xf0, 0x3a, 0x8a, 0x38, 0x5d, 0x26,
+       0x4a, 0xf9, 0xb1, 0xaa, 0x5c, 0xe0, 0x77, 0xb2, 0xdb, 0x4c, 0xf8, 0x9d,
+       0x98, 0xbf, 0x88, 0xf4, 0x51, 0xe6, 0x10, 0x7a, 0x9d, 0x8b, 0xff, 0x0f,
+       0xf2, 0x64, 0xd2, 0x57, 0xbe, 0xb5, 0xe8, 0x6f, 0xd2, 0x00, 0xa3, 0x7e,
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+       0xe3, 0x8a, 0x32, 0xdc, 0xd7, 0x12, 0x9d, 0x9b, 0x60, 0xa8, 0xc7, 0x78,
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+       0x7a, 0x22, 0xf4, 0xb8, 0x34, 0xa9, 0x47, 0x35, 0xfd, 0xce, 0x6e, 0x07,
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+       0x53, 0x95, 0x1e, 0xac, 0xf2, 0x71, 0x75, 0xc9, 0xd7, 0xe1, 0xfa, 0xf4,
+       0x50, 0x9b, 0x4e, 0xf9, 0xbd, 0x4d, 0x29, 0xcc, 0x43, 0xe7, 0x00, 0xec,
+       0xd2, 0x3e, 0x61, 0x46, 0x3d, 0x5b, 0x97, 0xf9, 0xb4, 0x4a, 0x1f, 0x65,
+       0x7e, 0x63, 0x3e, 0xad, 0xca, 0xa3, 0xed, 0xd1, 0xc7, 0xa5, 0xfe, 0xad,
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+       0x37, 0x7c, 0xdf, 0xab, 0x1c, 0x21, 0xcf, 0xf3, 0x85, 0xc1, 0x3f, 0xd4,
+       0x26, 0xe6, 0xdb, 0x74, 0x8f, 0x8d, 0xce, 0x2d, 0x28, 0xb8, 0xc2, 0xe1,
+       0x39, 0x2b, 0xf3, 0x3b, 0x77, 0xd8, 0xfb, 0x3e, 0x3f, 0xb2, 0x7c, 0x84,
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+       0x65, 0xf6, 0x35, 0x9e, 0xa7, 0xc3, 0xcf, 0xf9, 0xab, 0xe9, 0x7b, 0x36,
+       0xcf, 0x7d, 0xae, 0x6f, 0x1e, 0x6f, 0xde, 0x48, 0x31, 0x9f, 0x0a, 0x93,
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+       0x25, 0x7f, 0x57, 0xe7, 0x6b, 0x7d, 0xce, 0x6f, 0x5e, 0x9c, 0xc8, 0x2b,
+       0x62, 0x71, 0x36, 0x17, 0xf8, 0xb7, 0xff, 0xf1, 0x04, 0x3e, 0x93, 0x6d,
+       0x6c, 0x2d, 0x9d, 0x73, 0x91, 0x79, 0xe7, 0x77, 0x6c, 0x6a, 0x7b, 0x10,
+       0x2e, 0xf2, 0x0a, 0x5b, 0xb3, 0x55, 0xdc, 0x5f, 0x16, 0xb0, 0x82, 0x1f,
+       0xa6, 0x94, 0x72, 0xfd, 0xa9, 0x88, 0xdb, 0xc9, 0xdb, 0xff, 0xeb, 0x87,
+       0x0e, 0xae, 0xe7, 0x3c, 0xd1, 0x60, 0x21, 0x3f, 0xc4, 0xfa, 0x67, 0xca,
+       0x67, 0x70, 0xcd, 0xab, 0xe7, 0x1c, 0xc1, 0x50, 0x6e, 0x5f, 0x80, 0x3f,
+       0xa0, 0xab, 0xc0, 0x2e, 0xf9, 0x4b, 0x9e, 0xc8, 0x9b, 0xfd, 0xc9, 0x08,
+       0x46, 0x65, 0xb9, 0xf9, 0xab, 0x9e, 0xfc, 0x6f, 0xf2, 0xa7, 0x33, 0x26,
+       0xf7, 0x07, 0x61, 0xb7, 0xf4, 0xc1, 0x6f, 0xc4, 0x87, 0x6a, 0x1e, 0xff,
+       0xee, 0x3c, 0xf0, 0x70, 0x3c, 0x29, 0xbb, 0x90, 0xc9, 0xbc, 0xbb, 0x2c,
+       0x09, 0x97, 0xc2, 0x5f, 0x8f, 0x1d, 0x2f, 0xf1, 0xa7, 0xf2, 0xf1, 0x5d,
+       0x2b, 0xac, 0xbe, 0xa7, 0x1c, 0x94, 0xd7, 0x3f, 0x19, 0xf9, 0x4c, 0x8a,
+       0x7e, 0x31, 0xf9, 0x82, 0x2f, 0x7f, 0x27, 0xf1, 0x81, 0x76, 0x90, 0x47,
+       0xfd, 0xb5, 0x2b, 0x37, 0xe7, 0xc7, 0xc1, 0x5f, 0xdb, 0xcd, 0x5c, 0x71,
+       0xce, 0xaf, 0xf1, 0x47, 0xfe, 0xbb, 0xf0, 0xa2, 0xf0, 0xdf, 0xdf, 0xf9,
+       0x9e, 0xfe, 0xe4, 0xc3, 0x65, 0x72, 0xa1, 0x9f, 0xf3, 0x3e, 0xfd, 0xf1,
+       0x27, 0xfd, 0xfd, 0x13, 0xe7, 0x7e, 0x42, 0xe4, 0x83, 0xc8, 0x2f, 0x91,
+       0xf4, 0x08, 0x64, 0x99, 0x28, 0x9e, 0xbb, 0x21, 0xc6, 0xb8, 0x8e, 0xed,
+       0x79, 0x62, 0x5f, 0x78, 0x4e, 0xed, 0x17, 0x7e, 0x6e, 0x4f, 0x1a, 0xe5,
+       0x04, 0x83, 0x7f, 0xb9, 0x69, 0x9d, 0x59, 0xca, 0x09, 0xb1, 0x6f, 0x63,
+       0xff, 0xc4, 0xf3, 0x05, 0xeb, 0xac, 0xa4, 0xcf, 0xb0, 0x06, 0x91, 0x8f,
+       0x5c, 0x23, 0x65, 0x31, 0x63, 0xbe, 0xa4, 0x71, 0xa3, 0x11, 0x8f, 0xb5,
+       0xd2, 0x7d, 0x56, 0xd7, 0x79, 0x19, 0xe9, 0x3b, 0xf3, 0x1d, 0xb6, 0x40,
+       0x2b, 0x6f, 0x5f, 0xe9, 0x0f, 0xdf, 0xb7, 0xbd, 0xf4, 0x3d, 0xc5, 0x6b,
+       0x5c, 0xb8, 0xb7, 0xc4, 0xb3, 0x1e, 0xfe, 0xf7, 0xaa, 0x8d, 0xc6, 0x76,
+       0x8b, 0x1c, 0xe2, 0x5e, 0xaf, 0x05, 0x61, 0x76, 0xe9, 0x22, 0x69, 0x97,
+       0x2e, 0x0a, 0xb3, 0x4b, 0xff, 0x3a, 0x42, 0xda, 0xa5, 0x1e, 0xe6, 0x21,
+       0xbd, 0x4c, 0xc6, 0x9f, 0x15, 0x9c, 0x3d, 0x7c, 0x15, 0xc8, 0xa4, 0xbc,
+       0x60, 0xd8, 0xa9, 0x66, 0xe1, 0x2f, 0xa1, 0x7c, 0x25, 0x85, 0x27, 0x17,
+       0xe2, 0x0b, 0x21, 0xf7, 0x68, 0x72, 0x7c, 0x46, 0xe5, 0x62, 0xdf, 0x5e,
+       0x6b, 0xe9, 0x33, 0x8f, 0xac, 0x07, 0x9f, 0xfd, 0xc4, 0xc9, 0xcf, 0x22,
+       0x4e, 0xee, 0xc2, 0xfa, 0xef, 0xa6, 0xf3, 0x3f, 0xdd, 0x7b, 0x23, 0x45,
+       0x1c, 0x4d, 0xc5, 0x2f, 0x64, 0xfb, 0xb3, 0xfe, 0x8b, 0xf4, 0x1e, 0xed,
+       0xd1, 0xdb, 0xb9, 0xa2, 0xf6, 0x42, 0xc4, 0x91, 0x7a, 0xe2, 0x1d, 0x61,
+       0x71, 0x93, 0x6e, 0x87, 0x29, 0xb6, 0x04, 0xfd, 0xed, 0x16, 0xf7, 0x2f,
+       0xa8, 0x3c, 0x80, 0x25, 0x7f, 0x0d, 0x14, 0x3a, 0x43, 0xe2, 0x9c, 0x7a,
+       0x87, 0xc9, 0x90, 0x77, 0x11, 0x5e, 0xea, 0x6b, 0xf6, 0x51, 0x5e, 0x40,
+       0xab, 0x45, 0xcf, 0xcc, 0x43, 0x3e, 0xb2, 0xc5, 0x63, 0xc7, 0x7d, 0x91,
+       0xf7, 0x3b, 0x0e, 0x27, 0xe1, 0xbc, 0xf6, 0x14, 0xe9, 0xaf, 0x09, 0x87,
+       0xb7, 0x47, 0xaf, 0x1a, 0xaf, 0x89, 0x38, 0xa1, 0x5f, 0xe8, 0xb9, 0xdd,
+       0x93, 0x35, 0xd2, 0x73, 0xb9, 0x5c, 0x64, 0x58, 0x47, 0x2a, 0x9e, 0x3d,
+       0x8d, 0x05, 0x07, 0xa0, 0x54, 0xf1, 0x03, 0x7d, 0x63, 0x09, 0xe1, 0x59,
+       0xc5, 0x0f, 0x2a, 0x83, 0x25, 0x04, 0xe7, 0x8c, 0xa6, 0x45, 0x56, 0x5c,
+       0xd9, 0xd7, 0xf1, 0xe8, 0xea, 0xf2, 0x28, 0x57, 0x6f, 0x5c, 0xa1, 0x23,
+       0x4d, 0xe4, 0xa3, 0xf4, 0x17, 0x5f, 0x98, 0x7e, 0xc9, 0x43, 0xfd, 0xdd,
+       0x76, 0x69, 0x1c, 0xf5, 0x53, 0x9a, 0xe7, 0x16, 0xe7, 0xf5, 0xd7, 0x3e,
+       0xb8, 0x02, 0x7c, 0x34, 0x62, 0x17, 0xb3, 0x62, 0x9e, 0x1d, 0x61, 0xf9,
+       0xd8, 0xaa, 0x7c, 0x21, 0x4f, 0xc8, 0x9f, 0x77, 0xf3, 0x94, 0xdc, 0x96,
+       0x79, 0x2e, 0x6b, 0x34, 0xa1, 0xc7, 0x6b, 0x4c, 0xe5, 0xbd, 0x90, 0xdc,
+       0x56, 0xf5, 0x8b, 0xcd, 0xb2, 0x5e, 0x2e, 0xea, 0xab, 0xd6, 0x89, 0x7a,
+       0x87, 0xbc, 0xc7, 0x68, 0xa7, 0xf4, 0x37, 0x60, 0x9e, 0x28, 0x31, 0x1f,
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+       0xe4, 0x14, 0xea, 0x90, 0x53, 0xa8, 0x43, 0x4e, 0xa1, 0x0e, 0x39, 0x85,
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+       0x1f, 0xf7, 0x89, 0x31, 0xdb, 0x02, 0xc8, 0x77, 0x9b, 0xd0, 0x13, 0xf0,
+       0x1d, 0xec, 0xc7, 0x3c, 0xbf, 0xe6, 0x7d, 0x2a, 0x84, 0xbf, 0x3f, 0xcd,
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+       0x3a, 0xe9, 0x9c, 0x57, 0x8f, 0xbd, 0xb2, 0x2d, 0x9d, 0xce, 0xa5, 0x55,
+       0xb2, 0x8e, 0xb2, 0x64, 0xf2, 0xe5, 0x6b, 0x74, 0x8f, 0xb9, 0xc2, 0x1b,
+       0x9f, 0xdf, 0x51, 0xcc, 0x8f, 0x8b, 0xf8, 0x63, 0x56, 0xd2, 0x47, 0xc5,
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+       0xea, 0x75, 0xd0, 0xb9, 0xf2, 0x71, 0x79, 0x1f, 0xc8, 0xc6, 0x4a, 0x3a,
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+       0x99, 0x68, 0xc2, 0xbd, 0x15, 0x15, 0xfb, 0xbc, 0x1e, 0xad, 0x0f, 0xfe,
+       0x78, 0x57, 0xea, 0x2f, 0x53, 0x30, 0x68, 0x22, 0xf2, 0x7c, 0x06, 0x53,
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+       0x52, 0x11, 0x73, 0x96, 0x43, 0x6e, 0x8c, 0xf0, 0x6a, 0x47, 0xe0, 0xbe,
+       0x9e, 0x62, 0xd5, 0xd7, 0x21, 0x8f, 0x70, 0x4a, 0x2b, 0xa3, 0xf3, 0x30,
+       0x37, 0x43, 0xaf, 0xe1, 0x2f, 0x66, 0x43, 0xcf, 0x19, 0x05, 0x3e, 0x77,
+       0x97, 0xd3, 0xb9, 0x80, 0xc9, 0x1a, 0x9d, 0xaf, 0xb8, 0x79, 0xf4, 0x0a,
+       0xc9, 0xd7, 0x9c, 0xcf, 0x19, 0xf8, 0xdc, 0x2f, 0xf9, 0xd6, 0x47, 0xf5,
+       0x9e, 0xfd, 0x40, 0xf2, 0xb7, 0xee, 0xef, 0xb4, 0xd0, 0xbd, 0xac, 0x7e,
+       0xcd, 0x86, 0x7b, 0xd9, 0x74, 0x69, 0xcf, 0x2a, 0xfe, 0x0d, 0xe7, 0xf3,
+       0x79, 0xf2, 0xf7, 0x26, 0x98, 0x43, 0xf8, 0x99, 0x7a, 0xfc, 0x50, 0x00,
+       0x16, 0x97, 0xab, 0xf8, 0xc7, 0xce, 0x84, 0xbe, 0x38, 0x0f, 0xbe, 0xc1,
+       0xc1, 0x92, 0x90, 0x76, 0xd8, 0x75, 0xe2, 0xfd, 0xdd, 0xbb, 0xc7, 0xce,
+       0x5c, 0x8b, 0x1c, 0xeb, 0xff, 0x4b, 0xff, 0x44, 0x85, 0xfa, 0x1d, 0x06,
+       0xae, 0x67, 0x41, 0x9e, 0xde, 0x71, 0x57, 0x91, 0x6d, 0x7e, 0x88, 0x5c,
+       0x29, 0x2d, 0x2c, 0x6d, 0x29, 0x18, 0xd8, 0x4b, 0xf7, 0xf9, 0x3d, 0xe7,
+       0xc6, 0xf2, 0x07, 0x41, 0xff, 0x5f, 0x79, 0x7f, 0xf6, 0xa0, 0xaf, 0x3b,
+       0xbf, 0x58, 0xc5, 0xf1, 0x8c, 0xf5, 0x31, 0x2f, 0xae, 0xe3, 0x6e, 0xdc,
+       0x8c, 0xfb, 0x70, 0x3e, 0xf3, 0x96, 0x25, 0xe3, 0x3e, 0x66, 0xa6, 0x2e,
+       0x91, 0x09, 0x22, 0x5f, 0x6d, 0xae, 0xac, 0x1f, 0xde, 0x7d, 0xe7, 0x7f,
+       0x6e, 0x74, 0x10, 0x7e, 0xa8, 0xbe, 0x39, 0xbf, 0x7c, 0xa6, 0x9f, 0xd6,
+       0x8b, 0x90, 0x57, 0xb7, 0x43, 0x5e, 0x99, 0x21, 0xa7, 0xf4, 0x87, 0xf2,
+       0x91, 0x1f, 0x64, 0xef, 0x98, 0x04, 0x7a, 0x44, 0xe7, 0x77, 0xc9, 0xf3,
+       0xf0, 0xf2, 0x1c, 0x6b, 0x98, 0x3f, 0xe2, 0x70, 0xbe, 0xa0, 0x43, 0xb8,
+       0x5f, 0xa2, 0x2a, 0x5f, 0xc8, 0x71, 0x66, 0x71, 0xa5, 0xdf, 0x4e, 0xe7,
+       0x54, 0x5d, 0xe4, 0xd7, 0x53, 0xf0, 0x7f, 0x62, 0x35, 0x9e, 0x1b, 0x54,
+       0xe5, 0xcf, 0xa4, 0x7d, 0xfd, 0xef, 0xca, 0xb7, 0xff, 0x73, 0x92, 0xfe,
+       0x2c, 0xe6, 0xf7, 0x88, 0x49, 0x9c, 0xdf, 0x1e, 0x6c, 0x6e, 0x66, 0xd2,
+       0x3f, 0x24, 0x7e, 0x27, 0x43, 0xae, 0x1f, 0x26, 0xef, 0x33, 0xe8, 0xa5,
+       0x3f, 0x97, 0x1a, 0xa0, 0xff, 0xfd, 0x9a, 0x33, 0x94, 0xfe, 0xfa, 0x46,
+       0x4d, 0x9c, 0x9b, 0xee, 0xc7, 0x8f, 0xc3, 0x72, 0xbb, 0x1e, 0xdd, 0x01,
+       0x3f, 0x5e, 0xa3, 0xf8, 0x7d, 0x8e, 0x27, 0x73, 0x04, 0x1f, 0x3d, 0xf9,
+       0x1d, 0x1b, 0xe9, 0xdf, 0x15, 0xb6, 0xf6, 0xd7, 0x70, 0x4f, 0x93, 0xc2,
+       0xe3, 0x47, 0x0d, 0xff, 0x61, 0xa5, 0xfb, 0xfe, 0x58, 0x30, 0x1b, 0xf7,
+       0x4f, 0xcd, 0xad, 0x8f, 0xa4, 0xfb, 0x5e, 0x4b, 0x0b, 0x7d, 0x87, 0x20,
+       0xf7, 0xa2, 0xf3, 0x3d, 0x44, 0x8f, 0x96, 0x02, 0xc1, 0x67, 0x1d, 0x4e,
+       0xdf, 0x51, 0x3c, 0xaf, 0xdb, 0x74, 0xe8, 0x09, 0x9c, 0x1f, 0x5f, 0x7e,
+       0xd0, 0x4d, 0xe7, 0x1a, 0x2b, 0x0f, 0x14, 0xad, 0xc7, 0xbd, 0x16, 0xa5,
+       0x85, 0xfa, 0x9b, 0x98, 0x6f, 0xa5, 0xc3, 0x69, 0xc3, 0xfe, 0xbd, 0x6c,
+       0x6d, 0x3c, 0xed, 0x67, 0xf3, 0x06, 0xc9, 0xf3, 0x85, 0xac, 0x8b, 0xe2,
+       0x54, 0x0a, 0xff, 0x9d, 0xf9, 0x62, 0x1f, 0xdd, 0x52, 0xc8, 0xe4, 0x3d,
+       0xa7, 0x32, 0xbf, 0x9e, 0x0b, 0xca, 0x69, 0x86, 0x76, 0x32, 0xaf, 0x38,
+       0x6c, 0x9d, 0x28, 0xff, 0x60, 0xb8, 0x9f, 0x21, 0xfc, 0x3e, 0x81, 0xfe,
+       0xd6, 0x8f, 0xf2, 0x27, 0xc0, 0x7f, 0x60, 0x0b, 0xf1, 0x2f, 0x2a, 0xff,
+       0x84, 0x35, 0xf7, 0x93, 0x39, 0xd8, 0x3f, 0x2b, 0x6c, 0xc6, 0xf3, 0x70,
+       0xaa, 0x4c, 0x28, 0x90, 0x76, 0xae, 0xb4, 0x03, 0x17, 0xf4, 0xec, 0x5f,
+       0xf9, 0x93, 0x06, 0x41, 0x5f, 0xde, 0xac, 0xd1, 0xef, 0xd6, 0x54, 0x3b,
+       0x5c, 0xb3, 0xae, 0xe6, 0xf5, 0xea, 0x63, 0x56, 0x64, 0x0a, 0xb2, 0x29,
+       0x09, 0x2e, 0x71, 0x8f, 0xc4, 0xfd, 0xe2, 0x1e, 0x89, 0xf9, 0x7c, 0xbd,
+       0x42, 0xde, 0x54, 0xc8, 0xbc, 0xa1, 0xea, 0xad, 0x25, 0xb4, 0xde, 0xaa,
+       0x03, 0xbc, 0x4c, 0xec, 0x7f, 0x5d, 0xde, 0xbe, 0xf9, 0x48, 0xda, 0xcb,
+       0xe0, 0x9f, 0xa0, 0x97, 0xce, 0x89, 0x57, 0x3b, 0xbd, 0xb6, 0x84, 0x90,
+       0x75, 0x5f, 0xd5, 0xac, 0x19, 0xce, 0x99, 0xab, 0xba, 0xa9, 0xc0, 0x2c,
+       0xd6, 0x11, 0xae, 0x30, 0x2f, 0x86, 0xbc, 0x70, 0xdb, 0x70, 0x97, 0x4b,
+       0x05, 0x57, 0x2b, 0x90, 0x87, 0x96, 0x50, 0x20, 0xf8, 0x43, 0x7d, 0xc7,
+       0xdb, 0x51, 0x1e, 0xc3, 0x94, 0x0c, 0xf6, 0xba, 0xb8, 0xc7, 0x87, 0xc3,
+       0xed, 0x16, 0xe3, 0x15, 0x87, 0xf4, 0x3f, 0xbf, 0xd9, 0x78, 0x5e, 0x9e,
+       0xb7, 0x27, 0x7d, 0xc8, 0x51, 0x10, 0x23, 0xce, 0xa7, 0x3b, 0xf9, 0xbc,
+       0xe1, 0xff, 0x70, 0x3a, 0x09, 0x4e, 0x8e, 0x07, 0xc2, 0x53, 0xd7, 0x83,
+       0xbc, 0x3f, 0x17, 0x8d, 0x43, 0xf4, 0xa8, 0x0a, 0x06, 0xac, 0xb0, 0xb7,
+       0x2b, 0x90, 0x3f, 0xc1, 0xeb, 0x73, 0x9d, 0x01, 0x2b, 0xc6, 0x99, 0xbf,
+       0x56, 0xdc, 0x5b, 0xa1, 0x6f, 0x12, 0xe3, 0xe8, 0x1b, 0xe3, 0x6d, 0x05,
+       0xd0, 0x97, 0x2c, 0x4e, 0x5b, 0x1a, 0xf0, 0x27, 0xef, 0xb5, 0xe7, 0xf0,
+       0x91, 0x1c, 0xac, 0xe6, 0x78, 0xc1, 0xf9, 0x1f, 0x75, 0x0e, 0x30, 0x1c,
+       0x3f, 0x95, 0x12, 0xde, 0xea, 0xe6, 0x78, 0xa3, 0x1e, 0xd6, 0xbc, 0xd9,
+       0x0a, 0x7a, 0xcc, 0xe9, 0xe7, 0xfc, 0xfc, 0x75, 0x05, 0x82, 0x6f, 0xe7,
+       0xaf, 0x9d, 0x40, 0xe7, 0x9f, 0xab, 0x2d, 0x5e, 0xca, 0xaf, 0xd7, 0x25,
+       0x7e, 0xff, 0xb8, 0x22, 0xf2, 0x01, 0xc4, 0x07, 0xe6, 0xb4, 0x6c, 0xb1,
+       0xba, 0x79, 0xbd, 0xb0, 0x40, 0xc8, 0x99, 0xeb, 0x0a, 0x04, 0x7f, 0x4d,
+       0xc9, 0x08, 0x66, 0xd3, 0xfd, 0x34, 0x2b, 0x22, 0x3d, 0x80, 0x73, 0x8e,
+       0xb3, 0x99, 0xe6, 0xd7, 0x83, 0xdf, 0x87, 0x39, 0x3e, 0x34, 0xdc, 0x83,
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+       0xcf, 0x5e, 0x78, 0x62, 0xc4, 0x3d, 0x46, 0x2d, 0x95, 0xb4, 0xde, 0x16,
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+       0x1f, 0x64, 0xe5, 0xcb, 0xd6, 0x49, 0xf8, 0xdd, 0x11, 0xae, 0x7f, 0xd1,
+       0x93, 0x5a, 0x4b, 0xd0, 0xd6, 0x17, 0xfd, 0x96, 0x48, 0xfd, 0xaa, 0xa7,
+       0xbe, 0x77, 0x0f, 0xd9, 0x6d, 0xb5, 0xbb, 0x85, 0xfe, 0x50, 0xdb, 0xd6,
+       0x49, 0xfa, 0x83, 0xd2, 0x47, 0xd4, 0xb9, 0xb8, 0xa5, 0xbb, 0x3b, 0x49,
+       0x9f, 0x50, 0xdf, 0x2d, 0xdb, 0x2b, 0xf0, 0x52, 0xb7, 0x57, 0x3c, 0xaf,
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+       0x77, 0x76, 0xcf, 0x9d, 0xb5, 0xc6, 0x50, 0x9f, 0x43, 0xf5, 0x77, 0xf2,
+       0xa5, 0xbf, 0xde, 0xd2, 0x45, 0xfa, 0xe0, 0x03, 0xb9, 0xbf, 0x21, 0x3b,
+       0xbc, 0x6e, 0xad, 0xec, 0x97, 0xd7, 0xad, 0x21, 0xe3, 0xed, 0x07, 0x13,
+       0x8d, 0x11, 0xcf, 0x33, 0x1d, 0xf8, 0xde, 0x65, 0xd0, 0x1b, 0xea, 0xf6,
+       0xc6, 0xd3, 0xf7, 0xc1, 0xba, 0xa8, 0x8d, 0xd8, 0xe7, 0xbd, 0xcb, 0x1c,
+       0x16, 0x94, 0x4d, 0x75, 0x0e, 0xda, 0xf7, 0xb7, 0xd5, 0x9b, 0x72, 0x2d,
+       0xa3, 0x01, 0x5c, 0x94, 0x07, 0x7a, 0xdc, 0x41, 0x99, 0xbf, 0x35, 0x70,
+       0xe9, 0x7f, 0x46, 0xc2, 0x7f, 0x90, 0xc2, 0xba, 0x8e, 0xe0, 0xde, 0xd7,
+       0xc3, 0x4e, 0xfd, 0x4d, 0xc8, 0x19, 0xf5, 0x7b, 0x96, 0xea, 0xdc, 0xcb,
+       0x85, 0x57, 0x3f, 0x1b, 0x85, 0xfe, 0xaf, 0x1b, 0xda, 0x71, 0x11, 0x77,
+       0x3c, 0x58, 0xb5, 0x85, 0xb3, 0x10, 0x9f, 0xf8, 0x75, 0xa1, 0x9c, 0x47,
+       0x7e, 0xc7, 0x28, 0xf0, 0xf5, 0xc0, 0xc3, 0x42, 0x3e, 0x3f, 0x6e, 0x65,
+       0x1b, 0xe9, 0xfe, 0x60, 0x8b, 0x8f, 0xc1, 0x6f, 0x1f, 0x94, 0x71, 0x45,
+       0xff, 0x5f, 0x4c, 0xe2, 0xf7, 0x25, 0xb4, 0xe0, 0x8f, 0x43, 0xf5, 0x2b,
+       0xeb, 0x48, 0xb1, 0x9f, 0xfa, 0x22, 0x44, 0x7c, 0xb1, 0xc8, 0xad, 0x7f,
+       0x08, 0x38, 0x6e, 0xd1, 0xac, 0x05, 0x45, 0xb0, 0xa9, 0x5d, 0xe6, 0x6c,
+       0xf4, 0xaf, 0x7e, 0x47, 0x45, 0xe9, 0xa9, 0xa5, 0x52, 0x3e, 0xa7, 0x49,
+       0xfb, 0xca, 0x36, 0x38, 0xd9, 0x01, 0x3e, 0xd6, 0xbc, 0x5e, 0x3a, 0x87,
+       0x78, 0x5f, 0xfe, 0xe1, 0x2a, 0xec, 0xcb, 0xdf, 0xef, 0xb2, 0xd3, 0xef,
+       0xab, 0xaa, 0x3c, 0xbf, 0xd2, 0xae, 0x28, 0xd2, 0x5b, 0xd3, 0x06, 0x4f,
+       0xa6, 0xfd, 0x4c, 0x73, 0x59, 0x58, 0x45, 0x31, 0xfc, 0x2a, 0xa6, 0x20,
+       0xf2, 0x55, 0xbf, 0xcf, 0xec, 0x22, 0x2f, 0xc0, 0x1e, 0xa6, 0xd7, 0x9a,
+       0x22, 0x29, 0x1f, 0x59, 0x3b, 0xf8, 0xc6, 0x5f, 0x20, 0xcf, 0x53, 0xcd,
+       0x5f, 0x1e, 0xc1, 0xef, 0x94, 0xa4, 0x7e, 0x5b, 0xa3, 0xfb, 0x2f, 0xe7,
+       0x75, 0x7f, 0xfa, 0x38, 0x7e, 0x63, 0xa6, 0x82, 0x05, 0x8a, 0xe8, 0x1e,
+       0xbc, 0x78, 0xfd, 0x22, 0x48, 0x77, 0xa2, 0x7b, 0x72, 0xa7, 0xce, 0x49,
+       0xf6, 0x7d, 0x67, 0x9b, 0xdd, 0x23, 0xf6, 0x09, 0x16, 0x0a, 0xff, 0xc1,
+       0x7b, 0xfe, 0x12, 0x9b, 0x60, 0xea, 0x85, 0xeb, 0x42, 0xd7, 0xa7, 0x74,
+       0xaf, 0xe0, 0x85, 0x2e, 0x3b, 0xf9, 0x6b, 0x4b, 0x0f, 0xca, 0xfb, 0xf6,
+       0xc2, 0xe0, 0xb9, 0x90, 0xec, 0xa2, 0xbc, 0x68, 0xde, 0x8e, 0xf4, 0xcc,
+       0x0b, 0x0e, 0x13, 0xdd, 0x33, 0x56, 0x7a, 0xf0, 0x08, 0xdd, 0x9b, 0x57,
+       0xaa, 0xee, 0xd5, 0xb3, 0x1b, 0xef, 0xd5, 0x63, 0xae, 0xb4, 0x78, 0xf8,
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+       0x8c, 0x76, 0x62, 0xd2, 0x48, 0xa1, 0x27, 0x26, 0x8d, 0xd4, 0xe4, 0x3d,
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+       0x7f, 0x5a, 0x14, 0xde, 0x22, 0xc3, 0xf8, 0xc1, 0xe3, 0xb7, 0xe5, 0x3a,
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+       0xa6, 0x67, 0x1a, 0x6c, 0x1f, 0xd2, 0x97, 0xcc, 0x62, 0x2c, 0xc3, 0x6a,
+       0x21, 0x3c, 0x4c, 0x3c, 0x01, 0x78, 0x82, 0x7d, 0x0e, 0x2d, 0x8c, 0x70,
+       0xb7, 0xc0, 0xf9, 0x58, 0x86, 0x92, 0x8b, 0xed, 0x49, 0xba, 0xa1, 0x48,
+       0x0b, 0xe0, 0x63, 0xf0, 0x86, 0xb6, 0xc8, 0x6d, 0xa6, 0x71, 0x91, 0x7f,
+       0x0f, 0xf5, 0x37, 0xf1, 0xef, 0x07, 0x8c, 0xed, 0xee, 0x96, 0xa9, 0x5e,
+       0x85, 0xd5, 0xd2, 0x67, 0x85, 0x49, 0x60, 0xbd, 0xfa, 0x54, 0xf3, 0x13,
+       0x88, 0xbf, 0xba, 0x04, 0xa3, 0x91, 0xca, 0xee, 0x6b, 0x85, 0x0c, 0xe7,
+       0xd1, 0x96, 0xa4, 0xde, 0x0d, 0xf3, 0xd8, 0xf5, 0x6c, 0x79, 0x49, 0xc6,
+       0xe8, 0xf1, 0x03, 0x56, 0x0d, 0xed, 0x2b, 0x79, 0x23, 0x10, 0x74, 0x32,
+       0xae, 0xcb, 0xec, 0x4c, 0x81, 0xff, 0x0b, 0x63, 0x2a, 0xec, 0x62, 0x73,
+       0x18, 0x6b, 0xfe, 0x25, 0x54, 0xfc, 0x1d, 0x6f, 0x87, 0x93, 0x30, 0xfd,
+       0x0c, 0x8d, 0x80, 0x6d, 0x3b, 0xf2, 0x53, 0x83, 0xfa, 0xdb, 0xb1, 0xbf,
+       0xbf, 0x9d, 0xd9, 0x8d, 0xcc, 0x3f, 0xfe, 0x7e, 0xeb, 0x8c, 0x1d, 0x1b,
+       0xb4, 0x62, 0x3d, 0xa4, 0x73, 0x05, 0x73, 0xcf, 0x80, 0x23, 0x24, 0xb2,
+       0x06, 0x89, 0x01, 0xfe, 0x12, 0x98, 0x97, 0xe8, 0xb3, 0xdb, 0x16, 0x43,
+       0xfb, 0xa2, 0x3f, 0xa0, 0xd3, 0x0b, 0xb1, 0xa6, 0xe6, 0x2d, 0xd0, 0x2f,
+       0x55, 0x66, 0x2e, 0x53, 0x16, 0x95, 0xcc, 0x02, 0x65, 0x62, 0x38, 0xac,
+       0x07, 0xed, 0x89, 0xaf, 0x99, 0xdc, 0xc8, 0x57, 0x7b, 0x4d, 0xd0, 0x0e,
+       0x43, 0x53, 0x35, 0xbc, 0xdc, 0xab, 0xe1, 0xfd, 0xf5, 0x61, 0xcc, 0x85,
+       0x7c, 0x3a, 0x15, 0x60, 0x06, 0xe5, 0x31, 0x9b, 0xa3, 0xce, 0x36, 0x91,
+       0xe6, 0xf1, 0xd2, 0x3c, 0xf2, 0x21, 0x1b, 0xf2, 0xe3, 0x24, 0xe6, 0xa1,
+       0xf5, 0xe3, 0x99, 0x8b, 0xf6, 0xa3, 0xf6, 0x9b, 0xc2, 0x7a, 0x4d, 0x08,
+       0x33, 0xed, 0x50, 0x1a, 0xd2, 0x6b, 0xae, 0xac, 0x19, 0x13, 0x9f, 0x3a,
+       0xdb, 0xbc, 0xf5, 0x48, 0x7f, 0x5f, 0xa3, 0x9d, 0x7d, 0xa2, 0x0d, 0xa0,
+       0x53, 0x78, 0xe4, 0xba, 0x40, 0xfa, 0xd5, 0xe1, 0x78, 0x73, 0xe0, 0xb8,
+       0xf9, 0x34, 0x4e, 0x1d, 0xef, 0x5c, 0xa7, 0x61, 0x9f, 0x4c, 0xc0, 0xc3,
+       0x7b, 0x89, 0x7f, 0x9c, 0xa9, 0x1a, 0xbb, 0x3b, 0x03, 0xc7, 0xb1, 0x37,
+       0xa5, 0x2c, 0xac, 0xef, 0xd5, 0x97, 0x44, 0xf8, 0xc7, 0xf5, 0x37, 0x1a,
+       0xd9, 0x27, 0x40, 0x87, 0xff, 0x68, 0x64, 0x54, 0x9e, 0x69, 0xb4, 0xd0,
+       0xfa, 0xff, 0xd9, 0x98, 0x40, 0xe5, 0x1f, 0x1b, 0x15, 0xaa, 0x3f, 0xdb,
+       0x98, 0x4e, 0xe5, 0x40, 0xa3, 0x95, 0xea, 0x3f, 0x6a, 0x9c, 0x43, 0xe5,
+       0xbd, 0xcb, 0x22, 0x72, 0x90, 0xff, 0xeb, 0x3b, 0xe7, 0xb1, 0x4f, 0x8c,
+       0x1c, 0xed, 0x37, 0xe1, 0x7f, 0x4e, 0x8f, 0xce, 0x31, 0x10, 0x00, 0xf7,
+       0xcf, 0x1b, 0x9b, 0x8f, 0xf6, 0x0b, 0x3e, 0xea, 0x4f, 0x1e, 0xbb, 0xdd,
+       0x8b, 0xed, 0xb8, 0xcf, 0xef, 0x73, 0x7a, 0x0e, 0x3e, 0xc8, 0xdc, 0x2d,
+       0xc9, 0xc4, 0x97, 0x1b, 0x2c, 0x31, 0xa3, 0xe9, 0x0f, 0xe7, 0x33, 0xe1,
+       0xf9, 0x06, 0x23, 0xd8, 0x12, 0x0f, 0xe0, 0xe9, 0x58, 0x8e, 0x44, 0xf3,
+       0x0f, 0x4e, 0xe2, 0x70, 0xb3, 0x55, 0x47, 0xf3, 0xd9, 0x35, 0x6c, 0x07,
+       0x8e, 0x3f, 0x96, 0xa3, 0xe7, 0xf3, 0x4f, 0xd7, 0x54, 0x62, 0xbb, 0x3d,
+       0x86, 0xcf, 0xdb, 0x9f, 0x06, 0x30, 0xec, 0xa7, 0x68, 0xce, 0xbc, 0x17,
+       0x11, 0x4f, 0xf6, 0x38, 0xa8, 0xcf, 0xf2, 0xc3, 0xfd, 0xb7, 0xf3, 0x76,
+       0xfb, 0x64, 0x5e, 0xaf, 0xee, 0x57, 0x6d, 0xaf, 0xb3, 0x59, 0x68, 0x5e,
+       0x95, 0xee, 0x83, 0x3a, 0x58, 0x3f, 0x83, 0xf8, 0x9d, 0xe6, 0x57, 0xfb,
+       0x7f, 0x96, 0xc7, 0xe5, 0x30, 0xb4, 0xbf, 0x3b, 0x55, 0x53, 0xe4, 0x1e,
+       0x03, 0x1f, 0x1a, 0x1b, 0xef, 0x4f, 0x72, 0x01, 0xf8, 0x70, 0xa1, 0x1c,
+       0x24, 0x07, 0xc8, 0x45, 0x9d, 0x42, 0x72, 0xa1, 0xf2, 0xa1, 0xca, 0x7f,
+       0xbb, 0x6d, 0x1c, 0x8f, 0xa9, 0x06, 0xc1, 0xe7, 0xe1, 0x20, 0x07, 0x31,
+       0x24, 0x07, 0x34, 0x2e, 0x31, 0x1e, 0xe4, 0x40, 0x22, 0xbc, 0xd8, 0x19,
+       0x9c, 0x67, 0xaf, 0x24, 0xe4, 0x25, 0x54, 0x1e, 0xa0, 0x44, 0x3d, 0xae,
+       0xca, 0x83, 0x2a, 0x07, 0x2a, 0xbf, 0x27, 0x82, 0x9c, 0x49, 0x31, 0xfe,
+       0x73, 0x7c, 0x2f, 0x84, 0x5f, 0xd5, 0xf2, 0x94, 0x95, 0xd3, 0xa5, 0x37,
+       0x2e, 0xe2, 0x17, 0x44, 0xd7, 0x6e, 0x9d, 0x05, 0x54, 0x21, 0xf4, 0x07,
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+       0x26, 0xd8, 0x48, 0xe7, 0x8b, 0x7e, 0x55, 0x59, 0xdc, 0x1f, 0x2f, 0xd4,
+       0x3b, 0x52, 0xd1, 0x2e, 0xf4, 0x99, 0x95, 0x08, 0xe4, 0xe3, 0x47, 0x8b,
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+       0xfd, 0x78, 0xfd, 0xf2, 0x2c, 0x9e, 0x2f, 0x3a, 0xed, 0x7e, 0xff, 0x5e,
+       0xf4, 0x53, 0xfa, 0xd2, 0xc3, 0xad, 0x48, 0x97, 0x1e, 0x3d, 0xa3, 0xf8,
+       0xb6, 0x06, 0xe8, 0x8a, 0xf6, 0xa0, 0xaf, 0x3b, 0xb1, 0x19, 0xf1, 0xa0,
+       0xae, 0xb7, 0x3c, 0x4b, 0xc4, 0xc9, 0xe9, 0x1a, 0xa2, 0xab, 0xaf, 0x53,
+       0x27, 0xfa, 0x2d, 0x6b, 0x65, 0x41, 0xfd, 0x78, 0xfc, 0x7c, 0x75, 0x6f,
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+       0xfe, 0x2a, 0x05, 0x9e, 0x6b, 0x75, 0xde, 0xb8, 0xb8, 0x00, 0x7e, 0xad,
+       0xed, 0x1a, 0x91, 0x17, 0x33, 0xf1, 0x77, 0x97, 0x2a, 0x1f, 0x0a, 0xd1,
+       0x53, 0xa5, 0x63, 0x5f, 0x3a, 0xf7, 0xdb, 0xfa, 0x12, 0x0c, 0x6e, 0x8c,
+       0x17, 0x6b, 0x0f, 0xb5, 0x12, 0x5f, 0x8f, 0xce, 0xef, 0xf4, 0x26, 0xa3,
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+       0x14, 0xef, 0xf5, 0xb1, 0xa1, 0x0a, 0x34, 0xfe, 0x4e, 0xf4, 0x83, 0xa3,
+       0x50, 0xef, 0xfe, 0xf1, 0x19, 0x5c, 0x77, 0xb8, 0x1d, 0xfc, 0x3d, 0x58,
+       0xd7, 0x69, 0xec, 0x5c, 0x74, 0x1e, 0xfc, 0xac, 0x61, 0x2b, 0x08, 0x0a,
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+       0xc2, 0x3f, 0xfd, 0x54, 0x71, 0xe4, 0xc9, 0x60, 0x5f, 0x9d, 0xeb, 0x35,
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+       0xe4, 0x9f, 0x20, 0xbf, 0xd6, 0x9e, 0x92, 0x2d, 0x46, 0xf4, 0x43, 0x21,
+       0x6e, 0x21, 0xb8, 0x8d, 0xfb, 0x05, 0x75, 0x9e, 0xe4, 0x7f, 0x9a, 0x8b,
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+       0xd4, 0xb8, 0xed, 0x44, 0xd6, 0x88, 0xff, 0x30, 0x13, 0xe3, 0x8f, 0x02,
+       0x79, 0x6e, 0x3c, 0xca, 0xc1, 0x07, 0x82, 0x9e, 0x6a, 0x3c, 0xb2, 0x76,
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+       0x4f, 0xf5, 0xc7, 0x0f, 0x57, 0xe1, 0x7e, 0xdd, 0xb5, 0x61, 0x56, 0x8a,
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+       0xc6, 0xfd, 0x23, 0xc6, 0xf1, 0x3a, 0xd8, 0xc9, 0xf9, 0xbb, 0x5e, 0x27,
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+       0xc0, 0xee, 0x31, 0xb6, 0x9e, 0xfa, 0xab, 0xf3, 0x83, 0x26, 0xe1, 0xe3,
+       0x6f, 0x35, 0xbf, 0x05, 0xe6, 0x37, 0xfb, 0xe7, 0x07, 0x7c, 0x47, 0x21,
+       0xbe, 0x3f, 0xcf, 0xb1, 0x92, 0x3d, 0x4e, 0x5a, 0xcc, 0x58, 0x2f, 0xc9,
+       0x63, 0x03, 0xc9, 0xa3, 0x7a, 0x9e, 0xab, 0xc0, 0x67, 0x98, 0x8f, 0xc5,
+       0x9c, 0x09, 0xd2, 0xad, 0x76, 0xd7, 0xeb, 0x94, 0x07, 0x76, 0xb2, 0x5e,
+       0x8a, 0x47, 0x0a, 0x23, 0xf9, 0x3e, 0x0a, 0x71, 0x3f, 0x08, 0x87, 0xf1,
+       0x92, 0x65, 0x73, 0x7c, 0xd9, 0xb3, 0xb9, 0xfe, 0x58, 0x9b, 0x1d, 0x6c,
+       0x97, 0xbb, 0xb2, 0xed, 0x52, 0x36, 0x94, 0x3b, 0xb2, 0x1d, 0xba, 0x6c,
+       0xd2, 0x67, 0x16, 0xe2, 0xcb, 0xb5, 0x82, 0x57, 0xc0, 0x4f, 0x89, 0x1f,
+       0x18, 0x43, 0xef, 0xae, 0x79, 0x97, 0xc7, 0x55, 0x9f, 0x83, 0x1c, 0xa0,
+       0x9c, 0xdf, 0xdf, 0x20, 0x29, 0xa9, 0x41, 0x7e, 0x10, 0xe7, 0xef, 0x7a,
+       0x5e, 0xc5, 0xae, 0x30, 0x4f, 0xff, 0x5c, 0xc4, 0x83, 0xcb, 0xde, 0x9b,
+       0x1e, 0x87, 0x71, 0x14, 0x97, 0xab, 0xe5, 0xeb, 0x4c, 0x4a, 0x6a, 0x00,
+       0x9f, 0xd6, 0x23, 0x9f, 0x03, 0x5e, 0x2a, 0x2d, 0x55, 0x3f, 0x42, 0xbf,
+       0xdb, 0xb1, 0x2e, 0x4e, 0xc1, 0x7c, 0x7f, 0x3d, 0xf2, 0xfd, 0x74, 0x44,
+       0x23, 0xe7, 0xeb, 0x58, 0xf8, 0x87, 0xf1, 0xc5, 0x28, 0x3e, 0xf7, 0x04,
+       0xc3, 0xf0, 0xb7, 0x0b, 0xf9, 0xab, 0x8e, 0x19, 0xac, 0x68, 0x47, 0xea,
+       0x3b, 0x43, 0xdb, 0xad, 0x5a, 0xcc, 0xeb, 0xa4, 0x64, 0x83, 0x1c, 0x84,
+       0xfb, 0xe5, 0x20, 0x49, 0xf0, 0x65, 0xb3, 0x43, 0x72, 0xa3, 0xde, 0x6f,
+       0xbe, 0xa1, 0xe5, 0x79, 0xac, 0x52, 0x89, 0xf2, 0x56, 0xf7, 0x40, 0x25,
+       0xf2, 0x25, 0xfd, 0x61, 0xbf, 0xca, 0x79, 0x6e, 0x9c, 0xff, 0x1e, 0x00,
+       0x31, 0x1e, 0x62, 0xdb, 0x63, 0x49, 0x6e, 0xa8, 0x11, 0xf4, 0xc8, 0xdf,
+       0x8b, 0xf3, 0xde, 0xa3, 0xf5, 0xbe, 0x8e, 0x72, 0x7c, 0x52, 0xe7, 0x49,
+       0xc6, 0x7c, 0xca, 0x49, 0xa7, 0xd1, 0x8a, 0xf3, 0x2f, 0x65, 0xe0, 0x70,
+       0x80, 0x7e, 0x29, 0x65, 0xbd, 0x54, 0xf6, 0x87, 0xd7, 0x75, 0x78, 0x69,
+       0x72, 0xd7, 0x54, 0x8c, 0x9b, 0x3f, 0x70, 0x18, 0x28, 0x8f, 0xd3, 0xbc,
+       0xa1, 0x25, 0x02, 0xf5, 0x69, 0x26, 0xdb, 0x60, 0xb9, 0x90, 0x8e, 0xc6,
+       0x9d, 0x1d, 0xb8, 0x99, 0x3d, 0xbe, 0x5f, 0x01, 0x8c, 0xc4, 0x2e, 0xa8,
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+       0xcf, 0xcb, 0xce, 0x1d, 0x7f, 0x7c, 0xcd, 0x1f, 0x3a, 0xee, 0xc2, 0x90,
+       0xa2, 0xe6, 0x17, 0xad, 0xfa, 0x78, 0xce, 0x36, 0xbd, 0xe9, 0x79, 0x7e,
+       0xfa, 0xd5, 0x33, 0x4f, 0x3a, 0xee, 0x57, 0xa5, 0xd7, 0x08, 0xfd, 0x60,
+       0xcf, 0x53, 0x00, 0x0f, 0x4b, 0xd8, 0x50, 0x1e, 0xc6, 0x35, 0x2a, 0xdd,
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+       0x06, 0x1d, 0xcf, 0x73, 0x35, 0xbc, 0xb7, 0x14, 0xfa, 0xdf, 0xb7, 0x41,
+       0xa3, 0xa0, 0x7f, 0x38, 0x8a, 0xbe, 0xb7, 0xa0, 0x83, 0xd7, 0xc4, 0x9b,
+       0xbc, 0x11, 0x12, 0xc5, 0x9b, 0xe3, 0xd1, 0x45, 0xa5, 0x87, 0x4a, 0x9f,
+       0x33, 0xd1, 0x7c, 0xdc, 0x99, 0xfb, 0x65, 0xca, 0xd3, 0xfd, 0x5f, 0xd3,
+       0xa5, 0x2b, 0xdb, 0xf1, 0xd0, 0xd7, 0xc9, 0x63, 0xa8, 0xfc, 0x8d, 0x27,
+       0x6f, 0xcb, 0xd7, 0x85, 0xc8, 0x65, 0x88, 0xfc, 0xa9, 0xf4, 0x72, 0xac,
+       0x8b, 0x24, 0x39, 0x53, 0xe9, 0x58, 0xab, 0x30, 0x8a, 0x5b, 0x6b, 0xbb,
+       0x23, 0xac, 0x6e, 0xe6, 0xa7, 0x9f, 0x19, 0xfe, 0x21, 0xfd, 0xf0, 0x9e,
+       0x82, 0xf2, 0x31, 0xed, 0x12, 0xdb, 0x29, 0x7d, 0x13, 0x39, 0x1c, 0xa0,
+       0x7b, 0x8d, 0x50, 0xfa, 0x00, 0x6f, 0xd8, 0x51, 0xaf, 0x3f, 0x95, 0x1d,
+       0x6c, 0x87, 0x54, 0xba, 0x8d, 0xa7, 0x7f, 0x54, 0xfd, 0xf5, 0x21, 0xf3,
+       0x9e, 0xb4, 0x48, 0x74, 0x3f, 0xc0, 0xe5, 0xf3, 0x97, 0x06, 0x37, 0xde,
+       0x2f, 0xaa, 0xf7, 0x03, 0xea, 0x3d, 0xc0, 0x61, 0xa1, 0xf7, 0x42, 0xcb,
+       0x0f, 0xc1, 0xef, 0xc0, 0x7b, 0x97, 0x2d, 0xe9, 0x7d, 0x13, 0xd1, 0x5f,
+       0xeb, 0xd7, 0xab, 0xf3, 0xf0, 0xfb, 0xc7, 0x0f, 0xd7, 0xf7, 0x4e, 0x5d,
+       0x0d, 0xe3, 0x3f, 0x9c, 0xc7, 0xcb, 0x7e, 0xf4, 0xd3, 0x02, 0x60, 0x7b,
+       0x18, 0xcf, 0xc3, 0x7d, 0x38, 0xc9, 0xe0, 0x42, 0xbc, 0x7d, 0x28, 0xcd,
+       0x9c, 0x8f, 0x76, 0xfc, 0x43, 0xe9, 0xa1, 0xbb, 0x38, 0x1c, 0xaf, 0x57,
+       0x10, 0x5e, 0x1a, 0x3f, 0xdf, 0x02, 0x70, 0xbf, 0x4e, 0xcd, 0xdb, 0x3d,
+       0x2a, 0xf4, 0xb0, 0x9b, 0xef, 0x63, 0xe9, 0xec, 0x7c, 0xea, 0x27, 0xb1,
+       0x37, 0x11, 0x1f, 0x8a, 0xc4, 0x4a, 0x68, 0x1d, 0x49, 0x8a, 0x29, 0x82,
+       0xfd, 0x7c, 0xf8, 0x8b, 0x19, 0x59, 0x4d, 0xcc, 0x7f, 0xfe, 0x96, 0x6c,
+       0xee, 0xcf, 0xba, 0x55, 0xfd, 0xae, 0xe6, 0xb1, 0xff, 0x41, 0xa2, 0x3c,
+       0xf6, 0x72, 0x30, 0x01, 0x16, 0xcc, 0xb7, 0xcf, 0x7f, 0xb6, 0x68, 0x3a,
+       0xd4, 0x9f, 0xfd, 0xc7, 0x14, 0x1b, 0xdd, 0xff, 0xad, 0x09, 0x5e, 0x1f,
+       0xed, 0x68, 0x32, 0xe5, 0x07, 0xb7, 0xd1, 0x3c, 0xdf, 0xff, 0x6a, 0x48,
+       0xb7, 0x22, 0xc3, 0xbf, 0xaf, 0x11, 0xfb, 0x97, 0x7f, 0x8d, 0xd7, 0x97,
+       0xcf, 0xa0, 0x78, 0xa2, 0x52, 0xd0, 0xd0, 0x1e, 0x33, 0x93, 0xc7, 0xb1,
+       0xee, 0x94, 0x28, 0xb4, 0x47, 0xaa, 0x7d, 0x1a, 0x3e, 0x75, 0xd8, 0x1c,
+       0x98, 0xbf, 0xbc, 0x04, 0xf6, 0x8b, 0xe9, 0x03, 0xe0, 0x99, 0x4f, 0x26,
+       0x05, 0xda, 0xb7, 0xd7, 0xf7, 0xfd, 0x3a, 0x0d, 0xe7, 0xa9, 0xd4, 0xbb,
+       0x32, 0xad, 0x18, 0x4f, 0x36, 0x3f, 0x9f, 0x84, 0x7e, 0x40, 0xe5, 0xbe,
+       0xc7, 0xd3, 0xc8, 0x2f, 0xdd, 0xb7, 0x39, 0x0d, 0xe3, 0x8b, 0xca, 0x96,
+       0x5f, 0xa7, 0xd9, 0x09, 0x0e, 0x77, 0x50, 0x7c, 0xa3, 0xe5, 0xe7, 0xbe,
+       0x72, 0xf0, 0xce, 0x3d, 0x5b, 0x02, 0xfc, 0xe0, 0xea, 0x5c, 0x99, 0xf6,
+       0x5f, 0x6a, 0x7c, 0xbd, 0x00, 0xfd, 0xd3, 0x45, 0x77, 0x7c, 0xf6, 0x18,
+       0xe6, 0xc3, 0x67, 0xfc, 0xa3, 0x44, 0x79, 0xb1, 0xfb, 0x59, 0xef, 0x63,
+       0x68, 0x37, 0xcb, 0xd2, 0xb9, 0x1c, 0xb1, 0xed, 0x46, 0xd2, 0xeb, 0x30,
+       0x1f, 0xdd, 0x3b, 0xb6, 0xce, 0xfc, 0xf1, 0x5e, 0xd4, 0xe7, 0xa7, 0xd3,
+       0x3f, 0xd6, 0x95, 0x43, 0xbf, 0xeb, 0xd9, 0x5a, 0xc2, 0x4f, 0x19, 0x73,
+       0x3f, 0x11, 0x8f, 0xf9, 0xb0, 0x4d, 0x12, 0xe5, 0xc3, 0xfc, 0xfd, 0xa7,
+       0xd2, 0x3d, 0xe6, 0x8a, 0x0d, 0x92, 0x3e, 0x21, 0x16, 0xed, 0x61, 0xb4,
+       0x4d, 0x56, 0x70, 0x5c, 0x34, 0xed, 0xe3, 0x81, 0x4d, 0xb6, 0x1e, 0xac,
+       0x2f, 0x7b, 0x98, 0xd7, 0x2f, 0x32, 0xb8, 0xdb, 0xfb, 0x70, 0x9e, 0x67,
+       0xf5, 0xd6, 0x56, 0x05, 0x27, 0x2a, 0x99, 0x5e, 0x12, 0x70, 0x2f, 0x7c,
+       0x3d, 0x9b, 0xc7, 0x5d, 0xcb, 0x9f, 0x90, 0xc8, 0x1f, 0x57, 0xd7, 0x99,
+       0xf1, 0x4c, 0x5c, 0x73, 0xe0, 0x39, 0xaf, 0x0b, 0xfa, 0xb3, 0x1b, 0xff,
+       0x46, 0xfa, 0xed, 0x27, 0x82, 0x2e, 0x3f, 0x7a, 0xf8, 0xfd, 0x37, 0x13,
+       0x14, 0xbc, 0x4f, 0x72, 0xdc, 0x44, 0x3d, 0xf2, 0xde, 0xd3, 0x17, 0x52,
+       0x51, 0x7f, 0xe5, 0xc7, 0x5c, 0xca, 0x40, 0x3e, 0x9f, 0xa1, 0x77, 0xec,
+       0xac, 0xc2, 0x73, 0xb7, 0x18, 0x28, 0x7f, 0x98, 0x93, 0x99, 0x28, 0xc7,
+       0x43, 0xff, 0xac, 0x9f, 0xcf, 0x7b, 0x0a, 0xcb, 0xe5, 0x0f, 0xaf, 0xd8,
+       0x59, 0x85, 0x79, 0xd0, 0x1d, 0x46, 0x8a, 0xa3, 0xd4, 0xfd, 0xad, 0x91,
+       0x14, 0x0d, 0xc6, 0x9b, 0x6f, 0x34, 0xff, 0xec, 0x01, 0xc4, 0xdb, 0xc5,
+       0xa7, 0x8d, 0xe4, 0x47, 0xaf, 0x69, 0xbe, 0x2d, 0x9e, 0x8d, 0x21, 0xa7,
+       0x6a, 0xb9, 0x1f, 0xe8, 0xaf, 0xa4, 0x31, 0xf6, 0x52, 0xa3, 0x91, 0xca,
+       0x97, 0x1b, 0x2d, 0x4c, 0x81, 0x23, 0x1e, 0x6c, 0x4c, 0x20, 0xf8, 0x5f,
+       0x1b, 0x15, 0x2a, 0xd9, 0x12, 0xce, 0x5f, 0x6b, 0x44, 0xbc, 0x3a, 0xde,
+       0x7c, 0xd9, 0x10, 0xef, 0x2b, 0xa0, 0xaf, 0x72, 0x36, 0xc1, 0x7c, 0xe0,
+       0x6f, 0xda, 0x4c, 0xf6, 0xc9, 0x39, 0x80, 0xaf, 0x19, 0xb7, 0x3b, 0x5b,
+       0x36, 0x8b, 0x73, 0xcd, 0x80, 0xf1, 0x36, 0x57, 0xf2, 0x02, 0xc4, 0x43,
+       0xce, 0xe6, 0xd5, 0x3d, 0xe8, 0x8a, 0xea, 0x73, 0x78, 0x7c, 0xf4, 0x76,
+       0xdf, 0xa6, 0x24, 0xf2, 0xa3, 0x1f, 0x3e, 0xb7, 0xbb, 0x0a, 0xda, 0x17,
+       0xe7, 0x94, 0xa4, 0xe0, 0x78, 0xe3, 0xae, 0x6b, 0x14, 0xe7, 0xbf, 0xd1,
+       0xf5, 0x78, 0x19, 0xe5, 0xf5, 0x5b, 0x0c, 0xfc, 0x7c, 0xe2, 0xdc, 0x17,
+       0x9f, 0x4e, 0x8b, 0xdf, 0x89, 0x79, 0xd7, 0xb7, 0x74, 0x14, 0x7f, 0xd7,
+       0xef, 0x3a, 0xb7, 0x7b, 0x33, 0x94, 0x2b, 0x9f, 0x58, 0xad, 0x0f, 0xe4,
+       0xf7, 0x6f, 0x7a, 0xde, 0x64, 0xb1, 0x9f, 0x5b, 0xc9, 0xd5, 0x78, 0x78,
+       0xf8, 0xf6, 0x72, 0xf5, 0xeb, 0x24, 0x92, 0x9f, 0x16, 0x90, 0xab, 0x8c,
+       0xbf, 0x5e, 0xae, 0xea, 0x1f, 0x5e, 0x4f, 0xf8, 0x7b, 0x28, 0xa7, 0x64,
+       0x51, 0x0e, 0xec, 0xff, 0xa2, 0xce, 0x95, 0x84, 0xf2, 0x74, 0x71, 0xe6,
+       0xf7, 0x88, 0xcf, 0x5d, 0xc7, 0x25, 0xc2, 0xbf, 0xaa, 0xc7, 0xd5, 0xf1,
+       0x45, 0xe2, 0xbc, 0x35, 0x1a, 0xcf, 0x13, 0xe4, 0x0f, 0x0a, 0x3d, 0xfe,
+       0x25, 0x44, 0x7e, 0x88, 0xdf, 0xd7, 0xbb, 0x3e, 0x4d, 0x43, 0x7f, 0xf8,
+       0xcb, 0xce, 0xa5, 0x5f, 0x7b, 0xee, 0x23, 0x8d, 0x78, 0x83, 0x8e, 0x79,
+       0x2d, 0x23, 0x95, 0xa1, 0xed, 0x79, 0x7a, 0x47, 0x8a, 0x15, 0xce, 0x97,
+       0xa7, 0xe1, 0x7e, 0xf0, 0x28, 0xff, 0x55, 0xdc, 0xcf, 0xa9, 0xf7, 0xed,
+       0xf8, 0x87, 0x79, 0xe1, 0x5a, 0x61, 0x3f, 0x9d, 0xb0, 0xb1, 0xa8, 0x18,
+       0xb4, 0x7f, 0x92, 0x37, 0x2c, 0x13, 0xef, 0x39, 0x7e, 0x78, 0x49, 0x8b,
+       0xf1, 0x17, 0xc4, 0x75, 0x1f, 0x05, 0xfb, 0x97, 0xec, 0xa3, 0x00, 0x3b,
+       0x3e, 0xde, 0x7e, 0x6f, 0x55, 0xd6, 0xe1, 0x3c, 0x5a, 0xbf, 0xde, 0x9d,
+       0x7d, 0x46, 0xc3, 0xbc, 0x01, 0x76, 0xfb, 0xce, 0x81, 0x30, 0xe6, 0x0d,
+       0x58, 0x77, 0x24, 0xee, 0x30, 0x22, 0x4f, 0x43, 0x1c, 0xda, 0x35, 0x89,
+       0xf4, 0x02, 0xd2, 0x0d, 0xef, 0x65, 0x7c, 0x5d, 0x33, 0x5b, 0x10, 0xbe,
+       0xa4, 0xe7, 0x74, 0xf4, 0x1d, 0x81, 0xf8, 0x8a, 0xe7, 0x55, 0x98, 0x9c,
+       0xe7, 0x3f, 0xe7, 0xa5, 0xae, 0x2b, 0x99, 0xa8, 0x67, 0x43, 0xcf, 0x5b,
+       0x77, 0xf4, 0x0a, 0xf1, 0x47, 0x6d, 0xe7, 0xe3, 0xd7, 0x24, 0x3a, 0xff,
+       0xc2, 0x4b, 0xda, 0xcc, 0x5b, 0x9f, 0xff, 0xf5, 0x7d, 0x57, 0x32, 0x91,
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+       0x87, 0xba, 0x63, 0x5c, 0x9f, 0x7f, 0x5b, 0x3c, 0xa8, 0xf5, 0x55, 0x9b,
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+       0xe7, 0xdb, 0xc9, 0xfc, 0xe3, 0x2f, 0xb7, 0xe9, 0xbc, 0x7a, 0xc0, 0x51,
+       0x95, 0x81, 0x6d, 0xc0, 0xf7, 0xc1, 0xaa, 0x3c, 0x54, 0x27, 0xfe, 0xb0,
+       0x08, 0xcf, 0x57, 0xad, 0x69, 0x4e, 0x43, 0x7f, 0xa5, 0x2a, 0x7b, 0xa0,
+       0x0c, 0xe5, 0xe2, 0x92, 0x89, 0x19, 0x13, 0xa0, 0xdf, 0xdb, 0xc2, 0x5e,
+       0x55, 0xb7, 0xaf, 0x5f, 0x8c, 0x7e, 0xef, 0x78, 0xfb, 0xf9, 0x8b, 0xb0,
+       0x3f, 0x5f, 0x0a, 0x39, 0xfc, 0xb2, 0xd3, 0xe4, 0x0e, 0xbc, 0x1f, 0x0c,
+       0x2d, 0xff, 0xd8, 0xc8, 0x94, 0x77, 0x02, 0xde, 0x0d, 0xdf, 0xdf, 0x60,
+       0x20, 0xdf, 0x5d, 0x9d, 0xef, 0x6d, 0xbd, 0xa7, 0x16, 0xe3, 0xb3, 0xba,
+       0x18, 0xae, 0x3f, 0xce, 0x42, 0xff, 0x36, 0xd0, 0x63, 0x37, 0x84, 0xde,
+       0x5b, 0xbe, 0x2e, 0xb8, 0xff, 0xb5, 0xdc, 0x18, 0xfe, 0x2e, 0x55, 0x3f,
+       0x90, 0x86, 0x76, 0x4f, 0x9d, 0xdf, 0x97, 0xab, 0xea, 0xb5, 0x81, 0x34,
+       0xd4, 0x57, 0xa1, 0xe3, 0x8a, 0x65, 0xa1, 0x6f, 0x5e, 0x96, 0x48, 0xdf,
+       0x54, 0xb7, 0x4b, 0xe7, 0x64, 0xc0, 0x53, 0xb5, 0xd1, 0xe5, 0xc6, 0xf7,
+       0x3b, 0xd5, 0x18, 0x4c, 0xf2, 0x73, 0x6a, 0x6f, 0x4a, 0x7c, 0x5c, 0x42,
+       0x9e, 0xc0, 0x3b, 0x8c, 0x7d, 0x3c, 0x2f, 0x99, 0xce, 0x5d, 0xdd, 0x66,
+       0xb2, 0x9b, 0x60, 0x5c, 0x4d, 0xd8, 0x40, 0x24, 0xfa, 0x43, 0xb5, 0x11,
+       0x03, 0x91, 0xe8, 0xe7, 0xf8, 0x8e, 0xca, 0xac, 0x45, 0x90, 0x2b, 0x36,
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+       0x65, 0x20, 0x0f, 0xf9, 0xb4, 0x72, 0x57, 0xf0, 0x38, 0x3c, 0x97, 0x25,
+       0x40, 0xfe, 0x7c, 0x9d, 0x7b, 0xe2, 0x02, 0xe3, 0xf1, 0x64, 0xb1, 0xef,
+       0x41, 0xe9, 0x1c, 0xc9, 0xc9, 0xe0, 0x9f, 0x3f, 0x4a, 0x42, 0xba, 0x57,
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+       0xa4, 0x84, 0xf4, 0x81, 0x4f, 0x37, 0x40, 0x7a, 0xed, 0x44, 0xde, 0xbd,
+       0xa4, 0xc7, 0x7c, 0xd1, 0x03, 0x65, 0xa8, 0xa7, 0xde, 0x3d, 0x52, 0xc1,
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+       0x64, 0xef, 0xff, 0x2b, 0xcf, 0x49, 0xfa, 0xa3, 0x58, 0xe6, 0xef, 0x1b,
+       0xd8, 0x1e, 0x9d, 0x85, 0xe7, 0x81, 0x36, 0xf5, 0x37, 0x52, 0x5c, 0xa1,
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+       0x65, 0xbf, 0xdc, 0xf8, 0x98, 0x72, 0xb0, 0x1d, 0xe5, 0xb0, 0xd2, 0x4c,
+       0xf9, 0x1c, 0xf0, 0x9f, 0xda, 0x5e, 0x41, 0x3f, 0x6f, 0x69, 0x9c, 0x15,
+       0xf3, 0xe2, 0x95, 0x38, 0x8e, 0xf3, 0x81, 0x3e, 0xf0, 0xfe, 0x2f, 0x36,
+       0xe6, 0x7a, 0x05, 0xd2, 0x67, 0x59, 0x94, 0xa3, 0x20, 0x2f, 0x17, 0xef,
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+       0x8a, 0x23, 0x07, 0x75, 0x43, 0xfb, 0x50, 0x4f, 0x65, 0x46, 0x39, 0x16,
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+       0xd0, 0x83, 0xf7, 0x7e, 0x8b, 0x64, 0xae, 0x8f, 0xd8, 0x7e, 0xce, 0x57,
+       0xbe, 0x8c, 0x3d, 0xfc, 0x3b, 0x09, 0x71, 0x7f, 0xb8, 0x54, 0xe0, 0x1f,
+       0xec, 0x16, 0x6b, 0x46, 0xbe, 0x90, 0x38, 0x7d, 0xdf, 0xe8, 0x3c, 0xfc,
+       0x0e, 0xea, 0x15, 0x5f, 0x6f, 0x0a, 0xe9, 0xe3, 0x50, 0xb9, 0xb9, 0xd4,
+       0xf9, 0x54, 0x24, 0xea, 0x87, 0x33, 0x60, 0xc7, 0x5d, 0x01, 0x71, 0xfe,
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+       0xea, 0x91, 0x0f, 0xb7, 0x07, 0xc3, 0xa1, 0x7c, 0x84, 0xfc, 0xe8, 0x0d,
+       0xd2, 0x3b, 0x2e, 0x92, 0xa7, 0x67, 0x73, 0xb9, 0x1f, 0x56, 0x33, 0xbf,
+       0xb7, 0x0e, 0xf1, 0x30, 0x02, 0xdf, 0x0d, 0xb0, 0x1c, 0x00, 0x9f, 0x08,
+       0x81, 0x43, 0xfa, 0xb3, 0x12, 0xee, 0x27, 0x3c, 0x8b, 0xff, 0x8d, 0x78,
+       0x9c, 0xea, 0xed, 0xa7, 0xf8, 0xfc, 0x20, 0x7f, 0x17, 0xdb, 0x04, 0xf6,
+       0x8b, 0xe0, 0x8e, 0x70, 0xba, 0x37, 0xd6, 0x1c, 0x04, 0xfb, 0x14, 0xcb,
+       0xed, 0x13, 0xda, 0x85, 0x9a, 0xc8, 0x5e, 0xca, 0x4b, 0xf9, 0x3a, 0x0c,
+       0x74, 0x3f, 0xf2, 0x68, 0xd7, 0xa7, 0xf4, 0x9e, 0x11, 0xf8, 0x90, 0xf2,
+       0x2f, 0x35, 0x5d, 0xaf, 0xc6, 0x61, 0xdc, 0x7e, 0x00, 0xe3, 0x84, 0x5c,
+       0xb2, 0x83, 0x71, 0xf4, 0x4e, 0xa5, 0xa3, 0x2b, 0x0e, 0xe3, 0x0d, 0xb5,
+       0xbe, 0x56, 0xe3, 0x49, 0x13, 0xef, 0xf1, 0xc9, 0x4f, 0x57, 0xeb, 0x9d,
+       0xb2, 0x37, 0x0d, 0xf7, 0x5f, 0x23, 0xf5, 0x66, 0x62, 0xfb, 0x01, 0xb1,
+       0xef, 0x5a, 0x0d, 0xc0, 0x32, 0xc2, 0x62, 0xdf, 0x12, 0x97, 0x77, 0xd6,
+       0x25, 0x93, 0x3e, 0x0f, 0xa5, 0xdb, 0x0e, 0xc1, 0xaf, 0xa0, 0x17, 0x32,
+       0xe9, 0x9d, 0xc5, 0x51, 0x9e, 0x17, 0x50, 0xf5, 0x40, 0x95, 0xd0, 0x27,
+       0x27, 0xb0, 0x3e, 0x83, 0xcb, 0xbd, 0x45, 0xbd, 0x57, 0x92, 0xf0, 0xbd,
+       0x5c, 0xf8, 0x98, 0xfa, 0x21, 0x3e, 0x4f, 0xe8, 0x37, 0xd6, 0x40, 0x79,
+       0x9b, 0xed, 0x79, 0x7c, 0xdf, 0xea, 0x78, 0x9a, 0x97, 0xe7, 0x95, 0xa8,
+       0xbd, 0xee, 0xd8, 0x95, 0xcc, 0xe9, 0x19, 0x38, 0x4e, 0x19, 0x79, 0x07,
+       0x39, 0xa2, 0x87, 0x52, 0xfc, 0x7a, 0x05, 0xe5, 0x3f, 0x81, 0xe4, 0xff,
+       0x51, 0x5d, 0x1c, 0x9c, 0xab, 0x7a, 0xb7, 0x64, 0x6d, 0x42, 0x3d, 0x55,
+       0xba, 0xbe, 0x10, 0xba, 0xb3, 0x55, 0xda, 0xd5, 0x85, 0x94, 0x2f, 0x13,
+       0xef, 0x3f, 0x43, 0xf7, 0x15, 0xca, 0x47, 0x56, 0xd8, 0x0b, 0xe9, 0x49,
+       0x4d, 0x74, 0x41, 0x6c, 0xc0, 0x7c, 0x97, 0x21, 0x5c, 0x4f, 0xc8, 0x22,
+       0x3d, 0x43, 0xef, 0xe8, 0x1f, 0x8c, 0x7d, 0xb2, 0x10, 0xf3, 0x13, 0x3f,
+       0x2b, 0xdd, 0x46, 0xfc, 0x3c, 0x62, 0x6f, 0x02, 0xe5, 0x1c, 0xcf, 0xb3,
+       0x8b, 0xeb, 0x71, 0x14, 0x9b, 0x9b, 0x9a, 0xd1, 0x7c, 0xbc, 0xaa, 0xa1,
+       0x79, 0x63, 0xfc, 0x18, 0xfb, 0x08, 0xdd, 0x67, 0x95, 0xa3, 0xb9, 0x30,
+       0x4e, 0x19, 0x5d, 0xaf, 0xee, 0xf7, 0xb2, 0x49, 0xdd, 0xdf, 0x7c, 0xdd,
+       0xc4, 0x40, 0x3c, 0x2c, 0x59, 0x5f, 0x38, 0x11, 0xca, 0x55, 0xc6, 0xbf,
+       0x16, 0x0f, 0xfc, 0xbc, 0x97, 0xbb, 0x0c, 0x5e, 0xb4, 0xab, 0x55, 0xa5,
+       0xab, 0x37, 0x46, 0x8d, 0xc1, 0x37, 0xa3, 0xec, 0xc1, 0xae, 0x00, 0xfb,
+       0x35, 0x1d, 0xe9, 0xeb, 0xa6, 0x7b, 0x8d, 0xf1, 0xf6, 0x1f, 0x5a, 0xd6,
+       0x4a, 0xde, 0x7e, 0xcc, 0x13, 0x31, 0x90, 0xab, 0x56, 0x92, 0x2f, 0x90,
+       0x97, 0x00, 0xbb, 0x30, 0x27, 0x2f, 0x24, 0xdf, 0x50, 0xb9, 0x62, 0x1a,
+       0xc6, 0x9d, 0xcc, 0xb1, 0x62, 0x1a, 0xda, 0x19, 0x90, 0xab, 0x32, 0xeb,
+       0x18, 0x71, 0x25, 0x7e, 0x59, 0xa2, 0xa1, 0xb7, 0x1b, 0x2e, 0x2a, 0x43,
+       0xf7, 0x73, 0x3e, 0x8f, 0xe7, 0x49, 0xe7, 0xe4, 0x71, 0x79, 0xe9, 0xb6,
+       0xd9, 0x7d, 0xa8, 0x37, 0xc7, 0xfb, 0xde, 0xe2, 0xbf, 0xc5, 0x3e, 0xc6,
+       0xfb, 0xde, 0x22, 0x51, 0x33, 0xfc, 0x1e, 0xca, 0x5b, 0x62, 0x5c, 0x84,
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+       0xb2, 0x75, 0x36, 0x5f, 0x27, 0x3c, 0x87, 0xfb, 0x2d, 0xf5, 0xe9, 0xba,
+       0xaf, 0xcf, 0x0b, 0x65, 0x44, 0x8c, 0xe4, 0x85, 0xc8, 0x6f, 0xc8, 0x08,
+       0xa7, 0x7b, 0x12, 0x5f, 0xe7, 0xe7, 0x64, 0xb7, 0x06, 0xbb, 0x73, 0x2d,
+       0x78, 0x9f, 0xe1, 0xeb, 0x85, 0xe8, 0x10, 0xe4, 0xa9, 0xfe, 0xcf, 0xff,
+       0x1d, 0x87, 0xf6, 0xd5, 0xd7, 0xfd, 0x09, 0xbd, 0x07, 0xf3, 0xdd, 0xf8,
+       0x94, 0xde, 0x89, 0x6d, 0x16, 0xef, 0xf4, 0x4e, 0x74, 0x8a, 0x77, 0x56,
+       0xbd, 0x4a, 0x04, 0x7d, 0x17, 0x57, 0xf4, 0x71, 0x21, 0xf6, 0xdb, 0x22,
+       0x4a, 0x7f, 0x7e, 0x80, 0xe7, 0x89, 0xd5, 0x52, 0x8d, 0xff, 0x03, 0xe2,
+       0xdf, 0xc9, 0xb3, 0xc7, 0x8e, 0x7f, 0x63, 0x1c, 0xe6, 0xc0, 0xbc, 0x80,
+       0x12, 0x3f, 0x56, 0x1e, 0x25, 0x30, 0x2f, 0x90, 0xaa, 0xe5, 0x79, 0x01,
+       0x2c, 0x31, 0x2f, 0x90, 0x9a, 0xca, 0xf3, 0x02, 0x08, 0x63, 0x5e, 0x00,
+       0x4b, 0xcc, 0x0b, 0x60, 0x3d, 0xe6, 0x05, 0x10, 0xc6, 0xbc, 0x00, 0xc2,
+       0x98, 0x17, 0x40, 0x18, 0xf3, 0x02, 0x58, 0x62, 0x5e, 0x00, 0xeb, 0xbf,
+       0x10, 0xdf, 0x3f, 0x0c, 0x82, 0x62, 0xe2, 0xf9, 0x4a, 0x33, 0xe9, 0xf5,
+       0xb5, 0xf8, 0xbe, 0x1d, 0xf0, 0xb7, 0xf6, 0x38, 0xbf, 0x77, 0x5a, 0xdb,
+       0x2a, 0xd3, 0xfd, 0x2d, 0x7e, 0xff, 0x80, 0xf6, 0x6d, 0xd4, 0xbb, 0x99,
+       0x76, 0xf1, 0x6e, 0xc6, 0xb3, 0x8d, 0xee, 0xf1, 0xea, 0x3b, 0x64, 0x2b,
+       0x92, 0xa8, 0x5e, 0x37, 0x74, 0x12, 0xf3, 0x38, 0xf5, 0x87, 0x24, 0xeb,
+       0x7a, 0xd4, 0x2b, 0x8d, 0x4b, 0x68, 0xfd, 0xcd, 0xdd, 0xb9, 0x1f, 0x94,
+       0x62, 0x7d, 0xab, 0xce, 0xaa, 0x51, 0x88, 0x8f, 0x38, 0x1d, 0x9b, 0x25,
+       0x7a, 0xa7, 0x5f, 0xdd, 0xdd, 0x4a, 0x79, 0xa7, 0xfc, 0xf8, 0xe3, 0x7a,
+       0xaa, 0x6f, 0x93, 0x18, 0xe6, 0x49, 0xef, 0x35, 0xf0, 0x38, 0xd7, 0x29,
+       0x43, 0x6d, 0x16, 0xdd, 0x83, 0x92, 0x1f, 0xec, 0x34, 0xf4, 0x52, 0xfc,
+       0x51, 0x73, 0x40, 0x52, 0xca, 0x03, 0xdf, 0x69, 0xcc, 0xb9, 0x46, 0x7a,
+       0x40, 0xbd, 0x4f, 0xae, 0xe0, 0x4d, 0xcc, 0xe9, 0x31, 0x29, 0xe5, 0x63,
+       0xbc, 0x03, 0x19, 0x79, 0x77, 0x2e, 0xde, 0x4d, 0x57, 0xe0, 0x3d, 0x33,
+       0xbe, 0x17, 0x97, 0x6f, 0xd0, 0xbb, 0x7e, 0x27, 0x04, 0xa4, 0x13, 0x90,
+       0x0f, 0x77, 0xf0, 0xf7, 0xcf, 0x16, 0xf8, 0x47, 0xf2, 0x1e, 0xf2, 0xae,
+       0xa9, 0xba, 0xfb, 0xd0, 0x46, 0x7c, 0x0f, 0x15, 0x7a, 0xdf, 0x3c, 0xf2,
+       0x3d, 0x5d, 0xc8, 0xbd, 0x73, 0xd9, 0x6c, 0x71, 0xaf, 0x6c, 0xe3, 0xdf,
+       0x57, 0x14, 0x3d, 0x5d, 0x7e, 0xb0, 0x03, 0xd6, 0x1b, 0xde, 0x6a, 0x20,
+       0x7f, 0xa3, 0x21, 0xd7, 0xf1, 0x20, 0xf2, 0xd1, 0x49, 0x9d, 0x9d, 0xf2,
+       0x23, 0x27, 0x8f, 0x9b, 0x28, 0x2e, 0x3a, 0xbf, 0xed, 0xb6, 0xa0, 0xfc,
+       0xc8, 0x50, 0x96, 0xa3, 0x7a, 0x36, 0xe5, 0x9b, 0xa6, 0x50, 0xbe, 0x62,
+       0x8d, 0x4e, 0x22, 0x7b, 0xbc, 0xa0, 0x28, 0x25, 0x1e, 0xf1, 0xb8, 0xe0,
+       0x94, 0x8e, 0xec, 0x4e, 0x4f, 0x56, 0x49, 0x2d, 0xf6, 0x5b, 0x33, 0x4b,
+       0xa1, 0x7c, 0x54, 0x81, 0x81, 0xfd, 0x82, 0xe6, 0x11, 0xef, 0xa5, 0x54,
+       0x7a, 0x14, 0x34, 0x49, 0x6e, 0x0d, 0xc0, 0x2b, 0x98, 0x95, 0xde, 0xd9,
+       0x2f, 0x07, 0x34, 0x61, 0xbe, 0x72, 0x50, 0x67, 0xde, 0x84, 0xef, 0x9a,
+       0x96, 0x33, 0xfe, 0xce, 0x41, 0xe5, 0x9b, 0x35, 0xdb, 0x24, 0xe2, 0x1b,
+       0x4c, 0x10, 0x20, 0x3e, 0xcb, 0x04, 0x3e, 0x97, 0x77, 0xff, 0xfe, 0x3a,
+       0xbe, 0x63, 0x58, 0x69, 0xe0, 0x7e, 0x6b, 0xa2, 0x86, 0xdf, 0x5f, 0x27,
+       0x6e, 0xe1, 0xef, 0x19, 0x1e, 0x64, 0x0e, 0x3d, 0xda, 0xd9, 0x55, 0xc8,
+       0x5d, 0x32, 0xd9, 0xc7, 0xdf, 0x0d, 0x40, 0xbd, 0x23, 0x7c, 0x4a, 0x12,
+       0xf7, 0xcb, 0x95, 0x78, 0x9c, 0x7f, 0xc5, 0x69, 0x1d, 0xbd, 0xb7, 0x2d,
+       0x88, 0xff, 0x71, 0x9a, 0x83, 0xec, 0x74, 0x3e, 0xbd, 0x63, 0x90, 0xbc,
+       0xcb, 0xe4, 0x9b, 0x77, 0x8c, 0x2f, 0x3f, 0xa1, 0xef, 0x18, 0x4e, 0xea,
+       0xb8, 0x5e, 0x01, 0x3c, 0x52, 0x3c, 0xd4, 0x83, 0x7c, 0x49, 0x79, 0x19,
+       0x07, 0x95, 0xa7, 0x1b, 0x2b, 0xa9, 0xac, 0x13, 0xdf, 0x43, 0x8c, 0x7e,
+       0xff, 0x3f, 0x74, 0x16, 0xe3, 0xc4, 0xc4, 0xf8, 0x08, 0x2b, 0xea, 0xb9,
+       0x71, 0xbf, 0x77, 0x0b, 0xfb, 0xfa, 0xef, 0xbd, 0x76, 0x8a, 0xf7, 0x6b,
+       0x89, 0x9a, 0xbe, 0x6c, 0x05, 0xf1, 0xf1, 0x27, 0xb3, 0x15, 0xf1, 0xa1,
+       0xbe, 0x13, 0xec, 0xb6, 0x95, 0x34, 0x23, 0x9d, 0xec, 0x91, 0xcc, 0x65,
+       0xa1, 0xef, 0xc1, 0x40, 0x03, 0x02, 0x5e, 0x0b, 0xf1, 0x20, 0x12, 0xe6,
+       0xb5, 0x3d, 0x76, 0xfc, 0xee, 0x68, 0xe8, 0xb8, 0x64, 0xa1, 0x77, 0xc9,
+       0xa3, 0xf4, 0xe3, 0xb6, 0xc7, 0xf0, 0x9d, 0x48, 0x7d, 0xaa, 0x64, 0x91,
+       0x14, 0xcc, 0x7f, 0x6f, 0x2d, 0x88, 0x83, 0x7d, 0x17, 0x4e, 0x4f, 0xa6,
+       0x7d, 0xd7, 0x77, 0xf2, 0xfc, 0x28, 0x61, 0x28, 0x0e, 0xf3, 0xe7, 0x9c,
+       0x5e, 0x91, 0x59, 0x8e, 0xc3, 0xb3, 0x73, 0xfd, 0xf5, 0xc5, 0x42, 0x6e,
+       0x7c, 0xd0, 0x9f, 0xf3, 0xc9, 0x77, 0xdd, 0xc8, 0x6f, 0xdf, 0x20, 0x6f,
+       0xba, 0x17, 0xfb, 0xbb, 0x98, 0x89, 0xbe, 0xa7, 0xa6, 0x3f, 0xd8, 0x4f,
+       0xf1, 0x1d, 0x53, 0x29, 0x7f, 0xaa, 0xf2, 0xcd, 0x70, 0x5b, 0x7c, 0x0b,
+       0xf2, 0xcd, 0xef, 0x67, 0xf3, 0x38, 0xb2, 0xb4, 0xf4, 0x7d, 0x1d, 0xda,
+       0xff, 0x9e, 0x6c, 0xc7, 0x09, 0xdc, 0x47, 0x59, 0xf9, 0xb5, 0xc7, 0xe2,
+       0xe8, 0x7c, 0x63, 0xe7, 0xaf, 0xd4, 0x77, 0xea, 0xa1, 0xf9, 0xab, 0x40,
+       0xfd, 0xf9, 0xff, 0xf1, 0x3e, 0xfd, 0x9d, 0xc6, 0x06, 0x2a, 0xdf, 0x6b,
+       0x5c, 0x47, 0x65, 0x6f, 0xa3, 0x8b, 0xda, 0x03, 0xf4, 0xff, 0x7f, 0x8e,
+       0xa3, 0xff, 0x43, 0xf3, 0x9f, 0xe7, 0xb0, 0x5f, 0x68, 0xfe, 0x93, 0x19,
+       0x95, 0x28, 0xb2, 0x9f, 0x20, 0xdf, 0x3c, 0xdf, 0x1c, 0x92, 0xef, 0x2c,
+       0x9a, 0xf0, 0xc0, 0x26, 0xc0, 0xdf, 0x82, 0xed, 0x7a, 0x2b, 0x56, 0xa9,
+       0xf9, 0x4f, 0x7c, 0x3f, 0xbc, 0xd6, 0x4c, 0xfa, 0xe0, 0xf2, 0xec, 0x31,
+       0xf3, 0x9e, 0x2a, 0xde, 0xcc, 0x94, 0x27, 0x1d, 0x66, 0xa6, 0x2c, 0xc4,
+       0xff, 0xfc, 0xf4, 0x14, 0xad, 0x06, 0xda, 0xbf, 0x10, 0x74, 0x50, 0xf3,
+       0x8e, 0x28, 0x1f, 0x78, 0x3e, 0x94, 0x0f, 0x2c, 0x51, 0x3e, 0xb4, 0x5a,
+       0xbf, 0x7c, 0xbc, 0xa0, 0x07, 0x11, 0xce, 0xe1, 0x76, 0xde, 0x45, 0x76,
+       0xde, 0x44, 0x74, 0xdd, 0xb8, 0x1e, 0xf4, 0x07, 0xc0, 0x2b, 0x99, 0x25,
+       0x48, 0x7f, 0x5c, 0x0d, 0xd1, 0x1f, 0x10, 0x70, 0xdc, 0x47, 0xdf, 0x55,
+       0x75, 0x1b, 0x18, 0xe6, 0x09, 0xd5, 0x77, 0x94, 0xf3, 0xa1, 0xf8, 0x2a,
+       0x6b, 0x0c, 0x7d, 0xe2, 0xe1, 0xfa, 0x64, 0x6a, 0x98, 0xe7, 0x25, 0xfa,
+       0xde, 0xbf, 0x2e, 0x8c, 0xde, 0xe7, 0x9e, 0x14, 0xef, 0xe1, 0x4e, 0x6e,
+       0xe6, 0xef, 0xe1, 0xca, 0x59, 0x09, 0xad, 0x3b, 0x86, 0x5e, 0x89, 0x44,
+       0x7a, 0xac, 0x9c, 0x30, 0x74, 0xf6, 0x79, 0xe8, 0xbf, 0xf2, 0xd7, 0x66,
+       0xf2, 0x57, 0x36, 0x4e, 0xaa, 0xc8, 0xfb, 0x5b, 0xf4, 0xca, 0xe0, 0x6c,
+       0x8e, 0x8f, 0x67, 0xf1, 0x77, 0x05, 0xb4, 0x5f, 0xf7, 0xbb, 0x02, 0x4f,
+       0x48, 0x78, 0x1f, 0xba, 0xe6, 0x7e, 0x66, 0x43, 0x3a, 0xab, 0xbf, 0x2b,
+       0x10, 0x2f, 0xee, 0xb3, 0xbf, 0xc5, 0xef, 0x0a, 0xdc, 0x36, 0x67, 0xe2,
+       0x37, 0xff, 0x5d, 0x81, 0xcc, 0x39, 0xf1, 0xa5, 0x81, 0xbf, 0x2b, 0x90,
+       0xd9, 0x39, 0x89, 0xc3, 0xea, 0xef, 0x0a, 0xb0, 0xf8, 0xd2, 0x71, 0x7e,
+       0x57, 0x20, 0x7b, 0x4e, 0xee, 0xe8, 0xdf, 0x15, 0x98, 0x3d, 0x87, 0xc7,
+       0x39, 0xe3, 0xfd, 0xae, 0x00, 0xf8, 0x93, 0x73, 0x70, 0x7f, 0x3a, 0x9b,
+       0xfd, 0x4e, 0x2c, 0x13, 0xc5, 0x3e, 0x43, 0xbf, 0xa7, 0x3d, 0x2d, 0xee,
+       0xef, 0x7a, 0x34, 0x8e, 0x52, 0x2c, 0x0b, 0x23, 0x5d, 0x5a, 0xaa, 0xd7,
+       0xb8, 0x73, 0xb0, 0x7c, 0x5b, 0xe3, 0xf9, 0x39, 0xd6, 0x03, 0x3f, 0xe7,
+       0xe3, 0x3e, 0x0a, 0x9f, 0xb2, 0xdd, 0x9e, 0x0e, 0x70, 0xa2, 0xc1, 0x43,
+       0x7a, 0xb2, 0x27, 0xcb, 0x5e, 0x80, 0xf5, 0x83, 0x36, 0x7b, 0x21, 0xae,
+       0x13, 0x9a, 0x37, 0x47, 0xda, 0x62, 0x7c, 0x0f, 0xfb, 0x59, 0x84, 0xed,
+       0xa1, 0xef, 0xae, 0x54, 0x7a, 0xae, 0x98, 0xc3, 0xf9, 0xfe, 0x01, 0x51,
+       0xce, 0x6d, 0x1a, 0xfb, 0x7b, 0xf2, 0x07, 0xe6, 0xf0, 0xef, 0xd5, 0x6e,
+       0xb5, 0x6f, 0xd8, 0xef, 0x7d, 0xb8, 0x2f, 0x75, 0xff, 0x6c, 0xeb, 0x8a,
+       0x1c, 0x92, 0xa7, 0x2c, 0xfb, 0x32, 0xb1, 0xdf, 0x52, 0x2c, 0x99, 0x39,
+       0x26, 0xe8, 0xfb, 0xd4, 0xd1, 0x7c, 0xe6, 0x12, 0xfb, 0xe2, 0xfc, 0x05,
+       0xfa, 0xac, 0xf8, 0x3c, 0xf7, 0x07, 0xa9, 0x4c, 0xd3, 0xba, 0xa3, 0xd1,
+       0x7f, 0x9c, 0xfc, 0x88, 0x3b, 0x1a, 0xf7, 0x3b, 0xb9, 0x79, 0xc8, 0x84,
+       0xdf, 0x41, 0xbc, 0xe8, 0x1a, 0x32, 0xa1, 0x7d, 0x7f, 0xf1, 0xe1, 0x21,
+       0x13, 0xd6, 0xbf, 0x68, 0xe7, 0xef, 0x95, 0x43, 0xe7, 0x7f, 0x71, 0x0e,
+       0xff, 0x4e, 0x20, 0x6d, 0xee, 0x10, 0x8d, 0x9f, 0x06, 0xff, 0xdd, 0x4b,
+       0xfe, 0xf9, 0x50, 0x34, 0xfa, 0x4f, 0x69, 0x95, 0xe7, 0x37, 0xd2, 0x7d,
+       0xcb, 0x81, 0x99, 0x64, 0x5f, 0xa6, 0x09, 0xfb, 0x32, 0xed, 0x91, 0xe9,
+       0x9d, 0x03, 0xc0, 0x6f, 0xd3, 0x9e, 0x8b, 0xa2, 0xfb, 0x6c, 0x96, 0x1f,
+       0x4b, 0xed, 0xd5, 0x46, 0x2e, 0xa7, 0xd5, 0x8f, 0x94, 0x1f, 0xe9, 0x50,
+       0xe8, 0xbb, 0xad, 0xe2, 0xf3, 0x01, 0xfe, 0xce, 0x4c, 0x37, 0xec, 0x3b,
+       0xc8, 0xff, 0xd2, 0x0e, 0xf3, 0x77, 0x97, 0x00, 0x23, 0x9e, 0x0e, 0xe8,
+       0x08, 0x46, 0x9e, 0x45, 0xff, 0xca, 0xc9, 0xf8, 0xbb, 0xcb, 0xc9, 0x42,
+       0x6f, 0xa0, 0x9f, 0x56, 0x0a, 0x7a, 0xc1, 0x59, 0xf9, 0xe6, 0x75, 0xba,
+       0xf7, 0xc7, 0xf1, 0x38, 0x1f, 0xde, 0xd1, 0x22, 0xff, 0x75, 0xea, 0x86,
+       0xc5, 0xf7, 0x69, 0x16, 0x8c, 0x43, 0x57, 0x2d, 0x59, 0xdf, 0x43, 0x71,
+       0xe1, 0x8e, 0x91, 0x7a, 0x11, 0x67, 0x1e, 0xda, 0x88, 0x71, 0x33, 0xf8,
+       0x6f, 0x41, 0xf5, 0xd5, 0xe5, 0xaf, 0xf7, 0xa0, 0xbd, 0xa9, 0x39, 0x10,
+       0x5c, 0xef, 0x6c, 0xb8, 0x46, 0xf1, 0x2b, 0xf8, 0x6f, 0x41, 0xf5, 0xf7,
+       0xff, 0xfc, 0x9c, 0x9e, 0xff, 0x7e, 0x41, 0x70, 0x3d, 0xd0, 0x77, 0x07,
+       0xf2, 0x9b, 0x4a, 0xdf, 0x93, 0x3a, 0xcf, 0x4c, 0x8c, 0xf3, 0x4e, 0x3a,
+       0xc3, 0xac, 0xfc, 0xfd, 0xbe, 0x87, 0x7e, 0xaf, 0xa4, 0x45, 0x7c, 0xff,
+       0xbc, 0xe7, 0x9f, 0xe7, 0xe7, 0xf0, 0xf7, 0xa2, 0x9c, 0xde, 0x30, 0xde,
+       0xfd, 0xcd, 0xf8, 0xa3, 0x89, 0xfa, 0xbb, 0xe6, 0xb3, 0x74, 0x94, 0x87,
+       0x5b, 0x95, 0xaa, 0x5e, 0x1a, 0xf9, 0xfd, 0x13, 0x3d, 0x73, 0x51, 0x7e,
+       0x6f, 0x51, 0x04, 0xe9, 0x9d, 0x7a, 0x11, 0x57, 0xd5, 0x95, 0x5b, 0xc8,
+       0xce, 0x27, 0xd6, 0x19, 0x49, 0x7f, 0x15, 0xc8, 0x61, 0x56, 0x84, 0x47,
+       0x7e, 0xff, 0xa4, 0x48, 0x16, 0x7a, 0xca, 0x43, 0xf2, 0xdf, 0x77, 0x57,
+       0x34, 0xe5, 0xf1, 0xe8, 0x00, 0x08, 0xc7, 0xcc, 0xa2, 0x7b, 0x9f, 0xb8,
+       0x26, 0x0e, 0x0f, 0x4d, 0x34, 0x90, 0x7e, 0x28, 0xd0, 0x94, 0xd4, 0xee,
+       0x87, 0xf2, 0x4d, 0x4d, 0xf0, 0x77, 0xec, 0x2f, 0xa0, 0x7e, 0x90, 0x51,
+       0x7e, 0x79, 0x3e, 0xb5, 0x5e, 0xef, 0xe1, 0xdf, 0x89, 0x6b, 0x95, 0x5c,
+       0x8c, 0x73, 0x9b, 0x24, 0xfb, 0x73, 0xf8, 0xdd, 0x63, 0x93, 0x24, 0xf2,
+       0x88, 0x55, 0x66, 0xba, 0x2f, 0x18, 0xc4, 0xfc, 0x22, 0x9c, 0x67, 0x7b,
+       0xb4, 0xfb, 0xb9, 0x0a, 0x58, 0x67, 0xfb, 0x3d, 0x19, 0xe4, 0x1f, 0x0f,
+       0x32, 0xae, 0x4f, 0x5d, 0x4b, 0xf8, 0xbd, 0xd5, 0xf6, 0xe8, 0x92, 0xd2,
+       0xd5, 0xd8, 0xbe, 0xf4, 0x76, 0x6a, 0x3f, 0xf2, 0x97, 0x94, 0x27, 0x73,
+       0xd0, 0x7f, 0xaa, 0x0a, 0xb3, 0xa2, 0xff, 0xb4, 0xdd, 0xc6, 0xfd, 0xeb,
+       0xed, 0x8b, 0xd3, 0xa9, 0xfd, 0x98, 0xa4, 0xac, 0xc7, 0x73, 0xbb, 0x1e,
+       0x61, 0xb4, 0xce, 0xf6, 0xc5, 0xfc, 0xdc, 0xdb, 0x9f, 0x9c, 0x2a, 0xbe,
+       0xbf, 0x70, 0x9b, 0x50, 0x9e, 0xb7, 0x37, 0xdb, 0x27, 0xe1, 0x7d, 0xd4,
+       0x7c, 0x8b, 0xe3, 0x0c, 0xd2, 0x6b, 0xb2, 0xb8, 0x8f, 0xdb, 0x9e, 0x0c,
+       0xf5, 0x50, 0x3e, 0x23, 0x95, 0x2c, 0x7d, 0x10, 0xe7, 0x99, 0xc5, 0xf7,
+       0x5b, 0x67, 0x53, 0x88, 0x5e, 0x27, 0x97, 0xde, 0xfe, 0xe4, 0x3e, 0x85,
+       0xcc, 0x88, 0x17, 0xef, 0x85, 0xea, 0x17, 0x45, 0x50, 0x1c, 0xfc, 0xbf,
+       0x93, 0x01, 0x13, 0x53, 0xf0, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+void bnx2x_init_e1_firmware(struct bnx2x *bp)
+{
+       INIT_OPS(bp)                  = (struct raw_op *)init_ops_e1;
+       INIT_DATA(bp)                 = (u32 *)init_data_e1;
+       INIT_OPS_OFFSETS(bp)          = (u16 *)init_ops_offsets_e1;
+       INIT_TSEM_INT_TABLE_DATA(bp)  = tsem_int_table_data_e1;
+       INIT_TSEM_PRAM_DATA(bp)       = tsem_pram_data_e1;
+       INIT_USEM_INT_TABLE_DATA(bp)  = usem_int_table_data_e1;
+       INIT_USEM_PRAM_DATA(bp)       = usem_pram_data_e1;
+       INIT_XSEM_INT_TABLE_DATA(bp)  = xsem_int_table_data_e1;
+       INIT_XSEM_PRAM_DATA(bp)       = xsem_pram_data_e1;
+       INIT_CSEM_INT_TABLE_DATA(bp)  = csem_int_table_data_e1;
+       INIT_CSEM_PRAM_DATA(bp)       = csem_pram_data_e1;
+}
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init_values_e1h.c linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init_values_e1h.c
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_init_values_e1h.c     1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_init_values_e1h.c  2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,17784 @@
+/* init_ops array contains the list of operations needed to initialize the chip.
+ *
+ * For each block in the chip there are three init stages:
+ * common - HW used by both ports,
+ * port1 and port2 - initialization for a specific Ethernet port.
+ * When a port is opened or closed, the management CPU tells the driver
+ * whether to init/disable common HW in addition to the port HW.
+ * This way the first port going up will first initializes the common HW,
+ * and the last port going down also resets the common HW
+ *
+ * For each init stage/block there is a list of actions needed in a format:
+ * {operation, register, data}
+ * where:
+ * OP_WR - write a value to the chip.
+ * OP_RD - read a register (usually a clear on read register).
+ * OP_SW - string write, write a section of consecutive addresses to the chip.
+ * OP_SI - copy a string using indirect writes.
+ * OP_ZR - clear a range of memory.
+ * OP_ZP - unzip and copy using DMAE.
+ * OP_WB - string copy using DMAE.
+ *
+ * The #defines mark the stages.
+ *
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include "bnx2x_compat.h"
+#include "bnx2x_init.h"
+#include "bnx2x.h"
+
+
+static const struct raw_op init_ops_e1h[] = {
+/* #define PRS_COMMON_START        0 */
+       {OP_WR, PRS_REG_INC_VALUE, 0xf},
+       {OP_WR, PRS_REG_EVENT_ID_1, 0x45},
+       {OP_WR, PRS_REG_EVENT_ID_2, 0x84},
+       {OP_WR, PRS_REG_EVENT_ID_3, 0x6},
+       {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
+       {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
+       {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
+       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
+       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
+       {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
+       {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
+       {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000},
+       {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
+       {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000},
+       {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3},
+       {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
+       {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
+       {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
+       {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
+       {OP_WR, PRS_REG_FCOE_TYPE, 0x8906},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
+       {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
+       {OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
+       {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
+/* #define PRS_COMMON_END          1 */
+/* #define SRCH_COMMON_START       22 */
+       {OP_WR, SRC_REG_E1HMF_ENABLE, 0x1},
+/* #define SRCH_COMMON_END         23 */
+/* #define TSDM_COMMON_START       44 */
+       {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
+       {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
+       {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
+       {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_WR, TSDM_REG_AGG_INT_EVENT_0, 0x20},
+       {OP_WR, TSDM_REG_AGG_INT_EVENT_1, 0x0},
+       {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
+       {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
+       {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x1c},
+       {OP_WR, TSDM_REG_AGG_INT_T_0, 0x1},
+       {OP_ZR, TSDM_REG_AGG_INT_T_1, 0x5f},
+       {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
+/* #define TSDM_COMMON_END         45 */
+/* #define TCM_COMMON_START        66 */
+       {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
+       {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
+       {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
+       {OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
+       {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
+       {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
+       {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
+       {OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
+       {OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
+       {OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_CP_WEIGHT, 0x0},
+       {OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
+       {OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_TM_WEIGHT, 0x2},
+       {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
+       {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, TCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, TCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
+       {OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
+       {OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
+       {OP_ZR, TCM_REG_XX_TABLE, 0xa},
+       {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
+       {OP_WR, TCM_REG_N_SM_CTX_LD_4, 0x1},
+       {OP_ZR, TCM_REG_N_SM_CTX_LD_5, 0x3},
+       {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
+       {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
+       {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
+       {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
+       {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
+       {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
+       {OP_WR, TCM_REG_TSDM_IFEN, 0x1},
+       {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
+       {OP_WR, TCM_REG_PRS_IFEN, 0x1},
+       {OP_WR, TCM_REG_PBF_IFEN, 0x1},
+       {OP_WR, TCM_REG_USEM_IFEN, 0x1},
+       {OP_WR, TCM_REG_CSEM_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
+/* #define TCM_COMMON_END          67 */
+/* #define TCM_FUNC0_START         72 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd},
+       {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7},
+       {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7},
+       {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7},
+/* #define TCM_FUNC0_END           73 */
+/* #define TCM_FUNC1_START         74 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27},
+       {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27},
+       {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27},
+/* #define TCM_FUNC1_END           75 */
+/* #define TCM_FUNC2_START         76 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_0, 0x1d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x17},
+       {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x17},
+       {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x17},
+/* #define TCM_FUNC2_END           77 */
+/* #define TCM_FUNC3_START         78 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x3d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x37},
+       {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x37},
+       {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x37},
+/* #define TCM_FUNC3_END           79 */
+/* #define TCM_FUNC4_START         80 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_0, 0x4d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x47},
+       {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x47},
+       {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x47},
+/* #define TCM_FUNC4_END           81 */
+/* #define TCM_FUNC5_START         82 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x6d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x67},
+       {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x67},
+       {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x67},
+/* #define TCM_FUNC5_END           83 */
+/* #define TCM_FUNC6_START         84 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_0, 0x5d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_0, 0x57},
+       {OP_WR, TCM_REG_PHYS_QNUM2_0, 0x57},
+       {OP_WR, TCM_REG_PHYS_QNUM3_0, 0x57},
+/* #define TCM_FUNC6_END           85 */
+/* #define TCM_FUNC7_START         86 */
+       {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x7d},
+       {OP_WR, TCM_REG_PHYS_QNUM1_1, 0x77},
+       {OP_WR, TCM_REG_PHYS_QNUM2_1, 0x77},
+       {OP_WR, TCM_REG_PHYS_QNUM3_1, 0x77},
+/* #define TCM_FUNC7_END           87 */
+/* #define BRB1_COMMON_START       88 */
+       {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
+       {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
+       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
+       {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
+       {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
+/* #define BRB1_COMMON_END         89 */
+/* #define BRB1_PORT0_START        90 */
+       {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
+       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
+/* #define BRB1_PORT0_END          91 */
+/* #define BRB1_PORT1_START        92 */
+       {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
+       {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
+/* #define BRB1_PORT1_END          93 */
+/* #define TSEM_COMMON_START       110 */
+       {OP_ZP, TSEM_REG_INT_TABLE, 0xa90000},
+       {OP_WR_64, TSEM_REG_INT_TABLE + 0x3c8, 0x70223},
+       {OP_ZP, TSEM_REG_PRAM, 0x2c2d0000},
+       {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x38a20b0c},
+       {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x28ef1935},
+       {OP_WR_64, TSEM_REG_PRAM + 0x16810, 0x52fe0225},
+       {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, TSEM_REG_TS_0_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_1_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_2_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_3_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_4_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_5_AS, 0x3},
+       {OP_WR, TSEM_REG_TS_6_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_7_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_8_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_9_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_10_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_11_AS, 0x3},
+       {OP_WR, TSEM_REG_TS_12_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_13_AS, 0x1},
+       {OP_WR, TSEM_REG_TS_14_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_15_AS, 0x0},
+       {OP_WR, TSEM_REG_TS_16_AS, 0x4},
+       {OP_WR, TSEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, TSEM_REG_TS_18_AS, 0x2},
+       {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, TSEM_REG_THREADS_LIST, 0xff},
+       {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+       {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+       {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+       {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
+       {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x3b3},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x1000 + 0xecc, 0x10227},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x1ed0, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1ed8, 0x6},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e8, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e0, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4040, 0x20228},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x62c0, 0x20022a},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd100, 0x2},
+/* #define TSEM_COMMON_END         111 */
+/* #define TSEM_PORT0_START        112 */
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x124},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3300, 0x14},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x33a0, 0x68},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1c8, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d8, 0x20},
+/* #define TSEM_PORT0_END          113 */
+/* #define TSEM_PORT1_START        114 */
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2490, 0x124},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3350, 0x14},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3540, 0x68},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d0, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd258, 0x20},
+/* #define TSEM_PORT1_END          115 */
+/* #define TSEM_FUNC0_START        116 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x2920, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x5024a},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c0, 0x2},
+/* #define TSEM_FUNC0_END          117 */
+/* #define TSEM_FUNC1_START        118 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x2924, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x3040 + 0x8, 0x5024f},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c8, 0x2},
+/* #define TSEM_FUNC1_END          119 */
+/* #define TSEM_FUNC2_START        120 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x2928, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x3080 + 0x8, 0x50254},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4010, 0x20259},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d0, 0x2},
+/* #define TSEM_FUNC2_END          121 */
+/* #define TSEM_FUNC3_START        122 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x292c, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x8, 0x5025b},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4018, 0x20260},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d8, 0x2},
+/* #define TSEM_FUNC3_END          123 */
+/* #define TSEM_FUNC4_START        124 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x2930, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x3100 + 0x8, 0x50262},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4020, 0x20267},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e0, 0x2},
+/* #define TSEM_FUNC4_END          125 */
+/* #define TSEM_FUNC5_START        126 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x2934, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x3140 + 0x8, 0x50269},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026e},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e8, 0x2},
+/* #define TSEM_FUNC5_END          127 */
+/* #define TSEM_FUNC6_START        128 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x2938, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x3180 + 0x8, 0x50270},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x32c0, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4030, 0x20275},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f0, 0x2},
+/* #define TSEM_FUNC6_END          129 */
+/* #define TSEM_FUNC7_START        130 */
+       {OP_WR, TSEM_REG_FAST_MEMORY + 0x293c, 0x0},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0, 0x2},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x8, 0x50277},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x1c, 0x9},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x32e0, 0x8},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
+       {OP_SW, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027c},
+       {OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f8, 0x2},
+/* #define TSEM_FUNC7_END          131 */
+/* #define MISC_COMMON_START       220 */
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
+       {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
+       {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
+/* #define MISC_COMMON_END         221 */
+/* #define MISC_FUNC0_START        226 */
+       {OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC0_END          227 */
+/* #define MISC_FUNC1_START        228 */
+       {OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC1_END          229 */
+/* #define MISC_FUNC2_START        230 */
+       {OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC2_END          231 */
+/* #define MISC_FUNC3_START        232 */
+       {OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC3_END          233 */
+/* #define MISC_FUNC4_START        234 */
+       {OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC4_END          235 */
+/* #define MISC_FUNC5_START        236 */
+       {OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC5_END          237 */
+/* #define MISC_FUNC6_START        238 */
+       {OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC6_END          239 */
+/* #define MISC_FUNC7_START        240 */
+       {OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC7_END          241 */
+/* #define NIG_COMMON_START        264 */
+       {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
+       {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
+       {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
+       {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
+       {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
+/* #define NIG_COMMON_END          265 */
+/* #define NIG_PORT0_START         266 */
+       {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
+       {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
+       {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
+       {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
+       {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
+       {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
+       {OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7},
+       {OP_WR, NIG_REG_LLH0_CLS_TYPE, 0x1},
+       {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
+       {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
+       {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
+       {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
+       {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
+/* #define NIG_PORT0_END           267 */
+/* #define NIG_PORT1_START         268 */
+       {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
+       {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
+       {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
+       {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
+       {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
+       {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
+       {OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_1, 0x7},
+       {OP_WR, NIG_REG_LLH1_CLS_TYPE, 0x1},
+       {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
+       {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
+       {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
+       {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
+       {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
+/* #define NIG_PORT1_END           269 */
+/* #define UPB_COMMON_START        308 */
+       {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
+/* #define UPB_COMMON_END          309 */
+/* #define CSDM_COMMON_START       330 */
+       {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
+       {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
+       {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a},
+       {OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b},
+       {OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1},
+       {OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1},
+       {OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10},
+       {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
+/* #define CSDM_COMMON_END         331 */
+/* #define USDM_COMMON_START       352 */
+       {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x411},
+       {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
+       {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
+       {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
+       {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
+       {OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x2},
+       {OP_WR, USDM_REG_AGG_INT_EVENT_4, 0xa},
+       {OP_WR, USDM_REG_AGG_INT_EVENT_5, 0xf0},
+       {OP_ZR, USDM_REG_AGG_INT_EVENT_6, 0x1f},
+       {OP_WR, USDM_REG_AGG_INT_T_5, 0x1},
+       {OP_ZR, USDM_REG_AGG_INT_T_6, 0x3a},
+       {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
+       {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x3},
+       {OP_WR, USDM_REG_AGG_INT_MODE_4, 0x1},
+       {OP_WR, USDM_REG_AGG_INT_MODE_5, 0x1},
+       {OP_ZR, USDM_REG_AGG_INT_MODE_6, 0x1a},
+       {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
+/* #define USDM_COMMON_END         353 */
+/* #define CCM_COMMON_START        374 */
+       {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
+       {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
+       {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
+       {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
+       {OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
+       {OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
+       {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
+       {OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
+       {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
+       {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
+       {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
+       {OP_WR, CCM_REG_INV_DONE_Q, 0x1},
+       {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, CCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, CCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
+       {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
+       {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
+       {OP_ZR, CCM_REG_XX_TABLE, 0x12},
+       {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x24027e},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
+       {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
+       {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
+       {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
+       {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
+       {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
+       {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
+       {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
+       {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
+       {OP_WR, CCM_REG_CSDM_IFEN, 0x1},
+       {OP_WR, CCM_REG_TSEM_IFEN, 0x1},
+       {OP_WR, CCM_REG_XSEM_IFEN, 0x1},
+       {OP_WR, CCM_REG_USEM_IFEN, 0x1},
+       {OP_WR, CCM_REG_PBF_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
+/* #define CCM_COMMON_END          375 */
+/* #define CCM_FUNC0_START         380 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
+       {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc},
+       {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb},
+       {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x7},
+/* #define CCM_FUNC0_END           381 */
+/* #define CCM_FUNC1_START         382 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
+       {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x27},
+/* #define CCM_FUNC1_END           383 */
+/* #define CCM_FUNC2_START         384 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
+       {OP_WR, CCM_REG_PHYS_QNUM1_0, 0x1c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_0, 0x1b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x17},
+/* #define CCM_FUNC2_END           385 */
+/* #define CCM_FUNC3_START         386 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
+       {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x3c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x3b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x37},
+/* #define CCM_FUNC3_END           387 */
+/* #define CCM_FUNC4_START         388 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
+       {OP_WR, CCM_REG_PHYS_QNUM1_0, 0x4c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_0, 0x4b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x47},
+/* #define CCM_FUNC4_END           389 */
+/* #define CCM_FUNC5_START         390 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
+       {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x6c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x6b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x67},
+/* #define CCM_FUNC5_END           391 */
+/* #define CCM_FUNC6_START         392 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
+       {OP_WR, CCM_REG_PHYS_QNUM1_0, 0x5c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_0, 0x5b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_0, 0x57},
+/* #define CCM_FUNC6_END           393 */
+/* #define CCM_FUNC7_START         394 */
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
+       {OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
+       {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x7c},
+       {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x7b},
+       {OP_WR, CCM_REG_PHYS_QNUM3_1, 0x77},
+/* #define CCM_FUNC7_END           395 */
+/* #define UCM_COMMON_START        396 */
+       {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
+       {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
+       {OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
+       {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
+       {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
+       {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
+       {OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
+       {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
+       {OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_CP_WEIGHT, 0x0},
+       {OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
+       {OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_TM_WEIGHT, 0x2},
+       {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
+       {OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
+       {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, UCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, UCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
+       {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
+       {OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
+       {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
+       {OP_ZR, UCM_REG_XX_TABLE, 0x12},
+       {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b02a2},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
+       {OP_WR, UCM_REG_N_SM_CTX_LD_4, 0xb},
+       {OP_ZR, UCM_REG_N_SM_CTX_LD_5, 0x3},
+       {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
+       {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
+       {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
+       {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
+       {OP_WR, UCM_REG_USDM_IFEN, 0x1},
+       {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
+       {OP_WR, UCM_REG_TSEM_IFEN, 0x1},
+       {OP_WR, UCM_REG_CSEM_IFEN, 0x1},
+       {OP_WR, UCM_REG_XSEM_IFEN, 0x1},
+       {OP_WR, UCM_REG_DORQ_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
+/* #define UCM_COMMON_END          397 */
+/* #define UCM_FUNC0_START         402 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf},
+       {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe},
+       {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC0_END           403 */
+/* #define UCM_FUNC1_START         404 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC1_END           405 */
+/* #define UCM_FUNC2_START         406 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_0, 0x1f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_0, 0x1e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC2_END           407 */
+/* #define UCM_FUNC3_START         408 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x3f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x3e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC3_END           409 */
+/* #define UCM_FUNC4_START         410 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_0, 0x4f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_0, 0x4e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC4_END           411 */
+/* #define UCM_FUNC5_START         412 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x6f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x6e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC5_END           413 */
+/* #define UCM_FUNC6_START         414 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_0, 0x5f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_0, 0x5e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC6_END           415 */
+/* #define UCM_FUNC7_START         416 */
+       {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x7f},
+       {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x7e},
+       {OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+       {OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC7_END           417 */
+/* #define USEM_COMMON_START       418 */
+       {OP_ZP, USEM_REG_INT_TABLE, 0xe10000},
+       {OP_WR_64, USEM_REG_INT_TABLE + 0x3d8, 0x502bd},
+       {OP_ZP, USEM_REG_PRAM, 0x2eca0000},
+       {OP_ZP, USEM_REG_PRAM + 0x8000, 0x311a0bb3},
+       {OP_ZP, USEM_REG_PRAM + 0x10000, 0x368b17fa},
+       {OP_ZP, USEM_REG_PRAM + 0x18000, 0x39c6259d},
+       {OP_ZP, USEM_REG_PRAM + 0x20000, 0x13d5340f},
+       {OP_WR_64, USEM_REG_PRAM + 0x23070, 0x39f202bf},
+       {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, USEM_REG_TS_0_AS, 0x0},
+       {OP_WR, USEM_REG_TS_1_AS, 0x1},
+       {OP_WR, USEM_REG_TS_2_AS, 0x4},
+       {OP_WR, USEM_REG_TS_3_AS, 0x0},
+       {OP_WR, USEM_REG_TS_4_AS, 0x1},
+       {OP_WR, USEM_REG_TS_5_AS, 0x3},
+       {OP_WR, USEM_REG_TS_6_AS, 0x0},
+       {OP_WR, USEM_REG_TS_7_AS, 0x1},
+       {OP_WR, USEM_REG_TS_8_AS, 0x4},
+       {OP_WR, USEM_REG_TS_9_AS, 0x0},
+       {OP_WR, USEM_REG_TS_10_AS, 0x1},
+       {OP_WR, USEM_REG_TS_11_AS, 0x3},
+       {OP_WR, USEM_REG_TS_12_AS, 0x0},
+       {OP_WR, USEM_REG_TS_13_AS, 0x1},
+       {OP_WR, USEM_REG_TS_14_AS, 0x4},
+       {OP_WR, USEM_REG_TS_15_AS, 0x0},
+       {OP_WR, USEM_REG_TS_16_AS, 0x4},
+       {OP_WR, USEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, USEM_REG_TS_18_AS, 0x2},
+       {OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, USEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, USEM_REG_THREADS_LIST, 0xffff},
+       {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+       {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
+       {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+       {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+       {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x8020, 0xc8},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x8000, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x3da8, 0x4},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x9},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x3d80 + 0x24, 0x102c1},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x102c2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4000 + 0xc, 0x3},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x40d8, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x202c3},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x74c0, 0x202c5},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xda40, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xe000, 0x800},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x1002c7},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
+       {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002d7},
+/* #define USEM_COMMON_END         419 */
+/* #define USEM_PORT0_START        420 */
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x2450, 0xb4},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad0, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x1a0},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x3db8, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xda88, 0x2},
+/* #define USEM_PORT0_END          421 */
+/* #define USEM_PORT1_START        422 */
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x2720, 0xb4},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad8, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0x1a0},
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x3dbc, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xda90, 0x2},
+/* #define USEM_PORT1_END          423 */
+/* #define USEM_FUNC0_START        424 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a30, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4018, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd000, 0x6},
+/* #define USEM_FUNC0_END          425 */
+/* #define USEM_FUNC1_START        426 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a34, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4028, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd018, 0x6},
+/* #define USEM_FUNC1_END          427 */
+/* #define USEM_FUNC2_START        428 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a38, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4038, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd030, 0x6},
+/* #define USEM_FUNC2_END          429 */
+/* #define USEM_FUNC3_START        430 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a3c, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4048, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd048, 0x6},
+/* #define USEM_FUNC3_END          431 */
+/* #define USEM_FUNC4_START        432 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a40, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4058, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd060, 0x6},
+/* #define USEM_FUNC4_END          433 */
+/* #define USEM_FUNC5_START        434 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a44, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4068, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd078, 0x6},
+/* #define USEM_FUNC5_END          435 */
+/* #define USEM_FUNC6_START        436 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a48, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4078, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd090, 0x6},
+/* #define USEM_FUNC6_END          437 */
+/* #define USEM_FUNC7_START        438 */
+       {OP_WR, USEM_REG_FAST_MEMORY + 0x2a4c, 0x0},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0x4088, 0x2},
+       {OP_ZR, USEM_REG_FAST_MEMORY + 0xd0a8, 0x6},
+/* #define USEM_FUNC7_END          439 */
+/* #define CSEM_COMMON_START       440 */
+       {OP_ZP, CSEM_REG_INT_TABLE, 0x930000},
+       {OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002e7},
+       {OP_ZP, CSEM_REG_PRAM, 0x2adf0000},
+       {OP_ZP, CSEM_REG_PRAM + 0x8000, 0x2e050ab8},
+       {OP_WR_64, CSEM_REG_PRAM + 0xe4a0, 0x61d202e9},
+       {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, CSEM_REG_TS_0_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_1_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_2_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_3_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_4_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_5_AS, 0x3},
+       {OP_WR, CSEM_REG_TS_6_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_7_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_8_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_9_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_10_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_11_AS, 0x3},
+       {OP_WR, CSEM_REG_TS_12_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_13_AS, 0x1},
+       {OP_WR, CSEM_REG_TS_14_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_15_AS, 0x0},
+       {OP_WR, CSEM_REG_TS_16_AS, 0x4},
+       {OP_WR, CSEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, CSEM_REG_TS_18_AS, 0x2},
+       {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
+       {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
+       {OP_WR_EMUL, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6700, 0x100},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x9000, 0x400},
+       {OP_SW, CSEM_REG_FAST_MEMORY + 0x6b08, 0x2002eb},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
+       {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x10030b},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+       {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x10031b},
+/* #define CSEM_COMMON_END         441 */
+/* #define CSEM_PORT0_START        442 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8100, 0xa0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8c00, 0x3c},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0xb000, 0x200},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8800, 0x80},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8de0, 0x3c},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
+/* #define CSEM_PORT0_END          443 */
+/* #define CSEM_PORT1_START        444 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8380, 0xa0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8700, 0x40},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8cf0, 0x3c},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0xb800, 0x200},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8a00, 0x80},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8ed0, 0x3c},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
+/* #define CSEM_PORT1_END          445 */
+/* #define CSEM_FUNC0_START        446 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8000, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
+/* #define CSEM_FUNC0_END          447 */
+/* #define CSEM_FUNC1_START        448 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8020, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
+/* #define CSEM_FUNC1_END          449 */
+/* #define CSEM_FUNC2_START        450 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8040, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x61c0, 0x30},
+/* #define CSEM_FUNC2_END          451 */
+/* #define CSEM_FUNC3_START        452 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8060, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6280, 0x30},
+/* #define CSEM_FUNC3_END          453 */
+/* #define CSEM_FUNC4_START        454 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x8080, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6340, 0x30},
+/* #define CSEM_FUNC4_END          455 */
+/* #define CSEM_FUNC5_START        456 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x80a0, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6400, 0x30},
+/* #define CSEM_FUNC5_END          457 */
+/* #define CSEM_FUNC6_START        458 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x80c0, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x64c0, 0x30},
+/* #define CSEM_FUNC6_END          459 */
+/* #define CSEM_FUNC7_START        460 */
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x80e0, 0x8},
+       {OP_WR, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
+       {OP_ZR, CSEM_REG_FAST_MEMORY + 0x6580, 0x30},
+/* #define CSEM_FUNC7_END          461 */
+/* #define XPB_COMMON_START        462 */
+       {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28},
+/* #define XPB_COMMON_END          463 */
+/* #define DQ_COMMON_START         484 */
+       {OP_WR, DORQ_REG_MODE_ACT, 0x2},
+       {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
+       {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
+       {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
+       {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
+       {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
+       {OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
+       {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
+       {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
+       {OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
+       {OP_WR, DORQ_REG_AGG_CMD1, 0x80},
+       {OP_WR, DORQ_REG_AGG_CMD2, 0x81},
+       {OP_WR, DORQ_REG_AGG_CMD3, 0x80},
+       {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
+       {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
+       {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
+       {OP_WR, DORQ_REG_REGN, 0x7c1004},
+       {OP_WR, DORQ_REG_IF_EN, 0xf},
+/* #define DQ_COMMON_END           485 */
+/* #define TIMERS_COMMON_START     506 */
+       {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
+       {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
+       {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
+       {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
+       {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
+       {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
+       {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
+       {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
+       {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
+       {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
+       {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
+       {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
+       {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
+       {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
+       {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
+       {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
+       {OP_WR, TM_REG_EN_TIMERS, 0x1},
+       {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
+       {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
+       {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
+       {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
+/* #define TIMERS_COMMON_END       507 */
+/* #define TIMERS_PORT0_START      508 */
+       {OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0},
+       {OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0},
+       {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT0_END        509 */
+/* #define TIMERS_PORT1_START      510 */
+       {OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0},
+       {OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0},
+       {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT1_END        511 */
+/* #define XSDM_COMMON_START       528 */
+       {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
+       {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
+       {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+       {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c},
+       {OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d},
+       {OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52},
+       {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
+       {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
+       {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
+       {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
+       {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
+       {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
+       {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+       {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+       {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
+       {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
+       {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
+/* #define XSDM_COMMON_END         529 */
+/* #define QM_COMMON_START         550 */
+       {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
+       {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
+       {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
+       {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
+       {OP_WR, QM_REG_PCIREQAT, 0x2},
+       {OP_WR, QM_REG_CMINITCRD_0, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_1, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_2, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_3, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_4, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_5, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_6, 0x4},
+       {OP_WR, QM_REG_CMINITCRD_7, 0x4},
+       {OP_WR, QM_REG_OUTLDREQ, 0x4},
+       {OP_WR, QM_REG_CTXREG_0, 0x7c},
+       {OP_WR, QM_REG_CTXREG_1, 0x3d},
+       {OP_WR, QM_REG_CTXREG_2, 0x3f},
+       {OP_WR, QM_REG_CTXREG_3, 0x9c},
+       {OP_WR, QM_REG_ENSEC, 0x7},
+       {OP_ZR, QM_REG_QVOQIDX_0, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_5, 0x0},
+       {OP_WR, QM_REG_QVOQIDX_6, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_7, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_8, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_9, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_10, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_11, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_12, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_13, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_14, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_15, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_16, 0x0},
+       {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
+       {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
+       {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_21, 0x0},
+       {OP_WR, QM_REG_QVOQIDX_22, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_23, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_24, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_5, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_25, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_26, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_27, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_28, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_6, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_29, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_30, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_31, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_32, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010120},
+       {OP_WR, QM_REG_QVOQIDX_33, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_34, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_35, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_36, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_37, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_38, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_39, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_40, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_41, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_42, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_43, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_44, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_45, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_46, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_47, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_48, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
+       {OP_WR, QM_REG_QVOQIDX_49, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_50, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_51, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_52, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_53, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_54, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_55, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_56, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_13, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_57, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_58, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_59, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_60, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_14, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_61, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_62, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_63, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_64, 0x0},
+       {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010120},
+       {OP_ZR, QM_REG_QVOQIDX_65, 0x4},
+       {OP_WR, QM_REG_WRRWEIGHTS_16, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_69, 0x0},
+       {OP_WR, QM_REG_QVOQIDX_70, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_71, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_72, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_17, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_73, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_74, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_75, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_76, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_18, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_77, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_78, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_79, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_80, 0x0},
+       {OP_WR, QM_REG_WRRWEIGHTS_19, 0x1010120},
+       {OP_ZR, QM_REG_QVOQIDX_81, 0x4},
+       {OP_WR, QM_REG_WRRWEIGHTS_20, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_85, 0x0},
+       {OP_WR, QM_REG_QVOQIDX_86, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_87, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_88, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_21, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_89, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_90, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_91, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_92, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_22, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_93, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_94, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_95, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_96, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_23, 0x1010120},
+       {OP_WR, QM_REG_QVOQIDX_97, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_98, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_99, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_100, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_24, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_101, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_102, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_103, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_104, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_25, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_105, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_106, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_107, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_108, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_26, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_109, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_110, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_111, 0x7},
+       {OP_WR, QM_REG_QVOQIDX_112, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_27, 0x1010120},
+       {OP_WR, QM_REG_QVOQIDX_113, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_114, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_115, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_116, 0x1},
+       {OP_WR, QM_REG_WRRWEIGHTS_28, 0x1010101},
+       {OP_WR, QM_REG_QVOQIDX_117, 0x1},
+       {OP_WR, QM_REG_QVOQIDX_118, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_119, 0x4},
+       {OP_WR, QM_REG_QVOQIDX_120, 0x2},
+       {OP_WR, QM_REG_WRRWEIGHTS_29, 0x8012004},
+       {OP_WR, QM_REG_QVOQIDX_121, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_122, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_123, 0x5},
+       {OP_WR, QM_REG_QVOQIDX_124, 0x5},
+       {OP_WR, QM_REG_WRRWEIGHTS_30, 0x20081001},
+       {OP_WR, QM_REG_QVOQIDX_125, 0x8},
+       {OP_WR, QM_REG_QVOQIDX_126, 0x6},
+       {OP_WR, QM_REG_QVOQIDX_127, 0x7},
+       {OP_WR, QM_REG_WRRWEIGHTS_31, 0x1010120},
+       {OP_WR, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
+       {OP_WR, QM_REG_VOQQMASK_0_MSB, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
+       {OP_WR, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_1_LSB, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
+       {OP_WR, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
+       {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x1000100},
+       {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x1000100},
+       {OP_WR, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
+       {OP_WR, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
+       {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
+       {OP_WR, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
+       {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
+       {OP_WR, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
+       {OP_WR, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
+       {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
+       {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
+       {OP_WR, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
+       {OP_WR, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
+       {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x40004000},
+       {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x40004000},
+       {OP_WR, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
+       {OP_WR, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
+       {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x80008000},
+       {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x80008000},
+       {OP_WR, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
+       {OP_WR, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
+       {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x20002000},
+       {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x20002000},
+       {OP_WR, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
+       {OP_WR, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
+       {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x2},
+       {OP_WR, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_10_LSB, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_10_MSB, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_11_LSB, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_11_MSB, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_VOQPORT_0, 0x0},
+       {OP_WR, QM_REG_VOQPORT_1, 0x1},
+       {OP_ZR, QM_REG_VOQPORT_2, 0xa},
+       {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
+       {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
+       {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
+       {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
+       {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
+       {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
+       {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
+       {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
+       {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
+       {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
+       {OP_WR, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
+       {OP_WR, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
+       {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
+       {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
+       {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
+       {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
+       {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
+       {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
+       {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
+       {OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
+       {OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
+       {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
+       {OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
+       {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
+       {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
+       {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
+       {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
+       {OP_WR, QM_REG_ENBYTECRD_LSB, 0xf000f},
+       {OP_WR, QM_REG_ENBYTECRD_MSB, 0xf000f},
+       {OP_WR, QM_REG_ENBYTECRD_LSB_EXT_A, 0xf000f},
+       {OP_WR, QM_REG_ENBYTECRD_MSB_EXT_A, 0xf000f},
+       {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
+       {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
+       {OP_WR, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
+       {OP_WR, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
+       {OP_WR, QM_REG_PQ2PCIFUNC_0, 0x0},
+       {OP_WR, QM_REG_PQ2PCIFUNC_1, 0x2},
+       {OP_WR, QM_REG_PQ2PCIFUNC_2, 0x1},
+       {OP_WR, QM_REG_PQ2PCIFUNC_3, 0x3},
+       {OP_WR, QM_REG_PQ2PCIFUNC_4, 0x4},
+       {OP_WR, QM_REG_PQ2PCIFUNC_5, 0x6},
+       {OP_WR, QM_REG_PQ2PCIFUNC_6, 0x5},
+       {OP_WR, QM_REG_PQ2PCIFUNC_7, 0x7},
+       {OP_WR, QM_REG_CMINTEN, 0xff},
+/* #define QM_COMMON_END           551 */
+/* #define PBF_COMMON_START        572 */
+       {OP_WR, PBF_REG_INIT, 0x1},
+       {OP_WR, PBF_REG_INIT_P4, 0x1},
+       {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
+       {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
+       {OP_WR, PBF_REG_INIT_P4, 0x0},
+       {OP_WR, PBF_REG_INIT, 0x0},
+       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
+/* #define PBF_COMMON_END          573 */
+/* #define PBF_PORT0_START         574 */
+       {OP_WR, PBF_REG_INIT_P0, 0x1},
+       {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
+       {OP_WR, PBF_REG_INIT_P0, 0x0},
+       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
+/* #define PBF_PORT0_END           575 */
+/* #define PBF_PORT1_START         576 */
+       {OP_WR, PBF_REG_INIT_P1, 0x1},
+       {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
+       {OP_WR, PBF_REG_INIT_P1, 0x0},
+       {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
+/* #define PBF_PORT1_END           577 */
+/* #define XCM_COMMON_START        594 */
+       {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
+       {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
+       {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
+       {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
+       {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
+       {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
+       {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
+       {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
+       {OP_WR, XCM_REG_STORM_WEIGHT, 0x3},
+       {OP_WR, XCM_REG_TSEM_WEIGHT, 0x6},
+       {OP_WR, XCM_REG_CSEM_WEIGHT, 0x3},
+       {OP_WR, XCM_REG_USEM_WEIGHT, 0x3},
+       {OP_WR, XCM_REG_DORQ_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_PBF_WEIGHT, 0x0},
+       {OP_WR, XCM_REG_NIG0_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_CP_WEIGHT, 0x0},
+       {OP_WR, XCM_REG_XSDM_WEIGHT, 0x6},
+       {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4},
+       {OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_TM_WEIGHT, 0x2},
+       {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
+       {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
+       {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
+       {OP_WR, XCM_REG_AUX1_Q, 0x2},
+       {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
+       {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
+       {OP_WR, XCM_REG_GR_LD0_PR, 0x1},
+       {OP_WR, XCM_REG_GR_LD1_PR, 0x2},
+       {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
+       {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
+       {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
+       {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
+       {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
+       {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
+       {OP_WR, XCM_REG_XX_MSG_NUM, 0x20},
+       {OP_ZR, XCM_REG_XX_TABLE, 0x12},
+       {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f032b},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
+       {OP_WR, XCM_REG_N_SM_CTX_LD_4, 0xe},
+       {OP_ZR, XCM_REG_N_SM_CTX_LD_5, 0x3},
+       {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
+       {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
+       {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
+       {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
+       {OP_WR, XCM_REG_XSDM_IFEN, 0x1},
+       {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
+       {OP_WR, XCM_REG_TSEM_IFEN, 0x1},
+       {OP_WR, XCM_REG_CSEM_IFEN, 0x1},
+       {OP_WR, XCM_REG_USEM_IFEN, 0x1},
+       {OP_WR, XCM_REG_DORQ_IFEN, 0x1},
+       {OP_WR, XCM_REG_PBF_IFEN, 0x1},
+       {OP_WR, XCM_REG_NIG0_IFEN, 0x1},
+       {OP_WR, XCM_REG_NIG1_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
+       {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
+       {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
+/* #define XCM_COMMON_END          595 */
+/* #define XCM_FUNC0_START         600 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC0_END           601 */
+/* #define XCM_FUNC1_START         602 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC1_END           603 */
+/* #define XCM_FUNC2_START         604 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC2_END           605 */
+/* #define XCM_FUNC3_START         606 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC3_END           607 */
+/* #define XCM_FUNC4_START         608 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC4_END           609 */
+/* #define XCM_FUNC5_START         610 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC5_END           611 */
+/* #define XCM_FUNC6_START         612 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC6_END           613 */
+/* #define XCM_FUNC7_START         614 */
+       {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+       {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+       {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+       {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+       {OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC7_END           615 */
+/* #define XSEM_COMMON_START       616 */
+       {OP_ZP, XSEM_REG_INT_TABLE, 0xc00000},
+       {OP_WR_64, XSEM_REG_INT_TABLE + 0x3a8, 0xb034a},
+       {OP_ZP, XSEM_REG_PRAM, 0x32fd0000},
+       {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x357e0cc0},
+       {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x3ae41a20},
+       {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x39cf28da},
+       {OP_ZP, XSEM_REG_PRAM + 0x20000, 0x1c3c374e},
+       {OP_WR_64, XSEM_REG_PRAM + 0x23710, 0x391e034c},
+       {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
+       {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
+       {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
+       {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
+       {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
+       {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
+       {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
+       {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
+       {OP_WR, XSEM_REG_TS_0_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_1_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_2_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_3_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_4_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_5_AS, 0x3},
+       {OP_WR, XSEM_REG_TS_6_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_7_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_8_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_9_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_10_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_11_AS, 0x3},
+       {OP_WR, XSEM_REG_TS_12_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_13_AS, 0x1},
+       {OP_WR, XSEM_REG_TS_14_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_15_AS, 0x0},
+       {OP_WR, XSEM_REG_TS_16_AS, 0x4},
+       {OP_WR, XSEM_REG_TS_17_AS, 0x3},
+       {OP_ZR, XSEM_REG_TS_18_AS, 0x2},
+       {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
+       {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
+       {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
+       {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
+       {OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
+       {OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
+       {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
+       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
+       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+       {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+       {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
+       {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x29c8, 0x4},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x29c8 + 0x10, 0x2034e},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20350},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2498, 0x40352},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x2c50, 0x0},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x2c10, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2c08, 0x20356},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x3000, 0x20358},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x100},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x4000, 0x10035a},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x8408, 0x2036a},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x10036c},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x8037c},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80384},
+/* #define XSEM_COMMON_END         617 */
+/* #define XSEM_PORT0_START        618 */
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xc000, 0xd8},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x24a8, 0x14},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2548, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2668, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2788, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x28a8, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x29e0, 0x2038c},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2038e},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd0, 0x2},
+/* #define XSEM_PORT0_END          619 */
+/* #define XSEM_PORT1_START        620 */
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xc360, 0xd8},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x24f8, 0x14},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x25d8, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x26f8, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2818, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x2938, 0x24},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x29e8, 0x20390},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x20392},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd8, 0x2},
+/* #define XSEM_PORT1_END          621 */
+/* #define XSEM_FUNC0_START        622 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c0, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x29f0, 0x100394},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb000, 0x6},
+/* #define XSEM_FUNC0_END          623 */
+/* #define XSEM_FUNC1_START        624 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c4, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2a30, 0x1003a4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb018, 0x6},
+/* #define XSEM_FUNC1_END          625 */
+/* #define XSEM_FUNC2_START        626 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c8, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2a70, 0x1003b4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb030, 0x6},
+/* #define XSEM_FUNC2_END          627 */
+/* #define XSEM_FUNC3_START        628 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6cc, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2ab0, 0x1003c4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb048, 0x6},
+/* #define XSEM_FUNC3_END          629 */
+/* #define XSEM_FUNC4_START        630 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d0, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2af0, 0x1003d4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb060, 0x6},
+/* #define XSEM_FUNC4_END          631 */
+/* #define XSEM_FUNC5_START        632 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d4, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2b30, 0x1003e4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb078, 0x6},
+/* #define XSEM_FUNC5_END          633 */
+/* #define XSEM_FUNC6_START        634 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d8, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2b70, 0x1003f4},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb090, 0x6},
+/* #define XSEM_FUNC6_END          635 */
+/* #define XSEM_FUNC7_START        636 */
+       {OP_WR, XSEM_REG_FAST_MEMORY + 0xc6dc, 0x0},
+       {OP_SW, XSEM_REG_FAST_MEMORY + 0x2bb0, 0x100404},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
+       {OP_ZR, XSEM_REG_FAST_MEMORY + 0xb0a8, 0x6},
+/* #define XSEM_FUNC7_END          637 */
+/* #define CDU_COMMON_START        638 */
+       {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
+       {OP_WR, CDU_REG_MF_MODE, 0x1},
+       {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
+       {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
+       {OP_WB, CDU_REG_L1TT, 0x2000414},
+       {OP_WB, CDU_REG_MATT, 0x280614},
+       {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
+/* #define CDU_COMMON_END          639 */
+/* #define DMAE_COMMON_START       660 */
+       {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
+       {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
+       {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
+       {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
+       {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
+       {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
+/* #define DMAE_COMMON_END         661 */
+/* #define PXP_COMMON_START        682 */
+       {OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x5063c},
+       {OP_WB, PXP_REG_HST_INBOUND_INT, 0x50641},
+       {OP_WB, PXP_REG_HST_INBOUND_INT + 0x20, 0x50646},
+/* #define PXP_COMMON_END          683 */
+/* #define CFC_COMMON_START        704 */
+       {OP_ZR, CFC_REG_LINK_LIST, 0x100},
+       {OP_WR, CFC_REG_CONTROL0, 0x10},
+       {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
+       {OP_WR, CFC_REG_INTERFACES, 0x280000},
+       {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
+       {OP_WR, CFC_REG_INTERFACES, 0x0},
+/* #define CFC_COMMON_END          705 */
+/* #define HC_FUNC0_START          732 */
+       {OP_WR, HC_REG_CONFIG_0, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P0, 0x0},
+       {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT, 0x2},
+       {OP_WR, HC_REG_VQID_0, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+       {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+       {OP_WR, HC_REG_CONFIG_0, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC0_END            733 */
+/* #define HC_FUNC1_START          734 */
+       {OP_WR, HC_REG_CONFIG_1, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P1, 0x1},
+       {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+       {OP_WR, HC_REG_VQID_1, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+       {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+       {OP_WR, HC_REG_CONFIG_1, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC1_END            735 */
+/* #define HC_FUNC2_START          736 */
+       {OP_WR, HC_REG_CONFIG_0, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P0, 0x2},
+       {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT, 0x2},
+       {OP_WR, HC_REG_VQID_0, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+       {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+       {OP_WR, HC_REG_CONFIG_0, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC2_END            737 */
+/* #define HC_FUNC3_START          738 */
+       {OP_WR, HC_REG_CONFIG_1, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P1, 0x3},
+       {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+       {OP_WR, HC_REG_VQID_1, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+       {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+       {OP_WR, HC_REG_CONFIG_1, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC3_END            739 */
+/* #define HC_FUNC4_START          740 */
+       {OP_WR, HC_REG_CONFIG_0, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P0, 0x4},
+       {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT, 0x2},
+       {OP_WR, HC_REG_VQID_0, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+       {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+       {OP_WR, HC_REG_CONFIG_0, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC4_END            741 */
+/* #define HC_FUNC5_START          742 */
+       {OP_WR, HC_REG_CONFIG_1, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P1, 0x5},
+       {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+       {OP_WR, HC_REG_VQID_1, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+       {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+       {OP_WR, HC_REG_CONFIG_1, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC5_END            743 */
+/* #define HC_FUNC6_START          744 */
+       {OP_WR, HC_REG_CONFIG_0, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P0, 0x6},
+       {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT, 0x2},
+       {OP_WR, HC_REG_VQID_0, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+       {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+       {OP_WR, HC_REG_CONFIG_0, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC6_END            745 */
+/* #define HC_FUNC7_START          746 */
+       {OP_WR, HC_REG_CONFIG_1, 0x1080},
+       {OP_WR, HC_REG_FUNC_NUM_P1, 0x7},
+       {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+       {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+       {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+       {OP_WR, HC_REG_VQID_1, 0x2b5},
+       {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+       {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+       {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+       {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+       {OP_WR, HC_REG_CONFIG_1, 0x1a80},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+       {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC7_END            747 */
+/* #define PXP2_COMMON_START       748 */
+       {OP_WR, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
+       {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340},
+       {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
+       {OP_WR, PXP2_REG_RQ_ELT_DISABLE, 0x1},
+       {OP_WR, PXP2_REG_WR_REV_MODE, 0x0},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
+       {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
+       {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xf0001000},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
+       {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
+       {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
+       {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
+       {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
+       {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
+       {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
+       {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
+       {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
+       {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
+       {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
+       {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
+       {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
+       {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
+       {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
+       {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
+       {OP_WR, PXP2_REG_RQ_ILT_MODE, 0x1},
+       {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
+/* #define PXP2_COMMON_END         749 */
+/* #define MISC_AEU_COMMON_START   770 */
+       {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
+       {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
+       {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
+       {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
+       {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
+       {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
+       {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
+       {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
+       {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
+       {OP_WR, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
+       {OP_WR, MISC_REG_AEU_GENERAL_MASK, 0x3},
+/* #define MISC_AEU_COMMON_END     771 */
+/* #define MISC_AEU_PORT0_START    772 */
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
+       {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
+       {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
+       {OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
+/* #define MISC_AEU_PORT0_END      773 */
+/* #define MISC_AEU_PORT1_START    774 */
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
+       {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
+       {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
+       {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
+       {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
+       {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
+       {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
+       {OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
+/* #define MISC_AEU_PORT1_END      775 */
+
+};
+
+static const u16 init_ops_offsets_e1h[] = {
+       0x0000, 0x0031, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0031, 0x0032, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0032,
+       0x0056, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0056, 0x008c, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x008c, 0x0090, 0x0090, 0x0094, 0x0094, 0x0098, 0x0098, 0x009c, 0x009c,
+       0x00a0, 0x00a0, 0x00a4, 0x00a4, 0x00a8, 0x00a8, 0x00ac, 0x00ac, 0x00b1,
+       0x00b1, 0x00b3, 0x00b3, 0x00b5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x00b5, 0x0102, 0x0102, 0x010a, 0x010a, 0x0112, 0x0112,
+       0x011b, 0x011b, 0x0124, 0x0124, 0x012d, 0x012d, 0x0136, 0x0136, 0x013f,
+       0x013f, 0x0148, 0x0148, 0x0151, 0x0151, 0x015a, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x015a, 0x015f, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x015f, 0x0160, 0x0160, 0x0161, 0x0161, 0x0162, 0x0162, 0x0163,
+       0x0163, 0x0164, 0x0164, 0x0165, 0x0165, 0x0166, 0x0166, 0x0167, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0167, 0x016c, 0x016c, 0x0179, 0x0179, 0x0186,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0186, 0x0187, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0187, 0x01be, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x01be, 0x01e9, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x01e9, 0x021a, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x021a, 0x0221, 0x0221, 0x0228, 0x0228, 0x022f, 0x022f,
+       0x0236, 0x0236, 0x023d, 0x023d, 0x0244, 0x0244, 0x024b, 0x024b, 0x0252,
+       0x0252, 0x028a, 0x0000, 0x0000, 0x0000, 0x0000, 0x028a, 0x028e, 0x028e,
+       0x0292, 0x0292, 0x0296, 0x0296, 0x029a, 0x029a, 0x029e, 0x029e, 0x02a2,
+       0x02a2, 0x02a6, 0x02a6, 0x02aa, 0x02aa, 0x02fc, 0x02fc, 0x0313, 0x0313,
+       0x032a, 0x032a, 0x032d, 0x032d, 0x0330, 0x0330, 0x0333, 0x0333, 0x0336,
+       0x0336, 0x0339, 0x0339, 0x033c, 0x033c, 0x033f, 0x033f, 0x0342, 0x0342,
+       0x0383, 0x0383, 0x038a, 0x038a, 0x0391, 0x0391, 0x0395, 0x0395, 0x0399,
+       0x0399, 0x039d, 0x039d, 0x03a1, 0x03a1, 0x03a5, 0x03a5, 0x03a9, 0x03a9,
+       0x03ad, 0x03ad, 0x03b1, 0x03b1, 0x03b2, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03b2, 0x03c4,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x03c4, 0x03d9, 0x03d9, 0x03dc, 0x03dc, 0x03df, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03df, 0x040c, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x040c, 0x050f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x050f, 0x0516, 0x0516, 0x051a,
+       0x051a, 0x051e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x051e, 0x055e, 0x0000, 0x0000, 0x0000, 0x0000, 0x055e, 0x0567, 0x0567,
+       0x0570, 0x0570, 0x0579, 0x0579, 0x0582, 0x0582, 0x058b, 0x058b, 0x0594,
+       0x0594, 0x059d, 0x059d, 0x05a6, 0x05a6, 0x05ff, 0x05ff, 0x0611, 0x0611,
+       0x0623, 0x0623, 0x0627, 0x0627, 0x062b, 0x062b, 0x062f, 0x062f, 0x0633,
+       0x0633, 0x0637, 0x0637, 0x063b, 0x063b, 0x063f, 0x063f, 0x0643, 0x0643,
+       0x064a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x064a, 0x0650, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0650, 0x0653,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0653, 0x0659, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0659, 0x0668, 0x0668, 0x0677, 0x0677, 0x0686,
+       0x0686, 0x0695, 0x0695, 0x06a4, 0x06a4, 0x06b3, 0x06b3, 0x06c2, 0x06c2,
+       0x06d1, 0x06d1, 0x0742, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0742, 0x0755, 0x0755, 0x0766,
+       0x0766, 0x0777, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+static const u32 init_data_e1h[] = {
+       0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
+       0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
+       0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
+       0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
+       0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
+       0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
+       0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
+       0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
+       0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
+       0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
+       0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
+       0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
+       0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
+       0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
+       0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
+       0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
+       0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
+       0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
+       0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
+       0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
+       0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
+       0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
+       0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
+       0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
+       0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
+       0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
+       0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
+       0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
+       0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
+       0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
+       0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
+       0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
+       0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
+       0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
+       0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
+       0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
+       0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
+       0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
+       0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
+       0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
+       0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
+       0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
+       0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
+       0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
+       0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
+       0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
+       0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
+       0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
+       0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
+       0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
+       0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
+       0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
+       0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
+       0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
+       0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
+       0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
+       0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
+       0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
+       0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
+       0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
+       0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
+       0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
+       0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
+       0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
+       0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
+       0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
+       0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
+       0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
+       0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
+       0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
+       0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
+       0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
+       0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
+       0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
+       0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
+       0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
+       0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
+       0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
+       0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
+       0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
+       0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
+       0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
+       0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
+       0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
+       0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
+       0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
+       0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
+       0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
+       0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
+       0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
+       0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
+       0x00000200, 0x00007ff8, 0x00007ff8, 0x00000cdf, 0x00001500, 0x00000001,
+       0x00000001, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000,
+       0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+       0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+       0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff,
+       0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000,
+       0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff,
+       0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20,
+       0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003,
+       0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+       0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240,
+       0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0,
+       0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40,
+       0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0,
+       0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440,
+       0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0,
+       0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80,
+       0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80,
+       0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480,
+       0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980,
+       0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00007ff8,
+       0x00007ff8, 0x0000193c, 0x00001500, 0x00001900, 0x00000028, 0x00100000,
+       0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00007ff8,
+       0x00007ff8, 0x000005c7, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x00001000, 0x00002080, 0x00003100, 0x00004180, 0x00005200,
+       0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480, 0x0000b500,
+       0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, 0x00011800,
+       0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00,
+       0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00,
+       0x0001ee80, 0x0001ff00, 0x00007ff8, 0x00007ff8, 0x0000112e, 0x00003500,
+       0x10000000, 0x000028ad, 0x00000000, 0x00010001, 0x00150005, 0xccccccc5,
+       0xffffffff, 0xffffffff, 0x7058103c, 0x00000000, 0x00000000, 0x00000001,
+       0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc,
+       0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc,
+       0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x000e0232, 0x011600d6, 0x00100000, 0x00000000,
+       0x00720236, 0x012300f3, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+       0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+       0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
+       0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+       0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+       0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff,
+       0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+       0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+       0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+       0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
+       0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+       0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+       0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+       0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
+       0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+       0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
+       0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x316fffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+       0xfffffff1, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffffff6, 0x30bfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf314, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+       0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+       0xfffffff0, 0x307fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+       0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+       0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+       0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+       0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+       0x0040cf3c, 0xcdcdcdcd, 0x000c0000, 0x000700c0, 0x00028130, 0x000b8158,
+       0x00020210, 0x00010230, 0x000f0240, 0x00010330, 0x00080000, 0x00080080,
+       0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210, 0x00020280,
+       0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250, 0x00010270,
+       0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180, 0x000b81a8,
+       0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x000b0000, 0x000100b0,
+       0x000280c0, 0x000580e8, 0x00020140, 0x00010160, 0x000e0170, 0x00038250,
+       0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc,
+       0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc,
+       0xcccccccc, 0xcccccccc, 0x04002000
+};
+
+static const u8 tsem_int_table_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51,
+       0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0x59, 0x05, 0x19, 0x18, 0xf4, 0x84, 0x11,
+       0x7c, 0x7a, 0x60, 0x7e, 0x4e, 0xca, 0xf4, 0x3b, 0xf2, 0x32, 0x30, 0x38,
+       0x03, 0xb1, 0x2b, 0x10, 0x37, 0x00, 0xf1, 0x61, 0x6e, 0x06, 0x86, 0x23,
+       0xdc, 0xc4, 0xeb, 0x3f, 0x2b, 0x8f, 0x60, 0x07, 0xca, 0x32, 0x30, 0xd4,
+       0x02, 0xf1, 0x7e, 0x69, 0x06, 0x06, 0x2b, 0x39, 0x84, 0xb8, 0xa1, 0x02,
+       0x03, 0xc3, 0x12, 0x20, 0x3f, 0x0d, 0x2a, 0xf6, 0x1a, 0x48, 0x17, 0xca,
+       0x53, 0xe6, 0xee, 0xc1, 0x82, 0x55, 0x54, 0x31, 0xc5, 0x14, 0x95, 0x11,
+       0x6c, 0x55, 0x2c, 0xf2, 0xc8, 0x58, 0x0d, 0x4d, 0xbe, 0x41, 0x19, 0x95,
+       0xaf, 0x4e, 0x40, 0xff, 0x40, 0xe3, 0x64, 0x1d, 0x54, 0xfe, 0x04, 0x2d,
+       0x08, 0xfd, 0x5e, 0x1b, 0x42, 0xa7, 0xa0, 0xc9, 0x4f, 0x84, 0xca, 0xbb,
+       0x42, 0xfd, 0x95, 0xaa, 0x83, 0xdd, 0x5c, 0x37, 0x22, 0xfd, 0x9d, 0xc6,
+       0x82, 0xca, 0x4f, 0x40, 0xe3, 0xb7, 0x30, 0xa2, 0xf2, 0xcd, 0x38, 0xd0,
+       0xdc, 0x0f, 0x55, 0x0f, 0x00, 0x00, 0x17, 0x4b, 0x67, 0xc8, 0x03, 0x00,
+       0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 tsem_pram_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
+       0x0d, 0x78, 0x54, 0xd5, 0xb5, 0xe8, 0x3e, 0x3f, 0x73, 0xe6, 0xcc, 0xe4,
+       0xcc, 0xe4, 0x24, 0x24, 0x61, 0xc2, 0xef, 0x24, 0x84, 0x10, 0x34, 0xe2,
+       0x10, 0x22, 0x06, 0x4b, 0xeb, 0x09, 0x7f, 0x86, 0x9a, 0x7a, 0x07, 0xaa,
+       0x98, 0x5a, 0xc5, 0x01, 0x23, 0x06, 0x08, 0x24, 0x52, 0xf5, 0xe1, 0xd3,
+       0x7e, 0x99, 0x48, 0x02, 0x01, 0x11, 0x06, 0xb5, 0x34, 0x14, 0xd4, 0xe1,
+       0x4f, 0x69, 0x2f, 0xb6, 0x91, 0x8b, 0x96, 0x5a, 0x8a, 0x03, 0x3e, 0x2d,
+       0xb6, 0xbe, 0xef, 0x05, 0x9f, 0xb5, 0x7a, 0xb5, 0x7d, 0xd1, 0x52, 0xfc,
+       0x29, 0x4a, 0xca, 0xbb, 0x52, 0xfb, 0xae, 0xad, 0x6f, 0xaf, 0xb5, 0xf7,
+       0x4e, 0xce, 0x39, 0xcc, 0x90, 0xe0, 0x4f, 0xdb, 0xfb, 0xde, 0xa5, 0x9f,
+       0xdd, 0xd9, 0xe7, 0xec, 0x9f, 0xb5, 0xd7, 0xdf, 0x5e, 0x6b, 0xed, 0xb5,
+       0xcf, 0x78, 0x48, 0x3e, 0x29, 0xb8, 0x9c, 0x90, 0x4f, 0xe0, 0x1f, 0x2d,
+       0xff, 0x97, 0x41, 0x08, 0x7d, 0xd4, 0x57, 0x7a, 0x74, 0x12, 0xcf, 0xba,
+       0x98, 0x90, 0x9c, 0x3c, 0x2b, 0xde, 0x53, 0x4e, 0xc8, 0xd0, 0x3c, 0x2b,
+       0x45, 0x2a, 0xe9, 0x73, 0x53, 0x0b, 0x7b, 0xa5, 0xfe, 0x7e, 0xa2, 0x3c,
+       0x9c, 0x33, 0x2b, 0x04, 0xed, 0xda, 0xf2, 0xad, 0x10, 0xa1, 0x63, 0xb4,
+       0xe5, 0xcc, 0x23, 0x31, 0x18, 0x2b, 0xd6, 0x40, 0x48, 0x01, 0x21, 0xaa,
+       0x4e, 0xf0, 0x9f, 0x68, 0xef, 0x31, 0xe7, 0xea, 0xa4, 0x1c, 0x1f, 0xfd,
+       0xf5, 0x13, 0xf1, 0x5e, 0x21, 0xa4, 0xdd, 0x2c, 0xce, 0x86, 0x7e, 0xee,
+       0xf1, 0x09, 0x49, 0x12, 0x72, 0x89, 0xbd, 0x2e, 0x13, 0x22, 0xc6, 0xa4,
+       0xfd, 0x7c, 0x02, 0xde, 0x12, 0xfa, 0x20, 0x8f, 0x10, 0x7f, 0x95, 0x9c,
+       0xbc, 0xa2, 0x88, 0xc2, 0x5d, 0x92, 0x4c, 0x41, 0xdd, 0x08, 0x33, 0xb8,
+       0x0f, 0x17, 0xbd, 0x52, 0x33, 0x86, 0xae, 0x63, 0x5d, 0xb5, 0x1c, 0xf1,
+       0x86, 0xa1, 0xf7, 0xad, 0x84, 0x4c, 0x26, 0x64, 0x05, 0x8c, 0x45, 0xeb,
+       0xeb, 0x26, 0x76, 0xd7, 0x8c, 0xc9, 0x83, 0xf7, 0x6a, 0x04, 0xde, 0xce,
+       0x54, 0xf6, 0xb6, 0x6a, 0xb4, 0xbd, 0x51, 0x42, 0xb0, 0x7d, 0x70, 0x62,
+       0x3c, 0xa5, 0x61, 0x3f, 0xcb, 0x28, 0xa4, 0xfd, 0x72, 0x18, 0x08, 0x24,
+       0xa7, 0x6c, 0x51, 0x2d, 0x09, 0x12, 0x62, 0xce, 0xd0, 0xfa, 0xe1, 0xc2,
+       0xff, 0xb7, 0x70, 0xfd, 0x06, 0x6f, 0xa7, 0x97, 0x38, 0xdf, 0x1b, 0x64,
+       0xfd, 0x1f, 0x95, 0x09, 0x50, 0xeb, 0x25, 0xd1, 0x8b, 0xe8, 0xf8, 0x53,
+       0x5d, 0xef, 0xcb, 0x66, 0xbd, 0x0d, 0xe3, 0x1a, 0x84, 0x3e, 0x2f, 0xe3,
+       0xcf, 0xe9, 0xba, 0xee, 0x87, 0x3f, 0x0a, 0x09, 0xf9, 0x12, 0x09, 0xe4,
+       0x9d, 0xc8, 0xa2, 0x7f, 0x5f, 0x4a, 0x2e, 0x05, 0x3c, 0x90, 0x9a, 0x5c,
+       0x42, 0xa6, 0x9c, 0x8d, 0xbf, 0x7e, 0xbc, 0xc5, 0x91, 0xbe, 0x84, 0x30,
+       0xba, 0x68, 0xa4, 0xef, 0x1f, 0xd2, 0x41, 0xe7, 0x74, 0xb8, 0x62, 0x46,
+       0x4f, 0xa7, 0x44, 0xd7, 0xed, 0x8b, 0xc8, 0xc4, 0x4b, 0x1f, 0xcd, 0x52,
+       0x5e, 0xd4, 0x8b, 0x01, 0x2f, 0x47, 0x15, 0xc4, 0xc3, 0xba, 0x3a, 0x86,
+       0xe7, 0x75, 0x33, 0xe4, 0x64, 0x5c, 0xc2, 0x75, 0xd6, 0x16, 0xd2, 0xfe,
+       0xa3, 0x09, 0xc3, 0x63, 0xce, 0xf8, 0x62, 0x89, 0x14, 0x13, 0xb2, 0xb1,
+       0x85, 0xd6, 0xc7, 0x9d, 0x8d, 0xe7, 0xec, 0x92, 0x84, 0x05, 0xf4, 0xf7,
+       0x95, 0x10, 0x09, 0xf8, 0x2a, 0x9b, 0x3e, 0x1b, 0x42, 0xd7, 0x95, 0x3d,
+       0x35, 0x85, 0x7c, 0x33, 0xba, 0x8a, 0xe1, 0x93, 0xdc, 0xcd, 0xf0, 0x11,
+       0xa7, 0xff, 0xfb, 0xa4, 0xb8, 0x1f, 0x9f, 0xd9, 0x02, 0x9f, 0x11, 0x27,
+       0xbe, 0xb2, 0x39, 0x3e, 0x73, 0x6a, 0x6c, 0xf8, 0x82, 0xe7, 0x55, 0x14,
+       0x8f, 0x13, 0xe0, 0xbd, 0x13, 0x8f, 0x49, 0xf8, 0x83, 0xe2, 0xab, 0x5e,
+       0xe0, 0x31, 0x9f, 0x8c, 0x45, 0x3c, 0xc6, 0x73, 0x11, 0xbf, 0x03, 0xe1,
+       0xf1, 0x0a, 0x8a, 0x83, 0x2c, 0x0a, 0xbf, 0xff, 0x55, 0x6f, 0xd2, 0x5b,
+       0xd4, 0x8f, 0x57, 0xc1, 0x17, 0x02, 0xaf, 0x26, 0xc7, 0xeb, 0x86, 0x99,
+       0xbd, 0x3a, 0x30, 0xc3, 0x46, 0x8b, 0xf1, 0x39, 0x21, 0x29, 0x49, 0x0e,
+       0xe1, 0x78, 0x92, 0x5c, 0x85, 0xeb, 0xc3, 0xb2, 0x03, 0xf0, 0xe6, 0xc5,
+       0xfe, 0xf8, 0x5e, 0xa7, 0x30, 0x1b, 0x7c, 0x9e, 0x30, 0x9d, 0xc7, 0x5f,
+       0x96, 0x40, 0xfc, 0xeb, 0x14, 0x1d, 0x43, 0x24, 0xe0, 0x53, 0x43, 0x52,
+       0x81, 0xaf, 0x81, 0x4f, 0xd3, 0xcc, 0xbb, 0x4e, 0x4f, 0xea, 0x12, 0x6d,
+       0xbf, 0x69, 0xaa, 0x4c, 0x80, 0x5e, 0xeb, 0x2c, 0x99, 0x84, 0x69, 0xfd,
+       0x74, 0x99, 0x9a, 0x54, 0x00, 0xee, 0xb8, 0xd5, 0x1d, 0xb2, 0xf1, 0xa9,
+       0x01, 0xf8, 0xa7, 0xf8, 0xba, 0x8f, 0xe3, 0x47, 0x1b, 0x21, 0x3b, 0xf0,
+       0xa9, 0xe6, 0xf9, 0x5d, 0x7c, 0xee, 0x5c, 0xc7, 0xa6, 0xbe, 0xf5, 0x59,
+       0x7c, 0x5d, 0x6c, 0x1d, 0xa4, 0x3b, 0xd9, 0x01, 0x70, 0x9c, 0x99, 0x29,
+       0x93, 0x75, 0xd2, 0xc0, 0xe3, 0x0e, 0x84, 0x27, 0x31, 0xee, 0x80, 0xf0,
+       0xf5, 0x98, 0xbe, 0x12, 0x98, 0xf7, 0x05, 0x25, 0xb2, 0x8e, 0xf2, 0xda,
+       0xba, 0x70, 0xb2, 0x43, 0xa6, 0xf8, 0xda, 0x38, 0x83, 0xe1, 0xe3, 0x6c,
+       0xfa, 0x7e, 0xc6, 0xf9, 0x7a, 0x7b, 0xf5, 0x92, 0x4a, 0xdb, 0x7c, 0x91,
+       0x5e, 0xdd, 0x2c, 0xff, 0x02, 0xe6, 0x21, 0x39, 0xce, 0x75, 0x55, 0x99,
+       0x3e, 0x33, 0xad, 0xfe, 0x3c, 0xbf, 0x79, 0x88, 0xb9, 0x60, 0x74, 0x34,
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+       0xc1, 0xe4, 0xa9, 0x9d, 0xf3, 0x3b, 0xc8, 0xcd, 0x1c, 0x5a, 0x9f, 0x77,
+       0x7d, 0x7a, 0x38, 0x37, 0xcd, 0xd4, 0x86, 0x31, 0xbb, 0xc5, 0x2c, 0x44,
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+       0x4d, 0x40, 0xdf, 0x3e, 0x72, 0xf7, 0x0a, 0x0b, 0xe8, 0x78, 0x7a, 0x04,
+       0x5d, 0x7a, 0x1a, 0x3b, 0x41, 0x94, 0xaa, 0x25, 0x3b, 0xec, 0x14, 0x7d,
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+       0x6e, 0x48, 0x8f, 0x68, 0x08, 0xe8, 0xb1, 0x98, 0x44, 0x77, 0x42, 0xff,
+       0x40, 0x65, 0x94, 0xc5, 0x2b, 0x07, 0x09, 0x47, 0x26, 0xfe, 0x0f, 0x87,
+       0x98, 0xde, 0x0a, 0x73, 0x7e, 0x6f, 0x8f, 0x50, 0x7e, 0x97, 0xfa, 0xe5,
+       0xc1, 0xcf, 0xe5, 0xa1, 0x9d, 0xbf, 0x3f, 0x5d, 0x49, 0xd0, 0xbf, 0x68,
+       0xcf, 0xab, 0x30, 0xd3, 0xed, 0x17, 0x82, 0xdf, 0x05, 0xff, 0x0b, 0x7d,
+       0xe8, 0x6e, 0x77, 0xf8, 0x53, 0xf0, 0xf9, 0x78, 0x5a, 0x96, 0x12, 0x13,
+       0xfd, 0x9a, 0x0f, 0x49, 0xec, 0x39, 0xc0, 0x03, 0x5d, 0x3d, 0xca, 0x9f,
+       0x16, 0xea, 0x42, 0xff, 0x4e, 0xc8, 0x55, 0x6d, 0xe4, 0xd8, 0x8c, 0x21,
+       0x10, 0x47, 0xad, 0x0c, 0x57, 0x28, 0xb6, 0xfd, 0xfa, 0x7d, 0xce, 0x77,
+       0x0b, 0x74, 0xeb, 0x97, 0xd0, 0x7f, 0xde, 0xf5, 0x0b, 0xda, 0xf3, 0x29,
+       0x1e, 0xc6, 0xdd, 0x4d, 0x22, 0xa0, 0x66, 0xaf, 0xbd, 0x7e, 0x01, 0xb1,
+       0xf3, 0xfb, 0xaf, 0xfb, 0xda, 0x47, 0x5f, 0x42, 0xf9, 0xba, 0xbb, 0x1b,
+       0xdd, 0xd2, 0x81, 0xfa, 0x75, 0xf3, 0xf5, 0x5d, 0x2d, 0x45, 0x5f, 0xb3,
+       0xf3, 0x21, 0x1d, 0xe7, 0x75, 0x1c, 0xa7, 0xa4, 0x3b, 0x2e, 0xdb, 0xf4,
+       0x4e, 0x0e, 0xc7, 0xb3, 0x32, 0xb3, 0x8f, 0x3f, 0x4d, 0x10, 0xcd, 0x9a,
+       0xdb, 0x12, 0x2a, 0xd0, 0xa7, 0xa2, 0x36, 0xa2, 0x48, 0xb6, 0x75, 0x5c,
+       0x5b, 0xe7, 0xb4, 0xe7, 0x29, 0xbf, 0xbf, 0x03, 0xe3, 0xba, 0xf9, 0x74,
+       0x1e, 0x69, 0xf6, 0x90, 0xf3, 0xd8, 0x3f, 0x46, 0x49, 0xb1, 0x5e, 0x80,
+       0xb7, 0xb6, 0xa4, 0xbb, 0x0d, 0xe0, 0xd3, 0x42, 0x51, 0xf4, 0xf7, 0x28,
+       0xdc, 0xa7, 0xe1, 0xf9, 0x17, 0x00, 0xf7, 0x27, 0xe7, 0x82, 0xfb, 0x1d,
+       0x88, 0x75, 0x80, 0xde, 0x8c, 0x54, 0x5b, 0x43, 0xc2, 0x08, 0x9f, 0xaa,
+       0x5c, 0x02, 0x7e, 0x54, 0xaa, 0x2d, 0x3f, 0x0c, 0x78, 0x3f, 0xa6, 0x02,
+       0xde, 0x29, 0x9e, 0x35, 0xc5, 0x86, 0xe7, 0xc1, 0xca, 0xf9, 0xfd, 0x7c,
+       0xbf, 0x18, 0x48, 0xde, 0xdb, 0xe0, 0x0f, 0xb4, 0x97, 0x63, 0x79, 0x0a,
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+       0xe3, 0x97, 0xc2, 0x6e, 0x0e, 0x86, 0x08, 0xc6, 0x59, 0x73, 0x6a, 0x7b,
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+       0x5e, 0xbe, 0xb7, 0xa5, 0x4c, 0xc4, 0x6b, 0x11, 0xee, 0x21, 0x22, 0xde,
+       0x5b, 0xcb, 0xec, 0x7b, 0x11, 0x17, 0x16, 0x70, 0xd1, 0xfe, 0x3a, 0x0f,
+       0xb6, 0x3a, 0xda, 0x93, 0x90, 0x0d, 0x6f, 0xc5, 0xb6, 0xfe, 0x61, 0xa6,
+       0x6f, 0x06, 0xea, 0x9f, 0x55, 0xe9, 0xc4, 0x7b, 0x5f, 0x7f, 0x6b, 0x70,
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+       0xdc, 0x63, 0x3d, 0xd7, 0x55, 0x1f, 0xe6, 0x6a, 0x5f, 0xec, 0x7a, 0x7f,
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+       0x91, 0xf3, 0xe2, 0x22, 0x78, 0xd5, 0xa3, 0x48, 0xea, 0x09, 0x98, 0x47,
+       0xc4, 0xb7, 0x48, 0x6a, 0x82, 0xdd, 0x8f, 0xfd, 0xbd, 0x11, 0xfb, 0x1d,
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+       0x05, 0x61, 0x7f, 0x13, 0xcf, 0x4f, 0x4a, 0x6f, 0x04, 0xc7, 0x87, 0xa9,
+       0x7d, 0xa8, 0xa5, 0x96, 0xb3, 0x78, 0x50, 0x02, 0xe5, 0xc6, 0x4f, 0xd4,
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+       0xae, 0x97, 0xd0, 0xe7, 0x36, 0x7d, 0xe5, 0x25, 0x51, 0xa4, 0xb3, 0x36,
+       0xc2, 0xf9, 0x9c, 0x24, 0x98, 0x1c, 0x96, 0x40, 0x80, 0x8a, 0x8e, 0x17,
+       0xdf, 0xa4, 0xa1, 0xbd, 0x17, 0x1f, 0x49, 0x92, 0x63, 0x41, 0x9e, 0xf3,
+       0xd8, 0xf8, 0xd8, 0xbe, 0xb8, 0x1f, 0xde, 0x49, 0x2a, 0xd3, 0x4f, 0xa1,
+       0x68, 0xa2, 0x1a, 0x64, 0x78, 0x58, 0x5d, 0xd7, 0x61, 0x28, 0xdd, 0x78,
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+       0xa7, 0xbe, 0x32, 0x49, 0xe9, 0x1f, 0x7f, 0xd7, 0xb7, 0x8d, 0x48, 0x2b,
+       0x6d, 0xb2, 0x0b, 0x80, 0xa0, 0xf5, 0xf8, 0xb7, 0xf5, 0x24, 0xc4, 0x37,
+       0x46, 0x41, 0xbc, 0x8e, 0x1d, 0x22, 0x60, 0xbc, 0x6e, 0x24, 0xe1, 0xff,
+       0x78, 0x5c, 0x6e, 0x04, 0xfc, 0x4d, 0xfb, 0x8d, 0x34, 0x8e, 0x62, 0xfc,
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+       0x10, 0x4f, 0xd9, 0xa8, 0x45, 0xc6, 0x22, 0x9e, 0x23, 0x88, 0x67, 0xea,
+       0x8f, 0xb7, 0x79, 0x2b, 0x80, 0x4d, 0x18, 0x7e, 0x57, 0xc1, 0xee, 0xcb,
+       0x9e, 0xab, 0x81, 0x5c, 0x38, 0x77, 0xe1, 0xf4, 0x00, 0xfd, 0x4b, 0x4b,
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+       0x36, 0xb7, 0x73, 0xcb, 0xd4, 0x22, 0x5c, 0x7f, 0x0e, 0xf7, 0x33, 0x09,
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+       0xc2, 0xb5, 0x8a, 0xf4, 0x09, 0xc4, 0x5f, 0xcd, 0xc1, 0xd9, 0x8b, 0xa1,
+       0x6f, 0x3a, 0xe9, 0x4a, 0xd4, 0x66, 0x32, 0xc7, 0xe6, 0x5f, 0x5e, 0xaf,
+       0x0a, 0x3f, 0x8f, 0xe1, 0x6b, 0x4c, 0x88, 0xad, 0x3f, 0xb4, 0x51, 0x6b,
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+       0x83, 0xeb, 0x4d, 0x88, 0x57, 0x4b, 0x71, 0x8a, 0xb7, 0xac, 0xc1, 0xe3,
+       0xcd, 0x54, 0xac, 0x6f, 0xaa, 0xb8, 0x4e, 0x82, 0xe3, 0xfe, 0x40, 0xb2,
+       0x6e, 0xb0, 0xd7, 0x55, 0x62, 0xdd, 0xa8, 0xe6, 0xf7, 0xd7, 0x7f, 0xad,
+       0x44, 0x17, 0xc2, 0xfb, 0xf8, 0x34, 0x52, 0xd6, 0x6c, 0xf4, 0x8f, 0x43,
+       0x9f, 0xdf, 0x0c, 0xed, 0xd2, 0x3c, 0x6f, 0x48, 0xd7, 0x7e, 0x1c, 0x8f,
+       0xdb, 0xd2, 0xfd, 0x19, 0xf7, 0xf1, 0x52, 0xae, 0x03, 0x86, 0x6e, 0x33,
+       0x65, 0xb0, 0x27, 0x8b, 0x3a, 0x57, 0xf8, 0xed, 0x79, 0x2e, 0xa5, 0x7c,
+       0xbf, 0x7e, 0xac, 0x73, 0x9f, 0x0f, 0xd6, 0xbb, 0xb5, 0xf1, 0xdc, 0xf6,
+       0xd1, 0x7d, 0x2d, 0xc8, 0xfc, 0x19, 0xdb, 0x05, 0xa5, 0xee, 0x28, 0xd0,
+       0x83, 0x5c, 0xa2, 0x92, 0xdd, 0x69, 0xce, 0xb1, 0x7f, 0xca, 0xf9, 0xbb,
+       0xaf, 0xbd, 0xcb, 0x3e, 0x9c, 0xd1, 0x16, 0xaf, 0x86, 0xfe, 0xb9, 0x75,
+       0x32, 0x81, 0x78, 0x34, 0xdd, 0xe7, 0xd1, 0xbe, 0x2b, 0xe2, 0x7e, 0xed,
+       0xe6, 0xa9, 0x71, 0x49, 0xa3, 0x72, 0xf8, 0xc0, 0x16, 0x82, 0x76, 0x72,
+       0x6e, 0xdb, 0x42, 0x9f, 0x7d, 0x3d, 0x85, 0x7c, 0x3d, 0x9b, 0x6b, 0x0b,
+       0xfc, 0x60, 0xb7, 0x6c, 0xaf, 0x5f, 0xf8, 0x55, 0xf4, 0x13, 0xa8, 0xfd,
+       0xaf, 0xa0, 0xdf, 0x1b, 0x5b, 0x07, 0xe3, 0x17, 0xd6, 0xb0, 0xf3, 0x7e,
+       0x37, 0x7c, 0xf7, 0xf2, 0xf5, 0x25, 0xea, 0x19, 0x9e, 0xdc, 0xef, 0xb3,
+       0x34, 0x12, 0x4b, 0x27, 0x87, 0x3f, 0x55, 0xf9, 0xf9, 0x83, 0x4a, 0xdd,
+       0xc7, 0x82, 0xfe, 0x73, 0x94, 0x7b, 0x0f, 0xdf, 0xf9, 0x8b, 0xf1, 0x74,
+       0xbe, 0xd2, 0x2a, 0x39, 0xe2, 0x0b, 0xf7, 0xc3, 0x39, 0xae, 0xcf, 0x6e,
+       0xea, 0x41, 0x7c, 0x65, 0x5d, 0xa6, 0x9a, 0xeb, 0x40, 0x0f, 0x77, 0x6a,
+       0x0e, 0x7b, 0x73, 0xfb, 0xb6, 0xfb, 0xb7, 0xd4, 0xc3, 0xb9, 0x1f, 0x7d,
+       0x0e, 0xea, 0xe0, 0xd1, 0x2f, 0x37, 0x0f, 0x8b, 0x52, 0xb8, 0x1e, 0xfb,
+       0xda, 0xa2, 0x17, 0x16, 0x03, 0xdf, 0xb7, 0xcb, 0x04, 0xf4, 0x91, 0x80,
+       0xc3, 0x28, 0x77, 0xda, 0xbb, 0x47, 0xfa, 0xe4, 0xcc, 0x39, 0x2f, 0x1d,
+       0xb7, 0x1a, 0xf1, 0x52, 0x7f, 0x6e, 0xff, 0xe9, 0xd3, 0xe2, 0x63, 0x0b,
+       0x97, 0xf3, 0x4c, 0x7c, 0xe2, 0xde, 0x57, 0xdd, 0x7c, 0x70, 0x3e, 0xfb,
+       0xc3, 0x55, 0xca, 0x67, 0x5f, 0xdf, 0x7e, 0x90, 0x43, 0x3a, 0x6e, 0x01,
+       0xf7, 0xfb, 0x86, 0xd6, 0x85, 0xa5, 0x1e, 0xa3, 0x5f, 0x8e, 0x84, 0x9f,
+       0x22, 0xe6, 0x29, 0xe0, 0x7c, 0x96, 0x5b, 0x7b, 0xbf, 0x0f, 0xf8, 0x6c,
+       0x4b, 0x5d, 0x05, 0xca, 0xcf, 0xe9, 0xda, 0x85, 0x12, 0xe8, 0x93, 0x4d,
+       0xd0, 0x32, 0x8d, 0x9e, 0x10, 0xf3, 0x65, 0x82, 0x27, 0xcb, 0x93, 0xc0,
+       0x7c, 0x89, 0x2d, 0xf5, 0xf7, 0x4b, 0xe9, 0xf0, 0x56, 0x18, 0x63, 0xf1,
+       0x22, 0xf7, 0xf3, 0x6a, 0x0f, 0xa3, 0xf3, 0x7a, 0x35, 0x21, 0x41, 0xff,
+       0x4c, 0xed, 0x46, 0x7b, 0xb8, 0xbe, 0xe6, 0x72, 0x55, 0xc8, 0xd7, 0x15,
+       0x9a, 0x9a, 0x8a, 0x02, 0xbe, 0x0a, 0x22, 0x2a, 0xb9, 0x87, 0xe2, 0xeb,
+       0x81, 0xda, 0x85, 0xd5, 0xa5, 0xc0, 0x77, 0x54, 0x0e, 0x21, 0xbe, 0x32,
+       0xa3, 0x86, 0xa0, 0xbd, 0x50, 0x68, 0xb1, 0x73, 0x22, 0x93, 0xe2, 0xeb,
+       0x69, 0xba, 0xef, 0x6d, 0xae, 0x27, 0x91, 0x14, 0x6d, 0xb7, 0xd9, 0xd2,
+       0xf0, 0x1c, 0xc6, 0x2d, 0x87, 0x6e, 0x7e, 0xdc, 0x5c, 0x7f, 0x6e, 0xfd,
+       0x42, 0x2c, 0x5b, 0x7b, 0xca, 0xff, 0x1e, 0x8f, 0xc1, 0xce, 0x73, 0x4b,
+       0x48, 0x09, 0xd8, 0x53, 0x0f, 0x0c, 0xe0, 0xbf, 0x0d, 0x16, 0xbf, 0xa1,
+       0x7a, 0x99, 0xc5, 0x4b, 0x67, 0x54, 0x0c, 0xa0, 0xcf, 0x5b, 0xcf, 0x37,
+       0x8e, 0x39, 0xef, 0xcb, 0xc0, 0x8f, 0x33, 0x06, 0x99, 0x07, 0xe0, 0xd2,
+       0x17, 0xe4, 0xd9, 0x2d, 0xb3, 0x4b, 0xf3, 0x20, 0x1e, 0x42, 0xf5, 0x05,
+       0x49, 0x87, 0x1f, 0xa7, 0x7e, 0x18, 0x08, 0x1f, 0x6e, 0xfc, 0x5f, 0x0c,
+       0xf8, 0xbc, 0xf0, 0x8b, 0xc3, 0xa7, 0xfb, 0x7d, 0x9e, 0x87, 0xc7, 0x01,
+       0x07, 0x89, 0x8f, 0xf5, 0x75, 0xc5, 0xff, 0x03, 0x52, 0x26, 0x33, 0xb5,
+       0x77, 0xaf, 0x47, 0xf4, 0x13, 0x79, 0x61, 0x5f, 0x21, 0xbd, 0x0a, 0xc8,
+       0xbf, 0x05, 0x1c, 0x3a, 0x06, 0xbc, 0x8a, 0x08, 0x96, 0x33, 0x48, 0x14,
+       0xcb, 0x63, 0x6a, 0x2c, 0xea, 0xa1, 0xed, 0x67, 0x91, 0x66, 0xac, 0xd7,
+       0x90, 0x04, 0x96, 0x8b, 0x55, 0x93, 0xd1, 0x99, 0xe7, 0xc1, 0x88, 0xf3,
+       0x6e, 0x75, 0x3a, 0xe3, 0xfb, 0x71, 0x97, 0x92, 0x24, 0x9c, 0x3b, 0x93,
+       0xa9, 0x73, 0xf9, 0x61, 0xb0, 0x6a, 0x9d, 0xd0, 0x09, 0x86, 0x52, 0x3f,
+       0x49, 0xe3, 0x57, 0x11, 0x72, 0x0f, 0x8e, 0x37, 0xdc, 0xb5, 0x1f, 0x8b,
+       0x38, 0xc5, 0xd0, 0xc6, 0x44, 0x6d, 0x05, 0x1d, 0x77, 0x78, 0x2d, 0xcb,
+       0xfb, 0x1c, 0x5e, 0xb5, 0xcf, 0xb1, 0x8f, 0x05, 0xb9, 0xfc, 0x88, 0xf1,
+       0xb6, 0x56, 0x0d, 0x6e, 0x7f, 0x7e, 0xd4, 0xb5, 0x3f, 0x3f, 0xaa, 0xf6,
+       0xe8, 0x40, 0x9f, 0x47, 0xab, 0xee, 0x69, 0x85, 0xed, 0x46, 0xcd, 0x7d,
+       0x27, 0x94, 0xae, 0xff, 0xb8, 0x4e, 0x27, 0x5e, 0x37, 0x7c, 0xdc, 0xe5,
+       0x8b, 0xa6, 0x81, 0x67, 0x6b, 0xfd, 0x01, 0x1f, 0xe4, 0x8d, 0x6d, 0xad,
+       0x4a, 0x9f, 0x17, 0xeb, 0x86, 0x23, 0xd3, 0xfb, 0x71, 0x19, 0xce, 0x99,
+       0xbe, 0xe2, 0x65, 0xe7, 0x4c, 0x5b, 0x73, 0xf4, 0x6f, 0xb0, 0x64, 0x9d,
+       0x95, 0x8e, 0xbc, 0x04, 0xa2, 0x18, 0x45, 0xf6, 0x79, 0xb7, 0x7e, 0x4c,
+       0x72, 0xa2, 0xe7, 0xd4, 0x27, 0x4e, 0x79, 0xd9, 0xe8, 0xe1, 0xf9, 0x21,
+       0x01, 0x12, 0x00, 0xfe, 0xcf, 0x84, 0x0f, 0x51, 0x7e, 0xd1, 0x78, 0x78,
+       0x6c, 0x5a, 0xf3, 0x92, 0x68, 0x9a, 0xfe, 0xa5, 0x5e, 0x26, 0x37, 0xed,
+       0x39, 0x24, 0x0e, 0xe7, 0xd2, 0x8f, 0xbd, 0xa6, 0x32, 0xfe, 0xe3, 0x7a,
+       0x78, 0xf2, 0x37, 0xc2, 0x49, 0xb0, 0x17, 0xda, 0x41, 0x49, 0x50, 0xfd,
+       0xfb, 0x58, 0x35, 0xe3, 0xcf, 0xc9, 0x39, 0xfc, 0xfd, 0x43, 0x61, 0xcc,
+       0xaf, 0x1a, 0xde, 0x49, 0xe2, 0x1a, 0xdd, 0xcf, 0x86, 0xbf, 0x5a, 0xff,
+       0x40, 0x0e, 0x6d, 0x77, 0x5f, 0x3d, 0xf5, 0x20, 0x6d, 0xcf, 0xef, 0xab,
+       0x7c, 0xa9, 0x03, 0xce, 0x89, 0x9f, 0x7a, 0x59, 0xc6, 0xb8, 0xee, 0x64,
+       0x5f, 0xb7, 0x1e, 0xa1, 0xf0, 0x54, 0xf1, 0x7d, 0x70, 0x6b, 0xfd, 0x4b,
+       0x98, 0x9f, 0x1c, 0xdf, 0xa6, 0x46, 0xc6, 0xa2, 0x7e, 0x97, 0x88, 0x34,
+       0x19, 0xbd, 0x79, 0xa4, 0x87, 0x80, 0xf7, 0x19, 0x8f, 0xca, 0xe8, 0x56,
+       0x79, 0xbf, 0x2f, 0x0c, 0xfb, 0x57, 0xb8, 0x47, 0x8f, 0x50, 0xfc, 0xdc,
+       0x3e, 0xe5, 0x25, 0x3d, 0x4c, 0xcb, 0xfb, 0x46, 0xa4, 0x74, 0x58, 0xe7,
+       0xfa, 0xaa, 0xfb, 0x91, 0xcf, 0xf7, 0xd5, 0x17, 0x7f, 0xbd, 0x14, 0xd1,
+       0xea, 0xcc, 0x3b, 0x99, 0xa5, 0x4c, 0xed, 0xb6, 0xe8, 0x7c, 0xeb, 0xeb,
+       0xd9, 0xb9, 0x5d, 0x4e, 0x4f, 0x4a, 0xf7, 0x42, 0x9c, 0xb5, 0x4e, 0x25,
+       0x57, 0x50, 0xf8, 0x82, 0x06, 0x5b, 0xef, 0x7d, 0xed, 0x24, 0x79, 0x8f,
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+       0xae, 0x02, 0x57, 0xde, 0x9b, 0x59, 0x39, 0xeb, 0x5d, 0xc8, 0x67, 0x31,
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+       0xff, 0xd6, 0x10, 0x1d, 0xc7, 0xa6, 0xa7, 0xae, 0xf4, 0xb2, 0xf9, 0x45,
+       0x49, 0x52, 0x9f, 0xa0, 0xdf, 0x3a, 0x9c, 0x9f, 0xe7, 0x4e, 0x59, 0x7e,
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+       0xf1, 0xfe, 0x79, 0x97, 0xfb, 0x5e, 0x94, 0xed, 0x3e, 0x15, 0x15, 0xf1,
+       0xc3, 0x77, 0x96, 0xc6, 0xa1, 0xfd, 0xc3, 0x8b, 0x59, 0x9e, 0xf2, 0xc3,
+       0x13, 0x09, 0xfa, 0x11, 0x0f, 0xe7, 0xb3, 0xbc, 0xfc, 0xbe, 0x78, 0x16,
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+       0xd3, 0xb0, 0xfb, 0x55, 0xc2, 0xde, 0x13, 0xf7, 0xac, 0x56, 0xa9, 0x7c,
+       0x7e, 0x8b, 0x24, 0x5b, 0x69, 0xff, 0x87, 0xcb, 0x59, 0x7d, 0xeb, 0x0c,
+       0x92, 0x94, 0x8b, 0x6c, 0xf7, 0xaf, 0xca, 0x52, 0x78, 0x0f, 0x08, 0x0c,
+       0x5b, 0x88, 0xc3, 0xf6, 0xdf, 0x1f, 0xb3, 0xc8, 0xca, 0x0a, 0x5b, 0x1e,
+       0xc6, 0xca, 0x14, 0xe6, 0x19, 0xa8, 0x3c, 0x5f, 0x84, 0x22, 0x84, 0x38,
+       0xf2, 0x31, 0x5c, 0xf7, 0xb6, 0xc4, 0xb9, 0xe1, 0x35, 0x11, 0x6b, 0x26,
+       0xa8, 0xb9, 0xa2, 0x4a, 0x76, 0x8e, 0x57, 0x14, 0x75, 0xfa, 0x0f, 0x8d,
+       0x70, 0x99, 0x8b, 0xb6, 0xff, 0x2d, 0xd7, 0x93, 0x66, 0x65, 0xfa, 0x7b,
+       0x35, 0x7b, 0x75, 0x16, 0x97, 0x15, 0xf9, 0x9a, 0x57, 0xf3, 0xf5, 0x0b,
+       0xbc, 0x55, 0x70, 0x7a, 0x6e, 0x98, 0xf3, 0xc7, 0xee, 0xe9, 0x74, 0x9d,
+       0x2f, 0x4c, 0xf5, 0x60, 0xfe, 0xe8, 0x0b, 0x47, 0x39, 0x1e, 0xa7, 0x2a,
+       0x49, 0x76, 0x6e, 0x4e, 0x3c, 0xe9, 0xee, 0xe3, 0x64, 0x8a, 0xb3, 0x19,
+       0x9d, 0xcd, 0x47, 0x7c, 0x14, 0x3f, 0xd7, 0xbc, 0x48, 0x22, 0x40, 0xc6,
+       0xc0, 0x36, 0xab, 0x3d, 0x8c, 0x71, 0xb5, 0x8f, 0x91, 0xff, 0x30, 0xae,
+       0x46, 0xe7, 0xbd, 0x66, 0x5b, 0x42, 0x05, 0xfe, 0x9b, 0xdd, 0x19, 0x9e,
+       0x0e, 0xf1, 0xc0, 0xab, 0x5f, 0x0c, 0xaf, 0x82, 0xef, 0x0a, 0x8c, 0xeb,
+       0x24, 0x11, 0x0b, 0xd0, 0xfb, 0xf1, 0xb7, 0x70, 0x9c, 0xdc, 0x36, 0x12,
+       0x49, 0x32, 0x52, 0xb5, 0x9a, 0x2c, 0xde, 0xe7, 0x8c, 0xcf, 0x89, 0x7b,
+       0xbf, 0x3c, 0x3e, 0x07, 0x61, 0x6a, 0xbb, 0x7f, 0x39, 0x9b, 0xaf, 0xbb,
+       0xa2, 0xcd, 0x6c, 0x87, 0x23, 0xbb, 0x8a, 0x19, 0x5e, 0x87, 0xfd, 0x3a,
+       0x9b, 0xfb, 0x99, 0xff, 0x64, 0x79, 0x1d, 0x7e, 0xe6, 0x6c, 0x7e, 0x7f,
+       0x7a, 0xb6, 0xcb, 0xcf, 0xec, 0xd4, 0x9d, 0xf1, 0x3a, 0xa3, 0x33, 0x3a,
+       0x13, 0xe2, 0xdc, 0xca, 0xd5, 0xc7, 0x2c, 0x1d, 0xe0, 0x8f, 0x4a, 0x26,
+       0x5c, 0x4b, 0xb9, 0x21, 0xba, 0x49, 0x85, 0x73, 0xe4, 0xd9, 0xdb, 0x9a,
+       0xd9, 0xbd, 0xda, 0x0c, 0xe7, 0x5a, 0xd9, 0x0f, 0xcd, 0x0d, 0xd8, 0xed,
+       0x77, 0x71, 0x8e, 0xfd, 0xab, 0x6d, 0xe7, 0xb6, 0xd7, 0x45, 0x9c, 0x41,
+       0xc4, 0x1d, 0x5e, 0xe1, 0xf7, 0xf1, 0x5e, 0xe6, 0x79, 0xc5, 0x7d, 0xf9,
+       0x28, 0x9c, 0x3f, 0x72, 0xaf, 0x96, 0x1c, 0x7c, 0xd2, 0xa9, 0x33, 0x3d,
+       0xd2, 0x09, 0x7c, 0x92, 0xff, 0x9f, 0x7c, 0xf2, 0x79, 0xf3, 0xc9, 0x6f,
+       0x74, 0x67, 0xfc, 0xa1, 0x13, 0xde, 0x51, 0x79, 0x2c, 0x8d, 0xa4, 0x3f,
+       0x9f, 0x6f, 0xd0, 0xb5, 0xff, 0x94, 0xd7, 0x2f, 0x80, 0x0e, 0x41, 0x5f,
+       0x7a, 0x3a, 0x90, 0xc6, 0x6c, 0x47, 0x1e, 0xb1, 0xc8, 0xa7, 0x72, 0xe3,
+       0x6d, 0x0d, 0xc7, 0x9b, 0xa8, 0xeb, 0x19, 0xee, 0xbd, 0x8c, 0xf0, 0xf1,
+       0x7d, 0xd6, 0xed, 0xd7, 0xbf, 0x11, 0xab, 0x86, 0x75, 0x89, 0x38, 0x0d,
+       0x21, 0x77, 0xb9, 0xce, 0x35, 0xa7, 0x46, 0xce, 0x15, 0x97, 0x50, 0xc4,
+       0xb9, 0x8f, 0xfc, 0x86, 0x02, 0xeb, 0x29, 0xf3, 0x71, 0xfd, 0xa3, 0x12,
+       0x15, 0xc7, 0x77, 0xad, 0x03, 0xe5, 0xbe, 0x00, 0xf2, 0x0d, 0x39, 0x0c,
+       0xae, 0xf1, 0xda, 0x41, 0x5f, 0x78, 0xfb, 0xd7, 0xe5, 0x29, 0x89, 0x5a,
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+       0x7f, 0x34, 0x1d, 0xeb, 0xb6, 0x7c, 0x6c, 0xbf, 0x59, 0xc7, 0xef, 0x0b,
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+       0xe3, 0x5f, 0xa7, 0x3b, 0x25, 0x8c, 0x7f, 0xbd, 0x2d, 0x25, 0x35, 0x48,
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+       0x52, 0x48, 0x6f, 0x5c, 0x02, 0xff, 0x68, 0x2a, 0x21, 0x6f, 0xd9, 0xe8,
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+       0x17, 0x24, 0xd9, 0x77, 0x10, 0xcc, 0xc8, 0x04, 0x80, 0x53, 0x09, 0x1d,
+       0x2d, 0x28, 0xb1, 0xed, 0x73, 0x5e, 0xbe, 0x3e, 0xef, 0xf4, 0x85, 0xfc,
+       0x7b, 0x49, 0x16, 0xf7, 0x6f, 0x22, 0xc4, 0xee, 0xdf, 0x7a, 0xf9, 0xba,
+       0x40, 0x87, 0xbf, 0x65, 0xeb, 0xef, 0x09, 0x39, 0xeb, 0x8a, 0xf9, 0xf9,
+       0xae, 0x43, 0xd8, 0xdd, 0xd2, 0x33, 0x7f, 0x39, 0x01, 0x74, 0x5c, 0xf5,
+       0xa4, 0x07, 0xe3, 0x9e, 0xd3, 0x9f, 0xf4, 0xa4, 0x2e, 0xa7, 0xf5, 0x65,
+       0xdb, 0x25, 0xdc, 0x67, 0xe4, 0x43, 0x4c, 0xaf, 0x7f, 0xb0, 0x4b, 0x42,
+       0xb9, 0x4f, 0x05, 0x34, 0xd4, 0x03, 0xef, 0x9b, 0x3a, 0xd6, 0x9b, 0xbc,
+       0xdd, 0x1b, 0xbe, 0x44, 0xeb, 0xbd, 0x4f, 0x2a, 0x64, 0x07, 0xa2, 0xa5,
+       0x0e, 0xbf, 0x2f, 0x75, 0x42, 0xec, 0xa7, 0x07, 0x58, 0x7d, 0x11, 0x77,
+       0x90, 0x96, 0x6d, 0x3f, 0x3c, 0x1f, 0xc6, 0x6b, 0x38, 0xe0, 0x25, 0xb0,
+       0x4f, 0x2c, 0xfb, 0xc9, 0x2d, 0x57, 0x7d, 0x89, 0xd6, 0x6f, 0xa1, 0x7c,
+       0x0c, 0x4d, 0x96, 0xed, 0x6e, 0xd5, 0x86, 0xd1, 0xfa, 0xe2, 0xa4, 0xd4,
+       0x05, 0xf5, 0x53, 0xd3, 0x08, 0xf2, 0x59, 0x3c, 0x57, 0x4b, 0x42, 0x5e,
+       0xcb, 0xa9, 0x60, 0x77, 0xc1, 0x35, 0x06, 0xee, 0x63, 0x24, 0x3c, 0x0e,
+       0xce, 0xb7, 0xbb, 0x0b, 0xae, 0xa6, 0xfc, 0xb8, 0x24, 0xf9, 0xc4, 0x2c,
+       0xe8, 0xb7, 0x64, 0xaf, 0x04, 0x91, 0x54, 0xba, 0x8e, 0xdd, 0xcf, 0x17,
+       0x52, 0xb8, 0x96, 0x7d, 0x5f, 0xc2, 0xfd, 0x71, 0xe9, 0x9e, 0x2c, 0x12,
+       0xb6, 0xe1, 0xf3, 0x04, 0x5d, 0xca, 0xe5, 0xf4, 0xfd, 0x0a, 0xba, 0x4e,
+       0xd0, 0x87, 0xb7, 0x90, 0xc4, 0x2c, 0xa0, 0xd7, 0xb2, 0xdd, 0x9b, 0x34,
+       0xfb, 0x3e, 0xf7, 0x5e, 0x4b, 0x19, 0xa6, 0x7e, 0x88, 0xfa, 0xb2, 0xef,
+       0xd3, 0x79, 0x68, 0xbf, 0xe5, 0x3f, 0x94, 0x22, 0xb0, 0xc4, 0xe5, 0x90,
+       0xef, 0x00, 0xfb, 0xe5, 0x4f, 0x7c, 0x75, 0x3b, 0x0d, 0x58, 0x5f, 0xab,
+       0x56, 0x1a, 0x80, 0x75, 0xad, 0xd1, 0xa0, 0xdd, 0x2d, 0xc9, 0x05, 0x4f,
+       0xf9, 0xc2, 0x00, 0xdf, 0x76, 0x6d, 0x16, 0x7d, 0xbf, 0x64, 0xdb, 0x76,
+       0x6d, 0x51, 0x39, 0xe0, 0x8d, 0xdc, 0x08, 0xfb, 0xea, 0xd2, 0x3d, 0x17,
+       0x92, 0xb0, 0x8d, 0xae, 0x27, 0x3a, 0x15, 0xf4, 0x17, 0x56, 0xe4, 0xe8,
+       0x3b, 0xf0, 0x7b, 0xa2, 0x86, 0x15, 0x9a, 0x9b, 0x26, 0x1e, 0xf2, 0x5e,
+       0x0b, 0x71, 0xc0, 0xb5, 0x84, 0xeb, 0x0d, 0xea, 0xf7, 0x69, 0x73, 0x6c,
+       0xed, 0x9f, 0xca, 0xca, 0x41, 0x3e, 0x5d, 0xba, 0x47, 0x71, 0xcc, 0x23,
+       0xe8, 0x1f, 0x3f, 0x46, 0xd8, 0x3d, 0xb4, 0x9f, 0x05, 0xf0, 0x1e, 0x9a,
+       0xa0, 0x9f, 0xd8, 0xaf, 0x04, 0xfd, 0x56, 0x88, 0x0f, 0xe5, 0xa9, 0xbd,
+       0x93, 0xd3, 0xc1, 0x03, 0xdf, 0xd5, 0x02, 0x78, 0x12, 0xd4, 0xbf, 0x81,
+       0xf2, 0xfe, 0x96, 0x10, 0x96, 0x0f, 0xb6, 0x84, 0x91, 0x4e, 0x9b, 0x01,
+       0x8f, 0xe3, 0x58, 0x5e, 0x0a, 0x3c, 0xa7, 0x72, 0x8b, 0xdf, 0xf3, 0x0b,
+       0x5a, 0xf0, 0xa1, 0x29, 0xb8, 0x8f, 0x62, 0x55, 0x43, 0xfe, 0x65, 0x6e,
+       0x94, 0xd5, 0x0b, 0xae, 0x8f, 0x49, 0xe1, 0x73, 0xd8, 0xe9, 0xa2, 0xdc,
+       0xec, 0x89, 0x2d, 0x00, 0x23, 0x67, 0x6a, 0xd6, 0xf7, 0x66, 0xaa, 0xd4,
+       0x1f, 0xdb, 0xac, 0xc5, 0x6e, 0x85, 0x90, 0xb5, 0xa9, 0xee, 0x98, 0x39,
+       0x83, 0xee, 0x79, 0x8d, 0x59, 0xd1, 0xc9, 0x59, 0xb6, 0x73, 0xbf, 0xd5,
+       0xfc, 0x3b, 0x32, 0x17, 0x67, 0x85, 0x71, 0xfd, 0xab, 0x0b, 0x35, 0xc4,
+       0xf7, 0xe6, 0x1b, 0x26, 0xef, 0xe4, 0xf1, 0x27, 0xdc, 0x27, 0x37, 0xdf,
+       0xb0, 0xe8, 0x51, 0x88, 0x8f, 0xd3, 0xfe, 0x5f, 0xc9, 0x02, 0xff, 0x82,
+       0x9f, 0xff, 0x65, 0xea, 0x5f, 0x30, 0xbf, 0xca, 0xd1, 0xbf, 0x60, 0x7e,
+       0x83, 0xe8, 0x3f, 0x0b, 0xfb, 0xeb, 0xe7, 0xee, 0xbf, 0x79, 0xfe, 0x65,
+       0xce, 0xf9, 0xe7, 0x2f, 0x11, 0xfd, 0xaf, 0x42, 0xf8, 0x8d, 0x73, 0xc3,
+       0x5f, 0x70, 0xe3, 0x54, 0xe7, 0xfc, 0x37, 0x36, 0x62, 0xff, 0x26, 0x2f,
+       0xa3, 0x6f, 0x6f, 0x8e, 0x8e, 0x79, 0xd6, 0x6d, 0xbe, 0x48, 0xca, 0x03,
+       0x74, 0x56, 0x09, 0x7e, 0x87, 0x5a, 0xcd, 0x2d, 0xdd, 0x01, 0xed, 0xc4,
+       0xbe, 0x43, 0x2d, 0x4b, 0x0b, 0xf2, 0xb6, 0x8d, 0xbd, 0x39, 0x15, 0xeb,
+       0x88, 0x9d, 0x8f, 0xa6, 0xcd, 0x07, 0x38, 0x02, 0x54, 0xba, 0xec, 0x7c,
+       0x94, 0x5d, 0xe5, 0x77, 0xc8, 0x55, 0x8e, 0x95, 0xeb, 0xa8, 0x0f, 0xa9,
+       0x19, 0xe6, 0x68, 0x9f, 0x1f, 0x2d, 0x76, 0xbc, 0x1f, 0x5a, 0x77, 0x81,
+       0x8b, 0x2f, 0x0d, 0xbc, 0xb7, 0x88, 0x75, 0x00, 0x0a, 0x0c, 0x73, 0x0a,
+       0xa7, 0x36, 0x4c, 0x43, 0x7d, 0x54, 0x3d, 0x8c, 0xd9, 0xc1, 0x77, 0x1c,
+       0xf2, 0x61, 0xfd, 0x8e, 0xcb, 0xd8, 0xfa, 0xee, 0x18, 0x66, 0xa0, 0x1c,
+       0x03, 0xcc, 0xe0, 0x97, 0xdf, 0xa1, 0xc5, 0x2e, 0xb6, 0x7f, 0x27, 0x96,
+       0xae, 0x4b, 0x82, 0xc3, 0x9c, 0x9b, 0x8d, 0xd8, 0x9d, 0xb0, 0x8e, 0xfe,
+       0xe7, 0x61, 0x19, 0x9e, 0xfb, 0x79, 0xbe, 0x93, 0xdf, 0x4b, 0x50, 0xdf,
+       0xad, 0x29, 0x9a, 0xbc, 0x33, 0x6e, 0xc3, 0x67, 0xc7, 0x48, 0xca, 0x0f,
+       0xb4, 0xde, 0x96, 0xa5, 0x31, 0xbc, 0x73, 0x3a, 0xac, 0x19, 0xb9, 0x28,
+       0x64, 0xb7, 0xd7, 0x57, 0x8f, 0xd4, 0xea, 0xc0, 0xdf, 0x80, 0xe7, 0x37,
+       0x19, 0x30, 0x5f, 0x74, 0x35, 0xcc, 0xd7, 0xa4, 0xf5, 0x96, 0x82, 0xdd,
+       0xe1, 0x9e, 0xc7, 0x5b, 0x5c, 0xe5, 0x98, 0x47, 0x1f, 0xd5, 0x80, 0xf3,
+       0x6c, 0xca, 0x62, 0xf1, 0x54, 0x31, 0x8f, 0x77, 0x54, 0x83, 0x6b, 0x1e,
+       0xbd, 0x6e, 0x07, 0x7f, 0xce, 0xe7, 0x79, 0x00, 0xf8, 0x2c, 0xd3, 0x3c,
+       0x6b, 0x8a, 0x2f, 0x73, 0xae, 0x67, 0xd4, 0x12, 0x9c, 0xe7, 0x61, 0xd7,
+       0x3c, 0x6b, 0x46, 0x2d, 0x71, 0xcd, 0xe3, 0x67, 0xeb, 0xa1, 0xcf, 0xf9,
+       0x3c, 0xc9, 0x73, 0xcd, 0xe3, 0x1d, 0x33, 0xd5, 0xb9, 0x9e, 0xd1, 0x8d,
+       0x38, 0xcf, 0x3f, 0xbb, 0xd7, 0x33, 0xba, 0xd1, 0x35, 0x8f, 0x81, 0xf3,
+       0xc0, 0x73, 0x98, 0x87, 0x1a, 0xbe, 0x61, 0xf8, 0x3e, 0x96, 0xe6, 0xed,
+       0x5d, 0x84, 0xf4, 0x7f, 0xc6, 0x87, 0x76, 0x8e, 0xe6, 0x8d, 0x3d, 0x86,
+       0x76, 0xce, 0xeb, 0x3e, 0xb4, 0x73, 0x68, 0x2b, 0x0b, 0xbf, 0xa3, 0x55,
+       0xc6, 0xfc, 0xdb, 0xdb, 0xb2, 0x72, 0x91, 0x3e, 0x67, 0xfc, 0x94, 0xfe,
+       0x86, 0x9d, 0xce, 0x71, 0x9e, 0x77, 0x10, 0x47, 0xbf, 0xf8, 0x66, 0x0e,
+       0x22, 0x49, 0x52, 0x88, 0xa8, 0x7e, 0x5b, 0xce, 0x79, 0xb0, 0x7e, 0xef,
+       0x9c, 0x51, 0xad, 0x50, 0x1e, 0x98, 0x1e, 0x5a, 0x00, 0xfe, 0xe8, 0x83,
+       0x01, 0x8c, 0xe3, 0x7d, 0x70, 0x60, 0xba, 0x76, 0x53, 0x1a, 0x7d, 0x74,
+       0x73, 0xc2, 0x73, 0xa2, 0xc7, 0xc6, 0xcf, 0x7d, 0x7a, 0x95, 0xc7, 0x63,
+       0x43, 0x59, 0xec, 0x1c, 0x52, 0xd4, 0x4f, 0xf0, 0xf8, 0xcf, 0x5b, 0x10,
+       0x27, 0xa2, 0xe5, 0xdb, 0x1e, 0x82, 0xfe, 0xd0, 0x71, 0x1e, 0x2f, 0xea,
+       0x87, 0xb7, 0x15, 0xfb, 0x9d, 0xe0, 0xe7, 0x7a, 0x27, 0xb6, 0xb1, 0x7d,
+       0xea, 0xcc, 0xa6, 0x63, 0xec, 0xbb, 0x39, 0x71, 0xf2, 0x72, 0xf9, 0x64,
+       0xf8, 0x1e, 0x0d, 0xfb, 0x77, 0x73, 0x22, 0xcb, 0xe1, 0x8f, 0x37, 0x71,
+       0x7a, 0xf4, 0xfe, 0xc4, 0x9b, 0xdc, 0x81, 0xf4, 0xb0, 0x86, 0xe3, 0x77,
+       0x7f, 0x3b, 0x87, 0x38, 0xe2, 0x85, 0xbf, 0x39, 0xf4, 0xb5, 0xe7, 0x59,
+       0xde, 0x1d, 0x19, 0x0e, 0xdf, 0xcb, 0xbb, 0xae, 0xe3, 0x89, 0xe7, 0xa0,
+       0xd9, 0x2b, 0xd2, 0x82, 0x91, 0x2b, 0xe8, 0x7a, 0xeb, 0xf6, 0x6f, 0xf2,
+       0x0c, 0xa7, 0xf5, 0x0f, 0x3c, 0x3d, 0xf3, 0x23, 0x86, 0x6d, 0x9c, 0x3a,
+       0x0f, 0xde, 0xbb, 0x17, 0x7e, 0xc8, 0x37, 0x62, 0x1e, 0x87, 0xfd, 0xfc,
+       0xcd, 0x06, 0x67, 0xfd, 0x06, 0x97, 0x3d, 0xfd, 0x46, 0x56, 0xb1, 0x38,
+       0x9f, 0x65, 0xf3, 0x86, 0x93, 0x1e, 0xa0, 0xd7, 0x3c, 0x38, 0x63, 0xa5,
+       0x24, 0xbc, 0x01, 0x4a, 0x4c, 0xbe, 0x33, 0x91, 0x5e, 0xf3, 0x4d, 0xd6,
+       0x57, 0xc0, 0xd3, 0x74, 0x97, 0x87, 0xa4, 0x70, 0xbf, 0xeb, 0xc9, 0xc7,
+       0x38, 0x67, 0x3c, 0x1f, 0xe3, 0x34, 0x31, 0xb1, 0x6f, 0xb9, 0xe0, 0x9b,
+       0xef, 0xd1, 0xad, 0x28, 0xa5, 0xe7, 0xfc, 0x3b, 0x15, 0xc4, 0xa3, 0x1b,
+       0xde, 0x9e, 0x43, 0x59, 0x96, 0x4c, 0xfd, 0x9c, 0x9e, 0xce, 0xff, 0xed,
+       0x81, 0xfb, 0x3b, 0x03, 0xc1, 0x7f, 0xe3, 0x4a, 0xe7, 0x7b, 0x12, 0xf7,
+       0x38, 0xbe, 0x43, 0x20, 0xf8, 0xe0, 0xda, 0xba, 0xea, 0x9d, 0xc7, 0x6d,
+       0xfc, 0xf1, 0x8d, 0xd8, 0xec, 0x9d, 0xc7, 0x1d, 0x78, 0x9a, 0xe3, 0xa8,
+       0xdf, 0xd0, 0xfc, 0x0d, 0x47, 0xfb, 0x1b, 0x57, 0x2e, 0x70, 0xbc, 0x5f,
+       0x10, 0x5f, 0xec, 0x78, 0x7f, 0x53, 0xc7, 0xad, 0x8e, 0xfa, 0xcd, 0x89,
+       0x3b, 0x1d, 0xed, 0x6f, 0xe9, 0x6c, 0x75, 0xbc, 0x5f, 0x9c, 0x5c, 0xeb,
+       0x78, 0xbf, 0x74, 0xcf, 0x26, 0x47, 0x7d, 0x59, 0xd7, 0x16, 0x47, 0xfb,
+       0xa6, 0x03, 0xdb, 0x1d, 0xef, 0xe5, 0x43, 0xe3, 0xff, 0x09, 0xfd, 0xc0,
+       0x5f, 0x29, 0x78, 0xcf, 0xf9, 0x43, 0xe3, 0xc4, 0x06, 0xb0, 0xdf, 0x3e,
+       0x34, 0xd9, 0x77, 0xfe, 0xdf, 0xe1, 0xe7, 0x77, 0xef, 0xf1, 0xef, 0xfd,
+       0x2c, 0x07, 0xde, 0x9b, 0x02, 0xf2, 0x33, 0x49, 0x07, 0xbf, 0xa1, 0xc9,
+       0x4f, 0xe5, 0x99, 0xda, 0x12, 0x13, 0x8c, 0xfc, 0xd5, 0x1d, 0x53, 0x41,
+       0x8f, 0x10, 0xfc, 0xa4, 0x46, 0x85, 0x31, 0x7c, 0x75, 0x9c, 0x3a, 0xbb,
+       0x53, 0xf8, 0xbd, 0x44, 0xa5, 0x53, 0x23, 0xa9, 0x21, 0x70, 0xbc, 0xd2,
+       0x1f, 0x87, 0xed, 0x55, 0xfa, 0xdf, 0xab, 0x3d, 0xf4, 0xfd, 0xa4, 0xcc,
+       0xef, 0x95, 0x4e, 0x35, 0xed, 0x7b, 0xb5, 0x47, 0x4d, 0x3b, 0xee, 0x29,
+       0xa9, 0xb7, 0x14, 0xec, 0xc7, 0xf8, 0x6b, 0xde, 0xb4, 0xf7, 0xbf, 0xfb,
+       0xe5, 0x92, 0x0c, 0x87, 0xfd, 0x22, 0xd3, 0xfb, 0x93, 0x32, 0x69, 0xb0,
+       0xfb, 0x6f, 0xf3, 0x0c, 0x16, 0x1f, 0x7a, 0x3e, 0x6b, 0xda, 0x3c, 0x03,
+       0xfc, 0x21, 0x8d, 0xc9, 0x7b, 0xe3, 0xbe, 0xc2, 0x69, 0xe0, 0x37, 0x34,
+       0x6a, 0xa9, 0xd2, 0x74, 0xe7, 0x36, 0x7d, 0xf3, 0x75, 0x49, 0xf8, 0x9d,
+       0xc0, 0x79, 0x06, 0x93, 0x97, 0xc5, 0x49, 0xe7, 0xf7, 0x6f, 0x97, 0xee,
+       0x19, 0xe3, 0x90, 0xfb, 0x57, 0xfd, 0xb1, 0x6b, 0x0c, 0xda, 0xee, 0xe4,
+       0x61, 0x85, 0x7d, 0x2f, 0x2f, 0xf5, 0xec, 0xa8, 0xaf, 0x5f, 0x04, 0xf3,
+       0x5b, 0xf3, 0xe0, 0x39, 0x39, 0x90, 0x8f, 0xfb, 0xe3, 0x2b, 0x2d, 0xd6,
+       0xce, 0xe3, 0xd4, 0x0f, 0x78, 0xb5, 0xa5, 0x06, 0xcb, 0x7f, 0x6d, 0x89,
+       0xee, 0x3c, 0x4e, 0x1d, 0xb5, 0x37, 0x5a, 0xea, 0xb0, 0xfe, 0xdb, 0x96,
+       0x18, 0x96, 0x3d, 0x2d, 0x0d, 0x58, 0xbe, 0xd5, 0xd2, 0x8c, 0xef, 0x8f,
+       0xb7, 0xac, 0xc4, 0xfa, 0x89, 0x96, 0x38, 0x96, 0xef, 0xb4, 0x74, 0x60,
+       0xf9, 0x5e, 0x4b, 0x02, 0xdf, 0x9f, 0x6c, 0xe9, 0xc4, 0xfa, 0x07, 0x2d,
+       0x49, 0x2c, 0x85, 0x1c, 0x08, 0x7b, 0x97, 0x44, 0xb9, 0x3d, 0x29, 0x0e,
+       0x4c, 0x08, 0xab, 0x9f, 0xe6, 0x6b, 0x50, 0x0a, 0x44, 0x1c, 0x33, 0x82,
+       0xdf, 0x8f, 0x3a, 0x6d, 0x9c, 0x29, 0x05, 0x3b, 0xfa, 0xf4, 0xab, 0x5e,
+       0xcc, 0xbb, 0xcd, 0x84, 0x27, 0x37, 0xdf, 0x65, 0xa6, 0x9f, 0x85, 0xfb,
+       0xfd, 0xa2, 0xa4, 0x33, 0xce, 0x2c, 0x4a, 0x9f, 0x9f, 0xd1, 0xc7, 0x27,
+       0x93, 0x1a, 0xc8, 0x91, 0x58, 0x3b, 0x56, 0xc3, 0x38, 0x9a, 0xff, 0x99,
+       0x0b, 0xd1, 0x1e, 0xa7, 0xcf, 0x55, 0xc2, 0xbe, 0xb7, 0x1c, 0xb1, 0x7f,
+       0x4f, 0xa2, 0x6f, 0x7c, 0x48, 0x1e, 0x1e, 0x3a, 0x30, 0x9d, 0x44, 0xfb,
+       0x13, 0xdf, 0xfb, 0xf7, 0xc9, 0x0b, 0xcb, 0x81, 0x3e, 0xc5, 0x88, 0x27,
+       0xff, 0xb3, 0x4a, 0x33, 0xa3, 0xdb, 0xce, 0xc8, 0xd7, 0x2f, 0x1a, 0x18,
+       0x7f, 0x68, 0xf3, 0x15, 0x9e, 0x8d, 0x47, 0xe9, 0x99, 0xdf, 0x8c, 0x82,
+       0xf8, 0xd4, 0xfb, 0xf9, 0x02, 0x9f, 0xdd, 0xa3, 0x20, 0xb8, 0xa5, 0x1a,
+       0xd1, 0x2d, 0xc0, 0x87, 0xa7, 0xf7, 0x7b, 0x71, 0x5d, 0xa7, 0x0f, 0x66,
+       0xb1, 0x7c, 0x14, 0x08, 0xaa, 0x0d, 0x22, 0xff, 0x75, 0xe9, 0x1e, 0x5f,
+       0xd2, 0xae, 0x1f, 0x96, 0x75, 0xe5, 0x24, 0x9d, 0xfa, 0xa2, 0x30, 0x69,
+       0xd7, 0x17, 0xa7, 0x8f, 0xee, 0x0c, 0x82, 0xdc, 0xaf, 0x08, 0x29, 0xc9,
+       0xe3, 0x93, 0x80, 0x3f, 0x2c, 0xce, 0x1f, 0x8c, 0xef, 0xc4, 0xf8, 0xcb,
+       0xba, 0x8a, 0x92, 0x86, 0x63, 0x1c, 0x67, 0xfd, 0x74, 0x42, 0xaa, 0xe9,
+       0xc2, 0xb8, 0x58, 0x38, 0xfb, 0xea, 0x34, 0xfe, 0x87, 0x28, 0x57, 0x84,
+       0x34, 0x9c, 0xe7, 0xbd, 0x3d, 0x63, 0x30, 0xff, 0x80, 0xfa, 0x89, 0xc9,
+       0xe3, 0x2c, 0xde, 0x99, 0x64, 0xf3, 0x86, 0x92, 0x76, 0xbe, 0x6c, 0x5c,
+       0x99, 0x95, 0x3c, 0x3e, 0xa4, 0x1f, 0xbe, 0x4c, 0xe3, 0x7e, 0xde, 0xf0,
+       0x11, 0xb2, 0x9f, 0xfc, 0x4e, 0xcf, 0x7c, 0x0f, 0x77, 0xa0, 0x92, 0xa8,
+       0xff, 0xa6, 0xe1, 0xf7, 0x2d, 0x0f, 0x7a, 0xce, 0xc0, 0xbe, 0xe3, 0xa5,
+       0xff, 0x7d, 0x82, 0xf9, 0x42, 0x2a, 0xd6, 0xc5, 0xb8, 0x4d, 0x5d, 0x4a,
+       0xdc, 0x0b, 0xf7, 0x78, 0xc9, 0x5e, 0xc7, 0x7c, 0xb4, 0x5f, 0x58, 0xf8,
+       0xe8, 0xf6, 0xef, 0xe6, 0x9c, 0x4d, 0x77, 0x67, 0x3e, 0xf8, 0x6f, 0x81,
+       0x97, 0x70, 0xdf, 0x66, 0xf7, 0xca, 0x63, 0x70, 0xaf, 0x9c, 0x8e, 0x77,
+       0x4a, 0x35, 0x3a, 0xa4, 0x8b, 0xfb, 0xef, 0x95, 0x37, 0x71, 0xbe, 0x5c,
+       0xa6, 0xf7, 0x68, 0x31, 0xfa, 0xe8, 0xfd, 0xfd, 0x63, 0xce, 0x99, 0x0f,
+       0xf2, 0x5e, 0xcb, 0x51, 0x53, 0x1d, 0x0b, 0x79, 0x04, 0x09, 0xfc, 0x60,
+       0x44, 0x43, 0xd7, 0xf8, 0x19, 0xa0, 0x1f, 0xdf, 0xdf, 0xbf, 0xaa, 0x00,
+       0xe2, 0x69, 0x4b, 0x95, 0xd3, 0x77, 0xa4, 0xbb, 0x2f, 0xfb, 0x91, 0xc1,
+       0xe2, 0x6c, 0x24, 0xe9, 0xe9, 0xed, 0xb1, 0xad, 0x47, 0xc4, 0x67, 0x08,
+       0xa1, 0xe3, 0xea, 0xfd, 0xf0, 0x03, 0xa7, 0x9f, 0xb0, 0xd5, 0xdd, 0xfa,
+       0x5a, 0x94, 0x72, 0x80, 0xc5, 0xdd, 0x97, 0xef, 0x3d, 0x36, 0xeb, 0x4b,
+       0x14, 0xfe, 0xe5, 0x07, 0xfe, 0xa8, 0x01, 0x1c, 0x07, 0x8c, 0x98, 0x1c,
+       0xb0, 0xad, 0x5f, 0xe2, 0xf7, 0xea, 0x97, 0xec, 0x79, 0x53, 0x83, 0xf5,
+       0xbd, 0xe3, 0x89, 0x97, 0xde, 0x75, 0x0e, 0x3d, 0x75, 0x36, 0x9c, 0x46,
+       0xc8, 0x71, 0x1e, 0x1a, 0x27, 0xdd, 0x20, 0xc7, 0x0b, 0xd9, 0x6f, 0x30,
+       0x00, 0x3f, 0x5d, 0xfb, 0x3a, 0x15, 0xcd, 0x77, 0x7f, 0xe9, 0x21, 0xf0,
+       0xbb, 0x0e, 0xe2, 0xbc, 0x42, 0xdc, 0x7b, 0xa8, 0x27, 0xd1, 0x20, 0xe0,
+       0x6b, 0xe1, 0xfe, 0xa5, 0x18, 0x1f, 0x7e, 0xf7, 0xa9, 0x2b, 0xb9, 0x3d,
+       0x97, 0x98, 0x0c, 0xfc, 0xf1, 0x3e, 0x91, 0x6b, 0x60, 0x7d, 0xef, 0x93,
+       0x97, 0x82, 0x93, 0x6c, 0xf8, 0x2b, 0x09, 0x30, 0x3f, 0x86, 0x74, 0x30,
+       0x3b, 0x46, 0xdc, 0x0b, 0xa4, 0xf6, 0xac, 0xc3, 0xae, 0xb9, 0xa5, 0xd3,
+       0x59, 0x5f, 0x44, 0xe6, 0x16, 0x80, 0xde, 0x58, 0xf4, 0xa0, 0x07, 0xbe,
+       0xa1, 0x4a, 0x16, 0x13, 0xdb, 0xf7, 0x97, 0xe8, 0xba, 0xf3, 0x02, 0xcc,
+       0xde, 0xbd, 0x85, 0x34, 0xaf, 0x06, 0x7b, 0x4e, 0xf5, 0x32, 0xff, 0x60,
+       0xa1, 0x49, 0xd4, 0xe1, 0x54, 0x9f, 0x2e, 0xfb, 0xf1, 0x43, 0x93, 0xc1,
+       0xee, 0xbf, 0x30, 0xc0, 0xce, 0x1d, 0x45, 0x1c, 0x63, 0x71, 0x2e, 0xb3,
+       0xf7, 0x96, 0xe4, 0x25, 0x35, 0x38, 0x4f, 0xf8, 0xdd, 0xfe, 0x49, 0xf3,
+       0xbe, 0x04, 0xdc, 0xe7, 0x4d, 0xae, 0x86, 0x7d, 0x99, 0x64, 0xa7, 0x3f,
+       0xff, 0xbb, 0xa9, 0xc3, 0x09, 0xdf, 0x40, 0xf0, 0xbb, 0xe1, 0x15, 0xf7,
+       0xdd, 0xcf, 0x8a, 0xa7, 0x70, 0x38, 0x94, 0x3d, 0x52, 0xda, 0xfc, 0xb4,
+       0x29, 0x01, 0xce, 0x77, 0x5c, 0x8f, 0xdc, 0x13, 0x70, 0xda, 0xf9, 0x6b,
+       0x5c, 0xf5, 0xda, 0x00, 0x8f, 0xb3, 0x2a, 0x44, 0x01, 0x3a, 0xbf, 0x6f,
+       0xea, 0x71, 0x39, 0x1b, 0xdf, 0xe3, 0xfd, 0xda, 0xf8, 0x3e, 0x6f, 0x64,
+       0x55, 0x18, 0xbe, 0xa7, 0x15, 0x8d, 0x02, 0x7f, 0x51, 0xbb, 0x60, 0x02,
+       0xb1, 0xb5, 0xfb, 0xbd, 0x11, 0xc3, 0xe7, 0x27, 0xa5, 0x17, 0x17, 0xe1,
+       0xfd, 0x72, 0x35, 0x35, 0x01, 0xf3, 0xf1, 0x74, 0xa2, 0xda, 0x7f, 0x8f,
+       0x41, 0xf1, 0x07, 0x27, 0x90, 0x8b, 0x21, 0x4e, 0xda, 0x8c, 0x4e, 0xfd,
+       0x2a, 0x5f, 0x70, 0x07, 0xd4, 0x57, 0x07, 0xd8, 0x3d, 0xa8, 0x26, 0x90,
+       0x53, 0xb8, 0x3f, 0x1d, 0x9c, 0x75, 0x14, 0xe2, 0xfa, 0x3a, 0x49, 0xa4,
+       0xac, 0x22, 0x38, 0xff, 0x76, 0xc6, 0xbf, 0x7d, 0x61, 0x67, 0x3d, 0x0b,
+       0xe4, 0x09, 0xf4, 0x09, 0x3c, 0x00, 0x7a, 0x44, 0x08, 0xc6, 0x8b, 0xb2,
+       0xca, 0x9c, 0xed, 0x02, 0x11, 0x67, 0x7d, 0x49, 0x1f, 0x9e, 0x52, 0x8a,
+       0xfd, 0xde, 0x47, 0x50, 0x37, 0x52, 0xf8, 0x7b, 0x4d, 0x55, 0xea, 0x49,
+       0xbb, 0xdd, 0xbc, 0x5c, 0x67, 0xf0, 0x13, 0xf8, 0x9e, 0x2a, 0x6d, 0x7f,
+       0x1b, 0xb7, 0xe7, 0x97, 0x93, 0x70, 0x1c, 0xf3, 0x16, 0x43, 0x8c, 0x0f,
+       0x6e, 0x9b, 0xcd, 0xf2, 0x26, 0x6e, 0x0b, 0x84, 0xf1, 0x5e, 0xb2, 0xa4,
+       0x5a, 0x78, 0x3f, 0x62, 0x0d, 0x74, 0xb5, 0xed, 0x63, 0x4d, 0x1f, 0x49,
+       0x24, 0x69, 0xd3, 0xeb, 0x4d, 0x6a, 0xaf, 0x06, 0x7c, 0xd9, 0xf4, 0x91,
+       0x8a, 0xcf, 0x1f, 0x36, 0x62, 0xdf, 0x06, 0xbc, 0x6a, 0xc4, 0x42, 0x3b,
+       0x57, 0xa7, 0x48, 0x83, 0xf3, 0x6b, 0xd5, 0xa8, 0x71, 0xd8, 0xbd, 0x64,
+       0x04, 0xff, 0x2e, 0xa0, 0x2b, 0x7f, 0x61, 0x7d, 0xc0, 0x74, 0xf8, 0x7b,
+       0x42, 0x2f, 0x78, 0xb8, 0x5e, 0xa4, 0xfa, 0x62, 0x4d, 0x20, 0x1f, 0xf4,
+       0x60, 0xef, 0x2c, 0x76, 0xae, 0xde, 0xa3, 0xb1, 0xf3, 0x1d, 0xd6, 0x4e,
+       0xeb, 0x6f, 0xb7, 0x1e, 0xe0, 0xc8, 0xd4, 0xce, 0xd7, 0xdf, 0x6e, 0x53,
+       0xba, 0x76, 0xcb, 0x7e, 0xfc, 0xf8, 0x53, 0x71, 0x2a, 0xef, 0x4b, 0x7e,
+       0xf4, 0x9d, 0x20, 0x1c, 0xa6, 0xbd, 0xab, 0x26, 0x0a, 0x20, 0xff, 0xa1,
+       0x71, 0x77, 0x7b, 0x10, 0xf8, 0xf8, 0x1d, 0x35, 0x1e, 0x84, 0x75, 0xbf,
+       0x9b, 0x4c, 0x9f, 0xf7, 0xfe, 0x73, 0xae, 0xef, 0x20, 0xdf, 0x09, 0xee,
+       0xc9, 0x2f, 0xe7, 0x74, 0x7a, 0xef, 0x07, 0xf7, 0x5e, 0x05, 0x78, 0x3f,
+       0xb3, 0xdb, 0x83, 0xf7, 0xec, 0x9b, 0xf6, 0x78, 0x53, 0x5e, 0x4a, 0xc4,
+       0xe5, 0xfb, 0x17, 0x33, 0x7e, 0xda, 0xe3, 0x7d, 0x93, 0xd5, 0xd7, 0xe0,
+       0xef, 0x2e, 0x34, 0x1d, 0x70, 0xca, 0xdb, 0x92, 0xc7, 0xbe, 0x53, 0x10,
+       0xc6, 0xc3, 0xbd, 0x38, 0xf3, 0x1b, 0x49, 0x0a, 0xed, 0xe7, 0xe5, 0xbb,
+       0x7e, 0x3f, 0x0b, 0xec, 0x91, 0x26, 0xd2, 0x8b, 0x7a, 0xc2, 0xdd, 0x0f,
+       0xe6, 0xff, 0x28, 0x17, 0xf7, 0xaf, 0x05, 0x70, 0xdf, 0xdf, 0xfd, 0x5e,
+       0xe4, 0x5b, 0x35, 0x71, 0xbe, 0x6f, 0xda, 0x7f, 0x2f, 0xe6, 0x55, 0x35,
+       0xed, 0x9f, 0x8d, 0x79, 0x54, 0x4d, 0x2e, 0x39, 0x6f, 0xe0, 0x7e, 0xc8,
+       0x81, 0x80, 0xf3, 0x77, 0x36, 0x04, 0x3e, 0x48, 0x92, 0xd9, 0xc5, 0xab,
+       0xbe, 0xff, 0xdd, 0x09, 0x6f, 0x52, 0x78, 0x4e, 0xee, 0xfa, 0x65, 0x50,
+       0x72, 0xc4, 0x8f, 0x98, 0x9e, 0x38, 0xdd, 0x75, 0xd3, 0x23, 0x4f, 0x87,
+       0x33, 0xeb, 0xf7, 0x0f, 0xb8, 0x5f, 0xdf, 0xdf, 0x2f, 0x89, 0xfd, 0xc2,
+       0x07, 0x98, 0x1d, 0x4f, 0x0e, 0xb2, 0xb2, 0xd1, 0x93, 0x0a, 0x82, 0xdf,
+       0xd4, 0xb8, 0xdd, 0x13, 0xa1, 0x1a, 0x84, 0x34, 0x3e, 0xbe, 0xf3, 0xd1,
+       0xef, 0x01, 0x7f, 0xbf, 0xe6, 0xc5, 0x78, 0xc3, 0xd2, 0xc7, 0x9f, 0x7b,
+       0xe5, 0x32, 0x5a, 0x5f, 0xfa, 0x84, 0x27, 0xaf, 0x96, 0x2d, 0xc3, 0x80,
+       0x3c, 0x60, 0x41, 0x17, 0xb8, 0xdb, 0x0e, 0xf9, 0xba, 0x82, 0x0e, 0x4b,
+       0xfe, 0xe5, 0x39, 0x2d, 0x7c, 0x11, 0x7b, 0x7e, 0x77, 0x6e, 0x3f, 0x3d,
+       0x96, 0x3e, 0x71, 0x58, 0x23, 0x17, 0x9d, 0x8d, 0xbf, 0xe9, 0x5d, 0x87,
+       0x35, 0xfc, 0x4e, 0x90, 0x9b, 0x2e, 0x5d, 0x6f, 0xce, 0x02, 0xbb, 0x7b,
+       0xd5, 0xf7, 0xff, 0xa4, 0x81, 0x7c, 0xbd, 0x7b, 0x48, 0x22, 0x43, 0x8b,
+       0xce, 0xee, 0xdf, 0xb0, 0xfd, 0x39, 0xb4, 0xeb, 0x00, 0x4f, 0x48, 0x47,
+       0x4e, 0xa7, 0x3e, 0xba, 0x9d, 0x45, 0xaf, 0xd4, 0x55, 0x4f, 0x57, 0x62,
+       0x3b, 0x13, 0xf6, 0xb1, 0x81, 0xe8, 0xf5, 0x3d, 0xe0, 0x99, 0x7c, 0xe4,
+       0xeb, 0x1f, 0x3e, 0x0d, 0xe7, 0x05, 0xff, 0xea, 0x8d, 0x00, 0x1e, 0x1a,
+       0x7e, 0xf8, 0xad, 0x20, 0xac, 0xe7, 0x6d, 0xb5, 0x99, 0xf1, 0xf7, 0x43,
+       0xed, 0x05, 0x70, 0x8e, 0xde, 0xe0, 0x89, 0x17, 0x98, 0x58, 0xb2, 0xe7,
+       0x0d, 0x0f, 0xdf, 0x8e, 0x7c, 0x77, 0xcb, 0xb1, 0xdb, 0x0b, 0x58, 0x1e,
+       0x94, 0x55, 0xc8, 0x7f, 0x17, 0xa0, 0x10, 0xe3, 0x80, 0xdb, 0xae, 0xc1,
+       0x75, 0x2e, 0x22, 0x31, 0xe4, 0xbf, 0x86, 0x87, 0x94, 0x28, 0x9c, 0x93,
+       0x7d, 0xa8, 0x92, 0x9a, 0x27, 0xd2, 0xc8, 0xc7, 0xe5, 0x41, 0xa6, 0xc7,
+       0xde, 0xde, 0xe1, 0xc5, 0x8f, 0xde, 0xbd, 0x0d, 0x0a, 0x17, 0xfc, 0xc5,
+       0x97, 0x94, 0x24, 0xbb, 0x6f, 0xcb, 0xf2, 0x12, 0x6f, 0x17, 0xe7, 0x1e,
+       0xf0, 0xdd, 0x46, 0x5a, 0xff, 0x50, 0x67, 0xf4, 0xca, 0x0f, 0xca, 0xe2,
+       0x7b, 0x56, 0xba, 0x83, 0x6f, 0x77, 0xad, 0xe9, 0x06, 0x3a, 0xbd, 0x37,
+       0xd2, 0x1a, 0x0a, 0xf1, 0x4a, 0x8a, 0x87, 0x38, 0xc7, 0x9b, 0x04, 0x7a,
+       0x48, 0x39, 0x36, 0x73, 0x28, 0xa3, 0x13, 0x09, 0xab, 0x93, 0x79, 0x3f,
+       0xaa, 0x27, 0xa7, 0xc3, 0x73, 0x68, 0xdf, 0xed, 0xb1, 0x7c, 0x13, 0x1c,
+       0xfd, 0xf8, 0xbe, 0xc6, 0xe6, 0xbf, 0x8d, 0xcf, 0x4f, 0xe1, 0xf6, 0x83,
+       0x7d, 0xf6, 0x76, 0x01, 0xb5, 0x77, 0xd2, 0xac, 0x6f, 0x69, 0x50, 0xc8,
+       0x3f, 0xb5, 0x3f, 0x6c, 0x7c, 0x66, 0x93, 0x73, 0x26, 0xf7, 0xbb, 0xd6,
+       0x32, 0x39, 0x17, 0x72, 0x9f, 0x9c, 0x53, 0x03, 0xef, 0xff, 0xed, 0x65,
+       0x26, 0x47, 0xd0, 0x0f, 0xf6, 0x79, 0x0a, 0x57, 0x6a, 0x28, 0xbe, 0x3f,
+       0x7c, 0xb5, 0x84, 0x7a, 0xc1, 0x4b, 0x52, 0xe9, 0xe4, 0x7b, 0x97, 0x87,
+       0xcb, 0xb7, 0xf3, 0x3d, 0xf5, 0xca, 0xd1, 0xbe, 0x15, 0x7c, 0x42, 0xe1,
+       0x57, 0x61, 0xdf, 0xea, 0xe7, 0x17, 0x76, 0xce, 0x4b, 0xe9, 0x80, 0xf6,
+       0xdb, 0xa2, 0x07, 0x69, 0x7f, 0xbb, 0x7d, 0x0e, 0xf3, 0x62, 0x3b, 0xad,
+       0xff, 0xb9, 0x6d, 0xbf, 0xbf, 0x85, 0xeb, 0x83, 0xcb, 0x82, 0xae, 0xdf,
+       0xdd, 0xd9, 0x96, 0x3f, 0xa8, 0xef, 0xe4, 0x35, 0x7a, 0x92, 0x8f, 0x7e,
+       0x0f, 0xe4, 0x97, 0xca, 0x2b, 0xec, 0x3f, 0x8d, 0x8f, 0x7b, 0x30, 0x4f,
+       0xe4, 0x0f, 0x7b, 0x9f, 0x7d, 0xe5, 0x3a, 0xca, 0xe7, 0x7f, 0xe8, 0x12,
+       0x72, 0xeb, 0xd4, 0xa7, 0x6e, 0xb9, 0x6d, 0xd8, 0x77, 0x09, 0x49, 0x27,
+       0xb7, 0x7f, 0x30, 0x22, 0x24, 0xad, 0xdc, 0xd2, 0xe7, 0x69, 0xe5, 0xd6,
+       0xe8, 0x41, 0x7e, 0xfe, 0x5b, 0xe9, 0x53, 0x81, 0xbf, 0x85, 0x41, 0x67,
+       0x9e, 0x93, 0xd0, 0x8f, 0x99, 0xf0, 0xe8, 0xd6, 0x8f, 0x7f, 0x0d, 0x84,
+       0xd9, 0xef, 0x22, 0xb8, 0xf4, 0x23, 0xfd, 0xf7, 0x32, 0x99, 0x7c, 0x36,
+       0x1f, 0x0a, 0xfe, 0x13, 0x7c, 0xb7, 0xe4, 0x9f, 0x97, 0xe1, 0xef, 0x83,
+       0xf4, 0xf1, 0xa7, 0xe0, 0xbf, 0x3e, 0xfe, 0x14, 0xfc, 0xe7, 0x5e, 0xaf,
+       0x13, 0x7f, 0xee, 0xf7, 0x17, 0x82, 0xa1, 0x22, 0xe2, 0xc5, 0xb4, 0xf4,
+       0xdc, 0x43, 0xe2, 0x01, 0x88, 0xa7, 0xfe, 0x4c, 0xc1, 0x78, 0xea, 0x29,
+       0x0a, 0xd3, 0x6a, 0x4a, 0xe7, 0x53, 0x7b, 0x8b, 0xf0, 0x1e, 0x71, 0xbb,
+       0x8f, 0xf9, 0xe7, 0xa7, 0xcc, 0xde, 0x60, 0x6e, 0x39, 0x7e, 0xff, 0x06,
+       0xeb, 0xbd, 0xf9, 0xda, 0x6a, 0xd0, 0x17, 0xe2, 0x79, 0xaf, 0x8f, 0xc5,
+       0xbf, 0x4f, 0x45, 0x7b, 0x83, 0xf6, 0x3c, 0x90, 0x37, 0x0f, 0x2a, 0x41,
+       0x38, 0xef, 0xea, 0x49, 0x92, 0x9a, 0x74, 0xfe, 0x08, 0xd5, 0xc8, 0x08,
+       0x47, 0x0f, 0xc9, 0xf4, 0x9e, 0xc5, 0x8b, 0x4f, 0x81, 0xfd, 0x07, 0xf3,
+       0xf9, 0x47, 0x25, 0x81, 0x6e, 0x33, 0x15, 0x63, 0xd4, 0x4a, 0xf0, 0xf3,
+       0x13, 0xec, 0xbe, 0x7c, 0x7d, 0xeb, 0xb5, 0x41, 0xc8, 0x53, 0x38, 0x75,
+       0x70, 0xcc, 0x46, 0xd0, 0x5f, 0x37, 0xbf, 0xa0, 0x10, 0xfe, 0xbb, 0x85,
+       0x2a, 0xe4, 0x9b, 0xdc, 0xc4, 0xe9, 0xff, 0x0e, 0x89, 0x6f, 0x9e, 0x4a,
+       0xd7, 0x79, 0xd3, 0x41, 0xe6, 0x57, 0xd4, 0xaf, 0x4f, 0xcf, 0x2f, 0x4b,
+       0x78, 0xfb, 0x45, 0xc6, 0x6d, 0x1a, 0xe8, 0x25, 0xea, 0x17, 0xbc, 0x65,
+       0x8f, 0x87, 0x2f, 0xe1, 0xbf, 0xc7, 0xd4, 0xb0, 0xcd, 0xf5, 0xfc, 0xe0,
+       0x95, 0xc8, 0x57, 0x4b, 0x5c, 0x7c, 0x15, 0xe3, 0x7e, 0xe3, 0xe3, 0x82,
+       0xaf, 0x26, 0x92, 0x89, 0xdc, 0x6f, 0x93, 0xed, 0xf9, 0x6c, 0x33, 0x95,
+       0xf2, 0x8d, 0x60, 0x97, 0x9c, 0x3a, 0xca, 0xe2, 0x90, 0xa7, 0x0f, 0x2a,
+       0x48, 0x8f, 0xd3, 0x7b, 0x25, 0x96, 0xff, 0x04, 0xf1, 0xe0, 0x29, 0xc0,
+       0x0f, 0xbd, 0x9a, 0x3d, 0x8f, 0xed, 0x24, 0xf0, 0x5f, 0x9a, 0xef, 0x1b,
+       0xf4, 0xbd, 0x7f, 0xf2, 0x37, 0x93, 0xef, 0xa2, 0x4d, 0x1a, 0x9f, 0x7a,
+       0x7d, 0xc2, 0x56, 0x5a, 0x9e, 0x7c, 0xea, 0xb5, 0xd2, 0x9f, 0x42, 0xfd,
+       0xc7, 0xbf, 0x1e, 0xf5, 0x3a, 0x39, 0xbb, 0xfd, 0xf4, 0x43, 0x7f, 0xc6,
+       0xf3, 0xec, 0x53, 0x87, 0xbc, 0x08, 0xc7, 0xa9, 0x43, 0x3f, 0x1f, 0x75,
+       0x17, 0xd4, 0x9f, 0xf6, 0xe2, 0x77, 0x6a, 0x4e, 0xdd, 0xe3, 0x65, 0xf9,
+       0x9f, 0x87, 0x02, 0xc9, 0xb1, 0xf0, 0x7e, 0x24, 0xcb, 0x17, 0x5a, 0xf5,
+       0xb3, 0x3f, 0x4d, 0x60, 0xdf, 0x7f, 0x69, 0x43, 0xba, 0xbd, 0x1a, 0x64,
+       0xfe, 0xd8, 0xe9, 0x83, 0xff, 0xfe, 0x5b, 0xc8, 0x1f, 0x3e, 0x7d, 0xd0,
+       0x1b, 0x86, 0x75, 0x34, 0x1d, 0xca, 0xc2, 0xf3, 0xad, 0xa6, 0xa7, 0x7d,
+       0x18, 0xa7, 0x39, 0xf5, 0xb3, 0x3f, 0x4d, 0xb6, 0xe7, 0x33, 0x7d, 0xd6,
+       0xf5, 0x2c, 0xe7, 0xdf, 0x41, 0x3c, 0x15, 0x20, 0x75, 0x90, 0xa7, 0x7c,
+       0x2a, 0x87, 0x9d, 0x1b, 0x34, 0xfd, 0x74, 0xca, 0x4e, 0xb8, 0x47, 0xb4,
+       0x6c, 0xff, 0x61, 0x0d, 0xce, 0x63, 0xa6, 0x3f, 0xf3, 0x97, 0x09, 0xa0,
+       0x77, 0x4e, 0xed, 0x63, 0xf6, 0xc4, 0x07, 0x9e, 0x9e, 0x87, 0xe1, 0x9c,
+       0xf5, 0x77, 0xc1, 0x1b, 0xd7, 0x78, 0x20, 0xbe, 0x0b, 0xfb, 0xf5, 0x30,
+       0x42, 0x5a, 0xb2, 0x93, 0x57, 0xc4, 0x8d, 0x74, 0x78, 0x61, 0x78, 0x38,
+       0x45, 0xf1, 0x00, 0xeb, 0xa2, 0x78, 0x69, 0x00, 0x7d, 0x99, 0x09, 0x1f,
+       0xff, 0xe7, 0x1f, 0x16, 0x1f, 0x7f, 0x9c, 0x0f, 0xf3, 0x37, 0x1e, 0xbc,
+       0x14, 0xe5, 0xa6, 0x1f, 0x2f, 0x92, 0xc5, 0x9e, 0x07, 0x92, 0x70, 0xb5,
+       0x89, 0xae, 0x9f, 0x3d, 0x3f, 0xf4, 0xa7, 0x09, 0x60, 0x1f, 0xfd, 0xa1,
+       0xab, 0x15, 0xf7, 0xf9, 0x81, 0xd6, 0x5d, 0x98, 0xfd, 0xff, 0xda, 0xba,
+       0xa5, 0xd4, 0x60, 0xd6, 0x5d, 0xf5, 0x0f, 0xbb, 0x6e, 0xc6, 0xff, 0x87,
+       0x82, 0x61, 0x96, 0xf7, 0xe7, 0x92, 0x83, 0xb3, 0xf9, 0xfc, 0xc7, 0x77,
+       0x60, 0xfd, 0x87, 0x81, 0x08, 0xc2, 0x3b, 0x48, 0xf9, 0xaf, 0xfb, 0x87,
+       0x5d, 0xff, 0xa7, 0xa4, 0xfb, 0x3e, 0x4a, 0xf7, 0xe0, 0xc0, 0x74, 0xff,
+       0x2f, 0xd9, 0xec, 0x5c, 0xf8, 0x1f, 0x6f, 0xdd, 0x03, 0xd1, 0xfd, 0x05,
+       0x4e, 0xf7, 0x80, 0x09, 0x79, 0x08, 0xa7, 0x7e, 0xf6, 0x17, 0x8c, 0xaf,
+       0x8b, 0xf5, 0x0f, 0xb4, 0xee, 0xcd, 0xff, 0x41, 0xd7, 0x2d, 0xec, 0xa1,
+       0x75, 0x72, 0x24, 0x51, 0x5c, 0x04, 0x79, 0xd8, 0xa9, 0xee, 0xb0, 0x04,
+       0xbf, 0xc3, 0x33, 0x37, 0x01, 0x61, 0x29, 0x85, 0xe7, 0x5d, 0xbb, 0xe1,
+       0x7a, 0x3e, 0x9b, 0xf9, 0x17, 0x8a, 0xc4, 0xe2, 0x36, 0x64, 0x24, 0x8b,
+       0x1f, 0x11, 0xee, 0x6f, 0xf4, 0xfd, 0x5e, 0xac, 0xc1, 0xee, 0x57, 0xa9,
+       0xc6, 0x6a, 0xf6, 0x3d, 0x32, 0x35, 0x82, 0xdf, 0xd5, 0x5b, 0x77, 0xc1,
+       0xc2, 0x08, 0xe6, 0x76, 0x90, 0x8a, 0x57, 0x63, 0x50, 0x1f, 0x31, 0x15,
+       0x7f, 0xe7, 0xd6, 0xed, 0x77, 0xb5, 0x49, 0xc4, 0x92, 0xa8, 0xfd, 0xa7,
+       0x5e, 0xf0, 0xd5, 0xa3, 0x60, 0xff, 0x7b, 0xca, 0xe4, 0x94, 0x77, 0x02,
+       0x96, 0x6f, 0x42, 0xb9, 0x86, 0xc7, 0xbd, 0x3c, 0xa6, 0xe6, 0xf0, 0x37,
+       0x0c, 0x97, 0x9f, 0xe0, 0x0b, 0x3b, 0xdf, 0x7b, 0xf9, 0x78, 0x3a, 0xa9,
+       0x48, 0xc0, 0xef, 0x77, 0xeb, 0x86, 0x6a, 0x26, 0xe9, 0xfc, 0x46, 0x35,
+       0xfb, 0xfd, 0x68, 0xc8, 0xed, 0x4c, 0xd8, 0xce, 0x0d, 0xbd, 0xc4, 0xd6,
+       0x9f, 0x8e, 0xb7, 0x03, 0x7e, 0x93, 0xc5, 0x66, 0x4f, 0x9e, 0x2f, 0xfe,
+       0xfe, 0x94, 0xcd, 0xfc, 0x4f, 0x45, 0xaa, 0xe8, 0x86, 0xbc, 0x58, 0x32,
+       0x5e, 0x66, 0xdf, 0x35, 0x27, 0xec, 0x5e, 0xf1, 0xba, 0x11, 0x91, 0xe4,
+       0x3a, 0xf4, 0x43, 0x99, 0x7f, 0xd9, 0x8f, 0xcf, 0xd5, 0xdd, 0x80, 0x47,
+       0x95, 0x50, 0xff, 0x90, 0xad, 0x0f, 0xfd, 0x4a, 0xc2, 0xfd, 0x49, 0x95,
+       0x0f, 0xa1, 0x96, 0xc9, 0x96, 0xcf, 0xd9, 0x8e, 0xfb, 0x4b, 0x03, 0xd2,
+       0x87, 0xd1, 0x63, 0x54, 0x23, 0xa7, 0xcf, 0x0a, 0x07, 0x3d, 0x04, 0xfe,
+       0xd3, 0xd0, 0xc5, 0x41, 0x0f, 0x81, 0xdf, 0xf3, 0xa5, 0x8b, 0x9b, 0x1e,
+       0x6e, 0xbc, 0xff, 0x22, 0x9b, 0xc5, 0xe7, 0xdc, 0x74, 0x72, 0xe4, 0x83,
+       0xe4, 0x33, 0xbf, 0x24, 0x45, 0x0d, 0xe4, 0x9f, 0xef, 0xdd, 0x89, 0x71,
+       0x91, 0xf7, 0x7f, 0xf0, 0xe6, 0x55, 0xd0, 0x7e, 0xe9, 0x4f, 0x15, 0x02,
+       0xbf, 0x8b, 0xf6, 0xc1, 0xde, 0x00, 0x49, 0x81, 0xfc, 0xaa, 0x49, 0x0d,
+       0xfc, 0xac, 0x25, 0xfb, 0x15, 0x8c, 0x0b, 0xff, 0x5f, 0x82, 0x42, 0xfc,
+       0xff, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00,
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d, 0x7b, 0x7c, 0x54, 0xd5,
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+       0x73, 0x32, 0x76, 0xcf, 0x9e, 0xa4, 0xc8, 0xf4, 0x42, 0xb8, 0xee, 0xfd,
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+       0xc1, 0x38, 0x12, 0x6e, 0x58, 0xdf, 0x67, 0xf8, 0x8f, 0x97, 0xb1, 0xb1,
+       0x8e, 0x54, 0xe7, 0xc7, 0x57, 0xc1, 0xff, 0x63, 0xd8, 0x98, 0x4b, 0x2a,
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+       0xd7, 0xf3, 0x6e, 0x52, 0x24, 0x0c, 0xb7, 0x7a, 0x5e, 0x3e, 0x5d, 0xe0,
+       0x83, 0xf5, 0xf6, 0xec, 0xfe, 0x9b, 0xdb, 0x07, 0xfd, 0x97, 0xbd, 0x3c,
+       0x29, 0x1b, 0xd7, 0xbf, 0xec, 0x85, 0xaa, 0x6c, 0x66, 0x1f, 0x18, 0x8e,
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+       0xa9, 0xf5, 0x2d, 0x0b, 0xd9, 0xb1, 0x51, 0x6f, 0x27, 0x47, 0x92, 0x00,
+       0x4f, 0xcb, 0xde, 0x9a, 0xf2, 0x87, 0x74, 0x27, 0x5e, 0x2d, 0x3e, 0x40,
+       0x2d, 0xeb, 0x5c, 0xc9, 0xf9, 0xaa, 0xf3, 0xfe, 0x40, 0x2e, 0xd2, 0xa5,
+       0xf3, 0xad, 0x6f, 0xaa, 0x68, 0x4f, 0xf6, 0x22, 0x1e, 0xaf, 0x88, 0x8d,
+       0x5b, 0x71, 0xbc, 0xa9, 0x2a, 0x15, 0xe4, 0xb6, 0xe2, 0x64, 0x70, 0x14,
+       0xb2, 0x55, 0xbc, 0x3e, 0x18, 0x73, 0xc2, 0x64, 0x80, 0x1b, 0xe6, 0xc9,
+       0x46, 0xfd, 0xdc, 0x02, 0xe3, 0xf8, 0x60, 0x1c, 0xa6, 0xf9, 0x3d, 0x41,
+       0x18, 0x57, 0x4d, 0x9b, 0x3c, 0x05, 0xe1, 0x51, 0x1d, 0x26, 0x87, 0x2d,
+       0xa1, 0x5d, 0xe5, 0xe3, 0x99, 0xed, 0x41, 0x16, 0x02, 0xb8, 0xcc, 0x60,
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+       0x54, 0x03, 0xf8, 0x98, 0x29, 0xd9, 0xff, 0x14, 0x8c, 0xbb, 0x74, 0x58,
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+       0x0b, 0x7f, 0xef, 0x9c, 0xc3, 0x1e, 0x36, 0x8d, 0xc0, 0x76, 0x41, 0x04,
+       0xe5, 0x28, 0xe5, 0xa2, 0xca, 0x7c, 0xa0, 0xfa, 0xce, 0x2a, 0xbf, 0x5e,
+       0xc8, 0x40, 0x25, 0xa4, 0x08, 0xbe, 0xca, 0xed, 0x48, 0x21, 0x3b, 0x93,
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+       0x47, 0xf6, 0x50, 0x7e, 0x86, 0x0b, 0xdf, 0xb3, 0xd0, 0x7b, 0xde, 0x0c,
+       0x45, 0xfb, 0x18, 0xd7, 0x9d, 0xc6, 0xd2, 0x50, 0xde, 0xe4, 0xf8, 0xb2,
+       0x9f, 0x1c, 0x97, 0x69, 0xd1, 0xe1, 0xb8, 0x7e, 0x66, 0x65, 0x1a, 0x03,
+       0xbb, 0x92, 0xc7, 0x38, 0xdc, 0xaa, 0x58, 0x4f, 0x31, 0xeb, 0x52, 0x90,
+       0xbf, 0x9b, 0x67, 0xa4, 0x6d, 0xc7, 0xf6, 0xd6, 0xd4, 0x1a, 0xb2, 0xff,
+       0x05, 0xac, 0xf7, 0x60, 0x00, 0xe8, 0xf6, 0x64, 0xda, 0xe4, 0x63, 0xa8,
+       0xc7, 0xe0, 0x5f, 0x13, 0xf6, 0xcb, 0x6f, 0x32, 0xda, 0xf7, 0x41, 0xcb,
+       0x8d, 0xed, 0xc2, 0xb0, 0x16, 0x27, 0xbf, 0x3e, 0x53, 0x10, 0xf8, 0xaf,
+       0xb8, 0xcd, 0x78, 0xdf, 0x59, 0x55, 0xb9, 0x64, 0x90, 0x1f, 0xe4, 0x6c,
+       0x7d, 0xe7, 0x14, 0x0d, 0xf4, 0xb7, 0x73, 0x76, 0xe5, 0xee, 0x5c, 0xc0,
+       0xe9, 0xb4, 0x35, 0x6f, 0xf3, 0xf6, 0x33, 0x95, 0x65, 0x5e, 0x68, 0x1f,
+       0x5f, 0x5f, 0x37, 0x55, 0x03, 0x3d, 0xe2, 0xfc, 0x4d, 0x65, 0x59, 0x01,
+       0xb4, 0xcf, 0x3f, 0xfc, 0x9d, 0xa9, 0xf4, 0xbc, 0x16, 0x90, 0x74, 0x2d,
+       0xa8, 0xfe, 0xf5, 0x57, 0x4f, 0x0d, 0x97, 0xc6, 0xe4, 0xd6, 0x05, 0x60,
+       0xa6, 0xab, 0x24, 0xcf, 0x37, 0x20, 0x1e, 0xce, 0x05, 0xcf, 0xb6, 0xe2,
+       0xd3, 0xfa, 0x59, 0x7f, 0xb5, 0xc0, 0x23, 0xfc, 0x0b, 0x22, 0x1e, 0xf2,
+       0xc7, 0x72, 0x3c, 0xe4, 0xd9, 0x4f, 0xee, 0x66, 0xd0, 0x7f, 0x90, 0xa9,
+       0x7b, 0x25, 0xf2, 0xe5, 0x13, 0x2f, 0xff, 0xdf, 0x0c, 0xec, 0xe7, 0x63,
+       0x0e, 0x5a, 0xaf, 0x83, 0xb5, 0x38, 0x3e, 0xb6, 0xe2, 0xe2, 0xd9, 0xd8,
+       0x4b, 0x23, 0xbf, 0x4c, 0x9f, 0x69, 0xec, 0x63, 0xc9, 0x87, 0x6a, 0x4c,
+       0x0e, 0x54, 0x77, 0xe8, 0xe6, 0x0c, 0xe0, 0xab, 0xd6, 0xb9, 0x43, 0x37,
+       0x4d, 0x46, 0x5d, 0x5b, 0xe7, 0x27, 0xfe, 0x82, 0x99, 0x1d, 0x64, 0x0f,
+       0x65, 0x7f, 0x87, 0x93, 0xe8, 0x33, 0x5f, 0xd0, 0x07, 0xe1, 0xb4, 0x02,
+       0x9f, 0x2d, 0xe0, 0x5d, 0xd8, 0x22, 0x35, 0x6c, 0x61, 0x34, 0x6e, 0xbb,
+       0x25, 0x48, 0xf6, 0x6a, 0xa2, 0x03, 0xe7, 0x53, 0xc2, 0x75, 0xea, 0xa5,
+       0xab, 0xbe, 0x3e, 0x5c, 0xf3, 0x90, 0x7f, 0x90, 0x1e, 0xa9, 0x2c, 0x15,
+       0xef, 0x6b, 0x75, 0x3e, 0x82, 0xef, 0xb0, 0x2b, 0xb0, 0x90, 0xf0, 0xe6,
+       0x0a, 0xd1, 0x55, 0xde, 0xf7, 0xcc, 0x9d, 0xe3, 0x0b, 0x01, 0x9e, 0x6f,
+       0xc8, 0x08, 0xd6, 0xe0, 0x7a, 0xbc, 0x0b, 0x2f, 0x16, 0xe0, 0x3a, 0xa6,
+       0x67, 0x30, 0x1a, 0xaf, 0x6a, 0x91, 0x3d, 0x80, 0xf6, 0xf5, 0xc2, 0x01,
+       0x50, 0x83, 0x09, 0xe4, 0x4b, 0x5e, 0xb7, 0xaf, 0x60, 0x7e, 0x6d, 0xc8,
+       0xc0, 0xcf, 0x83, 0x99, 0xa1, 0x6f, 0xe3, 0xbc, 0x45, 0xbf, 0xf4, 0xed,
+       0x39, 0x06, 0xe3, 0x8d, 0x98, 0x6f, 0xf1, 0xdb, 0x60, 0x8a, 0x11, 0xcb,
+       0x47, 0xf9, 0xb5, 0x2c, 0xc6, 0x17, 0x84, 0xfe, 0x87, 0xa0, 0x9f, 0x07,
+       0x69, 0x8a, 0xf2, 0xf7, 0x6d, 0x16, 0x41, 0xf9, 0x3b, 0x9f, 0xa4, 0x04,
+       0x02, 0xd0, 0x3e, 0x7f, 0xaf, 0x83, 0xf4, 0x73, 0xde, 0xfc, 0xe9, 0xc7,
+       0xd0, 0xae, 0x9d, 0x4f, 0x29, 0xec, 0x88, 0xe2, 0xfd, 0xef, 0xfb, 0x48,
+       0x2e, 0xc1, 0x13, 0x50, 0x50, 0x2e, 0xf2, 0x0f, 0xa4, 0x47, 0x6d, 0x69,
+       0xc4, 0xd7, 0x7f, 0x8d, 0xe3, 0xeb, 0xbf, 0x1a, 0xf9, 0xd8, 0x38, 0xef,
+       0xf9, 0x4b, 0xbe, 0x7d, 0xdd, 0x34, 0x9e, 0x43, 0x8c, 0x07, 0x8e, 0x11,
+       0x3c, 0xcf, 0x17, 0xf4, 0x3a, 0xaf, 0x72, 0xff, 0xfc, 0xfc, 0x0a, 0x1f,
+       0xc1, 0x01, 0x6e, 0xe4, 0x41, 0xb4, 0xbb, 0x5f, 0x75, 0xbe, 0x47, 0x33,
+       0x84, 0x3d, 0x15, 0xf4, 0xb9, 0xdf, 0x16, 0xd8, 0x88, 0x78, 0x01, 0xfc,
+       0x6f, 0xd6, 0xe3, 0x7f, 0xeb, 0xc0, 0x74, 0x7c, 0x42, 0xd0, 0xf1, 0x89,
+       0x44, 0x74, 0x5c, 0x68, 0x6d, 0x2a, 0x40, 0xfd, 0x70, 0x4f, 0xb0, 0x63,
+       0x32, 0x68, 0x6e, 0x36, 0x23, 0x23, 0xb4, 0x03, 0xc7, 0x3d, 0xbd, 0xf0,
+       0x68, 0xab, 0x19, 0xd6, 0x53, 0x5f, 0xdd, 0x54, 0x82, 0x4c, 0xdf, 0x9f,
+       0xbe, 0x0a, 0xe9, 0x73, 0xf7, 0x81, 0xbb, 0x57, 0x9a, 0xa1, 0xdd, 0x88,
+       0xf4, 0xf1, 0xf5, 0xa7, 0xe3, 0x88, 0xe5, 0x65, 0x44, 0x2f, 0x1d, 0x5d,
+       0x3b, 0x10, 0x8e, 0x11, 0x07, 0xfe, 0x64, 0x42, 0xb8, 0x25, 0x3d, 0x37,
+       0x29, 0xdc, 0x0e, 0xc4, 0xbf, 0xff, 0x52, 0x86, 0x22, 0xe6, 0xad, 0x5b,
+       0x69, 0x06, 0x3c, 0x5e, 0xd8, 0x67, 0x21, 0xff, 0x37, 0xbe, 0xdf, 0x91,
+       0x0c, 0x1f, 0xf5, 0x93, 0xed, 0xe1, 0xd6, 0x0a, 0xbf, 0x06, 0x72, 0x9a,
+       0x6d, 0x62, 0xa1, 0x44, 0xe3, 0x1e, 0xe9, 0x37, 0xae, 0xd5, 0x9f, 0x94,
+       0x00, 0xfe, 0xbe, 0xf1, 0x1c, 0x7c, 0x3c, 0xc0, 0xfb, 0x6b, 0x7a, 0xbc,
+       0xbf, 0x21, 0xf5, 0x6f, 0x7f, 0xbc, 0xff, 0x1f, 0xec, 0x07, 0x78, 0xa7,
+       0xeb, 0x57, 0xc0, 0xfb, 0x3b, 0x5f, 0x86, 0x77, 0xe9, 0x6f, 0xd7, 0x0a,
+       0xbd, 0x50, 0xcb, 0xd6, 0x91, 0x9f, 0xf9, 0x51, 0x60, 0xa6, 0x7b, 0x30,
+       0xcc, 0x3b, 0x59, 0xb5, 0x13, 0xff, 0x2f, 0x7e, 0x4a, 0x25, 0xb9, 0x83,
+       0xfe, 0xd3, 0xbd, 0xee, 0x98, 0x1e, 0x59, 0x7c, 0x4d, 0xd3, 0x41, 0x5c,
+       0xe7, 0xe2, 0x1f, 0x2b, 0xc4, 0xa7, 0xf3, 0x43, 0x5c, 0xbf, 0x9f, 0x59,
+       0x38, 0xfd, 0x28, 0xea, 0xf5, 0x05, 0xed, 0x46, 0xbf, 0x69, 0xe1, 0x1c,
+       0xd0, 0x33, 0x00, 0xdf, 0xa2, 0xcd, 0xc6, 0xfb, 0x8b, 0x23, 0x71, 0x71,
+       0x20, 0xd3, 0xe9, 0x73, 0xe0, 0x87, 0x33, 0x31, 0x7e, 0x1d, 0xc4, 0xf5,
+       0x8c, 0x87, 0xec, 0xa4, 0x2a, 0xe4, 0xa1, 0x6a, 0x51, 0x69, 0x3a, 0xfa,
+       0x49, 0xaf, 0x98, 0x7d, 0xbf, 0x21, 0x3f, 0xfc, 0x75, 0x95, 0x6d, 0x4f,
+       0x80, 0xf7, 0xfc, 0xcc, 0x42, 0xb2, 0xc3, 0x7d, 0xed, 0x26, 0x40, 0x86,
+       0xce, 0xbe, 0xb3, 0xf9, 0x36, 0x13, 0xea, 0x49, 0x39, 0xee, 0xc4, 0x45,
+       0xa5, 0xd9, 0xe8, 0xcf, 0x2c, 0x4d, 0xf5, 0x7d, 0x69, 0xfc, 0x35, 0x68,
+       0xb9, 0xd1, 0x9e, 0x17, 0x86, 0x93, 0x99, 0x4f, 0x37, 0x6e, 0x71, 0x5b,
+       0xa6, 0xa1, 0x3d, 0xa4, 0x3d, 0xc7, 0xd0, 0xff, 0x8a, 0xcd, 0x45, 0x86,
+       0xe7, 0xc3, 0x22, 0x57, 0x1a, 0x9e, 0x5f, 0xb5, 0xb3, 0xdc, 0xd0, 0xbe,
+       0xba, 0xe3, 0x5a, 0x43, 0xff, 0x11, 0xfb, 0x26, 0x18, 0xda, 0x65, 0xd1,
+       0x9b, 0x0c, 0xfd, 0x47, 0x1e, 0x9b, 0x69, 0x68, 0x8f, 0xee, 0xfa, 0xa6,
+       0xa1, 0xff, 0x98, 0x13, 0x73, 0x0d, 0xcf, 0xaf, 0xe9, 0xbe, 0xc7, 0xf0,
+       0xfc, 0xba, 0x4f, 0x96, 0x1a, 0xda, 0xd7, 0xf7, 0x7e, 0xcf, 0xe8, 0xbf,
+       0x98, 0x18, 0xe9, 0x45, 0x96, 0xac, 0x90, 0x9e, 0x3c, 0xbc, 0xe2, 0x93,
+       0x8a, 0x0f, 0x91, 0x01, 0x47, 0x29, 0x13, 0x11, 0x9f, 0x55, 0x63, 0x79,
+       0xdf, 0xc3, 0x4b, 0x2c, 0x26, 0x47, 0x1a, 0x5e, 0x4b, 0x4c, 0x0e, 0xe0,
+       0x8f, 0x57, 0x17, 0x4c, 0x27, 0xfb, 0x7f, 0x78, 0x89, 0x3b, 0xe0, 0xa3,
+       0x6b, 0x45, 0x00, 0xe3, 0x1e, 0xa6, 0x8e, 0x1b, 0x15, 0x4a, 0xe0, 0xdf,
+       0x4e, 0x72, 0x7c, 0x5a, 0xf1, 0xa1, 0x6e, 0xde, 0x2a, 0xab, 0xd9, 0xa0,
+       0xd7, 0x26, 0x39, 0x8c, 0xed, 0xf2, 0x4c, 0x11, 0x17, 0x0e, 0xe2, 0x7c,
+       0x33, 0x26, 0xd3, 0x28, 0x57, 0x6a, 0xd3, 0xf4, 0xa8, 0x05, 0x9a, 0x39,
+       0x8b, 0x07, 0x67, 0xe3, 0x7c, 0x20, 0x5f, 0xd7, 0x66, 0x72, 0xbd, 0x46,
+       0xd7, 0xaf, 0x20, 0x5f, 0xe3, 0xb1, 0xdf, 0xe9, 0xb4, 0x68, 0x2b, 0xb6,
+       0xa5, 0x7c, 0x31, 0x61, 0x5f, 0x2b, 0x05, 0x1f, 0xc1, 0x35, 0x60, 0x29,
+       0x47, 0x86, 0x4a, 0x25, 0x3b, 0x1c, 0xc0, 0x9b, 0x3e, 0xba, 0x1f, 0xd6,
+       0x20, 0x3e, 0x99, 0x60, 0xf5, 0xe7, 0x1d, 0xc1, 0xf5, 0x98, 0xfc, 0x4e,
+       0x64, 0xbe, 0x89, 0x73, 0x82, 0x87, 0xcd, 0x9c, 0x03, 0xb9, 0x1d, 0x66,
+       0x43, 0x4d, 0x5f, 0xc7, 0x0e, 0x4b, 0xf9, 0xf6, 0x98, 0x7c, 0x61, 0xb2,
+       0x5f, 0x99, 0x8c, 0xf2, 0x49, 0x5b, 0x16, 0x94, 0xa4, 0x33, 0x1d, 0x5e,
+       0xe7, 0x64, 0xf2, 0xfc, 0x11, 0xd8, 0x7d, 0x7e, 0x75, 0xec, 0x1c, 0xa9,
+       0x49, 0xfc, 0x15, 0xe9, 0xef, 0x4f, 0x19, 0xad, 0x0d, 0x8d, 0xdd, 0x57,
+       0x16, 0x4d, 0xcf, 0x46, 0x79, 0xf3, 0x0c, 0xa0, 0x07, 0x2d, 0x9e, 0xe2,
+       0x61, 0x3b, 0x40, 0xff, 0x5a, 0xbc, 0x85, 0x74, 0x95, 0xf7, 0x5b, 0xe7,
+       0x98, 0xa6, 0x44, 0x12, 0xd0, 0xb5, 0x36, 0x53, 0x11, 0x70, 0x70, 0x3f,
+       0x6b, 0x58, 0xcc, 0xcf, 0xaa, 0x25, 0x7a, 0x78, 0xde, 0xde, 0x38, 0x04,
+       0xf0, 0xd5, 0x50, 0xdd, 0x4b, 0x7e, 0x96, 0xc7, 0xd4, 0xbe, 0xe4, 0x28,
+       0xae, 0xeb, 0x57, 0x2a, 0xcf, 0x93, 0x81, 0x27, 0x85, 0xfa, 0x60, 0x81,
+       0xf0, 0x9b, 0x17, 0x4c, 0x7d, 0x78, 0xc9, 0x51, 0xd0, 0x4b, 0x0b, 0xde,
+       0x1c, 0x42, 0x7a, 0x49, 0xce, 0xb3, 0x75, 0x45, 0x74, 0x98, 0xde, 0x3f,
+       0xc8, 0x1b, 0x20, 0x8e, 0x7a, 0x3a, 0x93, 0xeb, 0xf1, 0xc7, 0x57, 0x04,
+       0x86, 0xcd, 0x1f, 0x42, 0x70, 0x91, 0x5e, 0x90, 0x7e, 0x79, 0x41, 0xb8,
+       0x7e, 0x32, 0xc6, 0x37, 0x83, 0x58, 0x13, 0xc5, 0x89, 0x1b, 0x4d, 0xac,
+       0x26, 0xd1, 0x38, 0x0f, 0x8a, 0x71, 0xb2, 0x91, 0xe4, 0x08, 0xaf, 0xc3,
+       0x4e, 0xf2, 0x71, 0x6e, 0xe1, 0xc9, 0x34, 0x0d, 0xd6, 0x91, 0x9c, 0x1a,
+       0x7a, 0x10, 0xd7, 0x37, 0x77, 0x44, 0x57, 0x05, 0x8f, 0x03, 0x03, 0xfe,
+       0x99, 0xe0, 0x7f, 0x15, 0x44, 0xef, 0xd8, 0x88, 0xfd, 0x0b, 0x3c, 0x1a,
+       0x8b, 0x28, 0xfd, 0xe7, 0xcf, 0xae, 0x0e, 0xb5, 0x15, 0xc2, 0xfa, 0x5a,
+       0x32, 0x4d, 0x7e, 0x3b, 0xb5, 0x7b, 0x15, 0xec, 0x9f, 0x74, 0x1f, 0x63,
+       0x59, 0xd0, 0xbf, 0xe5, 0xbf, 0x54, 0x82, 0xa7, 0xe5, 0xd5, 0x6b, 0x18,
+       0xc6, 0x67, 0x49, 0xf6, 0x26, 0x86, 0x7e, 0xac, 0x5c, 0xd7, 0xa1, 0xcc,
+       0xc7, 0x08, 0x3f, 0x6a, 0x67, 0x0a, 0xd9, 0x3d, 0x86, 0x2e, 0x28, 0xe0,
+       0xef, 0x5b, 0x82, 0xf6, 0x9f, 0x7b, 0xe6, 0x77, 0xa1, 0x7f, 0xf1, 0xf9,
+       0x06, 0x33, 0xcd, 0xf7, 0x39, 0xac, 0xd1, 0x01, 0xe3, 0x7f, 0xde, 0xa9,
+       0x46, 0xd0, 0x59, 0x3f, 0x9a, 0x99, 0x1c, 0x35, 0x41, 0x5b, 0x6d, 0x4b,
+       0x25, 0x7b, 0x5d, 0x80, 0x3e, 0x27, 0xf4, 0x5f, 0xd8, 0x99, 0x1a, 0xf1,
+       0x15, 0xc6, 0xf0, 0xa2, 0x6d, 0x1e, 0xc7, 0xa2, 0x60, 0xdf, 0x92, 0xf2,
+       0xf8, 0xfa, 0x5b, 0x32, 0xed, 0x11, 0x7b, 0x21, 0xad, 0xfb, 0x87, 0x99,
+       0xa3, 0x63, 0x70, 0xca, 0x75, 0xe7, 0x0f, 0x10, 0x77, 0xbe, 0x22, 0xe0,
+       0x66, 0x81, 0xa1, 0x06, 0x3a, 0x7b, 0x21, 0x06, 0xeb, 0xc2, 0xb9, 0x35,
+       0x70, 0xf6, 0x61, 0x1c, 0x75, 0x83, 0x99, 0xe2, 0xc2, 0x05, 0x19, 0x76,
+       0x82, 0x33, 0xb2, 0x22, 0x3c, 0x6c, 0xbe, 0xb9, 0xff, 0xfa, 0x5a, 0x3d,
+       0x33, 0x6f, 0xbe, 0x1d, 0xe0, 0x69, 0x3e, 0xae, 0x32, 0x15, 0xc6, 0xf1,
+       0x75, 0xb7, 0x13, 0x3e, 0x16, 0x02, 0x3e, 0x22, 0xbe, 0xfe, 0xf8, 0x3e,
+       0xe7, 0x2b, 0xfc, 0xab, 0x49, 0x25, 0xb8, 0x5f, 0x41, 0x7a, 0xa9, 0x9b,
+       0x27, 0xd3, 0xba, 0x18, 0xfa, 0xf1, 0xf0, 0x5e, 0xfd, 0x13, 0x0a, 0x7b,
+       0xac, 0x10, 0xf9, 0x32, 0x34, 0x85, 0xe8, 0x9c, 0x63, 0x62, 0x4f, 0x15,
+       0x26, 0xf0, 0x0f, 0x50, 0xde, 0x5c, 0x88, 0x3f, 0x9e, 0x3f, 0xb0, 0x78,
+       0x4a, 0xb8, 0x9c, 0x78, 0x06, 0x0f, 0xdb, 0x01, 0xe3, 0xfd, 0x2a, 0x73,
+       0x40, 0x7f, 0xeb, 0xcd, 0x4c, 0x6e, 0xf7, 0xe9, 0x1a, 0xaf, 0x97, 0xc0,
+       0xfe, 0x85, 0x11, 0x8e, 0x0b, 0x9b, 0x15, 0xa2, 0xe7, 0x69, 0x25, 0x62,
+       0x31, 0x03, 0xca, 0x6a, 0x6f, 0x8d, 0x1a, 0xec, 0xbe, 0x1a, 0x50, 0xc9,
+       0xdf, 0x88, 0x87, 0x0b, 0xf4, 0xd8, 0x89, 0x4c, 0x9d, 0x9f, 0xa3, 0xa6,
+       0xdf, 0x37, 0x1c, 0xc7, 0x1d, 0xd8, 0x3f, 0xdb, 0x7d, 0xd0, 0x82, 0xfe,
+       0x99, 0x83, 0x91, 0x7f, 0x26, 0xf5, 0xe7, 0x40, 0xfe, 0x19, 0xfa, 0x65,
+       0xc8, 0x7f, 0xd2, 0x2f, 0xfb, 0x38, 0x4e, 0x0f, 0xc3, 0xfa, 0x3e, 0x15,
+       0xeb, 0xfb, 0x34, 0xd1, 0xfa, 0x12, 0xe8, 0xdd, 0x1e, 0xd2, 0xbb, 0xdf,
+       0x8c, 0x26, 0xf4, 0x6b, 0x5c, 0x96, 0xc4, 0x7a, 0x29, 0x37, 0x8b, 0xeb,
+       0xbb, 0x46, 0x87, 0x85, 0x51, 0x1e, 0x6a, 0x80, 0xbc, 0xba, 0x2b, 0x4b,
+       0xfa, 0x71, 0xdc, 0xaf, 0x18, 0x48, 0xcf, 0x5d, 0x2e, 0xde, 0x28, 0x5a,
+       0x5b, 0x4a, 0xfa, 0xf6, 0x42, 0x97, 0x2f, 0x3d, 0x13, 0xae, 0xce, 0x0f,
+       0x94, 0xa6, 0x44, 0xe3, 0xa8, 0xcb, 0x9f, 0x1d, 0x89, 0x74, 0x59, 0x6c,
+       0xab, 0x4c, 0xca, 0x02, 0xf8, 0xec, 0x59, 0x46, 0xfc, 0x6c, 0x59, 0xdd,
+       0xcf, 0x4e, 0xa5, 0x67, 0x71, 0x7c, 0xd1, 0xb5, 0x1f, 0xbe, 0xec, 0x80,
+       0x2f, 0x93, 0x01, 0x5f, 0xce, 0xac, 0x2f, 0xf5, 0x03, 0xb9, 0xde, 0xcd,
+       0xc1, 0xbc, 0x14, 0xcc, 0xd7, 0x23, 0xf0, 0x03, 0xfa, 0xf7, 0x22, 0xe9,
+       0xdf, 0x5b, 0x7a, 0x6e, 0xc3, 0x58, 0xb1, 0xfe, 0x96, 0x2f, 0x44, 0x9c,
+       0xcb, 0xfb, 0xbb, 0x85, 0x9e, 0x86, 0x38, 0xf8, 0x86, 0x8f, 0x7c, 0xd4,
+       0xff, 0xcf, 0x48, 0xbf, 0x58, 0x3c, 0xdc, 0x5d, 0x81, 0x71, 0x50, 0xf3,
+       0x0b, 0x57, 0xa4, 0xa3, 0x1f, 0x35, 0x71, 0xef, 0xed, 0x0e, 0xbc, 0x5e,
+       0x70, 0x0e, 0x26, 0xbc, 0x9c, 0xdb, 0x9b, 0x14, 0xc0, 0x79, 0xce, 0x65,
+       0x82, 0xfe, 0xb4, 0x63, 0x7b, 0xcc, 0x51, 0xcc, 0x13, 0x9c, 0x59, 0x71,
+       0x2c, 0x53, 0x8f, 0xd7, 0x73, 0xcf, 0xbd, 0x55, 0x61, 0x86, 0x71, 0xce,
+       0xed, 0x79, 0xab, 0x42, 0xc3, 0x7c, 0x83, 0xc8, 0xa7, 0xc8, 0xe7, 0xf5,
+       0x97, 0xde, 0xa9, 0x08, 0xc2, 0xfb, 0xe1, 0x09, 0x6c, 0x68, 0x93, 0x5d,
+       0x47, 0x5f, 0x2b, 0xd7, 0xef, 0x1b, 0x6c, 0x3c, 0x1f, 0xe1, 0x72, 0x5b,
+       0x5a, 0xd9, 0x08, 0xf0, 0x6b, 0x5d, 0x19, 0xf4, 0xfe, 0xa3, 0x6e, 0xd3,
+       0x0f, 0xf0, 0xbe, 0x6a, 0x7d, 0xa7, 0xe0, 0x43, 0x94, 0xe7, 0xb8, 0xfc,
+       0xcb, 0x06, 0xb3, 0xaf, 0xd9, 0x0e, 0x7c, 0x0e, 0x31, 0x96, 0x1f, 0xf3,
+       0xf8, 0x4b, 0x87, 0x05, 0xbc, 0x0b, 0x30, 0xff, 0x32, 0xc3, 0x43, 0x79,
+       0x93, 0x66, 0x85, 0xeb, 0xbd, 0xf0, 0x02, 0x1e, 0x1f, 0x3a, 0x8b, 0xd8,
+       0xd0, 0x42, 0x18, 0xcf, 0x6c, 0x52, 0x55, 0x7c, 0xaf, 0xd7, 0xcb, 0xfc,
+       0xdb, 0xa1, 0x4b, 0xd2, 0xe1, 0xf6, 0x28, 0xaa, 0xa9, 0xe4, 0xae, 0x8e,
+       0x00, 0x82, 0x3f, 0x2a, 0x39, 0x93, 0xf0, 0x7e, 0xdd, 0x59, 0x87, 0x82,
+       0xfe, 0xbe, 0xcc, 0xd7, 0x68, 0x55, 0x7c, 0xbc, 0xde, 0x59, 0x96, 0xc8,
+       0x76, 0x5d, 0x9e, 0xc6, 0x33, 0x47, 0x23, 0x3b, 0x96, 0xa2, 0x75, 0x30,
+       0xd4, 0xab, 0xb3, 0x5c, 0xfc, 0x7d, 0x99, 0xaf, 0xa9, 0x9a, 0x39, 0x27,
+       0x58, 0x89, 0x70, 0x3d, 0x60, 0xa2, 0x78, 0x03, 0x14, 0xa5, 0x82, 0xfa,
+       0x2b, 0x57, 0xac, 0xa3, 0xd0, 0xbb, 0x67, 0xb5, 0xf4, 0x45, 0x34, 0x37,
+       0xb2, 0x15, 0xc3, 0xe4, 0x0c, 0x5b, 0x0b, 0xfc, 0x3b, 0x18, 0xf0, 0x9c,
+       0xe6, 0x33, 0x05, 0x30, 0x3f, 0x9a, 0x96, 0x17, 0x3d, 0x61, 0x06, 0x3f,
+       0x2c, 0xb7, 0x85, 0xb1, 0x53, 0x3a, 0x7f, 0x2f, 0x05, 0x99, 0x0f, 0xd7,
+       0xf3, 0xa6, 0x1a, 0xd9, 0x0e, 0xf2, 0x9f, 0xfa, 0xc5, 0x78, 0xeb, 0x1c,
+       0xf0, 0x67, 0x52, 0x92, 0xb9, 0xfc, 0xa4, 0x05, 0x5b, 0x97, 0x60, 0xde,
+       0x1a, 0xef, 0xff, 0x6b, 0x39, 0xd2, 0x85, 0xbf, 0x4f, 0xf4, 0x51, 0x31,
+       0x8d, 0xc4, 0xc2, 0xe9, 0x00, 0x72, 0xea, 0x58, 0xe3, 0xb8, 0x92, 0x7e,
+       0x9d, 0x2b, 0xac, 0xfe, 0xc1, 0xc0, 0xa8, 0x7b, 0x56, 0x38, 0xe8, 0xfa,
+       0xf4, 0x0a, 0x0f, 0xc1, 0xf5, 0xf0, 0x0a, 0x1f, 0x5d, 0x7f, 0xb8, 0x62,
+       0x28, 0xdd, 0x1f, 0x48, 0xce, 0x2e, 0x77, 0x7d, 0x68, 0x05, 0xcc, 0xab,
+       0xe3, 0x27, 0xe7, 0x18, 0xc0, 0x0a, 0xac, 0xd7, 0xa9, 0x32, 0x92, 0xc7,
+       0x87, 0x46, 0x57, 0xa4, 0xcf, 0x4d, 0xa0, 0x07, 0xe4, 0xf5, 0xb1, 0x15,
+       0xc7, 0xdc, 0x13, 0x87, 0x08, 0x04, 0x02, 0x3d, 0x72, 0xea, 0x1c, 0xdb,
+       0xd6, 0x14, 0x12, 0x9d, 0x51, 0x68, 0x60, 0x75, 0xaf, 0xad, 0x0e, 0x8c,
+       0x63, 0xec, 0x01, 0x73, 0x60, 0x09, 0x03, 0xd6, 0x7a, 0x20, 0xeb, 0x8b,
+       0x89, 0x98, 0x57, 0x5a, 0xab, 0x98, 0x28, 0x8f, 0xd4, 0x9a, 0x75, 0x70,
+       0x75, 0x38, 0x0f, 0xaf, 0x3e, 0x4e, 0xb7, 0x43, 0xef, 0x32, 0xcc, 0x47,
+       0x7a, 0x47, 0xb5, 0x2b, 0x28, 0xaf, 0xde, 0xba, 0x76, 0xe2, 0x83, 0x51,
+       0x5d, 0x5d, 0x2c, 0x24, 0xee, 0x07, 0xa0, 0xed, 0x3d, 0xce, 0xef, 0x3f,
+       0x60, 0xe3, 0x78, 0x5e, 0xc7, 0xd8, 0x14, 0x84, 0xd7, 0xae, 0xb0, 0x20,
+       0x5e, 0x7b, 0x6c, 0xdc, 0x9e, 0x7c, 0x6c, 0xe3, 0x7a, 0xed, 0x53, 0x71,
+       0x2d, 0xcc, 0x0a, 0x3d, 0x9c, 0x05, 0xf7, 0xff, 0xe2, 0x38, 0x51, 0xf2,
+       0x00, 0x80, 0x67, 0x2b, 0xfd, 0x7d, 0x01, 0xee, 0x47, 0xa4, 0x1c, 0xfa,
+       0x1b, 0xe5, 0x6b, 0xd5, 0xe1, 0x16, 0x2b, 0xca, 0x87, 0xf7, 0xc0, 0xfb,
+       0xb4, 0x4f, 0xa1, 0x9a, 0xba, 0x2d, 0x0c, 0x4c, 0xe8, 0xf3, 0x8f, 0xbc,
+       0x4b, 0xf9, 0x2f, 0xd5, 0x12, 0x2c, 0xe4, 0xed, 0x9f, 0xaf, 0xc1, 0x75,
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+       0x89, 0x76, 0xf8, 0xdf, 0x08, 0x0f, 0x6b, 0xcd, 0xbc, 0xfd, 0xfc, 0x23,
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+       0xc6, 0xdb, 0xcc, 0xca, 0xaf, 0x72, 0x7d, 0xf5, 0x87, 0xfe, 0x76, 0x34,
+       0x17, 0xf8, 0xb5, 0xe1, 0x80, 0xd2, 0x81, 0xa0, 0x79, 0x0f, 0xac, 0x57,
+       0x70, 0x9d, 0xde, 0x7d, 0xeb, 0x09, 0xdf, 0xf4, 0x07, 0xf2, 0x81, 0xcb,
+       0xa0, 0x3c, 0xa6, 0x35, 0x4c, 0x79, 0xaf, 0xa7, 0x57, 0x1c, 0x73, 0xb4,
+       0x00, 0x9d, 0xb5, 0xcc, 0x36, 0x37, 0xe2, 0xfd, 0x0a, 0x4f, 0x28, 0x10,
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+       0x22, 0xe6, 0xde, 0x6e, 0x9d, 0xff, 0xec, 0x65, 0x5c, 0x6e, 0x58, 0x0b,
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+       0x83, 0x12, 0x5a, 0xa3, 0xa2, 0x9e, 0xf9, 0x99, 0xd9, 0x81, 0x7a, 0x84,
+       0x75, 0x71, 0x3d, 0x74, 0x56, 0x8c, 0xc5, 0x22, 0x39, 0xe4, 0x8f, 0xd4,
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+       0xc5, 0xfd, 0x82, 0xf5, 0x05, 0x98, 0xcf, 0x6f, 0x60, 0xed, 0x77, 0x7e,
+       0x0f, 0xe1, 0xfd, 0xb5, 0xca, 0xd0, 0xaf, 0xfe, 0xf4, 0xe0, 0x35, 0xe9,
+       0xd7, 0x41, 0xbb, 0x1e, 0xda, 0x68, 0xe7, 0xeb, 0x3b, 0xdf, 0xb2, 0x20,
+       0x7f, 0x3e, 0xe8, 0xe4, 0xfa, 0xb3, 0xa1, 0x13, 0xf8, 0x07, 0xc6, 0x59,
+       0x07, 0xf2, 0x15, 0x00, 0xc7, 0x63, 0x9b, 0xe6, 0x48, 0x46, 0xfd, 0xf4,
+       0x74, 0xa0, 0xe9, 0x4a, 0x74, 0xc9, 0x7a, 0x1f, 0xf9, 0xcb, 0x54, 0x1b,
+       0x38, 0x75, 0xcf, 0x14, 0x05, 0x1c, 0x44, 0x6f, 0xe7, 0xa5, 0xd5, 0x56,
+       0x6c, 0x5b, 0x1c, 0xc3, 0x58, 0x19, 0xb6, 0x2d, 0x6b, 0x90, 0xdf, 0x6a,
+       0xcb, 0x4c, 0x5c, 0x8e, 0x98, 0xe5, 0x57, 0x01, 0x4d, 0xec, 0x4f, 0x42,
+       0xfb, 0xb7, 0x8f, 0x54, 0xdd, 0x14, 0xb6, 0xc7, 0xec, 0x8d, 0x57, 0xd8,
+       0xa7, 0xc6, 0xad, 0xf6, 0xb0, 0x89, 0xdb, 0xa7, 0xf3, 0x68, 0xd7, 0x1a,
+       0x36, 0x9b, 0xc2, 0xa8, 0xbf, 0x4c, 0xd6, 0x2e, 0x0b, 0xd2, 0xd7, 0x8e,
+       0x7b, 0xaf, 0x44, 0x1f, 0x07, 0xe1, 0x6d, 0x99, 0xd4, 0xe7, 0x71, 0xfa,
+       0x7a, 0xd9, 0xd4, 0xcc, 0x9b, 0xb0, 0xbd, 0xec, 0x81, 0x22, 0x47, 0xf8,
+       0x4b, 0xf2, 0x8a, 0x35, 0x17, 0x53, 0x58, 0x44, 0xe7, 0xcf, 0x3c, 0xe8,
+       0xe4, 0x72, 0x5c, 0xa3, 0x85, 0x69, 0x9f, 0xa3, 0xe6, 0x62, 0x1a, 0x3d,
+       0xff, 0xe7, 0xcd, 0x67, 0x63, 0x91, 0x91, 0x5f, 0x36, 0x9f, 0x9d, 0x9e,
+       0xcb, 0xf9, 0xea, 0x62, 0xf3, 0x11, 0x5d, 0x0f, 0x95, 0xff, 0x6a, 0xe3,
+       0x60, 0xa0, 0xdb, 0xb2, 0xdd, 0x66, 0x53, 0x92, 0x8e, 0xef, 0x96, 0xed,
+       0x16, 0xfb, 0xc9, 0xb6, 0x40, 0x36, 0x8e, 0xe3, 0xb2, 0x30, 0x81, 0x77,
+       0xf0, 0xcf, 0x01, 0xbf, 0x5a, 0x61, 0x5f, 0x3b, 0xac, 0x81, 0x9c, 0x3f,
+       0xd4, 0x27, 0xe7, 0xde, 0x35, 0x13, 0xc7, 0x21, 0xdd, 0x62, 0xcf, 0xd9,
+       0x58, 0x83, 0x1e, 0x08, 0x60, 0x7c, 0xf8, 0x50, 0xb2, 0xd4, 0x03, 0x85,
+       0x89, 0xfb, 0x27, 0xc7, 0xf5, 0x2f, 0x92, 0xed, 0x2b, 0xa9, 0x7f, 0x3c,
+       0x3c, 0xae, 0xe4, 0x58, 0xdb, 0x0a, 0xfd, 0xb5, 0xbf, 0x27, 0xf5, 0xb5,
+       0x11, 0xbe, 0xf5, 0xa6, 0xb8, 0xf1, 0x32, 0xe5, 0xfc, 0xe5, 0x6b, 0x26,
+       0xe6, 0xc5, 0xf8, 0xea, 0xb7, 0x59, 0xd7, 0xfd, 0x2a, 0x3c, 0x18, 0x9e,
+       0x67, 0xb4, 0x57, 0x62, 0x7d, 0x45, 0xef, 0x02, 0xe6, 0x43, 0xbb, 0x8c,
+       0xfc, 0xea, 0xd7, 0xe9, 0xfd, 0xdf, 0x0a, 0xbf, 0xaf, 0xe6, 0x62, 0xb1,
+       0x81, 0xde, 0x31, 0xbc, 0x97, 0x18, 0xee, 0x9f, 0x5e, 0xe1, 0x31, 0xec,
+       0xcb, 0x2d, 0xaa, 0x5e, 0x46, 0xfb, 0x87, 0xbf, 0x15, 0x7a, 0xbe, 0x86,
+       0x85, 0x29, 0x0e, 0xaa, 0xd9, 0x9a, 0xcb, 0x22, 0xba, 0xbc, 0xc4, 0xff,
+       0x87, 0xe3, 0x1f, 0x85, 0xe3, 0xba, 0x01, 0xe0, 0xb8, 0xe1, 0x7f, 0x19,
+       0x8e, 0x42, 0x83, 0x7c, 0xc6, 0xe0, 0x18, 0x6c, 0xb8, 0xff, 0x8f, 0xc2,
+       0xb1, 0xfd, 0xb6, 0x92, 0x9b, 0x0a, 0xa1, 0xcb, 0xa3, 0x4a, 0xd8, 0x5a,
+       0x84, 0x76, 0xe1, 0x7e, 0x13, 0xe5, 0x39, 0xd4, 0x8c, 0x89, 0xbe, 0x95,
+       0xb8, 0x2f, 0x70, 0xbf, 0x46, 0x7e, 0x1e, 0xba, 0x24, 0x58, 0x9f, 0x51,
+       0xa4, 0xb1, 0x63, 0x5a, 0x39, 0xca, 0x4f, 0x7b, 0x00, 0xe3, 0x72, 0xb6,
+       0x8a, 0xe7, 0x7b, 0xe0, 0x7e, 0x9b, 0xb9, 0x9c, 0xec, 0x10, 0xf9, 0xc1,
+       0xc5, 0x07, 0x92, 0xee, 0x46, 0x3f, 0xad, 0xa8, 0x26, 0xb0, 0x18, 0xaf,
+       0x2c, 0xaf, 0x94, 0xf6, 0x1d, 0xe4, 0xbe, 0x1d, 0x13, 0x79, 0x2b, 0xb9,
+       0xcf, 0x30, 0xc4, 0xc1, 0x2a, 0x35, 0x70, 0xde, 0x46, 0xb8, 0xee, 0x26,
+       0x3b, 0x55, 0x14, 0xac, 0xae, 0x45, 0x67, 0x4e, 0x4d, 0x1d, 0x95, 0x8c,
+       0xf6, 0xf1, 0x51, 0x53, 0x24, 0x8c, 0xf3, 0x85, 0x1f, 0xe6, 0xf3, 0xb9,
+       0x4c, 0x91, 0x0e, 0x2b, 0xea, 0xde, 0xb4, 0xc1, 0x0e, 0xb4, 0x77, 0xae,
+       0x34, 0xae, 0xff, 0xd8, 0x9a, 0x52, 0xb2, 0x7f, 0xdb, 0x4d, 0x45, 0x57,
+       0x2e, 0x01, 0x38, 0x1e, 0x50, 0x2a, 0x93, 0x5f, 0x47, 0x3c, 0x67, 0x14,
+       0x51, 0x9e, 0x16, 0xef, 0x2f, 0x85, 0xfb, 0xdb, 0x85, 0xdd, 0x52, 0x33,
+       0xfc, 0x0e, 0xb4, 0x53, 0xdb, 0x85, 0xdd, 0x6a, 0x16, 0xfa, 0x5d, 0xde,
+       0x4f, 0xc9, 0x0c, 0xde, 0x8d, 0xfe, 0xc4, 0x49, 0x67, 0xc3, 0x4d, 0xd6,
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+       0xc6, 0x73, 0x0d, 0xda, 0x1b, 0x5f, 0x91, 0x15, 0xec, 0xcb, 0x1f, 0x36,
+       0xd4, 0xaf, 0x41, 0x7b, 0xb3, 0x7d, 0xa5, 0x2f, 0xc7, 0x91, 0x11, 0x6b,
+       0x0f, 0xf9, 0x3b, 0x58, 0x6b, 0xd2, 0x13, 0xf5, 0x6b, 0xd0, 0x5f, 0x69,
+       0xb1, 0x2f, 0xbd, 0x07, 0xfd, 0x1d, 0x78, 0xfe, 0x2b, 0x2b, 0xac, 0xf3,
+       0x99, 0x4c, 0xa1, 0x77, 0xc4, 0xf3, 0xa2, 0x3e, 0x3d, 0x05, 0x7a, 0x09,
+       0xf4, 0x98, 0xba, 0xb2, 0xaf, 0x1d, 0x46, 0xbd, 0x54, 0xd4, 0xa7, 0x77,
+       0xea, 0x49, 0xef, 0xec, 0x78, 0x5c, 0xa5, 0xf6, 0x41, 0x98, 0x0f, 0xfd,
+       0x3e, 0x58, 0x47, 0x58, 0xc5, 0xf5, 0x0e, 0xd1, 0xc8, 0xaf, 0xb7, 0x01,
+       0x2c, 0xc9, 0xd0, 0xb6, 0x0d, 0x2b, 0xa2, 0xfd, 0x1b, 0x58, 0x37, 0x4b,
+       0x46, 0xff, 0x7a, 0x18, 0x7f, 0x2e, 0xf3, 0xee, 0x96, 0x21, 0x26, 0xca,
+       0xbb, 0x63, 0x7f, 0xc4, 0xa3, 0xcd, 0xcb, 0xfb, 0x5b, 0x66, 0x30, 0x3f,
+       0xee, 0x37, 0x59, 0x52, 0xed, 0x14, 0x87, 0xc8, 0x3c, 0xbe, 0x2a, 0xf6,
+       0x8f, 0x92, 0x45, 0x1d, 0x85, 0xe2, 0x98, 0xc1, 0x2e, 0xc1, 0xfb, 0xd6,
+       0x75, 0xe5, 0x4b, 0x31, 0x1e, 0xb3, 0x0e, 0x36, 0xee, 0x93, 0x5a, 0xe2,
+       0xea, 0x2d, 0xd4, 0xf8, 0xfa, 0x0b, 0x7b, 0x94, 0xfc, 0xaf, 0xf7, 0x9c,
+       0x22, 0xff, 0x9e, 0xc5, 0x3c, 0x97, 0x8a, 0x63, 0xf7, 0x19, 0xf3, 0x97,
+       0xe3, 0xd5, 0x7d, 0x7b, 0x4b, 0x25, 0xc2, 0xbb, 0x34, 0x95, 0x39, 0x54,
+       0xcc, 0x83, 0x84, 0xa2, 0xb4, 0x0f, 0x19, 0x6f, 0xd7, 0xac, 0x60, 0x47,
+       0x7d, 0x3a, 0xf9, 0xb0, 0xda, 0x59, 0x20, 0xd1, 0x7e, 0xff, 0x8b, 0x2e,
+       0xee, 0xd7, 0xda, 0x2f, 0x6a, 0x14, 0xdf, 0x6c, 0x50, 0xc0, 0xbf, 0x41,
+       0x3b, 0x9a, 0xca, 0xf9, 0x4c, 0xfa, 0x47, 0x66, 0x87, 0xe4, 0x5b, 0xa3,
+       0xdd, 0x95, 0xfe, 0x92, 0x39, 0x83, 0xaf, 0x65, 0xd9, 0xd4, 0x09, 0xd9,
+       0x18, 0x7f, 0xab, 0xf6, 0x80, 0x15, 0xfd, 0x9c, 0x83, 0x8e, 0x72, 0x8a,
+       0xeb, 0x55, 0xe6, 0xbf, 0xb9, 0x52, 0xe7, 0xef, 0xb4, 0x44, 0xa7, 0x52,
+       0xbe, 0x4c, 0x73, 0x04, 0xc8, 0x0f, 0xcf, 0xc6, 0x38, 0x11, 0xf3, 0x3d,
+       0x0e, 0x3f, 0xd3, 0xfb, 0x39, 0xad, 0x2b, 0x20, 0xb0, 0xbc, 0x82, 0xb1,
+       0x27, 0x2b, 0x4a, 0x26, 0xa0, 0x3c, 0x3c, 0x66, 0x8b, 0x5a, 0x8b, 0x91,
+       0xbe, 0x8f, 0x9a, 0x28, 0xde, 0x3b, 0x54, 0x7e, 0x4f, 0x58, 0xc1, 0x7c,
+       0xd9, 0x72, 0x46, 0x72, 0xfa, 0x64, 0x85, 0x7b, 0x02, 0xe6, 0xbb, 0xb7,
+       0x69, 0xc1, 0xf4, 0x3b, 0x50, 0x5e, 0x8e, 0xc3, 0x7c, 0x3e, 0x4e, 0x37,
+       0xbe, 0xcf, 0xda, 0xac, 0x60, 0x7e, 0xf7, 0x73, 0x6b, 0x30, 0x1d, 0xf5,
+       0xc1, 0x43, 0xc8, 0xf7, 0x3a, 0xbc, 0x3c, 0xe9, 0xe2, 0x7e, 0xfd, 0x05,
+       0x27, 0xf7, 0x3b, 0x1f, 0x30, 0x73, 0xb9, 0x68, 0x05, 0x78, 0xa2, 0x00,
+       0x87, 0x76, 0xf1, 0x2a, 0xca, 0x47, 0x3d, 0xe0, 0xe2, 0xfa, 0xc9, 0x52,
+       0x3d, 0x91, 0xf2, 0x35, 0x16, 0xc0, 0x07, 0xe6, 0xe3, 0x92, 0x58, 0x53,
+       0xd8, 0x41, 0xeb, 0xe5, 0xf9, 0xb5, 0x24, 0x8f, 0xc9, 0x50, 0xb7, 0xa7,
+       0x5d, 0x1c, 0x4e, 0xef, 0x5f, 0x70, 0x9a, 0x0c, 0x71, 0x75, 0x1b, 0xac,
+       0xd3, 0xa7, 0xd3, 0x5f, 0x36, 0x16, 0xa6, 0xfc, 0x1a, 0xe2, 0xf8, 0xa9,
+       0x04, 0xfe, 0xcb, 0x41, 0x41, 0x37, 0x2b, 0xf8, 0x43, 0x3e, 0xf2, 0x4f,
+       0xe2, 0xf6, 0xa1, 0xfb, 0xfb, 0x47, 0xe4, 0xaf, 0x48, 0xfa, 0xf4, 0xf9,
+       0x29, 0x0a, 0xf8, 0x27, 0x5f, 0x12, 0x8f, 0x35, 0x42, 0xbc, 0xac, 0xd7,
+       0xf7, 0x8d, 0x5a, 0x2f, 0xe9, 0xdf, 0x46, 0x88, 0x87, 0xf1, 0x7e, 0x8f,
+       0xc3, 0x4a, 0xfe, 0xa1, 0xac, 0x4b, 0xb0, 0x0b, 0x7d, 0xd6, 0xea, 0x09,
+       0xb5, 0x5f, 0x87, 0x7c, 0x9e, 0x9c, 0x36, 0x1c, 0xf3, 0x00, 0x1a, 0xeb,
+       0x20, 0xa4, 0xac, 0xc3, 0xba, 0x04, 0xd4, 0x87, 0x1e, 0xad, 0xb7, 0x8f,
+       0xff, 0x41, 0xe6, 0x9b, 0x6d, 0x69, 0xdb, 0xb1, 0x5f, 0x8b, 0xa8, 0x53,
+       0x48, 0xf1, 0x1b, 0xe5, 0x27, 0x99, 0xb5, 0x47, 0x03, 0x28, 0x9f, 0x43,
+       0x75, 0x72, 0xc3, 0x10, 0xdf, 0x61, 0x1a, 0x37, 0xc9, 0x67, 0xbc, 0xcf,
+       0x58, 0x88, 0x61, 0x9c, 0xa1, 0x79, 0xe2, 0xeb, 0x18, 0xc2, 0x7d, 0xf5,
+       0x4a, 0x54, 0x6f, 0xa7, 0xb1, 0x2d, 0xb8, 0xaf, 0x2c, 0xfd, 0xde, 0x5c,
+       0x51, 0x2f, 0x74, 0x2e, 0xe5, 0x8f, 0x15, 0x28, 0xc7, 0xe0, 0xf7, 0x8e,
+       0xce, 0xa2, 0xbc, 0x4d, 0x2f, 0xc5, 0x2d, 0x32, 0x5f, 0xf3, 0x75, 0xfd,
+       0xe4, 0x6c, 0x1c, 0x03, 0xe3, 0xd1, 0xe5, 0x7f, 0xae, 0xf8, 0x10, 0xe5,
+       0x6c, 0xc6, 0xe4, 0x42, 0xbc, 0x9f, 0xa2, 0x71, 0x3e, 0x01, 0x57, 0x5c,
+       0x4b, 0x2a, 0xc7, 0xf0, 0x6a, 0xf2, 0xe2, 0x0c, 0x58, 0xff, 0x37, 0xb2,
+       0x38, 0xff, 0x39, 0xd5, 0x76, 0xaa, 0xeb, 0x78, 0x5e, 0xd8, 0xb1, 0xbf,
+       0x38, 0xe6, 0x78, 0x29, 0x8e, 0x02, 0x7c, 0x52, 0x3d, 0x4c, 0xb2, 0xbf,
+       0x9b, 0xe2, 0x45, 0xe1, 0xa7, 0xa9, 0x7d, 0xfa, 0xf1, 0xdd, 0xd5, 0x01,
+       0xa3, 0xdf, 0x19, 0xd6, 0xfb, 0x79, 0x2b, 0x1e, 0x7d, 0x77, 0x75, 0x4b,
+       0x29, 0xc5, 0x2b, 0xd4, 0x7e, 0xfe, 0x91, 0x17, 0xd7, 0x60, 0x3c, 0xf8,
+       0x80, 0x4d, 0xb6, 0x5f, 0xa0, 0x36, 0xd8, 0xb9, 0x28, 0xc6, 0x4b, 0x6c,
+       0x6f, 0x92, 0x0f, 0xf9, 0x10, 0xde, 0x0f, 0xa0, 0xbc, 0xb1, 0xdb, 0x4a,
+       0xc8, 0xcf, 0x56, 0x8b, 0x58, 0x0e, 0xe2, 0x63, 0x62, 0x9a, 0x95, 0xf4,
+       0xa6, 0xba, 0x37, 0x69, 0x3b, 0xfa, 0xc1, 0x10, 0x17, 0x3f, 0x97, 0xa5,
+       0xcb, 0x73, 0x9e, 0x4b, 0x3d, 0x51, 0x80, 0xfe, 0x70, 0x82, 0xf1, 0xc2,
+       0x86, 0xf1, 0x0a, 0xbe, 0xde, 0x78, 0x30, 0x7f, 0x27, 0xd6, 0xcb, 0xc8,
+       0xe7, 0x13, 0xd3, 0x36, 0x47, 0x55, 0xfe, 0x9e, 0x0f, 0xdf, 0x63, 0x79,
+       0x5d, 0x7f, 0x0c, 0xc3, 0xf8, 0x8f, 0xbe, 0x90, 0xc4, 0xd6, 0x00, 0x0a,
+       0x1f, 0x33, 0x1b, 0xe5, 0x5d, 0x5e, 0x37, 0x8a, 0x38, 0x13, 0xf5, 0x8d,
+       0xbe, 0x5e, 0xd1, 0x52, 0x3d, 0x3f, 0x80, 0x4c, 0x2d, 0xe5, 0x3a, 0xc9,
+       0x93, 0xcc, 0xa2, 0x3a, 0x7e, 0x92, 0x72, 0xae, 0x5d, 0x1c, 0xc6, 0xa2,
+       0x3a, 0x39, 0xc9, 0x76, 0x15, 0x12, 0xbd, 0x34, 0x2d, 0x40, 0x79, 0x24,
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+       0x9f, 0x97, 0x7f, 0x5f, 0x05, 0xfa, 0xf9, 0xd9, 0xf1, 0xa8, 0x2f, 0x41,
+       0xdf, 0xa3, 0xbf, 0x59, 0xa1, 0x05, 0xa6, 0x61, 0xff, 0x8a, 0xae, 0x4c,
+       0xda, 0xa7, 0x92, 0xfc, 0x21, 0xf9, 0x42, 0xd2, 0xb5, 0x33, 0xb3, 0x89,
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+       0xee, 0xe1, 0x33, 0xaf, 0xee, 0x0f, 0xff, 0xaf, 0x85, 0x1f, 0x05, 0x74,
+       0xe4, 0xf8, 0x7f, 0xc1, 0x46, 0x75, 0x0a, 0xf1, 0xf6, 0x32, 0x86, 0xff,
+       0xdc, 0xcb, 0xd0, 0xb3, 0x80, 0x9e, 0x4b, 0x7f, 0xa8, 0x6e, 0x40, 0xbb,
+       0x99, 0x46, 0xef, 0x65, 0x9f, 0x88, 0xa6, 0xf9, 0xa0, 0x5f, 0x97, 0xe0,
+       0xff, 0xce, 0x8e, 0x0f, 0xd2, 0xae, 0x43, 0xb9, 0xd8, 0xa7, 0x32, 0xc5,
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+       0x68, 0xe4, 0x97, 0xc5, 0xec, 0x87, 0x8f, 0xfc, 0x33, 0xa9, 0x3f, 0xa3,
+       0x56, 0x6b, 0xac, 0x7f, 0x70, 0xe3, 0x88, 0x69, 0x2d, 0xa8, 0xbf, 0x93,
+       0xb8, 0xbc, 0x3a, 0x55, 0xb0, 0x36, 0xe5, 0x31, 0x38, 0x1e, 0xce, 0xe6,
+       0x7a, 0x6c, 0x6c, 0x28, 0x71, 0x7c, 0xf3, 0x03, 0x77, 0x2a, 0x3d, 0x97,
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+       0xd8, 0xee, 0xb0, 0x82, 0x74, 0x59, 0x20, 0xf0, 0xd8, 0xe7, 0xcf, 0x08,
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+       0x36, 0xf8, 0x3b, 0x0d, 0xa6, 0x62, 0xdd, 0x73, 0x3b, 0xd7, 0xbb, 0x72,
+       0x3e, 0x80, 0xb7, 0x85, 0x61, 0xc9, 0x0a, 0x5c, 0x15, 0xb8, 0xde, 0xe6,
+       0x29, 0x14, 0xe3, 0x70, 0xbe, 0x3c, 0xb5, 0x37, 0x7b, 0x1b, 0xea, 0x0f,
+       0x67, 0x71, 0xa0, 0x0c, 0xf5, 0x8d, 0xe4, 0x2f, 0xb0, 0x27, 0x62, 0xbd,
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+       0xb9, 0x06, 0x18, 0x3f, 0x84, 0x13, 0xc2, 0x67, 0x31, 0xdc, 0x3f, 0xb5,
+       0xc2, 0x0a, 0x02, 0xae, 0x83, 0xe3, 0x93, 0xc1, 0x54, 0x7f, 0xb2, 0xc5,
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+       0xc7, 0xc3, 0x75, 0xc6, 0xf3, 0x8f, 0xc6, 0x6b, 0xc5, 0x03, 0xe0, 0xb9,
+       0xe4, 0x7f, 0x25, 0x5e, 0xab, 0x18, 0xc7, 0xf5, 0x1a, 0x6b, 0x57, 0xa8,
+       0x96, 0x66, 0xcc, 0xc4, 0x38, 0xff, 0x59, 0xd8, 0xcb, 0x4b, 0x9e, 0x14,
+       0x43, 0x1e, 0x60, 0x7e, 0xb5, 0xb1, 0x9f, 0xea, 0xe5, 0xf1, 0xbf, 0xea,
+       0x4d, 0x31, 0xf8, 0xcd, 0x03, 0xe5, 0x01, 0xf4, 0x7e, 0xb3, 0x52, 0x8c,
+       0xfa, 0x83, 0x8f, 0xd7, 0x20, 0xec, 0x56, 0xe1, 0x67, 0x6f, 0x53, 0x1d,
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+       0x27, 0xea, 0xd8, 0xd7, 0xd9, 0xf8, 0x77, 0xfe, 0xdb, 0xfe, 0x7e, 0xc8,
+       0x33, 0x0f, 0xfd, 0x8d, 0x37, 0xcd, 0x54, 0x77, 0xc0, 0xf6, 0x71, 0xfe,
+       0xa9, 0xfc, 0xf1, 0xb2, 0x66, 0x3c, 0x37, 0xc0, 0xde, 0xa1, 0x38, 0xf4,
+       0xdf, 0xb5, 0x7e, 0x63, 0xb9, 0x12, 0x98, 0x0f, 0xf2, 0xe0, 0x16, 0x7a,
+       0xa2, 0xce, 0xcf, 0xd7, 0x53, 0xe7, 0x8f, 0x5a, 0x06, 0xdb, 0xb1, 0xae,
+       0x99, 0xc3, 0x91, 0xd7, 0x71, 0x50, 0xd1, 0x74, 0x7a, 0x23, 0xaf, 0x86,
+       0xf7, 0xf3, 0x79, 0xcd, 0x86, 0xfa, 0x80, 0xc1, 0x5e, 0x7e, 0x2e, 0x43,
+       0x91, 0x57, 0xe6, 0x0d, 0x23, 0x07, 0xa7, 0x3a, 0xb1, 0x7f, 0x40, 0x43,
+       0x3b, 0x93, 0xd3, 0xa1, 0x90, 0x1d, 0xca, 0x69, 0x62, 0xf4, 0x3d, 0x4e,
+       0xce, 0x28, 0xee, 0x9f, 0x7d, 0x63, 0xd4, 0x36, 0x65, 0x5e, 0x69, 0x6c,
+       0xbd, 0x6d, 0xa6, 0x19, 0xa5, 0x0e, 0x78, 0xaf, 0xcd, 0x9d, 0xe2, 0x47,
+       0xbd, 0xbd, 0x2a, 0x27, 0x74, 0xa5, 0x17, 0xe1, 0x3b, 0x19, 0x8d, 0x62,
+       0x3a, 0x67, 0xcc, 0xc9, 0x2e, 0x0d, 0xe3, 0xa7, 0x0d, 0x39, 0x81, 0xab,
+       0x10, 0x0f, 0x72, 0x9d, 0x3e, 0xd5, 0x91, 0x83, 0xf6, 0x27, 0xe5, 0x24,
+       0x87, 0xaf, 0xbd, 0x2f, 0x2f, 0xc1, 0xf5, 0x36, 0x63, 0x6b, 0x05, 0x5c,
+       0xdb, 0x79, 0x7c, 0xa8, 0xb2, 0x63, 0x8c, 0xfb, 0xbd, 0xb4, 0x8f, 0xeb,
+       0x5e, 0x35, 0x94, 0xec, 0x87, 0x5c, 0x8f, 0x3b, 0x53, 0xe8, 0x5f, 0x37,
+       0x0b, 0xed, 0x21, 0xff, 0x9b, 0xb5, 0x91, 0xfd, 0xb3, 0x72, 0x7b, 0xea,
+       0x5e, 0x55, 0x42, 0x7e, 0xb2, 0xa4, 0x6b, 0x2c, 0x9f, 0x32, 0xac, 0x1c,
+       0xf3, 0x29, 0xc5, 0xeb, 0xa2, 0xda, 0x5c, 0x78, 0xef, 0xc5, 0xad, 0xa6,
+       0x84, 0xe7, 0x58, 0x4c, 0x15, 0x78, 0x87, 0x75, 0x4c, 0xd4, 0xaf, 0xe3,
+       0x72, 0xf2, 0x2e, 0xfb, 0x99, 0x07, 0xc8, 0x53, 0x49, 0xbe, 0x4f, 0x99,
+       0x92, 0x38, 0xfe, 0x83, 0x08, 0x90, 0x9e, 0x57, 0xfe, 0xd8, 0xf9, 0x4d,
+       0x92, 0xcf, 0x16, 0x0b, 0xc3, 0xfc, 0xa6, 0xc4, 0xff, 0x86, 0x9c, 0xe0,
+       0x6c, 0x84, 0x27, 0xa7, 0x63, 0x9b, 0x82, 0xb8, 0x39, 0x25, 0xea, 0x23,
+       0x4e, 0x25, 0xf3, 0xfc, 0xed, 0xa9, 0x35, 0xcf, 0x2a, 0xe8, 0x87, 0xdd,
+       0xbb, 0x98, 0x39, 0x54, 0x36, 0x30, 0xdc, 0x75, 0xcb, 0xd5, 0xc0, 0x7c,
+       0xbd, 0x3c, 0xb7, 0x58, 0x88, 0x2e, 0x32, 0x0e, 0x88, 0xc1, 0xc3, 0xe3,
+       0x96, 0x26, 0x2f, 0xd7, 0xeb, 0xaf, 0xe7, 0x04, 0x17, 0x21, 0xbd, 0x1b,
+       0xf6, 0xad, 0xa7, 0xfc, 0xde, 0xe2, 0x1d, 0xef, 0x5b, 0xbe, 0x74, 0xff,
+       0xe3, 0x2b, 0xe2, 0x4d, 0xa9, 0xe1, 0xf1, 0x4d, 0xdd, 0x1c, 0x2b, 0xd5,
+       0x51, 0x55, 0xfe, 0x58, 0x23, 0xba, 0xd7, 0xb6, 0x58, 0x68, 0xbf, 0xb2,
+       0x6e, 0xd7, 0x6e, 0xfa, 0x8e, 0x8d, 0xdd, 0xc7, 0xfc, 0x28, 0xff, 0x75,
+       0x1d, 0xbb, 0x95, 0xf9, 0x30, 0x6f, 0xed, 0xae, 0xdd, 0xca, 0x02, 0x1d,
+       0x1e, 0x73, 0xeb, 0x22, 0x54, 0x37, 0x7e, 0x45, 0xaa, 0xcc, 0x5f, 0x47,
+       0x2d, 0xa8, 0xcf, 0xe3, 0xf9, 0x1b, 0xf3, 0xff, 0x68, 0xf7, 0x8f, 0xda,
+       0xb8, 0xfc, 0x9f, 0xad, 0xb4, 0x87, 0x31, 0x9f, 0x7d, 0xd6, 0x1c, 0xaa,
+       0xc3, 0x7e, 0x67, 0xbd, 0x29, 0x7e, 0xdc, 0x3f, 0x95, 0x78, 0x7f, 0x6d,
+       0xf7, 0x8d, 0x74, 0x7e, 0x40, 0xea, 0x9e, 0xa4, 0x28, 0x5e, 0xdb, 0x4c,
+       0xdb, 0x3d, 0x56, 0xe8, 0xd7, 0x76, 0xa5, 0xc5, 0x8f, 0xfc, 0xb4, 0x21,
+       0x27, 0xb4, 0x0e, 0xe9, 0x92, 0xa9, 0x05, 0x3b, 0xf1, 0xfd, 0x0c, 0x67,
+       0xaa, 0x1f, 0xf3, 0xe1, 0xbe, 0x24, 0x56, 0x4e, 0x76, 0xef, 0x2b, 0xe2,
+       0x61, 0x4c, 0x1c, 0x5f, 0x8c, 0xb9, 0x8f, 0xcb, 0xcb, 0x2b, 0x42, 0xbf,
+       0xc0, 0x1f, 0xd5, 0x71, 0x3d, 0xed, 0xe5, 0x71, 0x2e, 0x6e, 0x07, 0xa0,
+       0xbe, 0x3a, 0x6a, 0xe6, 0xeb, 0xd8, 0xc3, 0x38, 0xbc, 0x66, 0x6f, 0xe0,
+       0x47, 0xc4, 0xb7, 0xc7, 0x32, 0x69, 0xde, 0x9c, 0xba, 0xa8, 0x82, 0x75,
+       0x1f, 0xf1, 0xf3, 0xc6, 0xf8, 0x2a, 0xb0, 0xcd, 0xeb, 0xfa, 0x3a, 0x70,
+       0x76, 0x58, 0x50, 0xcf, 0xd7, 0x0a, 0x7d, 0x53, 0xf9, 0xe3, 0x1d, 0xca,
+       0x07, 0x3a, 0xb8, 0x3b, 0xbc, 0x2a, 0xc1, 0x97, 0xb3, 0x6b, 0x9b, 0x82,
+       0xf9, 0x16, 0x78, 0x4e, 0xfa, 0x06, 0xfa, 0x33, 0xac, 0xb3, 0xca, 0xd9,
+       0xc5, 0xf3, 0x4c, 0xb5, 0xf0, 0x7c, 0x81, 0x4e, 0xbf, 0xc8, 0x75, 0x24,
+       0xd0, 0x33, 0xbf, 0xc0, 0xf5, 0xd8, 0x4f, 0x76, 0x1d, 0xe6, 0x7a, 0x26,
+       0xca, 0xf3, 0xcb, 0x02, 0xde, 0x78, 0x7a, 0x1e, 0xf2, 0xfa, 0x68, 0xfe,
+       0xc9, 0x60, 0x66, 0xe9, 0xbe, 0x25, 0x3c, 0x14, 0xe3, 0xd0, 0xa3, 0x45,
+       0xc9, 0x34, 0x9e, 0x94, 0xfb, 0x78, 0x39, 0x3d, 0xe4, 0xe5, 0xfe, 0x58,
+       0xce, 0xd6, 0x1d, 0x8a, 0xc9, 0x4e, 0x79, 0x78, 0xf2, 0xcb, 0x24, 0x7c,
+       0xb2, 0xdf, 0xd8, 0x9c, 0x09, 0xaf, 0x21, 0x3c, 0x63, 0xa6, 0x74, 0x11,
+       0x1e, 0xea, 0xb7, 0x6a, 0xb4, 0x9e, 0x49, 0x96, 0xe0, 0xe0, 0x25, 0x3a,
+       0x79, 0xf8, 0xad, 0x90, 0x9b, 0x57, 0x67, 0xff, 0x91, 0xce, 0xdb, 0xd9,
+       0xf0, 0x8b, 0xb7, 0x88, 0x1f, 0xeb, 0xdb, 0x15, 0x1e, 0x0f, 0xb4, 0xbf,
+       0x65, 0x99, 0x85, 0x76, 0x26, 0xfc, 0x13, 0x15, 0xf7, 0x4d, 0xa6, 0x71,
+       0xd3, 0xce, 0x36, 0x8a, 0xf3, 0xa8, 0xa6, 0x75, 0x72, 0x3d, 0x5c, 0xdf,
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+       0x56, 0xf5, 0x1d, 0x49, 0x0c, 0xf7, 0x53, 0x81, 0xff, 0xfe, 0x80, 0xf4,
+       0x8b, 0xe7, 0x53, 0x89, 0x1f, 0xa9, 0x67, 0x07, 0xa2, 0x27, 0xe8, 0x23,
+       0xfe, 0xfd, 0x43, 0xd8, 0x22, 0xf2, 0xd7, 0xa1, 0xc2, 0x99, 0xa9, 0x31,
+       0x3d, 0x6d, 0x16, 0x78, 0x61, 0x76, 0x7e, 0xff, 0xa2, 0x58, 0x57, 0x8c,
+       0x7f, 0x42, 0xe7, 0x70, 0xfe, 0x98, 0x9e, 0xb5, 0x91, 0x5c, 0x14, 0x7e,
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+       0xc5, 0xf1, 0xa9, 0x87, 0x6b, 0x46, 0xc2, 0x7d, 0x32, 0xae, 0x27, 0x31,
+       0x4f, 0xce, 0xf3, 0x2a, 0xdd, 0x05, 0x33, 0x75, 0xdf, 0x93, 0xf5, 0xe9,
+       0x7b, 0xf1, 0xfe, 0x7f, 0x22, 0xbd, 0xb9, 0xdd, 0x88, 0xf2, 0xfb, 0xac,
+       0x08, 0xed, 0xb7, 0x84, 0x3f, 0x9e, 0x7e, 0x57, 0xe4, 0x70, 0x3f, 0x36,
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+       0xca, 0xb1, 0xd0, 0xb8, 0x59, 0x39, 0x1a, 0xc1, 0xb3, 0xb1, 0x92, 0xef,
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+       0xbb, 0x9d, 0xd7, 0xa9, 0xa5, 0x7e, 0xd3, 0x12, 0xc5, 0xeb, 0x11, 0xd3,
+       0xdc, 0x3a, 0x7c, 0x7e, 0x24, 0x87, 0xc3, 0xd1, 0x66, 0x5a, 0x45, 0xdf,
+       0xc7, 0x81, 0x5c, 0x3a, 0x73, 0x46, 0x23, 0xff, 0xa4, 0x31, 0xae, 0x1f,
+       0xb9, 0x3e, 0xdc, 0xf0, 0x3c, 0xd7, 0x67, 0x75, 0x61, 0x7b, 0x04, 0xcf,
+       0xab, 0xa9, 0x0b, 0xdd, 0x3a, 0x9f, 0xea, 0x10, 0x9c, 0x36, 0x3f, 0xd6,
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+       0xf8, 0x4b, 0xca, 0x83, 0xc4, 0x6b, 0x0c, 0x9f, 0x11, 0x83, 0x3c, 0x49,
+       0x7a, 0x98, 0xfb, 0xfc, 0x89, 0x50, 0x21, 0xf7, 0x97, 0x78, 0x9c, 0x52,
+       0xca, 0x54, 0xda, 0x17, 0xaa, 0xb1, 0x06, 0x8e, 0xe2, 0x77, 0x8c, 0x35,
+       0x62, 0x3f, 0x15, 0xef, 0x63, 0x9d, 0xab, 0xdc, 0x4f, 0x9d, 0x2b, 0xe8,
+       0xf2, 0xb8, 0x3d, 0x38, 0x12, 0xd7, 0xd9, 0x6f, 0x3f, 0xf5, 0x2b, 0xfa,
+       0xd9, 0xb5, 0xcb, 0xdf, 0xa0, 0xb8, 0xe6, 0x1e, 0xcf, 0xeb, 0x74, 0x95,
+       0x72, 0x0b, 0xf1, 0xa0, 0x41, 0xbe, 0x27, 0x08, 0xba, 0x0f, 0xcb, 0xe1,
+       0xf6, 0x7d, 0x6a, 0x0e, 0xe7, 0x9b, 0xda, 0x51, 0x1d, 0x24, 0x97, 0xb5,
+       0x1f, 0x36, 0x91, 0x3c, 0xdb, 0xa7, 0x70, 0xbd, 0x66, 0x3f, 0x69, 0xd4,
+       0xc7, 0x8c, 0x3d, 0x24, 0xd6, 0xbb, 0x8e, 0xde, 0x9b, 0x94, 0xd2, 0x31,
+       0x19, 0xf7, 0x21, 0x27, 0x3d, 0xa1, 0x38, 0x30, 0x4e, 0x1e, 0x08, 0xce,
+       0x45, 0xf8, 0x1d, 0x18, 0xc6, 0x4b, 0x5b, 0x0f, 0xa5, 0xdd, 0x8d, 0xf8,
+       0xfd, 0x02, 0xbc, 0x75, 0xdd, 0x77, 0x42, 0xdf, 0xcc, 0x11, 0xe7, 0x43,
+       0xee, 0x04, 0x84, 0x13, 0xbf, 0x37, 0x59, 0xbe, 0xcc, 0x1f, 0xbf, 0xdc,
+       0x78, 0x2c, 0x7a, 0x5c, 0xa1, 0xf3, 0x42, 0x04, 0x2e, 0xcf, 0xee, 0xaa,
+       0xba, 0xe6, 0x23, 0xdc, 0x37, 0xd8, 0x99, 0xee, 0xc7, 0xef, 0xf3, 0xcf,
+       0xec, 0xba, 0xe5, 0xbb, 0x1f, 0x01, 0xdc, 0x67, 0x77, 0x8c, 0xf7, 0xa3,
+       0x9f, 0xe0, 0x6c, 0x0e, 0x12, 0xff, 0xf4, 0xba, 0x6c, 0xfe, 0xed, 0x3c,
+       0x1f, 0x3a, 0x05, 0xf3, 0x3d, 0x2b, 0x3b, 0x0e, 0xa5, 0xe1, 0x77, 0x45,
+       0x9f, 0x3e, 0x3b, 0xa2, 0x1c, 0xf5, 0xf6, 0x12, 0x01, 0xe7, 0x67, 0xcf,
+       0xab, 0xcb, 0x11, 0x2f, 0xab, 0x9e, 0xf9, 0xf9, 0x0d, 0xf8, 0xbc, 0x36,
+       0xa2, 0x64, 0xa1, 0xff, 0x7a, 0x76, 0xe7, 0x13, 0xff, 0x95, 0x03, 0xe3,
+       0xd4, 0xec, 0x68, 0xc4, 0x13, 0xc8, 0x58, 0xf3, 0xb3, 0xbf, 0xa4, 0xb8,
+       0xc0, 0x14, 0xd9, 0xc6, 0xef, 0xef, 0x4c, 0x27, 0x3f, 0xf7, 0xd3, 0x27,
+       0xd7, 0xdf, 0x80, 0xf8, 0x6e, 0xee, 0x68, 0xa6, 0xe7, 0x9f, 0x3d, 0xb9,
+       0x8d, 0xda, 0xaf, 0x3e, 0xf3, 0xf3, 0x57, 0xfe, 0x03, 0xf3, 0x1f, 0xc1,
+       0x34, 0xfa, 0x3e, 0xfa, 0xb3, 0xe7, 0x0f, 0x12, 0x5d, 0xea, 0x42, 0x1a,
+       0xd5, 0xc5, 0x0f, 0xc4, 0xd7, 0x1b, 0x77, 0x1f, 0xe4, 0xfa, 0x12, 0xed,
+       0x3c, 0xca, 0xc1, 0x1c, 0xae, 0xc7, 0x24, 0x5f, 0x4b, 0xfe, 0xfd, 0xf4,
+       0x99, 0xbb, 0xae, 0xd1, 0xdb, 0x0d, 0x79, 0xbf, 0x4d, 0xe4, 0x41, 0xda,
+       0x92, 0xb9, 0x1d, 0x39, 0x23, 0xe4, 0xb6, 0x76, 0x82, 0xbd, 0x0d, 0xaf,
+       0x67, 0x7e, 0x66, 0xa3, 0x73, 0x3b, 0x1b, 0x2c, 0xdd, 0x25, 0x18, 0x1f,
+       0xd7, 0x95, 0x72, 0xbe, 0x58, 0x91, 0xc3, 0xf5, 0x60, 0x5d, 0xc7, 0x12,
+       0x73, 0x83, 0x9d, 0xde, 0xa7, 0x71, 0xfe, 0x0d, 0xe4, 0x1d, 0xaf, 0x57,
+       0x03, 0x7f, 0x62, 0xfd, 0x19, 0xf4, 0xda, 0x71, 0x89, 0xea, 0xa8, 0x9e,
+       0xa3, 0xfe, 0xd0, 0x6f, 0x2c, 0xe6, 0x49, 0x66, 0x57, 0xbf, 0xcf, 0xbf,
+       0x2b, 0x2d, 0x6d, 0x32, 0xd7, 0x12, 0x9c, 0xcf, 0xf2, 0xe7, 0xb0, 0x6a,
+       0xfd, 0xf3, 0x8a, 0x65, 0x89, 0xf7, 0x35, 0xb6, 0xe4, 0xd8, 0x0d, 0xf9,
+       0xd1, 0x9c, 0xce, 0x19, 0x79, 0x3e, 0xd2, 0x03, 0x49, 0xfe, 0x21, 0x3a,
+       0xff, 0x37, 0xa7, 0x26, 0xd4, 0x8c, 0x75, 0x02, 0x37, 0x2d, 0x0b, 0xf9,
+       0xf1, 0x3b, 0xfa, 0x17, 0x3f, 0x79, 0x7b, 0x32, 0xe6, 0xd3, 0x9e, 0x19,
+       0xaa, 0x8c, 0x24, 0xfa, 0xab, 0x0a, 0xb7, 0x73, 0x61, 0x3b, 0xcd, 0x53,
+       0x8f, 0xfb, 0x0e, 0x10, 0x7f, 0x3c, 0x2b, 0xe4, 0xc4, 0xed, 0x60, 0xce,
+       0x6b, 0x61, 0x3d, 0x93, 0x34, 0xe6, 0xb4, 0xe3, 0x95, 0xb1, 0xe3, 0x66,
+       0xd2, 0x0b, 0x4f, 0xd1, 0xf8, 0xe0, 0xe7, 0x90, 0xff, 0xe6, 0xfb, 0xe5,
+       0xec, 0xa7, 0xd0, 0xef, 0xd9, 0x68, 0x0e, 0x79, 0x47, 0xe3, 0x38, 0x6d,
+       0xc2, 0x3e, 0xee, 0xe0, 0xf0, 0xc3, 0xfb, 0x0e, 0x7b, 0x39, 0x8d, 0xe7,
+       0xb8, 0x96, 0xfb, 0xeb, 0x4b, 0xf1, 0xbd, 0xf3, 0x2b, 0xa7, 0x3b, 0xd1,
+       0xbf, 0x87, 0x71, 0xbb, 0xcc, 0xba, 0x78, 0x0c, 0x38, 0xb2, 0x00, 0xed,
+       0x23, 0x8e, 0x37, 0x0a, 0xf1, 0x34, 0x25, 0x3c, 0x87, 0xec, 0x94, 0xcf,
+       0x42, 0xeb, 0x93, 0xe7, 0x81, 0xc2, 0xfa, 0x29, 0x7f, 0x2a, 0xe5, 0x33,
+       0x3e, 0x4f, 0x83, 0xfa, 0x09, 0xf3, 0xad, 0xaf, 0xe7, 0x54, 0x1e, 0xce,
+       0x71, 0xc5, 0xae, 0xee, 0x01, 0xf2, 0x1c, 0xd6, 0x5c, 0xfe, 0x7c, 0x4a,
+       0x6e, 0x80, 0xae, 0x5f, 0xf5, 0x7c, 0xd1, 0x57, 0x67, 0xf7, 0x70, 0x3b,
+       0xff, 0xd2, 0xfb, 0xc4, 0xb7, 0x0d, 0xc8, 0xb7, 0x38, 0x7f, 0xe8, 0x43,
+       0x83, 0x9d, 0x97, 0xf5, 0x11, 0x1b, 0xf7, 0xbf, 0x4f, 0x7c, 0x3b, 0x7f,
+       0x1f, 0xd7, 0xc7, 0x0d, 0xfb, 0x2a, 0x2d, 0x18, 0x6f, 0x9d, 0x59, 0x11,
+       0x60, 0x1f, 0x80, 0xa3, 0xdb, 0x20, 0xf8, 0x6f, 0xa3, 0xd2, 0xbd, 0x90,
+       0xbe, 0x4f, 0xdb, 0x6f, 0xa3, 0xef, 0x0e, 0x7b, 0x24, 0x7f, 0xb6, 0xbf,
+       0xff, 0x31, 0xea, 0x9f, 0xa2, 0x7d, 0x5e, 0xaa, 0xe7, 0xe9, 0xd9, 0xcf,
+       0xf9, 0xf4, 0x88, 0xc9, 0x44, 0x79, 0x80, 0x23, 0xdb, 0xaf, 0xda, 0xd6,
+       0xac, 0xf4, 0xb7, 0xab, 0xe0, 0x6f, 0x93, 0x9c, 0x34, 0x34, 0x31, 0xe1,
+       0x6f, 0x2f, 0x7b, 0x1b, 0xfd, 0xb3, 0xfa, 0x1a, 0x5e, 0x07, 0xdf, 0x10,
+       0xc7, 0x47, 0x85, 0x8f, 0x9f, 0x6a, 0x45, 0x7e, 0xc9, 0x00, 0xef, 0x18,
+       0xeb, 0x32, 0xc0, 0x9f, 0x99, 0x4c, 0xdf, 0x6d, 0xd6, 0xb1, 0xd1, 0x28,
+       0xa7, 0x39, 0x13, 0x03, 0xfb, 0x73, 0x69, 0xff, 0x9b, 0xc7, 0xe7, 0x39,
+       0x35, 0xa0, 0x4f, 0xa0, 0x7d, 0x93, 0x73, 0xb1, 0x1f, 0x4b, 0x07, 0x32,
+       0x26, 0x82, 0x5f, 0x8c, 0xfc, 0xe7, 0xbc, 0xde, 0x8f, 0xf9, 0xa6, 0x8d,
+       0xf9, 0x1d, 0xad, 0xe8, 0x3f, 0x87, 0x27, 0x31, 0x3a, 0x77, 0x75, 0xa3,
+       0xb9, 0x7d, 0x02, 0xc6, 0xc1, 0x1b, 0x27, 0xf9, 0x1c, 0x80, 0x49, 0xc0,
+       0xdb, 0x0e, 0xf2, 0xaf, 0xd9, 0x50, 0x8b, 0xb0, 0x67, 0xf3, 0xc9, 0x2f,
+       0x6f, 0xf0, 0xfc, 0xab, 0x9f, 0xf2, 0xc1, 0xf1, 0xf2, 0xbf, 0x7f, 0x25,
+       0xf9, 0x77, 0x0d, 0xbe, 0x64, 0x3f, 0x9e, 0x83, 0x3b, 0x6d, 0x9f, 0xb2,
+       0x94, 0xfb, 0x33, 0x76, 0x86, 0xf0, 0x37, 0x00, 0x7e, 0xb1, 0x3d, 0x2d,
+       0x72, 0x5d, 0x04, 0xe1, 0x39, 0x27, 0xf0, 0x27, 0xf1, 0xd8, 0x63, 0xee,
+       0xa2, 0xf3, 0x78, 0x7b, 0x5e, 0x48, 0xa2, 0xf3, 0x0d, 0xa7, 0x4d, 0xe4,
+       0xfc, 0x9a, 0x31, 0xb1, 0x83, 0xf4, 0xc7, 0x6b, 0xfb, 0x6f, 0x24, 0x7b,
+       0x2d, 0xf9, 0x32, 0x75, 0x6f, 0x12, 0xd9, 0xed, 0x4c, 0xcd, 0xa1, 0xf8,
+       0x29, 0x5f, 0x74, 0x4b, 0x12, 0xc2, 0x33, 0x4f, 0xc0, 0xd3, 0x2e, 0xea,
+       0x84, 0x33, 0x84, 0x1d, 0x29, 0x5e, 0xc7, 0xfd, 0xb8, 0xcc, 0x5c, 0x2e,
+       0x4f, 0x99, 0xb9, 0x26, 0x71, 0xb5, 0x18, 0xeb, 0xac, 0x1c, 0x61, 0xca,
+       0x3b, 0x9c, 0x13, 0xf4, 0x27, 0x36, 0xd1, 0x9d, 0xfb, 0x54, 0x3f, 0x3f,
+       0x4a, 0xf2, 0x54, 0xb7, 0x8b, 0x8f, 0xe7, 0x4c, 0x0a, 0x94, 0xdd, 0xab,
+       0xe3, 0x5f, 0xe9, 0x5f, 0xc9, 0x7a, 0x03, 0xac, 0x1b, 0x98, 0x91, 0x80,
+       0xbf, 0xc7, 0xe6, 0x72, 0x3b, 0x58, 0xf8, 0xf8, 0x52, 0xa2, 0xfb, 0xbc,
+       0x1a, 0x71, 0x3e, 0xc4, 0x3a, 0xee, 0x57, 0x30, 0xe0, 0x0b, 0xc4, 0x1b,
+       0xd0, 0x91, 0xf8, 0xe0, 0x26, 0xe7, 0x22, 0xa2, 0xdb, 0xbc, 0x75, 0xca,
+       0x37, 0x89, 0x8e, 0xe1, 0x0a, 0xca, 0x1b, 0x4a, 0xff, 0x2c, 0x7e, 0xfc,
+       0x71, 0x62, 0x7d, 0x3b, 0x6d, 0xc1, 0x51, 0x58, 0x67, 0xd8, 0xeb, 0x4a,
+       0xf5, 0xe3, 0x7e, 0xd7, 0xce, 0x8c, 0x80, 0x89, 0xf2, 0xee, 0x65, 0x19,
+       0x94, 0x07, 0x71, 0x65, 0x71, 0x7f, 0xd1, 0x25, 0xfc, 0xc5, 0x98, 0xdc,
+       0x07, 0x47, 0x99, 0x60, 0x9e, 0x4f, 0xdc, 0xa9, 0x9c, 0xde, 0x91, 0xdf,
+       0x68, 0x98, 0x17, 0x9e, 0x92, 0xeb, 0x4b, 0xe8, 0xe7, 0xf5, 0x8f, 0xf3,
+       0xf9, 0x78, 0xd3, 0xdb, 0xc3, 0xc3, 0x31, 0xee, 0x91, 0xf5, 0x61, 0x12,
+       0x1f, 0x91, 0x95, 0xc9, 0x73, 0xf4, 0xfa, 0x74, 0x82, 0xa0, 0x4b, 0x64,
+       0x18, 0x9b, 0x83, 0x7a, 0x03, 0xe2, 0x09, 0x3b, 0xe5, 0xaf, 0x1d, 0x30,
+       0x0f, 0xe6, 0x13, 0xb6, 0x5f, 0xf7, 0x24, 0xcf, 0x27, 0xf0, 0x73, 0xa1,
+       0xaf, 0xca, 0xe5, 0xdf, 0x35, 0x4f, 0xca, 0x0a, 0x8e, 0xa2, 0xfd, 0xbf,
+       0xe2, 0xe0, 0x32, 0x6e, 0x3f, 0xf9, 0x3a, 0xe3, 0xf1, 0xf1, 0xba, 0xb0,
+       0x9b, 0xaf, 0xce, 0xbe, 0xb3, 0x0c, 0xe3, 0xd8, 0x86, 0x5b, 0xed, 0x7e,
+       0x94, 0xbb, 0x0d, 0x2f, 0x29, 0x73, 0x89, 0xaf, 0xc3, 0x56, 0x3c, 0x3c,
+       0x08, 0xf8, 0x9e, 0xcb, 0x21, 0x38, 0x4c, 0x54, 0x0f, 0xc5, 0x42, 0x1a,
+       0xd1, 0xa3, 0xa1, 0x29, 0x18, 0x49, 0xcc, 0xf7, 0x33, 0x48, 0xce, 0x1a,
+       0xc0, 0xef, 0xc3, 0x38, 0x60, 0x1a, 0xf2, 0xb9, 0x93, 0xf8, 0x3e, 0xc2,
+       0xf9, 0x9e, 0xdb, 0x3f, 0x99, 0x6f, 0x40, 0x3d, 0xa9, 0xf7, 0xb7, 0xa5,
+       0x3e, 0x90, 0x7a, 0x06, 0xed, 0x1b, 0xf2, 0xb3, 0x94, 0x8b, 0x86, 0x1b,
+       0xba, 0x4b, 0x90, 0xbe, 0x5f, 0x55, 0xaf, 0xf4, 0x98, 0xb9, 0x9c, 0xf7,
+       0x00, 0x1e, 0x50, 0x8e, 0xa4, 0xdc, 0xa4, 0xbe, 0xc8, 0xe5, 0x65, 0xcd,
+       0x4a, 0x5f, 0x25, 0x3e, 0x5f, 0x03, 0x72, 0xaf, 0xa7, 0x77, 0x7c, 0x7c,
+       0x86, 0x70, 0x62, 0xbc, 0x22, 0xf5, 0xfb, 0xaa, 0x9c, 0xe0, 0xb7, 0x73,
+       0x11, 0x4e, 0x53, 0xb4, 0x95, 0xbe, 0x7d, 0x15, 0xfa, 0xb8, 0xe1, 0xc5,
+       0xd5, 0x25, 0x89, 0xbe, 0x5f, 0x92, 0xfa, 0xd8, 0x2a, 0xce, 0xd3, 0xb4,
+       0x46, 0x52, 0x22, 0xfa, 0x7d, 0x06, 0xdc, 0xb3, 0x4f, 0x2d, 0xa7, 0x6b,
+       0x18, 0xed, 0x51, 0xca, 0xf2, 0xc4, 0xf9, 0x98, 0xd5, 0xb9, 0xd2, 0xbe,
+       0xf6, 0xab, 0x77, 0x5a, 0x9d, 0xeb, 0xea, 0x5f, 0xef, 0xe4, 0x46, 0xdb,
+       0x85, 0xf2, 0xb3, 0x3d, 0x85, 0xbe, 0xa3, 0x93, 0xf9, 0xa9, 0xf8, 0x71,
+       0xbf, 0x2f, 0xf8, 0x4d, 0xd2, 0x45, 0xc6, 0x29, 0xb8, 0x5f, 0x80, 0xfd,
+       0x9f, 0x12, 0xf2, 0xb3, 0x59, 0xc8, 0xe9, 0x73, 0xe2, 0xaa, 0x8b, 0x7f,
+       0x88, 0xff, 0x7d, 0xa6, 0xd0, 0xfb, 0xb8, 0xdf, 0x3f, 0x90, 0x1d, 0x93,
+       0xef, 0xfd, 0xb3, 0xf2, 0x65, 0x72, 0x1e, 0x69, 0x4f, 0xe3, 0xe9, 0x2f,
+       0xf7, 0x3b, 0x70, 0x3d, 0x33, 0x4a, 0x07, 0xee, 0xd7, 0x7e, 0x50, 0xc4,
+       0x81, 0x71, 0xfc, 0xf8, 0x82, 0xf0, 0xa7, 0xee, 0xcd, 0x65, 0x74, 0x6d,
+       0x37, 0x47, 0x3f, 0x27, 0xb9, 0x5a, 0x92, 0xca, 0x68, 0x9f, 0x6d, 0x33,
+       0x0b, 0x64, 0xe1, 0x7e, 0xd9, 0x2b, 0x57, 0x70, 0x79, 0x08, 0xf4, 0x96,
+       0xe0, 0xf8, 0x57, 0xe6, 0x87, 0x32, 0xf2, 0x46, 0xc7, 0xf2, 0xc2, 0x78,
+       0x1f, 0xe3, 0x93, 0x5a, 0x8d, 0x85, 0x71, 0x9f, 0xac, 0x76, 0xa7, 0x39,
+       0xa2, 0xff, 0x8e, 0x67, 0x27, 0x7e, 0x48, 0x09, 0xfd, 0xcf, 0xa7, 0x5a,
+       0xc3, 0x2a, 0xf0, 0xf9, 0xb8, 0xfc, 0xd0, 0x61, 0xa4, 0x67, 0x78, 0x02,
+       0xff, 0x5e, 0x2f, 0xfc, 0x3d, 0x1b, 0xed, 0xff, 0x80, 0x23, 0x3d, 0x1a,
+       0xf5, 0x4b, 0x23, 0xeb, 0x4e, 0x43, 0x3c, 0x37, 0xa8, 0x5d, 0x25, 0x98,
+       0xc7, 0xdc, 0xe2, 0x0e, 0xbd, 0x8e, 0xfd, 0x4f, 0x99, 0xba, 0x0a, 0x78,
+       0xbd, 0x05, 0xdf, 0x9f, 0x3a, 0x29, 0xf2, 0xbe, 0x27, 0x45, 0xde, 0xb7,
+       0xd3, 0x12, 0xcd, 0xff, 0x8e, 0x33, 0x76, 0xce, 0xdd, 0x05, 0xc6, 0xeb,
+       0x75, 0x2e, 0x74, 0x99, 0x32, 0x31, 0x0e, 0x7c, 0x6f, 0xdf, 0x3b, 0x3f,
+       0x7b, 0x09, 0xde, 0xbe, 0xe3, 0xa5, 0x73, 0x77, 0x7c, 0x1f, 0xb1, 0xb5,
+       0x26, 0xe5, 0xce, 0x1f, 0xc1, 0xb5, 0xda, 0xaa, 0x06, 0xf5, 0xe7, 0xff,
+       0x9c, 0x4c, 0x4d, 0xac, 0x67, 0x4f, 0x09, 0x3e, 0xea, 0xab, 0xa7, 0x59,
+       0x99, 0x94, 0x30, 0xef, 0xbf, 0x27, 0x8f, 0xf3, 0x41, 0x63, 0xdc, 0xfe,
+       0xef, 0x9e, 0x3c, 0x1f, 0xbf, 0xdf, 0xf7, 0x5d, 0x16, 0xdf, 0xff, 0x7d,
+       0x6f, 0x80, 0x73, 0xb2, 0x26, 0xe7, 0x71, 0xfa, 0x74, 0x8a, 0x3a, 0x9f,
+       0xf8, 0xe7, 0xd3, 0xc4, 0x3c, 0x3b, 0xcd, 0xac, 0x64, 0x33, 0xc2, 0xb3,
+       0x2d, 0x95, 0xf6, 0xd7, 0x99, 0xc6, 0xcf, 0x37, 0xab, 0x79, 0xa4, 0xd0,
+       0x8f, 0xfb, 0x92, 0x9d, 0x45, 0xfc, 0xfc, 0xfc, 0xde, 0x47, 0x15, 0xb2,
+       0x03, 0x27, 0xcd, 0x5c, 0xff, 0xc0, 0xdf, 0xad, 0xd6, 0x8a, 0x98, 0x1d,
+       0x45, 0x37, 0x05, 0xfd, 0xc4, 0x1a, 0x47, 0x38, 0x6a, 0x02, 0xfd, 0x51,
+       0xb3, 0x2c, 0x35, 0x8a, 0xe7, 0x67, 0xc2, 0x7d, 0x6d, 0x1c, 0xca, 0x5a,
+       0xd8, 0x41, 0xf5, 0xa6, 0x73, 0x85, 0x7d, 0x9c, 0xd7, 0xf4, 0xda, 0xdf,
+       0x30, 0xef, 0x51, 0xa3, 0x31, 0xeb, 0x38, 0x78, 0xef, 0xb4, 0x7d, 0x7e,
+       0x1a, 0x9a, 0x87, 0x85, 0xdf, 0xba, 0x17, 0x8f, 0xc0, 0x61, 0xd9, 0xd5,
+       0xed, 0xa2, 0x2e, 0x51, 0x9c, 0xd7, 0x16, 0x98, 0xae, 0x5e, 0x4a, 0xf9,
+       0x32, 0xbf, 0xce, 0xf8, 0x5d, 0xcb, 0xde, 0xbc, 0xa0, 0x15, 0xf9, 0xac,
+       0x3a, 0x9d, 0xe3, 0xbb, 0xfa, 0x5e, 0x7e, 0x4e, 0xaf, 0xec, 0xff, 0x92,
+       0x90, 0xdb, 0x7e, 0xfc, 0x86, 0xbc, 0x0a, 0xf0, 0xfe, 0x51, 0xe1, 0xf6,
+       0x25, 0x7e, 0x1e, 0x77, 0xfe, 0x84, 0xe7, 0x51, 0xbf, 0x2d, 0xf7, 0x04,
+       0xb3, 0x68, 0xfc, 0x7b, 0xcf, 0x19, 0xf4, 0x5a, 0x8f, 0xd2, 0xfd, 0xf4,
+       0x8f, 0x90, 0x2f, 0x97, 0xa4, 0x8a, 0x73, 0xd4, 0x58, 0x81, 0xbe, 0x5e,
+       0xca, 0x9f, 0xc7, 0xed, 0x4b, 0x2d, 0xee, 0x37, 0x81, 0x6a, 0x3c, 0x5f,
+       0xd6, 0x55, 0xb2, 0xbc, 0x10, 0xf9, 0xbf, 0xb7, 0xe0, 0x77, 0x98, 0x77,
+       0x3b, 0x90, 0x44, 0x75, 0xb1, 0xb5, 0xb8, 0xef, 0xa4, 0xab, 0x67, 0x1b,
+       0x68, 0xdf, 0x69, 0xe0, 0xfd, 0x26, 0x9f, 0x05, 0xf9, 0xbc, 0xe1, 0xa2,
+       0x42, 0x7c, 0x32, 0xf7, 0xc0, 0x6b, 0x27, 0x50, 0xaf, 0x37, 0x68, 0xdd,
+       0xc4, 0x3f, 0x73, 0xad, 0x76, 0xa2, 0x4f, 0xc3, 0x45, 0x8d, 0x9e, 0xb3,
+       0x36, 0xf3, 0x59, 0xfd, 0x77, 0x7a, 0xed, 0x9e, 0xc0, 0x70, 0x5c, 0x5f,
+       0xf8, 0xc1, 0x71, 0x19, 0xb4, 0x6f, 0x95, 0x0d, 0xf7, 0x09, 0xcf, 0x43,
+       0xe9, 0x9c, 0x8f, 0xa5, 0xa2, 0x1e, 0xd9, 0x9d, 0x1f, 0x1a, 0x8d, 0xfd,
+       0x36, 0xa5, 0xa4, 0xdd, 0x85, 0xf1, 0xe1, 0x05, 0x2b, 0x3f, 0x97, 0xa9,
+       0xd1, 0xc2, 0xeb, 0x8e, 0x99, 0xf8, 0xfe, 0x59, 0xf2, 0x09, 0xcb, 0x4b,
+       0x35, 0xf2, 0xc1, 0x81, 0xd7, 0xff, 0x86, 0x70, 0xcd, 0xb7, 0x86, 0xe8,
+       0x1c, 0xcb, 0x05, 0x73, 0x9a, 0xe8, 0xdc, 0xdc, 0xea, 0xf4, 0xe8, 0x68,
+       0x47, 0xa9, 0x9e, 0xfe, 0xe3, 0xbe, 0xd6, 0xb9, 0xb9, 0x5e, 0xa1, 0x37,
+       0xde, 0xb3, 0xf0, 0xfa, 0x9c, 0xfe, 0xfc, 0xcf, 0xe9, 0xb0, 0x27, 0x8f,
+       0xeb, 0xaf, 0xf7, 0x72, 0xb8, 0x1c, 0xbd, 0x57, 0xc0, 0x6a, 0xf6, 0xe0,
+       0xf5, 0x4a, 0xb8, 0xc2, 0x7b, 0xef, 0x15, 0x89, 0x76, 0x39, 0x6f, 0xc7,
+       0x8f, 0xd3, 0x28, 0xe4, 0xe8, 0xbd, 0xe1, 0xdc, 0x7e, 0x85, 0x97, 0xa6,
+       0x24, 0x3c, 0x97, 0xe4, 0x6e, 0x21, 0x8f, 0x7b, 0xf3, 0x02, 0xb7, 0x23,
+       0xbe, 0xe4, 0xfd, 0xa7, 0x05, 0x1c, 0xee, 0xfc, 0x40, 0x75, 0x9e, 0x8b,
+       0xf4, 0x63, 0x48, 0xf0, 0x6d, 0x34, 0x03, 0xc6, 0xab, 0xfe, 0x25, 0xff,
+       0x1d, 0x03, 0xd6, 0xd2, 0x4b, 0x75, 0x25, 0x7d, 0xeb, 0x2a, 0x11, 0xf0,
+       0xba, 0x13, 0xc3, 0xd5, 0x12, 0x1b, 0x77, 0x11, 0x8e, 0x07, 0xfd, 0x02,
+       0xe4, 0xc7, 0xbf, 0x62, 0xa3, 0xef, 0xef, 0xd8, 0x74, 0xd0, 0xd7, 0xa8,
+       0x9f, 0x97, 0xe6, 0x33, 0xd4, 0xcf, 0x30, 0x6f, 0x63, 0x1e, 0x1f, 0x37,
+       0x9a, 0x41, 0xfd, 0x92, 0x68, 0x1d, 0xac, 0x0d, 0xf4, 0x36, 0xf0, 0xef,
+       0xf9, 0xd1, 0x3e, 0xa2, 0xcb, 0x9a, 0x4a, 0xe0, 0xd3, 0x51, 0xe2, 0x5c,
+       0x7e, 0x5f, 0x8c, 0xaf, 0x24, 0x3f, 0xc5, 0xf3, 0xd1, 0x7d, 0x79, 0xca,
+       0x40, 0xfb, 0xe2, 0xf7, 0xe1, 0x7c, 0xf1, 0xfb, 0xe2, 0x8c, 0x0d, 0x26,
+       0x7a, 0x13, 0xbf, 0x7d, 0x8d, 0xef, 0xd8, 0x46, 0x64, 0x71, 0xbc, 0x80,
+       0xdc, 0xb7, 0xe6, 0x91, 0xfd, 0x8d, 0x5e, 0xad, 0x97, 0x3b, 0x89, 0x67,
+       0xa9, 0x2f, 0xdf, 0x4b, 0x36, 0xf2, 0x45, 0xaa, 0x80, 0xf3, 0x07, 0xa2,
+       0x5f, 0x1f, 0x9e, 0xc5, 0x39, 0x5a, 0xce, 0x62, 0x6e, 0x07, 0x65, 0xbc,
+       0xf0, 0xb8, 0xe8, 0x9f, 0x21, 0xe8, 0x2f, 0xaf, 0xd2, 0xae, 0xc5, 0xef,
+       0x0f, 0x64, 0x88, 0x71, 0x33, 0xf2, 0xd2, 0x24, 0x5d, 0x1e, 0x13, 0xf4,
+       0xce, 0x48, 0x48, 0xef, 0xad, 0x9c, 0xde, 0xd0, 0xef, 0x09, 0xec, 0x57,
+       0x9d, 0xd4, 0x7b, 0x67, 0x16, 0xd8, 0xb3, 0xdb, 0xc0, 0x4f, 0xc2, 0x73,
+       0x2f, 0xe1, 0x3d, 0x2f, 0xde, 0xef, 0x97, 0xb7, 0x98, 0xc8, 0xed, 0x70,
+       0xe3, 0xd2, 0x54, 0x86, 0x7e, 0xc2, 0x4f, 0xf2, 0x44, 0xde, 0x6f, 0x54,
+       0x2f, 0xdf, 0xbf, 0x1b, 0xda, 0x4b, 0xfa, 0x68, 0x2e, 0x03, 0xbd, 0xa3,
+       0x5c, 0x9e, 0x7e, 0x98, 0x23, 0xf0, 0x82, 0x3e, 0x7c, 0x43, 0xd4, 0x0f,
+       0x29, 0x58, 0xcf, 0x93, 0x49, 0x6a, 0xc0, 0x87, 0xe3, 0x01, 0xbe, 0x3b,
+       0xf3, 0x5c, 0x31, 0x7c, 0xc7, 0xcf, 0x77, 0x12, 0x1f, 0x81, 0x5f, 0xf8,
+       0x4a, 0x9e, 0xf8, 0xbe, 0xaf, 0x8c, 0x95, 0x21, 0xbd, 0xee, 0x7c, 0xeb,
+       0xcf, 0xa9, 0x77, 0xf8, 0xf0, 0x1c, 0x74, 0xfe, 0x5d, 0xf1, 0x47, 0xf6,
+       0xd0, 0xab, 0x38, 0xce, 0xd9, 0xef, 0xbe, 0x4e, 0x71, 0xc0, 0x49, 0x4b,
+       0xb4, 0xa4, 0xdd, 0x9e, 0xe0, 0xb9, 0x25, 0xfa, 0xf8, 0x26, 0x25, 0xf6,
+       0xfc, 0xae, 0x9f, 0xa8, 0x61, 0xfc, 0xdd, 0x8b, 0xce, 0xae, 0xb3, 0x8f,
+       0xce, 0x06, 0xbe, 0x9c, 0xdb, 0xa5, 0xfa, 0x71, 0xca, 0xb9, 0xf7, 0x7d,
+       0xfe, 0xe6, 0x18, 0xf4, 0xaf, 0xbb, 0xcc, 0xb4, 0x0f, 0x05, 0xfe, 0xc5,
+       0x3a, 0x3c, 0x17, 0x94, 0x35, 0x71, 0x7f, 0xf4, 0xa4, 0xc9, 0x48, 0xff,
+       0x33, 0xdf, 0x36, 0xd6, 0x75, 0x74, 0x0b, 0x79, 0x95, 0xdf, 0x3b, 0x4b,
+       0x7d, 0x25, 0xfd, 0x86, 0xc5, 0xcc, 0xcf, 0xf5, 0x54, 0x32, 0x3f, 0x87,
+       0xfd, 0xd4, 0x92, 0x45, 0xf4, 0xbd, 0xf3, 0x7c, 0x16, 0x3c, 0x8a, 0xe7,
+       0xb0, 0x7f, 0xba, 0x74, 0x2a, 0xf9, 0xd3, 0x8b, 0x58, 0x88, 0x7e, 0x8f,
+       0x60, 0x5e, 0x9b, 0xf1, 0x3c, 0xde, 0xf8, 0x73, 0x7c, 0xe3, 0xcf, 0xef,
+       0xc5, 0x04, 0x3f, 0xe2, 0x2f, 0xfe, 0x1c, 0xdf, 0xbe, 0x7c, 0x7b, 0x55,
+       0x62, 0x3f, 0x23, 0x35, 0x9f, 0xf3, 0xe1, 0x19, 0x8b, 0xa8, 0x2f, 0x18,
+       0xc0, 0xcf, 0xb8, 0x28, 0xf8, 0x57, 0xd6, 0x17, 0x34, 0xca, 0xfa, 0x82,
+       0x97, 0xbf, 0xbc, 0xbe, 0xa0, 0x31, 0xae, 0xbe, 0x20, 0xe6, 0x8f, 0xc8,
+       0xfa, 0x82, 0x2f, 0x28, 0x4f, 0x68, 0xce, 0xf7, 0xd1, 0xf8, 0x38, 0x9e,
+       0xbe, 0xce, 0xe0, 0xcc, 0x84, 0xc4, 0x70, 0x2b, 0xf9, 0xd2, 0xef, 0x49,
+       0x31, 0x8c, 0x2f, 0xc7, 0x89, 0xcd, 0x93, 0x46, 0xcf, 0x1b, 0xf1, 0x3c,
+       0x9f, 0x84, 0xdf, 0xab, 0xdb, 0xe9, 0xfe, 0x99, 0x85, 0x89, 0xe7, 0x49,
+       0xcf, 0xe7, 0xeb, 0x6e, 0x8c, 0xab, 0x67, 0x88, 0xbd, 0xcf, 0xeb, 0x18,
+       0x64, 0x9c, 0x2f, 0xf9, 0xa2, 0xf1, 0xa2, 0x97, 0xec, 0xb1, 0x6c, 0xf7,
+       0xfd, 0x0e, 0x43, 0xdf, 0x7b, 0x79, 0xf4, 0x3c, 0xfe, 0xfb, 0x7c, 0x99,
+       0xa7, 0x97, 0x72, 0xf0, 0x81, 0xc2, 0xac, 0x5e, 0xca, 0x9b, 0xad, 0x17,
+       0x7a, 0xd1, 0x3f, 0x1c, 0xfd, 0xdf, 0x0f, 0xd0, 0xaf, 0x42, 0x39, 0xbc,
+       0xd1, 0xf7, 0x4a, 0x37, 0x80, 0x38, 0xef, 0xfb, 0xd7, 0x94, 0x68, 0x45,
+       0x31, 0x39, 0x89, 0x5f, 0x07, 0xf0, 0xd3, 0x67, 0xfa, 0xef, 0xe0, 0x87,
+       0xe4, 0x8b, 0x73, 0x79, 0xfd, 0xcc, 0x4f, 0xdf, 0x49, 0x0a, 0x3e, 0xbf,
+       0xf3, 0xbb, 0x93, 0xd2, 0x71, 0x9f, 0xf5, 0xdf, 0xef, 0xab, 0x32, 0x7c,
+       0xff, 0xd6, 0xf7, 0x7d, 0xbc, 0x45, 0xfa, 0x73, 0x76, 0x83, 0x5d, 0x66,
+       0x71, 0x76, 0x7b, 0xde, 0xbe, 0xd7, 0xc9, 0x5f, 0x9b, 0x6f, 0x0d, 0xd2,
+       0x77, 0x78, 0x1f, 0xbd, 0xfc, 0x5d, 0xb2, 0xd7, 0x0b, 0x59, 0xd0, 0x8d,
+       0xfc, 0x7d, 0xfe, 0xe5, 0x2b, 0x0a, 0x42, 0xff, 0x03, 0x7b, 0x2d, 0xe1,
+       0xb9, 0x25, 0x7c, 0xb7, 0x99, 0xfb, 0xe9, 0x4e, 0xf2, 0x33, 0x66, 0x0a,
+       0x78, 0x6e, 0x39, 0xc0, 0xfd, 0x45, 0x93, 0x35, 0x60, 0xa6, 0x79, 0x02,
+       0xcc, 0xe7, 0x70, 0x53, 0x28, 0xce, 0xe1, 0x05, 0xa5, 0x89, 0xe7, 0xf0,
+       0x5d, 0xdf, 0x07, 0x7f, 0x29, 0x9d, 0xdf, 0x31, 0x4e, 0xc0, 0xaf, 0xe0,
+       0xfb, 0x80, 0xdf, 0xeb, 0xc5, 0x95, 0xcd, 0x0d, 0x79, 0x10, 0x6e, 0x79,
+       0xae, 0x00, 0x70, 0x93, 0x07, 0xaf, 0xcd, 0xd7, 0xf8, 0x7d, 0x78, 0x1d,
+       0xaf, 0x04, 0x35, 0xa6, 0xfb, 0xde, 0x74, 0x32, 0x6b, 0xca, 0xc3, 0xfe,
+       0x26, 0x6b, 0xb7, 0x2a, 0xce, 0x3b, 0xa3, 0xf3, 0xe3, 0x93, 0x62, 0xf8,
+       0xa2, 0x76, 0xaa, 0x68, 0xb7, 0xdc, 0x7a, 0xe1, 0xce, 0x05, 0x78, 0xdf,
+       0xce, 0xcf, 0x27, 0xb6, 0x08, 0x38, 0x16, 0xe6, 0x8b, 0xef, 0xa8, 0xad,
+       0xcc, 0x8a, 0xeb, 0x4e, 0xb2, 0x47, 0x3f, 0xa5, 0x7d, 0x40, 0x71, 0x0d,
+       0x4f, 0xe0, 0xfe, 0x77, 0xb8, 0x88, 0xd7, 0xed, 0x26, 0xe3, 0x79, 0x0a,
+       0x30, 0xaf, 0xdd, 0x7e, 0x2e, 0x8c, 0x8b, 0x75, 0x30, 0x07, 0x9d, 0x13,
+       0x60, 0x73, 0x5c, 0x88, 0x62, 0x1c, 0xa2, 0xfb, 0x1d, 0x89, 0x7b, 0xf2,
+       0x5d, 0xba, 0xdf, 0x91, 0x60, 0x51, 0x9e, 0x9f, 0x1a, 0xe8, 0x79, 0xdc,
+       0xef, 0x4c, 0x64, 0x0a, 0xf8, 0x9a, 0x85, 0x7e, 0xf3, 0xe2, 0x79, 0x87,
+       0xc5, 0x74, 0xae, 0x03, 0xe9, 0xb7, 0x87, 0x53, 0x17, 0xd2, 0x39, 0xe4,
+       0x2e, 0xfb, 0x32, 0xda, 0x9f, 0xde, 0x92, 0x36, 0x85, 0xf6, 0x2f, 0xdd,
+       0x88, 0x78, 0xac, 0x53, 0x9f, 0xa2, 0x3b, 0x97, 0x01, 0x9e, 0xbb, 0x82,
+       0xc6, 0xf3, 0x18, 0xb2, 0xe7, 0x18, 0xdb, 0xde, 0x90, 0xb1, 0x6d, 0x65,
+       0x27, 0xa9, 0x3e, 0x4a, 0x89, 0x06, 0x3d, 0x97, 0xb2, 0x62, 0xe7, 0x4e,
+       0x9a, 0x85, 0xbe, 0xb8, 0x35, 0x99, 0xc3, 0x75, 0x6b, 0x32, 0x8f, 0xd7,
+       0x56, 0xe7, 0x1b, 0xbf, 0x13, 0x0d, 0xca, 0xdf, 0x7f, 0xc9, 0xe4, 0xe7,
+       0x36, 0xf4, 0xb8, 0xad, 0x56, 0xac, 0xb7, 0xc0, 0xf8, 0x3f, 0x9f, 0xc7,
+       0xff, 0x7f, 0x04, 0x4a, 0x43, 0x5c, 0xc8, 0x7f, 0x1f, 0xa6, 0x6c, 0x7c,
+       0x60, 0xc8, 0xa3, 0xa3, 0xf0, 0x77, 0x4f, 0x54, 0xff, 0x2a, 0xa0, 0x53,
+       0x6b, 0xaa, 0x6f, 0xa5, 0x86, 0xfe, 0xdb, 0xed, 0xe2, 0x77, 0xc2, 0xb4,
+       0x0e, 0xaa, 0x63, 0xd8, 0x76, 0x67, 0x06, 0xd5, 0x89, 0xb6, 0xda, 0x1c,
+       0x95, 0x98, 0xf7, 0x0c, 0xe7, 0xf3, 0x7c, 0x4f, 0xa3, 0xa8, 0xf7, 0x07,
+       0x8a, 0xd4, 0xee, 0x82, 0xf7, 0xb6, 0xcd, 0xcc, 0xa5, 0x7e, 0xce, 0xaa,
+       0x5e, 0xca, 0x97, 0xf6, 0xae, 0x66, 0xe4, 0x1f, 0xf5, 0xe3, 0xd3, 0x2f,
+       0x80, 0xff, 0x01, 0xdf, 0x4f, 0x62, 0x1b, 0xcf, 0x93, 0x98, 0xef, 0xef,
+       0xc2, 0xef, 0x88, 0xbd, 0x01, 0x95, 0xea, 0x74, 0xe5, 0xf3, 0x1d, 0xf8,
+       0x1c, 0xe0, 0x54, 0x04, 0x5f, 0xe0, 0xfd, 0xf1, 0x15, 0xb1, 0xdf, 0x71,
+       0x2a, 0x3e, 0x50, 0x76, 0x08, 0xcf, 0xc3, 0x64, 0x21, 0xc5, 0xcf, 0xd3,
+       0x8f, 0x3e, 0xe2, 0xf7, 0x59, 0xc2, 0x2f, 0x6f, 0x3c, 0x50, 0x79, 0xf3,
+       0x68, 0x80, 0xab, 0xb8, 0x6b, 0x24, 0xb1, 0xf1, 0xe0, 0x03, 0x62, 0xbf,
+       0xc5, 0x99, 0x24, 0xf6, 0x8d, 0xf9, 0xf9, 0xbd, 0xf1, 0xfd, 0x07, 0x63,
+       0x7f, 0x68, 0xa7, 0x1c, 0xf3, 0xfd, 0x6b, 0x1d, 0x3e, 0x32, 0x41, 0x9c,
+       0x8d, 0xef, 0x4d, 0x48, 0xa1, 0x75, 0x1f, 0x17, 0xf9, 0x26, 0x26, 0xf4,
+       0xc3, 0x98, 0x38, 0xf9, 0xbb, 0x2e, 0x26, 0x0f, 0xf4, 0xbc, 0x4c, 0xb4,
+       0x1b, 0x45, 0x7d, 0x1d, 0x9e, 0x61, 0x11, 0xa8, 0xe0, 0xe9, 0x0c, 0xea,
+       0xe7, 0xe4, 0xf2, 0xe1, 0x67, 0xf2, 0x8f, 0xcb, 0xed, 0xb5, 0x2c, 0xf6,
+       0x87, 0xe3, 0x54, 0xc5, 0xc6, 0x25, 0x3d, 0x35, 0x31, 0xf6, 0x38, 0x26,
+       0x87, 0xb0, 0xc4, 0x72, 0xab, 0xbf, 0xb9, 0x0e, 0xfa, 0x1d, 0x99, 0xc1,
+       0xf7, 0xd7, 0xc7, 0x68, 0xd1, 0x83, 0x28, 0xef, 0xd7, 0x89, 0x6b, 0x99,
+       0xb8, 0xb2, 0xb9, 0xed, 0x84, 0xdf, 0x35, 0x2b, 0x03, 0x2a, 0xa3, 0x12,
+       0x88, 0x90, 0xba, 0x1e, 0xda, 0x63, 0xad, 0x5d, 0x59, 0xc8, 0xdf, 0xe3,
+       0xac, 0xdd, 0x2b, 0x5d, 0x30, 0xce, 0x35, 0x73, 0xee, 0xf6, 0x60, 0xbb,
+       0xa4, 0xa0, 0x98, 0xf8, 0x0d, 0xfc, 0x2f, 0x3a, 0x77, 0x28, 0xc3, 0x6e,
+       0x8a, 0xf0, 0xef, 0x28, 0xcb, 0xfc, 0x28, 0x47, 0xb3, 0xe7, 0xf0, 0x7c,
+       0xec, 0xac, 0x39, 0x56, 0xaa, 0x3b, 0x9e, 0xa5, 0xf1, 0xf3, 0xa1, 0x98,
+       0x16, 0x2a, 0xbc, 0x0d, 0x9e, 0xdf, 0x56, 0xcd, 0xf3, 0xc0, 0xd8, 0xae,
+       0xd6, 0xe5, 0x59, 0xe4, 0xbe, 0xc7, 0x71, 0x88, 0x53, 0x76, 0x27, 0x88,
+       0x37, 0x4b, 0x0a, 0xb8, 0x5d, 0x94, 0xef, 0x37, 0x8a, 0xfa, 0x1f, 0xf9,
+       0xbc, 0x08, 0x0f, 0x8a, 0xc6, 0x3c, 0x59, 0xc1, 0xe4, 0x8f, 0xf2, 0xc9,
+       0x9e, 0xf0, 0xfd, 0xdd, 0x33, 0x52, 0xcf, 0x0c, 0x65, 0x43, 0xe3, 0x7e,
+       0x6f, 0xe6, 0x7c, 0x3e, 0xee, 0x5f, 0x56, 0xbe, 0x31, 0x90, 0x9e, 0x30,
+       0x3e, 0x17, 0x7a, 0x62, 0x56, 0xe0, 0x11, 0x33, 0xf9, 0xe9, 0x42, 0x5f,
+       0x48, 0xbd, 0x1c, 0x14, 0x75, 0x4d, 0x5d, 0xe2, 0x5c, 0x97, 0x77, 0x27,
+       0x70, 0xbc, 0xbf, 0x5d, 0xb9, 0x98, 0xf4, 0xc5, 0xad, 0xac, 0x89, 0xf4,
+       0xf9, 0x6d, 0x2c, 0x6c, 0x46, 0x7c, 0xf7, 0xe9, 0xff, 0x29, 0x3a, 0xbf,
+       0x06, 0xe6, 0x99, 0x15, 0x34, 0xfa, 0x39, 0xb3, 0xe7, 0xc4, 0xfb, 0x3d,
+       0x9c, 0x5f, 0xe5, 0xbc, 0xb7, 0x87, 0x8c, 0xcf, 0x67, 0x4a, 0xff, 0x75,
+       0x8a, 0xd1, 0x7f, 0xad, 0xfe, 0xce, 0x17, 0x19, 0x64, 0x17, 0xb3, 0x9f,
+       0xae, 0xbf, 0x34, 0x28, 0x56, 0xbf, 0xd4, 0x18, 0x57, 0xbf, 0xd4, 0x20,
+       0xea, 0x97, 0x1a, 0xf7, 0x2d, 0x39, 0xe2, 0xd2, 0xd5, 0x2f, 0x35, 0x1e,
+       0xe0, 0xf5, 0x4b, 0x0d, 0xfb, 0x2e, 0x57, 0xbf, 0xd4, 0x4b, 0xfb, 0x48,
+       0xc7, 0xcd, 0x91, 0x83, 0xb8, 0xbf, 0x72, 0x7c, 0x31, 0x88, 0x04, 0xc0,
+       0x79, 0x48, 0xd4, 0xbb, 0x1c, 0xc6, 0x7a, 0x97, 0xf2, 0x18, 0x5f, 0xa6,
+       0xce, 0xe4, 0x79, 0x56, 0x60, 0x5f, 0xda, 0x2f, 0xc9, 0x73, 0xa4, 0xf8,
+       0xd1, 0x5f, 0x6f, 0x33, 0x95, 0x53, 0x5e, 0xb6, 0x2d, 0x2d, 0xd5, 0xaf,
+       0xcf, 0x83, 0xae, 0x59, 0x19, 0x9a, 0xa4, 0xcf, 0xc7, 0xca, 0x7a, 0xa5,
+       0xe3, 0x03, 0xc4, 0xb7, 0xc3, 0x0b, 0xb8, 0xff, 0xba, 0x51, 0xe1, 0x79,
+       0xf1, 0xf0, 0xed, 0x56, 0x8a, 0xe7, 0x5c, 0xc5, 0x41, 0xc3, 0x3e, 0x84,
+       0x4b, 0x65, 0x27, 0x30, 0xbf, 0xf8, 0x11, 0xfa, 0x59, 0xa3, 0xa9, 0x3f,
+       0xe5, 0x3d, 0x70, 0x1f, 0x6f, 0x24, 0x5c, 0x23, 0x0a, 0xaf, 0xb3, 0xef,
+       0x7b, 0x1f, 0xbf, 0x3b, 0xc2, 0x7c, 0x64, 0x9c, 0x3e, 0x72, 0x65, 0xf9,
+       0x69, 0x1f, 0xc0, 0x95, 0x7e, 0x35, 0xe5, 0xf3, 0xe7, 0x1c, 0x28, 0xdb,
+       0x41, 0xfa, 0xc6, 0x6e, 0xf3, 0xe3, 0xef, 0x22, 0xca, 0xf1, 0xe7, 0x84,
+       0xb6, 0x69, 0x58, 0x47, 0xd4, 0x78, 0x60, 0x9b, 0x36, 0xdf, 0x1e, 0xe3,
+       0xbb, 0xca, 0x02, 0xc1, 0xaf, 0x29, 0x2c, 0x05, 0xf9, 0xb5, 0x2f, 0xbf,
+       0xb7, 0x27, 0x89, 0xf2, 0x7b, 0x1f, 0xd9, 0x83, 0x93, 0x0a, 0xe0, 0xfd,
+       0x3a, 0x4b, 0x74, 0x38, 0x33, 0xf2, 0x33, 0xdd, 0x1f, 0xc8, 0xae, 0x2d,
+       0x12, 0xfc, 0x62, 0x9e, 0x10, 0xbc, 0x7d, 0x01, 0xc0, 0x73, 0xfe, 0x4d,
+       0x0b, 0xcf, 0x73, 0xdd, 0xc7, 0x48, 0x5e, 0x9f, 0xdf, 0x9f, 0x41, 0xf9,
+       0x49, 0x6d, 0x26, 0x23, 0xfb, 0xd2, 0x52, 0xc9, 0xf8, 0xef, 0xc0, 0x6c,
+       0xe3, 0xdf, 0x0b, 0x9c, 0xce, 0xe0, 0xe7, 0x18, 0xb5, 0xcc, 0x60, 0x64,
+       0x07, 0x7b, 0x32, 0x27, 0x13, 0xfd, 0x16, 0xb3, 0xc8, 0x51, 0x3c, 0xa7,
+       0xa8, 0x66, 0xab, 0xd9, 0x70, 0x1e, 0xd1, 0x3d, 0x3b, 0x8c, 0xed, 0x3a,
+       0xd6, 0x41, 0xf6, 0xa6, 0x6e, 0x57, 0x3f, 0x7e, 0x26, 0xbd, 0x25, 0xf5,
+       0x63, 0x3d, 0xf3, 0xa9, 0x66, 0xdc, 0x07, 0xe8, 0x34, 0xbe, 0xcf, 0x06,
+       0x1b, 0xf5, 0x63, 0x99, 0xb0, 0x07, 0x23, 0x67, 0x4d, 0x6c, 0xc6, 0x7a,
+       0x8d, 0x91, 0xa6, 0xa0, 0x4a, 0xf6, 0xf7, 0x3e, 0x7f, 0xee, 0x4c, 0x8a,
+       0x9f, 0xab, 0xb9, 0x1d, 0x65, 0x4f, 0xd3, 0xf9, 0x57, 0xe7, 0x53, 0x3f,
+       0x51, 0xb9, 0x9c, 0x73, 0x7d, 0x3c, 0x3a, 0xa6, 0x35, 0x0d, 0x76, 0x69,
+       0xb4, 0xf0, 0xaf, 0x6e, 0xd0, 0xf8, 0xef, 0x2a, 0x48, 0x7f, 0x69, 0xb4,
+       0xf8, 0x9d, 0x85, 0xc3, 0xa6, 0x03, 0x2a, 0xfd, 0x76, 0x8f, 0x80, 0x67,
+       0x94, 0x78, 0x4f, 0xfa, 0x69, 0x52, 0x5f, 0xf7, 0xd1, 0x73, 0x2c, 0xe8,
+       0x52, 0xe0, 0xfb, 0x07, 0x25, 0x5d, 0x8b, 0x58, 0x11, 0xd2, 0x15, 0xc6,
+       0x27, 0x79, 0x50, 0x30, 0xc0, 0xc9, 0xa4, 0xf1, 0xe9, 0xf7, 0x1a, 0xae,
+       0x13, 0xf3, 0x01, 0xdd, 0xf9, 0xf9, 0x77, 0x26, 0x6b, 0x04, 0xf9, 0xa8,
+       0x55, 0x69, 0x22, 0x3d, 0x6d, 0x65, 0x42, 0x5f, 0x2b, 0xa1, 0x66, 0x7c,
+       0xf9, 0x17, 0xe1, 0x30, 0xe9, 0xed, 0x6b, 0x58, 0xd3, 0x2d, 0xf8, 0x7b,
+       0x9f, 0xe3, 0xac, 0x5d, 0x29, 0xe4, 0x97, 0xda, 0x43, 0x6b, 0x0b, 0x5c,
+       0x31, 0x3e, 0x69, 0x66, 0xd1, 0x82, 0xdd, 0x8a, 0x81, 0x5f, 0xe8, 0xf9,
+       0xd9, 0x8c, 0x37, 0x12, 0xf2, 0x8b, 0xb4, 0x2b, 0xd1, 0x77, 0xb9, 0xbf,
+       0x31, 0x8d, 0x81, 0x1f, 0x08, 0xf3, 0x06, 0x7e, 0xcf, 0xfd, 0xa0, 0xc3,
+       0x0a, 0x8f, 0xf3, 0xc0, 0x1f, 0x3c, 0x8c, 0x71, 0xde, 0x1b, 0xa6, 0xa9,
+       0xc4, 0x0f, 0x53, 0x61, 0x19, 0xd8, 0x6f, 0x92, 0xc3, 0x48, 0xe7, 0x1b,
+       0x3d, 0xc6, 0xf6, 0x54, 0x5f, 0x3f, 0x3e, 0x50, 0xf5, 0xbf, 0x5f, 0x01,
+       0x12, 0xa7, 0x21, 0x3c, 0xd3, 0x86, 0x1a, 0xfb, 0x05, 0xa4, 0x7e, 0x63,
+       0x46, 0xfd, 0x56, 0xc8, 0xbe, 0xe0, 0x75, 0xe5, 0xab, 0x8f, 0x7e, 0x0b,
+       0xe3, 0xff, 0x94, 0xe5, 0x6c, 0x28, 0xfa, 0x31, 0xe0, 0x39, 0xfa, 0x13,
+       0xfd, 0x1e, 0xe9, 0x73, 0x05, 0x03, 0xee, 0x93, 0x3c, 0x57, 0x90, 0x60,
+       0x9f, 0xe4, 0xbc, 0xc8, 0xf7, 0x5e, 0xcb, 0xba, 0x17, 0xee, 0x52, 0xfa,
+       0xf3, 0x4d, 0xcf, 0x91, 0xe5, 0xaa, 0x47, 0xc7, 0x5f, 0x92, 0x9f, 0x5f,
+       0x14, 0x75, 0x15, 0xca, 0x2f, 0xc5, 0x7e, 0xec, 0x28, 0x9e, 0xf7, 0x8b,
+       0xd9, 0x79, 0xce, 0x37, 0x15, 0xa2, 0x75, 0x2d, 0xf2, 0x5d, 0x26, 0x7e,
+       0x7f, 0x22, 0xf8, 0x45, 0xfc, 0xbe, 0xc8, 0xf5, 0xfb, 0x6c, 0x51, 0xfc,
+       0xfd, 0x9c, 0x32, 0x31, 0xce, 0xb5, 0xc8, 0x3f, 0xe5, 0x31, 0xbb, 0x1e,
+       0x35, 0xd9, 0x7d, 0x96, 0x22, 0xe4, 0x13, 0x7f, 0x9b, 0xaa, 0xf6, 0xf7,
+       0xe7, 0xdd, 0x99, 0x3e, 0xe2, 0x97, 0x91, 0x26, 0x69, 0xe7, 0xfd, 0x59,
+       0x8c, 0xec, 0x7c, 0x47, 0xb3, 0x86, 0xf0, 0xef, 0x1f, 0x93, 0x1b, 0xb2,
+       0x1b, 0xf8, 0xe3, 0x1d, 0xae, 0x4f, 0x80, 0x3f, 0x28, 0x2f, 0xd5, 0xcf,
+       0x3e, 0x1a, 0x9f, 0xc7, 0xf1, 0x8f, 0xa4, 0xe3, 0x31, 0xe1, 0x47, 0xdf,
+       0xc8, 0x7c, 0x14, 0x47, 0x4c, 0x11, 0x7e, 0x74, 0xb4, 0x90, 0xf3, 0x4f,
+       0x95, 0xfd, 0x56, 0x0d, 0xdf, 0x7f, 0xad, 0x88, 0xe7, 0x09, 0x26, 0xe2,
+       0x06, 0x22, 0x7d, 0xef, 0x69, 0xb4, 0x8b, 0x55, 0x56, 0x23, 0x1f, 0xc4,
+       0xf3, 0x17, 0xcc, 0x68, 0xd2, 0xcf, 0x1b, 0xcf, 0x6f, 0x03, 0xf1, 0xcd,
+       0x20, 0xe4, 0x1b, 0x69, 0x17, 0xb3, 0x2e, 0xcf, 0x37, 0x9f, 0x0b, 0x3f,
+       0x23, 0x01, 0xdf, 0x7c, 0x5e, 0x30, 0x7a, 0x60, 0xbe, 0x89, 0xe7, 0x17,
+       0xa9, 0x57, 0x76, 0xdb, 0x1c, 0x55, 0x78, 0xa6, 0x70, 0x63, 0x8d, 0x42,
+       0xfa, 0x78, 0xe4, 0x9b, 0x83, 0x9b, 0xb1, 0x7d, 0x45, 0x7d, 0x21, 0xd5,
+       0xbd, 0xec, 0xce, 0xf0, 0x1f, 0xa2, 0xe7, 0x4d, 0xfc, 0xf9, 0xa8, 0xae,
+       0x80, 0x8a, 0x75, 0x31, 0xc5, 0xcb, 0xc4, 0xf3, 0xc2, 0x60, 0x15, 0xb6,
+       0x1b, 0x97, 0xf3, 0x7d, 0x89, 0xd1, 0xc7, 0x79, 0xdd, 0xcc, 0xe0, 0xfb,
+       0xf8, 0xf3, 0xb2, 0x55, 0x4d, 0x87, 0xf0, 0xbb, 0xb8, 0xc6, 0x30, 0x7f,
+       0xff, 0xc5, 0x4f, 0x5b, 0xe9, 0x7b, 0xa1, 0x48, 0xab, 0x78, 0xbf, 0xb2,
+       0xbd, 0x0a, 0xdb, 0x8d, 0x6d, 0xfc, 0xfd, 0xd3, 0xb8, 0xbf, 0x34, 0x02,
+       0xeb, 0xdd, 0x22, 0xcd, 0x78, 0x7f, 0xd8, 0xba, 0x42, 0x3f, 0x0f, 0x4b,
+       0xb9, 0x5f, 0x3b, 0x5e, 0xf0, 0xe9, 0x6e, 0x65, 0xcf, 0x21, 0x7a, 0xaf,
+       0x9d, 0xbf, 0xb7, 0xe8, 0xa8, 0x35, 0x99, 0x7e, 0x67, 0x50, 0xf8, 0xad,
+       0x37, 0x88, 0x75, 0x8e, 0xdf, 0xca, 0xd7, 0xe9, 0xfc, 0xe0, 0x26, 0xfa,
+       0xdd, 0xd1, 0x05, 0xbd, 0x61, 0xf2, 0x9f, 0x3e, 0x36, 0xd5, 0x55, 0x90,
+       0xde, 0x19, 0x20, 0xfe, 0xac, 0x54, 0xda, 0xf3, 0xf0, 0x7a, 0x23, 0xea,
+       0x13, 0x15, 0xe9, 0x07, 0x7c, 0x5d, 0xc4, 0xf7, 0x1f, 0xb7, 0xc3, 0x14,
+       0x65, 0x83, 0x78, 0xfe, 0x42, 0xee, 0xdb, 0x61, 0x1d, 0x81, 0xbe, 0x6e,
+       0xa0, 0x6c, 0x10, 0xb7, 0xfb, 0xb2, 0x9f, 0x3b, 0x93, 0x7f, 0xd7, 0xc5,
+       0x1e, 0x4b, 0xa5, 0xbc, 0xaf, 0xdc, 0x57, 0x8c, 0x6e, 0x62, 0x0a, 0xca,
+       0x19, 0xae, 0x51, 0xf8, 0x01, 0x09, 0xf7, 0x19, 0x6f, 0x2c, 0x6e, 0xa2,
+       0xfd, 0xc5, 0x1b, 0x07, 0xc9, 0xfd, 0xc5, 0x6e, 0x0d, 0xcf, 0x75, 0x2f,
+       0xbb, 0xf4, 0xe7, 0xc9, 0x89, 0xf2, 0x2b, 0x63, 0xc5, 0xbc, 0x9f, 0x88,
+       0xba, 0x08, 0x79, 0xbf, 0x26, 0x52, 0x48, 0xbf, 0x23, 0xb6, 0x1b, 0x99,
+       0x84, 0xbe, 0xc7, 0x7e, 0xf2, 0x37, 0xd4, 0x16, 0xe7, 0x94, 0x33, 0xf1,
+       0x1d, 0xd8, 0xee, 0x42, 0xde, 0x9e, 0x3c, 0xe8, 0x89, 0x1f, 0xb6, 0xe5,
+       0x01, 0x7e, 0x4d, 0x4d, 0x1a, 0x9e, 0xeb, 0xc6, 0x0a, 0x14, 0xfa, 0x0e,
+       0xee, 0x5f, 0xba, 0x58, 0x34, 0x3d, 0xad, 0x3f, 0xfc, 0x37, 0x6a, 0x2c,
+       0x6a, 0xe1, 0xdf, 0xb1, 0x11, 0xfc, 0x0b, 0x9b, 0x2d, 0xdb, 0xf9, 0xf7,
+       0x88, 0x5c, 0x2f, 0xcd, 0x92, 0x6a, 0x67, 0xdc, 0x10, 0x92, 0xd3, 0x5b,
+       0x05, 0x9d, 0x6e, 0x19, 0x24, 0xf2, 0x92, 0x23, 0xd9, 0x48, 0xd4, 0x37,
+       0xb3, 0x04, 0xdd, 0x6e, 0xb3, 0x82, 0xdf, 0x4a, 0x7a, 0xad, 0xdd, 0x1c,
+       0x27, 0xff, 0xb3, 0x07, 0xa1, 0xfd, 0xd8, 0x32, 0xa0, 0xff, 0x6c, 0x7c,
+       0x1e, 0xa7, 0x1f, 0x6a, 0xc4, 0xbc, 0x0b, 0x85, 0xdf, 0xbc, 0x18, 0x7f,
+       0xaf, 0x54, 0xc5, 0xf3, 0xe6, 0xb9, 0xff, 0xfc, 0xc9, 0x16, 0xee, 0x37,
+       0xdf, 0xc3, 0x3a, 0x28, 0x8f, 0x78, 0xfe, 0x31, 0xee, 0x2f, 0xd6, 0xc3,
+       0xf2, 0x90, 0x5f, 0xfa, 0xfd, 0xae, 0xd7, 0x4e, 0x63, 0xbb, 0xbe, 0x23,
+       0xfe, 0x77, 0x64, 0xf9, 0xef, 0x10, 0xf6, 0xfb, 0x9d, 0xd6, 0x52, 0x9e,
+       0x9f, 0x3d, 0xbf, 0xa5, 0xbe, 0x02, 0xf3, 0x73, 0x35, 0x9b, 0xdf, 0xa4,
+       0x3c, 0x70, 0x8d, 0xd4, 0x17, 0x11, 0xa3, 0xbe, 0x00, 0x07, 0x83, 0xeb,
+       0x8b, 0x4d, 0x57, 0x52, 0x5e, 0xc7, 0x64, 0xe5, 0xbf, 0xa3, 0x39, 0x12,
+       0xf4, 0x05, 0xd6, 0x97, 0x8c, 0xc4, 0xba, 0x51, 0x18, 0x7f, 0xb8, 0x38,
+       0x87, 0x67, 0x35, 0xbe, 0xc2, 0xcf, 0xdf, 0xf9, 0xee, 0x20, 0xb2, 0x37,
+       0x53, 0xa8, 0xae, 0x94, 0xc6, 0x53, 0x69, 0x3f, 0xf7, 0xcd, 0x80, 0x2f,
+       0x46, 0x1f, 0x69, 0x37, 0xe2, 0xf5, 0x45, 0x99, 0xcc, 0xd7, 0x0c, 0xce,
+       0xa4, 0x7c, 0x96, 0xd4, 0x1f, 0x65, 0x8c, 0xdb, 0x8b, 0x78, 0xff, 0xe8,
+       0x11, 0x49, 0x4f, 0x11, 0xf7, 0x48, 0x3f, 0xa3, 0x0c, 0xfd, 0x0c, 0xe0,
+       0x8f, 0x2e, 0x93, 0x3d, 0x62, 0x32, 0xe9, 0xfd, 0x8a, 0x08, 0xc9, 0x21,
+       0xc4, 0x8d, 0xd3, 0x6c, 0x45, 0xc8, 0x3a, 0xdc, 0x9f, 0x1a, 0x79, 0xfb,
+       0x28, 0xab, 0xa0, 0x3f, 0x8b, 0xa3, 0xef, 0x26, 0xa2, 0xef, 0xc0, 0xf1,
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+       0x46, 0xf1, 0x7d, 0xeb, 0x79, 0xc1, 0x2f, 0xe7, 0x6d, 0xfc, 0x2a, 0xe1,
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+       0xa8, 0xb6, 0xc5, 0xcf, 0xe5, 0x19, 0x10, 0xa8, 0x56, 0x2c, 0x11, 0x83,
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+       0x9f, 0x64, 0xb5, 0xbf, 0x19, 0x0e, 0xed, 0x1a, 0xc3, 0x23, 0x73, 0x18,
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+       0x97, 0xdf, 0x2d, 0x6e, 0xda, 0x4c, 0xdf, 0x2d, 0xf6, 0x6a, 0x9f, 0x2f,
+       0x7d, 0x5a, 0x5b, 0xf7, 0x94, 0xb2, 0xf4, 0x5a, 0x2b, 0x63, 0xcb, 0x1d,
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+       0xd4, 0xdf, 0x0e, 0x27, 0xf8, 0x84, 0x31, 0xaf, 0xa3, 0xeb, 0x7e, 0x9d,
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+       0x38, 0x97, 0xe6, 0x63, 0x8e, 0xd7, 0xe2, 0x41, 0xb8, 0x43, 0x8b, 0x07,
+       0x11, 0xe9, 0x5a, 0x3c, 0xb0, 0x39, 0xb5, 0xfb, 0xde, 0xb3, 0x58, 0xbb,
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+       0x78, 0x21, 0xe1, 0x5a, 0x0c, 0x3f, 0xdf, 0x25, 0x5c, 0x9f, 0xd0, 0xc1,
+       0xb3, 0x60, 0x9f, 0xab, 0xde, 0x4a, 0x70, 0x62, 0x93, 0x2d, 0x83, 0x11,
+       0x7e, 0x7c, 0xbe, 0x66, 0x56, 0xae, 0x22, 0x9f, 0x63, 0xb1, 0xc0, 0x67,
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+       0x73, 0x0e, 0xc5, 0x78, 0xc2, 0x12, 0xe8, 0x27, 0xcf, 0xd8, 0xb2, 0x17,
+       0xd7, 0xb3, 0x46, 0xf1, 0x30, 0xfc, 0x2e, 0x9c, 0x79, 0xe3, 0x91, 0x5f,
+       0xd4, 0x17, 0xb7, 0x24, 0xb4, 0xc0, 0xbe, 0xe4, 0x5b, 0x6a, 0x71, 0xe7,
+       0xd8, 0x17, 0xd6, 0xf2, 0xe7, 0x91, 0xee, 0x2b, 0x4d, 0x2d, 0x39, 0xf8,
+       0x5e, 0xf6, 0xf7, 0x85, 0xd5, 0x4d, 0xcf, 0x5b, 0x95, 0x77, 0x16, 0x30,
+       0x58, 0x2f, 0x33, 0xb6, 0xe4, 0x10, 0x3f, 0xb4, 0x30, 0x1a, 0x5f, 0xc2,
+       0x71, 0x70, 0x0f, 0x8e, 0xc7, 0x4b, 0x59, 0x39, 0xf1, 0xe1, 0x17, 0x05,
+       0x3e, 0x7f, 0xfe, 0xd1, 0x22, 0x82, 0xe3, 0x02, 0x56, 0xbb, 0xdf, 0x05,
+       0xe3, 0x9d, 0xf9, 0x98, 0xc3, 0x77, 0x31, 0xf3, 0x50, 0xbb, 0xf9, 0x1b,
+       0xb4, 0x70, 0xe8, 0x02, 0x3f, 0x1d, 0xdc, 0x00, 0x6d, 0x1c, 0x38, 0x6e,
+       0x8d, 0x58, 0xf7, 0x12, 0xc6, 0xbc, 0x86, 0xe4, 0xae, 0xf0, 0x54, 0x9a,
+       0x95, 0x16, 0x5b, 0x0e, 0x82, 0xa1, 0x59, 0xf2, 0x6d, 0xf7, 0xa5, 0x02,
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+       0x68, 0xa0, 0x04, 0xf3, 0x27, 0x1c, 0xcf, 0xde, 0x2b, 0x30, 0x9e, 0x84,
+       0xa7, 0xe4, 0x5b, 0x72, 0x1c, 0x33, 0xab, 0x55, 0xe3, 0x91, 0x0e, 0x74,
+       0x7c, 0x8c, 0xa5, 0x6b, 0xf7, 0x09, 0x36, 0x8e, 0x61, 0x7d, 0xb0, 0xa8,
+       0xbd, 0x02, 0x3c, 0xd4, 0x12, 0x2d, 0x06, 0xeb, 0x85, 0xfd, 0xe0, 0xe4,
+       0x19, 0xbb, 0x51, 0x8c, 0xc3, 0xe6, 0xb8, 0xe3, 0x11, 0x4e, 0x16, 0xb6,
+       0x81, 0xf6, 0x6f, 0xbd, 0xe2, 0x5c, 0xa7, 0xc2, 0x38, 0xea, 0x0d, 0x89,
+       0xf5, 0x0c, 0xe0, 0x59, 0x60, 0x77, 0xa9, 0xb8, 0x5f, 0x45, 0xcc, 0x37,
+       0x0d, 0x9f, 0x17, 0x5b, 0x1a, 0xea, 0x8d, 0xd0, 0xd5, 0x0d, 0xec, 0xa2,
+       0xfd, 0x04, 0xc8, 0x13, 0xd6, 0x7b, 0x7b, 0xd5, 0xa5, 0x98, 0xc0, 0x3a,
+       0x14, 0xb9, 0x2e, 0x8f, 0xc2, 0x8c, 0x50, 0x1f, 0x21, 0xea, 0x93, 0x3c,
+       0x8a, 0xff, 0xb1, 0x44, 0x5c, 0xcf, 0x5b, 0xdf, 0xe2, 0xb8, 0x23, 0x44,
+       0x39, 0x09, 0x4b, 0xd8, 0x3f, 0x58, 0xe6, 0xdf, 0xff, 0x0a, 0x1f, 0x0f,
+       0x57, 0x1c, 0x03, 0x70, 0xbc, 0x89, 0xaf, 0xa4, 0xc5, 0x21, 0xde, 0xac,
+       0x51, 0x6a, 0x99, 0x6e, 0x7e, 0x47, 0x5f, 0x85, 0x7e, 0x54, 0x43, 0x47,
+       0x0c, 0xb6, 0x1b, 0xc3, 0xdc, 0x46, 0x2e, 0x77, 0xbd, 0x38, 0x49, 0xf6,
+       0x96, 0xe2, 0xa7, 0x79, 0xff, 0x88, 0xb9, 0xee, 0xc7, 0x52, 0xca, 0xb7,
+       0x6a, 0xd6, 0x30, 0x76, 0x1a, 0xd4, 0xab, 0x1b, 0x41, 0x6e, 0x45, 0x62,
+       0x19, 0xde, 0xa2, 0x42, 0xc9, 0x9a, 0x74, 0xf0, 0x64, 0xc6, 0xe3, 0x58,
+       0x37, 0xc0, 0x4a, 0x10, 0xbf, 0x97, 0x62, 0x5d, 0xee, 0x7b, 0x62, 0xe0,
+       0x3d, 0xd5, 0xd5, 0xae, 0xf5, 0x55, 0xb0, 0x86, 0x3e, 0xd1, 0x57, 0x96,
+       0xef, 0x1b, 0x13, 0xed, 0x34, 0x5f, 0x90, 0x7f, 0xa9, 0xfc, 0x3d, 0xe7,
+       0x6f, 0x8b, 0x04, 0xbc, 0x16, 0x49, 0xb9, 0xe5, 0xd5, 0xce, 0xef, 0x18,
+       0xfe, 0xd2, 0x87, 0xb1, 0x3f, 0x9a, 0x00, 0x26, 0xf9, 0x48, 0x47, 0x16,
+       0x8f, 0xa1, 0x27, 0xa8, 0x05, 0x89, 0x40, 0x97, 0xd8, 0x2e, 0x87, 0xe5,
+       0x60, 0xff, 0x40, 0x57, 0x8e, 0x44, 0xe8, 0xbf, 0x57, 0x34, 0xd0, 0xa1,
+       0x12, 0x4c, 0x77, 0xbc, 0xbd, 0x7c, 0xdf, 0x85, 0xee, 0x74, 0xeb, 0x67,
+       0xb5, 0xb0, 0xb9, 0x43, 0x00, 0xde, 0xb6, 0x42, 0x93, 0x1b, 0x58, 0xee,
+       0xdc, 0xe0, 0xf5, 0x5e, 0x05, 0x3c, 0xa4, 0x1e, 0x31, 0x0f, 0xdb, 0x42,
+       0xf9, 0x2f, 0x87, 0x83, 0xd6, 0x5d, 0xd5, 0xe3, 0xd8, 0x07, 0x2e, 0x7c,
+       0x5d, 0xe8, 0x4b, 0x40, 0xf9, 0x2f, 0xf7, 0xa9, 0xc6, 0xc4, 0xdc, 0x0d,
+       0xa8, 0xb7, 0x34, 0xc4, 0xd1, 0xb8, 0xf2, 0xf9, 0xe8, 0x44, 0x83, 0xd0,
+       0x27, 0x00, 0x1f, 0xaf, 0x02, 0x4e, 0xdd, 0xef, 0x43, 0x0a, 0xe9, 0x43,
+       0x72, 0x1f, 0xae, 0x56, 0x1f, 0xca, 0x45, 0x1c, 0x2f, 0x0a, 0xc0, 0xef,
+       0xe6, 0xae, 0xf0, 0x9e, 0x90, 0x18, 0x17, 0x04, 0x4f, 0x06, 0xf0, 0xcc,
+       0xd6, 0xc0, 0x5b, 0xfb, 0x5e, 0xc0, 0x5b, 0xc2, 0xe3, 0x6c, 0x91, 0x6f,
+       0x3b, 0xee, 0x93, 0x6a, 0x3b, 0xdc, 0x0b, 0xe1, 0xbc, 0x32, 0xbe, 0x7c,
+       0x12, 0xee, 0xcf, 0x80, 0xa3, 0xfe, 0x13, 0x8a, 0x21, 0x30, 0xaf, 0x31,
+       0x6a, 0xeb, 0xf6, 0xc7, 0x50, 0x8e, 0x35, 0xa9, 0x4e, 0xa4, 0xe5, 0xea,
+       0x11, 0x9c, 0xcf, 0x55, 0xbf, 0xac, 0x12, 0xe9, 0xb7, 0x35, 0x9b, 0xbd,
+       0x0a, 0xf4, 0xb3, 0xa8, 0xe9, 0x4d, 0xd2, 0xcf, 0x5a, 0xeb, 0x80, 0x91,
+       0x86, 0x75, 0x0f, 0xa7, 0xce, 0xf5, 0xea, 0xe0, 0xdd, 0x15, 0x1e, 0x7c,
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+       0xe5, 0x5e, 0xe8, 0xf7, 0x6f, 0x2b, 0x96, 0x47, 0xcf, 0x85, 0xf2, 0xcb,
+       0x3a, 0x18, 0x7a, 0x20, 0x3c, 0x57, 0x0c, 0xe5, 0x84, 0x6f, 0x6c, 0xd7,
+       0x27, 0x3f, 0x85, 0xfe, 0xd2, 0x6c, 0xd3, 0x9d, 0xeb, 0xa1, 0x36, 0xc3,
+       0x0c, 0xf3, 0x81, 0x71, 0x12, 0x7f, 0x1c, 0xd1, 0x92, 0x0c, 0x7c, 0xe2,
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+       0x76, 0x44, 0xa9, 0x4e, 0xd4, 0x83, 0x63, 0x55, 0x36, 0x1a, 0xf1, 0x4b,
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+       0xb7, 0x06, 0x9e, 0x8f, 0xaa, 0xef, 0x28, 0x58, 0x06, 0x65, 0x45, 0x22,
+       0xdf, 0x77, 0xb9, 0xce, 0x51, 0x65, 0x1d, 0x05, 0xa8, 0xf7, 0x48, 0x38,
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+       0xac, 0x9b, 0xbd, 0xa7, 0xb2, 0x6d, 0x50, 0x7c, 0x6d, 0x77, 0xf5, 0x8c,
+       0x22, 0x78, 0xd8, 0x79, 0x3f, 0x42, 0xdf, 0x6a, 0x63, 0x6c, 0x1c, 0xc2,
+       0x69, 0xc5, 0xf8, 0xd2, 0xde, 0xd1, 0x50, 0xc6, 0xd5, 0x73, 0xf8, 0xe8,
+       0xf1, 0xa4, 0x31, 0x91, 0xeb, 0xfd, 0x95, 0x17, 0x80, 0xf0, 0x0a, 0x02,
+       0xcf, 0x2b, 0x8d, 0x2d, 0x26, 0xbb, 0x15, 0x9f, 0x9b, 0x34, 0xcf, 0x8f,
+       0x03, 0xdc, 0x3c, 0xe6, 0x40, 0x7d, 0xce, 0xa9, 0x94, 0xb1, 0x8c, 0xf8,
+       0x8c, 0x73, 0x0d, 0xb6, 0x9f, 0xbb, 0x2e, 0x82, 0x79, 0x82, 0xf4, 0xab,
+       0x46, 0x31, 0x8f, 0xee, 0xe0, 0x52, 0x1d, 0x65, 0x64, 0x46, 0x80, 0x47,
+       0xb5, 0xc2, 0xca, 0x2f, 0xd7, 0xee, 0xd5, 0xff, 0xa8, 0x04, 0x5f, 0xfd,
+       0xfc, 0xff, 0x2a, 0xf8, 0x4c, 0x5c, 0x59, 0xe8, 0xf5, 0x1d, 0x12, 0xeb,
+       0x2b, 0x5b, 0x7b, 0xeb, 0x6f, 0x51, 0xff, 0xac, 0xf6, 0x85, 0x31, 0x33,
+       0x3c, 0x5a, 0xf1, 0x72, 0x49, 0x6f, 0x16, 0xa2, 0xbf, 0x4e, 0x38, 0x5f,
+       0x18, 0xc6, 0xbc, 0x31, 0x41, 0x75, 0xa3, 0x9f, 0xe0, 0x51, 0x7d, 0x61,
+       0x24, 0x3d, 0x2f, 0x5b, 0xdb, 0x6a, 0x42, 0xbc, 0xc7, 0x7e, 0x1c, 0xf0,
+       0x7c, 0x45, 0xb8, 0xab, 0xb7, 0xf3, 0x32, 0x70, 0xce, 0xc5, 0x79, 0xe0,
+       0x7a, 0x2f, 0x44, 0x31, 0x4f, 0x4c, 0xf0, 0x73, 0x8e, 0x57, 0x81, 0xfe,
+       0x63, 0xe9, 0xfd, 0xef, 0x11, 0x80, 0x80, 0xb7, 0x9e, 0x26, 0xd5, 0xbb,
+       0x0d, 0x3e, 0xfd, 0xfd, 0x01, 0xc3, 0xb8, 0x2d, 0xa1, 0xe6, 0x2b, 0xd6,
+       0x3f, 0x28, 0xce, 0x48, 0xf4, 0x92, 0xd9, 0xc2, 0x5c, 0x9b, 0x43, 0x8c,
+       0x2f, 0xdb, 0xf5, 0x8a, 0x06, 0x7e, 0x6d, 0xe5, 0x70, 0xae, 0xc8, 0xee,
+       0x3a, 0xbf, 0xc6, 0x52, 0xff, 0x4c, 0x9c, 0xff, 0x8d, 0xa3, 0x99, 0x2b,
+       0xd4, 0x78, 0xe7, 0x44, 0x3b, 0x39, 0xef, 0xc6, 0x68, 0xff, 0x02, 0x81,
+       0xf7, 0xa9, 0x15, 0xb6, 0xa0, 0xba, 0x5d, 0xbb, 0x8f, 0x3d, 0xc5, 0xf8,
+       0x8d, 0x37, 0xfb, 0x13, 0xb0, 0xff, 0xb6, 0xf1, 0x6c, 0x6a, 0x43, 0x88,
+       0xfe, 0xe5, 0x7e, 0xcf, 0x88, 0x77, 0x67, 0x22, 0xdf, 0xa9, 0xbc, 0x03,
+       0x1a, 0x03, 0x7e, 0x0c, 0x36, 0xd6, 0x2a, 0xf6, 0x20, 0x7a, 0xeb, 0x6e,
+       0xbf, 0x03, 0x70, 0x06, 0xbb, 0xab, 0xe0, 0x72, 0x70, 0x36, 0xd1, 0x7b,
+       0xd9, 0xdf, 0xe9, 0x43, 0x82, 0x1e, 0x99, 0xcb, 0xaa, 0x00, 0x1d, 0xcd,
+       0x16, 0xf2, 0x6a, 0xf6, 0xd6, 0xa5, 0xb7, 0x02, 0xcf, 0xec, 0xb4, 0x5f,
+       0x4e, 0x6f, 0x02, 0xfb, 0x05, 0x86, 0x38, 0xcd, 0x6a, 0xdf, 0xb4, 0x61,
+       0x7d, 0x83, 0x42, 0xf6, 0xc9, 0x1c, 0x37, 0xc8, 0x00, 0xe0, 0x37, 0x0b,
+       0xb6, 0x15, 0xac, 0x41, 0xb1, 0x35, 0x3b, 0x9e, 0xb1, 0x91, 0xd1, 0xfc,
+       0xf9, 0xbd, 0x58, 0xae, 0x0e, 0x0b, 0xc8, 0x59, 0xfa, 0xdf, 0xc5, 0x82,
+       0xe5, 0xa2, 0x1c, 0x7f, 0xde, 0x83, 0x5a, 0xbd, 0x75, 0x11, 0x7b, 0xf0,
+       0x2b, 0xd4, 0x7b, 0x4e, 0x1f, 0xe2, 0x7c, 0x01, 0xd4, 0x53, 0xb2, 0xbf,
+       0x17, 0x3c, 0xa2, 0xed, 0x6f, 0xd1, 0xd6, 0x5b, 0x4e, 0xe2, 0x3c, 0x17,
+       0xe9, 0xf4, 0x9f, 0x34, 0x54, 0xf0, 0x40, 0xff, 0x48, 0x4b, 0x12, 0xf6,
+       0xc4, 0x60, 0x36, 0x18, 0xf9, 0xff, 0xb2, 0x6d, 0xe7, 0x4d, 0x91, 0x8e,
+       0xee, 0xf1, 0xff, 0x4b, 0xa0, 0xf3, 0x94, 0x81, 0xc8, 0x27, 0xed, 0x54,
+       0x0e, 0x4d, 0x72, 0xe5, 0x24, 0xa1, 0x7f, 0xe1, 0x3d, 0x3e, 0xcf, 0xf1,
+       0x49, 0xee, 0xfc, 0x24, 0xf4, 0xa3, 0xbc, 0xc7, 0xe7, 0x75, 0xae, 0xf2,
+       0x1c, 0x97, 0x0f, 0x8f, 0xc7, 0x92, 0x5c, 0x32, 0x23, 0x13, 0x87, 0x5f,
+       0xcd, 0xd3, 0x2c, 0xde, 0x7a, 0x98, 0xc7, 0x5a, 0x60, 0x23, 0xe1, 0x00,
+       0x1f, 0xb3, 0x99, 0xeb, 0x41, 0x52, 0xff, 0x53, 0xd5, 0xe5, 0x6a, 0x24,
+       0xbc, 0x1f, 0xf2, 0xc5, 0x8a, 0x68, 0x37, 0xf2, 0xe1, 0x67, 0x6f, 0x1a,
+       0x87, 0xfd, 0xc5, 0x3d, 0x1b, 0xe1, 0xc2, 0xf5, 0xac, 0x2f, 0x71, 0xe5,
+       0xa1, 0xbf, 0x60, 0x7d, 0x85, 0xd5, 0x59, 0x0f, 0x5d, 0x5a, 0xe0, 0x7b,
+       0x94, 0x1b, 0xde, 0xdf, 0x0f, 0x79, 0xa3, 0x2f, 0x6a, 0x07, 0x0d, 0x1b,
+       0x4b, 0xfb, 0x21, 0xba, 0x35, 0xef, 0x6d, 0x41, 0x7f, 0xca, 0x3a, 0xc3,
+       0x57, 0xfb, 0xfb, 0x41, 0xfb, 0x75, 0x23, 0x99, 0xb3, 0x9e, 0x05, 0xc6,
+       0xa9, 0x69, 0xae, 0x78, 0x1e, 0xe7, 0x93, 0x30, 0x99, 0xcb, 0x97, 0xf5,
+       0x89, 0xae, 0x3c, 0x7b, 0x50, 0xbf, 0x4c, 0xe8, 0x73, 0xd5, 0x02, 0x76,
+       0xed, 0x7b, 0xd2, 0x7e, 0x39, 0x0c, 0xf6, 0xf7, 0xb1, 0x03, 0xa4, 0x4e,
+       0xc3, 0xfa, 0xc0, 0x9e, 0x87, 0xf9, 0x0d, 0x62, 0x7c, 0x9f, 0xd9, 0x45,
+       0x80, 0x13, 0xe0, 0x09, 0x8e, 0x1d, 0xac, 0xb7, 0xb6, 0x82, 0x9c, 0x62,
+       0x69, 0x81, 0xfa, 0xa0, 0x06, 0xa5, 0x25, 0x0c, 0xd6, 0x53, 0xd5, 0xf8,
+       0xbc, 0x01, 0xe5, 0x60, 0xe5, 0x7d, 0x2d, 0xbd, 0xa6, 0xa1, 0x3c, 0x7a,
+       0xc6, 0xe8, 0xdc, 0x12, 0x34, 0xbf, 0xd8, 0xd7, 0xfb, 0x94, 0x3a, 0x22,
+       0x03, 0x72, 0x68, 0x9a, 0x62, 0x27, 0x3d, 0x41, 0xea, 0xe5, 0x77, 0x32,
+       0xf9, 0x2f, 0x8b, 0xf0, 0x66, 0xaa, 0xc0, 0x9b, 0x3b, 0x85, 0x3e, 0x3e,
+       0x2d, 0x82, 0xc3, 0x77, 0x0e, 0x73, 0x26, 0xe0, 0x77, 0x77, 0x59, 0x58,
+       0xa4, 0x01, 0x48, 0x69, 0x5a, 0x59, 0x43, 0x11, 0xc9, 0xa9, 0xa5, 0x61,
+       0x51, 0x28, 0xff, 0x71, 0x2d, 0xa1, 0xf6, 0x5b, 0x96, 0xdd, 0xf9, 0x95,
+       0xaa, 0xb7, 0xdb, 0x3c, 0x0a, 0xec, 0x7b, 0x9b, 0xd2, 0x91, 0x8a, 0x9d,
+       0x7c, 0x89, 0xbe, 0x1e, 0xee, 0x5f, 0xf2, 0x6e, 0x49, 0xec, 0xda, 0x4f,
+       0x5d, 0x92, 0xa0, 0xc3, 0x54, 0xa1, 0x1f, 0xa6, 0x30, 0x97, 0x0d, 0xd6,
+       0x5d, 0xfd, 0x5a, 0xda, 0xe6, 0xf5, 0xf0, 0xca, 0xdc, 0x03, 0xf6, 0x31,
+       0x9f, 0xf8, 0x91, 0xa5, 0x38, 0x9f, 0xf4, 0x63, 0x0b, 0xda, 0x3d, 0x8b,
+       0x5f, 0x0d, 0x6f, 0x51, 0x22, 0x03, 0x70, 0x61, 0x76, 0x57, 0x9e, 0x01,
+       0xbe, 0xab, 0x99, 0xd8, 0x3f, 0x7f, 0x3d, 0xea, 0xa4, 0x47, 0x81, 0xaf,
+       0x00, 0x81, 0xb5, 0x85, 0xf9, 0x13, 0x88, 0x8e, 0x81, 0xdf, 0x28, 0x20,
+       0xf3, 0x36, 0x25, 0x8d, 0xad, 0x30, 0x02, 0xde, 0x55, 0xf7, 0x05, 0xfd,
+       0x0b, 0xea, 0xfb, 0xb7, 0x4c, 0xaa, 0x30, 0x02, 0xde, 0x57, 0x27, 0xf9,
+       0x17, 0x18, 0xa0, 0xde, 0x96, 0x54, 0xc5, 0xeb, 0x83, 0xfc, 0x27, 0xb0,
+       0x7e, 0x21, 0x69, 0x25, 0xaf, 0xe7, 0xfb, 0x17, 0xa8, 0x50, 0x8f, 0x49,
+       0x5e, 0xc3, 0xeb, 0x68, 0x08, 0x02, 0x62, 0x39, 0x92, 0x1f, 0xaa, 0xf0,
+       0x40, 0xff, 0x5f, 0x46, 0x09, 0xb9, 0xee, 0xf4, 0xcf, 0x44, 0xfc, 0xa9,
+       0x7e, 0x25, 0xcd, 0xb0, 0x3e, 0x68, 0xbd, 0xd6, 0x64, 0xce, 0xaf, 0xbe,
+       0x0c, 0xe7, 0xed, 0xbe, 0x4c, 0x64, 0xb3, 0x26, 0x22, 0xbc, 0xd3, 0xfd,
+       0xa9, 0x38, 0x4f, 0xd9, 0xae, 0x23, 0x49, 0xea, 0xc3, 0x1b, 0xa8, 0xbd,
+       0x5c, 0xa7, 0xfc, 0x8e, 0xc5, 0x87, 0xee, 0xff, 0x77, 0x49, 0xbc, 0xff,
+       0xc5, 0x65, 0x42, 0x1f, 0x89, 0x60, 0xeb, 0x10, 0x6e, 0xb0, 0x4d, 0x9e,
+       0x48, 0x80, 0xff, 0xbe, 0xe6, 0xb4, 0x2d, 0xd8, 0xfe, 0xc1, 0xa4, 0x68,
+       0xde, 0xbf, 0x1d, 0xfa, 0x29, 0x0c, 0xf4, 0x23, 0xe1, 0x28, 0xfb, 0x93,
+       0xe3, 0x2e, 0x41, 0x79, 0x8b, 0x7c, 0x38, 0x0c, 0xf8, 0x70, 0x10, 0x1f,
+       0x6d, 0x4c, 0xe2, 0xf2, 0x12, 0xc6, 0x59, 0x4d, 0xe3, 0xa4, 0x00, 0xfc,
+       0xb1, 0xbf, 0x89, 0xfd, 0xf3, 0x70, 0xdf, 0x60, 0xbf, 0x8c, 0x62, 0xbf,
+       0x8c, 0xdc, 0x4e, 0xdd, 0x4c, 0xed, 0xb1, 0xdf, 0xa8, 0x1c, 0xe2, 0xfb,
+       0x05, 0x46, 0x58, 0xc7, 0xbe, 0x8b, 0xd0, 0x3e, 0x31, 0x30, 0x6f, 0x3d,
+       0x7e, 0xec, 0x15, 0xf8, 0xb1, 0xb8, 0x1e, 0x18, 0x21, 0xe9, 0x67, 0xc9,
+       0x84, 0x47, 0xa3, 0x22, 0xb8, 0x5e, 0xc8, 0x0a, 0xb5, 0xeb, 0x88, 0x49,
+       0xe6, 0xf0, 0xb3, 0x26, 0x47, 0xf1, 0x75, 0x76, 0xee, 0x47, 0x6f, 0x85,
+       0xc6, 0xa9, 0x17, 0x70, 0xec, 0x0f, 0x70, 0xcf, 0xbe, 0xf6, 0x75, 0xbf,
+       0x2f, 0xe6, 0xf3, 0x5d, 0xaf, 0x3b, 0x68, 0xbf, 0x5c, 0x2a, 0xbe, 0x6f,
+       0xca, 0xd8, 0x12, 0xbc, 0x1e, 0xb0, 0x2c, 0x35, 0xfd, 0x7c, 0xb9, 0x4a,
+       0xf7, 0x5d, 0x31, 0x10, 0x20, 0xae, 0x33, 0x3a, 0x99, 0xbe, 0x5b, 0x1b,
+       0xce, 0x2c, 0xf4, 0x9c, 0x6d, 0xe9, 0xfc, 0x2e, 0x31, 0x87, 0xeb, 0xa3,
+       0xa8, 0xa7, 0x56, 0x09, 0x7d, 0x9a, 0x79, 0x46, 0x92, 0x53, 0xa1, 0x52,
+       0x70, 0x8d, 0xaa, 0x75, 0x3e, 0x93, 0x03, 0xdf, 0x37, 0x28, 0x2e, 0xaf,
+       0x35, 0x78, 0x7d, 0xb7, 0x16, 0x8a, 0xf5, 0xd9, 0xc5, 0xfa, 0xec, 0x7c,
+       0x7d, 0x5e, 0x0d, 0x9e, 0xb2, 0xc3, 0x1d, 0x09, 0x93, 0x6d, 0x5d, 0xf1,
+       0xb7, 0x13, 0xee, 0x9d, 0xfd, 0x65, 0xe5, 0x8b, 0xfe, 0x34, 0x74, 0x1d,
+       0xaa, 0x3f, 0xa4, 0x8f, 0xee, 0xf6, 0x23, 0x2c, 0xf9, 0x3b, 0xde, 0x0f,
+       0x39, 0x4f, 0x1d, 0x3c, 0x3b, 0xe1, 0xac, 0x9b, 0x9f, 0x84, 0x27, 0xd2,
+       0x33, 0x7d, 0x97, 0xa5, 0xc5, 0x47, 0x39, 0xcf, 0x0b, 0x82, 0x3e, 0xbb,
+       0xd0, 0x75, 0xe2, 0x75, 0x8e, 0x57, 0xc2, 0xbf, 0xab, 0xfa, 0x09, 0xec,
+       0x23, 0xea, 0x27, 0x0e, 0x2d, 0x3e, 0x57, 0x35, 0x26, 0x1a, 0xe6, 0x64,
+       0x05, 0xbe, 0x6b, 0xc2, 0xbd, 0x2c, 0x0a, 0xf8, 0xe7, 0xd2, 0x93, 0x85,
+       0x9d, 0xd7, 0x9f, 0xf5, 0x47, 0xfe, 0xed, 0x29, 0xe5, 0x7e, 0x54, 0xcf,
+       0x2e, 0xb3, 0xb3, 0xde, 0x41, 0x7e, 0xbd, 0xac, 0xe4, 0xb8, 0x90, 0x7e,
+       0x3d, 0x7a, 0xae, 0xb7, 0xf3, 0xda, 0xa3, 0x4c, 0x4c, 0x21, 0xbd, 0x48,
+       0xeb, 0x67, 0x68, 0x8f, 0x73, 0xfa, 0x5c, 0xa8, 0x9f, 0x9e, 0x65, 0xce,
+       0x6d, 0xd0, 0xef, 0x30, 0x9d, 0xde, 0xd1, 0x0e, 0xfb, 0xb9, 0xcb, 0x1a,
+       0xf8, 0x2e, 0x20, 0x4f, 0xb4, 0xf5, 0x9f, 0x08, 0x3a, 0xe8, 0xea, 0x37,
+       0xea, 0x48, 0xc0, 0xf9, 0x15, 0x9a, 0x4b, 0x5f, 0x70, 0x38, 0x19, 0x1b,
+       0x9b, 0xfc, 0x14, 0xf1, 0xf7, 0xc2, 0x9e, 0xa5, 0xcb, 0x13, 0xa1, 0x7e,
+       0x4b, 0xf2, 0x36, 0xe2, 0xd7, 0x85, 0xfd, 0x4a, 0xcf, 0xa3, 0x6b, 0xe6,
+       0xb6, 0xe4, 0xed, 0xbc, 0x9e, 0x59, 0x7a, 0x3e, 0x09, 0xeb, 0x4f, 0x6d,
+       0xe7, 0xed, 0x47, 0xb9, 0x5e, 0x40, 0xfe, 0xce, 0x3c, 0xdb, 0x2b, 0x46,
+       0x0f, 0x09, 0xe8, 0x0f, 0x13, 0x92, 0x1d, 0x5c, 0xff, 0x28, 0x33, 0x30,
+       0xc4, 0x23, 0xb3, 0x7a, 0xb7, 0x13, 0xe5, 0xa4, 0x84, 0x67, 0x77, 0x65,
+       0xa1, 0xd9, 0x50, 0x1b, 0x4a, 0x6f, 0xbd, 0xa3, 0x93, 0x9e, 0xf9, 0x79,
+       0x46, 0xb1, 0x90, 0xcf, 0xc5, 0xd2, 0x8e, 0xf7, 0x1b, 0x35, 0x76, 0x7c,
+       0x7b, 0xa4, 0xc5, 0xa3, 0x02, 0x5c, 0xdb, 0x51, 0x9e, 0xc2, 0x7a, 0xe7,
+       0x24, 0xbb, 0xa7, 0x23, 0xfc, 0x6b, 0x22, 0x5a, 0x67, 0xa2, 0x0a, 0x7c,
+       0x5f, 0xc4, 0x27, 0x26, 0xd4, 0x87, 0x14, 0x17, 0xe8, 0x1b, 0xe8, 0x17,
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+       0xcf, 0xab, 0xaf, 0x3d, 0xf3, 0xb3, 0x7e, 0x7c, 0x98, 0x72, 0x9c, 0xc7,
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+       0x69, 0x75, 0xa2, 0x1b, 0x70, 0x48, 0xf3, 0xa3, 0xcb, 0x51, 0xbf, 0x1a,
+       0xd2, 0xfc, 0xa7, 0x6f, 0xb9, 0xbc, 0xb5, 0xd2, 0x39, 0x95, 0x9c, 0xf7,
+       0x10, 0xf4, 0x37, 0xc2, 0xf3, 0xe2, 0x26, 0x33, 0xcd, 0x7f, 0x48, 0x73,
+       0xc6, 0x7c, 0x6c, 0x3f, 0xec, 0xfd, 0xe6, 0x64, 0xc4, 0x8f, 0x11, 0xc7,
+       0x5a, 0xea, 0x91, 0x1d, 0xb4, 0xef, 0x79, 0xa9, 0x9f, 0x3b, 0xf8, 0xdc,
+       0x8a, 0x9d, 0x54, 0x2e, 0x65, 0x5e, 0xbb, 0x7e, 0xd1, 0x09, 0x8f, 0x2f,
+       0x4c, 0x0c, 0xf5, 0x4b, 0x80, 0xc7, 0xff, 0xe1, 0xf0, 0xb8, 0xb8, 0x00,
+       0xfd, 0x8a, 0x6d, 0x71, 0x87, 0xd6, 0xf8, 0x49, 0x4f, 0xeb, 0xcf, 0xfd,
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+       0x16, 0xfa, 0xbd, 0xf5, 0xf8, 0x7c, 0xd8, 0xc5, 0xda, 0xa2, 0x16, 0xd6,
+       0xd5, 0xbf, 0xcb, 0x96, 0xb8, 0xe9, 0x3c, 0xc0, 0x8c, 0xfb, 0xa2, 0x06,
+       0x9d, 0x0f, 0x94, 0xf8, 0x88, 0x1e, 0xdb, 0x0c, 0x4e, 0x47, 0xb0, 0x1f,
+       0xf7, 0xd1, 0x5e, 0xee, 0x17, 0x70, 0x9f, 0xde, 0x52, 0x00, 0xec, 0x00,
+       0xec, 0x91, 0x96, 0x8e, 0x18, 0xdc, 0xaf, 0x31, 0xb3, 0x1e, 0x52, 0x23,
+       0x71, 0x5f, 0x3a, 0x18, 0xf9, 0xbd, 0x1a, 0x4d, 0xfe, 0x5f, 0x0c, 0x43,
+       0x39, 0x3f, 0x43, 0x25, 0xbd, 0xb7, 0xd1, 0xc8, 0x48, 0x7f, 0x6c, 0x9c,
+       0x9a, 0xed, 0x45, 0xdf, 0xdf, 0x51, 0xc5, 0xff, 0xe2, 0x5f, 0x91, 0x4f,
+       0xcd, 0x88, 0x20, 0x7e, 0x32, 0x02, 0x34, 0x5c, 0x5a, 0x37, 0x9e, 0x81,
+       0x2a, 0xb8, 0x4f, 0x6e, 0xcd, 0xba, 0x4b, 0xd8, 0x62, 0xdd, 0x3e, 0xdd,
+       0xad, 0xa9, 0x8f, 0xb1, 0xff, 0x44, 0xd3, 0xfe, 0xa6, 0xf8, 0x55, 0x9a,
+       0xf7, 0xe3, 0x1d, 0x0f, 0xe8, 0xf6, 0x69, 0xa3, 0xa6, 0x7e, 0x9b, 0xf3,
+       0x51, 0xdd, 0x3e, 0x6d, 0xd6, 0xed, 0xd3, 0x33, 0x9a, 0xf7, 0x23, 0x3e,
+       0xf7, 0xd7, 0x23, 0x19, 0x8d, 0x6a, 0xf5, 0xa8, 0x36, 0x98, 0xff, 0xd0,
+       0xa3, 0x1b, 0xca, 0x70, 0x5f, 0x86, 0x1d, 0xf3, 0xcc, 0x40, 0x7a, 0x29,
+       0x6c, 0x71, 0xd7, 0x13, 0x0b, 0xd9, 0x57, 0xfb, 0x26, 0x96, 0x2d, 0x60,
+       0x57, 0xa1, 0x3f, 0xeb, 0x8d, 0xba, 0x78, 0x2a, 0xf7, 0xd5, 0x39, 0xc8,
+       0x1f, 0xb5, 0xbf, 0x2e, 0x9d, 0xca, 0x03, 0x75, 0x4e, 0x7a, 0xfe, 0x76,
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+       0x7d, 0x75, 0xe5, 0x54, 0x36, 0xd4, 0x35, 0x50, 0xfb, 0x5d, 0x75, 0x4d,
+       0x54, 0x02, 0x04, 0x07, 0xa0, 0xbc, 0x88, 0x8d, 0x11, 0xf2, 0x07, 0xea,
+       0x68, 0xe7, 0xb7, 0x19, 0xfc, 0xd5, 0x78, 0xe2, 0x7a, 0xfa, 0xa9, 0x6f,
+       0x88, 0x4f, 0xb6, 0xf5, 0xf0, 0xb7, 0x61, 0xfd, 0x3e, 0xf6, 0x8f, 0x8a,
+       0xd1, 0x50, 0x3f, 0x9c, 0xc2, 0x88, 0xbf, 0x59, 0xa1, 0x4f, 0xa4, 0xc7,
+       0x73, 0x29, 0xae, 0xca, 0x14, 0xa8, 0x5f, 0x48, 0xe6, 0xcf, 0xdb, 0xc3,
+       0xac, 0xeb, 0x50, 0x0e, 0x34, 0x18, 0x5c, 0x79, 0xa8, 0x5f, 0xff, 0xfb,
+       0xa9, 0xff, 0x6c, 0x34, 0x0e, 0x60, 0xec, 0xfe, 0x55, 0xe5, 0xf1, 0xf6,
+       0x28, 0x5e, 0xb7, 0x40, 0x9d, 0x36, 0x1b, 0x0d, 0x33, 0xcf, 0x7f, 0x36,
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+       0x7b, 0x38, 0x7f, 0x7f, 0xe1, 0xa9, 0xff, 0x90, 0x7e, 0x2d, 0xcf, 0x9b,
+       0x27, 0x07, 0xce, 0x9b, 0xff, 0x9d, 0x1c, 0xe2, 0xbc, 0xf9, 0xb9, 0x53,
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+       0x1c, 0xce, 0xdf, 0x39, 0x05, 0xf5, 0x08, 0xcf, 0xcd, 0x61, 0x6c, 0x1b,
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+       0xc4, 0xe1, 0x12, 0xd7, 0x40, 0x9c, 0xcf, 0xa1, 0x72, 0x33, 0xd1, 0x8f,
+       0xa7, 0xdc, 0xe6, 0x1d, 0x88, 0x4c, 0xce, 0xe8, 0x2a, 0x9a, 0x12, 0xe4,
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+       0x79, 0x6f, 0x7b, 0x79, 0x1a, 0xe9, 0x41, 0xed, 0xb5, 0x00, 0x25, 0xa0,
+       0x8f, 0xf6, 0x53, 0xb5, 0x67, 0x77, 0xd3, 0x7b, 0xb3, 0x3c, 0x0a, 0xa3,
+       0x73, 0xcd, 0x69, 0x82, 0x4f, 0x3d, 0xd7, 0xbc, 0xfc, 0x1f, 0x47, 0xa0,
+       0xfd, 0x27, 0x2b, 0x22, 0x9c, 0xc4, 0xc3, 0xed, 0x83, 0x48, 0x3e, 0xdd,
+       0x25, 0x1a, 0xcf, 0x88, 0xb1, 0x90, 0xde, 0x32, 0x63, 0xe2, 0x80, 0x52,
+       0x94, 0x4b, 0xd3, 0xc4, 0xf9, 0xd8, 0x4c, 0x9b, 0xb1, 0x17, 0x1d, 0x93,
+       0x19, 0xa3, 0x4c, 0x76, 0xe8, 0x67, 0x9e, 0x35, 0x6f, 0x0d, 0x8a, 0xff,
+       0x05, 0xb1, 0x15, 0xa6, 0x28, 0xa8, 0x2f, 0xea, 0x7f, 0xf7, 0x1a, 0x2c,
+       0x97, 0xa4, 0x6c, 0x34, 0x45, 0x43, 0x59, 0x99, 0xf5, 0xfc, 0x1a, 0x54,
+       0x1f, 0xab, 0x80, 0xb4, 0x8a, 0xc8, 0x5e, 0xf2, 0xff, 0xb9, 0x0e, 0xe6,
+       0x35, 0x6b, 0xa5, 0xea, 0xe0, 0xf6, 0x93, 0x90, 0x6b, 0xae, 0xa5, 0xd7,
+       0x14, 0x8f, 0x21, 0xf1, 0x10, 0xe1, 0x88, 0x78, 0x0a, 0xf0, 0x25, 0xbb,
+       0xf0, 0x3d, 0x01, 0x6f, 0xf9, 0xdd, 0x7b, 0x02, 0x9e, 0xb3, 0x52, 0xc4,
+       0x39, 0x6d, 0x36, 0xcb, 0xbe, 0xa4, 0x3d, 0xf7, 0x99, 0x8b, 0x78, 0xd2,
+       0x3a, 0xe3, 0xcf, 0xa9, 0xdd, 0xf8, 0xe7, 0xb5, 0xef, 0x85, 0xde, 0xf6,
+       0x81, 0x89, 0x8f, 0xbb, 0xf4, 0xe9, 0x30, 0x6f, 0xb0, 0x3f, 0x49, 0x8e,
+       0x7b, 0x48, 0xcc, 0xe3, 0xb0, 0x89, 0xb9, 0x14, 0xd4, 0xe3, 0xee, 0xb2,
+       0x11, 0x7e, 0xe4, 0x4c, 0x3d, 0x7f, 0x5f, 0x11, 0xac, 0x3f, 0xa7, 0xd9,
+       0x6e, 0xa0, 0x73, 0x7b, 0xc9, 0xc7, 0x7d, 0x8c, 0xfc, 0xf6, 0x45, 0x9f,
+       0xbb, 0x89, 0xcf, 0xdd, 0xd8, 0xea, 0xdf, 0x7e, 0x84, 0x11, 0x9e, 0x37,
+       0x21, 0x9d, 0x5c, 0x49, 0x4e, 0x4d, 0xf2, 0xac, 0x22, 0xf9, 0x30, 0xe4,
+       0x6b, 0x90, 0x3f, 0xc8, 0x17, 0x2f, 0xba, 0x3f, 0x39, 0x42, 0x7c, 0x70,
+       0x91, 0xe0, 0x83, 0xb5, 0xc4, 0xbf, 0xf6, 0xd5, 0xad, 0xa4, 0xfa, 0xfe,
+       0x3a, 0x0f, 0x95, 0x07, 0xea, 0xd6, 0x09, 0x3e, 0xb8, 0x81, 0xde, 0xbf,
+       0x53, 0xb7, 0x49, 0xf0, 0x41, 0xaf, 0xe0, 0x83, 0x4f, 0xd3, 0xf3, 0xe6,
+       0xba, 0xa9, 0x54, 0xbe, 0x56, 0xe7, 0x16, 0x7c, 0x90, 0x9f, 0xab, 0x4e,
+       0x14, 0xf8, 0xb4, 0x32, 0xde, 0xbd, 0x0e, 0xf9, 0x99, 0x3c, 0xbf, 0x9c,
+       0x6c, 0x71, 0x87, 0x21, 0xbc, 0xfe, 0xf8, 0xa8, 0x99, 0xa9, 0x78, 0x2e,
+       0xd1, 0x6c, 0x26, 0x3c, 0x05, 0x0a, 0x78, 0xf2, 0xb1, 0x58, 0x8c, 0x97,
+       0x31, 0xdb, 0xd7, 0x3b, 0xba, 0xc6, 0xcd, 0xe8, 0xf9, 0x6d, 0xe7, 0xfe,
+       0xeb, 0xce, 0x79, 0x37, 0xc4, 0xbb, 0x1e, 0xc1, 0xf1, 0x3a, 0xe3, 0x64,
+       0x50, 0x3f, 0xbb, 0xa1, 0x7b, 0xfc, 0x39, 0xc4, 0x1c, 0x36, 0xe4, 0x27,
+       0x3b, 0xb6, 0x4e, 0x24, 0xfe, 0x71, 0xc8, 0xe1, 0xb0, 0xa1, 0xde, 0xfa,
+       0x5c, 0xca, 0xa4, 0x89, 0xc8, 0xaf, 0x0f, 0xb9, 0x1c, 0xb6, 0x30, 0xa8,
+       0xff, 0x61, 0xeb, 0x24, 0xfe, 0xde, 0xed, 0xb0, 0x99, 0xa1, 0xbe, 0x33,
+       0x65, 0x32, 0x7f, 0xef, 0x71, 0xd8, 0xc2, 0xa1, 0xde, 0xb0, 0x55, 0xd4,
+       0xbd, 0x8c, 0x0e, 0xb5, 0x77, 0x6f, 0xbd, 0x93, 0xf8, 0x4f, 0x09, 0x53,
+       0xf6, 0x21, 0x3d, 0x94, 0x59, 0x12, 0x47, 0x03, 0xbb, 0x06, 0xf9, 0x58,
+       0xb2, 0x0f, 0xe9, 0xe0, 0xa6, 0xf8, 0xd9, 0xa3, 0x91, 0x0e, 0x52, 0x52,
+       0x1c, 0x84, 0x0f, 0xe3, 0x1d, 0xab, 0xf6, 0x61, 0xfd, 0x96, 0xf4, 0xcd,
+       0xc6, 0x18, 0x07, 0x7a, 0x43, 0xf3, 0x56, 0xe3, 0x77, 0xa5, 0xb1, 0x15,
+       0x46, 0xfc, 0x6e, 0x74, 0xff, 0xbb, 0x57, 0xe3, 0x77, 0x63, 0x53, 0x36,
+       0x1a, 0x83, 0xbf, 0x1b, 0x97, 0xf5, 0xfc, 0x6a, 0xac, 0xdf, 0xea, 0xdc,
+       0x6c, 0x44, 0x7d, 0x30, 0x05, 0xf9, 0x56, 0x5c, 0xa0, 0x1f, 0x59, 0x97,
+       0xef, 0x25, 0x7f, 0x45, 0x3b, 0x01, 0xf1, 0x34, 0xb7, 0xb9, 0x9c, 0xf8,
+       0x78, 0x4e, 0x53, 0x39, 0xf1, 0x71, 0x09, 0x97, 0xd2, 0xc9, 0x15, 0xf7,
+       0xa3, 0x9f, 0xae, 0xa6, 0x49, 0xb1, 0x2b, 0x38, 0x8f, 0xc9, 0x4a, 0xe7,
+       0x61, 0xbd, 0x02, 0x3a, 0x44, 0xf5, 0x45, 0xa0, 0x16, 0xe0, 0xb3, 0xfb,
+       0xb6, 0xce, 0x8b, 0x5e, 0x05, 0xdf, 0xd5, 0x60, 0x7d, 0x28, 0xd5, 0x7f,
+       0xb5, 0x2a, 0x34, 0xdf, 0x3d, 0x98, 0x12, 0x42, 0xbe, 0x7c, 0x28, 0xe8,
+       0x14, 0xe5, 0x66, 0x05, 0x7c, 0xf7, 0x21, 0xd0, 0xcf, 0x2e, 0xa8, 0x67,
+       0xe0, 0xfa, 0xc8, 0x7f, 0x38, 0xdb, 0x36, 0x9b, 0xfa, 0x73, 0xdb, 0x50,
+       0xbe, 0xe6, 0xa6, 0x70, 0x39, 0x59, 0x20, 0xe4, 0xe6, 0x5c, 0x51, 0x2e,
+       0x12, 0xcf, 0x3f, 0xb5, 0xba, 0xde, 0x47, 0xba, 0xfc, 0x38, 0x45, 0xd8,
+       0x63, 0x5d, 0xe9, 0xfa, 0x13, 0x41, 0xb7, 0x0b, 0xf8, 0x3c, 0xba, 0xd0,
+       0xb5, 0xf6, 0xbd, 0xa0, 0x6b, 0xbf, 0x94, 0x0f, 0x85, 0x1d, 0x09, 0x58,
+       0xaf, 0x62, 0x1b, 0xc8, 0x4f, 0x78, 0xa5, 0xf8, 0xae, 0xc5, 0xc1, 0xf6,
+       0x5b, 0x22, 0xc6, 0x49, 0x34, 0x50, 0xfc, 0x85, 0x3e, 0x4e, 0xa2, 0x92,
+       0xf9, 0x78, 0x7f, 0x0d, 0xba, 0x38, 0x0b, 0xe6, 0x37, 0xd1, 0x79, 0x6c,
+       0x53, 0xd0, 0x73, 0xe2, 0x47, 0xc2, 0xfe, 0xe8, 0xc1, 0xf9, 0xde, 0x54,
+       0x64, 0xd6, 0x80, 0x9f, 0xdf, 0x76, 0xcf, 0xcf, 0xfe, 0x8d, 0xf0, 0xbf,
+       0xcc, 0xba, 0xb5, 0xef, 0xc5, 0xba, 0x17, 0x33, 0x2f, 0xc5, 0xb5, 0xe9,
+       0xd7, 0xc1, 0xdc, 0x71, 0x44, 0x5b, 0x4b, 0xad, 0x87, 0x69, 0x3f, 0xbb,
+       0xae, 0xc7, 0x1f, 0x7a, 0x3d, 0x5d, 0xd6, 0xc1, 0xed, 0x77, 0x19, 0xc7,
+       0x22, 0xfd, 0xf2, 0xa0, 0x07, 0xd9, 0x06, 0x16, 0x21, 0x1f, 0xb4, 0x31,
+       0xf4, 0xdf, 0x04, 0xf3, 0x89, 0x23, 0x97, 0xe1, 0x13, 0x7a, 0x7e, 0xf4,
+       0x5d, 0xf1, 0xb9, 0xcb, 0xf0, 0x9b, 0xa4, 0x81, 0x21, 0xf8, 0x8d, 0x8c,
+       0xcf, 0xd2, 0x97, 0x52, 0x9f, 0x83, 0xba, 0x07, 0xe3, 0xf3, 0x3c, 0xaf,
+       0x85, 0x93, 0x9f, 0xfe, 0xa4, 0xc3, 0x9d, 0x8d, 0xfd, 0xb4, 0x97, 0x76,
+       0x7c, 0x63, 0x40, 0xfb, 0x2c, 0xd6, 0x4f, 0x78, 0xe6, 0xe9, 0xe7, 0x76,
+       0xe2, 0x73, 0xc5, 0xc4, 0xcf, 0xe9, 0xe1, 0x49, 0x2a, 0xee, 0xdb, 0x29,
+       0x83, 0xe7, 0x0f, 0xa8, 0x17, 0x0d, 0xdf, 0xf6, 0x24, 0xf1, 0x9d, 0x36,
+       0x14, 0x0e, 0x40, 0x8f, 0x85, 0x50, 0x47, 0xbe, 0xe3, 0xed, 0x5b, 0x3e,
+       0x18, 0xbf, 0x63, 0xe9, 0x1c, 0x7f, 0xda, 0x15, 0x2e, 0x17, 0x25, 0xdd,
+       0x83, 0x3e, 0x48, 0xe5, 0x88, 0x81, 0x5c, 0x1e, 0x75, 0x2d, 0x39, 0x5d,
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+       0x77, 0x83, 0x42, 0xb1, 0x73, 0x95, 0xf7, 0x86, 0x91, 0xbf, 0xfb, 0x4c,
+       0x74, 0x43, 0xce, 0xf2, 0x20, 0x7b, 0x45, 0xc6, 0xaf, 0x94, 0x97, 0xd9,
+       0x5c, 0xa8, 0xff, 0x55, 0xbd, 0x98, 0xb6, 0x45, 0x15, 0xf1, 0x3c, 0xa8,
+       0x7f, 0xfc, 0xcb, 0xc1, 0xed, 0x98, 0x31, 0xaa, 0x95, 0xce, 0x27, 0xce,
+       0x3d, 0xc8, 0xf9, 0x7e, 0x77, 0xfa, 0xdb, 0x82, 0x95, 0xaf, 0x6a, 0xf6,
+       0xb3, 0xcb, 0x7b, 0x55, 0xe1, 0xf6, 0x38, 0x1e, 0xdc, 0xc1, 0x78, 0x67,
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+       0xf8, 0x5d, 0x2f, 0xe0, 0xad, 0xc5, 0xd1, 0x81, 0x78, 0xb1, 0xd8, 0x64,
+       0xe6, 0x42, 0x7b, 0x35, 0xf6, 0x25, 0xe0, 0xcf, 0xb8, 0xc7, 0x9f, 0xfb,
+       0x88, 0x1f, 0x2f, 0x78, 0x89, 0xfb, 0x7f, 0xab, 0x1e, 0x7d, 0x93, 0xe4,
+       0xde, 0x1c, 0xd5, 0x41, 0xfe, 0xdc, 0xb1, 0x59, 0xee, 0x2f, 0x10, 0x6f,
+       0xdb, 0x6c, 0x3e, 0xf2, 0x2b, 0x2e, 0x58, 0xf9, 0x1a, 0xcd, 0xeb, 0x9b,
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+       0x45, 0xff, 0xf9, 0x7c, 0x5f, 0x6a, 0x94, 0x8a, 0x41, 0xc7, 0xbe, 0x5e,
+       0x3c, 0x5e, 0xe9, 0x9d, 0x22, 0xb4, 0x8b, 0xce, 0xd5, 0xda, 0x18, 0xee,
+       0xfb, 0xf4, 0xe5, 0x7f, 0xcb, 0x71, 0x87, 0xf0, 0xfb, 0xea, 0xed, 0x81,
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+       0x8e, 0x9b, 0x82, 0xe3, 0x62, 0x46, 0xa4, 0x72, 0xbc, 0xec, 0xd9, 0xc4,
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+       0x5a, 0xb8, 0x8e, 0x4e, 0xed, 0x82, 0xb7, 0xe3, 0xae, 0x00, 0xd7, 0x71,
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+       0x4f, 0xd1, 0xc3, 0x79, 0xa9, 0x80, 0xab, 0x84, 0xf7, 0xbd, 0x57, 0x80,
+       0xf3, 0xbd, 0xdf, 0x13, 0x9c, 0xef, 0x4d, 0x75, 0x68, 0xfc, 0x11, 0x12,
+       0xde, 0xdd, 0xc9, 0x27, 0xfd, 0xfe, 0xc8, 0x79, 0x87, 0xa0, 0xd3, 0xa2,
+       0xeb, 0xa1, 0xd3, 0x4b, 0x69, 0xdc, 0x4e, 0x64, 0x46, 0x3f, 0xc5, 0x99,
+       0xea, 0xf7, 0xbd, 0xbe, 0x2b, 0x3d, 0xad, 0xbd, 0xc2, 0xbe, 0xaf, 0xfd,
+       0x21, 0xf7, 0x5d, 0x0f, 0x37, 0x7d, 0x59, 0x29, 0xce, 0x3b, 0xf5, 0xcf,
+       0xb7, 0xa5, 0x76, 0xcb, 0xef, 0xbe, 0x13, 0x38, 0xfe, 0x6f, 0xf3, 0xa7,
+       0xcf, 0xa8, 0xdd, 0xab, 0x79, 0x3f, 0x6b, 0xe5, 0x41, 0xcd, 0xfb, 0xd9,
+       0x9e, 0xf7, 0x34, 0xf5, 0xe1, 0x7e, 0x5f, 0x19, 0xa2, 0xb9, 0xf4, 0x8f,
+       0x8f, 0x3c, 0xd5, 0xf1, 0x26, 0xd6, 0xaf, 0xd7, 0xcf, 0xde, 0x9d, 0x7f,
+       0x7d, 0xc2, 0x0b, 0x0b, 0x0d, 0x78, 0xfe, 0x56, 0xec, 0xe3, 0xfe, 0xfd,
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+       0x9c, 0x67, 0x66, 0xf2, 0x7f, 0xb6, 0xec, 0xcd, 0x30, 0x3a, 0xb2, 0xbb,
+       0xe2, 0x41, 0xc9, 0x05, 0x95, 0xb9, 0x82, 0xf4, 0xc4, 0x12, 0x4b, 0x94,
+       0x11, 0xf5, 0xa9, 0x12, 0xd0, 0x94, 0x43, 0xe1, 0xcd, 0x25, 0x81, 0x37,
+       0x14, 0x0f, 0x04, 0xf4, 0x3e, 0xd5, 0xc2, 0xc2, 0x62, 0x81, 0xce, 0xa7,
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+       0xe1, 0xfd, 0x04, 0x23, 0x6b, 0x31, 0x43, 0xbd, 0xc2, 0x6a, 0x6c, 0x31,
+       0xd3, 0xb9, 0x1f, 0xcf, 0x77, 0x98, 0xc2, 0xa7, 0xc9, 0xcc, 0x46, 0xe6,
+       0xc1, 0xf7, 0x2c, 0x36, 0x86, 0xec, 0xe0, 0xc9, 0xf8, 0x10, 0xe6, 0xab,
+       0xba, 0x54, 0x8a, 0x67, 0x9b, 0x52, 0xcc, 0xcf, 0x0b, 0xef, 0xb2, 0x36,
+       0x84, 0xa1, 0x3c, 0xbd, 0xf3, 0xc0, 0x7d, 0x67, 0x7f, 0x06, 0xef, 0xd9,
+       0x6a, 0x4f, 0x11, 0x8f, 0xd7, 0x96, 0xf9, 0x6b, 0x1f, 0x1b, 0xae, 0xe5,
+       0x1c, 0xf0, 0x52, 0x2a, 0xa7, 0xf3, 0x76, 0x45, 0x9c, 0x2b, 0x2b, 0x61,
+       0x4e, 0x8c, 0x6f, 0xd5, 0x7f, 0xf7, 0x7e, 0x2a, 0xf7, 0x97, 0x4e, 0x50,
+       0x57, 0xa9, 0x18, 0xff, 0xd2, 0xf1, 0x1e, 0x23, 0xbd, 0x5b, 0xd2, 0x1d,
+       0xac, 0xef, 0x80, 0x39, 0x9f, 0xe7, 0x67, 0x0c, 0xc5, 0x75, 0xb2, 0xb0,
+       0x96, 0xb4, 0x48, 0xd4, 0x9f, 0x37, 0x96, 0x61, 0xfb, 0xca, 0xc3, 0x0e,
+       0x82, 0x4b, 0x4d, 0xf1, 0xaa, 0x1c, 0xdc, 0xc7, 0x9a, 0xd1, 0xca, 0x67,
+       0xe6, 0x9c, 0x80, 0x7d, 0x53, 0xb3, 0xf2, 0x6b, 0xd2, 0xd3, 0xc7, 0xa8,
+       0x3b, 0xea, 0xb1, 0xfd, 0xb9, 0xa3, 0xdc, 0x35, 0x7e, 0x63, 0xab, 0x47,
+       0x45, 0x7b, 0x25, 0xe0, 0xbf, 0xf4, 0xcf, 0x44, 0xba, 0xbc, 0x92, 0x1d,
+       0x24, 0xe7, 0x7d, 0xac, 0xae, 0x85, 0xf0, 0xe9, 0x93, 0xba, 0x03, 0x54,
+       0xbe, 0x3b, 0xf2, 0x4f, 0x45, 0xa8, 0x67, 0xf8, 0xeb, 0x7c, 0x21, 0xfd,
+       0x97, 0xd7, 0xeb, 0x2f, 0x90, 0x7e, 0x02, 0xe9, 0x37, 0x90, 0x7c, 0xe0,
+       0xd3, 0x7b, 0xcb, 0x7a, 0x23, 0x5e, 0x66, 0xa4, 0x09, 0x3d, 0xd0, 0xa2,
+       0xf4, 0x43, 0xbe, 0xc0, 0x8c, 0xbc, 0x94, 0xfc, 0x32, 0x37, 0xad, 0x8b,
+       0x5c, 0x2d, 0x48, 0xbb, 0xbc, 0x3e, 0xa8, 0x7d, 0xff, 0x3d, 0xf3, 0xd7,
+       0xab, 0xc5, 0xf3, 0xca, 0x78, 0x2e, 0x17, 0xf5, 0xf8, 0xad, 0xc7, 0x6b,
+       0x89, 0xcf, 0xf0, 0x59, 0x91, 0x02, 0xe3, 0xde, 0x05, 0xfa, 0x1e, 0xca,
+       0xd5, 0x69, 0xcc, 0x93, 0x5d, 0x09, 0x7c, 0x76, 0xea, 0xc2, 0x0d, 0x61,
+       0xc3, 0x94, 0xeb, 0xc7, 0xeb, 0x25, 0xd6, 0xcf, 0x13, 0x58, 0x88, 0x3c,
+       0x95, 0x6b, 0xe7, 0xe7, 0x0e, 0xda, 0x47, 0xb5, 0x4c, 0x25, 0xfb, 0x40,
+       0xc6, 0x2b, 0xc8, 0x7d, 0x58, 0x90, 0xd6, 0x45, 0x2e, 0x2e, 0xb9, 0xc2,
+       0xbe, 0x2d, 0xf9, 0x21, 0xf7, 0xad, 0xab, 0x5c, 0xfb, 0x7c, 0xe6, 0xf5,
+       0xc9, 0x35, 0xa6, 0xc9, 0xeb, 0xb8, 0xbf, 0x2b, 0xbe, 0x3e, 0x90, 0x76,
+       0x79, 0x7d, 0x40, 0xfb, 0xfe, 0x7b, 0x5e, 0x77, 0x50, 0xfe, 0xcc, 0x4c,
+       0xd5, 0x10, 0xc8, 0x17, 0xc1, 0x78, 0x62, 0x8c, 0x6b, 0x6c, 0xf7, 0xf2,
+       0x7c, 0xc8, 0x45, 0x89, 0x1b, 0x22, 0x29, 0x38, 0xb3, 0xb8, 0x23, 0x12,
+       0xf5, 0xc6, 0xc5, 0x7b, 0x54, 0xc2, 0x43, 0x66, 0x74, 0x19, 0xfb, 0x00,
+       0xbe, 0x2e, 0x14, 0xf8, 0xda, 0xca, 0x5a, 0x3e, 0x40, 0x7c, 0x5c, 0x38,
+       0x7c, 0x21, 0xe5, 0xd1, 0x2d, 0x7a, 0x3c, 0x74, 0x5c, 0x71, 0xb5, 0x68,
+       0xbf, 0xc4, 0xda, 0x68, 0xc2, 0x75, 0x2e, 0xd9, 0xaa, 0x6d, 0x57, 0x2d,
+       0xe2, 0x8a, 0x2b, 0x77, 0x68, 0xfd, 0xa2, 0xd5, 0xc3, 0x6f, 0x3a, 0x89,
+       0xfd, 0x56, 0xeb, 0xe2, 0x79, 0x76, 0xa6, 0x89, 0xf8, 0xe1, 0x7c, 0x96,
+       0xcf, 0xe3, 0x2e, 0xb4, 0xfa, 0xa9, 0xbe, 0x6c, 0xab, 0x63, 0x1a, 0x7f,
+       0x65, 0xdb, 0xc5, 0x3a, 0xf2, 0x07, 0xbc, 0xf4, 0xbb, 0xd6, 0x87, 0x3d,
+       0xfd, 0x83, 0xec, 0xff, 0xae, 0x78, 0xbb, 0xf7, 0x0a, 0xfb, 0xb7, 0xf7,
+       0x87, 0xdc, 0x3f, 0x3d, 0xde, 0xaa, 0xb6, 0xad, 0x94, 0x57, 0x75, 0xad,
+       0x78, 0xfb, 0xd3, 0x41, 0xae, 0x0f, 0x70, 0xde, 0x92, 0x1f, 0x4f, 0x47,
+       0xde, 0x04, 0xe3, 0x4e, 0x7f, 0xd5, 0xec, 0xf5, 0xe0, 0xf9, 0x68, 0x91,
+       0x83, 0xfb, 0x37, 0x15, 0x6f, 0x3d, 0x9e, 0xb7, 0xb5, 0x7f, 0xcb, 0xc8,
+       0x7f, 0x34, 0x47, 0xf8, 0x39, 0xbb, 0xcb, 0x4b, 0x97, 0xf1, 0x06, 0x43,
+       0x0e, 0x7b, 0xeb, 0x79, 0xbc, 0x81, 0x4b, 0xc5, 0x3c, 0xd1, 0xc1, 0x07,
+       0xca, 0xcb, 0xf0, 0xb8, 0xa2, 0xe0, 0x9d, 0x5a, 0xd2, 0x47, 0xba, 0x3d,
+       0xb7, 0x92, 0xf9, 0x55, 0x22, 0x7e, 0xe8, 0x6a, 0xf9, 0x9a, 0xf4, 0xeb,
+       0x0d, 0x3e, 0x55, 0x4b, 0x7a, 0x96, 0xd3, 0x67, 0x27, 0x7d, 0x68, 0xe8,
+       0x85, 0x86, 0x37, 0x51, 0x3e, 0x7e, 0x57, 0xfe, 0x6e, 0x29, 0x0f, 0x73,
+       0x63, 0x38, 0xdc, 0x0a, 0xfd, 0xe5, 0xa4, 0xe7, 0xb5, 0x85, 0xb5, 0x14,
+       0x7d, 0x88, 0x7a, 0xc2, 0xcb, 0xe1, 0x21, 0xf5, 0x84, 0x1e, 0xe9, 0x5c,
+       0x4f, 0x98, 0xe4, 0x99, 0x1d, 0xc6, 0xf3, 0x0d, 0xbb, 0x9c, 0x07, 0xf6,
+       0x48, 0xc7, 0xf3, 0x40, 0xc1, 0xff, 0x0d, 0x16, 0x57, 0x18, 0xc2, 0x69,
+       0x8c, 0xda, 0xfa, 0xeb, 0x3b, 0x10, 0x7f, 0x7c, 0x2a, 0xf9, 0xf7, 0x56,
+       0xfc, 0xfc, 0xfd, 0x3f, 0x3c, 0xe6, 0xb8, 0xb2, 0xdd, 0x5f, 0x63, 0x3f,
+       0x4f, 0x7a, 0x43, 0x77, 0xfa, 0x7f, 0x8d, 0x81, 0xe7, 0x5d, 0xe4, 0x97,
+       0x39, 0x28, 0xce, 0x0f, 0xed, 0x29, 0xf4, 0xef, 0x49, 0x7f, 0x9f, 0xbe,
+       0x7d, 0xf1, 0xa0, 0xd2, 0xfe, 0xe9, 0x71, 0xe4, 0xaf, 0xf6, 0xb9, 0x70,
+       0x3e, 0x9b, 0xf8, 0x7c, 0xba, 0xdb, 0x9f, 0x9a, 0x95, 0x5f, 0x69, 0xfc,
+       0x8b, 0xdd, 0x8d, 0x5f, 0xb3, 0xa7, 0xc8, 0x3e, 0x27, 0x88, 0x0e, 0x66,
+       0xa4, 0x2b, 0x12, 0xcf, 0xed, 0x27, 0x2c, 0x81, 0xfd, 0xbd, 0x5a, 0x3c,
+       0x18, 0xd1, 0x31, 0x55, 0xa3, 0xff, 0xfc, 0xff, 0x6e, 0x57, 0x4c, 0x50,
+       0x41, 0xb5, 0x04, 0xf9, 0x99, 0xad, 0x78, 0xb9, 0xfe, 0xca, 0xb8, 0x1e,
+       0x3b, 0x9d, 0xf9, 0xa8, 0x9c, 0xc9, 0x3a, 0xa8, 0x74, 0x33, 0x1e, 0x7f,
+       0x3f, 0x87, 0x39, 0xa9, 0x9c, 0x27, 0xf2, 0x98, 0xdf, 0xce, 0x70, 0x57,
+       0xa4, 0x53, 0x3c, 0x4c, 0x47, 0x2f, 0x8a, 0x9f, 0x7c, 0xf1, 0x7f, 0xb2,
+       0x10, 0x6f, 0xce, 0x8e, 0x1c, 0xb6, 0x01, 0x63, 0xed, 0xbe, 0x2f, 0x3d,
+       0xae, 0x3d, 0xcf, 0x41, 0xe3, 0xb7, 0xef, 0xfe, 0x9f, 0x04, 0x8c, 0x83,
+       0xb9, 0x12, 0x5f, 0xd8, 0x10, 0xef, 0x9a, 0x97, 0x1e, 0xe2, 0x3c, 0xe8,
+       0x2f, 0x25, 0x2a, 0x9d, 0xb7, 0xb0, 0x53, 0x8f, 0x91, 0x9c, 0xa8, 0x10,
+       0xb7, 0x30, 0xb0, 0xd1, 0xfc, 0x1c, 0xed, 0x5f, 0x8e, 0x44, 0xa2, 0x9b,
+       0x00, 0x5f, 0xec, 0xbd, 0x59, 0xf2, 0x45, 0x3c, 0x9f, 0xcd, 0xfe, 0xcc,
+       0xc0, 0xe3, 0x49, 0x16, 0x2b, 0xde, 0x81, 0xd0, 0xb4, 0xc9, 0x6f, 0x20,
+       0xd2, 0xca, 0x9e, 0x9f, 0xe8, 0x55, 0xb1, 0xde, 0xc8, 0xdf, 0x67, 0x57,
+       0x45, 0x79, 0x15, 0xa8, 0x67, 0x0f, 0x09, 0xe7, 0xef, 0xef, 0x8e, 0xf2,
+       0xa2, 0x1f, 0x7d, 0x06, 0xf3, 0x13, 0x3d, 0xce, 0x62, 0x8c, 0xf8, 0xdd,
+       0x6c, 0xc6, 0xf9, 0xde, 0x5c, 0xe6, 0xe2, 0xf9, 0x0e, 0xac, 0x23, 0x09,
+       0xf5, 0xb0, 0xf9, 0xcd, 0x16, 0x1e, 0xef, 0xcf, 0xfc, 0x29, 0xc8, 0xdf,
+       0x73, 0xba, 0xb1, 0x7f, 0x5a, 0x04, 0x9d, 0xe7, 0x26, 0x71, 0x7e, 0x9e,
+       0x5b, 0xaa, 0xf5, 0x53, 0xac, 0x49, 0xe7, 0x7c, 0xfc, 0x64, 0x46, 0xe9,
+       0x67, 0x48, 0x4f, 0x67, 0xd2, 0x5d, 0x6b, 0xb1, 0xcc, 0x8d, 0xf6, 0xad,
+       0x7f, 0xb8, 0x90, 0xfc, 0xf6, 0x0c, 0xed, 0x87, 0x93, 0x43, 0x7e, 0x42,
+       0xe7, 0x8d, 0xf2, 0xbb, 0xc8, 0x41, 0xa5, 0x0f, 0x62, 0xbb, 0x9d, 0x0a,
+       0x8f, 0x4f, 0xf7, 0xec, 0x31, 0x53, 0x7c, 0x04, 0x7c, 0xd1, 0xab, 0x3c,
+       0x28, 0xae, 0xff, 0xed, 0x8c, 0xb2, 0x5f, 0x61, 0xbb, 0x47, 0x11, 0xf6,
+       0x45, 0xdd, 0xc3, 0x15, 0xbe, 0xd3, 0xe4, 0xcd, 0x06, 0xe8, 0xc9, 0xc3,
+       0xe7, 0x8f, 0x36, 0x17, 0xf9, 0xdf, 0xe1, 0x41, 0x31, 0x8d, 0x4b, 0xf5,
+       0xdf, 0x3f, 0x3d, 0x61, 0xf2, 0x6a, 0x2b, 0xf9, 0xf8, 0x3d, 0xa8, 0xf7,
+       0x46, 0x0e, 0x72, 0x3f, 0x85, 0xfb, 0x9a, 0x6b, 0x62, 0xcc, 0x8a, 0xf3,
+       0x7f, 0xc2, 0xec, 0xdd, 0x42, 0xfa, 0x69, 0x6d, 0x02, 0xfa, 0x2b, 0x17,
+       0x3e, 0x69, 0x36, 0xa0, 0xde, 0xf0, 0x11, 0x88, 0x5b, 0xcc, 0x43, 0xf9,
+       0x6b, 0x9d, 0x85, 0xca, 0xbf, 0x81, 0x1d, 0x8c, 0xe5, 0xa7, 0x60, 0x07,
+       0x63, 0xf9, 0x19, 0xd8, 0xc1, 0x58, 0xfe, 0x1d, 0xec, 0x60, 0x2c, 0xe7,
+       0x5f, 0xc8, 0x03, 0x61, 0xc1, 0xd8, 0xd8, 0x0c, 0x57, 0x33, 0xc7, 0xef,
+       0xd0, 0xf9, 0x59, 0xbb, 0x05, 0x3c, 0x3b, 0xc7, 0xdf, 0x63, 0xa2, 0xf1,
+       0x4f, 0x66, 0xb8, 0x09, 0xbe, 0x9d, 0xfb, 0xfd, 0x32, 0xf3, 0xe2, 0xa1,
+       0xce, 0xce, 0xa8, 0x8e, 0xbe, 0xd1, 0x97, 0xc1, 0xb7, 0xee, 0xf9, 0x8c,
+       0x47, 0xd8, 0x83, 0xa1, 0xe3, 0xb9, 0x9e, 0x15, 0xf3, 0xc8, 0x69, 0x34,
+       0x92, 0x7c, 0xcf, 0x69, 0xf2, 0x47, 0x2e, 0x08, 0x6a, 0xf7, 0x76, 0xba,
+       0x89, 0xde, 0x67, 0xef, 0xfe, 0x9c, 0xf2, 0x4f, 0xdb, 0xec, 0x9d, 0xf0,
+       0x75, 0x29, 0xb0, 0xe4, 0x09, 0x06, 0x5e, 0x7f, 0xfb, 0xe9, 0x79, 0x93,
+       0x57, 0x67, 0xe1, 0xfc, 0x5d, 0x9f, 0xe1, 0xba, 0x81, 0xbe, 0xff, 0x82,
+       0x65, 0x4e, 0xd3, 0xfb, 0xbf, 0xc2, 0xfc, 0x1f, 0xe8, 0x9f, 0xe2, 0x0e,
+       0xda, 0x95, 0x8e, 0xdf, 0x90, 0x1d, 0xa0, 0x5b, 0x87, 0x1e, 0x0e, 0x72,
+       0x5d, 0x3b, 0xa3, 0x7c, 0xeb, 0xf1, 0xfb, 0x9d, 0xbb, 0x93, 0x70, 0x25,
+       0xc0, 0x6f, 0x18, 0xa7, 0x1b, 0xc4, 0x23, 0x25, 0xd4, 0x7a, 0x57, 0xd1,
+       0x7c, 0x6f, 0x37, 0x77, 0x14, 0x62, 0x5e, 0xcb, 0xed, 0x97, 0xd4, 0x90,
+       0x71, 0xc6, 0x27, 0x33, 0x4a, 0x08, 0xce, 0x3f, 0x97, 0xf8, 0x26, 0xe1,
+       0x24, 0xf6, 0xeb, 0x7a, 0xe9, 0xba, 0xf3, 0xfc, 0x5b, 0xe0, 0x29, 0x93,
+       0xf7, 0x77, 0x20, 0xef, 0x74, 0xa0, 0x1c, 0xba, 0x18, 0x89, 0xfa, 0x5e,
+       0x85, 0x38, 0xdf, 0x6f, 0x6a, 0x4c, 0x79, 0x17, 0xd7, 0xe7, 0x39, 0xa0,
+       0xb2, 0x81, 0x0e, 0xc2, 0x5f, 0x0d, 0xdd, 0xc5, 0x66, 0xf0, 0xfd, 0x91,
+       0x65, 0xf6, 0x1e, 0x53, 0x39, 0xee, 0xd3, 0xce, 0x3d, 0x27, 0x52, 0xe6,
+       0x59, 0x69, 0x5f, 0x52, 0xe6, 0x43, 0x7b, 0x63, 0xc6, 0x40, 0x8d, 0xff,
+       0x31, 0x7b, 0xc8, 0xb7, 0xff, 0xfd, 0x70, 0x2c, 0xb5, 0xb7, 0xe3, 0x50,
+       0x77, 0xb2, 0xcd, 0x63, 0x30, 0xfe, 0x64, 0x9a, 0x65, 0xef, 0x1f, 0x71,
+       0x49, 0x33, 0xec, 0x9f, 0x8d, 0xc1, 0xf8, 0x93, 0x59, 0xf1, 0xca, 0x7e,
+       0x2c, 0x67, 0x3b, 0x12, 0xc7, 0x62, 0xdc, 0x89, 0x8c, 0x8f, 0x9f, 0x9b,
+       0x5e, 0xb2, 0x1f, 0x49, 0xe9, 0x56, 0x67, 0x05, 0xe9, 0x69, 0x25, 0xc8,
+       0x5c, 0x82, 0xe4, 0x41, 0x99, 0x25, 0x02, 0x0f, 0x05, 0x3b, 0xeb, 0x63,
+       0xec, 0x31, 0x9a, 0xfa, 0x4d, 0xf1, 0xfd, 0x34, 0xed, 0xc7, 0x3b, 0x92,
+       0x35, 0xef, 0x6f, 0x49, 0xcf, 0xd4, 0xbc, 0x97, 0xe3, 0xde, 0xea, 0x2c,
+       0xd0, 0xb4, 0xcb, 0x8d, 0xee, 0x48, 0x42, 0xfb, 0x0c, 0xd6, 0x41, 0xf4,
+       0xc0, 0xb6, 0xa9, 0x14, 0xa7, 0x97, 0xbd, 0xfb, 0xf0, 0xcd, 0x99, 0x50,
+       0x9f, 0xb0, 0x7d, 0x8a, 0x13, 0xd5, 0x92, 0x9d, 0xe2, 0xfd, 0x84, 0x5d,
+       0x65, 0x5e, 0xdc, 0x8f, 0x76, 0x80, 0xa7, 0x09, 0x14, 0xa8, 0x53, 0xc5,
+       0x0f, 0xfc, 0xe6, 0x61, 0xec, 0x4c, 0xa7, 0xff, 0x57, 0xee, 0x79, 0x6a,
+       0xbf, 0xcb, 0x71, 0x0d, 0xfa, 0x7f, 0x37, 0x7a, 0xbf, 0xe4, 0xb3, 0x4b,
+       0x9b, 0x2d, 0x45, 0xc8, 0x67, 0xaf, 0xd6, 0x0e, 0xd0, 0xef, 0x4f, 0x7e,
+       0x86, 0xd6, 0x2e, 0xe8, 0x0e, 0x6f, 0x3a, 0xe9, 0x42, 0x71, 0x70, 0xbc,
+       0x39, 0xa8, 0xb2, 0x6d, 0x21, 0xf0, 0x06, 0x23, 0x52, 0x39, 0x1e, 0xf2,
+       0x72, 0xc2, 0x21, 0x9e, 0x3f, 0x76, 0xad, 0xfc, 0xec, 0x0b, 0xe4, 0x67,
+       0x31, 0x01, 0xfa, 0xe8, 0x2c, 0x75, 0x7e, 0xb9, 0x5c, 0x93, 0xf3, 0xdd,
+       0xe5, 0xe8, 0xa7, 0xff, 0xb3, 0xca, 0x28, 0x1f, 0x4f, 0xe4, 0xf5, 0x2d,
+       0xc0, 0xdf, 0xd5, 0x00, 0xbe, 0xb3, 0x79, 0x9b, 0xef, 0xef, 0x13, 0x4b,
+       0xcf, 0x3d, 0xa8, 0xe7, 0x62, 0x7e, 0xa9, 0x0b, 0xfa, 0x5f, 0x92, 0x21,
+       0xf4, 0xa7, 0xca, 0xbd, 0xf7, 0xf7, 0x29, 0x0c, 0xbc, 0x67, 0x2b, 0x3e,
+       0xd3, 0xb4, 0x67, 0xf7, 0x2a, 0x6b, 0x34, 0xf5, 0xd5, 0x89, 0xda, 0xfa,
+       0x83, 0x25, 0x6b, 0x82, 0xbf, 0xef, 0x8e, 0x2f, 0x2e, 0xd8, 0x34, 0xdb,
+       0xe4, 0xa6, 0xfc, 0x4f, 0xc5, 0xe5, 0x0d, 0xc1, 0x1f, 0xe4, 0x7c, 0xc6,
+       0xbc, 0x11, 0x4e, 0x71, 0x7d, 0xb7, 0x61, 0xbc, 0x0a, 0x3c, 0xaa, 0x2e,
+       0x7c, 0xcf, 0x88, 0xe7, 0xb0, 0xb7, 0x75, 0x23, 0x47, 0x25, 0xff, 0xb9,
+       0x53, 0x65, 0xb5, 0xa1, 0xde, 0xdf, 0x93, 0xc1, 0xfd, 0xfc, 0xb7, 0xbe,
+       0x11, 0x4e, 0x71, 0x30, 0xd7, 0xda, 0xef, 0x47, 0x00, 0x4b, 0x8a, 0x33,
+       0x7c, 0x89, 0xcb, 0xd1, 0x8f, 0x7a, 0xfa, 0x8c, 0xc1, 0xfb, 0xee, 0x11,
+       0xfd, 0x9f, 0x2d, 0xda, 0xf8, 0xf3, 0x6f, 0xf0, 0x7c, 0xf4, 0x65, 0x46,
+       0x71, 0x9f, 0x67, 0xa3, 0x38, 0xff, 0xcf, 0x69, 0x3c, 0x69, 0x30, 0xa0,
+       0x1c, 0xec, 0xc1, 0xf1, 0x25, 0xc7, 0xee, 0x37, 0xa0, 0x5c, 0x69, 0x5f,
+       0x14, 0xe1, 0xc1, 0xb8, 0xfe, 0x9a, 0xc5, 0x36, 0x8a, 0x07, 0xcd, 0x4d,
+       0xea, 0xf8, 0xc0, 0x02, 0x5b, 0xbf, 0xee, 0x99, 0x03, 0x8f, 0x58, 0x00,
+       0xdf, 0x3e, 0xc6, 0x24, 0xc8, 0x20, 0xb9, 0xda, 0x8e, 0x46, 0x11, 0xd4,
+       0x37, 0x66, 0x1c, 0x20, 0xb9, 0x7a, 0xcb, 0x1b, 0xe1, 0x2d, 0x86, 0xeb,
+       0x58, 0xcf, 0x46, 0x3c, 0x97, 0x40, 0x39, 0x58, 0xca, 0xe9, 0x7c, 0x26,
+       0xe2, 0x8d, 0x90, 0x2f, 0xe8, 0x63, 0xaf, 0xb9, 0x9f, 0x75, 0xca, 0x1b,
+       0xe4, 0x0b, 0xb8, 0x7e, 0xac, 0x1f, 0x78, 0xe6, 0x4f, 0x87, 0x1f, 0x81,
+       0x79, 0xd7, 0x1c, 0xe4, 0x74, 0x8e, 0x11, 0x76, 0x7a, 0xfb, 0x7e, 0x5a,
+       0x90, 0x7d, 0xcf, 0x1e, 0xe7, 0x74, 0x69, 0x81, 0x1f, 0x1e, 0xa7, 0xa4,
+       0xa3, 0xef, 0x7d, 0x1b, 0x4c, 0xd6, 0xcb, 0xd2, 0x79, 0x03, 0xc5, 0xdd,
+       0x5c, 0x2d, 0x7d, 0xef, 0x40, 0x7a, 0x8e, 0xb8, 0x2c, 0x3d, 0x1f, 0xba,
+       0x05, 0xf6, 0xa7, 0xe6, 0x65, 0x7e, 0x9f, 0xc5, 0xb9, 0xe6, 0x81, 0x94,
+       0x17, 0xdb, 0x9d, 0x3c, 0xaf, 0xd9, 0xa4, 0x12, 0x1d, 0xca, 0x7a, 0x5b,
+       0xb3, 0x3a, 0x0e, 0xf1, 0x56, 0x9f, 0x7f, 0x2e, 0xe1, 0xca, 0x5c, 0x4e,
+       0xa2, 0x4f, 0x79, 0x6f, 0xd4, 0xb2, 0x11, 0xff, 0x9c, 0x88, 0x72, 0x73,
+       0xd9, 0x1e, 0x23, 0x0f, 0x12, 0xe9, 0x6e, 0x9c, 0x75, 0x2a, 0x73, 0x04,
+       0x8d, 0xb3, 0xf3, 0x35, 0xf3, 0x22, 0xca, 0x73, 0x13, 0xf3, 0x6f, 0x97,
+       0xf2, 0x7a, 0xcf, 0x3f, 0xa2, 0x4b, 0xb2, 0x78, 0xb9, 0x2a, 0x84, 0xdc,
+       0x03, 0x39, 0x1d, 0x16, 0x8b, 0x72, 0xba, 0x42, 0x21, 0xbb, 0xf2, 0xc8,
+       0x9e, 0xde, 0xa5, 0x08, 0xa7, 0x23, 0x0a, 0x6b, 0x71, 0x50, 0xde, 0x16,
+       0x8f, 0x53, 0x9e, 0xc4, 0xbb, 0xc3, 0xe7, 0x56, 0xba, 0xaf, 0x24, 0x3e,
+       0x9d, 0xe2, 0x93, 0xa5, 0x7d, 0x29, 0xed, 0xca, 0x29, 0x7b, 0xa6, 0x0c,
+       0x44, 0xbd, 0xf2, 0x83, 0xc6, 0x39, 0x47, 0x60, 0xe7, 0xd8, 0xa7, 0x19,
+       0xc9, 0x84, 0xe7, 0x77, 0x30, 0x0f, 0xe9, 0xc1, 0x47, 0xa2, 0xca, 0x07,
+       0xa0, 0x5f, 0x62, 0x82, 0x88, 0x0f, 0x38, 0x12, 0xd5, 0xd1, 0x8a, 0x7c,
+       0xf9, 0xc8, 0x88, 0x08, 0x05, 0xcf, 0xfb, 0xa1, 0xff, 0xd5, 0xd8, 0xbf,
+       0x5c, 0xd7, 0x91, 0xb0, 0xf2, 0x01, 0xfc, 0xde, 0x09, 0x19, 0x97, 0x3c,
+       0xe8, 0xba, 0xee, 0x89, 0x1b, 0xa3, 0xde, 0x5b, 0x72, 0x0b, 0x9e, 0x6f,
+       0x4f, 0x67, 0x76, 0xb4, 0x2b, 0x6f, 0x57, 0xb9, 0x9e, 0xcb, 0x5e, 0xe7,
+       0xf4, 0x29, 0xf9, 0x5e, 0x8d, 0xe2, 0x8b, 0xc6, 0x79, 0xbe, 0x9d, 0x31,
+       0xf1, 0xab, 0x0c, 0x3c, 0x2f, 0x5e, 0xf9, 0x0b, 0xe1, 0x57, 0x15, 0x70,
+       0x33, 0xf2, 0x38, 0xc4, 0xab, 0xd5, 0x73, 0x3b, 0xed, 0xd9, 0xa7, 0x15,
+       0x7e, 0x1f, 0x8a, 0x93, 0xeb, 0xff, 0xd5, 0xc3, 0xcf, 0xfc, 0xfa, 0x0e,
+       0xcc, 0x93, 0x03, 0xbb, 0x5b, 0x81, 0xf9, 0xcc, 0x69, 0xda, 0x4b, 0xf7,
+       0xfe, 0xe8, 0xed, 0xec, 0x4e, 0x7b, 0xe7, 0xff, 0xd1, 0x9f, 0xda, 0xd5,
+       0x5e, 0x2a, 0x8f, 0x18, 0x54, 0x14, 0xf0, 0x93, 0xeb, 0xed, 0xa6, 0x4e,
+       0x3d, 0x5d, 0xea, 0x7b, 0xdb, 0x78, 0x9c, 0xfc, 0x9b, 0x23, 0x7e, 0xdb,
+       0xb6, 0x14, 0xea, 0x2b, 0xb6, 0x45, 0x10, 0x1c, 0x4f, 0x3f, 0x69, 0xf6,
+       0x20, 0x1f, 0x3f, 0xbd, 0xc5, 0x4c, 0xf6, 0xcf, 0xe9, 0xe8, 0x8e, 0x63,
+       0xcb, 0xb1, 0xbe, 0x2b, 0xdb, 0xe9, 0xa1, 0xd1, 0x9c, 0x9a, 0x7b, 0xd1,
+       0x16, 0x1a, 0x1c, 0x1f, 0xa2, 0xfc, 0x61, 0x6f, 0x87, 0xd1, 0x7d, 0x1e,
+       0x27, 0x9f, 0x30, 0xb7, 0xe0, 0xf9, 0xee, 0xe2, 0xa7, 0x32, 0xb6, 0xa0,
+       0x3d, 0x75, 0x72, 0x80, 0xe3, 0xd9, 0x1d, 0xe8, 0x0f, 0x7c, 0x36, 0x8e,
+       0xee, 0x19, 0x60, 0x6e, 0xfe, 0xfd, 0x6d, 0x82, 0x1e, 0x91, 0xbe, 0x1c,
+       0xa0, 0x7a, 0xa8, 0xbf, 0xb3, 0x91, 0x1e, 0xb1, 0xf8, 0x85, 0x3e, 0xc4,
+       0xc7, 0xe4, 0xfe, 0x9d, 0x7a, 0x22, 0x9c, 0xf2, 0xe8, 0x4f, 0x1f, 0x98,
+       0xd4, 0x13, 0xfd, 0x65, 0xad, 0x86, 0xe7, 0x29, 0x8f, 0x87, 0xa9, 0x56,
+       0x0f, 0xf2, 0xe3, 0xa5, 0x5b, 0xc2, 0x49, 0x0f, 0x5c, 0x69, 0x77, 0x67,
+       0xe3, 0xfa, 0xcb, 0x7e, 0x77, 0xdb, 0x1d, 0x05, 0x38, 0xfe, 0xfb, 0x71,
+       0x0c, 0xd7, 0xd3, 0xde, 0xfc, 0x02, 0xf9, 0x2b, 0x03, 0xfb, 0x1b, 0x5a,
+       0xbe, 0x9f, 0x6b, 0x4e, 0xe6, 0x7c, 0xa0, 0x53, 0xde, 0xf2, 0xb8, 0xdb,
+       0x59, 0x18, 0x77, 0x9b, 0x4c, 0x71, 0xb7, 0x05, 0x83, 0xe2, 0x30, 0x5e,
+       0x55, 0xde, 0xbb, 0xc8, 0xe3, 0x6e, 0xf3, 0x55, 0xc5, 0x45, 0x79, 0x07,
+       0x0f, 0x85, 0xce, 0x23, 0x1f, 0x3d, 0x48, 0x9c, 0xab, 0x4a, 0xff, 0x49,
+       0x0c, 0xb3, 0xc4, 0x23, 0x1d, 0xba, 0x19, 0xad, 0xb7, 0xfd, 0xa1, 0xb4,
+       0x2d, 0x68, 0xef, 0x4c, 0x1f, 0x24, 0xf2, 0x9f, 0x59, 0x87, 0xc8, 0x97,
+       0x94, 0xf8, 0x76, 0xac, 0xfa, 0x55, 0xf2, 0x9f, 0x98, 0x79, 0xbc, 0x5f,
+       0x78, 0xe8, 0x73, 0xec, 0xf2, 0x41, 0x3c, 0xaf, 0x78, 0x81, 0xe5, 0x6b,
+       0x8d, 0xff, 0xa6, 0x7a, 0xe5, 0xb7, 0x1a, 0xbf, 0x4a, 0x75, 0x16, 0x23,
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+       0xec, 0xfe, 0x19, 0xb5, 0xda, 0x38, 0xe3, 0x59, 0x2b, 0x3f, 0xd2, 0xe0,
+       0xdf, 0x6c, 0xcf, 0x67, 0x9a, 0xf7, 0xfe, 0xd8, 0x8e, 0xb0, 0x7e, 0xb0,
+       0x7e, 0xff, 0x8b, 0x7d, 0xc6, 0x4e, 0x03, 0xf8, 0x9d, 0xdd, 0x6d, 0x1e,
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+       0x78, 0x1e, 0x8f, 0xc6, 0x2e, 0x95, 0xa5, 0xe9, 0x0d, 0x46, 0xf7, 0xe4,
+       0x74, 0x28, 0x3d, 0x9c, 0xa1, 0xfc, 0x2c, 0x9f, 0x66, 0x71, 0xbd, 0xfd,
+       0x98, 0xc8, 0x83, 0x3c, 0x26, 0xf2, 0x20, 0x8f, 0x89, 0xbc, 0xc5, 0x63,
+       0x22, 0x4f, 0xf1, 0x98, 0xc8, 0x53, 0x94, 0xf9, 0xa3, 0xc7, 0x14, 0xe6,
+       0xc2, 0x78, 0x8a, 0xe9, 0x4a, 0xf9, 0x93, 0xb3, 0x15, 0xca, 0x1f, 0xbd,
+       0x07, 0xf1, 0xaf, 0x66, 0x49, 0x47, 0x0e, 0xe6, 0xdb, 0xd5, 0xe4, 0xfa,
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+       0xc1, 0xbc, 0xf7, 0x5d, 0x59, 0x77, 0xfe, 0x08, 0xf5, 0xf8, 0x53, 0x3d,
+       0x3c, 0x74, 0x2f, 0xc9, 0xef, 0x77, 0x4c, 0xe6, 0x75, 0x13, 0xa7, 0x8f,
+       0x57, 0xb2, 0x46, 0x11, 0x3d, 0x78, 0xfb, 0xba, 0xef, 0xc3, 0x7e, 0xbe,
+       0x50, 0xd4, 0x16, 0xc2, 0xe7, 0x97, 0x15, 0x3a, 0x4f, 0x65, 0x2e, 0xbf,
+       0x69, 0xe2, 0x65, 0xf2, 0x4b, 0x1f, 0xc8, 0xe2, 0xe7, 0x0b, 0xeb, 0x75,
+       0xe5, 0xd6, 0x2c, 0xce, 0xcf, 0x5e, 0x11, 0xe5, 0x18, 0xf5, 0xc1, 0x54,
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+       0xff, 0xd7, 0xe7, 0x67, 0xe5, 0xbf, 0x6e, 0x6e, 0x41, 0xbe, 0x21, 0xfd,
+       0x30, 0x4f, 0x64, 0x25, 0xf2, 0x73, 0xcf, 0x64, 0xee, 0x5f, 0x89, 0xfd,
+       0xa5, 0x99, 0xe7, 0x6d, 0xf9, 0x7d, 0x09, 0x98, 0xe7, 0x85, 0xf1, 0x3e,
+       0x78, 0x6f, 0x06, 0x3b, 0xcc, 0x5c, 0x3c, 0x0f, 0x8c, 0xdf, 0xdf, 0x27,
+       0xf7, 0xe1, 0x09, 0xb1, 0x0f, 0x74, 0x91, 0x7e, 0x61, 0x20, 0x4f, 0xac,
+       0xea, 0xe0, 0xf1, 0x4f, 0x90, 0x8f, 0x8c, 0xcd, 0x72, 0x6f, 0xc6, 0xf5,
+       0xcb, 0xfc, 0xa5, 0xaa, 0xc8, 0xbd, 0x14, 0x37, 0xf1, 0x42, 0x96, 0x83,
+       0xbe, 0x83, 0xf9, 0xd2, 0xfa, 0x81, 0x1f, 0xac, 0x56, 0x08, 0xce, 0x5d,
+       0xfc, 0x70, 0xcf, 0xe0, 0xfe, 0xe8, 0xf3, 0xdf, 0xbb, 0x5b, 0xff, 0xd9,
+       0xf9, 0xbe, 0xdf, 0x64, 0x25, 0x06, 0xf2, 0xa7, 0x82, 0xf2, 0xa6, 0x5e,
+       0xc0, 0x79, 0xc8, 0x75, 0xcb, 0x79, 0x04, 0xfa, 0xb9, 0x3c, 0x5e, 0x4b,
+       0x7f, 0x52, 0xc0, 0xdf, 0xb5, 0x36, 0x15, 0xe9, 0x44, 0xde, 0x4f, 0x9b,
+       0xaf, 0x2a, 0xb3, 0x26, 0x86, 0xf8, 0xfe, 0x03, 0xb1, 0x6f, 0x55, 0x49,
+       0xe5, 0x7b, 0x71, 0x1d, 0x4b, 0x6a, 0xb9, 0xbf, 0xad, 0xd3, 0x1e, 0x57,
+       0x36, 0xfc, 0xf8, 0x63, 0xdc, 0xaf, 0x83, 0x56, 0xe2, 0x73, 0xdd, 0x7d,
+       0xaf, 0x5f, 0x67, 0xd5, 0x6b, 0x07, 0x09, 0x1e, 0xb0, 0xce, 0x99, 0xb8,
+       0xbe, 0xa0, 0x75, 0xbe, 0x9b, 0x15, 0xe4, 0x17, 0x3c, 0xbb, 0xe7, 0xc3,
+       0xdf, 0x20, 0xa8, 0xaf, 0x77, 0x7d, 0xd7, 0x9a, 0xc7, 0x6c, 0xee, 0xc1,
+       0xef, 0x43, 0xec, 0xea, 0x8f, 0x86, 0x0d, 0x0d, 0xd2, 0xa3, 0xcc, 0xf2,
+       0xfb, 0xfe, 0xda, 0x7b, 0xc6, 0xcc, 0xf8, 0xf7, 0x10, 0x60, 0xbc, 0x46,
+       0x61, 0x7f, 0x34, 0x0a, 0xfb, 0xa3, 0x29, 0x4c, 0xfc, 0xbd, 0x1a, 0x9d,
+       0x3d, 0xda, 0xe8, 0xe3, 0xf1, 0x3c, 0x8d, 0xf1, 0x26, 0x8a, 0xd7, 0x61,
+       0xe2, 0xef, 0x2b, 0x48, 0xf9, 0xbb, 0xe2, 0x3d, 0x1e, 0xdf, 0xb3, 0x22,
+       0x91, 0xd1, 0x7b, 0x9c, 0x1f, 0xd2, 0x81, 0xe2, 0xdf, 0x4f, 0xf2, 0xa0,
+       0xf3, 0xbe, 0x28, 0x05, 0xe4, 0x1c, 0xe0, 0xc3, 0x19, 0xbb, 0xfb, 0x02,
+       0xc2, 0x8f, 0xb9, 0x97, 0x93, 0x7c, 0x50, 0x6f, 0xb0, 0x3a, 0x11, 0x9f,
+       0x77, 0xbd, 0x7d, 0xb3, 0xb0, 0xab, 0xb8, 0xbc, 0x29, 0x12, 0xf2, 0xa5,
+       0x08, 0xfb, 0xc1, 0x75, 0x64, 0xf5, 0x24, 0xb9, 0x53, 0x28, 0xc6, 0x1d,
+       0x6c, 0xa9, 0x25, 0xbd, 0x76, 0x08, 0xf3, 0x08, 0x3f, 0x8b, 0xf0, 0x47,
+       0x3c, 0xb0, 0x5f, 0x63, 0x8f, 0xfd, 0x5f, 0x0d, 0xf6, 0x2d, 0x39, 0x10,
+       0x68, 0x00, 0x00, 0x00
+};
+
+static const u8 usem_int_table_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51,
+       0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0xd7, 0x98, 0x33, 0x30, 0x38, 0x5a, 0x31,
+       0x30, 0xe4, 0x59, 0x33, 0x30, 0x5c, 0x07, 0xe2, 0x30, 0x73, 0x84, 0xdc,
+       0x4b, 0x71, 0x04, 0x9b, 0x9a, 0xf8, 0xa7, 0x3c, 0x65, 0xfa, 0x37, 0x48,
+       0x32, 0x30, 0x6c, 0x02, 0xe2, 0x2d, 0x40, 0xbc, 0x4d, 0x92, 0x74, 0xfd,
+       0xb7, 0xb4, 0x10, 0xec, 0xbd, 0xaa, 0x0c, 0x0c, 0xb7, 0x81, 0xfc, 0x6e,
+       0x20, 0xfd, 0x5d, 0x9d, 0x81, 0x61, 0x17, 0x90, 0x7d, 0x07, 0x88, 0x2f,
+       0x83, 0xf8, 0x40, 0xcc, 0xac, 0xc6, 0xc0, 0x20, 0x0e, 0xe4, 0xab, 0x00,
+       0x69, 0x3f, 0x20, 0xd6, 0x07, 0xe2, 0xbb, 0x40, 0x7e, 0x9a, 0x1a, 0x6e,
+       0xf3, 0xef, 0x69, 0xe1, 0xb7, 0x7f, 0x9b, 0x06, 0x2a, 0xff, 0x1d, 0x1a,
+       0xff, 0x92, 0x3a, 0x7e, 0xfd, 0x99, 0x9a, 0xf8, 0xe5, 0xdf, 0x11, 0x90,
+       0xc7, 0x86, 0x1f, 0xdb, 0x91, 0x1f, 0x1f, 0xea, 0xf6, 0xb4, 0x49, 0x27,
+       0xb4, 0xc2, 0x07, 0xd0, 0xd2, 0xf5, 0x4e, 0x13, 0x06, 0x86, 0x0b, 0xa6,
+       0x0c, 0x0c, 0x22, 0xd0, 0xb4, 0xbf, 0x17, 0x49, 0x5e, 0x0d, 0x28, 0xb6,
+       0xcb, 0x04, 0xc2, 0x9e, 0xab, 0x07, 0x4c, 0x7b, 0x66, 0x40, 0x3e, 0x8e,
+       0x7c, 0x31, 0x0f, 0x28, 0xbf, 0x11, 0x28, 0x6f, 0x64, 0x8e, 0xdf, 0x7e,
+       0x05, 0x66, 0x54, 0xbe, 0x00, 0x2f, 0xa6, 0x9a, 0x6f, 0x4c, 0x08, 0xf6,
+       0x04, 0x21, 0x54, 0xb9, 0xc3, 0xc2, 0x98, 0xea, 0xb9, 0x44, 0x19, 0x18,
+       0x00, 0x65, 0x83, 0x84, 0x86, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 usem_pram_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d,
+       0x0d, 0x78, 0x54, 0xd5, 0xb5, 0xf6, 0x3e, 0x73, 0xce, 0x9c, 0x99, 0x64,
+       0x4e, 0x26, 0x93, 0x10, 0xc2, 0x40, 0x02, 0x4e, 0x7e, 0xd0, 0xa8, 0x09,
+       0x8e, 0x10, 0x30, 0x26, 0x13, 0x72, 0x26, 0x3f, 0x24, 0x24, 0x01, 0xc3,
+       0x4f, 0x69, 0x5a, 0x69, 0x9d, 0xa0, 0x45, 0xda, 0x82, 0x22, 0xda, 0x5e,
+       0x6f, 0x2f, 0x5f, 0x19, 0x7e, 0x1a, 0x22, 0x45, 0xc5, 0x16, 0xad, 0xda,
+       0xde, 0xde, 0x81, 0x2a, 0x4f, 0xdb, 0xeb, 0x73, 0x9f, 0x60, 0xa9, 0xe5,
+       0x86, 0x44, 0x26, 0x10, 0x10, 0x0d, 0x3f, 0x11, 0xad, 0xde, 0x7e, 0xb6,
+       0xdf, 0x8d, 0xda, 0x8b, 0xa1, 0x0d, 0x38, 0xc1, 0x60, 0xe9, 0xf7, 0x60,
+       0xf9, 0xf6, 0x5a, 0x7b, 0xef, 0xcc, 0x9c, 0x93, 0x99, 0x04, 0xd4, 0xef,
+       0xde, 0xef, 0x07, 0x1f, 0x9f, 0x93, 0x73, 0xce, 0x3e, 0x7b, 0xaf, 0xbd,
+       0xf6, 0x5a, 0x6b, 0xbf, 0x6b, 0xed, 0xb5, 0xf7, 0x58, 0xc9, 0x44, 0xe2,
+       0xaa, 0x20, 0xe4, 0x0a, 0xfc, 0xa3, 0x57, 0xdf, 0x64, 0x42, 0xe8, 0xa3,
+       0x91, 0xab, 0x78, 0x5e, 0x69, 0x27, 0x41, 0xc7, 0x2d, 0x84, 0xa4, 0xd9,
+       0xf7, 0xf6, 0xce, 0xc8, 0x20, 0x64, 0x9e, 0x26, 0x7b, 0x6b, 0x3d, 0x84,
+       0x4c, 0xb2, 0xb7, 0xf4, 0x90, 0x62, 0x42, 0xca, 0x89, 0xcd, 0x63, 0xcb,
+       0x21, 0xa4, 0x5b, 0xfa, 0x4d, 0xef, 0x0c, 0x7a, 0x7f, 0x34, 0xc5, 0xea,
+       0xb5, 0x11, 0xf8, 0xf7, 0x00, 0x21, 0x73, 0x08, 0x59, 0x67, 0xa7, 0x7f,
+       0xd2, 0xf2, 0x47, 0x2f, 0xd2, 0x2b, 0xfd, 0xfe, 0xe8, 0x5f, 0x2d, 0x21,
+       0x22, 0x11, 0x52, 0x23, 0x37, 0x12, 0x09, 0xbe, 0xb7, 0x4b, 0xbc, 0xbc,
+       0xae, 0x2d, 0xc8, 0x24, 0xa4, 0x9a, 0xb0, 0x7f, 0x73, 0x2f, 0x92, 0x6a,
+       0x5a, 0x8c, 0x54, 0xbb, 0xef, 0x6d, 0x24, 0x33, 0x08, 0xa9, 0x72, 0xd1,
+       0x52, 0x76, 0xf6, 0xee, 0x0a, 0x2b, 0x4f, 0x08, 0x2d, 0x5f, 0x46, 0x58,
+       0xfd, 0xba, 0xdd, 0xf8, 0xbe, 0x8c, 0x6c, 0x1f, 0x92, 0x9d, 0x70, 0x17,
+       0x91, 0x9b, 0x8a, 0x68, 0x7d, 0x97, 0x55, 0xe3, 0x7b, 0x77, 0xed, 0x07,
+       0xc4, 0x09, 0xe5, 0x62, 0x9e, 0x43, 0x3f, 0xe0, 0x0f, 0xca, 0x83, 0xeb,
+       0x49, 0x4a, 0xc6, 0x19, 0x07, 0xfd, 0xfb, 0x36, 0x72, 0xdb, 0x15, 0x99,
+       0x5e, 0x95, 0x09, 0x84, 0xdc, 0x1e, 0xe5, 0x8b, 0xf9, 0x4a, 0x48, 0x10,
+       0xf9, 0xd6, 0xc1, 0xbf, 0x57, 0x48, 0xd3, 0x0c, 0xb8, 0x27, 0xe4, 0x45,
+       0x6c, 0x3f, 0x5d, 0xf0, 0xb1, 0xae, 0x9f, 0xb8, 0x69, 0xbf, 0x33, 0x4a,
+       0x88, 0xb7, 0x96, 0x76, 0x70, 0x52, 0x9d, 0xde, 0x0d, 0x7c, 0x29, 0xab,
+       0x56, 0x3d, 0x36, 0x7a, 0xdf, 0x5d, 0x33, 0x67, 0x72, 0xbf, 0x46, 0xc8,
+       0x0f, 0xcf, 0xb5, 0x67, 0x91, 0x42, 0xfa, 0x79, 0x68, 0x35, 0xf2, 0x31,
+       0x83, 0xf3, 0xb1, 0xfb, 0xdc, 0x4b, 0xef, 0xdc, 0x47, 0xbf, 0xf7, 0xd5,
+       0x11, 0xaf, 0x8d, 0xde, 0x1f, 0xb0, 0x7a, 0x27, 0x37, 0x15, 0x8e, 0xa6,
+       0xc7, 0x57, 0x97, 0x9e, 0x44, 0x68, 0x3d, 0x4f, 0x34, 0x1d, 0x72, 0x60,
+       0x3d, 0x84, 0xfc, 0xed, 0x4a, 0x26, 0xaf, 0x27, 0x8f, 0x90, 0xce, 0xa6,
+       0xdc, 0xd4, 0x40, 0x9c, 0xef, 0xc4, 0xf5, 0xf1, 0x0d, 0x2e, 0x42, 0x6c,
+       0xd1, 0xfb, 0x1d, 0x3a, 0xa9, 0x6b, 0xd7, 0x46, 0x97, 0x7b, 0x09, 0x06,
+       0x73, 0x36, 0x54, 0xbf, 0x1c, 0xe9, 0x2c, 0xe3, 0xbc, 0xfc, 0xa1, 0x44,
+       0x9a, 0xdb, 0xb1, 0xdd, 0x66, 0x1c, 0xa7, 0x03, 0x9c, 0xfe, 0x1e, 0xfd,
+       0x90, 0xa3, 0xbf, 0x10, 0xde, 0x87, 0x1d, 0x16, 0xda, 0x8f, 0xe0, 0x90,
+       0x85, 0x3c, 0x4f, 0xab, 0xe8, 0x1c, 0xac, 0x4c, 0x06, 0x7a, 0x37, 0xe9,
+       0x96, 0x30, 0x3c, 0xef, 0x1c, 0x54, 0x43, 0xc0, 0x0f, 0xe2, 0x6e, 0xcf,
+       0x5a, 0x54, 0x34, 0x9a, 0xfe, 0x03, 0x43, 0x2b, 0x66, 0x62, 0xbf, 0x02,
+       0xab, 0x0d, 0xed, 0xfe, 0x60, 0x90, 0xf6, 0x57, 0x83, 0xfe, 0xbd, 0xe8,
+       0x98, 0x47, 0xeb, 0xb9, 0x30, 0x68, 0x71, 0xc9, 0x74, 0x5c, 0x9f, 0xe0,
+       0xcf, 0x0f, 0x04, 0xda, 0x1d, 0x2e, 0xf8, 0x6e, 0x20, 0x1d, 0xc7, 0xf3,
+       0xf1, 0x0d, 0xf4, 0xef, 0x1b, 0x12, 0xf3, 0xe3, 0xf1, 0xb9, 0xdf, 0xc8,
+       0x0d, 0x68, 0x50, 0xce, 0x6e, 0xe4, 0xc7, 0xe0, 0x85, 0x63, 0x79, 0x74,
+       0xdc, 0x3a, 0x77, 0x2a, 0x5e, 0xe8, 0xd7, 0x78, 0xfc, 0xfc, 0x01, 0x6f,
+       0x47, 0xdc, 0xa7, 0x7b, 0xc3, 0x55, 0x2e, 0x5a, 0xaf, 0x2f, 0xe2, 0x95,
+       0x40, 0x8f, 0xd2, 0x07, 0x09, 0x99, 0x90, 0x03, 0x7a, 0xd1, 0x79, 0xd8,
+       0x09, 0xe3, 0xdb, 0x48, 0x50, 0x2f, 0x7c, 0x4d, 0x95, 0x49, 0xd3, 0x59,
+       0x3f, 0xbc, 0xb2, 0x07, 0xde, 0x1f, 0x97, 0x41, 0x3e, 0x7c, 0xae, 0x30,
+       0xf6, 0x63, 0x84, 0x1e, 0xa0, 0xef, 0x06, 0xa0, 0xd3, 0x8d, 0xd7, 0xa7,
+       0x79, 0x7b, 0x4f, 0xc1, 0x38, 0x62, 0xff, 0x36, 0x25, 0x5d, 0x4f, 0xe9,
+       0xbd, 0x50, 0xa2, 0x60, 0x3d, 0xbb, 0xf5, 0x4d, 0x7e, 0x05, 0xeb, 0xbb,
+       0x1c, 0x96, 0x41, 0x1e, 0x57, 0x33, 0x79, 0xca, 0xf0, 0x04, 0x36, 0x5a,
+       0x81, 0xff, 0xf7, 0x10, 0x6f, 0xd0, 0x03, 0xf5, 0x12, 0xec, 0xf7, 0x4f,
+       0x79, 0xff, 0x7f, 0xc2, 0xeb, 0x13, 0xed, 0x74, 0x0e, 0xa6, 0xfb, 0x15,
+       0xa0, 0xaf, 0x99, 0x78, 0x41, 0x4d, 0x6a, 0xe4, 0xf5, 0xdd, 0xf0, 0xbd,
+       0x6f, 0x15, 0xa3, 0x7f, 0xda, 0xc3, 0x6b, 0x25, 0xe0, 0xdf, 0x75, 0xeb,
+       0xfb, 0xf1, 0x1a, 0xe2, 0x74, 0xee, 0x80, 0xef, 0x69, 0x81, 0xec, 0xb5,
+       0x11, 0x09, 0xf8, 0x36, 0xf5, 0xa1, 0x30, 0x5e, 0x77, 0x6e, 0xfc, 0x7d,
+       0x37, 0xd0, 0x97, 0xba, 0x85, 0x24, 0x81, 0x2d, 0x78, 0xa2, 0xda, 0x92,
+       0x06, 0xdf, 0x3d, 0x31, 0x6f, 0x4a, 0x12, 0xbc, 0x77, 0x36, 0x51, 0xc5,
+       0xa7, 0xf6, 0xc0, 0xe7, 0x75, 0x3d, 0xd0, 0x43, 0xfb, 0xb3, 0xb3, 0x5a,
+       0x41, 0x3a, 0x77, 0x0e, 0x52, 0xfe, 0xd3, 0x72, 0xce, 0xa0, 0xcb, 0x0b,
+       0x7a, 0xed, 0x0c, 0x7a, 0xf8, 0xd5, 0xeb, 0x85, 0xf2, 0x07, 0x39, 0x3f,
+       0x0e, 0xf0, 0x76, 0xbb, 0x38, 0x1d, 0xce, 0xa0, 0xce, 0xcb, 0xad, 0x2d,
+       0x84, 0x72, 0xce, 0x60, 0x10, 0xaf, 0x21, 0xde, 0x4f, 0xe2, 0x59, 0x83,
+       0x72, 0xb7, 0x8e, 0xcb, 0xdd, 0x41, 0x6b, 0xe0, 0x26, 0xe0, 0x7b, 0xc6,
+       0x20, 0x71, 0x13, 0xaa, 0xcf, 0x07, 0xce, 0xd7, 0x4f, 0x86, 0x76, 0x45,
+       0xfd, 0xe6, 0xf2, 0x7b, 0x9e, 0xfd, 0x9f, 0xb3, 0xe0, 0xfd, 0xc4, 0x41,
+       0xf2, 0xae, 0x75, 0x06, 0x5c, 0xc3, 0x2d, 0xd0, 0xde, 0x0d, 0xd0, 0x0f,
+       0x27, 0xdc, 0xf7, 0xb5, 0x48, 0x68, 0xa7, 0x42, 0xa8, 0x47, 0xfa, 0x65,
+       0x0b, 0x21, 0x05, 0x51, 0x3b, 0x95, 0x71, 0xa9, 0x69, 0xfe, 0x1d, 0x1e,
+       0xb8, 0xab, 0x41, 0x3d, 0x12, 0x76, 0xa0, 0x6c, 0x50, 0xb5, 0x48, 0xa9,
+       0xb1, 0x7a, 0x56, 0x8d, 0x7a, 0xb0, 0x93, 0xeb, 0x41, 0xf5, 0x60, 0x18,
+       0xe5, 0x84, 0xea, 0xd9, 0x61, 0x0b, 0xe5, 0x53, 0xf0, 0x1c, 0xd5, 0x33,
+       0x2a, 0x5f, 0x07, 0x9a, 0x2c, 0x38, 0xde, 0xcf, 0x45, 0x54, 0xb4, 0xc3,
+       0xa4, 0x20, 0x9c, 0xb5, 0x28, 0x65, 0xb4, 0x1e, 0x75, 0x0e, 0xad, 0x9c,
+       0x09, 0xfc, 0x16, 0xfa, 0x34, 0xda, 0x7e, 0xfc, 0xbf, 0xa1, 0x5f, 0x3b,
+       0x69, 0x3f, 0x02, 0x71, 0xec, 0x9a, 0x68, 0x4f, 0xe8, 0x9b, 0xf9, 0xfd,
+       0xb8, 0xfa, 0xe6, 0x0a, 0xa2, 0xbe, 0x75, 0x52, 0x7d, 0x0b, 0x02, 0x3f,
+       0x9b, 0x2c, 0x49, 0xf9, 0xa0, 0x7f, 0x6d, 0x16, 0xd4, 0x13, 0x77, 0x75,
+       0x7b, 0x37, 0xd3, 0x97, 0xd5, 0xa8, 0x6f, 0x19, 0xf7, 0x30, 0x7a, 0x26,
+       0x2d, 0x0f, 0xa1, 0x1e, 0x8c, 0xa7, 0x77, 0x3b, 0x3d, 0x2e, 0xbf, 0x02,
+       0xf5, 0x37, 0x33, 0x3d, 0xed, 0x1c, 0x7c, 0x6f, 0xa3, 0x0d, 0xc6, 0x63,
+       0x39, 0xe1, 0x76, 0xe2, 0x72, 0x37, 0xdc, 0xfb, 0x1e, 0x66, 0x7a, 0x6d,
+       0xd6, 0x33, 0xb3, 0x1e, 0xa6, 0xfa, 0xfa, 0x50, 0x3f, 0x73, 0xb6, 0x44,
+       0x08, 0x5c, 0x3d, 0x9b, 0x1b, 0x51, 0xae, 0x69, 0x2b, 0x49, 0xa8, 0x7f,
+       0x09, 0xf4, 0xb0, 0x13, 0xf4, 0xb0, 0xf8, 0xff, 0x1f, 0x3d, 0xac, 0x82,
+       0x79, 0x9c, 0xea, 0x5d, 0x9a, 0x76, 0x6b, 0x8f, 0x8b, 0xf6, 0x7b, 0x7e,
+       0x84, 0x30, 0x3c, 0xa4, 0x3d, 0xd1, 0x03, 0xf3, 0x78, 0x4d, 0xb6, 0x8d,
+       0xcd, 0xe3, 0x53, 0xdf, 0xbe, 0xf3, 0x7e, 0x7a, 0x7f, 0xcc, 0xea, 0x40,
+       0xfe, 0x1f, 0x9b, 0x48, 0x1f, 0x16, 0xc3, 0xbd, 0x8c, 0x7a, 0xd7, 0x9d,
+       0xb3, 0x35, 0x7b, 0x1d, 0x7d, 0x3f, 0x3f, 0x43, 0xc2, 0xf7, 0x84, 0xac,
+       0x42, 0xfd, 0xae, 0x15, 0x78, 0x09, 0x1e, 0x51, 0xfd, 0xf1, 0xf7, 0x4b,
+       0x64, 0x4e, 0x3a, 0x94, 0x7b, 0x7f, 0x47, 0x15, 0xfd, 0xfe, 0xd5, 0x01,
+       0xe2, 0x85, 0x57, 0xaf, 0x66, 0xcb, 0x58, 0xdf, 0xe1, 0x41, 0xc2, 0xf4,
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+       0x02, 0xfd, 0xac, 0x00, 0x48, 0x42, 0x9f, 0x7f, 0x7c, 0x36, 0x32, 0xcd,
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+       0xf2, 0x3f, 0x9a, 0x46, 0x28, 0xab, 0xef, 0xcf, 0xfb, 0xcb, 0x19, 0xb8,
+       0x12, 0x12, 0xb6, 0x02, 0x5e, 0x32, 0xd7, 0x23, 0xbe, 0x7f, 0xd5, 0x1d,
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+       0xaf, 0xf5, 0x52, 0x3a, 0xd6, 0x5f, 0x36, 0xf0, 0xe9, 0xf8, 0x65, 0xb6,
+       0x2b, 0xa2, 0xde, 0x2e, 0xe0, 0x63, 0xe1, 0x68, 0xba, 0x08, 0x08, 0xb5,
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+       0x80, 0x37, 0xbc, 0x3f, 0x43, 0x3f, 0xf1, 0x42, 0xb1, 0xcd, 0x03, 0x76,
+       0x68, 0x92, 0xe7, 0x09, 0xa5, 0x3f, 0x46, 0xde, 0xea, 0xf9, 0xf7, 0x23,
+       0x7c, 0xdc, 0xa0, 0x63, 0x3f, 0xbb, 0x67, 0xbf, 0x9d, 0x05, 0xe5, 0xba,
+       0xa6, 0x6f, 0xcc, 0x86, 0x71, 0x98, 0xef, 0x79, 0xdb, 0xb1, 0x8e, 0xf2,
+       0xff, 0x28, 0xd7, 0x9b, 0x8e, 0x0d, 0x75, 0x58, 0xae, 0xec, 0x12, 0x79,
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+       0xf5, 0xcd, 0x0d, 0xab, 0xf0, 0x7a, 0x7a, 0xc3, 0x5a, 0xbc, 0xbe, 0x7a,
+       0xe9, 0x45, 0x0d, 0xc6, 0xaf, 0xb7, 0x20, 0x0f, 0xe7, 0xaf, 0x3a, 0xa5,
+       0x5d, 0x89, 0xe7, 0x57, 0x95, 0x0e, 0x1a, 0xe5, 0xe6, 0x65, 0x0f, 0xc5,
+       0x3b, 0xb4, 0x7c, 0xc3, 0xe0, 0x8a, 0xed, 0xb7, 0xd2, 0x7e, 0x1f, 0xbf,
+       0x64, 0x41, 0xfb, 0x7c, 0xbc, 0x20, 0x6f, 0x4c, 0xbc, 0x22, 0xec, 0x87,
+       0x28, 0xf7, 0x8a, 0xfb, 0x67, 0x55, 0xc0, 0xb7, 0xc6, 0x01, 0x4a, 0x6e,
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+       0x1c, 0x38, 0x97, 0x59, 0x04, 0xf5, 0x1e, 0x90, 0xfe, 0xb0, 0x64, 0x96,
+       0x27, 0x31, 0x1d, 0x65, 0xbe, 0x3e, 0xec, 0xe7, 0x82, 0xf0, 0xef, 0x14,
+       0x4f, 0x4a, 0xe2, 0x72, 0x27, 0x94, 0xbe, 0xc6, 0x59, 0xe8, 0xa7, 0x32,
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+       0xa2, 0x5c, 0x0c, 0x2b, 0x16, 0x90, 0x8b, 0xc6, 0xc2, 0xbd, 0x7c, 0x7c,
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+       0x67, 0x19, 0x97, 0xcf, 0x13, 0x30, 0xee, 0x20, 0xc7, 0x21, 0x19, 0xe7,
+       0x3f, 0x81, 0x97, 0x45, 0x7d, 0x5d, 0x97, 0x72, 0x1f, 0x2d, 0xa6, 0xed,
+       0x9d, 0x08, 0x59, 0xe3, 0x7e, 0xdf, 0x54, 0x6d, 0xd4, 0xc7, 0x3b, 0xdc,
+       0x0e, 0xc3, 0x7d, 0x75, 0xf6, 0x04, 0xc3, 0xfd, 0x89, 0xc1, 0x99, 0x6f,
+       0x36, 0x41, 0x7b, 0x94, 0x7e, 0xc0, 0x73, 0x24, 0xb8, 0xda, 0x40, 0x7f,
+       0x17, 0xd8, 0x7b, 0x68, 0xcf, 0x25, 0xe1, 0xfc, 0x7f, 0xf4, 0x72, 0xf5,
+       0xe0, 0xfd, 0x50, 0x2e, 0x64, 0xa4, 0xcb, 0x4c, 0x47, 0xef, 0xa5, 0xdc,
+       0x27, 0x97, 0xd2, 0x7a, 0x8f, 0xef, 0x93, 0x51, 0x4e, 0xab, 0xdd, 0x46,
+       0xba, 0xaa, 0x2e, 0xbe, 0x79, 0x1c, 0xe2, 0x38, 0x0d, 0xd4, 0xbe, 0x00,
+       0xdf, 0x5e, 0xd6, 0x15, 0x1d, 0xfa, 0x7d, 0x62, 0x5f, 0x4a, 0x68, 0x23,
+       0x95, 0xcb, 0x97, 0x0b, 0x5f, 0x77, 0x00, 0x6e, 0xa0, 0xff, 0xb4, 0x05,
+       0xb4, 0x9d, 0x2a, 0xc2, 0xc6, 0xb7, 0x32, 0xc3, 0x58, 0xcf, 0xf1, 0xc1,
+       0xf7, 0xbe, 0x0f, 0x76, 0xea, 0x82, 0x5d, 0x46, 0x3b, 0x57, 0xf9, 0xd7,
+       0x43, 0x5b, 0x00, 0x5e, 0x9d, 0x2a, 0x7e, 0xb0, 0x07, 0xf8, 0x7c, 0x80,
+       0x48, 0xc8, 0xa7, 0xf2, 0x73, 0xbb, 0x65, 0xa8, 0x6f, 0x59, 0xc8, 0xf8,
+       0xfd, 0xd2, 0xe5, 0x46, 0xfe, 0xac, 0x59, 0x3a, 0xc1, 0x64, 0xff, 0x8d,
+       0xf1, 0xa5, 0x2a, 0x0f, 0x8b, 0x13, 0xcd, 0xf5, 0x0e, 0x61, 0x7d, 0xa5,
+       0x10, 0xff, 0xa1, 0xf7, 0x95, 0x9a, 0x31, 0x2e, 0x34, 0x17, 0x8c, 0x41,
+       0x4c, 0xbd, 0xe5, 0xa6, 0xb8, 0x50, 0xa9, 0x87, 0xc5, 0x85, 0x4a, 0x21,
+       0x2e, 0x24, 0xca, 0xe5, 0x90, 0x51, 0x76, 0x9f, 0xde, 0x63, 0xfb, 0xe6,
+       0x79, 0xdd, 0xac, 0xdf, 0x09, 0xf5, 0xdf, 0x42, 0x56, 0x41, 0x3c, 0x85,
+       0x44, 0x16, 0x8f, 0x83, 0x5b, 0x36, 0xf1, 0xf8, 0x8a, 0xd1, 0xde, 0x12,
+       0x65, 0xa7, 0x04, 0xf2, 0x50, 0xca, 0xdb, 0xef, 0xb0, 0xb6, 0x3b, 0x80,
+       0x2e, 0xdf, 0xad, 0xcc, 0x7e, 0x91, 0x48, 0x7a, 0xdc, 0x78, 0x95, 0xd9,
+       0x8e, 0x10, 0xf2, 0x20, 0xca, 0x95, 0xe0, 0x23, 0x71, 0x05, 0x49, 0xc6,
+       0x1c, 0xe8, 0x3f, 0x2f, 0x63, 0xb6, 0x7f, 0x9c, 0x2f, 0x6d, 0x74, 0x38,
+       0xae, 0xe0, 0x3c, 0x10, 0xe4, 0xf8, 0xc5, 0x13, 0x57, 0xdf, 0xcd, 0xdf,
+       0x67, 0x73, 0x7d, 0x9f, 0x37, 0x40, 0xed, 0x66, 0x06, 0x8c, 0x97, 0xec,
+       0x02, 0xbb, 0x71, 0xfc, 0x12, 0xd1, 0x40, 0x1f, 0x4f, 0x51, 0x79, 0x67,
+       0x2d, 0xf7, 0x5f, 0x89, 0x95, 0xdb, 0x86, 0x81, 0x76, 0x94, 0x4b, 0x5a,
+       0x1e, 0x46, 0x90, 0x96, 0xf7, 0xa2, 0xfe, 0x36, 0x4d, 0x66, 0xfa, 0xdb,
+       0x9d, 0x53, 0xab, 0xa4, 0x31, 0xfb, 0x19, 0x57, 0xdf, 0xcd, 0x7a, 0x30,
+       0x40, 0x82, 0x4f, 0x15, 0xd3, 0x71, 0x3d, 0x9e, 0x9f, 0xf7, 0xe4, 0x52,
+       0xfa, 0x5d, 0xef, 0x3e, 0x61, 0x07, 0x2c, 0x3a, 0xea, 0xd5, 0x3e, 0x86,
+       0x7b, 0x4f, 0x0c, 0xae, 0x43, 0x79, 0xbd, 0x40, 0xe5, 0x15, 0xd8, 0x3e,
+       0x5a, 0xef, 0x4f, 0x6b, 0xb1, 0xf3, 0xfe, 0x7f, 0x96, 0xbe, 0x9b, 0xf5,
+       0x7c, 0x44, 0xff, 0x47, 0xe9, 0x3b, 0xb3, 0x5b, 0xc7, 0x87, 0x2d, 0xd8,
+       0x9f, 0xaa, 0x8b, 0x0a, 0xd6, 0xd3, 0x70, 0x99, 0xe0, 0x3c, 0x6e, 0xd6,
+       0xff, 0x13, 0xdc, 0x7f, 0x7b, 0x59, 0x7f, 0x53, 0xf3, 0xc2, 0x7c, 0x58,
+       0xf8, 0x3e, 0xfa, 0xc7, 0xe4, 0x53, 0xeb, 0x3b, 0xf3, 0x43, 0x0e, 0x0c,
+       0x10, 0x6c, 0xbf, 0xfc, 0xdc, 0x7b, 0x32, 0xed, 0xf9, 0xe7, 0xa6, 0xef,
+       0x42, 0xcf, 0x85, 0xde, 0x5e, 0xb3, 0xbe, 0xff, 0x27, 0xe9, 0xb9, 0xf9,
+       0xf9, 0xb7, 0x2d, 0x1c, 0xf7, 0x27, 0xd0, 0xd3, 0xa8, 0xfe, 0x07, 0xb1,
+       0xdc, 0xe6, 0x14, 0x52, 0x00, 0x71, 0xb6, 0x0e, 0x29, 0xd9, 0xbb, 0x29,
+       0x07, 0xf4, 0x9d, 0xc5, 0x7d, 0xcc, 0xe5, 0x27, 0xc8, 0x22, 0x1e, 0x6b,
+       0x0f, 0xfe, 0x91, 0xf6, 0xab, 0x85, 0x0a, 0x4b, 0x2a, 0x65, 0xf5, 0x1a,
+       0xd2, 0x3f, 0x0d, 0xe4, 0x61, 0xe2, 0x64, 0x0f, 0xd6, 0x77, 0x9f, 0xa5,
+       0x3f, 0x13, 0xee, 0x3f, 0x24, 0x91, 0xcc, 0x9b, 0x65, 0xc0, 0xcf, 0x64,
+       0x3f, 0xcc, 0xbf, 0x92, 0x4e, 0xc8, 0xc3, 0x94, 0x24, 0xc9, 0xe3, 0x22,
+       0xcb, 0x67, 0x12, 0xf2, 0xb8, 0x1c, 0xb0, 0xcb, 0xb4, 0x3e, 0x69, 0x20,
+       0xfc, 0x57, 0x89, 0xf2, 0x99, 0x3c, 0x44, 0x3c, 0x80, 0x07, 0x6f, 0x90,
+       0x02, 0x0e, 0x78, 0x6e, 0xa3, 0x7c, 0xd2, 0x68, 0x79, 0xa2, 0x9c, 0x46,
+       0x9c, 0x48, 0xfd, 0x37, 0xe4, 0xd7, 0x42, 0xae, 0x74, 0x0b, 0xed, 0x5a,
+       0x18, 0xe3, 0xf0, 0x25, 0xd6, 0xc1, 0x7e, 0xc1, 0x77, 0x9c, 0x3f, 0x96,
+       0xbb, 0xce, 0xdc, 0x4c, 0xeb, 0x25, 0x61, 0xe9, 0xca, 0xcd, 0xd1, 0x7e,
+       0xee, 0xb1, 0x86, 0xb2, 0xbc, 0x1a, 0xf4, 0x33, 0xf4, 0xe3, 0xfb, 0x20,
+       0x6e, 0xf5, 0x8c, 0xea, 0x7d, 0x3e, 0x0e, 0xdf, 0x2d, 0x9f, 0xb2, 0x9f,
+       0x60, 0x7e, 0x90, 0x9f, 0x16, 0xc6, 0xcf, 0xa0, 0x25, 0xd9, 0xfb, 0x7c,
+       0x1c, 0xbc, 0x35, 0xff, 0xda, 0xeb, 0x7f, 0x2b, 0x99, 0x5e, 0xcb, 0x80,
+       0x8f, 0xb7, 0x8c, 0xe6, 0xa3, 0x34, 0x48, 0xf9, 0x07, 0x7c, 0x50, 0xfe,
+       0x76, 0x05, 0xfc, 0xc4, 0x32, 0x37, 0x93, 0x2f, 0xf9, 0x43, 0x55, 0x87,
+       0x38, 0x0d, 0x91, 0xed, 0xa1, 0xe9, 0x71, 0xe8, 0x58, 0xc3, 0xe9, 0x78,
+       0x5c, 0xd6, 0x6f, 0xa3, 0xc8, 0x86, 0xc8, 0x55, 0xed, 0xc8, 0x9f, 0x03,
+       0x30, 0xfe, 0x1a, 0xf0, 0x2f, 0x83, 0x7c, 0x3b, 0x46, 0xbe, 0xe6, 0xc9,
+       0x2a, 0xd2, 0x25, 0x37, 0x90, 0xb5, 0x38, 0xbf, 0x90, 0xb0, 0x05, 0xec,
+       0xc8, 0x78, 0xe3, 0x61, 0x55, 0x88, 0x22, 0xc3, 0x38, 0xf6, 0x5d, 0x41,
+       0xbb, 0xdb, 0xca, 0xe9, 0xb3, 0xd1, 0xe7, 0xda, 0xcc, 0xc4, 0xe3, 0x25,
+       0x37, 0x78, 0x23, 0x61, 0x3a, 0x4e, 0xe4, 0x43, 0x36, 0x4e, 0x07, 0xe6,
+       0x1b, 0xe5, 0x72, 0x3d, 0xa7, 0xff, 0x41, 0x4e, 0x17, 0x98, 0x27, 0xa8,
+       0xbf, 0x14, 0xea, 0xa7, 0xfc, 0x92, 0xff, 0xac, 0xae, 0x8d, 0x37, 0x4f,
+       0x6c, 0x17, 0xfc, 0xe7, 0xfc, 0x32, 0x97, 0x3f, 0xf0, 0x25, 0xd6, 0x7f,
+       0x51, 0x7e, 0xab, 0xcc, 0xf4, 0x29, 0x78, 0xed, 0xe3, 0xb6, 0x6c, 0x52,
+       0x5e, 0xe2, 0x71, 0x13, 0xf2, 0x2e, 0x0d, 0x1e, 0x4d, 0x34, 0x7e, 0x6b,
+       0x43, 0x71, 0xf4, 0x7b, 0x8e, 0x6c, 0xe1, 0xfd, 0x0d, 0x4a, 0x57, 0xa3,
+       0x0f, 0xf3, 0xb8, 0x5c, 0xca, 0x55, 0x74, 0xdc, 0xa0, 0x7f, 0x35, 0x46,
+       0x3e, 0x6e, 0xe6, 0xfd, 0x5a, 0xce, 0xeb, 0xbd, 0x4b, 0xd2, 0xff, 0x1e,
+       0xe4, 0xe1, 0x06, 0xa9, 0xe9, 0x1f, 0xe0, 0x4a, 0xaa, 0xfb, 0x50, 0xff,
+       0x40, 0xc6, 0xa1, 0xdc, 0xcd, 0x44, 0xff, 0x6f, 0xfc, 0xfd, 0x06, 0xd0,
+       0x53, 0x52, 0x67, 0x7c, 0x4f, 0x9f, 0x6f, 0xc2, 0xef, 0x9a, 0xfb, 0x70,
+       0x7d, 0x4a, 0x3c, 0x3f, 0x2c, 0xe9, 0x5b, 0x64, 0xf6, 0xbe, 0x15, 0xbf,
+       0xd3, 0x8d, 0xef, 0xa9, 0x1c, 0xb6, 0xc1, 0x73, 0x2a, 0x2f, 0x44, 0x9e,
+       0x09, 0xcf, 0x19, 0x3f, 0xa9, 0x9c, 0x10, 0x3b, 0xbd, 0x6f, 0xdd, 0x75,
+       0xf7, 0x97, 0x81, 0xaf, 0xf4, 0xfb, 0xc7, 0xb0, 0x7e, 0x72, 0xda, 0xf0,
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+       0xc2, 0xf6, 0x51, 0xfe, 0xc4, 0xf3, 0xd7, 0x0a, 0xf2, 0x92, 0xe1, 0xbb,
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+       0x33, 0x15, 0xd0, 0x33, 0x10, 0x51, 0xa0, 0x7f, 0x12, 0x15, 0x1b, 0xd0,
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+       0x37, 0xad, 0xdf, 0x0d, 0x72, 0x23, 0x97, 0xcc, 0x3b, 0x0b, 0xf3, 0x2c,
+       0x29, 0x8c, 0xb1, 0xdb, 0xe0, 0xf7, 0x98, 0xfd, 0xff, 0xd8, 0x7b, 0x19,
+       0xa7, 0xae, 0x60, 0x4a, 0x3a, 0x5c, 0xcd, 0xe5, 0x18, 0x7f, 0x35, 0x2e,
+       0x42, 0x6d, 0xb7, 0x32, 0xfa, 0x1e, 0xe3, 0x71, 0x0e, 0xc1, 0x5f, 0x8d,
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+       0x98, 0xc7, 0x32, 0xd8, 0xba, 0xec, 0x85, 0x92, 0x15, 0x88, 0xcb, 0x4a,
+       0xb9, 0x5f, 0x60, 0x23, 0x3b, 0xb0, 0x7c, 0x32, 0x69, 0xc7, 0xeb, 0x66,
+       0xae, 0x67, 0x17, 0x4a, 0x4e, 0x13, 0xd0, 0x7b, 0x59, 0xa1, 0xb8, 0x39,
+       0x03, 0xe8, 0xb1, 0x87, 0x82, 0xf4, 0x7b, 0xa7, 0xc9, 0xbe, 0x2b, 0x9a,
+       0x91, 0xdf, 0x12, 0xe5, 0xc9, 0x72, 0xc0, 0xd7, 0x03, 0x8a, 0xc1, 0xdf,
+       0x90, 0x4a, 0x98, 0x9d, 0xb7, 0x83, 0xbf, 0x0e, 0x7e, 0x0c, 0xc7, 0x2f,
+       0x51, 0x3f, 0x2f, 0x40, 0xae, 0x00, 0xf3, 0xaf, 0x12, 0x4f, 0x6d, 0xb1,
+       0x1a, 0xfd, 0x31, 0x71, 0x1d, 0x50, 0x2c, 0x28, 0x0f, 0x2e, 0xab, 0x29,
+       0x9f, 0xee, 0xff, 0x7a, 0xfe, 0x1d, 0xfd, 0x5c, 0xf9, 0x27, 0xfc, 0xc4,
+       0x11, 0x9c, 0x77, 0xf8, 0xeb, 0x04, 0xd6, 0x63, 0x44, 0x3e, 0xa1, 0x28,
+       0xff, 0x8a, 0x29, 0xde, 0xa4, 0x66, 0xb3, 0x75, 0x18, 0x73, 0xbd, 0x77,
+       0x58, 0x19, 0xdf, 0x2b, 0xac, 0x1c, 0x1f, 0x0b, 0x3c, 0xe1, 0x33, 0xb7,
+       0x93, 0x14, 0x04, 0x7e, 0xaa, 0xd4, 0x9f, 0x4a, 0x92, 0x46, 0xd7, 0x93,
+       0xa8, 0x3d, 0x32, 0x30, 0x73, 0x9c, 0xb8, 0xf5, 0x46, 0x6c, 0xff, 0x94,
+       0xe2, 0x62, 0xfe, 0x04, 0xcf, 0x07, 0xa2, 0x6e, 0xb9, 0x64, 0xf0, 0x4f,
+       0xec, 0xba, 0x3b, 0x76, 0xbd, 0x7f, 0xe4, 0x7b, 0xb7, 0xc5, 0xa0, 0xa7,
+       0xa3, 0xe9, 0x66, 0xfc, 0xf9, 0xbc, 0xe9, 0x5d, 0x40, 0x1d, 0x52, 0xb8,
+       0x2e, 0x14, 0x76, 0xb8, 0x84, 0xe1, 0xc9, 0x45, 0x1e, 0x8a, 0x27, 0xe9,
+       0x9f, 0x8b, 0x34, 0x26, 0xa7, 0x27, 0xfd, 0x52, 0x68, 0x13, 0xca, 0xa9,
+       0x6e, 0xf0, 0xb7, 0xea, 0x4a, 0x6a, 0xcf, 0xa2, 0x5d, 0xa2, 0xfe, 0x88,
+       0x3a, 0x87, 0xe3, 0x74, 0x4a, 0x7f, 0x1b, 0xd4, 0x4b, 0xeb, 0x79, 0x7d,
+       0xb2, 0xf8, 0x6e, 0xc4, 0x9e, 0x58, 0xae, 0xdc, 0x32, 0xba, 0x9e, 0xa6,
+       0x6a, 0x86, 0x7b, 0x48, 0xf0, 0x97, 0xf3, 0x63, 0xe3, 0x07, 0x4d, 0x54,
+       0x5c, 0x0a, 0x66, 0x42, 0xbd, 0xec, 0x7b, 0x5a, 0xb4, 0xfb, 0x4a, 0x3c,
+       0x3a, 0xb8, 0xdd, 0x6a, 0x2a, 0x79, 0x60, 0xa1, 0xe6, 0x84, 0x7b, 0x5d,
+       0x7a, 0x1a, 0xf0, 0x5e, 0x61, 0x0c, 0x3e, 0x00, 0xbe, 0xe6, 0xdb, 0x8c,
+       0x7c, 0x36, 0xd9, 0xbf, 0xea, 0x51, 0x76, 0xcf, 0x68, 0x6f, 0xe7, 0x51,
+       0xf9, 0xdd, 0x4f, 0xdb, 0xa9, 0x93, 0xd7, 0x36, 0x42, 0xc8, 0xbb, 0xf6,
+       0x89, 0x15, 0xfb, 0x5e, 0x45, 0x72, 0x84, 0x1f, 0xe2, 0x89, 0x5b, 0xef,
+       0x71, 0xf8, 0xe3, 0x76, 0x40, 0x7f, 0x46, 0xbc, 0x42, 0xbc, 0x2c, 0x8f,
+       0xa3, 0x2a, 0xe8, 0x69, 0x44, 0xbe, 0x67, 0x48, 0x24, 0x94, 0x03, 0xf4,
+       0x1b, 0xe9, 0x98, 0x97, 0x6d, 0xf2, 0xc3, 0x32, 0xcc, 0xfd, 0xd8, 0x81,
+       0xe3, 0x78, 0x48, 0xa1, 0xf3, 0x08, 0x1d, 0xaf, 0x43, 0x74, 0x1c, 0x77,
+       0xa0, 0x7f, 0x1c, 0xdf, 0x9f, 0x12, 0x7e, 0x5e, 0x45, 0xce, 0x30, 0xfa,
+       0x53, 0xc2, 0xdf, 0x23, 0xdc, 0xdf, 0x73, 0xd1, 0xff, 0x62, 0xf1, 0x58,
+       0x39, 0x2f, 0xef, 0x7f, 0xc8, 0xa3, 0x00, 0xfe, 0xf5, 0xdb, 0x4d, 0x71,
+       0xe6, 0x91, 0xfc, 0x63, 0x82, 0xfe, 0x54, 0x05, 0x31, 0xd2, 0x5b, 0xce,
+       0xfd, 0xbe, 0x72, 0x93, 0xdf, 0x27, 0xf4, 0xfd, 0x25, 0x61, 0x2f, 0x85,
+       0x5f, 0xcb, 0xed, 0xe1, 0x1d, 0xc2, 0x9f, 0x2a, 0x1f, 0x7b, 0x7d, 0xb9,
+       0xc7, 0x94, 0x4f, 0x57, 0x4d, 0x09, 0x6f, 0xbf, 0x06, 0x3d, 0x20, 0x40,
+       0x15, 0xac, 0x37, 0x91, 0x11, 0x3e, 0x19, 0xe4, 0xab, 0x3b, 0xe7, 0xfa,
+       0xf6, 0x30, 0xe5, 0xeb, 0x1d, 0xde, 0x24, 0xb6, 0xde, 0x42, 0xe9, 0x54,
+       0x84, 0x3d, 0x47, 0x3e, 0x31, 0x9c, 0xbd, 0x90, 0x97, 0xbf, 0xc3, 0xa3,
+       0xa2, 0xfc, 0xfb, 0x34, 0xb6, 0x7e, 0xd1, 0x38, 0x4e, 0xdc, 0xc2, 0x57,
+       0xc2, 0xd6, 0x0d, 0x4e, 0xd9, 0x25, 0x36, 0x1f, 0x04, 0xc9, 0x9b, 0x24,
+       0x26, 0x3f, 0xbc, 0xca, 0xc3, 0xec, 0xb5, 0x66, 0x92, 0x8b, 0x6c, 0x4f,
+       0x53, 0x35, 0xac, 0x03, 0x69, 0x8a, 0xe4, 0x0d, 0x91, 0xd1, 0xf2, 0x5a,
+       0xcd, 0xfd, 0x39, 0xf8, 0x7e, 0x3d, 0x65, 0x45, 0x75, 0x3e, 0xf5, 0xc9,
+       0x67, 0xc6, 0xcb, 0x2f, 0xef, 0x83, 0xd0, 0x2a, 0x29, 0xa7, 0x34, 0x3c,
+       0x9b, 0x93, 0x78, 0x7c, 0x75, 0x6f, 0xa4, 0x0a, 0x86, 0xe7, 0x6a, 0xc7,
+       0x97, 0x98, 0x70, 0xf6, 0xa9, 0xc8, 0x7b, 0x98, 0xd7, 0x75, 0xa1, 0x50,
+       0xc2, 0x75, 0x9f, 0xee, 0x9c, 0x8f, 0xd1, 0x3f, 0x10, 0xeb, 0x3b, 0x51,
+       0xfe, 0x1d, 0xc5, 0x7c, 0x14, 0x5f, 0xc9, 0x47, 0xe8, 0xaf, 0x8c, 0xe4,
+       0x6d, 0xf1, 0xfa, 0x16, 0x8a, 0xfa, 0x4a, 0x0e, 0xe3, 0x7a, 0xcd, 0xf7,
+       0x5c, 0x87, 0x31, 0x4f, 0xe4, 0x24, 0xac, 0xe3, 0xd2, 0xef, 0x4f, 0x2a,
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+       0x73, 0x20, 0x4f, 0x82, 0xd5, 0x17, 0xe6, 0x7e, 0xd5, 0x29, 0xfb, 0x1b,
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+       0xf8, 0x98, 0x8d, 0xfd, 0x40, 0x3e, 0x98, 0xe7, 0x1b, 0xe1, 0xc7, 0x8a,
+       0x7d, 0x4a, 0x93, 0xdc, 0x4c, 0x6f, 0x1b, 0xb8, 0x1f, 0x5b, 0x56, 0xd8,
+       0x82, 0xfa, 0x98, 0xe6, 0xa6, 0x7e, 0x2b, 0xf0, 0xcd, 0xcb, 0xfc, 0x56,
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+       0x03, 0x4e, 0x0e, 0xb3, 0x38, 0x5e, 0xa2, 0x71, 0xdb, 0x66, 0xc2, 0xe9,
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+       0xc0, 0xb7, 0x70, 0x12, 0x49, 0x86, 0xfc, 0x33, 0xb7, 0x35, 0x94, 0x44,
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+       0x86, 0x82, 0xb0, 0xef, 0xec, 0xdc, 0x65, 0xb6, 0x9f, 0xa2, 0xf2, 0xd7,
+       0x6f, 0x54, 0xc1, 0xb4, 0x36, 0x7a, 0x5d, 0x46, 0x27, 0x80, 0x43, 0xc4,
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+       0xb9, 0x01, 0x5a, 0xbe, 0xa1, 0x70, 0x6f, 0xf6, 0xca, 0xa2, 0xd1, 0xf6,
+       0x65, 0x44, 0x7f, 0x0a, 0xff, 0xb2, 0x21, 0x40, 0xe9, 0x39, 0x39, 0xff,
+       0x37, 0xd9, 0x80, 0xdb, 0xde, 0xa0, 0x76, 0xd7, 0x03, 0xed, 0x72, 0xbb,
+       0x65, 0xf6, 0x97, 0xcc, 0xf3, 0xaa, 0x39, 0x2f, 0xc6, 0xdc, 0xef, 0x4c,
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+       0xdb, 0xff, 0xba, 0x2a, 0x83, 0x7d, 0xa3, 0xf8, 0xbd, 0x56, 0x8a, 0xca,
+       0xd1, 0x1a, 0x2e, 0x47, 0x0d, 0x1a, 0xb3, 0x7f, 0xad, 0x45, 0x24, 0xb4,
+       0x49, 0x02, 0xf9, 0x3b, 0xd3, 0x58, 0x06, 0x7a, 0xf7, 0x2a, 0xcb, 0x37,
+       0x9c, 0xb4, 0xff, 0x5d, 0x96, 0x3f, 0x6a, 0x9a, 0x1f, 0x7a, 0xf9, 0xbc,
+       0x21, 0xe6, 0xe3, 0xde, 0xc9, 0xef, 0xa1, 0xfe, 0x9c, 0xdf, 0xc7, 0xf5,
+       0x25, 0x68, 0x91, 0x62, 0xe3, 0x49, 0x5a, 0x49, 0x64, 0x29, 0x8c, 0x8b,
+       0xe0, 0x4f, 0xa7, 0xc9, 0xde, 0xf8, 0xec, 0xf1, 0xe3, 0x26, 0xef, 0xd8,
+       0x18, 0x5e, 0x2d, 0xd7, 0xd8, 0x7b, 0x8d, 0xda, 0x6f, 0x58, 0xd7, 0x36,
+       0xbf, 0xaf, 0xe4, 0xfe, 0x54, 0x15, 0x5c, 0x63, 0xe6, 0x85, 0x07, 0x6d,
+       0x0c, 0xf7, 0x8a, 0xeb, 0x35, 0xe4, 0x21, 0x3c, 0xf5, 0x5d, 0xaa, 0xff,
+       0xdd, 0xdb, 0x0f, 0xb9, 0xef, 0x46, 0x3b, 0xa5, 0x21, 0x6e, 0x5f, 0xb3,
+       0x7f, 0x6f, 0x01, 0xac, 0xd9, 0x64, 0xee, 0xdb, 0x5b, 0xcd, 0xed, 0x05,
+       0xfa, 0x65, 0x32, 0xef, 0xe7, 0x24, 0xe2, 0x41, 0x3b, 0xb5, 0x50, 0xb3,
+       0xb3, 0xf5, 0x03, 0x93, 0x9c, 0x5b, 0x4b, 0x76, 0x85, 0x01, 0x3e, 0x8b,
+       0x79, 0x1a, 0x1c, 0x72, 0x25, 0x33, 0x6a, 0x47, 0xe4, 0xd8, 0x38, 0x44,
+       0x1c, 0x3f, 0x8c, 0x04, 0xf5, 0x37, 0xf3, 0x63, 0xf2, 0xbe, 0xe8, 0xfc,
+       0x4e, 0xc0, 0xae, 0x54, 0xb9, 0x59, 0xfc, 0xd5, 0x2c, 0x27, 0x69, 0x25,
+       0xd4, 0xee, 0xe0, 0x20, 0x50, 0xee, 0xc5, 0xac, 0xfb, 0x9a, 0xe5, 0xb6,
+       0x41, 0x0b, 0xb8, 0x61, 0x3d, 0x9b, 0xea, 0xcf, 0x59, 0xb6, 0xfe, 0x49,
+       0xe7, 0x2b, 0x88, 0x4f, 0xc8, 0x8d, 0x5e, 0x1c, 0x4f, 0x2e, 0x9f, 0x16,
+       0xfa, 0x1f, 0xcc, 0x7f, 0x0e, 0xaf, 0x51, 0x3e, 0xad, 0x05, 0xaa, 0x01,
+       0xaf, 0x98, 0xe9, 0xf8, 0xa9, 0xcd, 0x88, 0xff, 0xc5, 0xfc, 0x9c, 0xe6,
+       0xee, 0x47, 0xfa, 0x16, 0x6a, 0xed, 0xd9, 0xd0, 0xfe, 0x24, 0x77, 0x3f,
+       0xfa, 0x5b, 0xd4, 0xbe, 0x67, 0xc3, 0x55, 0xc8, 0x99, 0xb0, 0xd7, 0x23,
+       0xf2, 0x57, 0x74, 0x5b, 0x3d, 0xd8, 0x77, 0x90, 0x6b, 0x58, 0x22, 0x3f,
+       0x59, 0x32, 0x2b, 0x19, 0xec, 0x60, 0x83, 0x9b, 0xe1, 0x14, 0x62, 0x8a,
+       0xa7, 0xf7, 0xba, 0xc7, 0xf6, 0x37, 0x7a, 0x4c, 0xf2, 0x78, 0xd2, 0xc5,
+       0xfc, 0xab, 0x86, 0x12, 0x92, 0xec, 0x4a, 0x05, 0x7d, 0x67, 0x71, 0xa7,
+       0xde, 0x47, 0xd3, 0x77, 0x39, 0x62, 0xe2, 0x72, 0xff, 0x64, 0x0d, 0x74,
+       0xd8, 0x62, 0xe2, 0xeb, 0xce, 0xc2, 0x2f, 0xd6, 0xbb, 0x9c, 0x60, 0x67,
+       0x58, 0xfe, 0x56, 0x29, 0x35, 0x5f, 0xd6, 0xbc, 0x68, 0x3c, 0x53, 0xc4,
+       0x4d, 0xc5, 0x7a, 0x9f, 0x88, 0x93, 0x8e, 0x8a, 0x67, 0x16, 0x76, 0x63,
+       0x7e, 0x97, 0x55, 0xe4, 0x5d, 0xf0, 0xf5, 0xbf, 0x51, 0x79, 0x3f, 0x09,
+       0xd6, 0x1d, 0xc5, 0x55, 0xc4, 0x33, 0x6d, 0x9b, 0xda, 0x15, 0x2f, 0x5f,
+       0x2f, 0x41, 0x3c, 0xd6, 0xc8, 0xe3, 0x70, 0xc3, 0x33, 0xc7, 0x89, 0x87,
+       0xb2, 0xf8, 0x03, 0xc5, 0x67, 0xbf, 0xb5, 0x4d, 0x1c, 0x1f, 0x9f, 0xed,
+       0xe1, 0x7e, 0xe6, 0x00, 0x18, 0x0f, 0x7a, 0x5d, 0x65, 0x73, 0xe1, 0x55,
+       0x83, 0x7c, 0x14, 0x4a, 0x6a, 0x6f, 0x52, 0x7c, 0xdc, 0x76, 0x90, 0xfb,
+       0x6d, 0xd7, 0xa2, 0x9f, 0xc7, 0x64, 0xf8, 0x8e, 0xb5, 0xf3, 0x27, 0x93,
+       0x7c, 0x89, 0xe7, 0x51, 0x3c, 0xcc, 0xf4, 0x60, 0x52, 0xc9, 0xde, 0x9e,
+       0x58, 0x3c, 0x5c, 0xde, 0x46, 0x79, 0x43, 0xc7, 0x49, 0x6d, 0x23, 0xd3,
+       0x48, 0x6a, 0x62, 0xb9, 0x5b, 0x38, 0x62, 0xf7, 0x7e, 0x65, 0x90, 0xaf,
+       0x11, 0x7c, 0x3c, 0x0e, 0x2e, 0x16, 0xf2, 0x75, 0x51, 0xd6, 0xff, 0x66,
+       0x9b, 0x98, 0xb8, 0x5c, 0x03, 0xa7, 0x23, 0xd1, 0xfb, 0xd6, 0x22, 0x5b,
+       0x33, 0xe4, 0x5b, 0xd1, 0x72, 0x64, 0x52, 0x2a, 0xbb, 0xde, 0x40, 0xaf,
+       0x3d, 0x33, 0xf6, 0x66, 0x5b, 0xe8, 0xf3, 0xd7, 0x00, 0x7f, 0xc5, 0xd0,
+       0xd1, 0xfb, 0xcc, 0x7e, 0xec, 0xc7, 0x1f, 0x54, 0xb6, 0xcf, 0xa6, 0xf7,
+       0xe2, 0xca, 0x5c, 0xc0, 0x07, 0xa7, 0x14, 0x3d, 0xd5, 0x3e, 0xf1, 0xea,
+       0xe5, 0xc7, 0xac, 0x4f, 0xf6, 0xd9, 0xba, 0x67, 0x23, 0xd5, 0xbf, 0xae,
+       0x6c, 0x3b, 0xce, 0xcf, 0x5d, 0x6e, 0x86, 0x43, 0x5e, 0x87, 0x92, 0x31,
+       0xf2, 0xb4, 0x4e, 0x0d, 0x5c, 0x67, 0x9f, 0x8d, 0x10, 0x44, 0x27, 0xe9,
+       0xdc, 0xc8, 0x09, 0x39, 0x07, 0xa3, 0x59, 0x7d, 0x75, 0xfb, 0xc4, 0xee,
+       0x72, 0xf4, 0x3f, 0xd4, 0x14, 0x33, 0x3f, 0x6c, 0x87, 0x57, 0x93, 0x61,
+       0x9d, 0x8f, 0xc9, 0xcd, 0x23, 0x6a, 0x3f, 0xe6, 0xe3, 0xdc, 0x45, 0x6b,
+       0xb7, 0xd1, 0x76, 0x0e, 0x6b, 0x72, 0xe6, 0x0a, 0x7a, 0x3f, 0xd3, 0xce,
+       0xe4, 0xf1, 0x70, 0xd0, 0x1a, 0x37, 0xff, 0x79, 0xa6, 0x9d, 0xe1, 0xe7,
+       0x75, 0x6a, 0xd3, 0x4c, 0xa0, 0x93, 0xb4, 0xaf, 0x45, 0x3d, 0x6b, 0x91,
+       0xe4, 0x26, 0xd0, 0x7f, 0xe2, 0xbd, 0xba, 0xf8, 0xdc, 0xe6, 0x8e, 0xf8,
+       0x79, 0xa5, 0x55, 0xd1, 0xfa, 0xe7, 0x62, 0xfd, 0xfb, 0x68, 0xfd, 0x80,
+       0x1b, 0xbc, 0x3c, 0xfe, 0x4e, 0x5c, 0x99, 0x71, 0xe3, 0xed, 0xbc, 0xdf,
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+       0x9b, 0xf7, 0xe6, 0x46, 0xeb, 0xaf, 0x8f, 0xad, 0x1f, 0xf3, 0xb3, 0x66,
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+       0x05, 0x09, 0x73, 0xb0, 0xb0, 0x9f, 0xca, 0x84, 0x29, 0xbb, 0xb6, 0xd1,
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+       0xc4, 0xfb, 0x5c, 0x5a, 0x08, 0xf6, 0x65, 0xd2, 0xef, 0xad, 0xcb, 0xc6,
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+       0x6f, 0xc2, 0xf3, 0xc6, 0x46, 0xe3, 0x78, 0x1c, 0x49, 0xce, 0x65, 0xe7,
+       0xc8, 0x28, 0x6c, 0x3c, 0x60, 0xfc, 0xb2, 0x66, 0x8e, 0x6e, 0x97, 0xce,
+       0x7e, 0x01, 0x35, 0x33, 0x86, 0xff, 0xbe, 0xdf, 0xfc, 0x9d, 0x14, 0x33,
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+       0xed, 0xaf, 0x1c, 0x8d, 0x3b, 0x4e, 0x2a, 0xd9, 0xb5, 0x03, 0xf6, 0xc7,
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+       0x5e, 0x12, 0xce, 0xe1, 0xf2, 0x85, 0xf9, 0x34, 0x3d, 0xf9, 0x6c, 0x5f,
+       0x10, 0xd7, 0xaf, 0xb4, 0x92, 0x5d, 0x6d, 0xb9, 0x10, 0xa7, 0x1c, 0x56,
+       0xd8, 0xfa, 0xb3, 0x69, 0x3e, 0x29, 0xa3, 0x63, 0x95, 0x9d, 0x0e, 0x71,
+       0x73, 0x36, 0x3e, 0x27, 0x67, 0xcb, 0xe8, 0xd7, 0x95, 0x95, 0x30, 0x5c,
+       0x5f, 0xc6, 0x71, 0x7d, 0x83, 0xde, 0x82, 0xeb, 0x7a, 0x8d, 0x8f, 0xf6,
+       0x6c, 0xcf, 0x85, 0xf7, 0x72, 0x76, 0x8d, 0xdf, 0xc3, 0xd7, 0x47, 0x63,
+       0xf8, 0x47, 0xf6, 0xb3, 0x38, 0xdc, 0x22, 0x93, 0x9c, 0xa7, 0x98, 0xe2,
+       0xfc, 0x65, 0x5e, 0x53, 0x7e, 0x20, 0xcf, 0xeb, 0xeb, 0x2a, 0x78, 0xce,
+       0x05, 0xf2, 0xf3, 0x48, 0x3a, 0x97, 0x9f, 0x99, 0x12, 0xea, 0xd1, 0xeb,
+       0x92, 0xe7, 0xd1, 0xdc, 0x98, 0xf9, 0xa8, 0x3e, 0x59, 0xe4, 0x1f, 0x11,
+       0x8f, 0x35, 0x46, 0x3e, 0x46, 0xe4, 0x81, 0x8f, 0xaf, 0x99, 0xef, 0x89,
+       0xf8, 0x69, 0xe6, 0x93, 0x59, 0x2e, 0xcc, 0xfc, 0x3e, 0x99, 0x62, 0xe2,
+       0x57, 0x02, 0xfe, 0x27, 0xe2, 0x77, 0x59, 0x89, 0xff, 0xbf, 0x94, 0xbf,
+       0xe7, 0xac, 0x36, 0x2b, 0xc8, 0x6d, 0xb7, 0xf5, 0x83, 0x6c, 0xee, 0x0f,
+       0x11, 0x39, 0xc6, 0x9e, 0x98, 0xf9, 0x76, 0x4e, 0xf3, 0xa4, 0x80, 0x9d,
+       0x38, 0x3d, 0xcc, 0xe6, 0x9b, 0x13, 0x53, 0x3d, 0x5f, 0xc1, 0x73, 0xb0,
+       0xa8, 0x1e, 0xe3, 0x39, 0x9e, 0x5c, 0x1f, 0xa2, 0xe3, 0x40, 0xf5, 0xc1,
+       0x19, 0xab, 0xcf, 0x6f, 0x4f, 0x03, 0x7d, 0xa6, 0x72, 0x66, 0x85, 0x7a,
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+       0xc3, 0xd7, 0x3f, 0xc4, 0x78, 0x6e, 0x5e, 0xdb, 0x87, 0xf9, 0x1e, 0xbd,
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+       0x7f, 0x15, 0x10, 0xea, 0x4d, 0x87, 0x7a, 0x3c, 0x3d, 0x13, 0x21, 0x9e,
+       0xa7, 0x90, 0x2d, 0x70, 0x8e, 0x4c, 0xa6, 0xbd, 0x45, 0x07, 0x3d, 0x50,
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+       0x79, 0x6d, 0x66, 0x39, 0x48, 0xb3, 0x0f, 0x61, 0x3c, 0xbe, 0x72, 0x58,
+       0xc3, 0xf3, 0x9e, 0xcd, 0xe3, 0x6e, 0x1e, 0xd7, 0x4a, 0x2d, 0xf2, 0xfe,
+       0xe3, 0xb0, 0x3f, 0xe3, 0x62, 0xb2, 0x77, 0x13, 0x8c, 0xb3, 0x9d, 0x8d,
+       0xb3, 0x18, 0x47, 0x55, 0xee, 0x94, 0x61, 0x1f, 0x07, 0x51, 0xd8, 0x78,
+       0x89, 0xf5, 0x2f, 0x73, 0xfc, 0xb5, 0xcc, 0xb4, 0x3f, 0xce, 0x4c, 0x97,
+       0x38, 0x17, 0x61, 0xbd, 0x66, 0xda, 0x2f, 0xc6, 0x71, 0x7c, 0x25, 0xa7,
+       0xae, 0x2d, 0x69, 0xaf, 0xe1, 0x7c, 0xda, 0x4a, 0x6e, 0x67, 0x46, 0xe6,
+       0x6d, 0x7b, 0x1e, 0x5f, 0xc7, 0x62, 0xe7, 0x99, 0x1e, 0x18, 0x1c, 0x7b,
+       0x1d, 0xeb, 0x80, 0x8b, 0x9d, 0xef, 0x47, 0x5c, 0x8b, 0xc7, 0xb1, 0x7b,
+       0x9b, 0x98, 0xff, 0xcd, 0xcf, 0x11, 0x28, 0x2b, 0x21, 0xc9, 0x80, 0x73,
+       0xca, 0x06, 0x09, 0x93, 0xaf, 0x47, 0x2d, 0x21, 0x47, 0x4e, 0x6c, 0xf9,
+       0x90, 0x61, 0xff, 0xb8, 0x73, 0x70, 0x59, 0x3d, 0x9e, 0xc7, 0xe8, 0x72,
+       0x55, 0x43, 0x9c, 0xad, 0x8c, 0xb0, 0xf5, 0x4a, 0x7d, 0x80, 0xe0, 0xfa,
+       0xa5, 0x4e, 0xf6, 0xca, 0x81, 0x98, 0x7e, 0x89, 0x75, 0x10, 0x95, 0xc7,
+       0xc5, 0x54, 0x89, 0xf5, 0x4b, 0xf0, 0xc9, 0x4c, 0xdf, 0x5d, 0xc3, 0x46,
+       0x7f, 0xe8, 0x2b, 0x41, 0xe3, 0xbe, 0x87, 0x3b, 0x1f, 0x36, 0xee, 0xd3,
+       0xf8, 0xd2, 0xda, 0x2c, 0xc3, 0xfb, 0xda, 0x55, 0x79, 0x86, 0xf7, 0x35,
+       0x9e, 0x9b, 0x0d, 0xf7, 0x5f, 0x74, 0x1b, 0xcf, 0x09, 0xfa, 0x42, 0xc0,
+       0x78, 0x4e, 0xd0, 0x92, 0xe6, 0x2a, 0x43, 0xf9, 0x45, 0x4d, 0xc6, 0x73,
+       0x82, 0xee, 0xa8, 0x33, 0x9e, 0x13, 0xd4, 0xa0, 0xdf, 0x69, 0xd2, 0x5f,
+       0xdd, 0x20, 0xdf, 0x5d, 0x52, 0xdf, 0x0f, 0xa1, 0xff, 0x16, 0xc7, 0xef,
+       0xf3, 0xc6, 0x8a, 0x07, 0x97, 0x8f, 0xb7, 0x6e, 0x1c, 0x64, 0xe7, 0x06,
+       0xa1, 0x1f, 0x18, 0x67, 0xbf, 0x8b, 0x79, 0x5f, 0xdb, 0x07, 0x9a, 0xc0,
+       0x0b, 0x46, 0x3d, 0xe8, 0x09, 0xfa, 0xd9, 0xb9, 0x3a, 0x03, 0x9e, 0x9d,
+       0x7e, 0x7a, 0x7f, 0x88, 0x78, 0x15, 0x74, 0x70, 0xf9, 0xf9, 0x41, 0x35,
+       0x84, 0x95, 0xab, 0x71, 0xb3, 0xf5, 0x96, 0xea, 0x8c, 0xf8, 0xfe, 0xbc,
+       0xb0, 0x83, 0xe6, 0xf5, 0x0a, 0x71, 0xfe, 0x5f, 0xd9, 0x60, 0x1f, 0xca,
+       0x41, 0xb9, 0xe9, 0xbc, 0xbf, 0x52, 0xf7, 0xbc, 0xb8, 0xe7, 0x79, 0xbe,
+       0xa7, 0x71, 0xbc, 0x20, 0xce, 0xbf, 0x48, 0x70, 0xce, 0xc5, 0xa8, 0xf9,
+       0xfb, 0x6a, 0xfb, 0xc7, 0xd7, 0x99, 0xc6, 0xed, 0x1f, 0x6f, 0xb7, 0x94,
+       0xf4, 0x1d, 0x76, 0xe6, 0x24, 0xee, 0xdf, 0xd5, 0xf6, 0x6b, 0x24, 0x8f,
+       0x0b, 0xce, 0x1d, 0xa4, 0xfc, 0xe8, 0x83, 0x47, 0x93, 0xd9, 0x7b, 0x8d,
+       0xea, 0xdb, 0x96, 0xb4, 0x02, 0x3c, 0xe7, 0x22, 0xc3, 0x5e, 0x29, 0xa5,
+       0x4c, 0x8c, 0xc6, 0x3b, 0x89, 0x3e, 0xeb, 0xaa, 0xf2, 0xce, 0xba, 0x79,
+       0x1c, 0x9f, 0xe8, 0x4b, 0xae, 0xea, 0xdc, 0xd2, 0x0c, 0xbb, 0x87, 0xe9,
+       0xbf, 0xce, 0xf0, 0xd1, 0x16, 0x49, 0x0f, 0xc1, 0x39, 0x79, 0xe6, 0x75,
+       0x53, 0x95, 0xcf, 0xa7, 0x93, 0x22, 0xec, 0xbc, 0x0b, 0x1f, 0x3f, 0xef,
+       0x22, 0x69, 0x0b, 0xd1, 0x0b, 0x29, 0x8b, 0x82, 0x95, 0x04, 0xd7, 0xf1,
+       0x83, 0xb9, 0xf6, 0xd0, 0x66, 0x09, 0xf2, 0xc6, 0xd9, 0x7e, 0xd2, 0xd6,
+       0x1b, 0x2d, 0x38, 0xff, 0xb4, 0x0e, 0xe9, 0x3b, 0xe0, 0x77, 0x2d, 0xda,
+       0x6e, 0x54, 0x70, 0x3f, 0x63, 0x8d, 0xac, 0x61, 0x79, 0x35, 0x9b, 0xcd,
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+       0x23, 0x32, 0xae, 0xc3, 0x9b, 0xeb, 0x6b, 0x9d, 0xca, 0xe7, 0xfd, 0x14,
+       0x2e, 0xcf, 0x93, 0x57, 0xa2, 0x7f, 0x65, 0xfe, 0x1d, 0xbd, 0x2a, 0x77,
+       0x68, 0xfb, 0x4c, 0x5a, 0x8f, 0xef, 0xd8, 0xdd, 0x6c, 0x9f, 0xd5, 0xe5,
+       0xbb, 0xc9, 0xb2, 0x22, 0xc0, 0x27, 0x01, 0x02, 0xe7, 0x6d, 0xaa, 0xf4,
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+       0x56, 0x89, 0xa4, 0xcc, 0x2b, 0x8c, 0xda, 0x91, 0xaa, 0x08, 0x09, 0x57,
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+       0x82, 0xf9, 0x3e, 0x4d, 0x81, 0xf5, 0xbe, 0xd7, 0x12, 0xfc, 0x1e, 0xd3,
+       0x93, 0x72, 0x60, 0x7a, 0x6a, 0x4c, 0xfd, 0x7e, 0x62, 0xc4, 0x2b, 0x74,
+       0xfc, 0xaf, 0x4f, 0x9d, 0x8d, 0xe3, 0x7f, 0x03, 0x94, 0xa3, 0xe3, 0x5f,
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+       0x43, 0x3b, 0xd5, 0x3f, 0x5f, 0xd4, 0x33, 0x85, 0x7e, 0xb2, 0xba, 0xbd,
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+       0x52, 0x71, 0x3d, 0xb0, 0xf5, 0x51, 0xe3, 0x3c, 0xf2, 0x1c, 0xff, 0xfe,
+       0x40, 0xaa, 0x88, 0xdf, 0x5d, 0x1b, 0x8e, 0xa0, 0xf6, 0xaf, 0x3e, 0x15,
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+       0x08, 0xcf, 0xe7, 0xfa, 0xc6, 0x0b, 0x39, 0x33, 0xe1, 0xbc, 0x2b, 0x95,
+       0xdb, 0xe7, 0x79, 0xee, 0x6e, 0x75, 0x05, 0x8c, 0x6b, 0xa4, 0x3f, 0x6e,
+       0xbe, 0xe9, 0x57, 0x46, 0xec, 0x20, 0xb5, 0xde, 0x86, 0x79, 0x2a, 0xfe,
+       0x39, 0x2f, 0xf7, 0xa7, 0x32, 0x5c, 0x4b, 0xf5, 0xf8, 0xab, 0x7c, 0xfc,
+       0xee, 0x02, 0x3a, 0x5f, 0x9c, 0xa8, 0x07, 0x52, 0x67, 0xff, 0xd7, 0xd9,
+       0x47, 0x61, 0x87, 0x02, 0x0a, 0xb3, 0x37, 0xd4, 0x6f, 0x0a, 0x82, 0xdf,
+       0xb4, 0xec, 0xd2, 0xda, 0x23, 0x30, 0x4d, 0x35, 0x93, 0x27, 0x6a, 0x60,
+       0x7d, 0x83, 0xca, 0xe5, 0xdf, 0x01, 0x9d, 0x5f, 0xb6, 0xef, 0x3d, 0xc2,
+       0x7e, 0x7a, 0x30, 0x38, 0x05, 0xda, 0xa5, 0xf2, 0xf8, 0x70, 0x2a, 0xb3,
+       0x47, 0x7f, 0x9f, 0xca, 0xec, 0xd1, 0x77, 0x52, 0x99, 0x3d, 0xfa, 0x87,
+       0xcf, 0x22, 0x67, 0xf7, 0xa6, 0x92, 0x31, 0xf1, 0xa7, 0xc0, 0xe1, 0x02,
+       0x7f, 0x53, 0x3b, 0xbf, 0x2d, 0x95, 0xe1, 0x4f, 0x8f, 0xf3, 0xf3, 0x99,
+       0x37, 0x76, 0xf2, 0xfa, 0x02, 0xce, 0x6b, 0x9c, 0x37, 0xbe, 0xf4, 0x39,
+       0xb4, 0x4f, 0xf1, 0xc6, 0xcf, 0x50, 0x5f, 0x39, 0x1f, 0x12, 0xe1, 0xdb,
+       0x5f, 0x70, 0xb9, 0xfa, 0x65, 0xaa, 0x88, 0xfb, 0xe9, 0xbf, 0x04, 0xfe,
+       0x2f, 0xb4, 0xeb, 0xff, 0x9c, 0x1a, 0x8b, 0x37, 0x0a, 0x8f, 0xfd, 0x11,
+       0xf2, 0xe4, 0xa2, 0x78, 0xa3, 0x5b, 0xe6, 0x78, 0x43, 0x89, 0x8d, 0x67,
+       0xfb, 0x28, 0xfe, 0xe2, 0x79, 0x75, 0xf7, 0x58, 0xe6, 0x44, 0xf5, 0x44,
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+       0x7c, 0xfe, 0x7c, 0xb4, 0x93, 0xa8, 0x2d, 0x74, 0x9e, 0xd1, 0x0a, 0x51,
+       0x77, 0x86, 0xe9, 0x57, 0x08, 0xfb, 0x84, 0x79, 0xa2, 0xc3, 0xcf, 0x33,
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+       0x7c, 0xbf, 0x94, 0x4f, 0xef, 0x84, 0xfd, 0x12, 0x27, 0xe5, 0x53, 0x3b,
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+       0x3a, 0x1f, 0xbb, 0x97, 0xf6, 0x6f, 0xfb, 0x2a, 0xda, 0x75, 0x17, 0x9c,
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+       0xb1, 0x49, 0x11, 0xbc, 0x1e, 0xda, 0xaf, 0xe9, 0x81, 0x79, 0x6b, 0xb2,
+       0x40, 0x5e, 0x6f, 0x90, 0x5c, 0xfd, 0x09, 0xd0, 0x39, 0xd9, 0x25, 0x50,
+       0x3a, 0x1f, 0x41, 0xd7, 0xbd, 0x85, 0xca, 0x1d, 0xb9, 0x90, 0xd8, 0x14,
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+       0xb9, 0x44, 0x65, 0x21, 0x2d, 0xfd, 0xbe, 0x6f, 0x04, 0x0a, 0x87, 0x58,
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+       0x0d, 0x01, 0xfa, 0x2a, 0x93, 0x88, 0xc7, 0x4a, 0xfb, 0x0b, 0x0e, 0x36,
+       0xef, 0x95, 0xc4, 0x2f, 0x92, 0xbe, 0x80, 0x07, 0xaa, 0x08, 0x68, 0x59,
+       0x42, 0x5c, 0x58, 0xde, 0x2b, 0xba, 0x3f, 0x06, 0xbe, 0xb1, 0xca, 0x14,
+       0xaf, 0x74, 0xff, 0x56, 0x93, 0xd5, 0xbb, 0x52, 0x00, 0xfc, 0x55, 0xbd,
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+       0x10, 0x40, 0xee, 0x63, 0x0d, 0xae, 0xe2, 0xf7, 0x97, 0x7b, 0xe5, 0xcb,
+       0xc3, 0xf3, 0xd5, 0xdf, 0x82, 0x7c, 0xf3, 0x37, 0x26, 0x97, 0x99, 0x5e,
+       0x9e, 0x9c, 0xcd, 0xe4, 0xce, 0x01, 0x7b, 0xe7, 0x0c, 0x3d, 0xdf, 0xaf,
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+       0x35, 0xc5, 0x9f, 0x87, 0xcf, 0xd7, 0xf2, 0x71, 0x97, 0x82, 0xf2, 0x01,
+       0x7d, 0x4c, 0xc2, 0xf3, 0x71, 0x4b, 0x3c, 0x93, 0x07, 0x93, 0xef, 0xf2,
+       0x36, 0xf5, 0xa2, 0xf0, 0x9b, 0x90, 0x20, 0xb8, 0x40, 0x0f, 0x97, 0x6f,
+       0x9f, 0x2d, 0xf5, 0x76, 0x06, 0xfb, 0xa5, 0x72, 0x7d, 0xa7, 0xa4, 0xa8,
+       0xf1, 0xf1, 0x30, 0xdf, 0x6e, 0xd7, 0x49, 0x6f, 0x12, 0x68, 0x1f, 0x19,
+       0xf5, 0x7b, 0xd3, 0x7b, 0x64, 0x1a, 0xcc, 0x3f, 0x9b, 0xcb, 0xcf, 0x00,
+       0x9f, 0xf7, 0x2f, 0xf1, 0x6c, 0x1f, 0xe9, 0xbc, 0x7e, 0x4c, 0xb0, 0x4f,
+       0x0b, 0x07, 0x97, 0xcc, 0xf8, 0x6e, 0xb8, 0x64, 0xc2, 0xb9, 0x88, 0x9b,
+       0xc1, 0x45, 0x8c, 0x19, 0xec, 0xf7, 0xd1, 0x75, 0x48, 0x6f, 0xbe, 0x8e,
+       0x59, 0xc0, 0x75, 0xda, 0xb3, 0x99, 0x7c, 0xcc, 0xe6, 0xfb, 0xd2, 0xd6,
+       0xe9, 0xc3, 0xe5, 0x1f, 0x95, 0xfb, 0x97, 0xc0, 0x3e, 0x27, 0x67, 0x7a,
+       0xd3, 0xa1, 0xdf, 0xab, 0x66, 0xb6, 0xbf, 0xd0, 0x75, 0x07, 0x06, 0xd7,
+       0x1d, 0x88, 0xeb, 0x2e, 0x61, 0xeb, 0x8e, 0x05, 0x39, 0x0f, 0xfc, 0xef,
+       0x3c, 0xf4, 0x12, 0xc8, 0xf9, 0x22, 0x4e, 0xa7, 0x63, 0xfd, 0x6e, 0x02,
+       0x76, 0x0f, 0xf0, 0xb0, 0xa9, 0x20, 0x28, 0xef, 0x65, 0xa7, 0x4f, 0xac,
+       0xa7, 0xed, 0x45, 0x11, 0xe4, 0xfc, 0xf0, 0xe0, 0x3a, 0xc3, 0x71, 0x9d,
+       0x7a, 0x86, 0xc7, 0x3d, 0x29, 0xea, 0x08, 0xd8, 0x27, 0xb5, 0x0b, 0x8a,
+       0xa0, 0xbd, 0x3d, 0x5b, 0x41, 0x79, 0xf9, 0x66, 0x2f, 0x13, 0xd9, 0x4c,
+       0xf9, 0x72, 0x76, 0x5a, 0xf6, 0x3d, 0x20, 0x36, 0xb5, 0x79, 0x76, 0xf2,
+       0x73, 0xb6, 0x67, 0x35, 0x39, 0xe6, 0x50, 0x7c, 0xc9, 0x7e, 0xe2, 0xb2,
+       0x20, 0x9d, 0xd7, 0xa0, 0xdc, 0x2b, 0xe2, 0xf2, 0xa5, 0x61, 0xb7, 0x9b,
+       0xc0, 0x73, 0x4f, 0x2f, 0x2a, 0x33, 0x75, 0xe3, 0x65, 0xff, 0x1c, 0x2b,
+       0xb1, 0xe1, 0x51, 0xfe, 0x71, 0x4e, 0xeb, 0x4f, 0xf9, 0xa8, 0xc9, 0x9f,
+       0x1d, 0xe7, 0x0e, 0x83, 0x17, 0xad, 0x5c, 0xbf, 0x82, 0x89, 0x22, 0xe2,
+       0x5c, 0x8a, 0xe3, 0x96, 0xf1, 0x71, 0xa1, 0xfd, 0x6c, 0x0f, 0xee, 0x8b,
+       0x81, 0xf9, 0x37, 0x40, 0xff, 0x1f, 0x11, 0x32, 0x91, 0xeb, 0x1b, 0x7a,
+       0x60, 0xdc, 0xdf, 0x58, 0xce, 0x3b, 0x0d, 0xfe, 0xcd, 0x31, 0x9d, 0xb4,
+       0xdf, 0xee, 0x9c, 0xb9, 0x86, 0xfd, 0xe0, 0x73, 0xca, 0x47, 0x4d, 0x39,
+       0x8f, 0xc5, 0x80, 0xbd, 0xd4, 0x96, 0x41, 0xf5, 0x00, 0xc8, 0xa9, 0x57,
+       0x44, 0x94, 0x93, 0x4d, 0x76, 0x86, 0xc7, 0xa6, 0xb4, 0x6a, 0xa2, 0xb7,
+       0x47, 0x4b, 0x1d, 0x3e, 0xf1, 0x63, 0x98, 0xe7, 0xdb, 0xb9, 0x64, 0x2a,
+       0xc5, 0x5f, 0x91, 0xc3, 0x4d, 0x2e, 0xa1, 0xf0, 0x5d, 0xc7, 0xf7, 0x51,
+       0xe4, 0xaa, 0xf6, 0x08, 0x49, 0xd8, 0xfe, 0x6c, 0x14, 0x9d, 0x67, 0x79,
+       0xfc, 0x25, 0x08, 0x47, 0x39, 0xc7, 0x4d, 0x2a, 0x72, 0x01, 0x2e, 0x5e,
+       0x52, 0x4d, 0xc7, 0xcb, 0x8a, 0x4f, 0x74, 0xd1, 0x7a, 0xa9, 0x9f, 0xf8,
+       0xae, 0xca, 0x87, 0xfe, 0x54, 0xce, 0x0b, 0x6c, 0x3e, 0xa7, 0x5d, 0x3f,
+       0x0f, 0x69, 0x81, 0x79, 0xe4, 0x5c, 0x46, 0x0f, 0xb2, 0xbf, 0x85, 0x00,
+       0xfc, 0x76, 0x9f, 0x3c, 0x3f, 0x1c, 0x63, 0x72, 0x4c, 0x06, 0xf9, 0xad,
+       0xf1, 0x25, 0xb5, 0xeb, 0x56, 0x00, 0x1d, 0x94, 0x29, 0x57, 0x97, 0xc5,
+       0xd3, 0xf9, 0x17, 0x6d, 0xcf, 0xca, 0x13, 0xe9, 0xfc, 0x15, 0x8e, 0x76,
+       0x79, 0x4e, 0x2e, 0xca, 0x6d, 0x0f, 0xd0, 0xc7, 0xce, 0x64, 0x75, 0x65,
+       0xfc, 0xff, 0xa0, 0x3d, 0x37, 0x8d, 0x78, 0xcd, 0x80, 0xf7, 0x51, 0x99,
+       0x4c, 0x0f, 0x4c, 0xa8, 0x15, 0xbc, 0x9b, 0x29, 0x7c, 0x9a, 0x42, 0xec,
+       0x84, 0x9f, 0xc6, 0x33, 0x3e, 0x2c, 0x0c, 0xca, 0xbb, 0x9f, 0xe1, 0xbe,
+       0x0b, 0x35, 0x3b, 0x41, 0xfd, 0x39, 0xd4, 0xcf, 0x63, 0x07, 0x3f, 0x0a,
+       0xf0, 0x38, 0x8f, 0x1d, 0xbc, 0x05, 0x9e, 0x87, 0xb1, 0x83, 0xb7, 0x42,
+       0x3b, 0x85, 0xd7, 0xe3, 0xf1, 0xcc, 0x0e, 0x7e, 0x02, 0xd6, 0xa1, 0x76,
+       0xf0, 0xb6, 0xef, 0x03, 0xb7, 0x09, 0x0a, 0x93, 0xa3, 0xd4, 0x0e, 0xdd,
+       0x01, 0xf3, 0xc6, 0x83, 0x71, 0x03, 0xf6, 0xd1, 0x1f, 0x98, 0x3d, 0x1a,
+       0xba, 0xff, 0xdb, 0xf8, 0xf9, 0xd7, 0xd0, 0xb3, 0x76, 0x00, 0x5d, 0x4a,
+       0x5e, 0x89, 0xd1, 0x39, 0xe3, 0xd3, 0xe1, 0x9c, 0x4f, 0xc7, 0x9e, 0xa4,
+       0xfc, 0x92, 0xdb, 0x93, 0xfe, 0xdb, 0x28, 0xfd, 0x7b, 0x28, 0xfd, 0x9d,
+       0xa5, 0x76, 0x93, 0x98, 0x15, 0x99, 0x9e, 0x7c, 0x17, 0xc9, 0x97, 0xc5,
+       0x0f, 0x32, 0xbe, 0x6f, 0x70, 0xec, 0x43, 0xbe, 0x7b, 0x91, 0xf3, 0x45,
+       0x1b, 0x5f, 0xbf, 0x2d, 0x47, 0xac, 0x04, 0x7c, 0xbe, 0x4a, 0x44, 0x45,
+       0x14, 0x7a, 0xce, 0xd7, 0x94, 0xe1, 0x76, 0x80, 0x5c, 0x0f, 0xe5, 0x3f,
+       0xf5, 0x5b, 0x23, 0x3d, 0x97, 0x3a, 0xbc, 0x1b, 0xf2, 0x80, 0x6f, 0x0e,
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+       0x17, 0xe0, 0x43, 0x98, 0xc7, 0x3d, 0x10, 0xec, 0x8c, 0x78, 0x49, 0xcd,
+       0x05, 0x3e, 0x62, 0xeb, 0x7a, 0x0e, 0x89, 0xa8, 0x27, 0x22, 0xf1, 0x11,
+       0xa5, 0x9b, 0x53, 0x80, 0xbf, 0x6e, 0xb8, 0x00, 0xb0, 0x75, 0xfb, 0xa7,
+       0x74, 0xf3, 0x39, 0x3c, 0xa7, 0x7c, 0x76, 0xfa, 0xfb, 0xd0, 0xcb, 0x1a,
+       0x4e, 0x1f, 0xd4, 0x0f, 0xf9, 0x1a, 0xe6, 0xeb, 0x1f, 0xcf, 0xe8, 0x67,
+       0x76, 0x04, 0xff, 0xe2, 0x1f, 0xf1, 0xdd, 0x7e, 0xc0, 0x3f, 0xa0, 0x3f,
+       0x99, 0xc1, 0xf4, 0x50, 0x66, 0xbc, 0x93, 0x8d, 0x23, 0x49, 0x32, 0xe8,
+       0x17, 0x55, 0xcc, 0xc8, 0x04, 0xf9, 0x42, 0xe7, 0x35, 0x25, 0xd0, 0xf6,
+       0xb7, 0xb8, 0x7f, 0x14, 0x69, 0xde, 0xa8, 0x84, 0x6e, 0xfe, 0x8b, 0x4a,
+       0x80, 0xf3, 0xdc, 0xc2, 0xe6, 0x3d, 0x04, 0x46, 0xf6, 0xd0, 0x9e, 0xf3,
+       0x8e, 0x4a, 0xa0, 0xf6, 0x47, 0x98, 0x79, 0xd2, 0xb8, 0x1c, 0xbf, 0x2e,
+       0x82, 0xbf, 0x90, 0xc5, 0xfd, 0x12, 0x92, 0xdb, 0x6d, 0x9f, 0xa4, 0xc0,
+       0x7a, 0x59, 0x9c, 0x6f, 0x76, 0x27, 0xab, 0x8e, 0x04, 0x1d, 0xdf, 0x14,
+       0x71, 0xbb, 0xe5, 0x65, 0xc1, 0xa8, 0x97, 0x73, 0xba, 0xfd, 0x7d, 0xc6,
+       0x3f, 0x49, 0x09, 0xac, 0x3f, 0x99, 0xd7, 0x3d, 0x6f, 0x56, 0x82, 0x0e,
+       0x9e, 0x9a, 0x1d, 0x30, 0x9b, 0xcb, 0x07, 0x6d, 0x9e, 0xfe, 0x9c, 0xff,
+       0x9c, 0x09, 0x0a, 0x1b, 0x5f, 0xc3, 0xc6, 0xc7, 0x43, 0x9d, 0x8e, 0xab,
+       0xe0, 0xfe, 0x13, 0x85, 0x4b, 0x2e, 0xcc, 0x47, 0xac, 0xec, 0xf9, 0x85,
+       0xfc, 0xa2, 0x7b, 0x14, 0x19, 0xc7, 0xcf, 0xe5, 0xfb, 0x12, 0xe2, 0x15,
+       0x4d, 0xbf, 0x21, 0x5c, 0x47, 0x47, 0xf2, 0xbb, 0x82, 0x72, 0x70, 0x38,
+       0xe2, 0xc1, 0xc5, 0xfa, 0x5f, 0xaa, 0x10, 0x0d, 0xef, 0x23, 0x71, 0x1f,
+       0x95, 0x6c, 0x1f, 0x85, 0x0a, 0xc3, 0x7b, 0x68, 0xfc, 0x20, 0x12, 0x7e,
+       0x34, 0xf8, 0x27, 0x6b, 0xe7, 0xcd, 0x61, 0xf3, 0x13, 0x4f, 0x37, 0xdc,
+       0x46, 0xeb, 0xe9, 0x25, 0x12, 0xdc, 0xde, 0x8a, 0x63, 0xf6, 0xc5, 0x28,
+       0x0e, 0x27, 0xd2, 0xc8, 0xe7, 0x09, 0x91, 0x07, 0x77, 0x4b, 0x1d, 0x56,
+       0x25, 0xcc, 0x39, 0xaf, 0x8d, 0x77, 0x1a, 0xf8, 0xd9, 0xee, 0x32, 0xca,
+       0x87, 0x48, 0xf1, 0x94, 0xbc, 0x20, 0x7c, 0x66, 0x22, 0x1c, 0xf2, 0xd9,
+       0xbe, 0x23, 0xc5, 0x57, 0x0a, 0xf8, 0x79, 0x47, 0x70, 0xfb, 0x96, 0x8e,
+       0x9b, 0x8f, 0x70, 0xb5, 0xb1, 0xfd, 0xde, 0xa3, 0x74, 0xb7, 0xd7, 0xe0,
+       0x7c, 0xe9, 0x6c, 0xbe, 0xfa, 0x20, 0xbc, 0x17, 0x63, 0xbb, 0x83, 0xf5,
+       0x8f, 0xe4, 0xf7, 0xd7, 0xf3, 0x7d, 0x55, 0x27, 0x74, 0x8f, 0x5b, 0x86,
+       0xeb, 0x24, 0xb1, 0x71, 0xa1, 0xf1, 0x04, 0xad, 0x5c, 0xc2, 0xf7, 0xb7,
+       0x30, 0x38, 0xee, 0x56, 0x5c, 0xaf, 0x1f, 0x1b, 0x97, 0x1c, 0xdc, 0xc7,
+       0x1d, 0xd8, 0x3e, 0x9a, 0xb5, 0x7f, 0xdf, 0xf8, 0x5b, 0x32, 0xdf, 0xef,
+       0x4f, 0x82, 0xeb, 0xae, 0xc1, 0xfd, 0xaa, 0xec, 0xfc, 0x81, 0xb8, 0x6e,
+       0xb8, 0xac, 0xc7, 0xf6, 0x22, 0xb6, 0x6e, 0x24, 0xf9, 0x11, 0x88, 0x63,
+       0xe7, 0x68, 0xe2, 0x70, 0xbe, 0x12, 0xfc, 0x62, 0x3a, 0x47, 0x7c, 0x80,
+       0xe4, 0x48, 0x49, 0xe0, 0x35, 0x45, 0xbb, 0x46, 0xd1, 0x2e, 0xa9, 0x01,
+       0xd5, 0x07, 0xfa, 0xa3, 0xe4, 0x4b, 0xd9, 0x09, 0x72, 0xba, 0x5c, 0xb4,
+       0x79, 0x04, 0x2a, 0x8f, 0x25, 0xa7, 0x15, 0xfd, 0xe4, 0x28, 0x89, 0xa8,
+       0xe0, 0xd7, 0xb6, 0x7f, 0xf5, 0x63, 0x47, 0x67, 0x2e, 0xd6, 0x7d, 0xa0,
+       0xd7, 0x57, 0x47, 0x15, 0x5b, 0xc1, 0xef, 0x5c, 0x93, 0x25, 0xb9, 0x40,
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+       0xb8, 0x04, 0xe7, 0xd9, 0xa7, 0x68, 0x76, 0xee, 0x8d, 0x06, 0x3f, 0xda,
+       0xa9, 0x38, 0x2b, 0xa3, 0x60, 0x1f, 0x56, 0x91, 0x38, 0x99, 0xff, 0x5f,
+       0x39, 0x9e, 0x3e, 0xbf, 0x8a, 0xcb, 0xeb, 0x7d, 0xd6, 0x44, 0x13, 0xcc,
+       0x37, 0x22, 0x83, 0xc5, 0x0b, 0xae, 0x72, 0x56, 0xa3, 0xbf, 0x4e, 0xbe,
+       0x65, 0x7e, 0xb4, 0x4a, 0xff, 0x63, 0xf2, 0x5b, 0x45, 0xbd, 0x2c, 0xf3,
+       0x71, 0x52, 0x7a, 0x3d, 0x11, 0xb0, 0x34, 0xfa, 0xdb, 0x32, 0xd9, 0x70,
+       0x46, 0x1c, 0x84, 0x7a, 0x01, 0xed, 0xa8, 0x11, 0x7e, 0xa3, 0xff, 0x2d,
+       0x3b, 0x2b, 0x4e, 0xc0, 0xfc, 0x32, 0xd1, 0x8d, 0xa3, 0xeb, 0x3e, 0x9f,
+       0x60, 0x4f, 0x42, 0x7b, 0xaa, 0x1f, 0xe9, 0x7f, 0x8e, 0xf2, 0x8f, 0x25,
+       0x47, 0x20, 0x16, 0xea, 0x5f, 0x94, 0x4b, 0xee, 0x3d, 0x80, 0x87, 0x31,
+       0xce, 0x6a, 0xa5, 0x84, 0x9e, 0xc7, 0x92, 0xee, 0xb6, 0x82, 0x1c, 0xee,
+       0x67, 0xf6, 0xf5, 0x86, 0x78, 0x42, 0x63, 0xba, 0xec, 0xf2, 0x00, 0x1b,
+       0x3e, 0x50, 0x66, 0xcd, 0x02, 0x7f, 0xab, 0x99, 0xfa, 0xe7, 0x08, 0x07,
+       0x35, 0xe1, 0xea, 0x81, 0x41, 0x3c, 0x59, 0x8a, 0x54, 0x02, 0x74, 0x48,
+       0x71, 0x82, 0xfc, 0xd5, 0x5d, 0xda, 0x58, 0x99, 0x90, 0xc8, 0xf0, 0xf8,
+       0x49, 0x82, 0x05, 0xcb, 0x12, 0x5e, 0xd7, 0x9e, 0x87, 0xe2, 0x7d, 0x48,
+       0x62, 0x34, 0xe3, 0x7f, 0x62, 0xf5, 0x7c, 0x94, 0x03, 0x72, 0x42, 0x20,
+       0x71, 0x94, 0x0e, 0x97, 0x92, 0xce, 0x4c, 0xa0, 0xc7, 0xe4, 0x34, 0x26,
+       0x9f, 0x6a, 0x4d, 0x9d, 0x29, 0x50, 0xef, 0x22, 0xfe, 0x94, 0x24, 0x5a,
+       0x36, 0x34, 0x4b, 0xa3, 0xc3, 0xf9, 0x3f, 0x1b, 0x79, 0xfc, 0x6c, 0xad,
+       0x29, 0xbc, 0xbd, 0xf4, 0x4b, 0xf3, 0x98, 0x0f, 0x00, 0x0e, 0x12, 0xc4,
+       0x0d, 0x2e, 0xc7, 0xb8, 0x80, 0xdb, 0xd2, 0x37, 0x18, 0x3f, 0xd0, 0xec,
+       0x55, 0x2d, 0x8e, 0x10, 0xc9, 0x6e, 0xbd, 0x57, 0xac, 0xfa, 0x18, 0xe6,
+       0x11, 0x14, 0xdf, 0x37, 0xd0, 0xbf, 0xa7, 0xfd, 0xeb, 0xc1, 0x7d, 0x48,
+       0xe9, 0x4c, 0x4e, 0x6b, 0xa5, 0xb6, 0x8f, 0x99, 0x89, 0x8c, 0x7f, 0x1c,
+       0x89, 0x56, 0x84, 0xcf, 0xde, 0x3b, 0x4a, 0xc9, 0x1c, 0x27, 0xe2, 0xe9,
+       0x2c, 0xf0, 0x29, 0xc5, 0xd3, 0xa1, 0x2b, 0x00, 0x2a, 0x59, 0xf3, 0x14,
+       0xc0, 0xd3, 0x2b, 0x59, 0x0f, 0xf5, 0x83, 0xb8, 0x94, 0x35, 0xeb, 0x81,
+       0x24, 0xe0, 0xcf, 0xd1, 0x84, 0xd9, 0xa7, 0xe5, 0x74, 0x8c, 0x83, 0x96,
+       0x0f, 0xd9, 0xdc, 0xdf, 0x24, 0xe8, 0xe4, 0xe1, 0x98, 0x7e, 0xb3, 0xd1,
+       0x6e, 0x2a, 0xca, 0xac, 0x47, 0x7b, 0x6a, 0x75, 0x04, 0xbf, 0xf4, 0xc7,
+       0x7c, 0x1f, 0x12, 0xa7, 0x93, 0x12, 0x9b, 0xdb, 0x94, 0x38, 0x14, 0xe2,
+       0x5f, 0xcb, 0xac, 0x30, 0x5e, 0x52, 0xaa, 0xa2, 0xa1, 0xdc, 0x1b, 0x98,
+       0x84, 0x25, 0xb5, 0x7b, 0xa5, 0x44, 0xda, 0x7f, 0x75, 0x3a, 0xab, 0x5f,
+       0x08, 0x0f, 0xef, 0x72, 0xf9, 0x10, 0x69, 0xff, 0xa3, 0x40, 0x2f, 0x40,
+       0xbc, 0x26, 0xbd, 0xfb, 0x1c, 0x09, 0x30, 0x3f, 0x7d, 0xee, 0x91, 0xf3,
+       0x82, 0xe7, 0xd0, 0xed, 0x2f, 0x25, 0xdc, 0xfe, 0xcc, 0x89, 0x4c, 0x1f,
+       0x69, 0xfb, 0x92, 0xfa, 0x71, 0xba, 0xcc, 0x31, 0xd2, 0xdd, 0x78, 0x4e,
+       0x8f, 0x39, 0x89, 0x9a, 0xbf, 0x78, 0xd1, 0x74, 0x77, 0xe4, 0x62, 0xe8,
+       0x2e, 0xf4, 0xbc, 0x63, 0xb2, 0x96, 0x8f, 0x1e, 0x40, 0x82, 0xfb, 0xd7,
+       0xce, 0xab, 0x9d, 0x9f, 0x9e, 0xd7, 0x05, 0xe7, 0x2d, 0x97, 0xd8, 0xf9,
+       0xb7, 0x2a, 0x6e, 0x15, 0xa6, 0xa0, 0x70, 0x1e, 0x0c, 0xed, 0x3d, 0xce,
+       0x65, 0x0d, 0xaf, 0xf7, 0x33, 0x12, 0x4d, 0xdf, 0xf5, 0x3c, 0x0f, 0x25,
+       0xf4, 0xbd, 0xf8, 0xf3, 0x7c, 0x87, 0x79, 0xa7, 0x26, 0x7e, 0x07, 0x38,
+       0x1d, 0x18, 0xa9, 0x3a, 0x40, 0x9e, 0x34, 0x26, 0x53, 0xfa, 0xa4, 0x78,
+       0x6a, 0x14, 0x58, 0xa9, 0xf5, 0x8f, 0xe6, 0x78, 0x6a, 0xe1, 0x74, 0xfa,
+       0x5d, 0xe4, 0x44, 0xff, 0xef, 0x70, 0xbe, 0x62, 0x87, 0xf0, 0x12, 0xe8,
+       0xc3, 0xab, 0xdc, 0xc7, 0x4a, 0x61, 0x99, 0xb2, 0xa2, 0xc1, 0xa0, 0x76,
+       0x80, 0x1f, 0xe7, 0x01, 0xbd, 0x95, 0xe4, 0xde, 0x27, 0xcd, 0xa1, 0xf5,
+       0xa6, 0x3b, 0xe6, 0xa2, 0xfc, 0x3c, 0x30, 0xb2, 0x1e, 0xf7, 0xbd, 0xda,
+       0x6e, 0xdc, 0xaf, 0x56, 0x26, 0x70, 0x7c, 0x14, 0x65, 0xaa, 0xc8, 0x7f,
+       0x8d, 0x9c, 0xff, 0xca, 0x09, 0xf3, 0x23, 0xb5, 0x7e, 0x6d, 0xfc, 0x5c,
+       0xa1, 0xfc, 0x11, 0x3a, 0x5f, 0x28, 0x5f, 0x3f, 0x64, 0x53, 0x6f, 0x06,
+       0xfa, 0x48, 0x48, 0x64, 0xfa, 0x32, 0xe8, 0xff, 0x75, 0x88, 0x7a, 0xff,
+       0xaf, 0x84, 0xeb, 0xaf, 0x91, 0xd6, 0x9b, 0x0c, 0xf1, 0x8f, 0x91, 0xdc,
+       0xff, 0x5b, 0xfd, 0x65, 0xb6, 0xcd, 0x43, 0x0f, 0x7a, 0x96, 0xea, 0xb5,
+       0x7f, 0x89, 0xff, 0xf7, 0x0d, 0x7d, 0x02, 0x7e, 0x52, 0x7a, 0x89, 0x55,
+       0xef, 0xff, 0x35, 0x5a, 0x4b, 0xb1, 0x7d, 0x75, 0x86, 0x3a, 0xfa, 0xf2,
+       0x24, 0xd0, 0xc7, 0xa2, 0xeb, 0x2e, 0x82, 0xf0, 0x43, 0x7f, 0xd0, 0x23,
+       0x88, 0xca, 0xd6, 0x30, 0xfe, 0xe0, 0xea, 0x0c, 0xd9, 0x77, 0x15, 0x7d,
+       0x6e, 0x51, 0xc8, 0xe3, 0xb0, 0xbf, 0x52, 0xaa, 0x2f, 0x21, 0xfe, 0x62,
+       0x51, 0x54, 0x72, 0xc9, 0xc0, 0x9e, 0x7e, 0xe1, 0x3e, 0x6b, 0x29, 0x81,
+       0xb8, 0xc9, 0x59, 0x85, 0x3c, 0x0b, 0xfe, 0xd8, 0x85, 0xce, 0xf3, 0x78,
+       0xa2, 0xd1, 0x2f, 0x94, 0xc0, 0x2f, 0xe4, 0xf3, 0xa3, 0x5f, 0xa8, 0xd4,
+       0x93, 0x4e, 0x8c, 0xf7, 0x94, 0x12, 0xb0, 0x6b, 0xa0, 0xdd, 0x39, 0x10,
+       0xe4, 0x8e, 0x4a, 0xdc, 0x76, 0xd0, 0x23, 0xd4, 0x2f, 0xd4, 0xc9, 0xa7,
+       0xb3, 0xd6, 0x9b, 0x90, 0xdf, 0x43, 0xd7, 0xa3, 0x72, 0xeb, 0x69, 0xa0,
+       0xa3, 0x46, 0x85, 0xf1, 0x71, 0xa8, 0x3f, 0x28, 0x72, 0x3e, 0xd7, 0xe4,
+       0x6c, 0x28, 0x3d, 0x94, 0x3b, 0x18, 0xdd, 0x44, 0xd1, 0xad, 0x9b, 0x99,
+       0xdc, 0x78, 0x2e, 0x31, 0xb9, 0x27, 0x5d, 0x7c, 0x77, 0xf9, 0x34, 0xaf,
+       0x0c, 0x5c, 0x80, 0x6b, 0xc9, 0xca, 0x03, 0xe0, 0xaa, 0x4d, 0x09, 0xf8,
+       0x25, 0x70, 0x79, 0x96, 0x27, 0x3a, 0xb1, 0x5f, 0x95, 0x6d, 0x47, 0x23,
+       0x3c, 0xd7, 0xe6, 0x0f, 0xc5, 0x0f, 0x3d, 0xb9, 0x0a, 0xf1, 0x74, 0xb0,
+       0x67, 0x58, 0xfc, 0x86, 0xda, 0x6b, 0xd4, 0x8e, 0x32, 0x53, 0x7b, 0x6d,
+       0x9d, 0x10, 0x5c, 0x7f, 0x35, 0x87, 0x77, 0x24, 0x7c, 0xac, 0x06, 0x7d,
+       0x1d, 0x86, 0x8f, 0xde, 0xee, 0x96, 0x6b, 0xa1, 0x71, 0xa2, 0x9b, 0x8c,
+       0xf7, 0x2f, 0x8a, 0x87, 0x24, 0x15, 0xb0, 0xb8, 0x3e, 0x09, 0x03, 0x7f,
+       0x91, 0xdb, 0x49, 0x6b, 0x28, 0xbf, 0xc0, 0xfd, 0xcd, 0x6a, 0xb3, 0xcb,
+       0xa1, 0x00, 0x9d, 0x66, 0x14, 0xbd, 0xeb, 0x06, 0x7f, 0x3e, 0x43, 0xc6,
+       0xfb, 0x08, 0x22, 0xd5, 0x3b, 0xae, 0xb6, 0xf7, 0x3c, 0xe7, 0x1a, 0x88,
+       0x9f, 0x85, 0xd9, 0xdf, 0x17, 0x89, 0x09, 0x08, 0x57, 0x6b, 0xba, 0xc9,
+       0x60, 0x9f, 0x11, 0x72, 0xa7, 0xc1, 0x7e, 0x8c, 0x74, 0x6e, 0xc2, 0xf7,
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+       0xf5, 0x9c, 0xb8, 0xc4, 0xc5, 0xe5, 0x33, 0xf9, 0x96, 0xc2, 0x2d, 0x9e,
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+       0x9a, 0x24, 0x40, 0x9e, 0x82, 0xc5, 0x34, 0x63, 0xb0, 0x92, 0x0d, 0x4b,
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+       0xe4, 0x33, 0x1b, 0xe6, 0x69, 0x15, 0x25, 0x09, 0xc8, 0x77, 0x92, 0x2f,
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+       0x05, 0xc7, 0x89, 0x90, 0x0f, 0x96, 0x6d, 0xc8, 0x3f, 0x7b, 0x46, 0x52,
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+       0xb2, 0xfd, 0x42, 0xbf, 0x27, 0xb7, 0x3a, 0x36, 0x01, 0x5d, 0xfc, 0x2e,
+       0x39, 0x0b, 0xd7, 0x7f, 0xc1, 0xe6, 0xde, 0x30, 0x98, 0xb6, 0x1f, 0xda,
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+       0xb3, 0x73, 0xff, 0x9a, 0xcc, 0xec, 0xef, 0x27, 0xcd, 0x1a, 0x5c, 0x25,
+       0xcc, 0x83, 0xdc, 0xb7, 0x55, 0x46, 0xfe, 0x3a, 0x94, 0x26, 0xe2, 0xfd,
+       0x13, 0x85, 0xdb, 0x12, 0xa8, 0xff, 0x25, 0x2d, 0x86, 0x50, 0x4a, 0x24,
+       0x65, 0xaa, 0xa7, 0x0c, 0xe0, 0x58, 0x4e, 0x5a, 0x1a, 0xc0, 0x9f, 0x2a,
+       0x73, 0x5e, 0xfd, 0x52, 0x2c, 0xf9, 0x27, 0xe0, 0x97, 0xbf, 0x53, 0x01,
+       0xfe, 0x5f, 0x1f, 0xc1, 0x0e, 0xff, 0x1d, 0xdf, 0x1f, 0x0a, 0x11, 0x4a,
+       0x3f, 0x07, 0xb7, 0x34, 0x5e, 0x47, 0xc2, 0xe4, 0x51, 0x6b, 0x74, 0xf8,
+       0x5c, 0x8c, 0x2a, 0xa5, 0xd0, 0xfe, 0x6b, 0xf9, 0xbd, 0x2e, 0x71, 0x4c,
+       0x42, 0xfa, 0x89, 0x8c, 0xef, 0xbb, 0x98, 0xbf, 0xd9, 0xe2, 0x6b, 0x88,
+       0xa6, 0x70, 0x1c, 0xbe, 0xbd, 0xb9, 0x97, 0x7e, 0xfe, 0x23, 0x10, 0x74,
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+       0xf3, 0x69, 0x1b, 0x4e, 0x9a, 0x10, 0x7e, 0xaf, 0xe6, 0x0a, 0x5e, 0x81,
+       0xc2, 0xe7, 0x60, 0x8e, 0x48, 0x6d, 0x36, 0xba, 0xab, 0x7e, 0x56, 0x6f,
+       0x7f, 0x5a, 0xdf, 0xc0, 0xe9, 0xb8, 0x72, 0xfb, 0xe1, 0xc6, 0x5e, 0xc0,
+       0xc2, 0x29, 0x49, 0xb8, 0xee, 0xab, 0x39, 0x8f, 0x59, 0x59, 0x7e, 0xeb,
+       0xc5, 0xc7, 0xaf, 0x87, 0x50, 0x3e, 0x58, 0x04, 0xf9, 0x53, 0x14, 0x1f,
+       0xa3, 0x94, 0x68, 0xaf, 0x93, 0xe2, 0x6b, 0x31, 0x4c, 0x41, 0xeb, 0x23,
+       0x15, 0xab, 0xd7, 0x47, 0xd7, 0x6b, 0xb7, 0x77, 0x94, 0xc6, 0xd1, 0x25,
+       0x5e, 0x48, 0x16, 0x5c, 0x9b, 0x81, 0x5e, 0x72, 0x88, 0x02, 0xf2, 0x03,
+       0x5d, 0x10, 0x13, 0x43, 0x94, 0x42, 0xeb, 0x20, 0x32, 0x90, 0x9e, 0x92,
+       0x08, 0xe6, 0x73, 0xad, 0x2f, 0xc8, 0xdd, 0x0c, 0x71, 0xb1, 0x75, 0xe9,
+       0xce, 0x16, 0xc8, 0x37, 0xdc, 0x33, 0xd0, 0x8a, 0xf9, 0x66, 0xa1, 0xf9,
+       0xc4, 0x7b, 0x84, 0xfa, 0x97, 0xe2, 0x21, 0x2e, 0x15, 0x2f, 0xa0, 0xbc,
+       0x3e, 0x98, 0xf3, 0x3b, 0xbc, 0xa7, 0x3b, 0x98, 0x6e, 0x21, 0x40, 0xaf,
+       0x98, 0xf0, 0x4b, 0x9f, 0x37, 0x26, 0x30, 0x3e, 0x8d, 0xc9, 0x37, 0xda,
+       0x9f, 0xe5, 0x29, 0x59, 0xdc, 0xcf, 0x26, 0x1e, 0x4b, 0x41, 0x70, 0x5f,
+       0x31, 0xfd, 0xac, 0x6a, 0x14, 0x25, 0xa4, 0x97, 0xe3, 0xd9, 0xf8, 0x43,
+       0xfd, 0x04, 0x2f, 0xd0, 0xdb, 0x21, 0x27, 0x97, 0x0f, 0xf4, 0xbc, 0x5b,
+       0xc1, 0x20, 0x92, 0x9a, 0xa5, 0xa9, 0x03, 0x23, 0xe3, 0xf5, 0x95, 0xfe,
+       0xa3, 0x9c, 0x9a, 0x5d, 0x2c, 0x68, 0xe7, 0x34, 0xf5, 0x3c, 0xc7, 0x0b,
+       0x82, 0x77, 0x4d, 0x36, 0x9c, 0x63, 0x00, 0x3d, 0x07, 0xad, 0xdb, 0x73,
+       0x04, 0x5c, 0xdf, 0xae, 0xac, 0xbb, 0x91, 0x60, 0x59, 0xb8, 0x00, 0xee,
+       0x31, 0x43, 0xf7, 0xbf, 0x22, 0x85, 0xf9, 0x47, 0x32, 0x25, 0xbb, 0x1c,
+       0x90, 0x6f, 0x2d, 0x6b, 0xc6, 0xe8, 0xf3, 0x63, 0xe4, 0xc2, 0x1b, 0x27,
+       0xd8, 0x62, 0x31, 0x8f, 0x09, 0xed, 0xca, 0xd4, 0x1c, 0x01, 0xcf, 0x33,
+       0xe6, 0x24, 0xbb, 0xcf, 0xed, 0x91, 0x9f, 0xad, 0x10, 0xb7, 0x6c, 0xc0,
+       0x0f, 0xb5, 0x3a, 0x52, 0x82, 0xf3, 0xc5, 0x7c, 0xf9, 0xec, 0x4f, 0x20,
+       0xff, 0x77, 0x5c, 0xa1, 0xe0, 0x8b, 0x82, 0xfd, 0xf0, 0xfc, 0x66, 0xfa,
+       0x7f, 0xed, 0xa0, 0x5f, 0xe4, 0x7e, 0xb3, 0x59, 0xfe, 0x75, 0xce, 0x26,
+       0x3c, 0xcf, 0xd8, 0x42, 0xb3, 0x0b, 0xee, 0x72, 0xc6, 0xda, 0xbc, 0xcd,
+       0x25, 0xb4, 0xfe, 0xca, 0x27, 0x12, 0xc6, 0xb3, 0xc7, 0xf5, 0x1b, 0x85,
+       0xf9, 0xd5, 0xa1, 0xeb, 0xaf, 0x53, 0x88, 0x6f, 0x34, 0x85, 0xef, 0x2b,
+       0xb9, 0x12, 0xc2, 0x3b, 0xea, 0x92, 0xc7, 0x70, 0x9e, 0x37, 0x73, 0x4d,
+       0x28, 0x6f, 0xc6, 0x41, 0x3e, 0x36, 0xe4, 0x2f, 0xeb, 0xf3, 0xaa, 0x51,
+       0x1f, 0x1a, 0xf3, 0xb9, 0xc7, 0x89, 0x1f, 0xa8, 0xc5, 0xd0, 0xec, 0x62,
+       0xfc, 0x4a, 0x24, 0x4f, 0x2f, 0x90, 0xef, 0x13, 0x1c, 0x46, 0xf8, 0xd9,
+       0x4f, 0x1a, 0xef, 0x8b, 0x2b, 0xf3, 0x2d, 0x86, 0xfa, 0xb8, 0x5c, 0x39,
+       0x44, 0x0f, 0x7b, 0x10, 0xde, 0x2f, 0x67, 0x30, 0xba, 0x78, 0x79, 0x80,
+       0xe0, 0xdd, 0x9c, 0x15, 0xa4, 0xb3, 0xb1, 0x27, 0x13, 0xbc, 0x40, 0x67,
+       0xf0, 0x27, 0x16, 0x18, 0xe0, 0x68, 0x38, 0x67, 0x8c, 0x5f, 0x56, 0x01,
+       0x7e, 0x87, 0x06, 0x3c, 0xf1, 0x5f, 0x70, 0x4f, 0x12, 0xe3, 0x5c, 0x7d,
+       0x23, 0xde, 0x83, 0x73, 0xf8, 0x6b, 0x74, 0x12, 0xc3, 0xf1, 0x6e, 0x4f,
+       0x7f, 0xee, 0x27, 0xa0, 0xa7, 0x34, 0xf8, 0x87, 0xd2, 0xc1, 0xc5, 0xe3,
+       0xff, 0xea, 0xaa, 0x62, 0xc0, 0x7f, 0xbe, 0x76, 0x7f, 0x1f, 0x82, 0xff,
+       0x10, 0x7c, 0x63, 0x0c, 0x52, 0x3b, 0x47, 0xdf, 0x9e, 0x78, 0xc7, 0xf5,
+       0xb3, 0x7a, 0xe2, 0x5b, 0xa3, 0x83, 0x1e, 0xe7, 0xbe, 0xbb, 0x75, 0x4d,
+       0x36, 0xc5, 0xeb, 0xab, 0x76, 0xfa, 0x00, 0xf0, 0xbc, 0x49, 0xf6, 0xde,
+       0x25, 0x04, 0xf1, 0x74, 0x41, 0xbc, 0xf6, 0x2b, 0x46, 0xba, 0x59, 0xa7,
+       0x34, 0xdb, 0x40, 0xee, 0x47, 0x5d, 0x72, 0xdc, 0x06, 0xfe, 0x81, 0x46,
+       0x17, 0x44, 0x6c, 0xcb, 0xd7, 0xdb, 0xfb, 0xff, 0x2a, 0x7c, 0x97, 0x6c,
+       0x10, 0x98, 0x33, 0xe9, 0x12, 0xbc, 0x10, 0xd7, 0x7b, 0x0b, 0x1e, 0x0d,
+       0x0b, 0xae, 0xf3, 0x52, 0x4a, 0x77, 0xbe, 0xcc, 0x4b, 0x20, 0xf7, 0x49,
+       0x15, 0xcb, 0xe3, 0x68, 0x50, 0xf3, 0xd8, 0x7b, 0x57, 0xf9, 0x4c, 0x9f,
+       0x86, 0xca, 0x87, 0x3f, 0xa4, 0xb0, 0xf7, 0x3a, 0xda, 0xcd, 0x2f, 0xa7,
+       0x9f, 0x2f, 0x4f, 0xb5, 0xd2, 0xe6, 0x26, 0x70, 0x3f, 0xd6, 0x00, 0xf9,
+       0x76, 0xf4, 0x7c, 0xf2, 0x86, 0xd9, 0xf0, 0x46, 0x03, 0x91, 0x27, 0xcf,
+       0x46, 0x79, 0x49, 0x36, 0x08, 0x2c, 0x0f, 0xa1, 0xe8, 0xf7, 0x28, 0xdf,
+       0xe7, 0x39, 0xbc, 0xab, 0x84, 0x30, 0xeb, 0xa1, 0x25, 0x83, 0xfb, 0x74,
+       0x32, 0xbb, 0xbf, 0x28, 0x11, 0xfb, 0x93, 0x69, 0x5a, 0x5e, 0x52, 0xd5,
+       0x07, 0xb8, 0xff, 0xc9, 0xac, 0x7e, 0xb1, 0xfb, 0x7a, 0xe3, 0x5f, 0xb4,
+       0xaf, 0xa3, 0x94, 0x56, 0x88, 0xce, 0xff, 0x9c, 0xc8, 0xe3, 0xf2, 0x9a,
+       0xdd, 0x3d, 0xc1, 0xc6, 0xf2, 0x0e, 0x27, 0x14, 0x89, 0x88, 0x8f, 0x37,
+       0xb7, 0x08, 0x5e, 0xcc, 0x8f, 0xa4, 0xfd, 0x3c, 0x94, 0x4e, 0x16, 0x71,
+       0xb2, 0x9d, 0xc8, 0xed, 0xc0, 0xb3, 0x85, 0xcf, 0x34, 0x0d, 0x76, 0x82,
+       0x3d, 0xa8, 0x1a, 0xec, 0x4e, 0xa1, 0xa8, 0x1d, 0xed, 0xbe, 0xb8, 0x42,
+       0xa3, 0x3f, 0x18, 0xaf, 0x46, 0x1b, 0xf0, 0x9f, 0x38, 0x3a, 0xc1, 0x50,
+       0x4f, 0xae, 0xea, 0x65, 0xe8, 0x9f, 0x3a, 0x2d, 0xdb, 0x18, 0x57, 0x70,
+       0x5f, 0x6a, 0x78, 0xde, 0xbb, 0x26, 0xcf, 0x50, 0xcf, 0xa8, 0x1f, 0x6e,
+       0xe8, 0xdf, 0xe7, 0x96, 0x12, 0x43, 0x3d, 0xcb, 0x33, 0xd6, 0xd0, 0xbf,
+       0xef, 0x9a, 0x49, 0x86, 0x7a, 0xff, 0xe6, 0xeb, 0x0c, 0xfd, 0x7f, 0xf4,
+       0xf0, 0x1c, 0xc3, 0xf3, 0x01, 0xde, 0x45, 0x86, 0xe7, 0x97, 0x6d, 0x5b,
+       0x66, 0xa8, 0x0f, 0x6c, 0xb9, 0xcd, 0xd0, 0xff, 0xf2, 0x5d, 0x77, 0x19,
+       0x9e, 0x0f, 0xf6, 0xad, 0x33, 0x3c, 0x1f, 0x72, 0xe8, 0x7e, 0x43, 0x7d,
+       0x68, 0xc7, 0xcf, 0x0d, 0xfd, 0xaf, 0x78, 0x77, 0xb3, 0xe1, 0xf9, 0xb0,
+       0xce, 0x5f, 0x19, 0x9e, 0x8f, 0x38, 0xb9, 0xd3, 0x50, 0x1f, 0xe9, 0xdf,
+       0x6d, 0xe8, 0x7f, 0x55, 0x60, 0x9f, 0xa1, 0x5e, 0x4c, 0x5e, 0x33, 0xf4,
+       0x2f, 0xb5, 0xfe, 0xde, 0x50, 0x2f, 0x57, 0xde, 0x37, 0xf4, 0x1f, 0xe5,
+       0x38, 0x6e, 0x78, 0x3e, 0xc6, 0xf9, 0x99, 0xe1, 0xb9, 0x46, 0x07, 0xe3,
+       0x72, 0xbe, 0x30, 0xb4, 0x8f, 0x77, 0xfd, 0x2d, 0xe4, 0x3d, 0x9d, 0x2a,
+       0x16, 0xe7, 0x80, 0x78, 0x40, 0x5f, 0x78, 0xd4, 0x8c, 0x65, 0x34, 0x69,
+       0x61, 0xf7, 0x3a, 0xa4, 0x03, 0xcb, 0x85, 0x05, 0xee, 0xe2, 0x54, 0xe0,
+       0x8f, 0x47, 0x3d, 0x4d, 0x90, 0x90, 0xd4, 0xe0, 0xf1, 0xff, 0x11, 0xae,
+       0xa6, 0xdf, 0x2c, 0xec, 0x1b, 0xc7, 0xec, 0x27, 0x95, 0xe8, 0xe5, 0xa7,
+       0x96, 0x9f, 0x4a, 0xfd, 0x16, 0x4f, 0x14, 0x25, 0x85, 0xd8, 0x00, 0xa5,
+       0xdb, 0x21, 0x94, 0xee, 0x02, 0x02, 0x96, 0x4a, 0x80, 0x4a, 0xd6, 0x44,
+       0x88, 0xf7, 0x44, 0x61, 0x99, 0x10, 0x48, 0xc4, 0xf6, 0xc4, 0x40, 0x3c,
+       0x96, 0x49, 0x81, 0xde, 0xd8, 0x9e, 0x1c, 0x48, 0xc3, 0x32, 0x25, 0xd0,
+       0x17, 0xcb, 0xd4, 0x40, 0x16, 0x96, 0x8e, 0xc0, 0x65, 0x58, 0xa6, 0x05,
+       0x06, 0x60, 0xd9, 0x2b, 0x30, 0x04, 0xc7, 0xf5, 0x0e, 0x0c, 0xc6, 0x32,
+       0x3d, 0x30, 0x02, 0xdb, 0x33, 0x02, 0xc3, 0xb0, 0xcc, 0x0c, 0x94, 0x62,
+       0x7b, 0x9f, 0x40, 0x31, 0x96, 0xce, 0xc0, 0x38, 0x2c, 0xb3, 0x02, 0x63,
+       0xb0, 0xcc, 0x0e, 0x5c, 0x83, 0xfd, 0xfa, 0x06, 0xae, 0xc6, 0xb2, 0x5f,
+       0xe0, 0x7a, 0x6c, 0xef, 0x1f, 0x98, 0x8e, 0xe5, 0x25, 0x81, 0xb9, 0x58,
+       0xfe, 0x28, 0x30, 0x1b, 0xcb, 0x9c, 0xc0, 0x62, 0x2c, 0x07, 0x04, 0x16,
+       0x62, 0x79, 0x69, 0xe0, 0x26, 0x1c, 0x77, 0x59, 0xe0, 0x46, 0x2c, 0x73,
+       0x03, 0xb7, 0x63, 0xfb, 0xc0, 0xc0, 0xad, 0x58, 0x0e, 0x0a, 0x34, 0x60,
+       0x79, 0x79, 0x60, 0x25, 0x96, 0xae, 0xc0, 0x7a, 0xec, 0x37, 0x38, 0xb0,
+       0x16, 0xcb, 0xbc, 0xc0, 0x7f, 0x61, 0xfb, 0x90, 0xc0, 0x7d, 0x58, 0xe6,
+       0x07, 0x7e, 0x81, 0xed, 0x43, 0x03, 0x3f, 0xc3, 0xb2, 0x20, 0xf0, 0x18,
+       0x96, 0x57, 0x04, 0x36, 0x61, 0x59, 0x18, 0xf8, 0x35, 0x96, 0xc3, 0x02,
+       0x4f, 0x62, 0x39, 0x3c, 0xf0, 0x0c, 0x8e, 0x1b, 0x11, 0xd8, 0x81, 0x65,
+       0x51, 0xe0, 0x05, 0x6c, 0x1f, 0x19, 0x78, 0x1e, 0xcb, 0x2b, 0x03, 0xfb,
+       0xb1, 0xfd, 0xaa, 0x40, 0x3b, 0x96, 0x6a, 0xe0, 0x35, 0x6c, 0x2f, 0x0e,
+       0xbc, 0x82, 0x65, 0x49, 0xe0, 0xf7, 0xd8, 0x5e, 0x1a, 0x38, 0x8c, 0x65,
+       0x59, 0xe0, 0x7d, 0x6c, 0x2f, 0x0f, 0xbc, 0x87, 0x65, 0x45, 0xe0, 0x38,
+       0x96, 0xa3, 0x02, 0xc7, 0xb0, 0x1c, 0x1d, 0xf8, 0x0c, 0xcb, 0x31, 0x81,
+       0x4f, 0xb0, 0x1c, 0x1b, 0xf8, 0x02, 0xc7, 0x8d, 0x0b, 0x9c, 0xc1, 0xb2,
+       0x32, 0xf0, 0x37, 0x6c, 0x1f, 0x1f, 0xf8, 0x06, 0xcb, 0x6e, 0x79, 0x17,
+       0x31, 0x5f, 0xd9, 0x6d, 0x42, 0x7f, 0x96, 0xfb, 0xa9, 0x91, 0xfd, 0x05,
+       0x0f, 0xca, 0x49, 0x33, 0x7f, 0x2f, 0x0e, 0x72, 0xab, 0x31, 0xff, 0xbf,
+       0x5e, 0xf0, 0x62, 0xbc, 0x30, 0xa9, 0xf3, 0x25, 0xa8, 0x9b, 0x0b, 0x2d,
+       0x18, 0x2f, 0xbc, 0x81, 0xf8, 0xf1, 0x3d, 0x81, 0xff, 0x26, 0x9d, 0x76,
+       0x90, 0xa7, 0xed, 0xc3, 0x4e, 0xa4, 0x43, 0xbc, 0xe9, 0xcd, 0x64, 0x5f,
+       0x86, 0x3e, 0xdf, 0xc1, 0xcc, 0xe3, 0x00, 0xe5, 0xe2, 0x29, 0x09, 0xfc,
+       0xd5, 0x09, 0x49, 0xfb, 0x92, 0x41, 0x9f, 0xde, 0x40, 0x9b, 0x21, 0xcf,
+       0x88, 0xa8, 0xe7, 0x30, 0x0f, 0x72, 0x02, 0xcf, 0x83, 0xbc, 0x41, 0xa2,
+       0x0e, 0x16, 0xdd, 0xea, 0x61, 0x98, 0x61, 0x18, 0xf6, 0xf3, 0x59, 0x68,
+       0x7d, 0x46, 0x25, 0x51, 0xf3, 0x68, 0xff, 0xa6, 0x61, 0x16, 0x8c, 0xeb,
+       0x37, 0xe5, 0x51, 0x3f, 0x88, 0x96, 0x77, 0x67, 0xb1, 0x7c, 0xd9, 0x1d,
+       0xa9, 0x4c, 0x5f, 0xfe, 0x8a, 0x97, 0xbb, 0x52, 0x99, 0x1d, 0xeb, 0x29,
+       0x60, 0xf7, 0xfb, 0x33, 0x6e, 0xec, 0xcf, 0xf8, 0xa9, 0x2c, 0xf1, 0x02,
+       0x7e, 0x13, 0x83, 0xc3, 0xdf, 0x07, 0xf2, 0x3c, 0x5b, 0x9b, 0x3f, 0x13,
+       0xf3, 0x63, 0x2f, 0x72, 0xdc, 0x67, 0x29, 0x7c, 0x1c, 0xef, 0xdf, 0x9c,
+       0x5a, 0xd5, 0x96, 0x0a, 0xfb, 0x28, 0x21, 0x39, 0xf5, 0xb6, 0x60, 0x3f,
+       0xda, 0xfe, 0x62, 0x84, 0xf6, 0x7d, 0xe1, 0xda, 0xf7, 0x99, 0x18, 0x3e,
+       0x3c, 0x47, 0x44, 0xee, 0x27, 0x54, 0xc5, 0x4d, 0x3a, 0x8f, 0x9f, 0xf0,
+       0xe6, 0x8a, 0x8e, 0x4b, 0x5f, 0xea, 0x1f, 0xac, 0xbf, 0x15, 0xc1, 0x0f,
+       0x25, 0x64, 0x25, 0xee, 0x37, 0x76, 0xdf, 0x27, 0x95, 0xd7, 0x52, 0x7d,
+       0x38, 0xb1, 0x50, 0x74, 0x51, 0xc9, 0x41, 0x3e, 0x58, 0xb1, 0x6b, 0xe4,
+       0x47, 0xfd, 0xd9, 0xba, 0x90, 0x9f, 0xe9, 0x29, 0x11, 0x31, 0x7e, 0x31,
+       0xa3, 0xe8, 0xf0, 0x81, 0x44, 0x5a, 0x9f, 0xb1, 0x3c, 0x1e, 0xf3, 0xee,
+       0xbb, 0xf7, 0x55, 0x62, 0xc6, 0xe7, 0x13, 0x1c, 0x47, 0x2e, 0x7d, 0x89,
+       0x1e, 0xfd, 0x86, 0xfa, 0xe7, 0x47, 0x7e, 0x64, 0x88, 0x8b, 0xba, 0xd1,
+       0xee, 0xba, 0x89, 0xd3, 0x28, 0x51, 0xcd, 0x7f, 0xed, 0xd4, 0x9e, 0x23,
+       0xbd, 0xb2, 0xb8, 0xef, 0x4d, 0xb0, 0xb8, 0x13, 0xe4, 0x9f, 0x19, 0xe7,
+       0xed, 0x50, 0xcd, 0xde, 0xf3, 0xe5, 0xc7, 0x10, 0xd5, 0x42, 0x54, 0x03,
+       0xdd, 0x33, 0x78, 0xad, 0x87, 0xfd, 0x83, 0xef, 0x4f, 0xac, 0x26, 0x58,
+       0x37, 0x96, 0xf7, 0xa1, 0x70, 0x45, 0xbd, 0xef, 0x89, 0x95, 0xbd, 0x0d,
+       0x02, 0x38, 0xef, 0xce, 0x38, 0xa0, 0xbb, 0x98, 0x5c, 0x3f, 0x39, 0x5f,
+       0x7c, 0x19, 0xe0, 0x29, 0x61, 0xa2, 0x42, 0xa7, 0x0d, 0xec, 0x98, 0x48,
+       0xf0, 0x4c, 0x70, 0x30, 0xfa, 0x8b, 0x2b, 0x52, 0x1d, 0x1e, 0x8a, 0x9f,
+       0xc6, 0xbf, 0x8b, 0x78, 0xcf, 0xb5, 0x3f, 0xbe, 0x40, 0x01, 0xfa, 0xbf,
+       0xc7, 0xd6, 0x2f, 0x15, 0xf8, 0x23, 0xd9, 0xc1, 0xe2, 0x27, 0x8d, 0xed,
+       0xef, 0x61, 0x7c, 0x2b, 0x2e, 0xdf, 0x4f, 0x3c, 0x36, 0x76, 0x7f, 0xee,
+       0xb4, 0x40, 0x1c, 0xdf, 0x8a, 0xe5, 0xaa, 0x15, 0x2e, 0x2c, 0x1b, 0x57,
+       0x14, 0x62, 0xb9, 0x2e, 0xfd, 0x7e, 0x2b, 0xc4, 0x4b, 0xc4, 0x64, 0x09,
+       0x32, 0x81, 0x49, 0x54, 0xc6, 0x3c, 0x8c, 0x07, 0x69, 0xeb, 0x9b, 0xe3,
+       0xe7, 0x58, 0x8b, 0x5d, 0x94, 0x6c, 0x1d, 0x72, 0x25, 0x84, 0x90, 0x44,
+       0x88, 0x33, 0x0c, 0x87, 0xf7, 0x36, 0xe5, 0xca, 0x95, 0xfd, 0x08, 0xf9,
+       0x26, 0x95, 0xe5, 0x7d, 0xbf, 0xe9, 0xf8, 0xc8, 0x06, 0xfc, 0xf0, 0x4d,
+       0xaa, 0x13, 0xeb, 0xa2, 0x89, 0xdd, 0x1b, 0xc7, 0xe4, 0xfb, 0x54, 0xc8,
+       0x4b, 0x88, 0x71, 0x29, 0x25, 0x92, 0x33, 0xd8, 0x8e, 0x7f, 0x49, 0xd8,
+       0xbe, 0x19, 0xfc, 0x91, 0x37, 0x49, 0xe7, 0x86, 0x6b, 0x00, 0x8e, 0x2a,
+       0x7b, 0x1f, 0xa3, 0x81, 0xbf, 0x6f, 0xda, 0x50, 0xdc, 0x9f, 0xc3, 0x55,
+       0x1b, 0x17, 0x82, 0xf7, 0x10, 0x3c, 0x8b, 0xb2, 0x0b, 0xef, 0xad, 0xc5,
+       0x68, 0xda, 0x3f, 0x37, 0x32, 0x5e, 0x07, 0x38, 0xe2, 0x71, 0x9f, 0x40,
+       0x5f, 0x12, 0xa5, 0x2f, 0x3f, 0xdf, 0x37, 0x51, 0x63, 0x4c, 0x30, 0x9f,
+       0x86, 0xdf, 0xb3, 0x92, 0x1f, 0xf3, 0xa9, 0x1a, 0x84, 0xf0, 0x79, 0x97,
+       0x43, 0x38, 0x7e, 0x1a, 0x15, 0x55, 0x39, 0xdf, 0x3d, 0x0a, 0x51, 0xa4,
+       0xbf, 0xea, 0xe5, 0xa9, 0x2d, 0x77, 0x57, 0x08, 0x3d, 0xdb, 0x50, 0xbe,
+       0x62, 0x1d, 0xf2, 0xb9, 0xb8, 0xbc, 0xda, 0x9f, 0xaa, 0x0e, 0x73, 0xd0,
+       0xf9, 0xc7, 0x5c, 0xc9, 0xf3, 0xeb, 0xd3, 0x13, 0x50, 0x0e, 0xd0, 0xf6,
+       0x01, 0xc3, 0x21, 0x9f, 0xce, 0x44, 0x15, 0x3a, 0xc0, 0x2d, 0x41, 0x46,
+       0x7e, 0xa1, 0x40, 0x88, 0x83, 0x3c, 0x5f, 0x62, 0x75, 0xc6, 0x4d, 0x3a,
+       0x4f, 0x1e, 0xc4, 0xda, 0x15, 0x0e, 0x55, 0x32, 0xc3, 0xfd, 0x80, 0x33,
+       0x0e, 0xe0, 0xb5, 0x96, 0x9f, 0x0f, 0xde, 0x50, 0xd6, 0xcb, 0x81, 0x7f,
+       0x57, 0xbf, 0xa0, 0xbc, 0xf0, 0x22, 0xdd, 0x86, 0xf6, 0x6f, 0xd1, 0xe4,
+       0x40, 0x82, 0x15, 0xe5, 0x93, 0xc8, 0xe1, 0xa1, 0x8d, 0x5b, 0xe8, 0x60,
+       0xf2, 0xd8, 0x94, 0x5d, 0x35, 0xd3, 0x31, 0x94, 0x8d, 0x03, 0x3e, 0xa2,
+       0x75, 0x37, 0xc0, 0x8b, 0x58, 0x69, 0x7d, 0x20, 0xd6, 0xe7, 0xe0, 0x73,
+       0xa5, 0xbb, 0x3e, 0x0f, 0xeb, 0x0e, 0xd6, 0x1f, 0x13, 0x69, 0x2e, 0x42,
+       0x0e, 0xd3, 0x71, 0x8b, 0x71, 0x9c, 0xd4, 0x3d, 0xcf, 0x52, 0xac, 0xdb,
+       0xba, 0xd7, 0xad, 0xc3, 0x75, 0x93, 0xba, 0xeb, 0x37, 0x62, 0x3d, 0x9d,
+       0xf5, 0xbf, 0xd8, 0x75, 0xb4, 0xb2, 0xfb, 0xfc, 0xbf, 0x63, 0x72, 0xf2,
+       0x4b, 0x49, 0x8d, 0x4b, 0xa0, 0xf4, 0x3c, 0xf6, 0x96, 0xb9, 0x55, 0xa0,
+       0x0a, 0xc6, 0xdf, 0xb2, 0xb0, 0xaa, 0x8c, 0xea, 0xef, 0x3f, 0xae, 0x78,
+       0x57, 0x05, 0xb9, 0xf4, 0x01, 0x95, 0x27, 0x8d, 0xb4, 0x1c, 0x3b, 0x60,
+       0x7f, 0x22, 0xf8, 0x39, 0xe3, 0x87, 0xee, 0x8f, 0x71, 0xea, 0xe8, 0xf5,
+       0x06, 0x1e, 0xd7, 0x6c, 0xbb, 0xc5, 0x3c, 0x1a, 0xf4, 0x5d, 0xd1, 0xad,
+       0x62, 0xd5, 0x16, 0x84, 0xf7, 0x4a, 0xc3, 0xbd, 0xcf, 0x1a, 0x87, 0x99,
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+       0xf0, 0xa5, 0x8d, 0x06, 0xbf, 0x93, 0xf3, 0xa1, 0xc2, 0xda, 0xba, 0xf7,
+       0x7b, 0x9b, 0x80, 0xfb, 0xfd, 0xa0, 0x9e, 0xc9, 0xdb, 0x0f, 0x96, 0x0b,
+       0x28, 0x6f, 0xbb, 0xf9, 0x34, 0x9e, 0x70, 0x3f, 0xde, 0x97, 0x0c, 0x70,
+       0x9a, 0xb9, 0x5c, 0x27, 0xb7, 0x49, 0x18, 0xb8, 0xd4, 0x5b, 0x88, 0xdb,
+       0x20, 0xd7, 0x23, 0xc1, 0x87, 0x90, 0xbf, 0xd2, 0xfa, 0x97, 0xb6, 0x7e,
+       0x18, 0x97, 0xa5, 0x96, 0x9a, 0xb5, 0x2a, 0x8c, 0x3e, 0xd3, 0xe0, 0x14,
+       0x09, 0x0f, 0x37, 0x44, 0x88, 0xff, 0x6a, 0x70, 0xd2, 0xe0, 0xad, 0xb5,
+       0xff, 0xe9, 0x8e, 0x21, 0x0a, 0xb3, 0xab, 0xbd, 0x06, 0x38, 0xce, 0xba,
+       0x73, 0x28, 0xc6, 0x2b, 0x6f, 0xe0, 0xf1, 0x7a, 0x12, 0x6f, 0xe5, 0xfc,
+       0xc9, 0xfa, 0xcd, 0xa0, 0xeb, 0xec, 0xcc, 0x45, 0x7a, 0x72, 0x02, 0xbd,
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+       0x17, 0x85, 0x07, 0xcc, 0x97, 0xff, 0xa0, 0xfe, 0x80, 0xdd, 0xad, 0xbb,
+       0xff, 0x0c, 0x85, 0x7b, 0x44, 0x3a, 0x8c, 0x00, 0xef, 0x3a, 0x0b, 0xc1,
+       0xf7, 0x2a, 0xfc, 0x5b, 0xed, 0x2c, 0x9e, 0x94, 0x34, 0x0d, 0xe7, 0xad,
+       0xe1, 0xeb, 0x92, 0xa4, 0x19, 0xb8, 0x8f, 0x1a, 0xbe, 0xce, 0x4b, 0x7b,
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+       0xbb, 0xfe, 0xc8, 0x2f, 0xe0, 0x3e, 0x78, 0x93, 0x19, 0xef, 0x4e, 0x16,
+       0x7e, 0xf1, 0x40, 0x01, 0xdc, 0xcb, 0x76, 0x71, 0x3d, 0x46, 0x15, 0x41,
+       0x3b, 0x7c, 0x47, 0xc1, 0x4d, 0xb4, 0x3f, 0x55, 0x80, 0xf9, 0x17, 0x10,
+       0x36, 0x7f, 0x97, 0x76, 0x0f, 0xb2, 0x35, 0x0e, 0xe1, 0x7a, 0xb2, 0x6c,
+       0x4b, 0xd3, 0x08, 0x5a, 0x76, 0xee, 0x59, 0x5a, 0x09, 0xf1, 0x97, 0x13,
+       0x7b, 0xc7, 0x1f, 0x04, 0xff, 0x79, 0x61, 0x34, 0x91, 0xd2, 0xc0, 0xde,
+       0xab, 0xdf, 0x21, 0x23, 0x3c, 0x3c, 0xe6, 0x8f, 0x8c, 0x76, 0x82, 0x14,
+       0xac, 0x8b, 0x3d, 0xeb, 0x0b, 0xa0, 0xae, 0x8b, 0x23, 0x2d, 0xf4, 0x9a,
+       0x83, 0x75, 0xfa, 0xbf, 0xc5, 0xdb, 0x8c, 0x75, 0x3d, 0xbc, 0x4c, 0x7a,
+       0x78, 0x39, 0xcb, 0x8c, 0xf0, 0x72, 0x96, 0x1b, 0xe0, 0x25, 0xbc, 0x68,
+       0xf7, 0x89, 0x3a, 0x78, 0x95, 0x9d, 0x79, 0x29, 0x11, 0xf4, 0xfb, 0x51,
+       0x87, 0x13, 0xe7, 0xab, 0x39, 0xd3, 0x98, 0x02, 0xf0, 0xa9, 0xd9, 0xb3,
+       0x16, 0xcb, 0xc5, 0xdb, 0xa2, 0x3c, 0x1f, 0xe9, 0xd6, 0x5d, 0xda, 0x12,
+       0x6f, 0xa8, 0xd7, 0xed, 0x4a, 0xf3, 0xe8, 0xf5, 0xcb, 0xd9, 0x43, 0x8f,
+       0xc5, 0xc2, 0xf9, 0x97, 0x39, 0x44, 0xcf, 0x47, 0x54, 0x7e, 0x9c, 0x5a,
+       0xa1, 0x36, 0x00, 0x1d, 0x9f, 0x5e, 0x31, 0xba, 0x41, 0x4f, 0xcf, 0x4b,
+       0x5b, 0xb2, 0x3c, 0x36, 0xc3, 0x3c, 0xc6, 0xfa, 0xd9, 0x66, 0x01, 0xed,
+       0x14, 0xd0, 0x33, 0x93, 0xcf, 0x63, 0x2f, 0x2e, 0x73, 0xc8, 0xb8, 0xce,
+       0xa7, 0xdb, 0x98, 0xdf, 0xf9, 0xe9, 0x0a, 0xab, 0x07, 0xd6, 0x39, 0xb5,
+       0x42, 0xf1, 0xb0, 0x75, 0x1d, 0x1e, 0x66, 0x4f, 0x31, 0x78, 0x2d, 0xb9,
+       0x25, 0xc6, 0xf3, 0xd1, 0x90, 0xe0, 0xfe, 0x22, 0xcd, 0xfb, 0xaf, 0xde,
+       0x1f, 0x21, 0xad, 0xe4, 0xb8, 0x95, 0xe0, 0xbb, 0x3b, 0xe7, 0xce, 0xa3,
+       0xbf, 0x23, 0xf2, 0x8b, 0xf4, 0xa5, 0x8c, 0xf2, 0xbd, 0xcd, 0xfc, 0x17,
+       0xa0, 0x1b, 0x2b, 0xfd, 0xdf, 0x39, 0x8c, 0xa7, 0x4a, 0x58, 0xd7, 0xe6,
+       0xad, 0x6b, 0x11, 0x3d, 0x90, 0x57, 0x4c, 0xc8, 0x76, 0xc3, 0x7a, 0x74,
+       0x9c, 0xf3, 0x63, 0x9d, 0x5d, 0x10, 0x59, 0x3f, 0x18, 0xbf, 0x37, 0x31,
+       0x02, 0x62, 0x62, 0x28, 0xa7, 0xd9, 0x7d, 0x88, 0x1b, 0xee, 0x43, 0xe8,
+       0x7c, 0x5d, 0x92, 0x6d, 0x0d, 0xc4, 0x13, 0xb4, 0xfb, 0x90, 0x3a, 0x58,
+       0x88, 0xf6, 0x5d, 0x6a, 0xed, 0x94, 0xdd, 0xb4, 0xe9, 0xf3, 0xd6, 0xbe,
+       0xe7, 0x7d, 0xdf, 0x9c, 0xe2, 0x29, 0x0b, 0xf4, 0x73, 0x8d, 0xb5, 0x59,
+       0x06, 0xa5, 0x5b, 0xd3, 0x32, 0xa0, 0x0c, 0xf8, 0xe9, 0xf3, 0xd6, 0x86,
+       0x14, 0xb0, 0x67, 0x17, 0x8b, 0x67, 0x7f, 0x1c, 0xee, 0xbd, 0xaf, 0x29,
+       0x69, 0x9c, 0x6f, 0xbd, 0x66, 0xbf, 0xd1, 0x6f, 0xf4, 0x6a, 0xfb, 0xcc,
+       0x92, 0x0c, 0x7c, 0x46, 0x6c, 0xdd, 0xe7, 0xa6, 0xf5, 0x53, 0x11, 0xde,
+       0xf3, 0x99, 0xc5, 0xe7, 0xad, 0xdd, 0x7e, 0xb8, 0x62, 0x04, 0xdd, 0x7f,
+       0xed, 0xae, 0x33, 0x32, 0xec, 0x23, 0x39, 0xcd, 0x3d, 0x2b, 0x2d, 0x39,
+       0x78, 0x7e, 0x81, 0xdf, 0x07, 0x2d, 0xda, 0x76, 0x0c, 0xf9, 0xfc, 0xa4,
+       0xd9, 0x73, 0xc9, 0xed, 0xe7, 0xb3, 0xf3, 0x7b, 0xec, 0xd3, 0xe6, 0x30,
+       0xe4, 0x1f, 0x7a, 0x48, 0x07, 0xf0, 0xe7, 0x9c, 0x42, 0xa2, 0x31, 0xec,
+       0xb5, 0xef, 0x53, 0x79, 0xf3, 0xc9, 0x6b, 0x66, 0x02, 0xf7, 0x88, 0xe4,
+       0x5b, 0xda, 0x8b, 0x3e, 0xcf, 0xe4, 0x4f, 0xe7, 0x91, 0xaa, 0x58, 0x80,
+       0xd7, 0x9c, 0xd6, 0xc5, 0x28, 0x7f, 0x3e, 0x79, 0x76, 0xdc, 0x41, 0x96,
+       0x87, 0xd4, 0x5c, 0x00, 0xf4, 0xf1, 0x39, 0x31, 0xe1, 0xfb, 0xee, 0x9f,
+       0x93, 0xdf, 0xc5, 0x0e, 0xd1, 0xc1, 0x6f, 0x5d, 0x9a, 0x96, 0x47, 0xc9,
+       0xbe, 0x73, 0xa3, 0xe5, 0xb9, 0xd0, 0x0d, 0xa6, 0x61, 0x9e, 0x7a, 0x4d,
+       0x53, 0x07, 0xbc, 0x3f, 0x66, 0x21, 0x92, 0x87, 0xcb, 0x25, 0x81, 0x7d,
+       0xb7, 0xc6, 0x2b, 0xa0, 0xfd, 0x52, 0xc3, 0xda, 0x3d, 0xc4, 0xba, 0x12,
+       0xcf, 0xb1, 0x86, 0xc9, 0x23, 0x0f, 0xfd, 0x0f, 0xea, 0xf3, 0x9b, 0x8d,
+       0xf2, 0x69, 0xc1, 0xc3, 0xc6, 0x7a, 0x35, 0x99, 0x94, 0x02, 0x79, 0xde,
+       0xd5, 0x0f, 0x98, 0x21, 0x93, 0x88, 0x2c, 0xd4, 0xcb, 0x3f, 0x0a, 0xbf,
+       0x1b, 0xd3, 0x98, 0xff, 0xb9, 0x80, 0xd4, 0x37, 0x81, 0x5d, 0xf7, 0x88,
+       0xcc, 0xf2, 0xbb, 0xe7, 0x28, 0x44, 0xea, 0x4d, 0xf5, 0xd1, 0xd2, 0xe7,
+       0x1e, 0x29, 0x98, 0x4d, 0xeb, 0xf7, 0xa5, 0x31, 0x7b, 0xec, 0x53, 0xee,
+       0x6f, 0xc0, 0x7b, 0x8c, 0x69, 0xf4, 0xf9, 0xa2, 0x5b, 0xbc, 0xb2, 0x9a,
+       0xdb, 0xf3, 0x7c, 0xc7, 0x5b, 0x87, 0x4c, 0x1d, 0x41, 0x70, 0x3e, 0xe6,
+       0x3f, 0x2d, 0xd2, 0xec, 0x57, 0xe2, 0x84, 0x78, 0x7e, 0x6f, 0xf8, 0x57,
+       0x76, 0xe4, 0xf3, 0xf7, 0x6e, 0x15, 0xf1, 0xfe, 0xa9, 0x37, 0xb4, 0xeb,
+       0xe4, 0xf3, 0xdc, 0x35, 0xc6, 0xf3, 0x5d, 0xe8, 0xfc, 0xa1, 0xe7, 0x25,
+       0xe4, 0x7e, 0x3c, 0xc7, 0xa2, 0x6d, 0x57, 0xa3, 0xff, 0xa6, 0x9d, 0x47,
+       0xc3, 0x97, 0x76, 0x1e, 0xf3, 0xb6, 0xf0, 0xef, 0xfb, 0x6e, 0x4b, 0x13,
+       0x0c, 0x76, 0xdc, 0x2e, 0x0e, 0x3f, 0xcd, 0xff, 0xde, 0x13, 0x52, 0xdf,
+       0x97, 0xc6, 0xec, 0x7a, 0xad, 0xfe, 0x72, 0x48, 0x5d, 0xa3, 0x6f, 0x33,
+       0xe7, 0x6f, 0x4a, 0xf7, 0x7b, 0x80, 0xee, 0x97, 0x5a, 0xfd, 0x15, 0x8c,
+       0x4e, 0x3a, 0x65, 0xfd, 0xbd, 0xa8, 0x1c, 0xec, 0xb7, 0x2f, 0x6d, 0x68,
+       0xe4, 0x7e, 0x16, 0xce, 0x2f, 0xb4, 0xdf, 0xcb, 0xe7, 0xeb, 0x17, 0x15,
+       0x9c, 0xef, 0xf5, 0x70, 0xeb, 0x2e, 0x7d, 0xee, 0xa9, 0x67, 0xc1, 0x2f,
+       0x5d, 0xf4, 0x9b, 0x07, 0x63, 0xe1, 0x52, 0xe8, 0x13, 0xa9, 0x39, 0x05,
+       0xde, 0xb7, 0x58, 0xb2, 0x75, 0x55, 0x2c, 0xc0, 0xe9, 0xa4, 0xe4, 0x89,
+       0x05, 0xba, 0xf9, 0xc4, 0x2b, 0x8e, 0x0e, 0x07, 0x2f, 0x53, 0x2f, 0x0d,
+       0x5e, 0xaa, 0x4d, 0xa0, 0x78, 0xaf, 0xd5, 0xe8, 0xbf, 0x68, 0xe5, 0x04,
+       0xd0, 0xef, 0x7f, 0xd9, 0x6a, 0x56, 0xc0, 0x3f, 0xac, 0xdb, 0x66, 0xf1,
+       0xc1, 0x77, 0x98, 0x6a, 0x5b, 0x17, 0xe2, 0xbd, 0x0d, 0xad, 0x1f, 0x63,
+       0xf5, 0xd5, 0xf8, 0x7e, 0x65, 0xdd, 0x2e, 0xf3, 0x87, 0x7a, 0xbc, 0x2e,
+       0x7a, 0xe2, 0xc1, 0x14, 0xcc, 0xf3, 0x20, 0x9e, 0xde, 0xec, 0x5e, 0xdd,
+       0xd7, 0x1b, 0x3e, 0x21, 0x54, 0xbb, 0xe5, 0xcf, 0x15, 0xe0, 0x2f, 0xd7,
+       0x11, 0x3f, 0xd2, 0x73, 0xe8, 0x38, 0x58, 0x3f, 0x90, 0x80, 0xf2, 0x7a,
+       0xb6, 0x1c, 0xd7, 0xf3, 0xb9, 0x16, 0x3f, 0xad, 0x63, 0x4d, 0xa4, 0xae,
+       0x75, 0xfd, 0x19, 0x88, 0x9f, 0xd6, 0xb5, 0x8e, 0x39, 0x01, 0x7c, 0x5f,
+       0x47, 0xa4, 0x0f, 0xf5, 0xf4, 0x54, 0x03, 0x34, 0x4d, 0xfd, 0x96, 0x2f,
+       0xd2, 0x78, 0xfe, 0xdd, 0x15, 0xe4, 0x0a, 0x90, 0x2f, 0x1a, 0x3c, 0x88,
+       0x37, 0x19, 0xe5, 0x73, 0xc3, 0x93, 0x3f, 0x1d, 0x74, 0x8c, 0xee, 0xe7,
+       0xd4, 0x96, 0xd7, 0x62, 0x05, 0xbd, 0xdf, 0xca, 0xef, 0xdd, 0xcf, 0xb6,
+       0xcc, 0xfd, 0x53, 0xe2, 0x79, 0xf4, 0xc3, 0x69, 0x4a, 0xa7, 0xfa, 0xf7,
+       0x32, 0x34, 0xb9, 0xeb, 0xdc, 0x45, 0x37, 0x90, 0x4a, 0xab, 0x6d, 0xac,
+       0x5c, 0x62, 0xf6, 0xc5, 0x8e, 0xa0, 0x70, 0x5d, 0xb2, 0xc9, 0x8c, 0xef,
+       0x89, 0x2e, 0x79, 0xea, 0xb1, 0xc7, 0x7f, 0x0e, 0xf9, 0x44, 0xef, 0x59,
+       0xf0, 0x1e, 0x64, 0xf1, 0x53, 0x07, 0x8e, 0x0c, 0xa7, 0xf5, 0xc5, 0x3b,
+       0xcc, 0x49, 0x95, 0xec, 0x18, 0x36, 0xb8, 0x17, 0xd6, 0xf0, 0x52, 0x47,
+       0xff, 0x07, 0xf7, 0x14, 0x1a, 0x1e, 0x16, 0x3d, 0x73, 0x40, 0x86, 0xf7,
+       0x68, 0xa0, 0x1d, 0xfc, 0x04, 0x0d, 0x1f, 0x8b, 0x77, 0xb4, 0xcb, 0x64,
+       0x60, 0x4f, 0xf8, 0x95, 0xb6, 0xb4, 0xcb, 0x9d, 0xb6, 0x30, 0x78, 0x69,
+       0x39, 0x56, 0x81, 0xef, 0x1b, 0x3d, 0xf9, 0xb5, 0x0c, 0x78, 0xff, 0x64,
+       0xaf, 0x40, 0x52, 0xb3, 0x7a, 0x8e, 0xaf, 0xd9, 0x74, 0x00, 0xed, 0x18,
+       0x80, 0x13, 0xe2, 0x91, 0xe3, 0xa9, 0x1b, 0x6f, 0x3d, 0xf0, 0xe5, 0x9b,
+       0xb0, 0x3b, 0x1f, 0xfb, 0x29, 0x20, 0xb7, 0x2f, 0x84, 0xaf, 0x77, 0xb8,
+       0x5e, 0xa5, 0x74, 0xfd, 0xf4, 0x6e, 0xba, 0x8f, 0x9a, 0x3f, 0x58, 0x5c,
+       0x00, 0x87, 0x9a, 0xa7, 0x6f, 0x8a, 0x85, 0xf3, 0x9c, 0x90, 0xea, 0x19,
+       0x7d, 0x3f, 0xb2, 0x2a, 0x05, 0xf2, 0xdd, 0x6a, 0xcc, 0x9e, 0x14, 0x05,
+       0x4b, 0xd6, 0x5e, 0xf3, 0xe8, 0xcd, 0x48, 0x77, 0x0b, 0x0e, 0xdf, 0x9c,
+       0xc2, 0xf2, 0x0f, 0xd5, 0x34, 0x9e, 0xe7, 0x91, 0x06, 0xe7, 0x9c, 0xbf,
+       0x71, 0x0a, 0x9e, 0xb3, 0x9a, 0xb8, 0x91, 0xfe, 0x6a, 0x1e, 0x11, 0xab,
+       0x20, 0x1f, 0xe6, 0x2b, 0x89, 0x8c, 0xde, 0x11, 0x86, 0x3f, 0x6e, 0xe3,
+       0xfc, 0x71, 0x62, 0x33, 0x45, 0x2e, 0x3d, 0xe7, 0x09, 0x90, 0x97, 0x3a,
+       0xbf, 0x47, 0x7b, 0xbf, 0xf9, 0xe6, 0xee, 0x78, 0x08, 0xbb, 0x8f, 0xfc,
+       0x8a, 0xdf, 0x47, 0x56, 0xf5, 0x32, 0x19, 0xf4, 0x4b, 0x37, 0xdd, 0x6e,
+       0x59, 0x8d, 0x72, 0xf5, 0xd3, 0x0c, 0x35, 0x15, 0xee, 0x29, 0x29, 0x1c,
+       0x34, 0x39, 0x8a, 0xf2, 0x55, 0x3c, 0x5c, 0x9e, 0xca, 0xf0, 0xc4, 0xe4,
+       0x31, 0x8e, 0xa3, 0xf4, 0x57, 0x0a, 0xed, 0xd0, 0xbf, 0xc3, 0x8c, 0xf7,
+       0xc3, 0xba, 0x71, 0x5c, 0x7e, 0xb2, 0xf5, 0x97, 0xf3, 0xf5, 0xe9, 0xbe,
+       0xa3, 0xc1, 0x1e, 0x39, 0x91, 0x12, 0xfe, 0xbd, 0xa0, 0xc7, 0x7b, 0x09,
+       0xda, 0xfe, 0x3a, 0x88, 0x8e, 0xce, 0x74, 0x7c, 0xce, 0xf8, 0x7e, 0xcb,
+       0x5a, 0xc6, 0xe7, 0x1a, 0xdf, 0x7b, 0xaf, 0x1e, 0x0d, 0xcf, 0xbf, 0x7c,
+       0x9b, 0xf1, 0x11, 0x8c, 0x03, 0x7d, 0x44, 0xf7, 0xe5, 0x4b, 0xc5, 0xe7,
+       0xed, 0x93, 0x05, 0x94, 0x0b, 0x16, 0xe2, 0x0b, 0xc7, 0xdf, 0x5b, 0xcc,
+       0x9c, 0xbf, 0x8d, 0xcf, 0xa9, 0xc5, 0x8e, 0xf6, 0x9c, 0x46, 0x27, 0x74,
+       0xff, 0x12, 0x7c, 0x97, 0x2c, 0x48, 0x2f, 0x74, 0x9d, 0x04, 0xc4, 0x03,
+       0xda, 0x2b, 0xd5, 0x0f, 0xd0, 0xf1, 0x3a, 0x3b, 0xbb, 0x0e, 0xd6, 0xc5,
+       0x7e, 0x72, 0xb0, 0x3d, 0x2b, 0xc8, 0xc7, 0x0b, 0xb8, 0x3c, 0xb8, 0xb9,
+       0x17, 0x95, 0x07, 0x97, 0x05, 0xe5, 0x01, 0xd9, 0x98, 0x7c, 0x51, 0xf1,
+       0x81, 0x25, 0x66, 0xef, 0xe3, 0x3f, 0x07, 0xfe, 0xa5, 0xfc, 0xea, 0x71,
+       0x02, 0xff, 0x9a, 0xf1, 0xfd, 0x9b, 0xcf, 0xb6, 0xef, 0x3f, 0x72, 0x1d,
+       0xa5, 0xf3, 0xcf, 0x5a, 0x34, 0xbe, 0x35, 0xca, 0xd3, 0x50, 0xbe, 0xad,
+       0xd9, 0x79, 0x33, 0xc6, 0x09, 0x43, 0xf9, 0xf6, 0xb3, 0xf4, 0x7a, 0x12,
+       0x96, 0x6f, 0xd3, 0xf9, 0xfb, 0x73, 0xa1, 0x7c, 0x9b, 0xde, 0xf9, 0x1f,
+       0x95, 0xa7, 0x1a, 0xfc, 0x1e, 0x09, 0x81, 0x1f, 0x95, 0x8f, 0xbf, 0xdc,
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+       0xa4, 0x7f, 0x6f, 0x93, 0x82, 0x9e, 0x74, 0xa8, 0xd1, 0x9f, 0x46, 0x77,
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+       0x27, 0xcb, 0x4d, 0x20, 0x27, 0xb4, 0x76, 0x7f, 0x14, 0x8b, 0xab, 0x75,
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+       0xcb, 0xc2, 0xe2, 0xc1, 0x7b, 0xed, 0x98, 0x4f, 0xd7, 0x95, 0xc1, 0xde,
+       0x8b, 0x69, 0xd8, 0xf3, 0xf5, 0x20, 0xcc, 0xdf, 0x26, 0x8d, 0x88, 0xb7,
+       0x84, 0xde, 0xcc, 0xef, 0x38, 0xdb, 0xf6, 0xb7, 0x3f, 0xe2, 0x7b, 0xb6,
+       0x6d, 0xf4, 0x54, 0xa0, 0x6f, 0xf7, 0xc6, 0xa0, 0x3d, 0x5e, 0xb7, 0x3b,
+       0xca, 0x0b, 0x4e, 0x6a, 0xd7, 0x9e, 0xaf, 0x0b, 0xf4, 0xf7, 0x18, 0xdf,
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+       0x75, 0xc5, 0xb3, 0x3c, 0x9b, 0xba, 0x17, 0x86, 0x3d, 0xb6, 0x92, 0xae,
+       0xbf, 0xb4, 0xb5, 0x5d, 0x86, 0xf7, 0x77, 0x4a, 0x5f, 0xfc, 0xfb, 0x20,
+       0x90, 0x37, 0x5d, 0x3b, 0x99, 0x1d, 0x71, 0xda, 0xdc, 0xf9, 0x28, 0x71,
+       0x11, 0x92, 0xd1, 0xfb, 0x8e, 0xbb, 0xcd, 0x14, 0x5f, 0xa7, 0xc1, 0xb6,
+       0xa3, 0xbc, 0xf2, 0x7c, 0xef, 0x3d, 0xe3, 0xe1, 0x9e, 0xa3, 0x27, 0x5c,
+       0x18, 0x1c, 0xba, 0x28, 0x1c, 0xe0, 0x5c, 0x14, 0x2e, 0x35, 0x20, 0x27,
+       0x23, 0xc1, 0x23, 0xbf, 0x37, 0xfb, 0x4e, 0xcf, 0x0f, 0x0f, 0x1e, 0x67,
+       0x66, 0xc2, 0xfa, 0x4b, 0xda, 0xae, 0xc0, 0x7b, 0x88, 0x20, 0x5c, 0x04,
+       0x95, 0xb5, 0xdb, 0xbd, 0x56, 0x01, 0xcf, 0xcf, 0xda, 0xf7, 0x7e, 0x3d,
+       0x08, 0xe4, 0xf1, 0x67, 0x2d, 0x2b, 0x51, 0xbf, 0x5f, 0xe8, 0xdc, 0xd7,
+       0xfc, 0x60, 0xe9, 0xe0, 0x9f, 0x3d, 0xb7, 0xe0, 0xbb, 0x98, 0x73, 0x2f,
+       0xfb, 0xc1, 0x9e, 0x9b, 0xd1, 0x7f, 0x00, 0xf4, 0x53, 0x72, 0x4f, 0x3e,
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+       0xb9, 0x3b, 0x7e, 0xb0, 0xf8, 0x3e, 0xff, 0xb9, 0x35, 0x3b, 0xa8, 0xc3,
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+       0x56, 0xb0, 0xf6, 0x42, 0xa3, 0x9f, 0x31, 0x3d, 0xc4, 0x3f, 0xb8, 0x76,
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+       0xcf, 0xf4, 0x1b, 0x04, 0xd2, 0xac, 0x8b, 0x6f, 0x4e, 0x09, 0x99, 0xef,
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+       0x77, 0x5a, 0x84, 0x65, 0x08, 0x0f, 0x52, 0x2c, 0xf2, 0xf7, 0x8d, 0x2e,
+       0x00, 0x3f, 0xc2, 0xe0, 0xdd, 0x31, 0x79, 0x30, 0xcb, 0x33, 0x96, 0x5c,
+       0x0c, 0x7e, 0x53, 0x97, 0xba, 0x30, 0x6e, 0xca, 0xfd, 0x50, 0x33, 0x1f,
+       0x6f, 0xb6, 0xad, 0xe9, 0x00, 0xbe, 0x35, 0x13, 0xa3, 0xff, 0xa9, 0xf9,
+       0x91, 0x91, 0xe0, 0x4c, 0xb8, 0x5f, 0x8a, 0xf3, 0x64, 0x07, 0xe1, 0x6e,
+       0x56, 0x45, 0xf4, 0x4b, 0x75, 0xf3, 0x21, 0x3c, 0x34, 0x7c, 0x7c, 0x57,
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+       0x2b, 0x17, 0x5a, 0x67, 0x2f, 0x86, 0x7b, 0x08, 0x2b, 0xe4, 0xbd, 0xd3,
+       0x79, 0x27, 0x6e, 0x60, 0xef, 0x91, 0x58, 0x73, 0x05, 0x84, 0x63, 0x55,
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+       0x56, 0x93, 0x7a, 0xb4, 0x3b, 0xc9, 0xb7, 0xe7, 0xce, 0x15, 0x15, 0xe0,
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+       0xa0, 0x02, 0xf9, 0x50, 0x1f, 0x07, 0xf5, 0x1a, 0xeb, 0xf0, 0x77, 0x65,
+       0x4a, 0x70, 0x9e, 0x0b, 0xf5, 0x8f, 0x24, 0x1f, 0xfe, 0xd5, 0xe5, 0x9f,
+       0xa8, 0x3c, 0xfa, 0x90, 0x22, 0xfd, 0x18, 0x94, 0x98, 0x3f, 0x43, 0x24,
+       0xbd, 0xff, 0x38, 0xab, 0x8d, 0xc1, 0xb1, 0x6e, 0x89, 0xe0, 0xcd, 0x46,
+       0x3a, 0xf2, 0x99, 0xf5, 0xf7, 0xc0, 0x4f, 0x70, 0xba, 0xfe, 0xd3, 0x1d,
+       0x43, 0x50, 0xce, 0x15, 0xdf, 0x3b, 0x30, 0x8e, 0xf9, 0xb5, 0xf9, 0x98,
+       0xd7, 0x53, 0xc7, 0xed, 0xfd, 0xb3, 0x1e, 0x67, 0x1c, 0xc4, 0x73, 0xce,
+       0xb6, 0xf5, 0x8d, 0x83, 0x78, 0xcd, 0xd9, 0x43, 0xa5, 0xb1, 0xe1, 0xf2,
+       0x79, 0x0e, 0x73, 0xbf, 0xf2, 0xf7, 0x2b, 0xac, 0x58, 0x76, 0x95, 0x09,
+       0xcd, 0x62, 0x1c, 0xbe, 0x7f, 0x32, 0x01, 0xf5, 0x70, 0x59, 0x14, 0x01,
+       0xb9, 0x13, 0x3a, 0x6e, 0x75, 0xba, 0x16, 0x97, 0xa9, 0x97, 0x31, 0x8e,
+       0x4f, 0x58, 0x3e, 0x7e, 0x35, 0x3f, 0xc7, 0x02, 0x3a, 0x34, 0x2e, 0x41,
+       0x87, 0xb7, 0x0d, 0xe3, 0x3f, 0x91, 0x06, 0xf5, 0xc4, 0x03, 0xfc, 0x7d,
+       0xa8, 0xbb, 0x57, 0xf9, 0xbe, 0xf0, 0x05, 0x3f, 0x16, 0xe0, 0x7a, 0x38,
+       0xaa, 0xb3, 0x22, 0xdc, 0x77, 0x0a, 0x7f, 0xc6, 0xe5, 0x6a, 0xe5, 0xbe,
+       0x6f, 0x64, 0x88, 0x1f, 0x4c, 0x6a, 0xcb, 0xc2, 0xef, 0x4c, 0x4e, 0x2a,
+       0x33, 0xbe, 0x0f, 0x78, 0x5f, 0x3a, 0xf7, 0xcf, 0x87, 0x90, 0x21, 0xb0,
+       0xaf, 0xca, 0x7d, 0x63, 0x62, 0x87, 0x01, 0x5e, 0x0e, 0x89, 0xae, 0x28,
+       0x0a, 0xdf, 0xba, 0xb6, 0x33, 0xb2, 0x3b, 0xcc, 0xfd, 0x5c, 0x28, 0x3c,
+       0x61, 0x7e, 0x88, 0x23, 0x1f, 0x37, 0xbb, 0xaa, 0x01, 0x9e, 0xc7, 0xef,
+       0x8e, 0xc2, 0xef, 0x00, 0xbc, 0xc1, 0xef, 0x8b, 0x72, 0xf9, 0xf7, 0x21,
+       0xe1, 0x13, 0x42, 0x10, 0x3f, 0xdb, 0x9c, 0xce, 0xee, 0x21, 0xbe, 0x4e,
+       0x67, 0x71, 0xf4, 0x6b, 0x2a, 0x8b, 0xcd, 0xc9, 0x74, 0xdd, 0xdc, 0x56,
+       0x65, 0x30, 0xe4, 0x97, 0xf5, 0xe2, 0xfd, 0xbf, 0x4e, 0x77, 0xe2, 0xf3,
+       0xde, 0x7c, 0x9c, 0xd6, 0xaf, 0xd7, 0x12, 0xd6, 0xef, 0x98, 0xac, 0xd4,
+       0x86, 0x3b, 0x7f, 0x46, 0x26, 0xa3, 0x9f, 0x05, 0xc4, 0xf5, 0xe3, 0x42,
+       0xe1, 0x87, 0x87, 0xb7, 0xe2, 0x7b, 0xed, 0x3e, 0x78, 0x3f, 0xee, 0x6c,
+       0x99, 0xc0, 0xdf, 0x9f, 0x09, 0xa5, 0x6b, 0x82, 0xfc, 0x71, 0x76, 0xb4,
+       0xe0, 0x05, 0xfd, 0x0b, 0x7e, 0x2c, 0xd6, 0x2b, 0x05, 0xd4, 0xff, 0x6f,
+       0x68, 0x79, 0x15, 0x93, 0x98, 0xbe, 0xd4, 0xe8, 0x3e, 0x14, 0xce, 0x6f,
+       0x71, 0xfa, 0xd5, 0xd6, 0xef, 0xe2, 0x70, 0x7f, 0x9b, 0xd3, 0x87, 0x06,
+       0x67, 0x0d, 0xbe, 0xa1, 0xfb, 0xd5, 0xfa, 0x53, 0x79, 0x75, 0x95, 0x3e,
+       0xde, 0x32, 0x71, 0xd7, 0xe0, 0xa7, 0xc1, 0x3e, 0xa9, 0x6d, 0x13, 0x14,
+       0x13, 0x9d, 0xaa, 0x56, 0xea, 0x94, 0x81, 0x0f, 0xeb, 0x76, 0xdd, 0x67,
+       0x86, 0xfb, 0x85, 0xe9, 0xfc, 0x77, 0x5a, 0x88, 0x54, 0x35, 0x48, 0x7f,
+       0xbf, 0xfb, 0x75, 0xba, 0x84, 0xf3, 0xed, 0xcf, 0x1b, 0x81, 0xf6, 0xe3,
+       0x17, 0x1b, 0x98, 0x7d, 0xac, 0xce, 0x3b, 0x13, 0x0b, 0x76, 0xd0, 0x1b,
+       0x26, 0xd7, 0x5b, 0x23, 0x80, 0x1f, 0xdf, 0x14, 0x0d, 0xdf, 0x37, 0x0f,
+       0x2d, 0xdf, 0x5f, 0xa1, 0x2c, 0x2a, 0x33, 0xeb, 0xe7, 0xcd, 0x62, 0x7e,
+       0xd2, 0x92, 0x62, 0x33, 0x84, 0x87, 0xae, 0x5f, 0xd2, 0x6e, 0x4e, 0xd5,
+       0xd1, 0xd3, 0xd7, 0x90, 0x8f, 0x35, 0x34, 0xd8, 0xde, 0x6b, 0x89, 0x13,
+       0xf3, 0x18, 0xe9, 0x7a, 0xb8, 0x0f, 0xcf, 0x3d, 0x16, 0x02, 0xf9, 0x4b,
+       0xb9, 0x2d, 0x1d, 0x25, 0x31, 0xf4, 0xf9, 0xf5, 0xf5, 0xf1, 0x8c, 0x0e,
+       0x6b, 0x5a, 0xda, 0x65, 0xac, 0xb3, 0xef, 0x0d, 0x6b, 0xeb, 0x69, 0xeb,
+       0x84, 0xf2, 0xd3, 0xe4, 0xca, 0x18, 0x43, 0x7d, 0x6e, 0x69, 0x67, 0x3a,
+       0xc0, 0xa5, 0xd2, 0xe2, 0x5b, 0xee, 0x0a, 0x43, 0xa7, 0xf7, 0x67, 0x74,
+       0xc7, 0x55, 0xbf, 0x9b, 0x9e, 0x50, 0x29, 0xdd, 0x0e, 0xfa, 0xff, 0x41,
+       0x4f, 0x9c, 0xa9, 0x08, 0xf7, 0x3d, 0xd4, 0xd9, 0x1c, 0x6e, 0x3a, 0xfd,
+       0x90, 0x1a, 0x4e, 0x3f, 0x2c, 0x5b, 0xe9, 0x4c, 0x05, 0xf8, 0x2f, 0xdb,
+       0xd3, 0x37, 0x15, 0x98, 0x63, 0xd9, 0x2b, 0xe5, 0x29, 0xe1, 0xf4, 0xc3,
+       0x3b, 0x2b, 0xd8, 0xfd, 0xe1, 0x51, 0x9e, 0x7f, 0xd9, 0x35, 0x99, 0xea,
+       0x87, 0xcb, 0x75, 0xfa, 0x61, 0x72, 0x14, 0xd2, 0x47, 0xe8, 0xb8, 0x71,
+       0x19, 0xda, 0x77, 0x55, 0x2e, 0xa0, 0x1f, 0x34, 0x7c, 0xfd, 0x87, 0xe5,
+       0xcc, 0x3b, 0xa0, 0x1f, 0xc2, 0xf0, 0xf5, 0xcc, 0x0c, 0xa3, 0x7e, 0x98,
+       0xda, 0x36, 0x1b, 0xf5, 0xc3, 0xd4, 0xc9, 0x22, 0x71, 0xea, 0xe2, 0x71,
+       0x53, 0x32, 0x2e, 0xa4, 0x1f, 0x8a, 0x53, 0xa6, 0x63, 0xdd, 0xec, 0x8a,
+       0x09, 0x43, 0x37, 0xef, 0x70, 0xbf, 0x04, 0xe0, 0x0a, 0x25, 0xac, 0x03,
+       0x7a, 0xe2, 0xee, 0x0c, 0x26, 0xf7, 0x43, 0xf5, 0x45, 0x24, 0x79, 0x9e,
+       0x7d, 0xb1, 0xf2, 0xfc, 0x7f, 0x08, 0xce, 0x9a, 0x3c, 0x5f, 0x36, 0x85,
+       0xbd, 0xcf, 0xdf, 0x93, 0x0e, 0x09, 0xca, 0xeb, 0x65, 0xd3, 0x05, 0xfc,
+       0x1d, 0x93, 0x65, 0x7b, 0x98, 0x3c, 0x5f, 0x76, 0x03, 0x8f, 0x4b, 0x86,
+       0xc8, 0xd7, 0x2a, 0x90, 0xaf, 0xf9, 0x7a, 0xf9, 0xca, 0xc6, 0xd7, 0xba,
+       0x99, 0x3e, 0xa8, 0xdb, 0x95, 0xf5, 0xd3, 0x19, 0xf4, 0xf9, 0x75, 0xcd,
+       0x66, 0x97, 0x95, 0xf6, 0xbf, 0x2e, 0x28, 0x6f, 0x0b, 0xf4, 0xf2, 0xf6,
+       0xee, 0x0c, 0x49, 0x83, 0x73, 0xa6, 0x12, 0x06, 0xbf, 0xd3, 0x66, 0xc4,
+       0x10, 0xa7, 0x51, 0x5e, 0xf5, 0x03, 0x39, 0x75, 0x7c, 0xf0, 0xcb, 0xb9,
+       0xcf, 0x00, 0xdd, 0xbf, 0xc1, 0xde, 0x37, 0xfb, 0x33, 0xd7, 0xe3, 0xaf,
+       0x0f, 0x7e, 0x39, 0x1f, 0xe2, 0xe9, 0x1f, 0xf1, 0x79, 0x5b, 0x33, 0x18,
+       0x5e, 0x4e, 0xaf, 0x20, 0x8b, 0xca, 0x28, 0x1c, 0x4a, 0xe7, 0x31, 0x7b,
+       0x78, 0xe9, 0x76, 0x11, 0xe1, 0x50, 0xdb, 0xca, 0xec, 0xbc, 0xda, 0x6d,
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+       0x55, 0x5a, 0xfc, 0x07, 0x61, 0x7c, 0xe5, 0x13, 0x82, 0x6b, 0x13, 0xca,
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+       0x5b, 0x48, 0xbb, 0x6b, 0x2d, 0xde, 0x67, 0x2c, 0x85, 0xb8, 0xb3, 0xce,
+       0x1f, 0xf9, 0x3d, 0xe7, 0x93, 0xf9, 0xa2, 0x2f, 0xf7, 0x19, 0xc8, 0x0f,
+       0x7c, 0x4b, 0x0c, 0xfb, 0xbb, 0x67, 0x5a, 0xbf, 0x6e, 0x38, 0xd4, 0x7c,
+       0x4f, 0x38, 0x1c, 0xa6, 0x70, 0xc8, 0xff, 0xe7, 0xe1, 0x50, 0xd7, 0x76,
+       0x1f, 0xe6, 0xdf, 0x7c, 0xdf, 0xf3, 0xbf, 0x93, 0xc1, 0xe3, 0xed, 0x79,
+       0x24, 0x1f, 0xf8, 0xe5, 0xcf, 0x26, 0x15, 0xf9, 0xdf, 0xf3, 0xaa, 0x88,
+       0xef, 0x17, 0xcf, 0xbb, 0xaf, 0x7f, 0xaa, 0x3e, 0x4f, 0xe9, 0x38, 0x87,
+       0xc3, 0x1b, 0x26, 0x77, 0x53, 0x1a, 0xf4, 0xab, 0x65, 0xef, 0x21, 0x2f,
+       0xd8, 0xb8, 0xe3, 0x00, 0xbc, 0x22, 0x3e, 0xa3, 0x85, 0x0c, 0x86, 0xb0,
+       0xfd, 0x82, 0x87, 0x8d, 0x7a, 0xb2, 0x5b, 0x2f, 0xb7, 0x3a, 0x51, 0xef,
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+       0x6c, 0x6e, 0x9e, 0xc5, 0x0d, 0xf7, 0xaf, 0x87, 0xa3, 0xfc, 0x28, 0xcf,
+       0x34, 0x3a, 0xb4, 0x67, 0xb2, 0xdf, 0x8f, 0x8b, 0xc9, 0x64, 0xeb, 0x1e,
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+       0x35, 0xa0, 0x4e, 0xf1, 0x00, 0xdf, 0xd5, 0xd8, 0x3f, 0xec, 0xeb, 0x0a,
+       0x0e, 0x77, 0x8c, 0xcf, 0xd4, 0xed, 0x62, 0x78, 0xaa, 0xa3, 0x78, 0x01,
+       0x3e, 0xab, 0xa0, 0xf6, 0x2e, 0xe8, 0x91, 0xeb, 0xa9, 0xde, 0xc1, 0xfb,
+       0xb2, 0xb6, 0x76, 0x33, 0xf4, 0xaf, 0xa1, 0xfd, 0x12, 0x51, 0xee, 0xb8,
+       0xd0, 0xdf, 0xd5, 0xf4, 0x13, 0xdc, 0xdf, 0x15, 0xa7, 0xe8, 0xf0, 0xb6,
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+       0xef, 0x7c, 0x78, 0x8b, 0x84, 0x2f, 0xcd, 0x7e, 0xb8, 0x58, 0xbc, 0x69,
+       0xf0, 0xb0, 0x67, 0x1a, 0xf1, 0x77, 0x38, 0xaa, 0xa3, 0x72, 0x08, 0xde,
+       0x53, 0xb1, 0xdf, 0x03, 0x22, 0x6d, 0xf1, 0x78, 0xaf, 0xf2, 0x51, 0x73,
+       0x5f, 0xc4, 0x63, 0x6f, 0x2e, 0x67, 0x43, 0xe9, 0x1b, 0xec, 0x7d, 0xa7,
+       0x2e, 0xbe, 0x74, 0x35, 0x6c, 0x1c, 0x3f, 0x60, 0x1f, 0x85, 0x79, 0x72,
+       0xb8, 0x6e, 0x36, 0xb3, 0x87, 0xf4, 0xf2, 0x25, 0xd4, 0x8f, 0xae, 0x23,
+       0x1d, 0x68, 0xd7, 0x24, 0xa7, 0xb9, 0x7f, 0x9d, 0xae, 0xcb, 0x8b, 0x9b,
+       0xca, 0xf3, 0x57, 0xba, 0xef, 0x75, 0x83, 0xfd, 0xe6, 0x67, 0x9c, 0xa7,
+       0x1f, 0x71, 0x94, 0xe0, 0xfd, 0x8f, 0x96, 0x57, 0x0b, 0xbf, 0x20, 0x85,
+       0xf9, 0x60, 0xbc, 0xbe, 0x3f, 0xa3, 0xe0, 0xe8, 0x0c, 0x7a, 0xde, 0x2f,
+       0xd6, 0x88, 0xf8, 0x9e, 0xf2, 0xb5, 0x26, 0xe7, 0x91, 0x22, 0xe0, 0xe3,
+       0x75, 0x66, 0x02, 0x74, 0xf9, 0xc5, 0xeb, 0x66, 0x95, 0xd9, 0xa1, 0x31,
+       0x28, 0x87, 0x67, 0xbf, 0x71, 0xdc, 0x0c, 0xa1, 0x91, 0xd9, 0x90, 0x5f,
+       0x40, 0xfb, 0xcd, 0xbe, 0x93, 0xc9, 0xdb, 0xe3, 0x30, 0x19, 0x6d, 0xfb,
+       0x03, 0xd5, 0x63, 0x2a, 0x7c, 0xbf, 0x84, 0xb4, 0x0c, 0x85, 0xfc, 0xfd,
+       0xc9, 0xae, 0xf6, 0x72, 0xc8, 0xdf, 0x9e, 0x92, 0x7f, 0x78, 0x15, 0xdc,
+       0xd3, 0x5d, 0x53, 0xaa, 0x1c, 0x39, 0x02, 0xf0, 0x5d, 0x2b, 0x12, 0x80,
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+       0xb7, 0xb9, 0x13, 0xed, 0x36, 0xb8, 0xa7, 0x1b, 0x97, 0x23, 0x06, 0xf3,
+       0x7b, 0x09, 0xbc, 0x0f, 0xd5, 0xb1, 0x0a, 0xe4, 0xf7, 0x8c, 0xfa, 0x1b,
+       0xa7, 0xc0, 0x7e, 0x6b, 0xa8, 0x5e, 0x80, 0xb8, 0x6b, 0x4d, 0xdb, 0xe1,
+       0xf2, 0x54, 0xa8, 0x6f, 0x14, 0xf0, 0xf7, 0xd4, 0xea, 0x3c, 0x6e, 0x19,
+       0x5e, 0x85, 0xea, 0x78, 0xf8, 0x8c, 0x0c, 0xf1, 0x8f, 0x6a, 0xda, 0x0f,
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+       0xbd, 0xce, 0xde, 0x13, 0xaa, 0x2e, 0x5c, 0x79, 0x10, 0xe4, 0x53, 0x35,
+       0x1d, 0x47, 0x1f, 0x93, 0x8e, 0x2d, 0x37, 0xe2, 0x7c, 0x0b, 0x37, 0x0a,
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+       0xa5, 0xd1, 0xf9, 0xe7, 0x8a, 0x9d, 0xe5, 0x98, 0x6f, 0x7d, 0xbb, 0xa0,
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+       0xb7, 0xb2, 0xfb, 0x66, 0x81, 0xd7, 0xb9, 0x5d, 0xa8, 0xe9, 0xc7, 0xc7,
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+       0x24, 0x67, 0x81, 0x4b, 0x54, 0xb7, 0xeb, 0x8c, 0x0c, 0x76, 0xde, 0x47,
+       0x2b, 0xe0, 0x03, 0x34, 0x14, 0x6f, 0x3c, 0x0f, 0x6e, 0xbf, 0xe7, 0xb8,
+       0xdc, 0xa9, 0x93, 0x53, 0xbe, 0xcc, 0xbe, 0x48, 0x8f, 0xf3, 0x76, 0x15,
+       0x23, 0x9f, 0xcf, 0x27, 0x55, 0x78, 0x2f, 0xee, 0x5e, 0xc9, 0xf4, 0xf2,
+       0xb1, 0x55, 0x51, 0x5e, 0x01, 0xec, 0x11, 0xb3, 0x82, 0x7a, 0x73, 0xff,
+       0xaa, 0x1f, 0x3d, 0x04, 0xe7, 0x3f, 0xfd, 0x94, 0x19, 0xef, 0x4b, 0x4f,
+       0x67, 0x74, 0x62, 0x7c, 0xf6, 0xc4, 0x46, 0x33, 0x7e, 0x3f, 0xa4, 0x61,
+       0xa3, 0x88, 0x72, 0xe4, 0xc4, 0x76, 0x16, 0x17, 0x12, 0x1f, 0x99, 0x52,
+       0x91, 0x06, 0xf0, 0xa3, 0x72, 0x00, 0xe8, 0x6e, 0xff, 0xc6, 0x52, 0x19,
+       0xe4, 0xe1, 0x09, 0xaf, 0x80, 0xe3, 0x4b, 0x1f, 0xb9, 0x39, 0x85, 0xc5,
+       0x7d, 0x8d, 0xf2, 0xa3, 0xda, 0xb9, 0x08, 0xe5, 0xc5, 0x23, 0x51, 0x4c,
+       0x3e, 0x2c, 0x78, 0x38, 0xfc, 0xfd, 0x6a, 0x44, 0x79, 0xb1, 0xbc, 0x82,
+       0xc9, 0xf7, 0x10, 0x79, 0xb0, 0x34, 0xbd, 0x09, 0xe3, 0x7e, 0xa1, 0x72,
+       0xa2, 0x8e, 0xd8, 0x34, 0xf9, 0x90, 0x07, 0xf5, 0x0e, 0x5f, 0x1a, 0xd2,
+       0x6f, 0xed, 0xeb, 0x66, 0x02, 0xf6, 0x5d, 0xad, 0xa4, 0xcc, 0x7c, 0x18,
+       0xe8, 0x66, 0x46, 0x14, 0xdc, 0x24, 0x53, 0xbe, 0xf0, 0x1d, 0x00, 0xf9,
+       0xf6, 0x85, 0x57, 0x70, 0x7a, 0xe8, 0xf3, 0xeb, 0x67, 0x3d, 0x3f, 0x14,
+       0xe0, 0xf7, 0x31, 0xc0, 0x1b, 0xf8, 0x62, 0x43, 0x22, 0xde, 0xaf, 0x56,
+       0x7b, 0x67, 0x23, 0x5c, 0xb5, 0x7c, 0xc4, 0x05, 0x0f, 0x1b, 0xe9, 0x59,
+       0xcb, 0x7b, 0x9a, 0xee, 0x16, 0x83, 0xef, 0xfb, 0xd0, 0xff, 0x5d, 0x5f,
+       0x13, 0x43, 0x54, 0x5d, 0xbf, 0xa3, 0x77, 0x52, 0xba, 0xa4, 0xeb, 0xcd,
+       0xda, 0x25, 0x78, 0xe1, 0x3b, 0x48, 0x47, 0xef, 0x3c, 0x76, 0xf0, 0xe6,
+       0x7c, 0xac, 0x2b, 0x40, 0x87, 0xb5, 0xb7, 0x70, 0xbd, 0xba, 0xc1, 0x8e,
+       0x74, 0x7b, 0xf4, 0xd6, 0x33, 0xab, 0x80, 0x2e, 0x67, 0xde, 0x21, 0xe0,
+       0xfe, 0x89, 0xc7, 0xdd, 0x04, 0x7a, 0xa5, 0xf6, 0x61, 0xc1, 0x09, 0x71,
+       0xcd, 0x05, 0x77, 0xb0, 0xf1, 0x0b, 0xe8, 0x78, 0xa0, 0x97, 0xa3, 0x3f,
+       0x63, 0xf4, 0x43, 0xe9, 0xd8, 0x09, 0x74, 0x5e, 0xbb, 0xf1, 0xbe, 0x83,
+       0xd8, 0x7f, 0x8b, 0xe0, 0x84, 0xf9, 0x8f, 0x6e, 0x9a, 0x8d, 0x7a, 0xb8,
+       0xc6, 0x23, 0x12, 0x7c, 0xbe, 0xe5, 0x18, 0xda, 0xcb, 0x54, 0x1f, 0x60,
+       0xde, 0xd0, 0x7e, 0x8f, 0x98, 0x02, 0x74, 0x5e, 0xdb, 0x68, 0x51, 0x00,
+       0xaf, 0x1a, 0xbd, 0x68, 0xf4, 0x77, 0x8c, 0x7f, 0x87, 0x9a, 0x58, 0x5d,
+       0x83, 0xae, 0xa1, 0xe3, 0x6e, 0xcc, 0x74, 0x86, 0xa5, 0x3b, 0x71, 0x5a,
+       0x16, 0xd2, 0x57, 0xdd, 0x76, 0x33, 0xd2, 0x4b, 0x9d, 0x87, 0xd1, 0xd3,
+       0xb1, 0xa7, 0x44, 0xa4, 0xc3, 0xfd, 0xab, 0xae, 0xad, 0x00, 0xfa, 0x39,
+       0xbd, 0x55, 0x88, 0x40, 0x7f, 0x94, 0xbe, 0xf2, 0x83, 0xf4, 0x25, 0x3e,
+       0x62, 0xc6, 0xf1, 0x0b, 0x9e, 0x64, 0xf1, 0x85, 0xfd, 0x1b, 0x19, 0x5d,
+       0x9f, 0x68, 0x65, 0xf6, 0x69, 0xe9, 0x23, 0xfd, 0xd1, 0xaf, 0x59, 0xf0,
+       0x86, 0x99, 0xb0, 0xf8, 0x03, 0xb1, 0xe9, 0xed, 0x8f, 0x0b, 0xd1, 0x61,
+       0x28, 0xdd, 0xf5, 0xd0, 0x4b, 0x9c, 0x0e, 0x23, 0xd1, 0x9d, 0xdb, 0xdc,
+       0x32, 0x15, 0xf2, 0x0f, 0x66, 0x3f, 0x4d, 0xf7, 0xef, 0x0c, 0xc2, 0xab,
+       0xb4, 0xe9, 0x56, 0x8c, 0x03, 0x94, 0x36, 0x4d, 0xc7, 0xf3, 0x6a, 0xfc,
+       0x53, 0x2d, 0xb1, 0xbc, 0x8d, 0x79, 0xcd, 0x2b, 0x59, 0x3e, 0xa3, 0xc4,
+       0xf2, 0x7b, 0xbe, 0xf3, 0xbe, 0x42, 0xf6, 0x71, 0x5f, 0x50, 0x3f, 0xe6,
+       0x81, 0x7e, 0x84, 0xfc, 0x13, 0x1f, 0xdd, 0xc7, 0xcb, 0xdb, 0x1f, 0x43,
+       0x3b, 0xe0, 0xf3, 0x5f, 0x1d, 0xc3, 0xfc, 0xc6, 0xc5, 0x2f, 0x50, 0xfc,
+       0xd3, 0xfe, 0xa7, 0xb7, 0xdb, 0x89, 0x0f, 0xed, 0x6c, 0x2f, 0xca, 0x99,
+       0x45, 0xad, 0x22, 0xe6, 0x97, 0x12, 0xc9, 0x57, 0x70, 0x8d, 0xee, 0x7d,
+       0x0d, 0x2d, 0x2f, 0x63, 0xf1, 0x6f, 0xec, 0x08, 0xf7, 0x45, 0x3b, 0x2d,
+       0xde, 0x4a, 0x3a, 0x7e, 0xd1, 0xb3, 0xc7, 0x07, 0xe1, 0x3d, 0xf9, 0x5d,
+       0xcc, 0x4e, 0xf5, 0xfc, 0x8a, 0x7d, 0x6f, 0x86, 0x78, 0x3a, 0x07, 0x5d,
+       0x03, 0xf9, 0x99, 0x12, 0xcb, 0x0f, 0x09, 0xd5, 0xbf, 0xd1, 0x7d, 0x58,
+       0x1c, 0xe7, 0xd4, 0xf3, 0x31, 0xf8, 0x5d, 0x26, 0x61, 0x5b, 0x3b, 0xde,
+       0x33, 0x2d, 0x6a, 0xb9, 0xd6, 0x6c, 0xd1, 0xc5, 0x2d, 0x85, 0x3e, 0x66,
+       0xad, 0x1f, 0xde, 0xdf, 0x78, 0x28, 0xfe, 0xe1, 0x7e, 0x11, 0xf6, 0xa7,
+       0xff, 0x5d, 0x09, 0x2d, 0x2f, 0xe4, 0xd4, 0x93, 0x8c, 0x7f, 0x16, 0xed,
+       0x32, 0xa3, 0x7d, 0xb4, 0x68, 0xdb, 0x26, 0x8c, 0xf7, 0xd5, 0x6d, 0x3b,
+       0x83, 0xf9, 0xb3, 0xa5, 0xbf, 0x79, 0x2a, 0x16, 0xe0, 0x50, 0xb7, 0x4b,
+       0x34, 0xe6, 0x4f, 0x6d, 0x13, 0x7d, 0x16, 0xcc, 0xf3, 0x12, 0x8f, 0x59,
+       0xd8, 0xf7, 0x39, 0x0c, 0x79, 0x4c, 0xb5, 0xad, 0xec, 0xfd, 0x8e, 0xda,
+       0x16, 0x9e, 0x27, 0x14, 0x92, 0x3f, 0xb3, 0xf8, 0x37, 0x7b, 0x9e, 0xf5,
+       0x50, 0xd0, 0x2c, 0x7e, 0xe6, 0x89, 0x58, 0xe0, 0xa7, 0x4f, 0x3b, 0xb6,
+       0xc6, 0x02, 0x3c, 0xe9, 0x7c, 0x98, 0x7f, 0x34, 0xb1, 0x30, 0x42, 0x7e,
+       0xd2, 0x85, 0xf2, 0x92, 0x5a, 0xd6, 0xf2, 0xbc, 0xa4, 0xf1, 0xf8, 0x7b,
+       0x1d, 0xa1, 0x79, 0x49, 0x9f, 0xc2, 0x3f, 0xa8, 0x1e, 0x77, 0xf5, 0x31,
+       0xe6, 0x79, 0x92, 0x6d, 0x4c, 0x6e, 0x51, 0xec, 0x17, 0x84, 0x7b, 0x1f,
+       0x49, 0xb3, 0x5f, 0x16, 0x3f, 0xf5, 0xd5, 0xa3, 0x90, 0x47, 0x7b, 0x6a,
+       0xe7, 0x67, 0x8f, 0xc2, 0xfe, 0x97, 0xfc, 0xe3, 0x8b, 0x47, 0x21, 0xaf,
+       0x83, 0xec, 0x8d, 0x52, 0xc0, 0x9e, 0xa8, 0xfb, 0xd5, 0x3b, 0x98, 0x7f,
+       0xa8, 0x8d, 0x1b, 0xdb, 0x87, 0xfb, 0x47, 0x4f, 0x3e, 0x81, 0xf9, 0x9b,
+       0xa7, 0xdf, 0xb3, 0xa0, 0x5d, 0x78, 0x7a, 0xcf, 0x89, 0x4c, 0xb0, 0x17,
+       0x4e, 0xef, 0xf8, 0x26, 0x05, 0xf2, 0x32, 0x97, 0xef, 0x29, 0xc7, 0xf8,
+       0xc4, 0xf2, 0xdf, 0x96, 0xe2, 0x7b, 0xa2, 0x91, 0xfc, 0x4d, 0xa0, 0x4f,
+       0xef, 0x45, 0xe4, 0x8f, 0x86, 0xe2, 0x63, 0x7f, 0xab, 0xe8, 0xb3, 0xd1,
+       0x7d, 0x7e, 0xfe, 0xae, 0x05, 0xf9, 0xbf, 0x3b, 0xcf, 0xac, 0x65, 0x29,
+       0xcb, 0xdf, 0x73, 0xf2, 0xfc, 0xb2, 0xed, 0xe1, 0xf3, 0x74, 0xb5, 0x7c,
+       0xa8, 0xda, 0xd6, 0x6b, 0x26, 0x8e, 0x04, 0x79, 0xd7, 0xca, 0xf4, 0x7a,
+       0x77, 0x7e, 0xd4, 0x85, 0xf2, 0xca, 0xde, 0xa6, 0x78, 0xbd, 0xfc, 0x22,
+       0xf0, 0xb7, 0x9d, 0xe7, 0x0f, 0xb6, 0x8c, 0x0f, 0x9b, 0x57, 0xf6, 0x39,
+       0xfc, 0x83, 0xe2, 0xa9, 0xa6, 0x8f, 0x31, 0xaf, 0xec, 0xab, 0xd6, 0xf9,
+       0xbf, 0xfc, 0x39, 0x3c, 0x6b, 0x0d, 0xff, 0xbe, 0xb6, 0xc6, 0xd7, 0x17,
+       0x82, 0x9b, 0x96, 0x07, 0x3c, 0xb4, 0x8f, 0x7a, 0x53, 0x1f, 0xe0, 0x8f,
+       0x9d, 0xbf, 0xc6, 0x3c, 0x3e, 0xc0, 0x5b, 0xa5, 0x13, 0xf4, 0xff, 0x57,
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+       0x40, 0xbe, 0xd7, 0xa2, 0x3d, 0x47, 0x91, 0x5f, 0x4e, 0xff, 0xf6, 0x30,
+       0xe6, 0xd9, 0x12, 0x9e, 0x8f, 0x7b, 0x9a, 0x74, 0xff, 0xb1, 0xbc, 0x49,
+       0x1e, 0xbb, 0xa8, 0xdb, 0x62, 0x67, 0xf9, 0x68, 0x1c, 0xfe, 0x90, 0xaf,
+       0xe6, 0x8c, 0xc5, 0x76, 0x9e, 0x97, 0xc6, 0xe8, 0x58, 0xcb, 0x57, 0x8b,
+       0x94, 0xa7, 0xf6, 0x64, 0x9f, 0x6c, 0x66, 0x5f, 0xf3, 0xfc, 0xe4, 0xa5,
+       0xce, 0x0e, 0x59, 0xb1, 0x05, 0xf1, 0x05, 0xf8, 0x11, 0x0a, 0x01, 0x5f,
+       0xc7, 0x0c, 0xf9, 0x7f, 0xda, 0xb9, 0x43, 0xe7, 0x53, 0x00, 0x0e, 0x57,
+       0xe8, 0xf3, 0x2f, 0x23, 0xe5, 0x03, 0x72, 0x3b, 0xbd, 0x07, 0xbe, 0x98,
+       0x5c, 0x3e, 0xbd, 0x89, 0xe7, 0x63, 0x76, 0xe7, 0x59, 0x12, 0x92, 0x9e,
+       0x07, 0xf9, 0x41, 0x4c, 0x1f, 0xd6, 0x79, 0x85, 0xa3, 0xe1, 0xf0, 0xab,
+       0xe5, 0x5f, 0x6e, 0x09, 0xc1, 0xaf, 0x76, 0xbe, 0x48, 0x7c, 0xa1, 0xf1,
+       0xe7, 0x85, 0xf7, 0xfd, 0xcf, 0xc1, 0xe5, 0xa1, 0x3e, 0xec, 0x7d, 0x00,
+       0x0d, 0x3e, 0xa7, 0xbe, 0x0d, 0x2f, 0xa7, 0x5f, 0xe4, 0xfc, 0x4e, 0xfd,
+       0x96, 0xbd, 0x7d, 0x74, 0xef, 0xbd, 0xcc, 0xe2, 0x7e, 0x8b, 0x96, 0x77,
+       0xa6, 0xed, 0xb7, 0xa9, 0x85, 0xe9, 0xe5, 0x53, 0xdb, 0x98, 0xdd, 0x18,
+       0xca, 0xdf, 0xb5, 0x11, 0x7e, 0x57, 0xeb, 0x0d, 0xbe, 0x4e, 0xed, 0xae,
+       0xf6, 0x41, 0x20, 0x87, 0x4e, 0xed, 0x7b, 0x9e, 0xd3, 0x9d, 0x97, 0xbf,
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+       0x63, 0x76, 0xb4, 0x0f, 0xf3, 0x17, 0xa9, 0xbf, 0x1b, 0x76, 0xbe, 0xba,
+       0xed, 0x67, 0xc2, 0xce, 0xf7, 0xa9, 0xa4, 0x5e, 0x0b, 0xfb, 0xff, 0xb4,
+       0x83, 0xd9, 0x21, 0x9f, 0xb6, 0x88, 0x61, 0x7f, 0x0f, 0xa1, 0xbd, 0x8f,
+       0xf1, 0x7d, 0xd5, 0x26, 0xbb, 0x8c, 0x7e, 0x97, 0x18, 0x1b, 0x8d, 0xf2,
+       0x68, 0xb9, 0xbd, 0xf0, 0x5d, 0xf8, 0xbe, 0xdb, 0x72, 0xbb, 0x8c, 0xf9,
+       0x0e, 0x0d, 0x2b, 0x79, 0x7e, 0xc4, 0x9d, 0x2e, 0xfc, 0x3d, 0x8f, 0x06,
+       0xfb, 0x58, 0xfc, 0x1d, 0x88, 0x55, 0x00, 0x1f, 0x9d, 0x1f, 0x6a, 0x56,
+       0xdc, 0xf8, 0xfb, 0x13, 0x66, 0x47, 0x55, 0x3e, 0xf8, 0x57, 0xa1, 0xef,
+       0x77, 0xca, 0x49, 0x26, 0xe2, 0xd5, 0xe3, 0x5f, 0xf2, 0xa4, 0xe3, 0xf7,
+       0xbb, 0xb2, 0xbf, 0x96, 0x40, 0xef, 0x74, 0xac, 0x30, 0xbe, 0x37, 0xd2,
+       0x21, 0x29, 0x07, 0x12, 0xe9, 0x7c, 0x1d, 0x65, 0x82, 0x0b, 0xec, 0xdd,
+       0x9e, 0x74, 0x66, 0x9c, 0xff, 0x6a, 0x55, 0x34, 0xc4, 0xcf, 0x20, 0x56,
+       0x0d, 0xe7, 0x3a, 0xeb, 0x62, 0xdf, 0x45, 0xb3, 0x9b, 0x7c, 0x0a, 0xed,
+       0x42, 0xec, 0x51, 0x1d, 0x0e, 0x74, 0xf4, 0x9c, 0xec, 0x77, 0xab, 0xe1,
+       0xe7, 0xba, 0xe0, 0x3e, 0x7c, 0xdd, 0x0a, 0x6b, 0x3f, 0x78, 0x8f, 0xeb,
+       0xff, 0x02, 0x2f, 0xb6, 0xd5, 0x84, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xb5, 0x7d,
+       0x09, 0x7c, 0x54, 0xd5, 0xb9, 0xf8, 0xb9, 0x73, 0xef, 0x4c, 0x26, 0xcb,
+       0x24, 0x93, 0x65, 0x60, 0x20, 0x2c, 0x37, 0xfb, 0x1e, 0x26, 0x10, 0x12,
+       0xd0, 0x58, 0x26, 0x1b, 0x06, 0x09, 0x38, 0x22, 0x55, 0xd4, 0x80, 0x37,
+       0x6c, 0x61, 0x0b, 0x89, 0x68, 0x6d, 0x6c, 0xfd, 0x97, 0x61, 0x31, 0x45,
+       0xe5, 0xb5, 0xa1, 0x2e, 0x50, 0xa5, 0xcf, 0x01, 0xc1, 0xc7, 0xa3, 0xf8,
+       0x1a, 0x16, 0x6b, 0xac, 0x51, 0x07, 0x08, 0x14, 0x2d, 0xda, 0xd0, 0xe2,
+       0x93, 0xfa, 0x57, 0x1b, 0x94, 0x2a, 0x28, 0x98, 0x11, 0x94, 0xf2, 0x5a,
+       0x2c, 0xff, 0xf3, 0x7d, 0xe7, 0x9c, 0xcc, 0xdc, 0x9b, 0x09, 0x84, 0xbe,
+       0xfe, 0xa3, 0xfe, 0xae, 0xe7, 0xde, 0xb3, 0x7e, 0xfb, 0xf7, 0x9d, 0xef,
+       0x9c, 0x89, 0x25, 0x2e, 0x89, 0xc8, 0x84, 0xd8, 0x5c, 0x8a, 0xb7, 0x27,
+       0x9b, 0xe0, 0xdf, 0x15, 0xfa, 0x5f, 0x1c, 0xa1, 0x65, 0x2b, 0x2f, 0xa7,
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+       0x6f, 0x92, 0x08, 0x89, 0xca, 0x26, 0xd9, 0x4a, 0x31, 0x21, 0x76, 0x12,
+       0xe5, 0x92, 0x69, 0xf9, 0x89, 0x58, 0xf7, 0x61, 0x29, 0x96, 0x90, 0xf5,
+       0x36, 0xad, 0x96, 0xd0, 0xe7, 0x15, 0xf8, 0x9b, 0xd4, 0xff, 0x49, 0x5c,
+       0xca, 0x29, 0x18, 0xcf, 0x4a, 0xff, 0xb9, 0x92, 0x4a, 0xfb, 0x9b, 0x40,
+       0xcb, 0xd6, 0xe0, 0xf8, 0xf1, 0x6e, 0x7d, 0x39, 0x91, 0x84, 0x94, 0x71,
+       0x3e, 0x6e, 0x42, 0x86, 0xc0, 0x7b, 0xfa, 0xa7, 0x12, 0x32, 0x59, 0xa6,
+       0x33, 0xa3, 0xf3, 0x88, 0xaf, 0x36, 0xf9, 0x22, 0x24, 0xfc, 0x5e, 0x9b,
+       0x31, 0x24, 0x38, 0xdf, 0x78, 0x07, 0x71, 0xf9, 0xe1, 0xfb, 0xb4, 0x18,
+       0x97, 0x97, 0xd6, 0x8f, 0x89, 0x61, 0xf3, 0x13, 0xf3, 0xa5, 0xf3, 0xf9,
+       0x18, 0xe6, 0xa3, 0xd2, 0x7f, 0x70, 0x3e, 0xf9, 0x3d, 0x5e, 0x13, 0xc1,
+       0x79, 0x7d, 0x1c, 0x3a, 0x0f, 0xfa, 0x27, 0x79, 0x6c, 0x38, 0xbf, 0x8f,
+       0x0d, 0xf3, 0xfb, 0x38, 0x74, 0x7e, 0x05, 0xaa, 0x2d, 0xe9, 0xd3, 0x68,
+       0x5a, 0x50, 0x88, 0x72, 0x85, 0xc2, 0x37, 0xc6, 0xda, 0x4d, 0x38, 0x9c,
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+       0xf4, 0x3b, 0xed, 0x27, 0x45, 0x7a, 0x52, 0xb9, 0x22, 0x01, 0x5c, 0xed,
+       0x12, 0x49, 0xc3, 0xf1, 0x0c, 0xed, 0x46, 0xd8, 0xb1, 0x7f, 0x28, 0xd3,
+       0x7e, 0xc7, 0xc0, 0x9a, 0x27, 0x12, 0x52, 0xe6, 0x94, 0xdc, 0xa7, 0xc6,
+       0xd1, 0xff, 0xef, 0x4c, 0x22, 0x64, 0x18, 0x21, 0xa9, 0x2d, 0x95, 0xe4,
+       0x13, 0x5a, 0x96, 0xda, 0x08, 0xc2, 0x27, 0x7d, 0x3d, 0xf1, 0x45, 0xd0,
+       0xf9, 0xa5, 0x07, 0x4c, 0x58, 0x26, 0x6b, 0xa3, 0x7c, 0x19, 0xb4, 0x6d,
+       0x84, 0x95, 0x78, 0x23, 0xc7, 0xd2, 0x7a, 0x0a, 0xf1, 0x9a, 0xc7, 0x42,
+       0xaf, 0x3e, 0x42, 0xc6, 0x23, 0x70, 0x57, 0x9b, 0x68, 0x57, 0xca, 0x3a,
+       0x42, 0x1e, 0xa3, 0xed, 0x3a, 0x03, 0x15, 0xa6, 0x05, 0x14, 0xa8, 0xed,
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+       0x34, 0xa7, 0xa9, 0x08, 0x96, 0x93, 0xd7, 0xd6, 0x55, 0x46, 0x08, 0x1d,
+       0x2e, 0x47, 0x72, 0x11, 0x62, 0x5a, 0x95, 0xdb, 0x7d, 0x64, 0x24, 0x21,
+       0x49, 0x50, 0xff, 0x06, 0xf8, 0x9e, 0xdb, 0xed, 0x8e, 0xc1, 0xef, 0xac,
+       0x4c, 0x88, 0x9f, 0xd0, 0x75, 0xb5, 0x45, 0xf5, 0x95, 0xdd, 0x56, 0x27,
+       0x2d, 0xa7, 0xb2, 0xf2, 0x9d, 0xbe, 0xdc, 0xb6, 0x75, 0xb4, 0xbf, 0x0f,
+       0xd2, 0x3d, 0x77, 0xaa, 0x0e, 0xfa, 0xce, 0x6a, 0xcf, 0x05, 0xf8, 0x13,
+       0x7f, 0x02, 0xae, 0x77, 0x40, 0xfa, 0xa2, 0x70, 0x25, 0x8e, 0xe0, 0x3c,
+       0xb3, 0xb7, 0xf9, 0x2b, 0xa3, 0xe8, 0x24, 0x6e, 0x09, 0x50, 0x80, 0x52,
+       0xfc, 0x67, 0xd0, 0x3e, 0xba, 0xf3, 0x01, 0x3f, 0xdd, 0x16, 0x20, 0x92,
+       0xed, 0x31, 0xa2, 0xec, 0xb7, 0x10, 0xfa, 0xf4, 0xec, 0x3b, 0x66, 0xe9,
+       0xa1, 0xcf, 0xc6, 0xf6, 0x63, 0xf8, 0xdd, 0x04, 0x65, 0xfa, 0x1c, 0x9d,
+       0xe8, 0xaf, 0x4c, 0xa6, 0xeb, 0x7c, 0x50, 0xbd, 0xd1, 0xe3, 0xcc, 0xa1,
+       0xfd, 0xed, 0xab, 0x77, 0x9a, 0xec, 0x84, 0xac, 0x54, 0x6f, 0xec, 0x56,
+       0x1c, 0xa1, 0x70, 0x98, 0xa4, 0x83, 0x83, 0xb2, 0xfa, 0x26, 0x03, 0x1c,
+       0x6e, 0xba, 0x2e, 0x38, 0xac, 0xf4, 0xdd, 0x84, 0x70, 0x18, 0xec, 0xba,
+       0xcf, 0xa9, 0x9e, 0x1f, 0x01, 0x5e, 0xa6, 0x96, 0x9b, 0x88, 0x44, 0x07,
+       0x2d, 0x3d, 0x11, 0xe3, 0x93, 0x18, 0x1f, 0x47, 0x7a, 0x0a, 0x82, 0xfd,
+       0x6c, 0x31, 0x91, 0x45, 0xed, 0x31, 0xe1, 0xfa, 0x59, 0xc5, 0xf0, 0xcf,
+       0xeb, 0x09, 0x3a, 0x1a, 0x88, 0x4e, 0xd2, 0x88, 0x3d, 0x17, 0xe8, 0xd4,
+       0x48, 0x2f, 0x74, 0x7d, 0x35, 0xed, 0x14, 0x8e, 0x53, 0xb5, 0x7a, 0x4f,
+       0x55, 0x62, 0x90, 0x4e, 0x89, 0x5d, 0x1b, 0x37, 0xa3, 0x00, 0xe6, 0x39,
+       0xf7, 0x49, 0x98, 0xa7, 0x18, 0x77, 0x6a, 0xf9, 0x0a, 0x39, 0x95, 0xce,
+       0xe7, 0x49, 0x8a, 0x23, 0xe8, 0xd7, 0xd1, 0xe2, 0x8d, 0xcc, 0xa4, 0x74,
+       0xea, 0x70, 0x9b, 0x5c, 0xc0, 0xe7, 0xe7, 0x54, 0xed, 0xe7, 0x50, 0x3f,
+       0x76, 0x56, 0xc0, 0x6f, 0xa6, 0x55, 0x4a, 0x89, 0x76, 0xbf, 0x94, 0x16,
+       0xec, 0x5f, 0xd0, 0x7d, 0xeb, 0x6b, 0x32, 0xd2, 0x77, 0x6b, 0xbd, 0xc9,
+       0xb7, 0x1a, 0xe5, 0x41, 0x8f, 0x04, 0xeb, 0x0e, 0xe2, 0xbd, 0xc7, 0x80,
+       0xf7, 0x00, 0xc3, 0x7b, 0xc7, 0x49, 0xc4, 0xfb, 0xf2, 0xce, 0x93, 0x0c,
+       0xef, 0x1d, 0xab, 0x2a, 0xa2, 0x8a, 0xa1, 0x2c, 0xd9, 0x23, 0x54, 0x58,
+       0x4f, 0xa0, 0x08, 0xf0, 0xf9, 0x2b, 0xdf, 0x9d, 0x1e, 0x85, 0xe2, 0x73,
+       0x74, 0x74, 0xa0, 0x15, 0xe8, 0xc1, 0x4c, 0xbe, 0xeb, 0xa9, 0xcd, 0x41,
+       0xb8, 0xbf, 0x08, 0x74, 0xda, 0x0f, 0xee, 0x7c, 0x5e, 0x02, 0xfe, 0x03,
+       0xe1, 0xad, 0xed, 0x48, 0xea, 0xe3, 0xf9, 0xb4, 0xaa, 0xf7, 0xa8, 0xc9,
+       0x95, 0xa1, 0x06, 0xe1, 0x25, 0xea, 0x1d, 0x57, 0x2d, 0x58, 0x6f, 0x63,
+       0xaa, 0xf6, 0x1b, 0x18, 0xa7, 0x69, 0x42, 0xcf, 0x61, 0xba, 0x52, 0xb2,
+       0xe7, 0xc8, 0x1f, 0x62, 0x35, 0x3a, 0xdf, 0xd8, 0xa3, 0x33, 0xf6, 0x43,
+       0xfb, 0xd8, 0x99, 0x14, 0x13, 0x6a, 0x70, 0xdc, 0xb6, 0xa3, 0xab, 0x2b,
+       0x80, 0xfe, 0xdb, 0x80, 0xfe, 0x51, 0xce, 0x04, 0xbc, 0xf6, 0x98, 0xab,
+       0xc1, 0x83, 0xf1, 0x45, 0x1f, 0x3c, 0xf6, 0x9d, 0x44, 0xf8, 0x98, 0xa0,
+       0x4c, 0xdf, 0xef, 0xb4, 0x30, 0xba, 0x29, 0xeb, 0x90, 0xdc, 0x3e, 0xe0,
+       0x8b, 0x68, 0x72, 0xaf, 0x87, 0x3e, 0xdf, 0x56, 0x4d, 0x38, 0xbf, 0x93,
+       0xaa, 0xcc, 0x9f, 0x12, 0xc3, 0xe3, 0xd1, 0x03, 0xb2, 0x4a, 0xdb, 0x97,
+       0xad, 0x35, 0x61, 0x7d, 0x07, 0x3c, 0xf3, 0x43, 0xd7, 0xbf, 0x16, 0xeb,
+       0x9d, 0x54, 0x15, 0x2e, 0x77, 0x18, 0x3c, 0x04, 0x5e, 0x05, 0x1d, 0x51,
+       0xc2, 0x89, 0xbe, 0x8d, 0xce, 0x79, 0x78, 0x96, 0xf6, 0x3e, 0xac, 0x3f,
+       0x48, 0x37, 0x09, 0xd1, 0xa9, 0xf4, 0x7b, 0x69, 0xd7, 0xdc, 0xfb, 0x49,
+       0x6a, 0xb0, 0xdd, 0x4f, 0x56, 0x12, 0xcf, 0x7c, 0x73, 0xb0, 0x1e, 0xa5,
+       0x9f, 0x97, 0x75, 0xf4, 0x56, 0x60, 0x8e, 0x04, 0xb8, 0xf5, 0xd1, 0x0f,
+       0xa5, 0x4b, 0x90, 0x2f, 0x46, 0xfc, 0xd0, 0x76, 0xa7, 0x19, 0x3f, 0x25,
+       0x44, 0xab, 0xb4, 0xfe, 0xee, 0xae, 0x15, 0xb2, 0x96, 0x3f, 0x78, 0xbc,
+       0x96, 0x44, 0x90, 0x66, 0x98, 0x7f, 0x49, 0x34, 0x69, 0xde, 0x43, 0xdb,
+       0x97, 0xc4, 0xd1, 0x27, 0x94, 0x13, 0x79, 0x79, 0x28, 0x2f, 0x27, 0xf3,
+       0xe7, 0x68, 0xfe, 0x3e, 0x8f, 0x95, 0xd3, 0x3e, 0x70, 0x99, 0x24, 0x5a,
+       0xde, 0x02, 0x70, 0x07, 0x3c, 0xa4, 0x98, 0x18, 0x9c, 0x14, 0x7b, 0x2e,
+       0xf0, 0x91, 0x29, 0x85, 0xc1, 0xb9, 0xcc, 0x19, 0x8d, 0xf2, 0x5f, 0xf0,
+       0xab, 0x42, 0xc1, 0x19, 0x97, 0x00, 0x6a, 0x88, 0x78, 0xe1, 0x99, 0x1a,
+       0x48, 0x35, 0x01, 0x1e, 0x05, 0xff, 0x2a, 0x01, 0x93, 0xdf, 0x46, 0xf5,
+       0x5f, 0xaa, 0xa2, 0x9a, 0x5c, 0xf4, 0xfd, 0x5b, 0x2b, 0x35, 0x4f, 0x55,
+       0xc6, 0xc0, 0xf2, 0xe5, 0x96, 0x1c, 0xd9, 0xe3, 0x0b, 0x23, 0x2f, 0xe2,
+       0x52, 0x18, 0xde, 0xa9, 0x80, 0xf6, 0x9e, 0xca, 0x06, 0xed, 0x2c, 0x91,
+       0x38, 0x20, 0x81, 0x61, 0x5a, 0x5c, 0x0a, 0x9d, 0x57, 0xa3, 0xb5, 0xe7,
+       0x27, 0x33, 0xe8, 0xd7, 0xe5, 0x39, 0x17, 0x2c, 0x80, 0x9f, 0xd5, 0xd1,
+       0xcb, 0x6f, 0xd4, 0xf2, 0x07, 0x1e, 0xc7, 0x38, 0x8f, 0xb7, 0x2e, 0xff,
+       0x36, 0x1a, 0xe8, 0xab, 0xf3, 0x52, 0x44, 0x4d, 0x38, 0x79, 0x55, 0x03,
+       0xeb, 0xa7, 0xe3, 0x1f, 0x59, 0x39, 0x0b, 0xdb, 0x3d, 0x1a, 0x15, 0x5b,
+       0xc8, 0x95, 0x2a, 0xda, 0x2d, 0xdf, 0x41, 0xd1, 0x44, 0x9f, 0xe9, 0x4b,
+       0x6a, 0x49, 0x21, 0xe0, 0xc3, 0xab, 0x24, 0x80, 0xfe, 0x8b, 0x96, 0x5c,
+       0xdb, 0x09, 0xe2, 0x85, 0xe9, 0xc3, 0xa1, 0x29, 0xbe, 0xed, 0x29, 0x80,
+       0x1f, 0x5f, 0x2d, 0x96, 0xf3, 0xd2, 0xc8, 0x76, 0x09, 0xf0, 0xa4, 0xad,
+       0xb1, 0x41, 0x59, 0x4e, 0xc1, 0xfa, 0x14, 0x72, 0xc2, 0x3e, 0x92, 0xae,
+       0x44, 0x60, 0xdf, 0xaa, 0x42, 0xed, 0x0d, 0x44, 0x79, 0x2a, 0xe0, 0xb3,
+       0xf9, 0xa0, 0x0d, 0x84, 0x7d, 0x04, 0xad, 0xaf, 0xc2, 0x7b, 0xbd, 0x3d,
+       0x45, 0xe7, 0xb7, 0x95, 0x8c, 0x01, 0x7c, 0xb7, 0x55, 0x25, 0x40, 0xbd,
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+       0xb2, 0x01, 0xed, 0xd3, 0xc5, 0x97, 0xdb, 0xd0, 0x6e, 0x55, 0x9b, 0xd9,
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+       0x26, 0xc9, 0x1d, 0xce, 0xae, 0xb6, 0x73, 0xfc, 0x9d, 0xe3, 0x7c, 0x40,
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+       0x5b, 0x2d, 0xc3, 0xfc, 0xcb, 0x98, 0x1c, 0xea, 0xe3, 0xeb, 0x32, 0x82,
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+       0x45, 0xfe, 0x72, 0x6c, 0x33, 0xbb, 0x99, 0x3f, 0xc9, 0xf8, 0xec, 0x62,
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+       0xef, 0xb6, 0x6d, 0x11, 0xb8, 0x9f, 0x20, 0xf8, 0x3e, 0x76, 0x26, 0xa9,
+       0x30, 0xc3, 0xfe, 0x2d, 0xe8, 0x1b, 0xa8, 0x35, 0x53, 0x3b, 0x71, 0x13,
+       0xec, 0xdb, 0x3a, 0x2d, 0x2a, 0xec, 0x23, 0x9f, 0x31, 0x07, 0x10, 0x4f,
+       0x67, 0xa8, 0xa3, 0xda, 0x86, 0xf8, 0xf4, 0x60, 0x3e, 0xca, 0x99, 0x43,
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+       0x04, 0xee, 0x27, 0x54, 0xcb, 0x9d, 0x48, 0xd7, 0x2b, 0xaa, 0x09, 0xea,
+       0x8f, 0xae, 0xed, 0xa5, 0x48, 0x07, 0x8b, 0x6a, 0x53, 0x25, 0xa0, 0xb3,
+       0x25, 0x3b, 0xe2, 0x25, 0xf8, 0x9e, 0x50, 0x65, 0x37, 0xc9, 0x21, 0x72,
+       0xb1, 0xb4, 0x45, 0x46, 0x7a, 0xa2, 0x74, 0xbb, 0x2e, 0x3d, 0x04, 0x7e,
+       0xa5, 0xde, 0x66, 0x19, 0xe0, 0x32, 0x3a, 0x51, 0x73, 0x9a, 0xe3, 0xa9,
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+       0x0c, 0xc6, 0x85, 0x68, 0xf9, 0x67, 0x31, 0xc3, 0x06, 0x1f, 0x17, 0xda,
+       0x98, 0x7e, 0xcb, 0xcf, 0xd6, 0x8d, 0xa0, 0x4a, 0x24, 0xcd, 0xfd, 0x14,
+       0x8c, 0x7b, 0x4e, 0xf5, 0x6c, 0x04, 0xbc, 0x94, 0x24, 0x37, 0x63, 0xbc,
+       0x73, 0xb0, 0x79, 0x10, 0x4d, 0x3c, 0xae, 0xf4, 0xc1, 0x23, 0x6f, 0x6d,
+       0xaf, 0xa7, 0xeb, 0xae, 0x7b, 0x34, 0xf0, 0x08, 0x7c, 0xbd, 0x17, 0xe2,
+       0xae, 0xd9, 0x90, 0x3f, 0xc0, 0xe2, 0xae, 0x4d, 0x9d, 0xc7, 0x30, 0x1e,
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+       0x29, 0xfa, 0xf8, 0x6b, 0x60, 0x70, 0xe3, 0x26, 0x71, 0xbe, 0x25, 0x1f,
+       0x10, 0x84, 0x7f, 0x92, 0xa7, 0x59, 0x86, 0xb8, 0x84, 0x90, 0x0b, 0xfb,
+       0xd2, 0x13, 0x84, 0xff, 0x28, 0xc1, 0xfe, 0x9b, 0xe0, 0x07, 0x90, 0x2b,
+       0x60, 0x7f, 0x8a, 0x3c, 0x08, 0x88, 0x87, 0xd9, 0x12, 0x82, 0x72, 0x19,
+       0xca, 0x71, 0x21, 0x7a, 0x75, 0x7d, 0x2d, 0xb5, 0x83, 0xc2, 0xf0, 0xd9,
+       0xc1, 0xf4, 0x98, 0xb0, 0x72, 0x90, 0x74, 0xfe, 0xfd, 0xd7, 0x3f, 0xa0,
+       0xfe, 0x7e, 0x13, 0x7c, 0x62, 0x72, 0xf1, 0x60, 0x7a, 0x88, 0xde, 0x7f,
+       0xa2, 0xf6, 0xe3, 0x21, 0x1a, 0x8b, 0x7b, 0x60, 0xbc, 0xe9, 0x7e, 0xee,
+       0x43, 0x3e, 0xb7, 0xda, 0xf5, 0xfb, 0x2c, 0x90, 0x43, 0xef, 0xc8, 0x28,
+       0xff, 0x8b, 0x22, 0x2c, 0x5e, 0x09, 0xf6, 0x87, 0xdc, 0x44, 0xb5, 0x0f,
+       0xe1, 0xfd, 0x01, 0x9b, 0x74, 0x4a, 0x7e, 0x1b, 0xf5, 0x3f, 0x9b, 0xfe,
+       0x26, 0x11, 0x37, 0xc4, 0xcf, 0xfe, 0x26, 0xe3, 0xf3, 0xb9, 0x1f, 0x79,
+       0x6a, 0x52, 0xc0, 0x9f, 0xef, 0x30, 0xb9, 0xa8, 0x25, 0x00, 0xf9, 0x14,
+       0x48, 0xc7, 0xae, 0xd1, 0xc4, 0x67, 0xa5, 0xf4, 0xd7, 0xce, 0xf7, 0x6b,
+       0xcb, 0x0f, 0xc6, 0xb8, 0xcd, 0xf4, 0x7d, 0xaf, 0x64, 0x45, 0xf9, 0xd7,
+       0xbb, 0x3f, 0xca, 0x0b, 0x7c, 0xdd, 0x6b, 0x33, 0x61, 0x5c, 0xb9, 0xeb,
+       0xb5, 0x08, 0x84, 0xeb, 0x85, 0xf4, 0x28, 0xee, 0x5f, 0xfb, 0x74, 0x7e,
+       0xb8, 0xd8, 0xff, 0x88, 0x8c, 0xe8, 0xf9, 0x43, 0x19, 0x6d, 0xbf, 0x35,
+       0x92, 0xf5, 0xbb, 0x35, 0x92, 0xc5, 0xe9, 0xb6, 0x3e, 0x9a, 0x19, 0x07,
+       0xf6, 0xe7, 0x40, 0xfb, 0xe3, 0x65, 0x2d, 0x69, 0x18, 0xe7, 0x13, 0xf1,
+       0xc7, 0xd4, 0x80, 0x6a, 0x62, 0x49, 0x64, 0x6c, 0x1c, 0x25, 0x40, 0x70,
+       0x7d, 0x62, 0xbf, 0x7c, 0x13, 0xe4, 0x6b, 0x14, 0x0f, 0x9c, 0xaf, 0xf1,
+       0xd7, 0xf4, 0xbe, 0x7c, 0x8d, 0x00, 0xd0, 0x53, 0xd3, 0xac, 0x9e, 0xc3,
+       0x30, 0x47, 0xa3, 0x1f, 0x36, 0xe4, 0xe8, 0xc7, 0xfb, 0xa1, 0x9f, 0x21,
+       0x2d, 0x2c, 0x4c, 0xb0, 0xe9, 0xe8, 0x0a, 0x09, 0xd6, 0xb9, 0xa9, 0x2e,
+       0xbc, 0x1f, 0x26, 0xe8, 0x68, 0x13, 0x8f, 0x7b, 0x85, 0xe4, 0x45, 0x7c,
+       0xab, 0xd3, 0x2f, 0xf5, 0x09, 0xd1, 0xa9, 0x21, 0xf2, 0x53, 0xb4, 0x7b,
+       0x9a, 0xe7, 0x45, 0x94, 0x76, 0xcd, 0xdd, 0x0b, 0x76, 0x1e, 0xe5, 0xef,
+       0x73, 0xa1, 0xfc, 0x3d, 0xb5, 0xe0, 0x91, 0xc8, 0x70, 0xfb, 0xf3, 0x9e,
+       0x96, 0x1f, 0x62, 0x5c, 0x74, 0x20, 0xfa, 0xf7, 0x98, 0x88, 0x16, 0x2e,
+       0xee, 0x37, 0x3a, 0x83, 0xcb, 0x5b, 0x25, 0x30, 0x1c, 0xed, 0xc1, 0x37,
+       0x2e, 0x46, 0xa9, 0x61, 0xf2, 0x25, 0x3c, 0xaf, 0x99, 0x1c, 0x00, 0x17,
+       0x11, 0x9f, 0xe9, 0x3f, 0xfe, 0x8f, 0x70, 0xfc, 0x61, 0x19, 0x7d, 0xfb,
+       0x7f, 0xc3, 0x07, 0xb3, 0xff, 0x67, 0x9c, 0x77, 0xb7, 0x99, 0x8c, 0x0c,
+       0xa7, 0x57, 0x04, 0x9e, 0x8d, 0xe3, 0x85, 0x69, 0x3f, 0xdb, 0x15, 0xd2,
+       0xde, 0x63, 0x21, 0xda, 0xee, 0x98, 0xfe, 0xed, 0x84, 0xdd, 0xeb, 0x91,
+       0xf8, 0xfe, 0xee, 0x87, 0x04, 0xf5, 0xab, 0xa0, 0x13, 0x0a, 0xf7, 0x71,
+       0x19, 0xf4, 0x7b, 0xe1, 0xdb, 0xf3, 0xc6, 0x45, 0x41, 0xc2, 0xa1, 0xb5,
+       0x59, 0x06, 0x79, 0x70, 0xa1, 0xa3, 0x2b, 0x19, 0xe2, 0x56, 0x03, 0xf9,
+       0x87, 0x62, 0x3e, 0xf4, 0x2f, 0x23, 0x5c, 0xbc, 0x85, 0x8e, 0xe7, 0x09,
+       0x87, 0x87, 0x69, 0x19, 0x4c, 0xbf, 0x7a, 0xcc, 0xcc, 0x0e, 0x95, 0xca,
+       0x0f, 0xdd, 0x03, 0xf3, 0xf2, 0x7c, 0x65, 0x91, 0x22, 0x42, 0xe8, 0x6c,
+       0x22, 0xaf, 0x67, 0xdc, 0xc7, 0xec, 0xfc, 0xea, 0xbf, 0xc7, 0xa1, 0x9c,
+       0x34, 0xfb, 0x93, 0xc3, 0xc1, 0xcf, 0xb8, 0xbf, 0x39, 0x11, 0x82, 0x93,
+       0x4c, 0xdf, 0xb1, 0x71, 0x39, 0x5c, 0x5a, 0xcb, 0x49, 0x45, 0x44, 0x12,
+       0xc6, 0x0b, 0xc8, 0x56, 0x15, 0xfc, 0x40, 0x26, 0x2f, 0xd5, 0x16, 0x82,
+       0x7c, 0x3e, 0x46, 0x72, 0xe3, 0xba, 0xeb, 0x20, 0xe8, 0xe2, 0x00, 0x3a,
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+       0x4a, 0x0b, 0xc2, 0x4b, 0xd0, 0x43, 0xeb, 0x8b, 0xd4, 0x4e, 0xd1, 0xc5,
+       0xad, 0x18, 0xff, 0x08, 0xff, 0x75, 0x24, 0x8f, 0xff, 0x50, 0x55, 0xe3,
+       0x0e, 0xc5, 0xdf, 0xd0, 0x59, 0x94, 0x54, 0x43, 0xe4, 0xfe, 0x30, 0xcd,
+       0x4a, 0x94, 0x90, 0x38, 0x5b, 0xf2, 0x22, 0xbb, 0xae, 0x3c, 0xb2, 0xd9,
+       0xa9, 0xab, 0xef, 0xf4, 0xfa, 0x25, 0xe0, 0x2b, 0x67, 0x8b, 0xaa, 0x7b,
+       0x1f, 0x94, 0x57, 0x6c, 0xbd, 0x23, 0xbd, 0x64, 0x0b, 0xe8, 0xff, 0x4d,
+       0xa4, 0x07, 0xd7, 0x37, 0x8a, 0xcf, 0x67, 0x8c, 0xa4, 0x21, 0x7d, 0x5c,
+       0x38, 0xfa, 0x49, 0x02, 0xc4, 0x25, 0x7f, 0xc0, 0xf9, 0x87, 0xae, 0xb7,
+       0x05, 0xd7, 0xdb, 0xa2, 0x5d, 0x08, 0xa5, 0x0f, 0xb1, 0xde, 0x6b, 0xad,
+       0xeb, 0x83, 0x95, 0x74, 0x3e, 0x94, 0xef, 0x3f, 0x02, 0xff, 0x9c, 0x3e,
+       0x67, 0x3f, 0x70, 0x52, 0x1a, 0x8a, 0x70, 0xb7, 0x83, 0x3a, 0xa0, 0x7a,
+       0x91, 0xb5, 0x1b, 0xf9, 0xf0, 0x31, 0xf4, 0x23, 0x47, 0x36, 0x77, 0xa3,
+       0x1d, 0x3f, 0xa7, 0x65, 0xbf, 0x04, 0xfa, 0x8b, 0xca, 0x0d, 0x6c, 0xb7,
+       0x69, 0xa5, 0x15, 0x9f, 0xcf, 0xac, 0xb4, 0xa3, 0x9f, 0x2f, 0xf0, 0x3b,
+       0x82, 0xd6, 0x83, 0x3c, 0x25, 0x6f, 0x05, 0xc9, 0x86, 0x7d, 0x81, 0x81,
+       0xf4, 0xd3, 0xc6, 0x8c, 0x41, 0xeb, 0xa7, 0x8d, 0x19, 0x61, 0xf4, 0x93,
+       0xc9, 0x1a, 0x78, 0x13, 0xf6, 0xc1, 0x1b, 0x3b, 0x65, 0x15, 0xe8, 0x60,
+       0xcd, 0xc3, 0x09, 0x98, 0xff, 0xf2, 0x5c, 0xbb, 0x84, 0xfb, 0x2e, 0x07,
+       0x3b, 0x59, 0xfe, 0xdf, 0x73, 0xad, 0x51, 0xa8, 0x47, 0xc4, 0xb8, 0x5f,
+       0xbe, 0x14, 0x87, 0xfb, 0x3f, 0x5f, 0xf2, 0x7d, 0x40, 0xd2, 0x15, 0x8f,
+       0xf4, 0xdd, 0x14, 0xcf, 0x71, 0xb2, 0x36, 0x1e, 0xf7, 0xc9, 0x7b, 0xf9,
+       0x3e, 0x64, 0x47, 0xba, 0xf6, 0x1f, 0x19, 0x21, 0xf2, 0xe0, 0xb9, 0xce,
+       0x6f, 0x22, 0x41, 0x7f, 0xe4, 0x89, 0x3c, 0x5b, 0x83, 0xde, 0x01, 0x41,
+       0x2c, 0xd1, 0xf6, 0xe0, 0x13, 0x01, 0x1d, 0xb7, 0xa6, 0x14, 0xad, 0x93,
+       0x61, 0x5d, 0x77, 0x68, 0xe3, 0x22, 0x65, 0xe4, 0xf7, 0xdd, 0x8c, 0x5e,
+       0x99, 0x7e, 0xfa, 0xe5, 0xae, 0x0a, 0x93, 0x16, 0x82, 0x9f, 0x0b, 0x1d,
+       0x5f, 0xcf, 0x39, 0xa0, 0xf6, 0xdf, 0x5f, 0x12, 0xfb, 0x50, 0x62, 0x7f,
+       0xea, 0x4d, 0xa7, 0xf6, 0x6a, 0x46, 0x88, 0xbc, 0x36, 0xee, 0x3b, 0x19,
+       0xf7, 0x4b, 0xe4, 0x58, 0x2b, 0xe6, 0x69, 0xbb, 0xe4, 0x28, 0x97, 0xac,
+       0xd7, 0xb7, 0x48, 0x87, 0x6b, 0x32, 0x98, 0x3e, 0x5d, 0xb3, 0x3f, 0x0a,
+       0xe1, 0xb8, 0x26, 0x23, 0x06, 0xf7, 0x7b, 0xe9, 0x7c, 0x8f, 0xc0, 0x38,
+       0x5d, 0x36, 0x0b, 0x19, 0x46, 0xdf, 0x5f, 0x38, 0x11, 0x83, 0xf5, 0xc4,
+       0xfc, 0xe9, 0x7c, 0x0b, 0x8f, 0x86, 0x99, 0x6f, 0x93, 0x29, 0x30, 0xe7,
+       0x80, 0xa4, 0x9b, 0xef, 0xb1, 0xab, 0xcf, 0x57, 0x9f, 0xcf, 0x2c, 0xe6,
+       0xd7, 0x87, 0x1f, 0x1e, 0x2f, 0x90, 0x6d, 0x0a, 0xae, 0xa3, 0x97, 0x44,
+       0xb9, 0x00, 0xaf, 0xed, 0x16, 0xd7, 0x09, 0x0d, 0xf4, 0xef, 0x3b, 0x51,
+       0x2c, 0x7f, 0x8a, 0xe3, 0x6f, 0x39, 0xe7, 0xcd, 0x5e, 0x8a, 0x2f, 0x89,
+       0xe2, 0xab, 0xb7, 0xe3, 0x42, 0x24, 0xd0, 0xf1, 0xc1, 0x74, 0xed, 0x24,
+       0xcc, 0x43, 0x1e, 0x19, 0x88, 0x05, 0xff, 0xe5, 0x60, 0xe7, 0x85, 0x1c,
+       0xe0, 0x97, 0x81, 0xf6, 0x0d, 0x95, 0x8c, 0x8a, 0xbf, 0x00, 0xbe, 0x20,
+       0xff, 0x0f, 0xf1, 0x66, 0xd7, 0x2e, 0xec, 0x22, 0x8c, 0x2f, 0xb5, 0xab,
+       0xb4, 0xcb, 0xc8, 0xa8, 0x38, 0x0b, 0xf5, 0xaf, 0x03, 0x3e, 0xdf, 0x5c,
+       0x0f, 0x7c, 0x9a, 0x94, 0x98, 0x75, 0xa1, 0xf6, 0x97, 0xc4, 0xe5, 0xb3,
+       0x91, 0x1e, 0xa5, 0xce, 0xfd, 0xff, 0x03, 0xfb, 0x01, 0x94, 0x1f, 0x31,
+       0x1f, 0xd5, 0x3b, 0x8a, 0xf8, 0xd6, 0x50, 0xb8, 0xb5, 0x16, 0x70, 0xba,
+       0x9c, 0x49, 0x54, 0x16, 0x9f, 0xd1, 0xd3, 0x4b, 0x47, 0xba, 0xc7, 0x9c,
+       0xe9, 0x08, 0xf2, 0xf1, 0x55, 0xe0, 0x13, 0x09, 0xf5, 0x7e, 0x99, 0xee,
+       0x89, 0x86, 0x27, 0xcc, 0x23, 0x79, 0x2c, 0xca, 0x29, 0x1b, 0x94, 0xa9,
+       0x5e, 0xdb, 0x6b, 0x49, 0x0d, 0xda, 0x5b, 0xa3, 0xd3, 0x98, 0xdc, 0x0b,
+       0xc4, 0x13, 0xcc, 0x5f, 0x31, 0xee, 0xf7, 0x66, 0x64, 0xcc, 0x48, 0xca,
+       0xa4, 0x70, 0x4b, 0xcd, 0x56, 0x4d, 0xf6, 0xfc, 0xeb, 0xe2, 0x87, 0x91,
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+       0x19, 0x29, 0x5c, 0xc8, 0x3e, 0xf3, 0x59, 0x5d, 0xbe, 0x80, 0x01, 0x0e,
+       0x07, 0xd3, 0x3d, 0x59, 0x0c, 0x0e, 0x41, 0x3a, 0x5b, 0xa3, 0x5e, 0x15,
+       0x1e, 0x79, 0x0c, 0x1e, 0x5a, 0x21, 0xac, 0xc3, 0x66, 0xa6, 0xf4, 0x02,
+       0x40, 0x99, 0x50, 0xef, 0xc4, 0xbc, 0x18, 0xd5, 0x7d, 0x37, 0xec, 0x7f,
+       0xee, 0x5c, 0xc5, 0xe0, 0xd0, 0xfb, 0x22, 0x83, 0xc3, 0xee, 0x2e, 0x13,
+       0xd2, 0xf5, 0x16, 0x92, 0x8b, 0xfc, 0x99, 0x6b, 0x3a, 0x3f, 0x07, 0xfa,
+       0xa7, 0xf2, 0x67, 0x02, 0xf4, 0x53, 0xdc, 0xdd, 0x66, 0x82, 0x7c, 0xc2,
+       0x0c, 0x9f, 0x6a, 0x82, 0xb8, 0x72, 0x4e, 0x77, 0xbb, 0xc9, 0x74, 0x75,
+       0xba, 0x2d, 0xcb, 0x44, 0x7d, 0xa1, 0x4d, 0xca, 0x64, 0xf6, 0xc5, 0xfd,
+       0x80, 0x87, 0xbc, 0x5d, 0x2c, 0x1e, 0x73, 0x15, 0xba, 0xad, 0xcc, 0x1c,
+       0x7f, 0x5d, 0x70, 0xaf, 0xcd, 0x1c, 0x3f, 0x78, 0x39, 0x44, 0xe9, 0xca,
+       0x13, 0x4a, 0x57, 0x83, 0xcd, 0x4b, 0xa2, 0xf4, 0x41, 0x92, 0x13, 0xfa,
+       0xf7, 0x47, 0x48, 0x0f, 0xc6, 0xfd, 0xf7, 0xbf, 0x12, 0x81, 0xf2, 0x7e,
+       0xf9, 0x1e, 0x09, 0xe5, 0xd3, 0xf2, 0xd7, 0x3f, 0x9b, 0x03, 0xf0, 0x5d,
+       0xfe, 0x9b, 0x08, 0x24, 0xca, 0xaa, 0xdf, 0x44, 0xe2, 0xf7, 0xf3, 0xfb,
+       0xd8, 0xf7, 0x2f, 0xcb, 0xc3, 0xef, 0x4f, 0xdf, 0x95, 0x99, 0x80, 0x7a,
+       0xb6, 0xb1, 0xfd, 0x3e, 0x4f, 0xa8, 0x7e, 0x17, 0x76, 0xc3, 0x4f, 0xdd,
+       0xe7, 0xed, 0xe9, 0x72, 0x70, 0x9f, 0x2f, 0x71, 0x1a, 0x3b, 0x6f, 0xb2,
+       0x26, 0x52, 0xe4, 0x9b, 0xb2, 0xfd, 0xbe, 0x58, 0x4e, 0x67, 0x89, 0x23,
+       0x3d, 0x6e, 0xd0, 0x53, 0x89, 0xd5, 0x2c, 0x9e, 0x14, 0x1b, 0xb3, 0x10,
+       0xf7, 0xfb, 0xfa, 0x9f, 0x2b, 0x61, 0x7c, 0xeb, 0xe0, 0xed, 0xec, 0x76,
+       0x15, 0xed, 0x07, 0xe3, 0x39, 0x13, 0x39, 0x8a, 0xe5, 0xe5, 0x39, 0xc8,
+       0xfa, 0xaf, 0x00, 0x4e, 0x89, 0x35, 0xfa, 0xef, 0x8e, 0x98, 0x1a, 0xcc,
+       0xc7, 0x73, 0x18, 0xf6, 0xff, 0x04, 0xbc, 0xbd, 0x99, 0xdc, 0x6e, 0xb6,
+       0x10, 0x27, 0xca, 0x59, 0xc3, 0x3e, 0xbf, 0x78, 0xfe, 0x25, 0x93, 0xdb,
+       0xeb, 0x6b, 0xe3, 0x4d, 0xa1, 0xf2, 0x04, 0xf4, 0x00, 0xc0, 0x75, 0x85,
+       0xcd, 0x8a, 0xeb, 0x5e, 0xe1, 0x20, 0x89, 0xb5, 0x10, 0x57, 0xb0, 0x29,
+       0x2e, 0x1c, 0xcb, 0xd0, 0x8f, 0x78, 0xc6, 0xbb, 0x4d, 0x44, 0x0d, 0x3d,
+       0x2f, 0x53, 0x13, 0x45, 0xd4, 0x10, 0xbb, 0xc8, 0xe1, 0x49, 0xd0, 0x95,
+       0x87, 0xce, 0x1a, 0xae, 0xab, 0x3f, 0x4c, 0x4b, 0xd5, 0x7d, 0x4f, 0x5e,
+       0x94, 0xab, 0xfb, 0x3e, 0xb2, 0x79, 0xac, 0xae, 0x3c, 0xba, 0xe5, 0x06,
+       0x5d, 0xfd, 0x14, 0x0a, 0x80, 0xd0, 0x72, 0xda, 0xba, 0x5b, 0x74, 0xf5,
+       0x33, 0xda, 0x66, 0xe8, 0xca, 0x59, 0x9b, 0xee, 0xd6, 0xd5, 0xcf, 0xf1,
+       0xcd, 0xd5, 0x7d, 0xcf, 0xdb, 0xb1, 0x44, 0xf7, 0xbd, 0xa0, 0x7d, 0x85,
+       0xae, 0x3c, 0xa6, 0xe3, 0x07, 0xba, 0xfa, 0xf2, 0x00, 0xf6, 0xb8, 0x80,
+       0xb3, 0x2c, 0xec, 0x71, 0x5b, 0xb1, 0x06, 0x74, 0x25, 0xdb, 0xac, 0x52,
+       0xa8, 0xdd, 0xf2, 0x22, 0xaf, 0x57, 0x1e, 0x6b, 0x45, 0xf8, 0x3f, 0xc2,
+       0xf5, 0xf5, 0x23, 0x36, 0x0b, 0xea, 0xeb, 0x47, 0xb8, 0xbe, 0xee, 0x72,
+       0x94, 0x5c, 0x75, 0x5f, 0xe6, 0x9f, 0xf5, 0xdf, 0xde, 0x16, 0xf4, 0xc0,
+       0xed, 0xb5, 0x0a, 0x1e, 0x2f, 0xfb, 0xf2, 0x80, 0xc5, 0x04, 0xf4, 0xb8,
+       0xfc, 0x20, 0xa5, 0x8b, 0x31, 0x68, 0xaf, 0xbd, 0x9d, 0xc9, 0xec, 0xb5,
+       0xe9, 0xf5, 0xb8, 0xfa, 0x80, 0x05, 0xe4, 0x5e, 0xf7, 0x00, 0xf9, 0x20,
+       0xef, 0x65, 0x72, 0x3f, 0x43, 0xa1, 0x7e, 0x4c, 0x18, 0x7f, 0xf0, 0x93,
+       0x4c, 0x55, 0x17, 0xb7, 0x13, 0xfe, 0x03, 0x95, 0x6b, 0xef, 0x73, 0xfd,
+       0xc2, 0xfc, 0x26, 0xd2, 0x2c, 0x83, 0x1c, 0x10, 0x72, 0xa9, 0x29, 0x9a,
+       0xa0, 0x9d, 0xd7, 0x14, 0x6d, 0xc7, 0x3c, 0x9f, 0xde, 0xd8, 0x4b, 0x99,
+       0xc0, 0x4f, 0x54, 0x5e, 0x7d, 0x0c, 0xed, 0xba, 0xb3, 0x9f, 0x68, 0x3e,
+       0x00, 0x72, 0xaa, 0x33, 0x02, 0xe5, 0xd4, 0x5b, 0xd9, 0x9f, 0xa0, 0x3f,
+       0x7e, 0x4b, 0xcb, 0x42, 0x6c, 0xff, 0x62, 0xa6, 0x9d, 0xe1, 0xc5, 0xe2,
+       0x52, 0xed, 0x28, 0xa7, 0xf4, 0xfa, 0xf7, 0xa8, 0xb9, 0xbb, 0x16, 0xf0,
+       0x70, 0x74, 0xbc, 0x4c, 0x56, 0x81, 0x1d, 0xe4, 0x2a, 0x1d, 0x4a, 0xae,
+       0x02, 0xf7, 0x77, 0xc0, 0xdf, 0xa6, 0x76, 0xf2, 0xb6, 0x2c, 0x82, 0xfd,
+       0x5e, 0xcb, 0x5f, 0x3d, 0xba, 0x72, 0x11, 0xe6, 0x4d, 0x0f, 0xd4, 0xdf,
+       0xd1, 0xa2, 0x48, 0x8c, 0x9b, 0xd6, 0x02, 0x5d, 0x85, 0x8c, 0x1b, 0x9d,
+       0xc5, 0xe0, 0x99, 0xc1, 0x9f, 0xd4, 0x10, 0x45, 0xbf, 0xf3, 0xdc, 0xaf,
+       0x6d, 0x3e, 0x2f, 0xf8, 0x4b, 0x63, 0xdf, 0x8d, 0x25, 0x36, 0xc8, 0x93,
+       0xf9, 0xe3, 0x38, 0x2f, 0xe8, 0x23, 0xd2, 0x7d, 0x3f, 0xec, 0xdf, 0x7b,
+       0xbf, 0x8e, 0xc1, 0xb8, 0x4e, 0x6d, 0xd1, 0xbb, 0xe3, 0x56, 0x61, 0xbe,
+       0xa8, 0x9b, 0xf9, 0x7d, 0x13, 0xd8, 0x9a, 0x6f, 0x7a, 0xf9, 0xed, 0x58,
+       0xf0, 0xd7, 0x6b, 0x77, 0x1f, 0x4c, 0xf2, 0x86, 0xe0, 0xd1, 0xe8, 0xef,
+       0x65, 0xf0, 0xf5, 0x11, 0xa5, 0x27, 0x13, 0xf3, 0x4e, 0x5f, 0x3d, 0x33,
+       0x44, 0xa5, 0xcf, 0xda, 0x57, 0x0e, 0x25, 0xb1, 0xb8, 0x92, 0x3e, 0xff,
+       0xc5, 0xe8, 0xe7, 0xd7, 0xb6, 0x2c, 0xd7, 0xd1, 0x67, 0xe3, 0xa5, 0x48,
+       0x5d, 0x1e, 0x4c, 0xa3, 0xd2, 0x6d, 0x01, 0x7c, 0x34, 0x5e, 0x8a, 0xc1,
+       0xf7, 0xbd, 0x99, 0xfa, 0x38, 0xc0, 0x80, 0xf0, 0x1a, 0x24, 0x3c, 0x8d,
+       0xef, 0x05, 0x3c, 0x8f, 0x16, 0x9d, 0x19, 0x05, 0x71, 0xfa, 0x2f, 0x23,
+       0xc3, 0xd3, 0xf1, 0x6d, 0xbc, 0x9e, 0x28, 0x1b, 0xcf, 0x2f, 0x0c, 0x94,
+       0x27, 0x3f, 0x81, 0xb7, 0xbb, 0xe0, 0x9a, 0x38, 0x14, 0xe2, 0x4c, 0xb5,
+       0x16, 0x7f, 0xfa, 0x60, 0xe2, 0x12, 0x02, 0x4e, 0x6f, 0x5d, 0x6e, 0xc0,
+       0x73, 0x11, 0xbf, 0x1e, 0xe0, 0x5c, 0x44, 0x51, 0x16, 0xdb, 0x37, 0xf9,
+       0x75, 0xf6, 0x02, 0xcc, 0x6b, 0x9e, 0x68, 0x6d, 0xae, 0x04, 0xfd, 0x3d,
+       0x91, 0xc7, 0x3f, 0xc3, 0xe4, 0x35, 0x57, 0x67, 0x81, 0x9d, 0x7b, 0xe2,
+       0x5f, 0x93, 0xd7, 0x3c, 0x3d, 0x8b, 0xe3, 0x87, 0xe7, 0x0d, 0x0f, 0xcf,
+       0x52, 0xc3, 0xe6, 0x35, 0x5f, 0xeb, 0xdc, 0xc9, 0x54, 0x0b, 0x95, 0x4b,
+       0x61, 0xf8, 0x2b, 0xb7, 0x0f, 0x7e, 0x7f, 0x9a, 0x39, 0x8e, 0xd2, 0xf1,
+       0xfd, 0xbf, 0x30, 0xdb, 0x61, 0x5e, 0x0d, 0xa0, 0xf3, 0x20, 0xde, 0xb2,
+       0xc5, 0x8c, 0xf1, 0xd7, 0xb7, 0x2f, 0x47, 0x10, 0x88, 0x87, 0x7f, 0xb6,
+       0xd9, 0xfc, 0x3c, 0xe4, 0xbb, 0x2c, 0xfa, 0xc5, 0xc1, 0x11, 0x4f, 0x40,
+       0xfc, 0xbb, 0x28, 0x02, 0xf3, 0xf1, 0x1a, 0xb6, 0x98, 0x59, 0xbc, 0xb6,
+       0x28, 0xd2, 0x07, 0x21, 0x87, 0x45, 0x5b, 0xbe, 0x37, 0x04, 0xf2, 0x2e,
+       0xbf, 0xa0, 0x7c, 0xbb, 0x8c, 0xce, 0xab, 0xe1, 0x17, 0x0e, 0xcc, 0x07,
+       0x7a, 0xbb, 0xeb, 0xb1, 0x21, 0x80, 0xa7, 0x33, 0x9c, 0x9f, 0x17, 0x7d,
+       0xfb, 0xe3, 0x3b, 0x00, 0xfe, 0xbb, 0x2d, 0xf6, 0xbc, 0x22, 0xfa, 0x5c,
+       0xb6, 0x4b, 0xd2, 0xe5, 0x99, 0x2f, 0xd9, 0x16, 0xa9, 0x2b, 0x8b, 0x7c,
+       0x22, 0x81, 0x3f, 0x22, 0x05, 0xf3, 0xcf, 0x55, 0x2a, 0x4f, 0x5b, 0xb2,
+       0xf4, 0xe7, 0x68, 0xc6, 0x05, 0xf7, 0x25, 0x5a, 0xb2, 0xb8, 0x5c, 0xbd,
+       0x9d, 0xce, 0x77, 0xf9, 0xf8, 0x0b, 0x16, 0xc0, 0xe3, 0xc1, 0xc3, 0x51,
+       0x38, 0xef, 0x37, 0x62, 0x64, 0xf4, 0x73, 0xfd, 0x45, 0x7f, 0xfd, 0xdd,
+       0x18, 0x5a, 0xae, 0xfc, 0x56, 0xc1, 0xbc, 0x7e, 0x63, 0x7e, 0x12, 0x21,
+       0x88, 0x74, 0xb2, 0x90, 0xe7, 0x11, 0x56, 0xbe, 0xa2, 0xf4, 0x9d, 0x03,
+       0x80, 0xb2, 0x7f, 0x65, 0x33, 0xf2, 0x09, 0x6d, 0x17, 0x53, 0x1d, 0x92,
+       0x6f, 0x5d, 0xf9, 0x73, 0xe6, 0x4f, 0x57, 0x46, 0xb2, 0x3c, 0xe0, 0x01,
+       0xf3, 0x96, 0x0c, 0xf9, 0x4a, 0xe2, 0x9c, 0x45, 0xbf, 0x3c, 0xa5, 0xe0,
+       0x39, 0x0b, 0x9d, 0x9d, 0x22, 0xe8, 0xe6, 0xa9, 0x2c, 0x3d, 0x5f, 0x1f,
+       0x3c, 0xcc, 0xf2, 0x92, 0x16, 0x1e, 0xe5, 0x76, 0xe5, 0x35, 0xe4, 0xe6,
+       0x3b, 0xb0, 0x8e, 0x0c, 0xc0, 0xd7, 0x5b, 0x75, 0xb0, 0x6f, 0xf9, 0x36,
+       0x87, 0xc6, 0xdb, 0x97, 0x3f, 0x5b, 0x3b, 0x8c, 0x96, 0x3f, 0x9b, 0x20,
+       0x41, 0x64, 0x8e, 0x7c, 0x76, 0x39, 0x3c, 0xdf, 0x7c, 0x26, 0xf4, 0x12,
+       0x9c, 0x0f, 0xc8, 0x0e, 0xe2, 0x67, 0x9a, 0x6b, 0x71, 0x5f, 0x19, 0xd8,
+       0xf2, 0xd6, 0x09, 0xf7, 0xe9, 0xce, 0x2d, 0x0c, 0x5e, 0xde, 0x5c, 0x5d,
+       0x9e, 0xdc, 0x95, 0x65, 0xc1, 0xf1, 0x8d, 0xf2, 0xdd, 0x48, 0xf7, 0xff,
+       0xbf, 0xe4, 0x7b, 0x6d, 0xd1, 0xa1, 0x51, 0x5e, 0x1b, 0x3e, 0x5f, 0x80,
+       0xe7, 0xd9, 0xdd, 0x4c, 0x3e, 0x1a, 0xf9, 0xdc, 0x28, 0xcf, 0x73, 0x0d,
+       0x72, 0x30, 0x28, 0xc7, 0x65, 0x9d, 0x1c, 0xcf, 0xe5, 0x72, 0x20, 0x28,
+       0xcf, 0x2d, 0xf8, 0x9d, 0x9a, 0x69, 0xb8, 0x1e, 0x6f, 0x89, 0xe2, 0x5b,
+       0x23, 0xa1, 0xff, 0xf3, 0x1e, 0xd0, 0x7d, 0x7e, 0x8c, 0x9a, 0x58, 0x4e,
+       0x9b, 0xac, 0xb5, 0xa7, 0x46, 0x6b, 0x57, 0xf7, 0x47, 0xff, 0x2f, 0xd4,
+       0xef, 0x4a, 0xd1, 0x3e, 0xca, 0xa2, 0x7c, 0x34, 0xfa, 0x97, 0xb9, 0x55,
+       0x60, 0x8c, 0xe7, 0xed, 0x6a, 0x33, 0x01, 0xff, 0xf6, 0x0e, 0x60, 0x87,
+       0x14, 0xa4, 0x1a, 0xf2, 0x82, 0x78, 0x7c, 0x48, 0x7c, 0x3f, 0x9b, 0x55,
+       0x5e, 0x00, 0xf9, 0xaa, 0x7b, 0x54, 0xf6, 0x14, 0xfc, 0x59, 0x4c, 0x99,
+       0x90, 0xef, 0x2f, 0x9f, 0xcd, 0x62, 0xfb, 0xcb, 0x3f, 0x01, 0xbb, 0x67,
+       0xf9, 0x7f, 0x5e, 0x44, 0xfe, 0xdc, 0x12, 0xa5, 0x39, 0x15, 0x58, 0xcf,
+       0x70, 0x8b, 0x2b, 0x74, 0xff, 0x56, 0x3c, 0x2f, 0x72, 0x7e, 0x1f, 0xf8,
+       0x7c, 0xad, 0x3e, 0xdf, 0xf9, 0x74, 0x3a, 0x61, 0x78, 0xcf, 0xce, 0xd6,
+       0xed, 0xcf, 0x80, 0x7f, 0x8f, 0xf9, 0x01, 0x07, 0xa2, 0x10, 0x6e, 0xcf,
+       0x3a, 0xdd, 0x97, 0x01, 0x0e, 0xed, 0x4e, 0xf7, 0xb7, 0x30, 0xaf, 0x32,
+       0xa7, 0xfb, 0x1f, 0x59, 0x21, 0x78, 0x59, 0xcb, 0xd7, 0xa9, 0x98, 0xf4,
+       0x71, 0x6b, 0xf1, 0x2c, 0xcd, 0x16, 0xf4, 0xef, 0x41, 0x3d, 0xbe, 0xa0,
+       0x22, 0xbc, 0xfc, 0x4d, 0xcd, 0x66, 0x79, 0xc1, 0xe5, 0x4f, 0xdf, 0x35,
+       0x0a, 0xec, 0xce, 0xbf, 0xec, 0xbf, 0x7b, 0x14, 0xc8, 0xc7, 0xae, 0xa7,
+       0x4a, 0xaf, 0x6a, 0x87, 0x6e, 0xe0, 0xfc, 0xf9, 0x6f, 0x5c, 0xee, 0xc7,
+       0xf3, 0xb8, 0xe3, 0x4f, 0x81, 0x6f, 0x68, 0x39, 0x01, 0xe2, 0x96, 0xb4,
+       0xfd, 0x02, 0x8b, 0x27, 0x33, 0x3e, 0xa4, 0x1f, 0x73, 0x76, 0x3c, 0xdb,
+       0xef, 0x2e, 0xff, 0x83, 0x27, 0x8d, 0xc2, 0xe5, 0xd4, 0x7a, 0x19, 0xe5,
+       0xf7, 0xa9, 0x18, 0x16, 0x67, 0xfc, 0x24, 0x46, 0xa9, 0xd9, 0xc6, 0xdb,
+       0x25, 0xe9, 0xda, 0xb1, 0x79, 0xca, 0x40, 0xf7, 0x94, 0x8f, 0x95, 0x18,
+       0x45, 0x77, 0x5e, 0xa2, 0x14, 0x68, 0xda, 0x31, 0xf0, 0x3a, 0x4b, 0xb3,
+       0x99, 0x1e, 0xb5, 0x10, 0x97, 0x15, 0xda, 0x5b, 0x0e, 0xdc, 0x62, 0x05,
+       0xfc, 0xca, 0x92, 0xdb, 0xce, 0xf2, 0xd2, 0x19, 0x3d, 0x4c, 0xa4, 0x23,
+       0x00, 0x3d, 0xfc, 0x98, 0xcb, 0xb1, 0xbf, 0x3b, 0xb5, 0xa2, 0x6c, 0x6c,
+       0xc7, 0xf4, 0xed, 0x44, 0xae, 0x6f, 0x95, 0x18, 0x83, 0x7e, 0x1d, 0x11,
+       0x5e, 0x9e, 0x89, 0xe7, 0x4b, 0x4e, 0x77, 0x09, 0xf4, 0x73, 0xa7, 0xd3,
+       0x5d, 0x9a, 0xed, 0x80, 0xb8, 0x17, 0xc9, 0x03, 0xbe, 0x69, 0x8f, 0x0a,
+       0x9f, 0xe7, 0x73, 0x13, 0xc7, 0xdf, 0xdf, 0x85, 0x3d, 0x46, 0x62, 0xd0,
+       0x6f, 0xc6, 0xf1, 0x64, 0xdc, 0x57, 0x75, 0x67, 0x63, 0x5c, 0xcb, 0x53,
+       0x01, 0xfd, 0xc1, 0xbe, 0xaa, 0x59, 0x02, 0x3e, 0xb0, 0xf3, 0xfa, 0x6e,
+       0x89, 0xc5, 0x2b, 0x3c, 0x37, 0xc3, 0x77, 0xe2, 0x74, 0x4b, 0xd3, 0x28,
+       0xbc, 0x4b, 0xfe, 0x4c, 0xf0, 0x3c, 0xc7, 0xde, 0x23, 0x15, 0x12, 0xec,
+       0xff, 0x26, 0x75, 0x57, 0x49, 0x20, 0xc7, 0x92, 0x38, 0xfe, 0x8c, 0xf3,
+       0xe8, 0xe1, 0x70, 0xdb, 0xc3, 0xf3, 0x25, 0xfa, 0xf3, 0x1d, 0xf3, 0x2b,
+       0x66, 0x70, 0xf8, 0xef, 0x51, 0x3d, 0xc8, 0x5f, 0xad, 0x29, 0x9a, 0x13,
+       0xfc, 0x55, 0xc8, 0xcb, 0x03, 0xbc, 0x1a, 0xf3, 0x2c, 0x7e, 0x99, 0xcd,
+       0xf6, 0xd5, 0xb6, 0x44, 0xf5, 0xe0, 0xfe, 0xa0, 0xf7, 0x6e, 0x82, 0xf9,
+       0x77, 0x43, 0xcb, 0xbc, 0x12, 0xe4, 0x0f, 0x25, 0xd7, 0xb6, 0x95, 0x53,
+       0x8c, 0x93, 0xf9, 0xd9, 0xcc, 0x9f, 0x4f, 0xa8, 0xd1, 0x9c, 0xe0, 0x87,
+       0x0f, 0x77, 0x5a, 0xf0, 0x9e, 0x8a, 0xc1, 0xf2, 0x5b, 0x7e, 0xbb, 0x1b,
+       0xe3, 0x25, 0xc5, 0x1a, 0x3b, 0xaf, 0xbc, 0xa9, 0xdb, 0x1b, 0x99, 0x49,
+       0xe7, 0x35, 0xa4, 0x5b, 0x2b, 0xb7, 0xd0, 0x67, 0x7a, 0xce, 0x10, 0x5c,
+       0xdf, 0x50, 0xd2, 0xbc, 0x8a, 0xf9, 0x09, 0xaa, 0x2e, 0xbf, 0xa9, 0x58,
+       0xab, 0xc0, 0x7d, 0x72, 0x31, 0xef, 0x92, 0xf9, 0xcd, 0x6b, 0x2c, 0x2a,
+       0xe6, 0xc3, 0xac, 0xc8, 0x0e, 0xf1, 0x6b, 0x92, 0x97, 0x79, 0xc3, 0xe6,
+       0x3b, 0x19, 0xf7, 0xb9, 0xd7, 0x08, 0xbe, 0xe4, 0xf9, 0x08, 0xc5, 0x3c,
+       0xff, 0xa0, 0x78, 0xdb, 0x53, 0x98, 0x4f, 0x50, 0xbc, 0xed, 0x66, 0x45,
+       0x0a, 0x91, 0x33, 0x9b, 0xb2, 0xcd, 0xb8, 0xfe, 0x33, 0x87, 0x96, 0x8c,
+       0x86, 0xf5, 0x0f, 0x94, 0xc7, 0xda, 0x96, 0xcd, 0xf0, 0xf0, 0xfd, 0x6c,
+       0x26, 0x5f, 0x06, 0xca, 0x1f, 0x5b, 0xdf, 0x27, 0x17, 0xfa, 0xe5, 0x8f,
+       0xad, 0xcf, 0x76, 0x84, 0xe4, 0xd7, 0x34, 0x9e, 0x47, 0xf9, 0xd7, 0x98,
+       0xcd, 0xe4, 0xfc, 0xb3, 0x90, 0x57, 0x43, 0xe1, 0xfa, 0xec, 0x7c, 0x91,
+       0x57, 0xb3, 0x45, 0x82, 0xf5, 0xee, 0xb5, 0xb4, 0x4f, 0xd9, 0x05, 0xf3,
+       0x5a, 0x6e, 0xc2, 0x3c, 0xa6, 0xbe, 0xbc, 0xa2, 0xf9, 0x2c, 0xcf, 0xad,
+       0xaf, 0x3d, 0xe4, 0x17, 0xd1, 0xf7, 0xcf, 0x2e, 0x62, 0xf9, 0x45, 0xc3,
+       0x7c, 0x1b, 0x70, 0x5f, 0xe2, 0x62, 0x24, 0xcb, 0xa3, 0xb8, 0xb8, 0x3d,
+       0x82, 0xc0, 0xb9, 0xa4, 0x67, 0xb7, 0x6d, 0x1c, 0x02, 0xe7, 0x10, 0x9f,
+       0xd5, 0x4c, 0x68, 0x07, 0x1a, 0xe7, 0x0f, 0x07, 0x82, 0x78, 0x5e, 0xa4,
+       0x19, 0xf2, 0x25, 0x01, 0x8f, 0x20, 0xaf, 0x04, 0xfe, 0xfa, 0xf2, 0x8f,
+       0x78, 0xfe, 0x5e, 0xd7, 0xf6, 0x97, 0x71, 0xde, 0x62, 0x3e, 0x94, 0x50,
+       0x2c, 0x00, 0xf7, 0xf4, 0x1c, 0x36, 0xaf, 0x25, 0x3b, 0x76, 0x4f, 0x01,
+       0xe2, 0x1f, 0xbe, 0x2c, 0x41, 0x82, 0xb8, 0x9d, 0x98, 0xd7, 0xb5, 0xe4,
+       0xfe, 0x4b, 0x9c, 0x2f, 0x06, 0x4b, 0x87, 0x2f, 0xe4, 0x30, 0xfe, 0x08,
+       0xa3, 0x1f, 0x5f, 0xcd, 0xbe, 0x3e, 0xfd, 0xf8, 0x06, 0xe0, 0x89, 0xea,
+       0xc7, 0x03, 0xd0, 0xee, 0xba, 0xf5, 0x23, 0xd7, 0x8b, 0x42, 0x4f, 0x8a,
+       0xef, 0xdd, 0x9c, 0x2e, 0x66, 0x66, 0x0f, 0xa8, 0x1f, 0xbb, 0xb3, 0xc3,
+       0xe8, 0x47, 0x15, 0xf2, 0x9e, 0x31, 0xef, 0xc8, 0xe4, 0xda, 0x1e, 0x06,
+       0x5f, 0x33, 0x78, 0xbf, 0x37, 0xba, 0xb5, 0x4a, 0xe0, 0xe7, 0xa2, 0x34,
+       0xed, 0x4f, 0xd0, 0xcf, 0xc4, 0x09, 0xbe, 0x83, 0x10, 0x07, 0x2d, 0xad,
+       0xf1, 0x1e, 0x04, 0x7e, 0x2f, 0x96, 0xf8, 0x79, 0xeb, 0x29, 0x4c, 0x0e,
+       0x24, 0xf6, 0x90, 0xfd, 0x10, 0x83, 0x8b, 0x3f, 0xd1, 0xe3, 0x86, 0x3c,
+       0xe5, 0xaa, 0x6c, 0x96, 0x6f, 0x71, 0xc3, 0x69, 0x37, 0xee, 0xb3, 0xc7,
+       0x79, 0x88, 0x04, 0xed, 0xc5, 0x3d, 0x06, 0x6d, 0x09, 0xec, 0xbc, 0xb3,
+       0x71, 0xfc, 0x49, 0x9c, 0x2f, 0x4c, 0x4f, 0x06, 0x30, 0x1f, 0x2e, 0xa9,
+       0x33, 0x7c, 0x5e, 0x6a, 0x41, 0x2a, 0xb3, 0xd7, 0xa8, 0xbc, 0x3c, 0x0b,
+       0x70, 0x2d, 0x19, 0x4d, 0xe5, 0x69, 0x4a, 0x7f, 0x79, 0x1a, 0x06, 0x7f,
+       0x17, 0xa0, 0x7e, 0xce, 0x2e, 0xff, 0x01, 0xa8, 0x35, 0x36, 0x3e, 0x3d,
+       0x1a, 0xcc, 0xaa, 0xab, 0xe0, 0xef, 0xaf, 0x0c, 0x7f, 0xee, 0x4b, 0xf0,
+       0x14, 0xf8, 0xca, 0xbd, 0x22, 0xeb, 0xe2, 0x78, 0x02, 0x5f, 0x57, 0xf8,
+       0xfc, 0x6f, 0xcd, 0x70, 0xff, 0x03, 0xc6, 0x39, 0xcc, 0xf9, 0x7b, 0x20,
+       0x3c, 0xc6, 0xe6, 0x50, 0xfc, 0x8d, 0x07, 0xfa, 0x66, 0x78, 0x14, 0x79,
+       0xc0, 0x3b, 0x0d, 0x76, 0x6a, 0x45, 0x0e, 0xc3, 0xcb, 0xe4, 0x1c, 0x7d,
+       0x5c, 0x28, 0x04, 0xdf, 0xb1, 0x39, 0xe3, 0xfb, 0xe3, 0x5b, 0xc8, 0xf1,
+       0xbd, 0x47, 0xf6, 0xc8, 0x80, 0xb7, 0x92, 0xaa, 0xb6, 0x35, 0x80, 0x07,
+       0x8a, 0xd7, 0xa4, 0x1c, 0xda, 0xcf, 0x0d, 0x65, 0xfa, 0xfc, 0x4f, 0x23,
+       0x5e, 0x85, 0x3c, 0x34, 0xe2, 0xd7, 0x88, 0x57, 0x91, 0x07, 0x48, 0xf1,
+       0x31, 0x3a, 0x27, 0x8c, 0xfe, 0x12, 0xfd, 0x18, 0xf5, 0x58, 0x88, 0x9c,
+       0xe0, 0xfb, 0xce, 0x6a, 0x5f, 0x7e, 0x07, 0xd8, 0xcf, 0x22, 0x4f, 0x5c,
+       0xac, 0x43, 0xf0, 0xcf, 0x24, 0x0e, 0x8f, 0x1b, 0x35, 0xad, 0xd2, 0xc2,
+       0xe8, 0xb4, 0x10, 0xc6, 0x9d, 0x38, 0xcb, 0x77, 0xd0, 0x0c, 0x74, 0xba,
+       0xc8, 0x7b, 0xd0, 0x12, 0x4a, 0xa7, 0x8b, 0x09, 0xdb, 0xaf, 0xe2, 0xf3,
+       0x48, 0xee, 0xf1, 0xe2, 0x7a, 0x86, 0x9d, 0xd0, 0xca, 0xe1, 0x79, 0xc3,
+       0x69, 0x3f, 0xde, 0xe3, 0x31, 0xb4, 0x99, 0xae, 0x87, 0x04, 0xd7, 0x33,
+       0xb2, 0xfb, 0x38, 0xe6, 0x63, 0xc2, 0xbe, 0x2c, 0xc4, 0x9b, 0xf6, 0x1e,
+       0x39, 0x80, 0xf3, 0x1e, 0xd1, 0xdd, 0xc5, 0x9e, 0x3c, 0x8f, 0xc8, 0xa8,
+       0x6f, 0x83, 0xf9, 0xb7, 0xac, 0x9f, 0x17, 0xb8, 0xfc, 0x6a, 0x3d, 0xc7,
+       0xf2, 0xf8, 0x5a, 0xcb, 0x99, 0xbe, 0xbd, 0x37, 0xc3, 0x5d, 0x99, 0x83,
+       0x7c, 0xec, 0xae, 0x82, 0xf9, 0xaf, 0xc8, 0x70, 0x57, 0x43, 0xb9, 0x20,
+       0x95, 0xd1, 0x4d, 0x6c, 0x8e, 0xfb, 0x66, 0x28, 0x8f, 0x1c, 0x40, 0xdf,
+       0xdf, 0x9a, 0xd3, 0xb7, 0x4f, 0x3d, 0x1d, 0xea, 0x25, 0x3d, 0x40, 0xbc,
+       0xe2, 0x1e, 0x14, 0x88, 0xc3, 0x27, 0x41, 0x24, 0x10, 0xb6, 0xf0, 0x9b,
+       0xbd, 0x92, 0x85, 0xc2, 0x35, 0xc9, 0x4d, 0xd0, 0xef, 0x1c, 0x9d, 0xa8,
+       0xad, 0x82, 0xbc, 0xb7, 0xc0, 0x44, 0xe2, 0x82, 0x7c, 0x80, 0xb8, 0x3a,
+       0x7b, 0x39, 0xc0, 0x2b, 0x61, 0x91, 0x6b, 0x3f, 0xc0, 0xb3, 0xf5, 0x1c,
+       0xbf, 0xcf, 0xe5, 0x3e, 0x82, 0xe7, 0xbd, 0xfa, 0xf2, 0xab, 0xb4, 0x54,
+       0xcc, 0xa7, 0x00, 0xfe, 0x0d, 0xe5, 0x97, 0x7a, 0x3e, 0x8f, 0xfa, 0x1c,
+       0xc6, 0x07, 0xd4, 0xde, 0x99, 0x93, 0xc3, 0xe6, 0xa5, 0xc1, 0xbc, 0x84,
+       0xbd, 0x23, 0xf8, 0x72, 0x20, 0xfb, 0x25, 0x84, 0xaf, 0x1b, 0xa0, 0xfd,
+       0x75, 0xf0, 0xf5, 0xf2, 0x9c, 0xeb, 0xe3, 0xeb, 0x15, 0x39, 0x8c, 0xaf,
+       0xef, 0x87, 0x76, 0xd7, 0xe2, 0xeb, 0x1f, 0xe4, 0xf4, 0xf1, 0xf5, 0x43,
+       0xd0, 0xee, 0x5a, 0x7c, 0xfd, 0x28, 0xe7, 0xeb, 0x17, 0xae, 0xc1, 0xd7,
+       0x3b, 0x78, 0xbf, 0xff, 0xc5, 0xeb, 0x87, 0xe1, 0xeb, 0x47, 0xc3, 0xf1,
+       0xb5, 0xca, 0xe9, 0x4e, 0xf0, 0xc5, 0x9e, 0x23, 0x63, 0xa3, 0x21, 0x5f,
+       0x60, 0x1b, 0xef, 0x2f, 0x44, 0x7e, 0x6f, 0x80, 0xf6, 0xd7, 0x92, 0xdf,
+       0xff, 0x04, 0x9f, 0x6f, 0x86, 0x7e, 0xaf, 0x65, 0xa7, 0x8a, 0x7e, 0x05,
+       0xbe, 0xaf, 0xc5, 0x27, 0xb1, 0xb9, 0x1e, 0x84, 0x83, 0xb0, 0x47, 0x4f,
+       0xa7, 0x33, 0xbc, 0x0b, 0xbe, 0xa7, 0xfc, 0xf2, 0x9f, 0x00, 0x7f, 0xca,
+       0x2f, 0x3b, 0x39, 0xbf, 0xfc, 0x92, 0xf1, 0x8b, 0x8a, 0xf5, 0x8c, 0xfc,
+       0xd5, 0xa7, 0xef, 0xba, 0x4d, 0xfc, 0x1e, 0x11, 0x7b, 0x74, 0x68, 0xdc,
+       0xfb, 0xcd, 0x9c, 0x7e, 0xfa, 0xee, 0xe5, 0x9c, 0x30, 0xfa, 0x6e, 0x24,
+       0xe1, 0xf0, 0xaa, 0x61, 0x72, 0x64, 0x04, 0xf1, 0xca, 0xb1, 0xd0, 0x6f,
+       0xad, 0x1d, 0xcb, 0xf6, 0xb3, 0x76, 0x74, 0xf3, 0x63, 0x4f, 0x05, 0xbc,
+       0x00, 0xb7, 0xf7, 0x72, 0x98, 0xbd, 0x51, 0x3c, 0x40, 0x3c, 0xe1, 0x77,
+       0x9c, 0x4f, 0x92, 0xba, 0x2b, 0x50, 0xbe, 0x50, 0x78, 0x1e, 0xca, 0x09,
+       0xd1, 0x63, 0x49, 0xc4, 0x3e, 0x15, 0xfc, 0x9c, 0xcf, 0x73, 0xd8, 0xba,
+       0xc6, 0x4d, 0x70, 0x1f, 0x04, 0xb9, 0x64, 0x77, 0x7b, 0x30, 0x9f, 0xdb,
+       0x91, 0xcb, 0xe0, 0x22, 0xe0, 0x44, 0xdb, 0xbf, 0x13, 0x4e, 0xee, 0xee,
+       0x03, 0x7c, 0xe4, 0xf7, 0xf7, 0x1b, 0x8c, 0x78, 0x38, 0xc8, 0xe7, 0xfb,
+       0x39, 0xa7, 0x1f, 0x63, 0xff, 0x42, 0xfe, 0x40, 0xff, 0x05, 0xd8, 0xbf,
+       0x6a, 0x82, 0xfe, 0x45, 0xfb, 0x3f, 0x07, 0xe5, 0xd0, 0x47, 0xb0, 0x8e,
+       0xd2, 0x07, 0x9a, 0x65, 0x58, 0x57, 0x12, 0x71, 0x47, 0x83, 0xfc, 0x11,
+       0x72, 0x92, 0x8c, 0xa0, 0xed, 0x8b, 0xfb, 0xb7, 0xff, 0x34, 0xd8, 0xfe,
+       0x53, 0x58, 0x47, 0x69, 0x33, 0x6d, 0x9f, 0x1f, 0x6c, 0x3f, 0x92, 0xf8,
+       0x31, 0x5f, 0x27, 0x61, 0x11, 0x95, 0x53, 0x04, 0xec, 0x77, 0x17, 0xda,
+       0xb3, 0xeb, 0x55, 0xcf, 0xb9, 0x1c, 0x9c, 0x27, 0x61, 0xf2, 0xaa, 0xdc,
+       0x84, 0xf2, 0x20, 0x2b, 0xdd, 0x8d, 0x7c, 0x17, 0x4e, 0xff, 0x43, 0xfd,
+       0xeb, 0xd1, 0xff, 0xb0, 0x1e, 0xd0, 0xff, 0x83, 0x91, 0x13, 0x57, 0x38,
+       0x3d, 0x81, 0xfe, 0x87, 0x71, 0x3e, 0xce, 0xba, 0x86, 0xfe, 0xcf, 0x65,
+       0xeb, 0x8e, 0xcb, 0xbd, 0xba, 0x9c, 0x88, 0xcf, 0x65, 0xfd, 0x3a, 0x72,
+       0x07, 0xd6, 0xff, 0xb9, 0x61, 0xe4, 0xc4, 0x1e, 0xd5, 0x8d, 0xfc, 0x14,
+       0x86, 0x8f, 0x12, 0x72, 0x1d, 0x10, 0x67, 0x71, 0x27, 0x42, 0x3b, 0xca,
+       0x47, 0x49, 0x50, 0x16, 0x7a, 0x87, 0xb6, 0x1b, 0x02, 0xef, 0xd7, 0xab,
+       0x0c, 0x8e, 0xeb, 0x6b, 0x4d, 0xd9, 0x68, 0x5f, 0x93, 0x28, 0x57, 0x38,
+       0x7f, 0x26, 0x2d, 0x37, 0x66, 0xb0, 0xf9, 0x45, 0x69, 0x7c, 0x9e, 0xd7,
+       0x95, 0xff, 0xfa, 0xdc, 0x8f, 0x7a, 0x2c, 0x00, 0x6f, 0x91, 0xa7, 0x22,
+       0xc6, 0x35, 0xe6, 0xbd, 0x0a, 0x3c, 0x2e, 0xef, 0x94, 0xc6, 0x41, 0x5c,
+       0xae, 0xfc, 0xe0, 0x65, 0x8c, 0x93, 0xf4, 0xee, 0xff, 0x1b, 0xc6, 0x49,
+       0x94, 0x8c, 0xb9, 0xe3, 0x60, 0xfc, 0xae, 0xd7, 0x58, 0xbc, 0x44, 0xe4,
+       0x95, 0x88, 0xf1, 0x57, 0x70, 0x3f, 0xb2, 0x5a, 0xce, 0x6f, 0x87, 0x38,
+       0xed, 0xf9, 0x1d, 0x16, 0x8c, 0x7f, 0xca, 0x44, 0xdd, 0x58, 0x46, 0xe7,
+       0xd3, 0x74, 0xc4, 0x4c, 0x7c, 0x28, 0x07, 0xd9, 0xf9, 0x65, 0xb1, 0x4f,
+       0x6b, 0xde, 0xd1, 0xda, 0x0d, 0x71, 0x79, 0x33, 0x09, 0xb9, 0x67, 0x07,
+       0xf5, 0x9d, 0x1a, 0x07, 0x74, 0x69, 0x3e, 0xc2, 0xee, 0xbb, 0x21, 0x49,
+       0xec, 0x7b, 0x33, 0xb1, 0xae, 0x62, 0xf7, 0x30, 0xea, 0xf7, 0x69, 0xe3,
+       0xdd, 0xfa, 0x7d, 0xda, 0xc4, 0x1a, 0xfd, 0x3e, 0xad, 0x88, 0x23, 0x2e,
+       0x25, 0x6c, 0x9e, 0x0e, 0x8f, 0x7e, 0xdf, 0x76, 0xe8, 0x2c, 0xfd, 0xbe,
+       0xed, 0x30, 0x4d, 0xbf, 0x6f, 0x9b, 0xbc, 0x68, 0xac, 0x61, 0x1f, 0x57,
+       0xbf, 0x6f, 0x3b, 0xba, 0xa5, 0xc2, 0xb0, 0x8f, 0xab, 0xdf, 0xb7, 0x4d,
+       0x5b, 0x37, 0xc3, 0xb0, 0x8f, 0xab, 0xdf, 0xb7, 0xfd, 0x8c, 0x34, 0x3f,
+       0x5d, 0x46, 0xd7, 0x9d, 0x2b, 0xee, 0xfb, 0xf1, 0xba, 0xbb, 0xe1, 0x5c,
+       0xf4, 0x7c, 0x3e, 0xdf, 0xac, 0x4d, 0xfa, 0x7d, 0xdd, 0x2f, 0x76, 0xd6,
+       0xe0, 0x7d, 0x21, 0xf3, 0x79, 0x7c, 0x3b, 0xc7, 0xa7, 0xdf, 0xe7, 0x5d,
+       0x2a, 0x2f, 0x43, 0x3a, 0x26, 0x6d, 0xec, 0x9c, 0x73, 0x33, 0xfd, 0x07,
+       0xe0, 0xa6, 0x90, 0xc0, 0xe1, 0x64, 0xc8, 0x3f, 0xf0, 0x49, 0x2e, 0x3f,
+       0xfd, 0xdc, 0xb0, 0x49, 0x7f, 0x0e, 0x7a, 0x71, 0xc7, 0x16, 0x6c, 0xb7,
+       0xd8, 0xa7, 0x7f, 0xbf, 0x74, 0x87, 0xbe, 0xfc, 0x40, 0x2e, 0xbf, 0x07,
+       0x86, 0xc7, 0xbd, 0xfb, 0xd3, 0x41, 0x0c, 0xcb, 0x63, 0xd8, 0xcc, 0xe2,
+       0xfd, 0xb2, 0x37, 0xcb, 0x40, 0x07, 0x7a, 0x7c, 0xfc, 0x6f, 0xe9, 0x42,
+       0xe5, 0x74, 0x11, 0xe1, 0xd4, 0xd3, 0x45, 0xa4, 0xaa, 0xa7, 0x8b, 0x86,
+       0x37, 0xf7, 0x96, 0xc0, 0xba, 0x8d, 0xf0, 0x8d, 0xce, 0xd6, 0xd3, 0x8b,
+       0x11, 0xbe, 0x36, 0x97, 0x9e, 0x5e, 0x04, 0x5c, 0xa9, 0x9e, 0xe4, 0xf9,
+       0x38, 0x6e, 0x5c, 0xef, 0xc2, 0x0e, 0x89, 0x3c, 0x23, 0xf5, 0x87, 0xeb,
+       0xa2, 0xce, 0x0d, 0xad, 0x70, 0x0e, 0xdd, 0x08, 0x57, 0x42, 0x7c, 0xb8,
+       0xef, 0x6c, 0x84, 0xaf, 0xcf, 0x00, 0xdf, 0x73, 0xaa, 0xf6, 0x3c, 0xf0,
+       0xdf, 0x85, 0x8e, 0x07, 0xf0, 0xbe, 0x1f, 0xa2, 0x69, 0xe3, 0xa0, 0xdd,
+       0x55, 0xf2, 0x63, 0xfe, 0x83, 0xd5, 0x1f, 0x74, 0x7e, 0x4c, 0x3b, 0xd4,
+       0x0f, 0xfa, 0xc9, 0xfa, 0xfc, 0x98, 0x5e, 0xc8, 0xe3, 0x1a, 0x43, 0x06,
+       0x91, 0xc7, 0x75, 0xf0, 0x7f, 0x20, 0xaf, 0x23, 0x82, 0xce, 0xd0, 0x0c,
+       0xf1, 0xc6, 0x09, 0x2e, 0x6b, 0xf8, 0xbc, 0x2d, 0xed, 0xf5, 0x5c, 0xd4,
+       0x33, 0x6e, 0x82, 0xf1, 0x9e, 0x3f, 0x10, 0xd7, 0x1a, 0x5a, 0x6b, 0x8d,
+       0xad, 0x24, 0xef, 0x1a, 0x71, 0x81, 0x03, 0xb9, 0x68, 0x47, 0x69, 0x78,
+       0x9f, 0x46, 0x69, 0x37, 0xcb, 0x73, 0x23, 0x4a, 0xb7, 0x1d, 0xe2, 0xbf,
+       0xe1, 0xee, 0x6f, 0x34, 0x9c, 0x6b, 0x3a, 0x0a, 0xed, 0xff, 0xd9, 0xfb,
+       0xf1, 0x84, 0xdd, 0x48, 0xed, 0xf4, 0x3f, 0xe6, 0x32, 0xbd, 0xfb, 0x2e,
+       0x3c, 0xfb, 0xec, 0x74, 0x6e, 0xb7, 0x09, 0x7b, 0x7b, 0xa0, 0x7e, 0xfa,
+       0xf2, 0x5c, 0x06, 0x78, 0x4a, 0x07, 0x64, 0xcc, 0xb3, 0x0a, 0x48, 0x51,
+       0xae, 0x70, 0xf7, 0x0d, 0x9d, 0xce, 0x95, 0xc2, 0xea, 0x0d, 0xaa, 0x27,
+       0x4e, 0xe7, 0x3a, 0x42, 0xe2, 0x5b, 0xdf, 0xbb, 0x70, 0x18, 0xf4, 0x07,
+       0x85, 0xf7, 0x17, 0xf0, 0xde, 0x66, 0xa3, 0xfa, 0x5b, 0x1a, 0x94, 0xfe,
+       0xee, 0x05, 0x38, 0x6d, 0x8c, 0x8e, 0x45, 0xba, 0x0e, 0xbc, 0x29, 0xfb,
+       0xb2, 0x68, 0x83, 0xf3, 0x56, 0x35, 0x0e, 0xce, 0x9f, 0x1b, 0xef, 0x27,
+       0x11, 0x79, 0x4f, 0xcd, 0x70, 0xff, 0x08, 0xd5, 0x27, 0x65, 0xe7, 0xb3,
+       0xe3, 0xae, 0x96, 0x67, 0x50, 0x66, 0xb8, 0x9f, 0xc6, 0x78, 0x8f, 0x47,
+       0xeb, 0x58, 0x9e, 0x67, 0x92, 0xc7, 0xd6, 0xf9, 0x6b, 0x7e, 0x8f, 0xa0,
+       0x33, 0x4f, 0xd2, 0x9d, 0x97, 0x11, 0xf1, 0xa8, 0xa6, 0x75, 0x2c, 0xfe,
+       0x0a, 0xf7, 0x0e, 0x76, 0x86, 0xf4, 0xe3, 0xcc, 0x63, 0x87, 0x56, 0x6e,
+       0x56, 0xcb, 0x9d, 0x79, 0x0e, 0x88, 0x77, 0xb1, 0x78, 0x61, 0x6b, 0x8a,
+       0x84, 0x76, 0x42, 0xab, 0x24, 0xa1, 0xdd, 0xb0, 0x39, 0xbd, 0xc2, 0x99,
+       0x47, 0xfb, 0x3f, 0x94, 0x5b, 0x3e, 0x14, 0xea, 0xd9, 0xf9, 0xb8, 0x4e,
+       0x88, 0x45, 0x8f, 0xc7, 0xf3, 0x3e, 0x38, 0x1f, 0xd5, 0x70, 0x5e, 0xec,
+       0x18, 0xaf, 0x7f, 0x2c, 0xb7, 0x02, 0x9f, 0xce, 0x3c, 0xe1, 0x6f, 0xd9,
+       0x73, 0x01, 0xff, 0x13, 0x55, 0x37, 0xf6, 0x6b, 0x91, 0xc3, 0xef, 0xab,
+       0x8f, 0xcc, 0x63, 0xf6, 0x4f, 0x35, 0xf0, 0xb4, 0x23, 0xc8, 0x4f, 0xd7,
+       0x73, 0x4f, 0x83, 0x25, 0xa9, 0xff, 0x3d, 0x0d, 0xc6, 0xfb, 0xcf, 0xdc,
+       0xd9, 0xf6, 0x2e, 0x50, 0x07, 0xc6, 0x7d, 0xcf, 0x17, 0xaf, 0x75, 0x4f,
+       0xc3, 0xbe, 0xf0, 0xf7, 0x34, 0x00, 0xdc, 0xa3, 0x13, 0x82, 0xfc, 0x50,
+       0x92, 0xa7, 0xbf, 0xe7, 0xac, 0x23, 0xaa, 0x07, 0xf7, 0x41, 0x03, 0x6f,
+       0xcb, 0xae, 0xad, 0xa4, 0xff, 0xba, 0x6f, 0xe6, 0x78, 0x5c, 0xcf, 0xcf,
+       0x85, 0x38, 0x78, 0xfe, 0xf7, 0x28, 0xbe, 0x9f, 0xd2, 0xbf, 0x3e, 0x83,
+       0xd3, 0x96, 0x01, 0xe2, 0xbd, 0x13, 0xd5, 0xf2, 0x6a, 0x80, 0xf3, 0x07,
+       0xe9, 0x9e, 0x9b, 0x01, 0x0f, 0xe2, 0x9e, 0x9d, 0x0e, 0x8b, 0xb6, 0x06,
+       0xfc, 0x8f, 0xc0, 0x4b, 0x04, 0xe7, 0x91, 0xed, 0x23, 0x07, 0xa0, 0x5c,
+       0xe0, 0x55, 0x31, 0x8f, 0xbc, 0x35, 0xc5, 0x1b, 0x8d, 0xf7, 0x01, 0x14,
+       0x99, 0xd0, 0x9f, 0x57, 0x37, 0xb5, 0x1d, 0x8c, 0x4c, 0xc2, 0x73, 0xb6,
+       0x09, 0x92, 0x1a, 0x94, 0x27, 0x66, 0x85, 0x78, 0x6d, 0x94, 0xce, 0x16,
+       0xc2, 0x65, 0x5d, 0x60, 0xdf, 0xf5, 0xcc, 0x3d, 0x60, 0xa3, 0xdf, 0x1d,
+       0x9b, 0x6f, 0x93, 0xe0, 0xfe, 0x96, 0x36, 0xd2, 0x56, 0x19, 0x0b, 0x76,
+       0xd7, 0x66, 0x12, 0x36, 0x3e, 0x58, 0xcf, 0xe9, 0x69, 0x6a, 0xf9, 0x01,
+       0x8c, 0xb3, 0x3b, 0x02, 0xec, 0xbc, 0x5f, 0xff, 0x7a, 0x26, 0xe1, 0x27,
+       0x6a, 0xb0, 0x8e, 0xd2, 0x80, 0x36, 0x4e, 0x4a, 0x0d, 0xca, 0x25, 0x14,
+       0xb9, 0xe0, 0x3f, 0x75, 0x99, 0x7c, 0xe1, 0xe2, 0xb5, 0x59, 0xe9, 0x95,
+       0x0b, 0xa1, 0x5d, 0x81, 0x8f, 0x84, 0x8d, 0xff, 0x55, 0xf3, 0x7b, 0x66,
+       0xea, 0x54, 0xcf, 0x32, 0xac, 0xb7, 0xcf, 0x8f, 0x7e, 0x51, 0x83, 0x90,
+       0xef, 0xf3, 0x4d, 0x04, 0xee, 0x37, 0xbc, 0x9d, 0xcb, 0xf3, 0xdb, 0x37,
+       0xb3, 0xbc, 0x5c, 0x72, 0xf9, 0xca, 0x15, 0xb9, 0x24, 0x78, 0x7e, 0x8a,
+       0xf6, 0x4f, 0x40, 0x3e, 0x35, 0xcc, 0xb4, 0xe1, 0xbd, 0xb1, 0x0d, 0x9d,
+       0x29, 0x78, 0xff, 0x16, 0xf1, 0x48, 0x78, 0xcf, 0x4b, 0x53, 0xe7, 0x31,
+       0x0f, 0x94, 0x1b, 0x8a, 0x8b, 0xed, 0x10, 0x6f, 0x76, 0xbf, 0x4f, 0x24,
+       0xb8, 0x97, 0x0d, 0xcf, 0xec, 0xa1, 0x1c, 0x54, 0xc8, 0xa7, 0x42, 0xdf,
+       0xa2, 0xfd, 0x90, 0x84, 0xfb, 0xfd, 0x33, 0x38, 0x5d, 0x8b, 0xfb, 0x94,
+       0xa8, 0x1e, 0x59, 0x1f, 0x4d, 0xe1, 0xde, 0xb0, 0x79, 0xd5, 0x01, 0xc8,
+       0xeb, 0x7e, 0xf7, 0x79, 0xda, 0x07, 0xfd, 0x74, 0x42, 0xd6, 0x4e, 0xfc,
+       0x90, 0xf6, 0xfb, 0x5d, 0xaa, 0xc4, 0x5a, 0xc6, 0xc2, 0x53, 0x21, 0x75,
+       0x18, 0x8f, 0x76, 0x62, 0x3f, 0x33, 0x79, 0x3f, 0xde, 0xbf, 0xd1, 0x71,
+       0xad, 0xc1, 0x71, 0xbf, 0xdb, 0xf9, 0x26, 0xae, 0xe7, 0x84, 0x99, 0x78,
+       0xad, 0x94, 0x7e, 0xcd, 0x15, 0x6c, 0x68, 0xf3, 0x0f, 0xe2, 0x30, 0xdf,
+       0x58, 0xe4, 0xaf, 0xdc, 0x61, 0x6d, 0xab, 0x06, 0x3d, 0xdb, 0x6b, 0x09,
+       0x14, 0xc2, 0xf9, 0xa9, 0xde, 0xd7, 0xde, 0x1b, 0x09, 0xfb, 0xd4, 0x1f,
+       0xfe, 0x9f, 0x0b, 0x36, 0xb0, 0x8f, 0xff, 0xac, 0x04, 0x6c, 0xf0, 0xfe,
+       0xf4, 0xc3, 0x7f, 0xb4, 0xc1, 0xfd, 0xc8, 0x1f, 0x3e, 0x2c, 0xe3, 0xbe,
+       0xde, 0x1c, 0xae, 0x77, 0x04, 0xbc, 0x9f, 0xe7, 0x74, 0x7e, 0x31, 0xcf,
+       0xf3, 0x0c, 0xd0, 0xe7, 0xbd, 0x2b, 0xbf, 0x2d, 0x09, 0xcd, 0xa3, 0x27,
+       0x2d, 0x0e, 0xe4, 0x9f, 0xc5, 0x3e, 0x19, 0x53, 0x1e, 0x04, 0xdf, 0x2d,
+       0xdd, 0x11, 0x0d, 0x16, 0x51, 0x5f, 0xb9, 0xb1, 0x3d, 0x51, 0x57, 0x16,
+       0x7a, 0xa4, 0x11, 0xee, 0x6b, 0x0d, 0x43, 0x47, 0x27, 0x38, 0xbf, 0x2c,
+       0xde, 0xb5, 0xc5, 0x02, 0xf7, 0x0b, 0x5c, 0xcc, 0xd3, 0x76, 0xc1, 0xf8,
+       0xa7, 0x15, 0x46, 0x3f, 0xa7, 0xf7, 0xd9, 0x7c, 0x70, 0x7f, 0xa2, 0x98,
+       0xcf, 0xdc, 0x5d, 0x45, 0x16, 0xb0, 0x4f, 0xfe, 0xdc, 0x19, 0x41, 0xfc,
+       0xa0, 0x0f, 0x95, 0x6e, 0x33, 0x3b, 0x4f, 0xe6, 0xae, 0x95, 0x28, 0x3d,
+       0x68, 0x1c, 0xef, 0xc6, 0x79, 0x1e, 0x7e, 0x3d, 0x1a, 0xfb, 0x5b, 0xf0,
+       0x14, 0x93, 0x4f, 0xf5, 0x74, 0xac, 0x16, 0x0a, 0x57, 0xad, 0x73, 0x31,
+       0xca, 0x21, 0xe3, 0x3a, 0x16, 0x7c, 0xa8, 0x4e, 0x86, 0x73, 0x1c, 0x0b,
+       0x1e, 0x95, 0x08, 0xec, 0xaf, 0x40, 0xfd, 0x87, 0x29, 0xde, 0xb4, 0x96,
+       0x1f, 0x63, 0x9e, 0xa8, 0x71, 0x9d, 0xf5, 0x5e, 0xe3, 0x7d, 0x76, 0x6e,
+       0x94, 0x8f, 0x0d, 0x1c, 0xbf, 0xf3, 0xd6, 0xe9, 0xbf, 0x37, 0x74, 0x3e,
+       0x8e, 0xfd, 0xcc, 0x27, 0xea, 0x7a, 0xb0, 0xa7, 0x17, 0xb4, 0x19, 0xbf,
+       0x4f, 0xf9, 0x0c, 0xec, 0x9f, 0x06, 0x83, 0x3c, 0x7b, 0x27, 0x8f, 0xdb,
+       0x5b, 0x25, 0xa4, 0x14, 0xee, 0x9d, 0x39, 0x60, 0x4d, 0x8b, 0xbb, 0xda,
+       0xbd, 0xaf, 0x67, 0x57, 0xda, 0x91, 0x38, 0x3f, 0x5f, 0x69, 0xc5, 0xe7,
+       0xe9, 0x95, 0x04, 0x9f, 0xcf, 0xe4, 0xa9, 0x08, 0xf7, 0x65, 0x9d, 0xc7,
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+       0x93, 0x75, 0x3d, 0xd2, 0x6b, 0x13, 0xd1, 0xfb, 0xa3, 0xf5, 0xd4, 0xf1,
+       0x81, 0xfd, 0xcf, 0xfa, 0xed, 0x89, 0x98, 0xd7, 0x44, 0xfb, 0x2f, 0xec,
+       0x00, 0x7b, 0x63, 0xbb, 0x19, 0xed, 0x09, 0x2f, 0x59, 0xe1, 0x84, 0xf3,
+       0xf6, 0x9e, 0x47, 0xcc, 0x28, 0x27, 0xe7, 0x76, 0xc4, 0xa3, 0x3f, 0x3c,
+       0x77, 0x2d, 0xdb, 0x27, 0x98, 0xbb, 0x2b, 0x1e, 0xcf, 0x07, 0x52, 0x7f,
+       0x14, 0xef, 0x11, 0x16, 0xf8, 0x38, 0xb9, 0xb6, 0xd2, 0x32, 0x0c, 0xf1,
+       0x95, 0x82, 0xf7, 0xf3, 0x90, 0x0e, 0x3d, 0x9d, 0x0b, 0x3c, 0xf5, 0xf7,
+       0x27, 0x0d, 0x78, 0x5a, 0xb7, 0xff, 0xb0, 0x53, 0xed, 0xef, 0x5f, 0x86,
+       0xe0, 0xe9, 0xd4, 0x00, 0x78, 0x3a, 0x15, 0x8a, 0xa7, 0x15, 0xf9, 0x5c,
+       0x8e, 0x70, 0x3c, 0x91, 0x87, 0xb9, 0xfc, 0xb9, 0xef, 0x50, 0x06, 0xdc,
+       0x5f, 0x75, 0xbe, 0x39, 0x12, 0xcf, 0x83, 0x18, 0xe9, 0x50, 0xe8, 0x29,
+       0x32, 0xff, 0x06, 0xcc, 0xbf, 0x12, 0x71, 0xaa, 0x9a, 0xe1, 0x0c, 0x2f,
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+       0xd5, 0xfc, 0x63, 0x1e, 0xe2, 0x85, 0xbc, 0x6f, 0xc3, 0xfb, 0x8b, 0x67,
+       0xa7, 0xb1, 0x7b, 0x5b, 0xee, 0x95, 0x18, 0xbf, 0xcc, 0x5e, 0x33, 0xa5,
+       0x06, 0xf4, 0xf9, 0xe3, 0xf9, 0xcc, 0xae, 0xf9, 0x3d, 0x95, 0x5b, 0xee,
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+       0x41, 0xf9, 0xdd, 0x95, 0x4e, 0x2c, 0xbf, 0xb7, 0x52, 0xc5, 0xe7, 0x9f,
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+       0x67, 0xcd, 0xd4, 0xeb, 0xbb, 0x1e, 0xb3, 0x7d, 0xb2, 0x13, 0xfc, 0xdb,
+       0x47, 0xd9, 0x3d, 0x4c, 0x73, 0x3d, 0x37, 0xea, 0xea, 0x13, 0x45, 0xb5,
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+       0x75, 0x79, 0xba, 0x72, 0x3d, 0xdc, 0x9b, 0x08, 0x74, 0xae, 0x4e, 0x40,
+       0xbe, 0x79, 0x80, 0xe7, 0x55, 0x52, 0x07, 0x9d, 0xe1, 0x85, 0x9f, 0x23,
+       0xfc, 0xba, 0xb9, 0x74, 0xe8, 0xf7, 0xe9, 0x7c, 0xbf, 0x3e, 0x6a, 0xc6,
+       0xef, 0x46, 0x7c, 0x08, 0xbc, 0xce, 0xdf, 0x24, 0x13, 0x8d, 0xf6, 0x37,
+       0x6f, 0x13, 0x95, 0x5f, 0x74, 0x8a, 0xa7, 0xda, 0x28, 0x9e, 0x68, 0xbb,
+       0x2f, 0x4e, 0xd8, 0xd0, 0x0f, 0x69, 0xdd, 0x35, 0xee, 0x9d, 0x09, 0xb4,
+       0x7c, 0x72, 0x97, 0x19, 0xe3, 0x07, 0x27, 0xd7, 0x26, 0xfe, 0x04, 0xec,
+       0xa7, 0x93, 0xbb, 0x1c, 0xb1, 0x84, 0x3e, 0xb5, 0x56, 0x99, 0xdb, 0x19,
+       0x76, 0xbc, 0x4f, 0x49, 0xf4, 0x5b, 0xb9, 0x76, 0x15, 0x9e, 0x87, 0xa9,
+       0xf7, 0x45, 0xb8, 0xd0, 0x9e, 0xe8, 0xf2, 0xfe, 0xbb, 0x28, 0xab, 0xe0,
+       0xb7, 0xc2, 0x24, 0x81, 0x6f, 0x8e, 0xcb, 0x3e, 0xbf, 0x84, 0xf8, 0x63,
+       0xf1, 0x83, 0x9d, 0x11, 0x68, 0x0f, 0x9f, 0xa6, 0x76, 0x1d, 0x5c, 0x3d,
+       0x7b, 0x5a, 0x22, 0x6b, 0xe1, 0x09, 0x07, 0xe6, 0xe3, 0xe8, 0xf7, 0x6f,
+       0xba, 0x1d, 0x3e, 0xe0, 0xeb, 0x9a, 0x7f, 0xc8, 0x6e, 0x27, 0xd0, 0xd3,
+       0xce, 0x48, 0x76, 0x7f, 0x08, 0x38, 0xc3, 0xf4, 0xfb, 0xe7, 0xc7, 0x32,
+       0xb6, 0x3e, 0x86, 0xf4, 0xa5, 0xb6, 0xfb, 0x91, 0x7f, 0x23, 0xd0, 0x5f,
+       0x98, 0xd7, 0xc3, 0xd6, 0x47, 0xa4, 0xb1, 0xc9, 0x80, 0xff, 0xd3, 0xf1,
+       0xc4, 0x1d, 0x4f, 0x27, 0xd1, 0xb8, 0xe2, 0xbd, 0x8f, 0x14, 0x8a, 0xa7,
+       0xc5, 0x99, 0xdd, 0x85, 0x7e, 0xda, 0xae, 0x2e, 0xc5, 0xef, 0xb8, 0x93,
+       0xb6, 0x3b, 0xbb, 0xcd, 0xcc, 0xee, 0x97, 0xa3, 0xfd, 0xda, 0x69, 0xb9,
+       0xf1, 0x97, 0x11, 0x5b, 0x98, 0x3c, 0x71, 0x0f, 0xbd, 0xad, 0x20, 0x14,
+       0x9e, 0xbe, 0x42, 0x58, 0x77, 0xd6, 0x70, 0xcf, 0x87, 0xf9, 0xb0, 0x7f,
+       0xb0, 0xd0, 0x57, 0x88, 0x72, 0xed, 0x61, 0x07, 0xf2, 0x95, 0x11, 0xee,
+       0xa7, 0x2c, 0x1a, 0xc2, 0xd7, 0x0b, 0x7c, 0x20, 0x05, 0xe5, 0x64, 0x90,
+       0xcf, 0xd8, 0x7e, 0x10, 0x15, 0x6e, 0xc3, 0x40, 0xde, 0xcc, 0x33, 0xbb,
+       0x86, 0x80, 0xbe, 0x3a, 0xb5, 0xde, 0x8c, 0x76, 0x29, 0xd5, 0x27, 0xb1,
+       0xb7, 0x61, 0x1c, 0x66, 0x0f, 0xd2, 0xf1, 0x29, 0x45, 0x9d, 0x0c, 0xeb,
+       0x3e, 0xb5, 0x2e, 0x85, 0x80, 0xdc, 0x12, 0xe3, 0xce, 0x5d, 0x2f, 0xf3,
+       0x7b, 0x42, 0x28, 0x5d, 0x42, 0xfd, 0x0d, 0xb2, 0x46, 0x6d, 0x07, 0x22,
+       0xf4, 0x96, 0x77, 0x9d, 0xa4, 0x91, 0xa1, 0xfd, 0xe9, 0xe6, 0xfe, 0xfb,
+       0x4a, 0x31, 0x2f, 0xdc, 0x68, 0xff, 0x8a, 0xe7, 0x97, 0x94, 0x57, 0xb5,
+       0x10, 0x3b, 0x62, 0xc9, 0x6b, 0xec, 0x7e, 0x7e, 0x52, 0xdc, 0xa3, 0xcc,
+       0x2c, 0x08, 0x5d, 0x07, 0xfb, 0x7d, 0x05, 0xa2, 0x4d, 0xd0, 0xe5, 0x6b,
+       0x2e, 0x4b, 0xfd, 0xed, 0x47, 0x31, 0x26, 0xb4, 0x6b, 0xe2, 0x20, 0x9e,
+       0x7e, 0xe6, 0xb8, 0x8c, 0x74, 0x76, 0x26, 0xb5, 0xad, 0xc4, 0x49, 0x49,
+       0xff, 0xac, 0xe9, 0x40, 0xc9, 0xf7, 0x69, 0xf9, 0x8b, 0x69, 0xde, 0x4f,
+       0x15, 0x5a, 0xbe, 0x6f, 0xb4, 0x16, 0x55, 0x40, 0x97, 0xb4, 0xd4, 0xb4,
+       0x7e, 0x14, 0xf8, 0x4f, 0xbd, 0x9d, 0x9f, 0xfc, 0x04, 0xee, 0xdd, 0xfb,
+       0xfc, 0x45, 0x33, 0x1c, 0x87, 0x27, 0x4b, 0x76, 0x2e, 0x1e, 0x8d, 0x71,
+       0x1f, 0x6e, 0x7f, 0xf7, 0x97, 0x5b, 0xe2, 0xfe, 0x3f, 0xf7, 0x30, 0xb8,
+       0x3f, 0x65, 0xa9, 0xda, 0x8e, 0x7a, 0x5c, 0x85, 0x43, 0x72, 0xb8, 0x7e,
+       0x1f, 0xce, 0x53, 0xe8, 0x75, 0xfb, 0x93, 0x12, 0xd8, 0x58, 0xe4, 0x93,
+       0xf1, 0xb6, 0xc7, 0xc0, 0x9f, 0x9e, 0x67, 0x38, 0x9f, 0xf2, 0x89, 0x99,
+       0xd9, 0x09, 0x23, 0x0a, 0x98, 0x9c, 0x12, 0xfa, 0xfe, 0x1e, 0x5e, 0x9e,
+       0x67, 0x62, 0x74, 0x4d, 0x5e, 0x97, 0x30, 0x0f, 0x9c, 0xf0, 0x7b, 0xe5,
+       0x85, 0x3e, 0x10, 0xf2, 0x5a, 0xc8, 0xfd, 0xfc, 0x02, 0x66, 0x5f, 0x08,
+       0x79, 0x0d, 0x99, 0x76, 0x20, 0xb7, 0x16, 0xc2, 0xed, 0x2d, 0x74, 0x9d,
+       0xcb, 0x76, 0x44, 0xf8, 0x7c, 0x29, 0xd8, 0xd6, 0x0e, 0x70, 0x5c, 0xcc,
+       0xd0, 0x44, 0x16, 0x17, 0xa8, 0xd8, 0x6e, 0x89, 0xe5, 0xc5, 0xa7, 0x81,
+       0x97, 0x1a, 0x48, 0x37, 0xce, 0xff, 0x73, 0xb3, 0x6f, 0x61, 0x77, 0x0a,
+       0xb4, 0xdf, 0xb2, 0x36, 0x01, 0xdb, 0x9b, 0x5d, 0x18, 0xa7, 0xe5, 0xfa,
+       0x05, 0xae, 0xb5, 0x06, 0xb9, 0xd4, 0xc0, 0xf9, 0xaf, 0xb1, 0x4d, 0xf2,
+       0xf9, 0x91, 0x7f, 0x98, 0x9e, 0x5c, 0xc0, 0xfb, 0x27, 0xa0, 0x67, 0x42,
+       0xe4, 0x58, 0x3f, 0xfd, 0x62, 0xd0, 0x2b, 0x0b, 0xb8, 0x5e, 0x5d, 0x40,
+       0x0c, 0x71, 0xde, 0x36, 0xbd, 0xbe, 0xf3, 0x44, 0xdb, 0x70, 0x5d, 0x4b,
+       0xe8, 0xb8, 0xa0, 0x3f, 0x83, 0xf3, 0xa2, 0xf6, 0x33, 0x85, 0xdd, 0x42,
+       0xcd, 0x77, 0x78, 0x3a, 0xce, 0x5b, 0x72, 0xf9, 0xc2, 0xcc, 0xa3, 0x81,
+       0x04, 0xfc, 0x90, 0x7f, 0xd7, 0xb8, 0x8b, 0xc5, 0xbd, 0x8d, 0xf3, 0x32,
+       0xae, 0x63, 0xb0, 0xf3, 0x5c, 0xe8, 0xba, 0xad, 0x2a, 0xbe, 0x38, 0x64,
+       0x5c, 0xc3, 0xbc, 0x05, 0xbc, 0x31, 0x50, 0x1c, 0x82, 0x07, 0x01, 0xf7,
+       0x85, 0x5e, 0x06, 0xcf, 0x85, 0x9d, 0x12, 0xe2, 0xeb, 0x2f, 0xdc, 0x5e,
+       0xa3, 0x7f, 0x18, 0x9f, 0x36, 0xe2, 0xbf, 0x81, 0x78, 0xa6, 0x43, 0x9e,
+       0x42, 0xc3, 0x93, 0x54, 0x7e, 0xa6, 0x04, 0xe9, 0x41, 0xd0, 0xc1, 0xe2,
+       0xdd, 0x3e, 0x0b, 0xd8, 0xcb, 0x5f, 0x90, 0xb6, 0xd8, 0x18, 0xca, 0x07,
+       0xcb, 0x36, 0xed, 0xbe, 0x63, 0xa2, 0x0a, 0xfe, 0xf3, 0x31, 0xf4, 0x43,
+       0xea, 0x12, 0xfc, 0x19, 0xa6, 0x78, 0x42, 0x12, 0xbd, 0x2f, 0x3d, 0x5d,
+       0x73, 0xd3, 0xb5, 0xe3, 0xfc, 0xff, 0x2a, 0x38, 0xc1, 0x2a, 0xe0, 0x7e,
+       0x5a, 0x6c, 0x47, 0xe1, 0xb2, 0x60, 0x9b, 0xec, 0x8e, 0x2c, 0xd4, 0xd5,
+       0xe3, 0x79, 0xda, 0x5e, 0x84, 0xd7, 0x22, 0xaf, 0xd7, 0x02, 0x71, 0xd0,
+       0x45, 0x3c, 0xae, 0x78, 0xad, 0x79, 0x36, 0x29, 0xec, 0x3c, 0xef, 0xb5,
+       0xe7, 0xcb, 0xe0, 0xf8, 0xaf, 0x9e, 0xf7, 0xd3, 0x05, 0x7a, 0x3b, 0x36,
+       0x68, 0x1f, 0x65, 0x84, 0xf5, 0xb7, 0xfa, 0xec, 0xa2, 0x6b, 0xe8, 0xe3,
+       0x0f, 0xcc, 0xfe, 0x91, 0xa0, 0x8f, 0x03, 0x23, 0x15, 0xd4, 0x47, 0x5f,
+       0x2b, 0xae, 0xf7, 0xca, 0x93, 0x40, 0x3f, 0x67, 0xa0, 0xdf, 0x30, 0x90,
+       0xbc, 0x5d, 0xc8, 0xf5, 0xf2, 0x02, 0xd0, 0xd3, 0xf4, 0xf9, 0xe9, 0xa6,
+       0xbd, 0x78, 0x6e, 0xec, 0x2f, 0x4f, 0xee, 0xc5, 0x7d, 0x43, 0xcb, 0x8b,
+       0x0b, 0x62, 0xc1, 0x5e, 0xfe, 0x74, 0xd3, 0xbc, 0x9f, 0x40, 0xde, 0xfc,
+       0xa7, 0xbb, 0xe6, 0xa1, 0x5e, 0x6e, 0x78, 0x46, 0xe8, 0x65, 0xcd, 0x12,
+       0xaa, 0xef, 0x2b, 0x37, 0xd5, 0x3f, 0xf7, 0x7f, 0x80, 0x4e, 0x77, 0x44,
+       0xe2, 0x09, 0x85, 0x85, 0x5d, 0x1a, 0xb7, 0xc7, 0xa9, 0xfc, 0x03, 0xb9,
+       0xb8, 0x89, 0xc9, 0x3f, 0xf2, 0x24, 0x93, 0x8f, 0x0d, 0xb1, 0xec, 0xde,
+       0x6f, 0xaa, 0xbf, 0xb2, 0xa0, 0xde, 0x83, 0x0b, 0xb5, 0x2c, 0xa0, 0xf7,
+       0x90, 0xf7, 0xa8, 0xd7, 0x1e, 0x9c, 0xa7, 0x95, 0x62, 0x7b, 0x62, 0xf7,
+       0xb3, 0x7b, 0x21, 0xed, 0x7e, 0xd0, 0x5f, 0x42, 0xbf, 0x0a, 0xbd, 0x7b,
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+       0xe7, 0x45, 0x30, 0xaf, 0xef, 0x75, 0x7e, 0xf2, 0x3d, 0x2b, 0x5d, 0xda,
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+       0x78, 0x88, 0xdf, 0xd2, 0x4f, 0xfb, 0xae, 0x24, 0x5e, 0x8d, 0x7e, 0xf4,
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+       0x6f, 0x3f, 0xd3, 0x5d, 0x6c, 0x7d, 0x21, 0xfd, 0xf4, 0xfe, 0x33, 0xfd,
+       0xec, 0x75, 0xe9, 0xe7, 0x23, 0xec, 0xa3, 0xa9, 0x63, 0xdd, 0x51, 0x63,
+       0x40, 0x3e, 0x54, 0xdd, 0xa8, 0x8b, 0xfb, 0x2d, 0xfd, 0x91, 0x2b, 0x0e,
+       0xec, 0x2b, 0xf2, 0x0e, 0xfb, 0x1d, 0x93, 0xa5, 0xab, 0xdb, 0x47, 0x8d,
+       0xa3, 0xfd, 0x2f, 0xfd, 0xaf, 0x57, 0x46, 0x2d, 0x0c, 0xf1, 0xc7, 0x97,
+       0x5f, 0x92, 0x89, 0x1b, 0xee, 0x47, 0xb8, 0x24, 0xe1, 0xf3, 0x8b, 0xfd,
+       0x7f, 0xb2, 0xc0, 0xf9, 0xfc, 0xe5, 0xfb, 0xf6, 0x5b, 0x26, 0xe7, 0xc3,
+       0xef, 0x2f, 0xec, 0xb7, 0x54, 0x86, 0xcc, 0x6b, 0x99, 0xc8, 0xb3, 0x24,
+       0x3d, 0xca, 0x8c, 0x10, 0xfd, 0x1e, 0x37, 0xc6, 0xc4, 0xe5, 0x06, 0xfb,
+       0x1d, 0x87, 0xa5, 0xff, 0x75, 0x46, 0x01, 0x7c, 0x2e, 0x35, 0xb5, 0x7f,
+       0xfa, 0x0c, 0xc4, 0x81, 0x6e, 0x90, 0xc2, 0xee, 0xd7, 0xfe, 0x95, 0xaf,
+       0xef, 0xa3, 0x01, 0xce, 0x83, 0x39, 0xc6, 0x30, 0xf9, 0x57, 0x56, 0xec,
+       0x4e, 0x82, 0x75, 0x5e, 0x04, 0x19, 0x44, 0xeb, 0x57, 0xae, 0x09, 0xbf,
+       0xcf, 0x3f, 0x67, 0x0c, 0x8b, 0x27, 0xd6, 0xf1, 0x7b, 0x95, 0xe7, 0x95,
+       0xd8, 0xac, 0x2a, 0x85, 0xf3, 0xf8, 0xe3, 0x6c, 0x7f, 0x7a, 0xe1, 0xe6,
+       0x94, 0xb1, 0x10, 0xe7, 0x75, 0x14, 0x54, 0x8c, 0x1a, 0x03, 0xf3, 0x1d,
+       0x30, 0x5e, 0x1a, 0x60, 0xf1, 0xd2, 0x4e, 0x16, 0x2f, 0xad, 0x4b, 0xe8,
+       0x7e, 0x00, 0xee, 0x31, 0xbd, 0xeb, 0x57, 0x4f, 0x6d, 0x84, 0x7b, 0x4d,
+       0xa7, 0x6e, 0x14, 0x7c, 0x42, 0xf0, 0xf7, 0x72, 0x6a, 0x22, 0x04, 0xdf,
+       0xed, 0xba, 0xb3, 0xaa, 0x0c, 0xe3, 0x5f, 0x58, 0x2e, 0x1b, 0xf3, 0xc2,
+       0x46, 0xe0, 0x9b, 0x23, 0xfc, 0x5e, 0xf1, 0xd9, 0xa5, 0x05, 0x51, 0x20,
+       0x1f, 0x7a, 0x52, 0xa2, 0x4d, 0x76, 0x2a, 0x47, 0x46, 0xe4, 0xd7, 0xdf,
+       0x05, 0xf3, 0x98, 0x5d, 0x7a, 0xd3, 0x64, 0x78, 0x5f, 0x1e, 0x61, 0xcb,
+       0xac, 0x67, 0x71, 0x77, 0xa4, 0x8b, 0x11, 0xf9, 0x9e, 0x62, 0xf8, 0x0e,
+       0xf5, 0x21, 0xde, 0xa1, 0x59, 0x58, 0xfc, 0x4b, 0x7b, 0x4b, 0xc6, 0xf8,
+       0x97, 0x56, 0x18, 0xad, 0x85, 0xdb, 0x7f, 0x1e, 0xcb, 0xe1, 0x70, 0xd7,
+       0x18, 0x76, 0x4f, 0xf1, 0x11, 0x13, 0x9d, 0xe7, 0xd8, 0xe0, 0x3c, 0xc4,
+       0xf8, 0xd4, 0x60, 0x79, 0xa0, 0x9b, 0xf6, 0x77, 0x6a, 0xf5, 0xb0, 0x22,
+       0xb8, 0x97, 0xbf, 0x25, 0xbf, 0x7c, 0x16, 0xd2, 0x13, 0x1f, 0xbf, 0x25,
+       0x5f, 0xab, 0x86, 0xb2, 0x18, 0x9f, 0x2e, 0xb7, 0x10, 0xde, 0x0f, 0x76,
+       0x1e, 0x15, 0x9c, 0x2e, 0x66, 0x8d, 0x61, 0x78, 0xf3, 0x94, 0x51, 0x7a,
+       0x0b, 0xf1, 0x1b, 0x67, 0x54, 0x45, 0xeb, 0xca, 0x33, 0x6b, 0x13, 0x89,
+       0x3b, 0x34, 0x0e, 0x3b, 0x33, 0x59, 0x57, 0x9e, 0x55, 0x97, 0xa6, 0xab,
+       0x7f, 0xf7, 0xfc, 0x3c, 0xdd, 0xf7, 0x69, 0x11, 0xdd, 0xc5, 0xcd, 0xd7,
+       0x61, 0x07, 0x37, 0xd9, 0x6c, 0x51, 0x60, 0x8f, 0x7d, 0xd8, 0xf9, 0xcd,
+       0x7f, 0xdf, 0x03, 0xf6, 0xdd, 0x36, 0xd9, 0x25, 0xd1, 0xf5, 0x2c, 0x7e,
+       0x6d, 0xfb, 0x7f, 0xc3, 0xef, 0xa3, 0x9c, 0x87, 0x1f, 0x5c, 0x60, 0xe7,
+       0xaf, 0x30, 0x1e, 0xf6, 0xf9, 0x11, 0xf6, 0x7b, 0x7f, 0xd4, 0xae, 0x53,
+       0x42, 0xf7, 0x75, 0xce, 0x91, 0x6e, 0xcc, 0x2b, 0x0c, 0xd9, 0x2f, 0x08,
+       0xbb, 0x9f, 0x2a, 0xf6, 0x0b, 0x96, 0xda, 0xbb, 0x30, 0xff, 0xef, 0x7f,
+       0xbb, 0xaf, 0xd3, 0x32, 0x86, 0xef, 0x17, 0x8c, 0x25, 0x63, 0x41, 0x1f,
+       0x9e, 0x6f, 0x7e, 0x17, 0xe3, 0x70, 0xcb, 0x63, 0xd8, 0xba, 0xce, 0xbd,
+       0xc2, 0xef, 0x21, 0x07, 0x3d, 0x42, 0xe9, 0xfc, 0x66, 0x68, 0x08, 0xf7,
+       0x85, 0x5d, 0x5a, 0x85, 0xbf, 0xef, 0x53, 0xc9, 0x7f, 0xbf, 0x75, 0xd8,
+       0x18, 0x95, 0xf9, 0x05, 0x23, 0xee, 0x53, 0xe0, 0xdc, 0x77, 0x13, 0x7d,
+       0x82, 0xfc, 0x9f, 0x4c, 0xe5, 0x54, 0x1c, 0xa5, 0x93, 0xee, 0xfd, 0xa4,
+       0x60, 0x1f, 0xe4, 0x5d, 0xa4, 0xd8, 0x30, 0x9f, 0xbc, 0xf1, 0xd2, 0xed,
+       0x18, 0xe7, 0x3e, 0x12, 0xe5, 0xcd, 0xbf, 0x8f, 0xd6, 0x5b, 0xba, 0x6e,
+       0x0a, 0x96, 0x97, 0x5f, 0x8a, 0xc6, 0x7e, 0x7f, 0x2f, 0x77, 0x4f, 0xc6,
+       0xbc, 0xe6, 0x97, 0xd9, 0xef, 0x21, 0x4e, 0x4b, 0x9e, 0xbd, 0x1a, 0xe6,
+       0x0f, 0xf5, 0xef, 0xa7, 0xe3, 0x4d, 0xfb, 0xd5, 0xcd, 0x35, 0x00, 0xa7,
+       0xe5, 0xfb, 0xd8, 0xf9, 0xa9, 0x69, 0xf2, 0x1f, 0x8a, 0xa1, 0x9f, 0x65,
+       0x6d, 0x53, 0xb0, 0xfd, 0x34, 0x99, 0x1c, 0x91, 0xa8, 0xbd, 0x10, 0x77,
+       0xe9, 0x1e, 0xec, 0x77, 0x1a, 0xe8, 0x7a, 0x5a, 0x96, 0x4b, 0x6c, 0x8f,
+       0x81, 0xfe, 0x95, 0x2d, 0xfe, 0xcc, 0x67, 0x41, 0xae, 0x58, 0x6c, 0x28,
+       0x57, 0x9a, 0x2e, 0x45, 0x62, 0xbb, 0xa9, 0x95, 0x4c, 0x4f, 0xfb, 0xc6,
+       0x30, 0x3b, 0xc6, 0xdc, 0xc3, 0xe6, 0x55, 0x7d, 0xe9, 0x36, 0xfc, 0x2e,
+       0xf0, 0xff, 0xc2, 0x98, 0x54, 0xdd, 0x3d, 0x32, 0x66, 0xc7, 0x36, 0x05,
+       0xce, 0x27, 0x98, 0x7b, 0x24, 0xac, 0x7f, 0xcb, 0xa5, 0x3c, 0x7c, 0x8a,
+       0x75, 0xbe, 0x95, 0xfd, 0x3c, 0xde, 0x57, 0x62, 0x76, 0x7c, 0x3d, 0x19,
+       0xf2, 0x3a, 0xdf, 0x4a, 0x92, 0xec, 0x68, 0x7e, 0x18, 0xe4, 0xee, 0x85,
+       0xe6, 0xd2, 0x38, 0x12, 0x46, 0x2e, 0xf5, 0x8d, 0x73, 0x89, 0xe5, 0x01,
+       0x47, 0x5c, 0x62, 0x79, 0xc1, 0x2f, 0x14, 0xb9, 0x3b, 0x81, 0xbf, 0xa7,
+       0x3f, 0xdc, 0xa3, 0xc0, 0xfe, 0x0e, 0x89, 0xb1, 0xda, 0x01, 0x5e, 0xd3,
+       0x27, 0x14, 0xa9, 0x0b, 0x43, 0xf8, 0x49, 0x3e, 0x70, 0x97, 0x05, 0xf0,
+       0x62, 0x7e, 0xf2, 0x98, 0x05, 0xf4, 0x7e, 0x04, 0x7d, 0x56, 0x86, 0x7c,
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+       0x41, 0xe8, 0x19, 0xa2, 0x76, 0xe8, 0x7e, 0x5f, 0x4d, 0xf0, 0xcb, 0xaf,
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+       0x9f, 0x7a, 0xa3, 0x48, 0x7b, 0x17, 0xe6, 0xdb, 0x5d, 0xce, 0x7e, 0x27,
+       0x83, 0x28, 0xdd, 0xa3, 0x60, 0x5f, 0xe5, 0x5f, 0x35, 0x7f, 0x8a, 0x67,
+       0xab, 0x84, 0xf6, 0x7e, 0x0f, 0xe6, 0xc5, 0x4f, 0x9f, 0xa0, 0x9a, 0x60,
+       0xbf, 0xe0, 0xfd, 0xbe, 0x75, 0x30, 0xbe, 0xbd, 0xd6, 0x3a, 0x7e, 0xcb,
+       0xeb, 0xff, 0x5e, 0x26, 0x2d, 0xd0, 0xef, 0xef, 0x27, 0x4d, 0xea, 0x76,
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+       0xd1, 0x2a, 0xf0, 0xf7, 0x34, 0x70, 0x96, 0x8a, 0x83, 0x76, 0x2d, 0x7d,
+       0x8f, 0xf7, 0xe5, 0x35, 0xbd, 0x1e, 0xb1, 0x55, 0xa2, 0xdf, 0x9b, 0x62,
+       0xa9, 0x7f, 0x4b, 0xc7, 0xaf, 0x7c, 0x23, 0xd2, 0x0f, 0x74, 0xbc, 0xff,
+       0x8d, 0x48, 0x05, 0x7f, 0xa7, 0xa8, 0x58, 0xfb, 0x02, 0xe4, 0x65, 0xe5,
+       0x1b, 0x59, 0x55, 0xe0, 0xcf, 0xb9, 0x3b, 0x23, 0x14, 0x82, 0x76, 0x8e,
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+       0x69, 0xd8, 0x0f, 0x7d, 0x58, 0x2a, 0xd8, 0x07, 0x76, 0x81, 0x6a, 0xc3,
+       0xfb, 0x89, 0x05, 0x5f, 0x4e, 0x03, 0x3f, 0x88, 0xbe, 0xff, 0x7f, 0x46,
+       0xe4, 0x8e, 0x2c, 0x00, 0x80, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00,
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+       0xb5, 0xf0, 0x3e, 0x73, 0xce, 0xbc, 0x92, 0x99, 0xc9, 0xe4, 0x49, 0x42,
+       0x1e, 0x9c, 0x40, 0x08, 0x41, 0x02, 0x4c, 0x26, 0x21, 0x84, 0x10, 0x60,
+       0x12, 0x02, 0xa2, 0x02, 0x0e, 0x50, 0x15, 0x30, 0xc8, 0x80, 0x08, 0x11,
+       0x09, 0x09, 0x51, 0x5b, 0xac, 0xf6, 0xcf, 0x84, 0x24, 0x10, 0x45, 0x2d,
+       0x56, 0xdb, 0x06, 0x8b, 0x74, 0xc0, 0x47, 0x51, 0x69, 0x6f, 0x40, 0x6c,
+       0xd3, 0x16, 0x61, 0x78, 0x68, 0x63, 0xf5, 0xd3, 0x68, 0xef, 0x6d, 0xf1,
+       0xd6, 0xda, 0xf8, 0xb8, 0x88, 0x8a, 0x35, 0x82, 0xf5, 0xa3, 0xb7, 0x28,
+       0xff, 0x5a, 0x6b, 0xef, 0x9d, 0x99, 0x33, 0x49, 0x10, 0xed, 0xbd, 0xff,
+       0x1f, 0xe5, 0x3b, 0x59, 0x67, 0xef, 0xb3, 0x1f, 0x6b, 0xad, 0xbd, 0x5e,
+       0x7b, 0xed, 0x9d, 0x79, 0xe3, 0x12, 0x43, 0x2d, 0x0a, 0x63, 0xeb, 0xce,
+       0x25, 0x32, 0x96, 0xcc, 0xd8, 0x3c, 0x95, 0x75, 0x2b, 0x49, 0x8c, 0xd5,
+       0x9d, 0xcb, 0x65, 0xac, 0x98, 0xb1, 0xf5, 0xe7, 0x92, 0xe9, 0x7d, 0xfd,
+       0x39, 0x3b, 0x3d, 0x57, 0x9e, 0x1b, 0x47, 0xef, 0xad, 0xe7, 0x54, 0xe6,
+       0x03, 0x78, 0xd5, 0x39, 0x85, 0xf9, 0x00, 0xbe, 0x6a, 0xa6, 0x33, 0x68,
+       0x4a, 0x60, 0xec, 0x42, 0x51, 0x20, 0xd3, 0x93, 0x0a, 0xed, 0xb4, 0x5c,
+       0x3e, 0x87, 0xb9, 0x18, 0x0b, 0x6c, 0xca, 0x28, 0x09, 0x38, 0x18, 0x9b,
+       0x7f, 0x57, 0xaf, 0x66, 0x4b, 0x61, 0x8c, 0x39, 0x2c, 0xee, 0xc7, 0xa1,
+       0xbf, 0xf9, 0x65, 0x45, 0xe9, 0xab, 0xe1, 0xfd, 0x05, 0xfc, 0x99, 0xc1,
+       0x58, 0xcb, 0x91, 0x25, 0x4c, 0x77, 0x42, 0xbb, 0x29, 0x7e, 0x8b, 0x0f,
+       0xde, 0xaf, 0x82, 0xe7, 0xcc, 0xa8, 0xf2, 0x9b, 0x18, 0xf3, 0x75, 0x02,
+       0xcc, 0x98, 0x7b, 0x76, 0x5a, 0x09, 0x7c, 0xdf, 0x9a, 0x6b, 0xba, 0x87,
+       0x45, 0xca, 0x75, 0x8f, 0x89, 0xb1, 0x49, 0x58, 0xde, 0x4c, 0xcf, 0xf9,
+       0xb2, 0xbe, 0xde, 0xc5, 0x58, 0x1a, 0x63, 0x37, 0xb8, 0x19, 0xff, 0xd9,
+       0x08, 0x83, 0xcb, 0x60, 0xcc, 0x29, 0xea, 0xaf, 0x74, 0x84, 0x47, 0x9b,
+       0xa0, 0x3d, 0x73, 0x83, 0xdd, 0xb3, 0x09, 0xc6, 0x75, 0x26, 0x45, 0x9f,
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+       0x09, 0xe3, 0x6e, 0xdc, 0xae, 0x78, 0x82, 0xf0, 0xf9, 0x8d, 0xa5, 0x4e,
+       0x1b, 0x83, 0x79, 0x96, 0x9e, 0x68, 0xb0, 0x04, 0x0a, 0x23, 0xfd, 0x2f,
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+       0x8e, 0x4f, 0xa6, 0x97, 0x99, 0x70, 0x3c, 0xb7, 0xd9, 0xf0, 0x77, 0x1c,
+       0x10, 0xc0, 0xa5, 0x8c, 0xdd, 0x2a, 0xc6, 0xf7, 0x59, 0xc3, 0xe4, 0x61,
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+       0x70, 0x3c, 0xe6, 0x90, 0xd5, 0xb3, 0x0b, 0xc6, 0x73, 0xca, 0x1e, 0x50,
+       0x19, 0x8c, 0xe7, 0x54, 0x36, 0x73, 0x3f, 0x08, 0x43, 0x3c, 0x65, 0x66,
+       0x41, 0x37, 0xd0, 0xeb, 0xc6, 0x0e, 0x95, 0x05, 0xa1, 0xfd, 0x55, 0xf0,
+       0x0c, 0xc0, 0xf3, 0x54, 0x22, 0xf3, 0x25, 0x7a, 0x11, 0x9f, 0x30, 0xcf,
+       0x02, 0xde, 0xf6, 0x05, 0xf8, 0xf7, 0x77, 0x6d, 0x5b, 0x0e, 0x1b, 0x05,
+       0xf4, 0x6d, 0xfc, 0xd3, 0x5b, 0xda, 0x48, 0xc6, 0x6e, 0xce, 0xef, 0x99,
+       0x10, 0x86, 0x76, 0x6b, 0x2a, 0xc3, 0xa9, 0xd7, 0x41, 0xbb, 0xa7, 0x1f,
+       0x33, 0x7b, 0x82, 0xd0, 0xef, 0xba, 0x23, 0xaf, 0x97, 0x9a, 0xa0, 0xfc,
+       0xc3, 0x5c, 0xdf, 0x30, 0xa6, 0x32, 0x36, 0x66, 0x78, 0x60, 0x0e, 0xce,
+       0x67, 0xed, 0xc2, 0xd0, 0x2f, 0xcc, 0x00, 0xdf, 0x72, 0xdf, 0x33, 0xae,
+       0x29, 0x7a, 0x04, 0x9f, 0x9d, 0x5a, 0x78, 0xb4, 0x06, 0xdf, 0x77, 0x02,
+       0x1e, 0x83, 0x30, 0xae, 0xce, 0x7b, 0xd5, 0x39, 0x21, 0xa2, 0x17, 0x8b,
+       0x5f, 0x30, 0x1e, 0x1f, 0x80, 0x3d, 0xa8, 0x3a, 0x7b, 0x81, 0x12, 0x4c,
+       0x00, 0xfc, 0xb1, 0xea, 0xa9, 0x7c, 0xde, 0x36, 0x3e, 0xb6, 0xb5, 0xe7,
+       0x46, 0x11, 0x7e, 0xce, 0x36, 0x58, 0xc7, 0x1f, 0x80, 0x76, 0xce, 0xea,
+       0x4e, 0x0f, 0xbe, 0xaf, 0x3b, 0xb7, 0x88, 0xde, 0xdf, 0xd2, 0x7e, 0x05,
+       0x3d, 0xcd, 0xbd, 0x57, 0x08, 0xbe, 0x8c, 0xe7, 0xfc, 0x9a, 0xb9, 0x6c,
+       0x13, 0xf2, 0x59, 0x9d, 0x06, 0x95, 0xe1, 0xbb, 0x3a, 0x47, 0x42, 0x28,
+       0x08, 0xf3, 0x99, 0xf7, 0x6f, 0xc0, 0x7f, 0x80, 0xf2, 0xf5, 0x07, 0x16,
+       0xf8, 0x2b, 0x91, 0xef, 0x0a, 0x14, 0xcf, 0x68, 0x78, 0xac, 0xdb, 0x76,
+       0x85, 0xe0, 0xf3, 0xdd, 0xf7, 0x97, 0x03, 0x5e, 0xe7, 0x7d, 0x92, 0xe2,
+       0x69, 0x81, 0xf7, 0xbf, 0x6a, 0x4a, 0x07, 0x64, 0x45, 0xf8, 0x7f, 0xd6,
+       0xb9, 0x05, 0x54, 0x2f, 0xe1, 0xdc, 0xf5, 0xd4, 0x9f, 0xe4, 0x7f, 0xab,
+       0xe0, 0x77, 0x33, 0xf2, 0x7f, 0x14, 0xdf, 0xc3, 0x77, 0x8c, 0xc1, 0x77,
+       0x81, 0xa2, 0xc0, 0x9d, 0x88, 0xa7, 0xaa, 0xa7, 0xff, 0xf9, 0xcc, 0x7f,
+       0xc2, 0xab, 0x2b, 0xb5, 0x70, 0xfe, 0x4f, 0x52, 0xf0, 0xe9, 0x24, 0xfe,
+       0x89, 0xac, 0x03, 0x9b, 0xfb, 0xf1, 0x5c, 0x5a, 0x07, 0xfa, 0xea, 0x28,
+       0x3e, 0x52, 0x8f, 0x2e, 0xb1, 0xe8, 0x80, 0x2f, 0xf3, 0x43, 0x6f, 0xd3,
+       0x3a, 0xb0, 0xc2, 0x73, 0x66, 0x54, 0xf9, 0x7a, 0xe4, 0xeb, 0x42, 0xc4,
+       0x4c, 0xaf, 0xb6, 0xd0, 0x19, 0x79, 0x1f, 0xfc, 0x9a, 0xfc, 0xbf, 0x5e,
+       0xd4, 0x9f, 0x63, 0x65, 0xcb, 0xfd, 0xd8, 0x9e, 0xd6, 0x93, 0x13, 0xdd,
+       0xde, 0xe1, 0xa2, 0xaa, 0x07, 0x3d, 0x50, 0xde, 0xe1, 0x51, 0x78, 0x7b,
+       0xff, 0x43, 0xe3, 0x06, 0x3c, 0xd9, 0x10, 0xbf, 0x30, 0x7e, 0x1f, 0xd2,
+       0x6b, 0x7e, 0x99, 0x6e, 0xba, 0x27, 0x17, 0xfb, 0x91, 0xe3, 0xe7, 0x7c,
+       0xf2, 0x55, 0xe3, 0x6f, 0x13, 0xf5, 0x5f, 0x55, 0xd9, 0x46, 0x6c, 0xf7,
+       0xd5, 0x19, 0x33, 0x7a, 0x7c, 0xd0, 0xde, 0x91, 0x3b, 0x8b, 0x8b, 0x55,
+       0x3d, 0xd2, 0xef, 0xd3, 0x1e, 0x0b, 0xb5, 0x37, 0x0f, 0x68, 0x87, 0xeb,
+       0xa8, 0xef, 0x39, 0x6b, 0x68, 0x77, 0x2e, 0x8a, 0x11, 0xc6, 0x14, 0xa8,
+       0xff, 0xc9, 0x73, 0x63, 0x43, 0xf7, 0xc0, 0x14, 0xdf, 0x62, 0x7d, 0xe7,
+       0x71, 0x3c, 0xc1, 0x83, 0xf1, 0x3a, 0xce, 0xaf, 0xfe, 0x50, 0x3c, 0xd5,
+       0xaf, 0x8f, 0x4b, 0x08, 0x29, 0x50, 0x5e, 0xef, 0xea, 0xcb, 0xf7, 0xc3,
+       0x78, 0x66, 0x1e, 0xb6, 0x87, 0x91, 0xaf, 0x8e, 0x1c, 0xb6, 0x6b, 0x0c,
+       0xfa, 0xad, 0x28, 0xb9, 0xf1, 0x69, 0xc4, 0xd3, 0xcc, 0xc3, 0x63, 0xaa,
+       0x15, 0xe0, 0x43, 0xdf, 0x41, 0xab, 0xc6, 0xa0, 0xde, 0xdf, 0x27, 0xf8,
+       0xf6, 0x22, 0x1f, 0x0c, 0x35, 0x7e, 0x39, 0xbe, 0xd8, 0xa7, 0x9c, 0xbf,
+       0xe4, 0x2b, 0xb9, 0x5e, 0xe4, 0xfa, 0x90, 0xeb, 0x21, 0x76, 0xfd, 0xc8,
+       0xf5, 0x70, 0xd5, 0x56, 0x4f, 0xc2, 0x77, 0x90, 0x4e, 0x80, 0x98, 0xc7,
+       0x71, 0xfd, 0x68, 0xc1, 0xbd, 0x38, 0x8f, 0x3a, 0x3d, 0xbe, 0x08, 0xd7,
+       0xa5, 0x5c, 0x47, 0xeb, 0x0f, 0x28, 0xb4, 0xce, 0x40, 0xe8, 0x7a, 0x46,
+       0xeb, 0x91, 0x75, 0x24, 0xd7, 0x4d, 0x64, 0x9d, 0x98, 0x08, 0x0f, 0xf3,
+       0x84, 0x9e, 0x18, 0x6a, 0x9d, 0xd4, 0x89, 0x75, 0x71, 0x93, 0x58, 0x17,
+       0x72, 0x3d, 0x1c, 0x53, 0x3b, 0x1f, 0x2c, 0x87, 0xef, 0x66, 0x16, 0x05,
+       0xfe, 0x82, 0x78, 0x92, 0xeb, 0x62, 0xdd, 0xfe, 0x58, 0xbd, 0x30, 0x24,
+       0x5f, 0x31, 0xe4, 0xab, 0x9b, 0x52, 0x1a, 0x18, 0xf2, 0x55, 0x1d, 0x3c,
+       0xa3, 0xf9, 0xca, 0x3a, 0xc4, 0x7a, 0x78, 0x07, 0xf9, 0x23, 0xf5, 0xd2,
+       0xd7, 0x43, 0xcf, 0x25, 0xf2, 0xd3, 0xdf, 0x91, 0x9f, 0x26, 0xfd, 0xaf,
+       0xf2, 0xd3, 0xdf, 0x91, 0x6f, 0x06, 0xe1, 0xa7, 0xcf, 0xff, 0x15, 0x7e,
+       0x8a, 0xe5, 0x97, 0xb3, 0x0d, 0x7f, 0x2a, 0xd1, 0x61, 0x3c, 0x67, 0x4b,
+       0x40, 0xce, 0xe6, 0x46, 0xf8, 0xed, 0xaa, 0x97, 0xd8, 0xf8, 0x03, 0xf0,
+       0x9e, 0x8d, 0x72, 0x7a, 0x90, 0x7f, 0xba, 0xe3, 0xf8, 0x3c, 0xbb, 0x2d,
+       0xd9, 0xa1, 0x16, 0xac, 0x77, 0x81, 0x35, 0x20, 0x1e, 0xa5, 0xfe, 0xbf,
+       0x09, 0xe9, 0x9e, 0x1c, 0xe1, 0x53, 0xaf, 0x37, 0x30, 0xbc, 0x68, 0x52,
+       0x84, 0xfe, 0xdd, 0x71, 0xc1, 0xc2, 0x0d, 0x85, 0x97, 0x4e, 0x67, 0x6b,
+       0x4a, 0x8f, 0xc5, 0x57, 0x88, 0xf4, 0xee, 0x31, 0xe8, 0xff, 0xba, 0x21,
+       0xe8, 0x3c, 0xa2, 0xe8, 0xeb, 0xd1, 0xd9, 0x29, 0xea, 0x7f, 0x15, 0x9d,
+       0x3d, 0x45, 0x5c, 0x6e, 0x30, 0x37, 0xd0, 0xb1, 0x84, 0xe8, 0xa7, 0x23,
+       0x5d, 0x63, 0xe9, 0x8e, 0x74, 0x45, 0xba, 0xd7, 0x1f, 0xb2, 0xee, 0xbe,
+       0x18, 0x5d, 0xd7, 0x97, 0x04, 0xa6, 0x16, 0x0d, 0x22, 0x27, 0x98, 0x8f,
+       0xdb, 0x03, 0x11, 0xba, 0x58, 0x17, 0x21, 0xdf, 0x9c, 0x0d, 0x83, 0x42,
+       0x53, 0x86, 0xa6, 0xab, 0xb9, 0x83, 0xe3, 0x5d, 0xc2, 0x6d, 0x61, 0x4d,
+       0xea, 0xdb, 0x64, 0xd4, 0xb7, 0xc0, 0x2f, 0x15, 0xd8, 0xdf, 0x37, 0xe5,
+       0x97, 0x79, 0x33, 0xe1, 0xd7, 0xe1, 0x08, 0x3e, 0xb5, 0xd8, 0x97, 0x05,
+       0x74, 0xff, 0xbe, 0x80, 0xd9, 0x2f, 0x16, 0x23, 0x7d, 0xae, 0x2d, 0x93,
+       0xe5, 0x4f, 0x77, 0xf8, 0xf2, 0x50, 0xee, 0xc0, 0xef, 0xe5, 0xd4, 0x83,
+       0x8f, 0xd9, 0x08, 0xbf, 0x1c, 0x0e, 0xee, 0x3d, 0x51, 0x0d, 0xf5, 0xaf,
+       0x7a, 0xb0, 0xbf, 0x3c, 0x88, 0xe5, 0xb3, 0x2a, 0x12, 0x44, 0x7b, 0xcc,
+       0xa7, 0xb0, 0x48, 0xfd, 0xeb, 0xf7, 0x3d, 0x79, 0xe2, 0x5e, 0x9a, 0xc7,
+       0x36, 0xae, 0x0f, 0x02, 0xbd, 0x9a, 0x7f, 0x7c, 0x14, 0x5c, 0x02, 0xb0,
+       0x33, 0x0a, 0x2e, 0x8b, 0x81, 0x77, 0xf0, 0xfa, 0x2e, 0xad, 0x97, 0xb9,
+       0xa9, 0x9d, 0x10, 0x5f, 0xaf, 0xd0, 0xbe, 0xe2, 0xe5, 0xfc, 0xe3, 0x8f,
+       0xb2, 0x47, 0x80, 0x92, 0xb3, 0x13, 0xd1, 0x9e, 0x3c, 0xa0, 0xb8, 0xef,
+       0x01, 0xfa, 0x2f, 0xad, 0xf8, 0xc4, 0x82, 0xf4, 0x8a, 0xcc, 0xff, 0x00,
+       0xcd, 0x7f, 0xfd, 0x41, 0x45, 0xc0, 0x5d, 0x27, 0x70, 0xbe, 0x4b, 0x0f,
+       0x70, 0xb8, 0x79, 0xdf, 0xc1, 0x8e, 0xa0, 0x26, 0xda, 0x03, 0x3c, 0xaf,
+       0x13, 0x68, 0x36, 0x77, 0x2a, 0x3e, 0x15, 0xda, 0x5d, 0x57, 0xa6, 0x84,
+       0x46, 0xe6, 0x0e, 0xc4, 0x73, 0x73, 0x91, 0x51, 0xdf, 0xe1, 0x8f, 0x66,
+       0xfc, 0x9e, 0x59, 0x52, 0xbe, 0xde, 0xf7, 0xb8, 0xbe, 0xe9, 0xfb, 0x91,
+       0xf4, 0x7d, 0xd8, 0xfa, 0x35, 0xfa, 0xbf, 0xae, 0x82, 0xf9, 0x42, 0x8e,
+       0x81, 0xf5, 0x1e, 0x90, 0xeb, 0xeb, 0x3c, 0xc0, 0xb2, 0x7d, 0xc0, 0xe5,
+       0x22, 0x98, 0x5f, 0xa8, 0x70, 0x60, 0xfd, 0xed, 0xa2, 0xdd, 0x1e, 0x93,
+       0x49, 0xe0, 0xeb, 0xb5, 0x0e, 0xc4, 0x5f, 0x8f, 0x45, 0xe2, 0xb3, 0xa7,
+       0xc3, 0x57, 0x01, 0xf4, 0x67, 0x1c, 0x7e, 0x74, 0x5f, 0xcf, 0xe2, 0x60,
+       0x21, 0x1f, 0xbe, 0x2f, 0x66, 0xfe, 0x17, 0x1b, 0x7f, 0x5b, 0xff, 0xba,
+       0x8f, 0xcc, 0x5f, 0x37, 0x7e, 0x1f, 0xbe, 0x18, 0xfe, 0xb6, 0x0e, 0xc0,
+       0x9f, 0xe0, 0x9f, 0x5a, 0x23, 0x3f, 0x25, 0x68, 0xfe, 0xe3, 0x67, 0xa1,
+       0x9d, 0x84, 0x14, 0xc5, 0x8d, 0x76, 0xf1, 0x7a, 0xbf, 0xfd, 0x5e, 0xb4,
+       0xff, 0x23, 0xfc, 0xf1, 0x67, 0xe2, 0x8f, 0x1e, 0x3b, 0xeb, 0xe7, 0x67,
+       0x23, 0xff, 0xbf, 0xb9, 0x18, 0xf9, 0x7f, 0x3d, 0x93, 0xf5, 0xdf, 0xea,
+       0xc0, 0xf5, 0xe3, 0x37, 0xf5, 0xd7, 0xe7, 0xeb, 0x41, 0xf2, 0x17, 0x7c,
+       0x5f, 0x00, 0xfc, 0x84, 0x26, 0x32, 0x7e, 0xff, 0xdc, 0xbe, 0xbf, 0x74,
+       0x04, 0x1d, 0x44, 0x1f, 0x2a, 0x27, 0x38, 0xef, 0x22, 0xeb, 0xa1, 0x33,
+       0x06, 0xae, 0x88, 0x59, 0x3f, 0x82, 0xff, 0x69, 0xfd, 0xa2, 0x9c, 0x07,
+       0xfc, 0x8c, 0x1e, 0x44, 0xce, 0xbc, 0x29, 0xf0, 0xfb, 0xb1, 0xc2, 0x16,
+       0xa3, 0x9c, 0xec, 0xa9, 0xe2, 0x76, 0x62, 0xcf, 0x48, 0xfe, 0x3c, 0x5f,
+       0xc4, 0xed, 0xc2, 0xf7, 0x04, 0x1e, 0x4f, 0x8b, 0xfa, 0x3d, 0x71, 0x51,
+       0x78, 0xc8, 0x8a, 0xd0, 0x19, 0x7e, 0xc2, 0xe8, 0x87, 0x44, 0xcd, 0x9b,
+       0xf0, 0xb4, 0x24, 0x45, 0xce, 0xfb, 0xcb, 0xc5, 0x73, 0x61, 0xde, 0x3d,
+       0x49, 0xbc, 0xfc, 0xf3, 0xa2, 0xff, 0xee, 0x08, 0x66, 0x45, 0xe0, 0xd8,
+       0xf6, 0xce, 0x15, 0x7d, 0x49, 0x7c, 0x13, 0x69, 0xff, 0xfc, 0x09, 0xc4,
+       0xeb, 0x12, 0x81, 0xb7, 0xf3, 0x45, 0x5f, 0x9c, 0x10, 0x7c, 0xa5, 0xe0,
+       0xba, 0xac, 0x23, 0x06, 0x01, 0xbe, 0x38, 0xa0, 0x04, 0x55, 0xf4, 0x13,
+       0x90, 0x2f, 0x06, 0x99, 0xf7, 0xf1, 0x81, 0x7c, 0x15, 0x8c, 0xf9, 0xde,
+       0x67, 0xbe, 0xc8, 0xf7, 0xbf, 0x1f, 0xb8, 0x2e, 0x7d, 0x31, 0xdf, 0x33,
+       0x73, 0xc9, 0xd7, 0xf9, 0x5e, 0xd0, 0x6d, 0x6e, 0x0c, 0x5d, 0xe7, 0xc4,
+       0xd0, 0xb5, 0x3a, 0x06, 0xae, 0x91, 0x70, 0xc8, 0x20, 0xff, 0xa4, 0x5c,
+       0x5c, 0xd9, 0xf5, 0x40, 0x5b, 0x1a, 0xcc, 0xe3, 0x96, 0x3d, 0x0a, 0xaa,
+       0x99, 0x28, 0x7e, 0x76, 0x2c, 0xc1, 0xf5, 0x79, 0x8b, 0x5b, 0xf2, 0xaf,
+       0xf3, 0x0d, 0xb4, 0xbb, 0x22, 0xfc, 0xec, 0x22, 0x78, 0x61, 0xa7, 0x94,
+       0x87, 0x09, 0xdb, 0x51, 0x1e, 0x2e, 0x40, 0x79, 0x58, 0x1e, 0x81, 0x17,
+       0xa1, 0xbc, 0x20, 0xd8, 0xbd, 0xc4, 0x37, 0x31, 0x5a, 0x5f, 0x24, 0x52,
+       0xf9, 0x75, 0xed, 0xb2, 0x7e, 0x12, 0xc1, 0x4b, 0x5b, 0x65, 0x7b, 0xc9,
+       0xdb, 0x7d, 0x5a, 0x84, 0x8e, 0x2c, 0x98, 0xb2, 0x04, 0xfb, 0x5b, 0x52,
+       0x22, 0xf4, 0x45, 0x30, 0xf5, 0x0d, 0xac, 0xbf, 0xf6, 0x20, 0xff, 0x7e,
+       0xe2, 0xfe, 0xb4, 0x37, 0x2e, 0xba, 0x1e, 0xb6, 0xc5, 0xe0, 0x65, 0x47,
+       0x0c, 0x1c, 0x8c, 0xa9, 0xff, 0xd0, 0x57, 0xe8, 0x97, 0xd6, 0x98, 0xef,
+       0xef, 0x8a, 0x29, 0xbf, 0x37, 0x06, 0xee, 0x88, 0x81, 0xdb, 0x8d, 0xdf,
+       0xaf, 0x58, 0xa5, 0xd0, 0x3a, 0x5c, 0x01, 0xfc, 0x80, 0x84, 0xf8, 0xaa,
+       0x75, 0x39, 0xc3, 0xdb, 0x6f, 0xa7, 0xf6, 0xeb, 0x53, 0xc5, 0x41, 0x76,
+       0x9b, 0x61, 0x5d, 0x5d, 0xd5, 0xc2, 0xe1, 0x2b, 0xf6, 0x8f, 0x5a, 0xd2,
+       0xee, 0x88, 0x82, 0xbd, 0xa3, 0x97, 0x04, 0x1d, 0x91, 0x75, 0x61, 0x66,
+       0xfc, 0xc7, 0x9a, 0xc2, 0x68, 0x5d, 0x98, 0x87, 0x90, 0x97, 0x93, 0xbd,
+       0xb1, 0xeb, 0x42, 0xcc, 0xa7, 0x20, 0x56, 0xdf, 0xf2, 0xf2, 0xbf, 0xe2,
+       0xaf, 0x19, 0x68, 0x07, 0x33, 0x83, 0x5d, 0x70, 0x4c, 0x35, 0xc2, 0x47,
+       0x54, 0x39, 0xee, 0xe2, 0x37, 0x6e, 0x2b, 0xc4, 0x97, 0x12, 0xf6, 0x2e,
+       0xc1, 0xf8, 0xca, 0x55, 0x3f, 0x36, 0xce, 0x0b, 0xfc, 0x55, 0x01, 0x7b,
+       0x96, 0x54, 0x57, 0x44, 0xd9, 0x25, 0xc1, 0x89, 0x4b, 0x70, 0xfd, 0xcb,
+       0x79, 0xca, 0xfa, 0xb3, 0xbf, 0xb8, 0xa0, 0x62, 0x7f, 0xcb, 0xbd, 0x13,
+       0x97, 0x3c, 0x06, 0xe5, 0x35, 0x55, 0xe1, 0xd1, 0x0d, 0x30, 0xce, 0x9a,
+       0x24, 0xfe, 0x04, 0xbd, 0xa6, 0xa2, 0xde, 0xac, 0x17, 0xf1, 0x98, 0xd9,
+       0xcf, 0xa9, 0x7e, 0xd4, 0x6b, 0x35, 0x71, 0xe1, 0xd1, 0x8d, 0x85, 0x51,
+       0xf3, 0x64, 0x9d, 0xf9, 0x38, 0xcf, 0x23, 0x77, 0xaa, 0x44, 0x9f, 0x60,
+       0x0b, 0xd0, 0x07, 0xf0, 0xb4, 0x92, 0x81, 0x43, 0x00, 0xae, 0xd9, 0x91,
+       0x84, 0x84, 0x8d, 0x4f, 0x40, 0xfd, 0x63, 0x77, 0xaa, 0x1b, 0x51, 0x8f,
+       0xbe, 0xb5, 0x31, 0x39, 0x0d, 0xfd, 0x9b, 0x83, 0x5e, 0xee, 0x2f, 0x1c,
+       0x4b, 0x18, 0x91, 0x76, 0x13, 0xc0, 0x47, 0xe2, 0x97, 0x5b, 0x74, 0xa8,
+       0x77, 0x64, 0xcb, 0x2c, 0x7a, 0x1e, 0x55, 0x7d, 0x9b, 0xfb, 0x60, 0xad,
+       0x7d, 0x6f, 0xff, 0xf4, 0x25, 0x8e, 0xb1, 0x58, 0x9e, 0x40, 0xf8, 0xb9,
+       0xc3, 0x5b, 0xbe, 0xa4, 0x19, 0xf8, 0xfa, 0x2e, 0xaf, 0x4e, 0xf8, 0x0c,
+       0x24, 0xb9, 0xd3, 0xba, 0xd0, 0x7e, 0xbe, 0xc7, 0xcc, 0x1e, 0xd7, 0x69,
+       0xfe, 0x3b, 0x89, 0x6f, 0xee, 0xb3, 0x16, 0xa1, 0xff, 0xbc, 0xa2, 0x79,
+       0x5c, 0x1a, 0xda, 0x93, 0x2b, 0x7f, 0xb8, 0x60, 0x76, 0x06, 0xd4, 0x5b,
+       0xd9, 0x66, 0xf6, 0x28, 0x54, 0x8f, 0x4d, 0xc0, 0x71, 0x07, 0xee, 0x99,
+       0x65, 0xc1, 0xf2, 0x55, 0xad, 0xe2, 0x19, 0xbc, 0x9c, 0x9e, 0x87, 0xbf,
+       0x7c, 0xb4, 0xc5, 0x05, 0xf5, 0xfb, 0x1e, 0x51, 0x3c, 0xbb, 0xa1, 0xfe,
+       0xb4, 0xcf, 0x3a, 0x5f, 0x9a, 0x00, 0xf0, 0x9a, 0xf6, 0x51, 0x1e, 0x24,
+       0xcd, 0xa1, 0x73, 0x26, 0xe6, 0x86, 0x7e, 0xde, 0xe9, 0x18, 0x13, 0x52,
+       0x81, 0x1f, 0xdf, 0xb5, 0x37, 0xbc, 0x30, 0x9f, 0xd7, 0x67, 0x58, 0x7f,
+       0xcd, 0x79, 0xfd, 0x95, 0xf9, 0x25, 0x58, 0x5f, 0x75, 0x6f, 0x82, 0xfa,
+       0x27, 0xe1, 0x3d, 0xda, 0xc3, 0x27, 0xef, 0x56, 0x77, 0x2b, 0x38, 0x2e,
+       0x97, 0x33, 0x4e, 0x81, 0x29, 0x9d, 0xfc, 0x42, 0x7f, 0x05, 0xed, 0x5a,
+       0x28, 0x77, 0x6f, 0x82, 0xf7, 0x27, 0xdb, 0x6e, 0x4e, 0x43, 0x3b, 0xeb,
+       0xa4, 0xa2, 0xbb, 0x14, 0x98, 0xff, 0xf6, 0xfd, 0x73, 0x97, 0xa4, 0x03,
+       0xbf, 0xac, 0xe9, 0xb0, 0x0a, 0x7a, 0xce, 0xcd, 0x58, 0x01, 0xf3, 0x5f,
+       0x61, 0xea, 0xe7, 0x17, 0xd2, 0x1f, 0xab, 0x13, 0x39, 0xbc, 0xdd, 0x3b,
+       0x77, 0xc9, 0xe3, 0x30, 0xfe, 0x93, 0xdb, 0xc7, 0xb8, 0x10, 0xcf, 0x89,
+       0xc5, 0xbe, 0x87, 0xbd, 0x80, 0xe7, 0xb7, 0x8a, 0x7d, 0x3f, 0xf1, 0xa6,
+       0xe2, 0x38, 0xb9, 0x9e, 0x3a, 0xfc, 0xa5, 0xba, 0x1c, 0xed, 0xf1, 0xdf,
+       0x9e, 0x5e, 0x99, 0x86, 0xfc, 0xf4, 0xb8, 0x58, 0x3f, 0x87, 0xce, 0xad,
+       0x4c, 0x5b, 0x19, 0x65, 0xef, 0xac, 0xfe, 0x58, 0x23, 0xba, 0x1f, 0xb6,
+       0xe8, 0xb7, 0xe1, 0x38, 0x0f, 0xc7, 0x65, 0x2b, 0xe8, 0x2f, 0x03, 0xdd,
+       0x93, 0x17, 0xc0, 0xfa, 0x5d, 0x25, 0xfc, 0x0f, 0xe0, 0xdf, 0x8d, 0xcf,
+       0x0c, 0x62, 0xf7, 0x04, 0xbd, 0x2a, 0xb5, 0x7b, 0x64, 0x6b, 0x6a, 0x85,
+       0x6e, 0xe0, 0xe3, 0xeb, 0xdf, 0x40, 0xbe, 0x24, 0xbf, 0x01, 0xe0, 0x5f,
+       0xee, 0xbf, 0x6e, 0x3b, 0xea, 0xb5, 0xf7, 0xac, 0x1b, 0xd9, 0xbb, 0xb8,
+       0xf8, 0xee, 0x82, 0x82, 0x29, 0xf0, 0x3c, 0x66, 0xa7, 0xf8, 0x95, 0x79,
+       0xaf, 0x3d, 0x64, 0xcf, 0xc5, 0xf8, 0xa7, 0x6f, 0x36, 0xca, 0x3d, 0x96,
+       0xde, 0x99, 0xbf, 0xd0, 0x19, 0xb5, 0xee, 0x44, 0xfd, 0xbf, 0x04, 0x9d,
+       0x54, 0xff, 0x2f, 0x50, 0x1f, 0xfd, 0xb7, 0xbf, 0x04, 0xff, 0xec, 0x64,
+       0x8e, 0x81, 0x76, 0xfc, 0x1a, 0x97, 0x33, 0x88, 0xc6, 0xc4, 0xfb, 0x4e,
+       0xa7, 0x86, 0x74, 0x78, 0x4b, 0x6b, 0x3a, 0x79, 0x07, 0x7c, 0xb7, 0xfa,
+       0x11, 0x33, 0xc9, 0xfd, 0xd5, 0x8f, 0xa4, 0xde, 0xd5, 0x87, 0xf2, 0x06,
+       0xf8, 0x05, 0xe3, 0x63, 0xb1, 0xf3, 0x52, 0x8b, 0xcd, 0x34, 0xaf, 0x21,
+       0xd7, 0x61, 0xb0, 0xd6, 0xb8, 0x0e, 0x59, 0x2d, 0xc9, 0xeb, 0xa1, 0xd6,
+       0x61, 0xcf, 0xfe, 0x35, 0x17, 0x5d, 0x87, 0x6b, 0x84, 0x9f, 0x32, 0xfb,
+       0x11, 0xb3, 0x1f, 0xd7, 0xd1, 0x9a, 0x49, 0x4e, 0x8d, 0x81, 0xfe, 0xa8,
+       0x7a, 0xe4, 0xf9, 0xc7, 0x91, 0xdf, 0xd7, 0x6c, 0xb0, 0x7b, 0xad, 0x30,
+       0xf0, 0x35, 0x8f, 0x58, 0x89, 0x5e, 0xbd, 0x4e, 0x67, 0xd0, 0x0d, 0xe5,
+       0x01, 0x97, 0x53, 0x4b, 0x84, 0xe7, 0x5b, 0x82, 0xbe, 0xac, 0x98, 0xaf,
+       0x9b, 0x99, 0x2a, 0xd3, 0x6c, 0x5e, 0x7a, 0xb6, 0x62, 0x9c, 0xf4, 0x0c,
+       0x8c, 0x27, 0x19, 0xe0, 0x0f, 0x36, 0x3e, 0xf8, 0xa3, 0xc9, 0x50, 0xed,
+       0x43, 0x16, 0xba, 0x76, 0x32, 0xe0, 0xef, 0x0c, 0x12, 0x0c, 0xf0, 0x72,
+       0xe6, 0x80, 0x4a, 0xf1, 0x43, 0xa6, 0xf9, 0xb4, 0x79, 0x20, 0x1f, 0x6b,
+       0x19, 0x97, 0x0b, 0x75, 0x2f, 0x3e, 0x63, 0xa9, 0xc4, 0xd9, 0x35, 0xac,
+       0x99, 0x8b, 0x7e, 0xdd, 0xcd, 0x21, 0xf3, 0x3b, 0xbd, 0xc2, 0x67, 0xbb,
+       0x20, 0xa6, 0x89, 0xf2, 0xb4, 0x9e, 0xbf, 0x02, 0xbd, 0x6a, 0x2c, 0xaf,
+       0x67, 0xf7, 0x7e, 0xaa, 0x4e, 0x20, 0x36, 0xb6, 0xe0, 0x7a, 0xac, 0xeb,
+       0x8c, 0x29, 0x6f, 0xb8, 0xfc, 0x7d, 0x8c, 0xbf, 0xd4, 0x33, 0xed, 0x9d,
+       0x5e, 0x19, 0xaf, 0x85, 0x71, 0x7c, 0xee, 0x75, 0xa6, 0x9c, 0x8c, 0x47,
+       0x71, 0xc8, 0xbc, 0x80, 0x21, 0x76, 0xa6, 0xc1, 0x9c, 0xcf, 0x60, 0x8a,
+       0x6b, 0x1c, 0xb0, 0xae, 0x60, 0xbe, 0x33, 0x77, 0x28, 0x34, 0xee, 0x35,
+       0x1b, 0xd5, 0x90, 0x15, 0xea, 0xcf, 0x4c, 0xe6, 0x71, 0xdf, 0xf7, 0x9a,
+       0x80, 0xfe, 0x63, 0x68, 0xde, 0x41, 0x37, 0xc0, 0x6b, 0x1e, 0xe2, 0x7a,
+       0x66, 0x0d, 0x53, 0x42, 0x36, 0xf8, 0xf5, 0xf2, 0x1d, 0x1b, 0x34, 0x5c,
+       0x0f, 0xeb, 0x85, 0x7c, 0x59, 0xa1, 0x30, 0x3f, 0xf2, 0xf7, 0xbb, 0x76,
+       0x4f, 0x0e, 0xfa, 0xeb, 0xab, 0x1f, 0xb1, 0x13, 0x7e, 0xd7, 0xec, 0xbc,
+       0xf9, 0x8f, 0xdb, 0xe1, 0xbb, 0xde, 0xe6, 0x79, 0x29, 0xd1, 0xfe, 0xb1,
+       0x43, 0xf0, 0x05, 0xb4, 0xcf, 0x6c, 0x49, 0x91, 0x76, 0xde, 0x6f, 0xfe,
+       0x5e, 0x0e, 0xf2, 0xff, 0xcc, 0x9f, 0x82, 0x9f, 0x0b, 0xf3, 0x5d, 0x93,
+       0xc8, 0x7e, 0xb1, 0x24, 0x17, 0xe9, 0x95, 0x91, 0xa3, 0x3b, 0x22, 0xf5,
+       0xd6, 0x6c, 0xba, 0x33, 0x9f, 0xd7, 0x03, 0x3f, 0x19, 0xe6, 0xbd, 0xe2,
+       0x6e, 0x95, 0xe6, 0xc1, 0x9e, 0xb5, 0x92, 0xde, 0x83, 0xb5, 0x9e, 0x4e,
+       0x72, 0x59, 0xe0, 0x73, 0x55, 0xeb, 0x8b, 0x16, 0x4b, 0x21, 0xca, 0xe9,
+       0x7b, 0x7b, 0x54, 0xa8, 0xff, 0x0e, 0xc0, 0xaa, 0x83, 0xf0, 0x15, 0x14,
+       0x78, 0xb4, 0x20, 0xbe, 0x96, 0xe3, 0xb7, 0x19, 0xfc, 0x9b, 0xf4, 0x52,
+       0x61, 0x77, 0xeb, 0x24, 0x47, 0x02, 0x38, 0xbf, 0x1a, 0x93, 0xb2, 0x7c,
+       0x21, 0xc9, 0xf5, 0x3e, 0x0b, 0xae, 0xeb, 0xf2, 0x62, 0x85, 0xc6, 0x33,
+       0xb1, 0x98, 0xdb, 0xb3, 0x2b, 0x72, 0x3c, 0x37, 0x50, 0x1c, 0xf9, 0x7e,
+       0xab, 0x07, 0xe5, 0x14, 0xfe, 0xa8, 0x72, 0x1c, 0xe0, 0x57, 0xd5, 0x99,
+       0x7a, 0x56, 0x63, 0x3c, 0x97, 0xfd, 0xd2, 0x4a, 0xf1, 0x91, 0xfa, 0x56,
+       0xbb, 0xcf, 0xee, 0x22, 0xbf, 0xc3, 0xb7, 0x1f, 0xc7, 0xa7, 0x31, 0xcd,
+       0x02, 0xf8, 0x58, 0xa7, 0x73, 0x79, 0x51, 0x2e, 0xf8, 0xb0, 0x5e, 0x5f,
+       0x70, 0x39, 0xf2, 0x0d, 0x94, 0x9f, 0xd0, 0x70, 0x7f, 0xc5, 0xc9, 0xe5,
+       0x62, 0x5d, 0x22, 0xe0, 0x9d, 0xeb, 0x63, 0x9f, 0x09, 0xfa, 0xf9, 0x04,
+       0x7f, 0x1b, 0xc5, 0xdb, 0xcd, 0x98, 0x10, 0xd5, 0xbf, 0x22, 0xde, 0x43,
+       0x3b, 0xba, 0x2b, 0xd2, 0x6e, 0xb7, 0x89, 0xb5, 0x63, 0x9c, 0x05, 0xeb,
+       0x8f, 0x9d, 0x80, 0x78, 0x4c, 0xbe, 0x76, 0x31, 0x8e, 0xef, 0xe7, 0x2a,
+       0xad, 0x67, 0x98, 0xfc, 0xfd, 0x65, 0x68, 0xe7, 0xfd, 0x5c, 0x2d, 0x46,
+       0xff, 0x76, 0xc5, 0xdd, 0xc7, 0x66, 0x77, 0x20, 0xbc, 0xaf, 0xc8, 0x8d,
+       0x4d, 0xae, 0xf8, 0xc5, 0x1f, 0x48, 0x6f, 0xdc, 0x22, 0xe8, 0xdf, 0x8b,
+       0xf6, 0x3e, 0xea, 0x11, 0x80, 0xf7, 0xc1, 0x73, 0x51, 0x31, 0xd7, 0xfb,
+       0x01, 0x95, 0xc7, 0x7d, 0x16, 0x09, 0x7c, 0x49, 0x3e, 0x90, 0xe5, 0x75,
+       0x77, 0x9b, 0x79, 0xfc, 0xbd, 0xcd, 0x4a, 0x76, 0x4c, 0x5d, 0xf3, 0x9f,
+       0xa8, 0xdd, 0x3a, 0x67, 0x4f, 0x1a, 0xca, 0xdf, 0xba, 0x67, 0xcd, 0xa5,
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+       0x6a, 0xa5, 0x39, 0xc1, 0xad, 0xc0, 0xab, 0x75, 0xc1, 0x79, 0x16, 0x84,
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+       0x7e, 0xab, 0xa4, 0x8e, 0xc3, 0x13, 0x93, 0x26, 0x99, 0x01, 0x6e, 0x6e,
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+       0x66, 0x39, 0x68, 0xdf, 0xbd, 0x5b, 0x22, 0xc7, 0x3f, 0xf8, 0x33, 0x6f,
+       0x92, 0xef, 0xed, 0x92, 0x41, 0xde, 0xaf, 0x64, 0xac, 0x0d, 0xe3, 0x2a,
+       0x2b, 0x83, 0xbf, 0x3b, 0xa1, 0x70, 0x3f, 0xcc, 0x6f, 0x03, 0x7a, 0x5d,
+       0x2d, 0xf8, 0x6a, 0xa5, 0xcd, 0x11, 0x26, 0x7f, 0xbe, 0xdd, 0x7c, 0xba,
+       0x9f, 0xde, 0xc8, 0x47, 0x9e, 0x04, 0x0d, 0xe9, 0x3a, 0x5f, 0xf0, 0xd1,
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+       0x6b, 0xc8, 0x83, 0xa5, 0x77, 0x75, 0x4f, 0x8f, 0x4b, 0x87, 0x41, 0x9f,
+       0x9e, 0x1f, 0xce, 0xc7, 0xf5, 0xfe, 0x69, 0x4e, 0x20, 0x6e, 0x12, 0xfa,
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+       0x70, 0xea, 0x75, 0x18, 0x1f, 0x79, 0x51, 0xa5, 0x78, 0xde, 0x50, 0xfd,
+       0xd5, 0x8b, 0xfc, 0xf1, 0x21, 0xcb, 0x0f, 0x7d, 0x90, 0x85, 0xf6, 0xf6,
+       0x9c, 0x2f, 0xd5, 0x00, 0xe2, 0xe9, 0x15, 0xb3, 0x73, 0x31, 0xc6, 0x0b,
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+       0x0c, 0xec, 0xc2, 0xf9, 0x2e, 0x01, 0x43, 0x1c, 0xe1, 0x40, 0xb9, 0x35,
+       0x67, 0xb0, 0x79, 0xc5, 0x8e, 0x6b, 0xaf, 0x18, 0xd7, 0x5e, 0x31, 0x1e,
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+       0x8c, 0x8a, 0xe0, 0x5f, 0xfa, 0xed, 0x9b, 0x2b, 0x45, 0x5e, 0xc9, 0x06,
+       0x85, 0xc7, 0xe5, 0xa4, 0xbd, 0x26, 0xf2, 0x52, 0xa4, 0xdf, 0x51, 0x73,
+       0xbb, 0x12, 0x42, 0x7b, 0x7d, 0x19, 0xf8, 0x3b, 0xb8, 0xbf, 0xf4, 0xa6,
+       0xb0, 0x3f, 0xdf, 0xb4, 0x73, 0xfd, 0x7c, 0xa6, 0xc1, 0x5c, 0x80, 0x76,
+       0x7d, 0x8d, 0x12, 0xe7, 0xc1, 0x7d, 0xb8, 0x33, 0x0d, 0xff, 0xe5, 0x40,
+       0x77, 0x1a, 0xea, 0x33, 0xdc, 0x27, 0x69, 0xc1, 0x9c, 0x03, 0x28, 0x6f,
+       0xb9, 0x43, 0xa1, 0x7c, 0xee, 0x1a, 0x68, 0xc7, 0x04, 0xed, 0xd4, 0x60,
+       0x20, 0x10, 0xbf, 0xbb, 0x4b, 0x21, 0xfe, 0xfb, 0x62, 0x7c, 0x2e, 0x8d,
+       0xaf, 0x06, 0xcc, 0x3f, 0xf2, 0xb3, 0x52, 0xfa, 0x72, 0x70, 0xbf, 0x14,
+       0xf8, 0xe5, 0x45, 0xa4, 0xc3, 0xda, 0x29, 0x6a, 0xd0, 0x02, 0xf6, 0xf0,
+       0x2b, 0xa6, 0x50, 0xbe, 0x42, 0xfb, 0xd2, 0x37, 0x59, 0x14, 0x18, 0xe7,
+       0x9a, 0x14, 0xe0, 0x93, 0x91, 0x43, 0xf3, 0xc3, 0x7a, 0x71, 0xfe, 0x40,
+       0xbe, 0x07, 0x3e, 0xfb, 0x03, 0xb6, 0xf7, 0xb7, 0x5f, 0x4f, 0x2e, 0xa0,
+       0x38, 0xfe, 0xa1, 0x29, 0x3a, 0xe2, 0xad, 0xc5, 0xc4, 0xcf, 0x23, 0x05,
+       0x7f, 0xaf, 0x7a, 0x78, 0xbe, 0x0b, 0x17, 0xd5, 0xea, 0xd4, 0xf1, 0x14,
+       0xa7, 0x64, 0x9a, 0xc7, 0x83, 0x71, 0xa6, 0x79, 0xe2, 0xfc, 0xca, 0x11,
+       0x95, 0x6d, 0xdc, 0x37, 0x88, 0x1c, 0xfd, 0xbb, 0xa0, 0xdb, 0x2b, 0xe9,
+       0xe6, 0x39, 0x21, 0x6a, 0xd7, 0xb8, 0x5f, 0xf3, 0xb1, 0xa0, 0xe3, 0xc7,
+       0xa2, 0xde, 0xbc, 0xa3, 0x2f, 0x66, 0xe3, 0xf9, 0xab, 0xf5, 0xdd, 0x66,
+       0xb2, 0x47, 0x58, 0x49, 0x6f, 0xa1, 0xdf, 0x39, 0xc8, 0x7c, 0x36, 0x6e,
+       0xfd, 0x76, 0x5e, 0x14, 0x7f, 0xd7, 0x77, 0xbd, 0xcd, 0xf3, 0x35, 0x58,
+       0x6f, 0x61, 0x74, 0x7e, 0xba, 0x6b, 0x32, 0x6f, 0x57, 0xf2, 0x93, 0x6a,
+       0x71, 0x06, 0x76, 0x39, 0xa2, 0xc7, 0xd7, 0xcf, 0xdf, 0x9f, 0x11, 0x7f,
+       0x27, 0x02, 0x7f, 0x8f, 0x22, 0xfe, 0x3e, 0x89, 0xf6, 0xf6, 0x7c, 0xab,
+       0x9e, 0x70, 0x1d, 0x3c, 0x7b, 0x01, 0x45, 0x61, 0x78, 0x06, 0x7e, 0xea,
+       0xa6, 0x7c, 0x23, 0x99, 0x77, 0xb4, 0x8a, 0xf9, 0xe9, 0xb9, 0x06, 0xd8,
+       0x01, 0xf9, 0xd9, 0x1f, 0x7c, 0xc0, 0x82, 0xf8, 0x5f, 0xcb, 0x3a, 0xe9,
+       0xfd, 0xfa, 0xb2, 0x1b, 0x73, 0x10, 0xae, 0x67, 0x7d, 0xd5, 0xe9, 0xe8,
+       0x4f, 0xb4, 0x37, 0x3f, 0x9f, 0x0e, 0xa3, 0x5c, 0xb4, 0xed, 0x81, 0x59,
+       0x18, 0x9f, 0x5d, 0x18, 0x5a, 0xf1, 0x3c, 0x3e, 0x17, 0x3c, 0xa6, 0x9c,
+       0x44, 0xff, 0x15, 0xd6, 0x87, 0x79, 0x32, 0xc6, 0x4f, 0x94, 0x86, 0xb6,
+       0xe1, 0xd0, 0xdf, 0xd2, 0xbd, 0x95, 0x6d, 0x99, 0xf0, 0x7e, 0xbe, 0xca,
+       0xe9, 0xc1, 0x5e, 0xe2, 0xf4, 0x00, 0xbe, 0xf1, 0xa9, 0x49, 0x03, 0xe7,
+       0x09, 0xeb, 0xc1, 0x39, 0x99, 0xe6, 0xe1, 0xa3, 0x79, 0xa8, 0xae, 0x39,
+       0x86, 0xf5, 0x50, 0xb3, 0x89, 0xf9, 0x94, 0x94, 0x48, 0xfe, 0x7c, 0xff,
+       0xfa, 0x28, 0xbb, 0xe5, 0xaf, 0x99, 0xe8, 0x0f, 0x69, 0x7d, 0xb4, 0xff,
+       0x5e, 0x7f, 0xc8, 0x9a, 0x84, 0x74, 0x5e, 0xcb, 0xb8, 0xfe, 0x8e, 0xc4,
+       0x3f, 0xa4, 0xde, 0x66, 0xc4, 0xe7, 0xb7, 0xb0, 0x38, 0x0f, 0xd6, 0xfb,
+       0x50, 0xf0, 0xf5, 0x87, 0xd9, 0x8c, 0xf8, 0xfa, 0x43, 0x05, 0x1c, 0x3c,
+       0x6f, 0xc4, 0x9e, 0x64, 0x39, 0x81, 0x74, 0xef, 0xa8, 0x88, 0xfe, 0xfd,
+       0xd0, 0x14, 0x2a, 0x75, 0x8d, 0x22, 0xfd, 0x9c, 0x87, 0xf3, 0x7d, 0x21,
+       0x7d, 0x91, 0x8e, 0x71, 0xb3, 0x5b, 0x52, 0x6c, 0x1e, 0x15, 0xcb, 0x13,
+       0x43, 0x39, 0x7c, 0x1f, 0xb5, 0x5f, 0xce, 0xb3, 0x0b, 0xf1, 0x91, 0xb8,
+       0xd7, 0xfd, 0x66, 0x1e, 0x87, 0x8a, 0x1d, 0x97, 0x52, 0xf6, 0xc2, 0x3f,
+       0xd0, 0x7e, 0xb0, 0x5a, 0x58, 0x10, 0xf7, 0x37, 0x60, 0x7d, 0xb3, 0x52,
+       0x5c, 0xd7, 0xc3, 0x2d, 0xb4, 0xae, 0x5a, 0x10, 0xb5, 0x18, 0x3f, 0xab,
+       0xf2, 0xeb, 0x83, 0xb5, 0xdf, 0x2a, 0xda, 0xed, 0xfe, 0x82, 0xfb, 0xc1,
+       0x41, 0x98, 0x0f, 0x9e, 0x97, 0x1c, 0xd0, 0x8f, 0x5b, 0xf4, 0x13, 0xc7,
+       0xfb, 0x91, 0x7a, 0x04, 0xfb, 0x23, 0x39, 0x92, 0xc6, 0x0c, 0xfd, 0xcd,
+       0xc2, 0x24, 0x17, 0xa0, 0xcb, 0x2b, 0x4e, 0x1f, 0x8d, 0xbf, 0xd9, 0x94,
+       0x48, 0x72, 0xe7, 0xe3, 0x11, 0x81, 0x6a, 0xa4, 0x97, 0x8c, 0xff, 0x48,
+       0xff, 0xb0, 0x3b, 0xf7, 0xfd, 0x3c, 0xf2, 0xe3, 0xcf, 0xb7, 0x64, 0xa1,
+       0x9d, 0x0e, 0xfc, 0xcb, 0xf3, 0x12, 0xa7, 0x73, 0xf9, 0xf4, 0x8a, 0x59,
+       0x0f, 0x22, 0xfc, 0x4a, 0x65, 0x2e, 0xc5, 0xff, 0xa5, 0xdc, 0xbd, 0xba,
+       0x8c, 0xc7, 0xcb, 0xae, 0x96, 0xf1, 0xb1, 0x8a, 0x98, 0xf8, 0x58, 0x4c,
+       0x5c, 0x86, 0x55, 0x0c, 0x1e, 0x2f, 0x63, 0xcc, 0x63, 0xc6, 0x7e, 0xc7,
+       0xb2, 0x37, 0x25, 0x7e, 0x28, 0x1e, 0x73, 0xb4, 0x42, 0x23, 0xba, 0x07,
+       0x81, 0xee, 0x18, 0x6f, 0x3e, 0x2a, 0xfc, 0xd4, 0xca, 0x78, 0xee, 0x9f,
+       0x77, 0x4e, 0x4e, 0x26, 0x7e, 0x4a, 0xba, 0x22, 0x6f, 0xd0, 0x7d, 0x15,
+       0xf9, 0xbc, 0x47, 0xc4, 0x57, 0xef, 0x05, 0x3b, 0x88, 0x45, 0xc5, 0xd5,
+       0xef, 0x29, 0x69, 0xb4, 0x61, 0x9e, 0xc1, 0x96, 0x42, 0x85, 0xf6, 0xbb,
+       0xee, 0xab, 0x8a, 0xab, 0x8d, 0xce, 0x73, 0xdf, 0x3b, 0xcd, 0xcc, 0xf7,
+       0x53, 0xa7, 0x57, 0xee, 0x44, 0xbc, 0x15, 0x3a, 0x42, 0x55, 0xa4, 0xae,
+       0x7d, 0x9a, 0x8e, 0xf3, 0x50, 0xc4, 0xbc, 0xc6, 0xb9, 0x01, 0xef, 0x26,
+       0x6c, 0xda, 0x2f, 0xe2, 0xa4, 0x1e, 0x1b, 0x8f, 0x4b, 0x55, 0x93, 0xbe,
+       0x96, 0xf4, 0xbe, 0x54, 0x7d, 0xfd, 0x94, 0x16, 0xda, 0x14, 0x87, 0xf3,
+       0x4e, 0x61, 0xb4, 0xfe, 0x9c, 0x1d, 0x76, 0x92, 0xa3, 0x6a, 0xa7, 0x2f,
+       0x8c, 0x29, 0xd7, 0x5f, 0x4e, 0x5b, 0x78, 0x27, 0xd1, 0x51, 0xf3, 0x17,
+       0x60, 0x3f, 0x47, 0x4a, 0xe3, 0x98, 0x03, 0xea, 0x7f, 0x7e, 0xc4, 0x42,
+       0xfe, 0xfd, 0x21, 0xd3, 0xca, 0x9f, 0x62, 0x3e, 0x7c, 0xdf, 0x1b, 0x56,
+       0x86, 0xfb, 0x9e, 0x9d, 0xce, 0x4c, 0x0d, 0xf5, 0x45, 0xe7, 0x17, 0x97,
+       0x55, 0xd3, 0xd3, 0x39, 0x75, 0x36, 0xe3, 0x71, 0xce, 0x78, 0x13, 0x08,
+       0x88, 0x22, 0x37, 0x7b, 0xf4, 0xdf, 0x90, 0x58, 0xe2, 0xdc, 0x59, 0xa7,
+       0xc2, 0xba, 0x19, 0xc5, 0xdb, 0x7c, 0xf1, 0x26, 0xf0, 0xc1, 0x3a, 0x4d,
+       0xec, 0xec, 0x0c, 0x18, 0xd7, 0x7e, 0x87, 0xf7, 0xc1, 0x89, 0xc4, 0x72,
+       0x7e, 0x15, 0xe7, 0xd9, 0x55, 0x11, 0xb8, 0x1f, 0xd7, 0x53, 0x29, 0x6b,
+       0x20, 0xf8, 0x3e, 0x8b, 0xbf, 0x76, 0x17, 0xf4, 0x7b, 0x5f, 0x92, 0x8d,
+       0xf8, 0xc4, 0x5f, 0xe1, 0x7f, 0x80, 0x8f, 0x93, 0xb5, 0xcd, 0x85, 0xf1,
+       0x4d, 0x9f, 0xa9, 0x30, 0x3c, 0xc7, 0xdb, 0x66, 0x01, 0xb9, 0x5c, 0x88,
+       0x71, 0x92, 0x38, 0xbe, 0x27, 0xc5, 0xb8, 0x7d, 0xef, 0x3f, 0x97, 0x4f,
+       0xfd, 0xef, 0x98, 0xcc, 0xf7, 0xf9, 0x5a, 0xd3, 0x7d, 0x3d, 0x78, 0x60,
+       0x64, 0x48, 0xbc, 0xb9, 0xb5, 0xbe, 0xfe, 0xb8, 0x08, 0xf1, 0x5b, 0x16,
+       0xc5, 0xf3, 0x24, 0x1e, 0xa3, 0xe9, 0xe5, 0x2e, 0x35, 0xd0, 0x2b, 0x60,
+       0x8e, 0xa6, 0x57, 0x19, 0xd0, 0x6b, 0x7c, 0x34, 0xbd, 0x7c, 0xca, 0xd7,
+       0xa1, 0xd7, 0xed, 0x98, 0x5c, 0x36, 0x69, 0x20, 0x7f, 0x06, 0xab, 0xf4,
+       0x07, 0xaa, 0x4b, 0xb8, 0x5e, 0xc3, 0x14, 0xb9, 0x4a, 0x6b, 0x76, 0x21,
+       0xda, 0xeb, 0x47, 0xe2, 0x32, 0x0b, 0xa3, 0xf7, 0xf5, 0x24, 0x5f, 0x4a,
+       0x3e, 0x1d, 0x84, 0x3f, 0x37, 0x1c, 0x43, 0xf9, 0x90, 0xa5, 0xb9, 0x31,
+       0x7e, 0x6a, 0x9d, 0x17, 0x47, 0xfb, 0x2d, 0x92, 0x5f, 0x25, 0x9f, 0xfe,
+       0x75, 0x4a, 0x3f, 0xbf, 0x7a, 0xcb, 0xe1, 0xb9, 0xcc, 0xe1, 0x9f, 0x85,
+       0x32, 0x24, 0x96, 0x5f, 0x31, 0x1e, 0x16, 0xcd, 0x97, 0x35, 0x43, 0xf2,
+       0x2f, 0x73, 0x47, 0xaf, 0xd7, 0xf9, 0x60, 0x3f, 0x24, 0x24, 0xa1, 0xdd,
+       0x73, 0xea, 0xb1, 0xce, 0x28, 0xbe, 0xac, 0x69, 0xf8, 0x54, 0xe3, 0xf2,
+       0xe3, 0xc2, 0x8c, 0xb8, 0xd2, 0x48, 0xfc, 0x6e, 0x7e, 0x85, 0xc2, 0xde,
+       0x89, 0xa6, 0x2f, 0xfc, 0x7b, 0xa7, 0x40, 0xcc, 0x8f, 0xec, 0x1e, 0x8d,
+       0xfc, 0x2d, 0x89, 0xc7, 0x4b, 0xc5, 0xb7, 0xf9, 0x5b, 0xcd, 0x05, 0x68,
+       0xc7, 0x6d, 0xc6, 0xf3, 0x89, 0x80, 0xaf, 0x76, 0xc5, 0xe3, 0x1b, 0x86,
+       0x71, 0xad, 0x86, 0xb7, 0x6f, 0xc5, 0xf7, 0x6d, 0xe2, 0x7c, 0x70, 0xb0,
+       0xd0, 0xc2, 0xed, 0x2b, 0xb1, 0x4e, 0x64, 0x7b, 0x5f, 0x4e, 0xab, 0x7a,
+       0x07, 0xf9, 0xd6, 0x39, 0xf9, 0x74, 0xfc, 0x6a, 0xa8, 0xf7, 0x79, 0x9a,
+       0x49, 0x47, 0xe4, 0xb4, 0xe9, 0x2b, 0xff, 0x8d, 0xd6, 0xdd, 0x89, 0x78,
+       0x86, 0xdf, 0xb9, 0x92, 0x7b, 0x6a, 0x1f, 0xa5, 0x75, 0x34, 0x86, 0xe1,
+       0xfe, 0xe0, 0xe7, 0x37, 0x07, 0x46, 0xe0, 0x7e, 0xfd, 0xdd, 0x40, 0xa7,
+       0x77, 0x28, 0x99, 0x3a, 0x34, 0xcc, 0x44, 0x7b, 0x59, 0xbd, 0xc3, 0x70,
+       0x1d, 0x01, 0x72, 0xd3, 0xf9, 0x33, 0x90, 0xce, 0xdf, 0x33, 0x51, 0x1e,
+       0x22, 0xf8, 0x3b, 0x53, 0x46, 0x0a, 0xbf, 0xc3, 0x27, 0xea, 0xf7, 0x52,
+       0xfd, 0xbb, 0x2d, 0xdb, 0x6c, 0x71, 0xd8, 0x4f, 0xae, 0xcd, 0xbd, 0x3b,
+       0x8a, 0xdf, 0x67, 0x88, 0xf8, 0x3a, 0x1e, 0x23, 0xe7, 0xfb, 0x67, 0x2d,
+       0x3a, 0xda, 0x65, 0x7a, 0x19, 0xd7, 0xbf, 0x0f, 0x36, 0xed, 0x99, 0xf6,
+       0xde, 0x68, 0x1c, 0x4f, 0xe7, 0xb4, 0xf7, 0x60, 0x3c, 0xc9, 0x73, 0x43,
+       0x2c, 0x00, 0x7c, 0x1c, 0x57, 0x10, 0xd4, 0x31, 0x05, 0xc4, 0xf6, 0xe5,
+       0x4c, 0x05, 0xcf, 0x2f, 0xb0, 0xcb, 0x58, 0x27, 0xf2, 0x0d, 0xbe, 0x6f,
+       0x1e, 0x1f, 0x69, 0xdf, 0x5c, 0xc6, 0xd7, 0x99, 0x0d, 0xed, 0x15, 0xa0,
+       0x9f, 0x6d, 0x53, 0x50, 0x4f, 0x8a, 0x92, 0x7f, 0x36, 0x93, 0x12, 0x18,
+       0x2c, 0xdf, 0xe5, 0x8e, 0x29, 0x1a, 0xff, 0x6e, 0x13, 0xa3, 0x72, 0xdb,
+       0xd1, 0xed, 0x74, 0x9e, 0x3f, 0x39, 0xcf, 0xa3, 0x60, 0xde, 0xb3, 0x6d,
+       0xd3, 0x36, 0x86, 0xfb, 0x31, 0xf6, 0x30, 0x7f, 0x9f, 0x92, 0xe7, 0x53,
+       0x56, 0x45, 0xb5, 0x9b, 0x32, 0x17, 0xc6, 0x1d, 0xc5, 0x17, 0xf3, 0xf1,
+       0x24, 0x01, 0xc8, 0x1b, 0xdb, 0x6e, 0x60, 0xcc, 0x12, 0xa4, 0x43, 0x1c,
+       0xc5, 0x1f, 0x63, 0xfb, 0x9d, 0x9f, 0x5a, 0xd5, 0xad, 0xb9, 0x86, 0xe6,
+       0x93, 0x58, 0x7e, 0x63, 0x82, 0xdf, 0x24, 0xdf, 0xc8, 0x79, 0xd2, 0xc9,
+       0x94, 0xa8, 0x73, 0xf9, 0xd5, 0x23, 0xb9, 0x3d, 0xdc, 0xb6, 0xd1, 0xb2,
+       0x0b, 0xed, 0xed, 0xf2, 0xb2, 0x44, 0xc2, 0xef, 0x67, 0x29, 0x55, 0x09,
+       0xec, 0x22, 0x7a, 0x65, 0x27, 0xf0, 0x41, 0xd0, 0x8a, 0xfe, 0xb1, 0x8d,
+       0x9e, 0xbb, 0xc1, 0xbf, 0x0e, 0x8e, 0x41, 0xff, 0x38, 0x9d, 0xe0, 0x27,
+       0xc0, 0xbf, 0xc6, 0xe7, 0x1e, 0xf0, 0xaf, 0xf1, 0xf9, 0x14, 0xf8, 0xd7,
+       0x58, 0xbe, 0x17, 0xfc, 0x6b, 0x84, 0x7f, 0x01, 0xfe, 0x35, 0xc2, 0x9d,
+       0xe0, 0x5f, 0x23, 0xbc, 0x1f, 0xfc, 0x6b, 0x84, 0x0f, 0x80, 0x7f, 0x8d,
+       0xf0, 0x2f, 0xc1, 0xbf, 0xc6, 0x67, 0x17, 0xf8, 0xd7, 0xf8, 0xfc, 0x0d,
+       0xf8, 0xd7, 0x58, 0x7e, 0x10, 0xfc, 0x6b, 0x84, 0x67, 0x58, 0x81, 0x3f,
+       0x70, 0x3e, 0x05, 0xc1, 0xf4, 0x85, 0x40, 0xd7, 0xf6, 0x3b, 0x2c, 0x3e,
+       0xcc, 0x17, 0xdc, 0x20, 0xe8, 0x7a, 0xcc, 0x37, 0x32, 0xd9, 0x03, 0xf4,
+       0xb7, 0x17, 0x98, 0x28, 0xf6, 0x6d, 0x7f, 0xf9, 0x07, 0x0c, 0xe7, 0x63,
+       0x4f, 0x37, 0xd1, 0xf9, 0xaf, 0xcd, 0xe9, 0x3f, 0x60, 0x37, 0xa2, 0xdf,
+       0x5a, 0xea, 0x24, 0xbb, 0xa9, 0xed, 0xe7, 0xdc, 0x1e, 0xb1, 0x6b, 0x0f,
+       0x32, 0x94, 0x3b, 0x3b, 0x95, 0x60, 0x2d, 0xf3, 0x30, 0xb6, 0xb8, 0x6c,
+       0x6c, 0x0d, 0xee, 0xf3, 0xe5, 0xa5, 0x6f, 0xa8, 0x4a, 0x02, 0xf8, 0x86,
+       0xb2, 0x89, 0x3b, 0x6c, 0xb0, 0x3e, 0xf2, 0xf5, 0x05, 0x8b, 0x9b, 0xa3,
+       0x60, 0xdd, 0xe9, 0x5d, 0xbb, 0xcf, 0x1d, 0x81, 0x47, 0x14, 0xee, 0xd2,
+       0xc0, 0x33, 0x61, 0x37, 0x76, 0x15, 0xed, 0xc0, 0xa3, 0x3f, 0x38, 0x0e,
+       0xcc, 0x13, 0xae, 0x2b, 0x2b, 0xa9, 0x69, 0x06, 0x16, 0x0a, 0x8f, 0x64,
+       0x64, 0x57, 0xf4, 0xe5, 0x5a, 0x28, 0x3f, 0x67, 0x15, 0xd2, 0x6b, 0x34,
+       0x8e, 0x9f, 0xc7, 0x0d, 0xaf, 0x62, 0x2d, 0xe9, 0xb8, 0x6f, 0x39, 0x42,
+       0x07, 0xef, 0x47, 0xa1, 0xfa, 0x61, 0x96, 0x72, 0xe9, 0xf5, 0x37, 0x94,
+       0xe9, 0xf4, 0x3e, 0xf6, 0xbb, 0x8b, 0xd5, 0x33, 0x95, 0x5c, 0x52, 0x3d,
+       0xa6, 0x5e, 0xa4, 0x3d, 0x2c, 0x57, 0x2e, 0xd2, 0x8e, 0x4d, 0x59, 0x64,
+       0xeb, 0x81, 0xb1, 0x6f, 0x35, 0x0b, 0x39, 0x95, 0xea, 0x20, 0x39, 0xd5,
+       0x8e, 0x71, 0x1c, 0xc0, 0x7b, 0xbb, 0x9d, 0x3f, 0xbb, 0xa7, 0xf0, 0xb8,
+       0xc1, 0xae, 0x29, 0x55, 0xde, 0x29, 0xf0, 0xf4, 0x4e, 0xe1, 0x74, 0x6d,
+       0xb7, 0x07, 0xdd, 0x55, 0xd8, 0xff, 0x78, 0x13, 0xe5, 0x2d, 0xb0, 0x8d,
+       0xb9, 0x7f, 0x18, 0x09, 0xfd, 0x7d, 0xfb, 0xf7, 0x1a, 0xc3, 0xbc, 0x4f,
+       0xc9, 0x9f, 0xed, 0x82, 0x0f, 0x46, 0x8f, 0x70, 0xd2, 0xf9, 0x7b, 0x76,
+       0xa7, 0x8d, 0xf6, 0xed, 0x2f, 0x1f, 0xf1, 0xf3, 0xd6, 0x24, 0x80, 0x47,
+       0x3f, 0xea, 0xf1, 0x60, 0x7e, 0xc3, 0x56, 0xe6, 0x89, 0x43, 0x3e, 0x09,
+       0xde, 0x6b, 0xa2, 0xfc, 0xc6, 0xa7, 0x4b, 0x46, 0x25, 0x2d, 0x80, 0xea,
+       0xe3, 0x26, 0x3d, 0x9b, 0x84, 0x72, 0xfd, 0xa4, 0x90, 0x37, 0x21, 0x91,
+       0x17, 0xd4, 0xdc, 0xb6, 0x7a, 0x04, 0xea, 0xb1, 0xcf, 0x5f, 0xe3, 0xf2,
+       0xf0, 0xc7, 0x42, 0x3e, 0xed, 0x32, 0xf7, 0x34, 0x10, 0x3d, 0x27, 0x39,
+       0xc8, 0xee, 0x60, 0x6c, 0x1b, 0xd9, 0x17, 0xcd, 0xe9, 0x40, 0x6c, 0xd0,
+       0x91, 0xa6, 0x0c, 0xfe, 0xb4, 0x98, 0xdd, 0x4b, 0xb1, 0x9e, 0x05, 0x0c,
+       0x01, 0xcc, 0xbf, 0xb6, 0x7c, 0x31, 0xd9, 0x86, 0x7e, 0x5d, 0xcb, 0x39,
+       0xeb, 0x1c, 0x9e, 0x1f, 0xdb, 0x43, 0x76, 0x87, 0xc5, 0x1e, 0x70, 0x27,
+       0xc2, 0xfb, 0x6d, 0x41, 0x13, 0xc9, 0x85, 0x16, 0xdd, 0x41, 0xf9, 0x6c,
+       0x5b, 0x1d, 0xde, 0x6e, 0x3c, 0xcf, 0x1c, 0x74, 0x9b, 0x28, 0xef, 0x75,
+       0x6b, 0xa1, 0x89, 0xf0, 0xd8, 0xea, 0xb8, 0x36, 0x84, 0xf6, 0xbc, 0xa6,
+       0x34, 0xd7, 0xa2, 0x1e, 0x0b, 0xb9, 0xf7, 0xdb, 0x72, 0xe1, 0x7d, 0xa8,
+       0xd0, 0x44, 0x79, 0x8c, 0x21, 0xdf, 0xc2, 0x39, 0x08, 0x07, 0x03, 0x1a,
+       0xe5, 0x59, 0xd1, 0x0f, 0x96, 0x07, 0x92, 0xe8, 0x1c, 0xf7, 0x56, 0xd6,
+       0xf7, 0xd2, 0x44, 0x2c, 0xaf, 0xe1, 0x76, 0x57, 0x5b, 0xda, 0x7f, 0x1f,
+       0x8d, 0xc7, 0x38, 0xf7, 0x35, 0x6e, 0x0f, 0xdf, 0x56, 0x61, 0x3a, 0xe6,
+       0x81, 0x51, 0x4a, 0x98, 0x09, 0xfd, 0xeb, 0xde, 0x4d, 0xf1, 0x38, 0x8e,
+       0x25, 0x4c, 0xf8, 0xad, 0x41, 0xf2, 0x53, 0x5d, 0x56, 0x4e, 0xbf, 0xef,
+       0x1f, 0xb9, 0xc2, 0x3d, 0x92, 0xec, 0x8a, 0xa8, 0xfd, 0x2b, 0x2b, 0xc6,
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+       0x1f, 0x19, 0xa1, 0x73, 0xfb, 0x32, 0xaf, 0x2f, 0x27, 0x7a, 0x1f, 0x44,
+       0x9d, 0xc1, 0xed, 0x86, 0x79, 0xf1, 0xaf, 0xdf, 0xa6, 0x83, 0xe8, 0xfd,
+       0xc7, 0xa1, 0xbb, 0x96, 0x63, 0x9e, 0xd4, 0xbc, 0x84, 0xd7, 0x6f, 0xcb,
+       0x05, 0xf8, 0xfc, 0xa1, 0xef, 0x2d, 0xc7, 0x3c, 0xaa, 0x79, 0x99, 0xaf,
+       0x7f, 0x96, 0x0b, 0xf2, 0xf6, 0xcb, 0x43, 0xff, 0x87, 0x97, 0x8f, 0x7b,
+       0xfd, 0xb3, 0x91, 0x68, 0x23, 0x1e, 0x6e, 0xe2, 0xe5, 0x53, 0x19, 0x21,
+       0xc9, 0x74, 0x38, 0xb8, 0x9c, 0xf6, 0x87, 0x66, 0xc8, 0x7b, 0x13, 0x7b,
+       0xe8, 0xbc, 0x76, 0x2a, 0x1e, 0xac, 0x98, 0xf4, 0xcd, 0x9f, 0xaa, 0xd5,
+       0x34, 0xe8, 0xba, 0x74, 0xcc, 0x90, 0x71, 0x4b, 0x46, 0xe7, 0xb3, 0xfd,
+       0x07, 0x7f, 0x77, 0x02, 0xe5, 0x94, 0x5f, 0xc6, 0x79, 0x7d, 0xc6, 0x7d,
+       0x4f, 0x26, 0xee, 0x4d, 0xbc, 0x4a, 0xb2, 0x57, 0x8a, 0x8b, 0xec, 0xa5,
+       0x2b, 0xf1, 0x77, 0xc0, 0xe7, 0x55, 0xe2, 0xbe, 0x1d, 0x93, 0x2d, 0x4c,
+       0x78, 0x1d, 0x13, 0xb9, 0xcf, 0xe4, 0xa1, 0xaf, 0x73, 0xdf, 0x4e, 0xe4,
+       0x7c, 0x3c, 0xbf, 0x3f, 0xa8, 0x65, 0x23, 0x0b, 0x18, 0xef, 0x45, 0xf4,
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+       0xc8, 0x1a, 0x54, 0x26, 0x46, 0xf6, 0x71, 0xe5, 0xb8, 0x3e, 0x51, 0xfa,
+       0x76, 0x62, 0xd0, 0xa3, 0xee, 0xd8, 0x2f, 0x57, 0x20, 0xdd, 0x3e, 0x71,
+       0xf6, 0xe5, 0xe0, 0xdf, 0x37, 0x39, 0x3e, 0xe3, 0x1d, 0xa2, 0xe3, 0x27,
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+       0x4e, 0xf6, 0x54, 0x45, 0x86, 0xcf, 0x3b, 0x23, 0x15, 0xef, 0x0f, 0xe0,
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+       0xf0, 0x1b, 0xe5, 0x71, 0x06, 0xb3, 0xf9, 0xb9, 0x86, 0xea, 0x12, 0xe3,
+       0xdf, 0x61, 0xab, 0x10, 0xfc, 0xf5, 0x9b, 0x19, 0x7c, 0xff, 0x78, 0x96,
+       0x75, 0x5b, 0xc3, 0x6b, 0x25, 0x78, 0x8f, 0xba, 0xc2, 0x9a, 0xa1, 0x7e,
+       0xfd, 0xf9, 0xb3, 0x16, 0xf4, 0xfb, 0xe7, 0x1d, 0xe4, 0x7f, 0xa7, 0x75,
+       0xfd, 0x81, 0xb7, 0x2d, 0xf4, 0x77, 0x19, 0x10, 0x86, 0x76, 0xd6, 0xef,
+       0xb0, 0x0c, 0xfa, 0x77, 0xe0, 0x0e, 0xcf, 0x50, 0x25, 0xdd, 0x0d, 0xfe,
+       0xca, 0xf3, 0xd9, 0xf9, 0x6d, 0x29, 0x30, 0x9e, 0xf5, 0xab, 0xf8, 0xfd,
+       0xd8, 0x8d, 0xbf, 0x4e, 0x9c, 0x85, 0x70, 0xe3, 0x0a, 0x9c, 0x25, 0xfe,
+       0x3d, 0xbd, 0x7d, 0xb3, 0xf0, 0xb3, 0x65, 0xfe, 0x23, 0x6d, 0xf8, 0x5c,
+       0xce, 0x7a, 0x9f, 0xc7, 0x73, 0x7f, 0x4b, 0x02, 0x46, 0x3f, 0xe2, 0xfa,
+       0x5a, 0xa3, 0xdd, 0xbf, 0xac, 0xc1, 0x68, 0xaf, 0x2f, 0xdf, 0x06, 0xd4,
+       0x01, 0xbd, 0xb6, 0x7c, 0x63, 0x66, 0xcc, 0x3d, 0x7e, 0xfc, 0x7e, 0xc0,
+       0x25, 0x82, 0x9e, 0x4b, 0xd2, 0xef, 0xed, 0xc1, 0x7b, 0x07, 0x96, 0xb0,
+       0x98, 0xfb, 0x01, 0x83, 0x3c, 0x8e, 0x74, 0x3d, 0x9f, 0x01, 0x3c, 0x8d,
+       0xf1, 0x91, 0x79, 0xf8, 0xf7, 0xa4, 0x70, 0x1e, 0xeb, 0x54, 0x8a, 0xf3,
+       0x3e, 0x9f, 0xbd, 0x59, 0xc3, 0xf3, 0x70, 0xf5, 0x0d, 0xfc, 0x5e, 0xb2,
+       0x59, 0x5d, 0x9f, 0x5a, 0xa8, 0x1c, 0xea, 0xe1, 0x7e, 0x53, 0xda, 0x70,
+       0x7e, 0x0f, 0x9e, 0x94, 0x9f, 0x52, 0xbf, 0x5f, 0xff, 0xdc, 0x2e, 0x33,
+       0xc6, 0x0b, 0x62, 0xef, 0x09, 0x5c, 0xbe, 0x78, 0x0e, 0xdd, 0x07, 0xbe,
+       0x58, 0x5f, 0xcb, 0xf5, 0xfb, 0x88, 0x3f, 0xce, 0x4a, 0x82, 0xf7, 0xb1,
+       0xf7, 0xff, 0xd5, 0x74, 0x71, 0xfd, 0x5e, 0xb3, 0x51, 0x09, 0xe1, 0x7d,
+       0xbb, 0xd7, 0xd7, 0x1a, 0xfd, 0x81, 0x65, 0xac, 0xa7, 0x0d, 0xfd, 0x99,
+       0x65, 0x0d, 0xc6, 0xf7, 0xcb, 0x37, 0x1a, 0xe1, 0xef, 0xcd, 0x10, 0x7a,
+       0x6d, 0x1c, 0x1b, 0x87, 0xeb, 0x63, 0xd3, 0x0c, 0x45, 0xa3, 0x73, 0xd5,
+       0x02, 0x3e, 0x9d, 0xfd, 0xc7, 0x57, 0xc2, 0xd0, 0x7f, 0x55, 0x86, 0xbf,
+       0x6d, 0x06, 0xf0, 0xc9, 0x3a, 0x4b, 0x78, 0x02, 0xea, 0xb9, 0xaa, 0x8c,
+       0x00, 0xc1, 0xb2, 0x1c, 0xde, 0xaf, 0xe7, 0x7a, 0x88, 0xeb, 0x7f, 0x13,
+       0xac, 0x24, 0x92, 0xbf, 0x66, 0x1e, 0xb7, 0x08, 0xd6, 0xf1, 0x7b, 0xd9,
+       0xae, 0x1f, 0x60, 0x0f, 0x44, 0xd9, 0x0b, 0xea, 0x40, 0xb8, 0x4b, 0xca,
+       0x4f, 0xbb, 0xff, 0x36, 0xf2, 0xc3, 0x9e, 0x53, 0xe8, 0xef, 0x82, 0x57,
+       0x6b, 0x3e, 0x2d, 0x29, 0xca, 0x4f, 0x8e, 0xe5, 0xc3, 0x5f, 0x0b, 0xbe,
+       0x7e, 0x85, 0xf5, 0x16, 0xe2, 0xb8, 0xf2, 0x91, 0xe9, 0x80, 0x2e, 0xf9,
+       0x8b, 0xf8, 0xdf, 0x7d, 0xce, 0x3f, 0xbc, 0x82, 0xf2, 0x2c, 0xf3, 0x8b,
+       0x15, 0x8f, 0x89, 0xd6, 0xb1, 0x89, 0x6d, 0xc4, 0xfb, 0xc4, 0x40, 0x5e,
+       0xa0, 0x5c, 0x40, 0xfb, 0x13, 0xef, 0xc9, 0xc8, 0x57, 0x3b, 0x17, 0x93,
+       0x9c, 0x9e, 0x68, 0x71, 0xf3, 0xfb, 0x76, 0xd2, 0x59, 0xf4, 0xfa, 0xf7,
+       0x3d, 0xc9, 0x14, 0xc4, 0x17, 0x0e, 0x1d, 0xfb, 0xbd, 0x2a, 0xab, 0x9b,
+       0xee, 0xdb, 0x98, 0xdf, 0x71, 0xef, 0xa7, 0x28, 0xe7, 0xf2, 0x46, 0xf9,
+       0xbc, 0x0f, 0xc0, 0xf8, 0xb6, 0x8a, 0xfb, 0xb4, 0xb7, 0xfe, 0x5a, 0x21,
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+       0x1b, 0xae, 0xa2, 0x7b, 0xa5, 0x86, 0x89, 0x7e, 0x7f, 0x3f, 0x4b, 0xa7,
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+       0xa8, 0x3d, 0x28, 0x0b, 0x53, 0x23, 0x4f, 0xb9, 0x4f, 0x70, 0x4d, 0x64,
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+       0xf3, 0x41, 0xea, 0xcd, 0x46, 0xb9, 0x33, 0xa0, 0x9e, 0x8f, 0x19, 0xf2,
+       0x80, 0x66, 0xa9, 0xe7, 0x5d, 0xb8, 0xbf, 0xdd, 0xf8, 0xdc, 0xa8, 0x8b,
+       0xe6, 0x75, 0xa8, 0x36, 0xe3, 0xfd, 0x90, 0x66, 0xb7, 0xf1, 0x7e, 0xc8,
+       0xab, 0x0a, 0x8c, 0xeb, 0x7b, 0x9e, 0xc7, 0xb8, 0xae, 0xaf, 0x2e, 0x1b,
+       0x65, 0x28, 0x5f, 0xe0, 0x1b, 0x67, 0x28, 0x5f, 0x34, 0xa7, 0xd8, 0x00,
+       0x5f, 0xe3, 0x9f, 0x6a, 0xa8, 0x7f, 0xdd, 0xe2, 0x99, 0xc6, 0x38, 0x42,
+       0xba, 0xf1, 0x7e, 0x48, 0xbb, 0x6e, 0xbc, 0x1f, 0x32, 0xbe, 0xc0, 0x78,
+       0x3f, 0xa4, 0xd3, 0x63, 0xbc, 0x1f, 0x92, 0xa5, 0x74, 0x52, 0x5e, 0x9a,
+       0xc5, 0x16, 0xec, 0x0d, 0xe8, 0x78, 0xbf, 0x00, 0xbf, 0x87, 0x56, 0xca,
+       0xe9, 0x71, 0x2e, 0x1b, 0x5d, 0x2a, 0x17, 0x57, 0x6c, 0x77, 0xe0, 0xb3,
+       0xbd, 0xc8, 0x1a, 0x46, 0xba, 0xb5, 0x0f, 0xe7, 0xfb, 0xb9, 0xd6, 0x17,
+       0x6f, 0x4f, 0x0f, 0x23, 0xd6, 0x13, 0xf6, 0xda, 0x2a, 0xe1, 0xf9, 0xb4,
+       0x12, 0xaa, 0xc2, 0xfd, 0x28, 0x9b, 0xf0, 0x1b, 0x2f, 0xbb, 0x8b, 0x19,
+       0xe4, 0xf8, 0x95, 0x33, 0xb9, 0x1c, 0x97, 0x4f, 0xe6, 0x0b, 0xc4, 0x57,
+       0x62, 0x5c, 0x76, 0x8f, 0x9e, 0xc9, 0xf3, 0xb6, 0x7b, 0x2e, 0xbb, 0x58,
+       0x7e, 0xc5, 0xa5, 0x3e, 0xff, 0x2f, 0xc2, 0x78, 0x4b, 0x6b, 0x00, 0x80,
+       0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x0b, 0xed, 0x5a, 0x7d, 0x50, 0x54, 0x57, 0x96, 0x3f, 0xb7, 0xfb,
+       0x75, 0xd3, 0x0d, 0x88, 0x0d, 0x28, 0x1f, 0x41, 0xf4, 0xa1, 0xa0, 0x26,
+       0x20, 0x69, 0x41, 0x8c, 0x4e, 0x66, 0x36, 0xaf, 0xbb, 0x81, 0x69, 0x3f,
+       0x32, 0x69, 0xfc, 0x98, 0x60, 0x10, 0xd3, 0xec, 0xe8, 0x16, 0x13, 0x81,
+       0x26, 0xd1, 0x4c, 0x91, 0xaa, 0xdd, 0xa2, 0x55, 0x86, 0x34, 0x66, 0xfe,
+       0x48, 0xac, 0x4c, 0xc6, 0xa4, 0x52, 0xb5, 0xad, 0x15, 0x33, 0x99, 0xa9,
+       0x71, 0x17, 0x13, 0x56, 0xdb, 0x4d, 0xeb, 0x36, 0x2a, 0xae, 0xc9, 0x9a,
+       0xb1, 0xdd, 0x31, 0x19, 0x4d, 0x2a, 0x29, 0x74, 0xdd, 0x4c, 0xac, 0x8c,
+       0x0a, 0x31, 0xe3, 0x98, 0x5d, 0x77, 0xdd, 0x73, 0xee, 0x7d, 0x8f, 0xee,
+       0xd7, 0x3c, 0x12, 0xb2, 0x35, 0x95, 0xaa, 0x9d, 0x5a, 0x28, 0xea, 0x72,
+       0xdf, 0xbb, 0x9f, 0xe7, 0xfb, 0xfc, 0xce, 0xb3, 0xa5, 0x03, 0xc0, 0x22,
+       0xfc, 0x3b, 0x68, 0x0b, 0xef, 0x2b, 0x01, 0xb8, 0x97, 0xe1, 0xff, 0x4b,
+       0x01, 0xee, 0xd0, 0xcf, 0x03, 0x00, 0xa7, 0xeb, 0x5c, 0x16, 0xa5, 0x06,
+       0xa0, 0xe2, 0xaf, 0x95, 0x65, 0x30, 0x0d, 0xdf, 0x45, 0xc0, 0x51, 0x86,
+       0xe3, 0xf6, 0x5a, 0x41, 0xa1, 0x7e, 0xf0, 0xa0, 0x95, 0xcf, 0xab, 0x88,
+       0x0c, 0x9b, 0x94, 0xcc, 0xc4, 0xbc, 0xe7, 0x14, 0x5c, 0x68, 0x3a, 0xc0,
+       0x4f, 0x7d, 0xee, 0x65, 0xb4, 0x7e, 0x47, 0x94, 0x39, 0x00, 0xc7, 0x75,
+       0xec, 0xbe, 0x64, 0x95, 0x2b, 0xa8, 0x3f, 0x98, 0xa5, 0x60, 0x5b, 0xe9,
+       0xbb, 0x64, 0x85, 0xcc, 0xe4, 0xe7, 0x17, 0xad, 0xf4, 0xbc, 0x43, 0x1a,
+       0x49, 0x77, 0x60, 0xfb, 0xf7, 0xfd, 0x66, 0x6f, 0xb8, 0x22, 0xb1, 0xae,
+       0xd6, 0xba, 0x14, 0x2b, 0x5f, 0xff, 0x64, 0x31, 0xb6, 0x78, 0x8e, 0xe6,
+       0x27, 0xcd, 0xe1, 0x34, 0x3a, 0x3b, 0x28, 0x2b, 0x5d, 0x8b, 0x01, 0x1a,
+       0xe9, 0x5f, 0x19, 0x9f, 0x1f, 0x18, 0x89, 0x99, 0x71, 0xff, 0xe6, 0x76,
+       0xe6, 0x0c, 0xe2, 0xa3, 0x46, 0xf9, 0xb1, 0x95, 0x90, 0x85, 0xff, 0xf8,
+       0x2d, 0x97, 0x86, 0x6d, 0x00, 0x36, 0xfc, 0xbd, 0x33, 0x1b, 0xcf, 0x59,
+       0x98, 0xb5, 0x17, 0xee, 0xe5, 0xf3, 0x01, 0xf2, 0x00, 0x1e, 0x05, 0xf1,
+       0xf3, 0xc8, 0x92, 0x98, 0x05, 0x4c, 0x00, 0x4d, 0xad, 0x62, 0x3c, 0xfd,
+       0xdc, 0xc1, 0xbf, 0x47, 0xd7, 0xd4, 0x5f, 0x61, 0x95, 0xb8, 0x6e, 0x67,
+       0xca, 0xf3, 0x19, 0xbd, 0xa3, 0xe6, 0x2c, 0x9a, 0x2f, 0x5d, 0x1a, 0x9e,
+       0xaf, 0x3e, 0x27, 0xba, 0x2a, 0x53, 0xa6, 0x7d, 0x5c, 0x8e, 0x9d, 0x72,
+       0xa8, 0xb8, 0x33, 0x07, 0xe0, 0xbc, 0xcf, 0x64, 0x78, 0xaf, 0x87, 0x3c,
+       0x12, 0xbf, 0xd7, 0x79, 0xbf, 0x87, 0xd3, 0xfb, 0xa7, 0x48, 0x37, 0x33,
+       0x23, 0x3a, 0xa6, 0xd2, 0x49, 0xd0, 0xef, 0xab, 0xe8, 0xb3, 0x1f, 0xcf,
+       0x9e, 0xcc, 0xa7, 0xd4, 0x71, 0x6b, 0x3c, 0x82, 0x4f, 0xfb, 0x19, 0x34,
+       0xf6, 0x67, 0x8e, 0x7f, 0xff, 0x33, 0x95, 0x8f, 0x7b, 0x59, 0xbc, 0x0a,
+       0xcc, 0x00, 0x01, 0x1f, 0x0a, 0xcc, 0x54, 0xa4, 0x87, 0xad, 0x65, 0xf3,
+       0xe5, 0x6a, 0xa2, 0xff, 0xcd, 0x5e, 0x46, 0xf4, 0xff, 0x07, 0x06, 0x69,
+       0xb8, 0xfe, 0x07, 0x83, 0x6f, 0xe5, 0xc9, 0x53, 0x00, 0xac, 0x07, 0x86,
+       0xf2, 0x86, 0x71, 0xbd, 0x40, 0xff, 0x50, 0x1e, 0x2c, 0x00, 0x68, 0xb3,
+       0xc8, 0xdb, 0xa4, 0x69, 0x5c, 0x0e, 0x9c, 0xdb, 0x90, 0x2f, 0x1d, 0x91,
+       0x18, 0x3f, 0x7f, 0x7b, 0x7f, 0xf5, 0x20, 0x3d, 0x6f, 0x8f, 0x30, 0xa7,
+       0x1d, 0x8f, 0x1a, 0x18, 0x18, 0xad, 0xe7, 0xf7, 0x84, 0xe1, 0x5e, 0x47,
+       0x26, 0xed, 0x6b, 0x7c, 0xae, 0x66, 0xc5, 0xc4, 0xcf, 0xd5, 0xaa, 0xc8,
+       0xbc, 0x0d, 0xf8, 0x71, 0xcf, 0x69, 0x34, 0x3f, 0x2d, 0x1c, 0x66, 0xc4,
+       0xf7, 0x61, 0x2b, 0x97, 0x8b, 0xc3, 0x0c, 0x9e, 0xc5, 0xfe, 0xde, 0x3e,
+       0x5b, 0x63, 0xd8, 0x60, 0x9d, 0x75, 0x44, 0x6f, 0x94, 0xef, 0x13, 0x7d,
+       0x56, 0x90, 0x50, 0x4e, 0xda, 0x70, 0x3e, 0xdd, 0xe3, 0x64, 0xf1, 0x49,
+       0xab, 0x8d, 0xe4, 0xe6, 0x00, 0xde, 0x8b, 0xd1, 0x3d, 0xce, 0xae, 0xcd,
+       0xa0, 0xf5, 0xb7, 0x5a, 0x40, 0x66, 0x89, 0xf3, 0x5d, 0x2d, 0x8e, 0x7f,
+       0x44, 0xf7, 0xbf, 0xb0, 0xd1, 0x02, 0x41, 0x7c, 0xbe, 0x63, 0xa3, 0x99,
+       0xd3, 0xfb, 0xc2, 0x56, 0x33, 0x5f, 0xc7, 0xbc, 0xe9, 0xdf, 0x7b, 0x8b,
+       0xb0, 0xbf, 0x0e, 0xe5, 0x2f, 0x0d, 0x8f, 0x7a, 0x7c, 0xe3, 0x8d, 0x93,
+       0x45, 0xb8, 0xee, 0x85, 0x56, 0xec, 0xe3, 0x7d, 0x3d, 0x9b, 0x2c, 0x5c,
+       0xff, 0xd6, 0x3d, 0xce, 0xf8, 0xf8, 0x54, 0xf9, 0xd5, 0xe4, 0xf5, 0x25,
+       0x55, 0x3e, 0xd7, 0xf9, 0xf5, 0xf2, 0x96, 0x2a, 0xaf, 0xe3, 0xe4, 0xb4,
+       0xf5, 0xeb, 0xc9, 0x69, 0x0f, 0xc9, 0x69, 0x06, 0x97, 0xd3, 0xca, 0x3b,
+       0x66, 0xce, 0xf7, 0xba, 0x7c, 0x92, 0x9f, 0xa7, 0xc0, 0xb9, 0x8f, 0xf4,
+       0xe7, 0xf6, 0x71, 0x4b, 0x3e, 0x9e, 0x77, 0x76, 0xaf, 0xc3, 0xb9, 0x1d,
+       0xfb, 0x0b, 0xcc, 0xe1, 0x1f, 0xe7, 0x91, 0x5d, 0x38, 0x2e, 0xde, 0x2f,
+       0x6c, 0xdb, 0xc3, 0x48, 0x5f, 0xf0, 0xf0, 0x8f, 0xd0, 0xbd, 0x8a, 0x42,
+       0x56, 0xd8, 0xc9, 0x48, 0x8e, 0x04, 0xbf, 0x7e, 0xa6, 0xf2, 0x4b, 0x86,
+       0x11, 0x96, 0x41, 0xfa, 0x2a, 0xc5, 0x67, 0xfb, 0x50, 0x3e, 0x70, 0x6b,
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+       0x16, 0x1c, 0x2a, 0xd8, 0xb3, 0x33, 0x49, 0x6e, 0xeb, 0x55, 0x79, 0xb4,
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+       0xb4, 0x45, 0x95, 0xbd, 0x1b, 0x51, 0x33, 0xd8, 0xf0, 0xfd, 0x8d, 0x01,
+       0x16, 0x06, 0x96, 0x38, 0xff, 0x86, 0x5b, 0x45, 0xe0, 0x47, 0x7b, 0xf2,
+       0x3e, 0xed, 0x87, 0x13, 0xdb, 0xbb, 0x7e, 0xc3, 0xed, 0x9c, 0xb3, 0x75,
+       0xb4, 0x5e, 0xce, 0x24, 0xb9, 0xba, 0xd8, 0x4b, 0xfd, 0x40, 0xd7, 0x1f,
+       0xea, 0x01, 0xdb, 0x8f, 0xd0, 0x4f, 0x90, 0x7c, 0x05, 0x22, 0x0c, 0x0a,
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+       0x74, 0x8e, 0x72, 0xfb, 0xf9, 0x32, 0xde, 0x4b, 0xc1, 0x73, 0xa7, 0xbb,
+       0xb2, 0x39, 0x5d, 0x02, 0xd1, 0x85, 0x26, 0xc1, 0xcf, 0x45, 0x26, 0xe2,
+       0xff, 0x13, 0x2a, 0xff, 0x07, 0xef, 0xf9, 0x8f, 0x2c, 0xb2, 0x5f, 0xb6,
+       0x2e, 0xf9, 0xcc, 0xfd, 0xc4, 0xc7, 0x53, 0x66, 0xce, 0xc7, 0x9d, 0xee,
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+       0x6d, 0xea, 0xfb, 0x46, 0x6b, 0xb0, 0xcc, 0x89, 0xf3, 0x1a, 0x55, 0xb9,
+       0x4d, 0x7d, 0x6f, 0x75, 0x09, 0xb9, 0x44, 0x0a, 0x5b, 0x7c, 0x53, 0x04,
+       0xad, 0x18, 0xd2, 0x6d, 0xbd, 0x2a, 0x5f, 0xcd, 0x78, 0x95, 0xa9, 0x39,
+       0xd8, 0x8f, 0xb0, 0x58, 0x3a, 0xea, 0x6d, 0x73, 0xd4, 0x73, 0x45, 0xa2,
+       0xb6, 0x93, 0xc1, 0x25, 0x9d, 0x3d, 0x00, 0xb8, 0xa4, 0xe9, 0xb3, 0x79,
+       0x62, 0x79, 0x9b, 0x6c, 0xdb, 0x41, 0xeb, 0x95, 0x25, 0xd9, 0x4b, 0x3f,
+       0x2e, 0x3a, 0x3f, 0xb1, 0x5f, 0x53, 0x6b, 0x06, 0x39, 0xd1, 0xa4, 0xfd,
+       0x83, 0xfc, 0x1e, 0x69, 0xc5, 0xa5, 0xf9, 0x7e, 0x83, 0x7b, 0x8e, 0xc9,
+       0xfb, 0x70, 0x11, 0xc8, 0xc8, 0xaf, 0x8e, 0x10, 0x03, 0x19, 0xe5, 0xbe,
+       0xfd, 0x56, 0x39, 0x6f, 0xaf, 0x1d, 0x7e, 0x5a, 0x26, 0x3d, 0xb1, 0xa5,
+       0x8f, 0xbc, 0x40, 0x7e, 0x01, 0xe6, 0x9a, 0x1c, 0xfb, 0x90, 0xbf, 0xed,
+       0x41, 0x50, 0x92, 0xfd, 0xdc, 0xa8, 0x5b, 0xe8, 0xed, 0xa8, 0x5b, 0xe8,
+       0xf1, 0x4c, 0x17, 0x93, 0x3e, 0xb6, 0x71, 0xbb, 0x55, 0x4e, 0xf7, 0x76,
+       0x17, 0xfa, 0x4b, 0x5c, 0x78, 0x8e, 0xdf, 0x17, 0xbf, 0x97, 0x75, 0x0c,
+       0x1f, 0xb7, 0x59, 0x63, 0x95, 0x60, 0xfc, 0xbc, 0x03, 0xd0, 0x1f, 0xdb,
+       0x48, 0x9f, 0x70, 0xdf, 0x72, 0xe4, 0xcf, 0xeb, 0x06, 0xe7, 0xbe, 0xe9,
+       0x76, 0xcf, 0xa5, 0x79, 0x33, 0xe1, 0x59, 0x2e, 0xdf, 0x80, 0xf2, 0x4d,
+       0x72, 0x95, 0x7a, 0xcf, 0x85, 0x2e, 0x71, 0x2e, 0x4d, 0x9f, 0xd7, 0x1d,
+       0xbb, 0x62, 0x1d, 0x26, 0xb9, 0x8d, 0x18, 0xeb, 0x33, 0xf3, 0xb8, 0x16,
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+       0x73, 0xa3, 0x5c, 0x5e, 0xc5, 0x73, 0xec, 0x45, 0xb9, 0xbc, 0xee, 0xf3,
+       0x65, 0x64, 0xe3, 0xfc, 0xeb, 0x7e, 0x5f, 0x46, 0x4e, 0x66, 0x42, 0xff,
+       0x3b, 0x76, 0x67, 0xf0, 0x79, 0x7d, 0xa5, 0xab, 0x72, 0x5b, 0xb0, 0x5f,
+       0x4f, 0x72, 0x8f, 0xfb, 0x5d, 0x8b, 0x78, 0x6c, 0x44, 0xe7, 0x0d, 0xbb,
+       0x85, 0xde, 0x69, 0xfb, 0x7d, 0x14, 0x5b, 0x97, 0x4b, 0xfa, 0x53, 0x63,
+       0x19, 0xb1, 0x3a, 0xf1, 0xfd, 0x8c, 0xe8, 0xc5, 0x2c, 0x8a, 0xeb, 0x6a,
+       0x0e, 0xaf, 0xce, 0x25, 0xfd, 0x9b, 0xe8, 0x9c, 0x8b, 0xdd, 0xc2, 0x2e,
+       0xb5, 0x77, 0x6d, 0xd9, 0x7c, 0x39, 0x57, 0xc8, 0x83, 0x19, 0xf5, 0x69,
+       0xb3, 0xea, 0xc7, 0x02, 0xdb, 0x63, 0x56, 0xa2, 0xff, 0xe6, 0x2e, 0xe0,
+       0xf2, 0x3b, 0x78, 0xf0, 0x83, 0x0e, 0xd2, 0xdf, 0x6b, 0xd1, 0x0c, 0x07,
+       0xf9, 0xbd, 0xab, 0x47, 0x32, 0x82, 0x64, 0xef, 0xaf, 0x1f, 0x4d, 0x0b,
+       0xa3, 0x25, 0x86, 0x36, 0x92, 0x77, 0xb4, 0x67, 0x57, 0x2d, 0xc3, 0xdf,
+       0xe3, 0xf1, 0xe3, 0x61, 0xb3, 0x23, 0x88, 0xe3, 0x02, 0x47, 0x3f, 0x7d,
+       0x81, 0xf4, 0x31, 0x70, 0x10, 0xb5, 0x11, 0xd7, 0xdd, 0x1c, 0x7d, 0x7a,
+       0x94, 0xfc, 0x5b, 0x5b, 0x74, 0xd9, 0x15, 0x89, 0xda, 0x5f, 0x7d, 0xb3,
+       0xfa, 0xd0, 0xde, 0xf5, 0x23, 0x7e, 0x5f, 0xad, 0xff, 0x69, 0xb7, 0x4d,
+       0x26, 0xfb, 0x79, 0x4d, 0x12, 0x76, 0x62, 0x73, 0xe4, 0x0d, 0x1e, 0xcf,
+       0x6e, 0xbe, 0x7d, 0xa3, 0xd2, 0x57, 0x41, 0xf7, 0xfc, 0xcf, 0xc5, 0x64,
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+       0xd3, 0xfb, 0xc0, 0xa1, 0x8c, 0x4e, 0xa3, 0xf8, 0xa4, 0xd5, 0x63, 0xe6,
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+       0xaf, 0x92, 0x9e, 0x67, 0xbd, 0xb3, 0x91, 0x7e, 0x35, 0x67, 0xd7, 0x38,
+       0xcd, 0x72, 0xe2, 0x7d, 0x4d, 0x99, 0xc9, 0x47, 0xe3, 0x6b, 0xde, 0xad,
+       0xcd, 0xdd, 0x94, 0x34, 0xaf, 0x27, 0x2e, 0x79, 0xe9, 0xf9, 0xa2, 0xb3,
+       0xb5, 0x19, 0x1b, 0x93, 0xe4, 0xd2, 0xea, 0xb1, 0xa8, 0x76, 0x08, 0xb5,
+       0x1a, 0xed, 0xcf, 0x3a, 0x95, 0x86, 0xeb, 0x0a, 0x7e, 0x12, 0x37, 0x57,
+       0x52, 0x5f, 0x0a, 0xaa, 0x71, 0x04, 0xbb, 0xc3, 0xe3, 0x6d, 0x90, 0x25,
+       0xe4, 0x73, 0x13, 0xfd, 0x87, 0xaa, 0xd8, 0x17, 0x97, 0x78, 0x3c, 0x13,
+       0x6c, 0x35, 0x87, 0xcb, 0xf0, 0x7d, 0x53, 0xdc, 0xa4, 0xd8, 0x2b, 0xe9,
+       0x3d, 0xce, 0x4b, 0x8a, 0x33, 0x00, 0x7c, 0x2b, 0x16, 0x10, 0xbf, 0x7f,
+       0x38, 0xdd, 0xb9, 0x53, 0xe6, 0xfe, 0x1e, 0xba, 0xa9, 0xff, 0x54, 0x59,
+       0x98, 0xfc, 0x3d, 0x04, 0x6d, 0x43, 0xa5, 0x49, 0x71, 0xd0, 0xba, 0xb8,
+       0x29, 0x96, 0x86, 0x72, 0xd3, 0x18, 0x4d, 0x8b, 0x51, 0x3c, 0xb4, 0x2e,
+       0x2e, 0x5d, 0xe4, 0x7d, 0x35, 0x3e, 0xfa, 0xc8, 0xf1, 0xfa, 0x8f, 0x67,
+       0x03, 0x8f, 0x8f, 0x2e, 0x27, 0xc7, 0x39, 0x18, 0x0f, 0x5d, 0xd6, 0xc7,
+       0x4b, 0x30, 0x85, 0xce, 0xab, 0xc5, 0x4b, 0xef, 0x51, 0x5c, 0x85, 0xf1,
+       0x6c, 0xf3, 0xd6, 0x98, 0x85, 0xfc, 0x15, 0xc6, 0x49, 0xba, 0xf1, 0x8f,
+       0x36, 0x7e, 0xf7, 0x0a, 0xa3, 0x38, 0xa9, 0x4b, 0xff, 0xbc, 0x24, 0x2e,
+       0x99, 0x1e, 0xc4, 0x7b, 0x96, 0xa0, 0xb9, 0x23, 0x32, 0xf4, 0xc5, 0x9f,
+       0xb7, 0x91, 0x7e, 0x68, 0x71, 0x26, 0xf1, 0x6b, 0xc0, 0x40, 0xdf, 0x2b,
+       0x55, 0x3d, 0xd1, 0xf4, 0xa8, 0x27, 0x6e, 0xe2, 0x7c, 0xe8, 0x89, 0xbb,
+       0x6d, 0xa5, 0xd8, 0xce, 0x53, 0xdf, 0x0f, 0x38, 0x4c, 0x10, 0xc4, 0xf5,
+       0x7b, 0xa2, 0xab, 0xf7, 0x31, 0x8a, 0xcb, 0x6e, 0x3f, 0x9c, 0x41, 0xf4,
+       0xea, 0x39, 0xb7, 0x0a, 0xb6, 0x93, 0xbe, 0x3b, 0xdc, 0xb6, 0x32, 0x9a,
+       0x77, 0xfb, 0xbb, 0xb6, 0xb5, 0x15, 0x09, 0xf9, 0x18, 0x67, 0x3f, 0x5c,
+       0xaa, 0x7d, 0x1c, 0x8b, 0x07, 0x8c, 0xfd, 0xdc, 0x27, 0x2e, 0x35, 0xae,
+       0xfa, 0x86, 0xfc, 0xdd, 0xe5, 0x3f, 0x17, 0x7f, 0xa7, 0xf8, 0x3f, 0x25,
+       0xfb, 0x5d, 0xf1, 0x9a, 0xdc, 0x44, 0xf1, 0x21, 0xde, 0xe7, 0x1e, 0x8a,
+       0x67, 0x53, 0xfd, 0x84, 0x66, 0x7f, 0xb5, 0x75, 0x8b, 0x54, 0x3e, 0x8f,
+       0xb7, 0xbf, 0x57, 0x78, 0xfc, 0x82, 0xf9, 0x2f, 0xb7, 0xbf, 0x45, 0x6e,
+       0x99, 0x8f, 0x9b, 0x11, 0x6d, 0xc8, 0xe5, 0x79, 0xf1, 0xb9, 0x35, 0xb9,
+       0x72, 0xe6, 0xf8, 0xf5, 0xe7, 0x48, 0x4e, 0x53, 0x4e, 0xc5, 0xf8, 0xf5,
+       0xb5, 0x78, 0x2d, 0x10, 0x54, 0x86, 0x6c, 0x94, 0xc7, 0x28, 0x66, 0xae,
+       0x9f, 0x81, 0x35, 0x2c, 0xcc, 0xa8, 0xef, 0x63, 0x3c, 0xce, 0x0e, 0xac,
+       0xb7, 0x84, 0xe9, 0xbd, 0x76, 0x9e, 0xf8, 0x1a, 0xc6, 0xc7, 0xad, 0x75,
+       0xb2, 0xb0, 0x9d, 0x25, 0xe2, 0x3f, 0x2d, 0x3e, 0x1c, 0x7b, 0xbf, 0x08,
+       0xdf, 0x97, 0x24, 0xe2, 0x45, 0x2d, 0x2e, 0x8c, 0xfb, 0x18, 0xcf, 0x83,
+       0xd6, 0x28, 0x16, 0xfe, 0x7e, 0xde, 0x4c, 0x7f, 0x8e, 0xbb, 0x86, 0xee,
+       0x67, 0xe7, 0xcf, 0x6b, 0x96, 0x8a, 0x75, 0xd1, 0x0e, 0x0c, 0x51, 0x7e,
+       0xf4, 0xf0, 0xf7, 0x19, 0x70, 0x3b, 0xa0, 0xc6, 0x8b, 0x9a, 0x7c, 0xa6,
+       0xc6, 0x93, 0x9f, 0x45, 0xe7, 0x4c, 0x85, 0x2f, 0x89, 0x2b, 0x5e, 0x56,
+       0xe5, 0x52, 0xd3, 0xaf, 0x99, 0x29, 0x7a, 0xa1, 0xf9, 0xa9, 0x7a, 0xd5,
+       0x4f, 0x77, 0x90, 0x9f, 0xae, 0x26, 0x3f, 0xfd, 0x85, 0x95, 0xf4, 0x60,
+       0xa2, 0xb8, 0x1b, 0xfd, 0xf4, 0x5c, 0x37, 0x9f, 0x07, 0x7c, 0xfe, 0xa2,
+       0x77, 0x25, 0x9f, 0x51, 0xde, 0x7d, 0x58, 0x5d, 0x77, 0xb1, 0xc6, 0xb7,
+       0xf8, 0x09, 0x17, 0x9d, 0xb7, 0x18, 0xe2, 0xdb, 0x28, 0x5f, 0x9c, 0xc8,
+       0x7f, 0xe6, 0x79, 0x4c, 0x3a, 0xbb, 0x90, 0xfa, 0xbe, 0x7e, 0x92, 0x7a,
+       0xdc, 0xa2, 0xc6, 0x0b, 0xdf, 0x94, 0x1e, 0x37, 0xab, 0xf1, 0xd7, 0xff,
+       0x75, 0x3d, 0x1e, 0x8b, 0xff, 0xac, 0xc6, 0xf7, 0xbc, 0xe9, 0x76, 0xfd,
+       0x15, 0xc9, 0x6f, 0xba, 0xb9, 0x33, 0xee, 0x22, 0xbd, 0xfb, 0x17, 0xd4,
+       0x3b, 0x79, 0xfc, 0xb8, 0x22, 0x2d, 0x9f, 0x94, 0x40, 0xc7, 0x9f, 0xa1,
+       0x62, 0xab, 0x89, 0xf2, 0x9e, 0x40, 0xab, 0xc0, 0x01, 0x42, 0xd9, 0xf2,
+       0x19, 0x9e, 0x9f, 0xbc, 0x65, 0x06, 0x5a, 0x67, 0xf3, 0xad, 0x42, 0x1e,
+       0xa7, 0x3d, 0x76, 0x2b, 0x9b, 0xb7, 0xa1, 0x42, 0x10, 0x7e, 0xf4, 0xc9,
+       0x12, 0x8e, 0xdb, 0x3c, 0xf6, 0xda, 0x59, 0x8b, 0x82, 0xf3, 0x9b, 0xb6,
+       0xb2, 0x85, 0x84, 0x07, 0x35, 0xb5, 0xea, 0xef, 0x13, 0x9a, 0xae, 0x70,
+       0x9c, 0x2d, 0x78, 0x84, 0xf1, 0x78, 0x39, 0x54, 0xd8, 0x7f, 0x92, 0xf4,
+       0x2a, 0xb8, 0x6f, 0x8e, 0x4c, 0xeb, 0x37, 0xd3, 0x65, 0x09, 0x0f, 0x69,
+       0xcd, 0x0e, 0xef, 0x20, 0xfc, 0x82, 0x70, 0x9c, 0x7b, 0xe9, 0x79, 0x7a,
+       0x82, 0x0e, 0xb8, 0x4f, 0xbb, 0xfa, 0xfc, 0x7e, 0x15, 0xdf, 0x81, 0x94,
+       0x38, 0xe0, 0xcd, 0xc1, 0x0b, 0x1c, 0xef, 0x09, 0x0c, 0x30, 0x20, 0xfd,
+       0xb5, 0x46, 0xd1, 0x7e, 0x90, 0x3d, 0x39, 0x25, 0xf0, 0x8e, 0x8e, 0xa8,
+       0xb0, 0x0b, 0x9f, 0x74, 0xd9, 0xb9, 0x3d, 0xf9, 0x44, 0x12, 0xf7, 0x08,
+       0x74, 0xb1, 0xf0, 0x36, 0x96, 0x88, 0x23, 0xae, 0x44, 0x9f, 0xcb, 0x23,
+       0x3d, 0x1b, 0x17, 0x4f, 0x28, 0x18, 0x4f, 0xe4, 0x25, 0xe2, 0x89, 0xf6,
+       0x57, 0xde, 0xe5, 0xf6, 0x30, 0x35, 0x7e, 0xc8, 0x19, 0x10, 0xfb, 0x04,
+       0xda, 0xcc, 0x61, 0xc2, 0x63, 0x86, 0x8a, 0x17, 0x33, 0xea, 0xb7, 0x63,
+       0x3e, 0x98, 0x4f, 0x71, 0xa2, 0x2c, 0x3f, 0x54, 0x24, 0xce, 0x05, 0x61,
+       0x6e, 0x57, 0x14, 0x1d, 0x4e, 0xb2, 0xf7, 0x2e, 0xe1, 0xf7, 0x3f, 0x3b,
+       0xf5, 0x6f, 0x3c, 0x8f, 0x6c, 0x3a, 0xcc, 0x20, 0x97, 0xc7, 0x1d, 0x4a,
+       0xbc, 0x34, 0x2f, 0x11, 0x77, 0x3c, 0x1a, 0x5a, 0xce, 0xfd, 0xbf, 0x16,
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+       0x88, 0x3c, 0xb8, 0xda, 0xea, 0x9c, 0xd3, 0x99, 0xc4, 0xa7, 0xcb, 0x6a,
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+       0x1e, 0x60, 0x95, 0x29, 0xbe, 0x4a, 0x5d, 0xf7, 0x50, 0x9d, 0x99, 0xcb,
+       0xc5, 0x1b, 0x14, 0x90, 0x10, 0xbd, 0x96, 0x49, 0x61, 0x1a, 0x57, 0xbd,
+       0x4c, 0xe2, 0xfc, 0xce, 0x69, 0xb6, 0xf3, 0x7c, 0x3c, 0xc7, 0x02, 0xe6,
+       0x4c, 0xea, 0x37, 0x08, 0x7f, 0x56, 0xe5, 0x9d, 0xe6, 0xa1, 0x3e, 0xac,
+       0xc9, 0xe6, 0xfe, 0xb8, 0xea, 0x94, 0x9c, 0xbd, 0xa9, 0x22, 0x91, 0xef,
+       0xe7, 0x2c, 0xdb, 0x3a, 0x9d, 0xe8, 0xf4, 0x55, 0x75, 0x22, 0x0d, 0x37,
+       0x98, 0x37, 0x53, 0x99, 0x4a, 0x7e, 0xe3, 0xeb, 0xd6, 0x89, 0xda, 0x4f,
+       0x9f, 0xb3, 0xd2, 0xbd, 0x37, 0x0c, 0xeb, 0xeb, 0x44, 0x5a, 0xdd, 0x67,
+       0xa2, 0x3a, 0x91, 0x56, 0xa7, 0x0d, 0x78, 0x3f, 0xd7, 0xd5, 0x95, 0x03,
+       0xd2, 0x48, 0x3d, 0xe1, 0x2b, 0xd5, 0x47, 0x2e, 0xf2, 0x3a, 0x71, 0x20,
+       0xc2, 0x1c, 0x05, 0x25, 0x89, 0xfa, 0x51, 0x60, 0x60, 0xd4, 0xca, 0xe9,
+       0xab, 0xd6, 0x8d, 0x70, 0xbc, 0x95, 0xe6, 0x0d, 0x74, 0x8b, 0xfa, 0xd1,
+       0x41, 0xdc, 0x9f, 0xda, 0x08, 0xde, 0x57, 0xc1, 0x73, 0xfc, 0x23, 0xde,
+       0x97, 0xda, 0x28, 0xde, 0x97, 0x9e, 0x1f, 0xed, 0x9e, 0xcf, 0xdb, 0x58,
+       0xb7, 0x93, 0xb7, 0xc7, 0xba, 0x97, 0xf0, 0xb6, 0x1a, 0xc5, 0xa6, 0x30,
+       0x87, 0xea, 0x4e, 0xa3, 0xbc, 0xee, 0x54, 0x53, 0xab, 0xaf, 0x5b, 0x68,
+       0x75, 0x09, 0x77, 0xa1, 0x6f, 0x49, 0x6d, 0x8d, 0xae, 0x6e, 0xc1, 0xfb,
+       0xa9, 0x75, 0x0b, 0x73, 0xba, 0xc8, 0x47, 0x03, 0xa7, 0x2c, 0xce, 0xbd,
+       0xf8, 0x3c, 0x70, 0xda, 0xc6, 0xed, 0xac, 0x2b, 0xda, 0x32, 0x8b, 0xe2,
+       0xb2, 0x9b, 0x67, 0xfd, 0xb3, 0x1c, 0xbc, 0x0e, 0x90, 0xcb, 0xf3, 0xca,
+       0x31, 0xf9, 0x55, 0x9c, 0xf6, 0x6c, 0xca, 0x07, 0x7c, 0x4e, 0x3b, 0xd5,
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+       0xf8, 0x53, 0xdc, 0x4a, 0x79, 0x3f, 0xd1, 0x41, 0xe1, 0xf1, 0x9c, 0xcb,
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+       0xf7, 0xa3, 0x75, 0x02, 0xdf, 0xd7, 0xec, 0x47, 0x95, 0xcf, 0xa4, 0xec,
+       0xa1, 0xf6, 0x94, 0x62, 0xdf, 0x94, 0x64, 0x1f, 0xfa, 0x7c, 0x02, 0x27,
+       0xee, 0x2b, 0x9d, 0xcd, 0xf5, 0xef, 0x79, 0xdf, 0xec, 0xec, 0x8d, 0xc9,
+       0x78, 0xbe, 0x57, 0xe4, 0x71, 0x39, 0xcb, 0x4a, 0xed, 0xc9, 0xcf, 0x59,
+       0xbd, 0x45, 0xc4, 0x7d, 0x0c, 0x7c, 0x46, 0x76, 0xac, 0xb7, 0x76, 0x42,
+       0x7b, 0xdb, 0x6b, 0x1c, 0xdf, 0x19, 0xd7, 0x05, 0xfa, 0xbc, 0xc2, 0x8e,
+       0x68, 0xb8, 0xff, 0xf8, 0x3a, 0x81, 0xf3, 0xad, 0xd2, 0x24, 0xbc, 0xff,
+       0xda, 0x3b, 0x28, 0xa7, 0x98, 0xb7, 0x0e, 0x1e, 0x4e, 0xe3, 0xfe, 0xfc,
+       0xe6, 0x91, 0xb4, 0xbd, 0x14, 0x7f, 0x57, 0x79, 0x37, 0xce, 0x9a, 0x82,
+       0xfd, 0xaa, 0xf3, 0x69, 0x50, 0x22, 0xfc, 0x91, 0xae, 0xbe, 0xd0, 0xe4,
+       0x35, 0x29, 0xf6, 0x2c, 0xa3, 0x7a, 0x82, 0x52, 0x64, 0x42, 0xb9, 0x1d,
+       0x57, 0x37, 0xf0, 0x9a, 0xb8, 0x7d, 0x1f, 0xab, 0x1b, 0x78, 0xa5, 0x8b,
+       0xbc, 0xaf, 0xc6, 0xe9, 0x1b, 0x46, 0x7f, 0x37, 0xa5, 0x84, 0x11, 0xfd,
+       0xc3, 0x21, 0xca, 0x33, 0xde, 0x68, 0x67, 0xce, 0x41, 0x18, 0x5f, 0x47,
+       0xc0, 0x85, 0x8b, 0x60, 0x09, 0xde, 0xc2, 0x7b, 0x8e, 0xd7, 0x95, 0x9d,
+       0x9d, 0xcc, 0x29, 0xcb, 0x5f, 0x5d, 0x5f, 0xc8, 0x53, 0x71, 0x86, 0x8e,
+       0x48, 0xb6, 0x99, 0xe4, 0xbc, 0xf9, 0x04, 0x40, 0x2e, 0x33, 0xaa, 0x33,
+       0x78, 0x79, 0xbc, 0x5f, 0x05, 0xcf, 0x86, 0x6a, 0xe9, 0x7b, 0xac, 0x52,
+       0x93, 0x83, 0xfc, 0x59, 0x2a, 0x5e, 0x40, 0x72, 0x42, 0xfe, 0x3f, 0x15,
+       0x27, 0x8c, 0xaa, 0x7c, 0x8c, 0xd6, 0x0a, 0x7f, 0x53, 0xe7, 0x11, 0xfe,
+       0xa6, 0x4a, 0x8d, 0x4b, 0xb4, 0x79, 0xa9, 0xfc, 0xcf, 0x56, 0xfd, 0xd3,
+       0x44, 0xb8, 0x23, 0x53, 0xe3, 0x9f, 0x1e, 0x6f, 0x55, 0x1f, 0xf1, 0x2f,
+       0xb8, 0xd2, 0x04, 0xe4, 0x07, 0x7a, 0xbc, 0x6e, 0x5b, 0x69, 0xd2, 0x7a,
+       0x67, 0x6a, 0xc5, 0x77, 0x4b, 0xbb, 0xa8, 0x6e, 0x31, 0x2d, 0xb9, 0x6e,
+       0x21, 0xea, 0x13, 0xa9, 0xf5, 0x0a, 0xcd, 0x4e, 0x55, 0x0f, 0x7e, 0x51,
+       0x4f, 0xfc, 0x7f, 0x3e, 0x2a, 0xf0, 0xa4, 0x40, 0x81, 0xc0, 0x37, 0xab,
+       0x8f, 0xba, 0x4e, 0x91, 0xde, 0x27, 0xce, 0x29, 0xee, 0xf7, 0x3c, 0xf2,
+       0x38, 0xce, 0xe3, 0x28, 0x67, 0x36, 0x88, 0x7b, 0x81, 0x4d, 0xe0, 0x5e,
+       0x1c, 0x67, 0xa8, 0x5a, 0xf9, 0xf9, 0xb1, 0x0c, 0xa2, 0x9f, 0x0f, 0xfd,
+       0x15, 0xd9, 0xa5, 0xd3, 0xa5, 0x3b, 0x32, 0xc9, 0x9e, 0xac, 0x94, 0x6a,
+       0x98, 0xcc, 0xf1, 0xee, 0x31, 0xfc, 0x9b, 0xf0, 0xa9, 0xd5, 0x67, 0x5a,
+       0x97, 0x03, 0xf9, 0xff, 0xb5, 0x0b, 0xcf, 0x12, 0xdd, 0xd7, 0xae, 0xb7,
+       0xf0, 0xef, 0x90, 0x34, 0x7f, 0xb5, 0xfa, 0x4c, 0x63, 0xbd, 0x78, 0xbf,
+       0x67, 0x7b, 0x3a, 0xbd, 0x9f, 0xcf, 0x9c, 0x76, 0x99, 0x9e, 0x7b, 0xdd,
+       0xf4, 0x7c, 0xc5, 0xaf, 0x62, 0x84, 0xf4, 0xc1, 0x83, 0x74, 0x7b, 0xd4,
+       0x9b, 0xf8, 0xe9, 0xcb, 0x12, 0xe9, 0xcb, 0xbc, 0x99, 0xfe, 0xeb, 0xa4,
+       0x3f, 0xd5, 0x0d, 0x2a, 0x0e, 0xbe, 0x5e, 0xf8, 0xd7, 0xb5, 0xd1, 0x06,
+       0x0b, 0x64, 0x8e, 0xf7, 0x77, 0xc7, 0x8b, 0x6f, 0xf2, 0x3c, 0xfa, 0x46,
+       0xb4, 0x9a, 0xe3, 0xdb, 0xb9, 0x54, 0x7f, 0xad, 0x48, 0xf8, 0x8b, 0xea,
+       0x23, 0xe8, 0x87, 0xa6, 0xfc, 0xe9, 0xfc, 0x50, 0x76, 0x9d, 0xc8, 0x07,
+       0xef, 0x45, 0x3f, 0x44, 0xe7, 0xc9, 0x69, 0x10, 0x75, 0xc2, 0x54, 0xfe,
+       0x9f, 0x51, 0xe3, 0xc9, 0x89, 0xfc, 0xca, 0x44, 0x76, 0x94, 0xfc, 0x88,
+       0x69, 0x89, 0xd0, 0x1b, 0x56, 0x90, 0xf0, 0xbf, 0x32, 0xe5, 0xd7, 0xf7,
+       0x25, 0xfc, 0xb0, 0x23, 0x82, 0xfd, 0xfc, 0x2f, 0xc1, 0xbd, 0x55, 0xb9,
+       0xce, 0x9e, 0x20, 0x0e, 0x73, 0xab, 0xf2, 0x3b, 0xe1, 0xf7, 0x1b, 0x91,
+       0x6f, 0x06, 0x07, 0xff, 0x8b, 0xba, 0x3f, 0x8f, 0x7a, 0x96, 0x96, 0xe7,
+       0x68, 0x78, 0xb8, 0x96, 0x17, 0xbd, 0xa8, 0xd2, 0x59, 0x6b, 0x5f, 0x52,
+       0xdb, 0x54, 0xbc, 0x4c, 0xc3, 0xc9, 0xf2, 0x15, 0x80, 0xae, 0x2f, 0xc1,
+       0xc9, 0xf2, 0x09, 0x47, 0xcb, 0x21, 0xb3, 0x5d, 0xc1, 0x71, 0xbb, 0x42,
+       0xf5, 0x0c, 0x63, 0xb8, 0x59, 0x2c, 0xc7, 0x74, 0xa7, 0x1c, 0xc7, 0xa9,
+       0xb8, 0x9d, 0x86, 0x9f, 0xe5, 0x6d, 0xe8, 0x67, 0x14, 0x67, 0x14, 0x43,
+       0x70, 0x1b, 0xd9, 0x97, 0x21, 0x2b, 0xb8, 0x0e, 0x4c, 0xa3, 0xef, 0xf6,
+       0x18, 0x6c, 0x23, 0xfd, 0x0e, 0x37, 0xf0, 0x38, 0x67, 0xe8, 0xa5, 0xf7,
+       0x7b, 0x7f, 0x41, 0xdf, 0x1b, 0x0e, 0x30, 0x07, 0xb9, 0x9f, 0xf6, 0xfe,
+       0xb3, 0xdc, 0x4f, 0xb7, 0x63, 0x5c, 0xc3, 0xe3, 0xa1, 0xe8, 0xa7, 0x02,
+       0xa7, 0xea, 0x17, 0xdf, 0x9b, 0xb6, 0x47, 0x98, 0x62, 0x84, 0x83, 0x0e,
+       0xaa, 0xfe, 0xb9, 0x56, 0x01, 0x6e, 0x37, 0xda, 0xd5, 0xef, 0xfa, 0xea,
+       0x07, 0x84, 0x5e, 0x27, 0x70, 0xa2, 0x1f, 0x49, 0xc9, 0x38, 0x51, 0x40,
+       0x8e, 0x4f, 0xd7, 0xbe, 0x17, 0x0c, 0x0b, 0xff, 0x64, 0xf8, 0x5d, 0x5f,
+       0x07, 0x8c, 0xf0, 0xef, 0x01, 0x3b, 0x5a, 0x99, 0x33, 0x86, 0xcf, 0x53,
+       0x71, 0xa3, 0x54, 0xbc, 0xe8, 0x59, 0xf5, 0x3b, 0xc0, 0x09, 0x71, 0x23,
+       0xe5, 0xeb, 0x7d, 0xef, 0xb7, 0xbd, 0x6e, 0xec, 0x7b, 0x3f, 0x8e, 0x3f,
+       0xef, 0xf3, 0x08, 0xbb, 0xd0, 0xe8, 0x67, 0x8c, 0xd6, 0xb7, 0x99, 0x7c,
+       0x6d, 0xfc, 0xbb, 0xdf, 0xa3, 0xcc, 0x61, 0xf4, 0xfd, 0xe8, 0x6e, 0x55,
+       0xee, 0x57, 0xa8, 0xf8, 0xed, 0xab, 0x56, 0x21, 0x0f, 0xaf, 0x7e, 0x8b,
+       0x85, 0x29, 0x9e, 0x5b, 0x01, 0x02, 0xa7, 0x7d, 0xf5, 0x68, 0x0b, 0xc7,
+       0x6f, 0x5f, 0xad, 0x62, 0x4e, 0x13, 0xdd, 0x53, 0xc5, 0x6b, 0x97, 0xab,
+       0xf4, 0xb8, 0x3b, 0x81, 0xd7, 0x3e, 0x4f, 0x78, 0xed, 0xf7, 0xd0, 0x9d,
+       0x10, 0x4e, 0xbb, 0x42, 0xe5, 0x3f, 0x40, 0x98, 0x9f, 0xab, 0x61, 0x77,
+       0x7a, 0x8c, 0xe2, 0x8d, 0x67, 0x2c, 0xfd, 0x05, 0xa4, 0x8f, 0xda, 0xf7,
+       0x46, 0x5e, 0x15, 0x47, 0x4d, 0x4f, 0x83, 0x4e, 0x23, 0xfd, 0xec, 0xa9,
+       0x73, 0x79, 0xeb, 0x6a, 0x68, 0xdc, 0x84, 0xf1, 0xce, 0x2b, 0x75, 0x06,
+       0xf8, 0xce, 0x55, 0x8f, 0x58, 0xf7, 0x97, 0x75, 0x18, 0xa7, 0xcf, 0x07,
+       0xa3, 0x38, 0x7d, 0x7f, 0xdd, 0x74, 0x5d, 0x9c, 0xce, 0xfb, 0xa9, 0x71,
+       0xfa, 0x9f, 0x0a, 0xaf, 0xf5, 0xd0, 0x3d, 0x8d, 0xcf, 0xff, 0xdf, 0x93,
+       0xc4, 0xed, 0x1e, 0xaf, 0x9d, 0xdc, 0xb8, 0x4d, 0x75, 0x06, 0xf1, 0xdf,
+       0x0e, 0x15, 0x3f, 0x49, 0xa5, 0x6f, 0x66, 0xbd, 0x66, 0x87, 0x67, 0x38,
+       0xb8, 0x3c, 0x8d, 0x9d, 0x1f, 0x44, 0x3d, 0x57, 0xc5, 0xbd, 0x86, 0x54,
+       0x3f, 0x17, 0x62, 0xf2, 0x6f, 0xef, 0xe7, 0xf5, 0x2f, 0x0b, 0xaf, 0x7f,
+       0x69, 0x76, 0x26, 0x34, 0x45, 0xac, 0xff, 0x81, 0x6a, 0x5f, 0xb4, 0xf6,
+       0xa6, 0xda, 0x86, 0x2c, 0xc6, 0x38, 0x0d, 0xab, 0x17, 0x7e, 0xea, 0xdb,
+       0x85, 0xca, 0xfb, 0xc4, 0xc7, 0xf2, 0xd7, 0xf4, 0xb8, 0xd9, 0x82, 0x7e,
+       0x3d, 0x6e, 0x76, 0x6f, 0x24, 0x47, 0xd7, 0x5f, 0x18, 0xbb, 0x4b, 0x37,
+       0xbe, 0xfa, 0xd4, 0x6c, 0xdd, 0xfb, 0x9a, 0xf8, 0x3d, 0xba, 0xf7, 0xf7,
+       0x9d, 0xaf, 0xd2, 0xf5, 0x97, 0x0e, 0x7f, 0x4b, 0x37, 0xfe, 0xfe, 0x4f,
+       0xdc, 0xba, 0xfe, 0x77, 0x46, 0xf4, 0xb8, 0xd9, 0x03, 0xb7, 0xf4, 0xb8,
+       0x99, 0x26, 0xdf, 0x2e, 0x94, 0x88, 0xe4, 0x79, 0x1e, 0xdb, 0x0f, 0x74,
+       0xe3, 0x8a, 0x5a, 0xf5, 0xf7, 0x2a, 0xee, 0xd4, 0xdf, 0x6b, 0x56, 0x97,
+       0xfe, 0x5e, 0xda, 0xba, 0x25, 0x41, 0xfd, 0xfd, 0xe6, 0x84, 0xf4, 0xf7,
+       0xcb, 0x21, 0x5c, 0xbf, 0xe2, 0x7f, 0x8f, 0xeb, 0xff, 0x4d, 0xad, 0xcc,
+       0xe9, 0x7f, 0x2c, 0x3a, 0xc7, 0x4e, 0xf3, 0x76, 0x79, 0x4b, 0xed, 0x14,
+       0xc7, 0x4c, 0x2f, 0x14, 0xf2, 0xaa, 0x8d, 0xfb, 0x1f, 0xac, 0x27, 0xe8,
+       0xd9, 0x70, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 csem_int_table_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe3, 0x14,
+       0x60, 0x60, 0xf8, 0x51, 0x0f, 0xc1, 0xd3, 0xf9, 0x19, 0x18, 0x36, 0xf3,
+       0x23, 0xf8, 0xf4, 0xc0, 0xc7, 0x98, 0x19, 0x18, 0x8e, 0x83, 0x30, 0x23,
+       0x03, 0xc3, 0x3e, 0x20, 0xde, 0x0a, 0xc4, 0x6b, 0x80, 0xf8, 0x3d, 0x03,
+       0x03, 0xc3, 0x52, 0x20, 0x3d, 0x07, 0x88, 0x27, 0x03, 0x71, 0x17, 0x10,
+       0xbf, 0x04, 0x8a, 0xd5, 0xb1, 0x62, 0x37, 0x87, 0x85, 0x8d, 0x81, 0x81,
+       0x0d, 0x88, 0x4f, 0x02, 0xcd, 0x3a, 0xc5, 0x4c, 0xbc, 0xfd, 0x8a, 0x7c,
+       0x08, 0xf6, 0x21, 0x5e, 0x06, 0x86, 0xb5, 0x40, 0x7c, 0x94, 0x97, 0xbe,
+       0x61, 0x30, 0xd8, 0xf0, 0x0c, 0x41, 0xfa, 0xd9, 0xf5, 0x0c, 0x6a, 0xd7,
+       0x6e, 0xd1, 0x81, 0xf7, 0x37, 0x08, 0xb3, 0x8a, 0x33, 0x30, 0x30, 0x4a,
+       0x20, 0xf8, 0xfd, 0x12, 0xa8, 0xf2, 0x6c, 0xe2, 0x08, 0x76, 0x96, 0x0c,
+       0x65, 0x76, 0x95, 0x01, 0xf5, 0x03, 0x00, 0x29, 0x51, 0x28, 0x15, 0x80,
+       0x03, 0x00, 0x00, 0x00
+};
+
+static const u8 csem_pram_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
+       0x09, 0x78, 0x54, 0x45, 0xb6, 0x70, 0xdd, 0xee, 0x7b, 0x7b, 0x49, 0xba,
+       0x3b, 0x9d, 0x90, 0x95, 0x25, 0x74, 0x80, 0x20, 0x2a, 0x4b, 0xcb, 0x12,
+       0x01, 0x11, 0x3b, 0x21, 0x89, 0x01, 0x03, 0x06, 0x44, 0x09, 0x28, 0xd2,
+       0x6c, 0x21, 0x84, 0x24, 0x9d, 0x01, 0x66, 0x1e, 0x3e, 0xfd, 0xff, 0x6e,
+       0x08, 0x42, 0xc4, 0xd1, 0x89, 0x8a, 0x1a, 0xfc, 0x19, 0x5f, 0x83, 0xe0,
+       0x04, 0x07, 0x9d, 0xe0, 0xa0, 0x13, 0x9d, 0xc0, 0x34, 0x8b, 0x88, 0x33,
+       0xe8, 0x04, 0xc7, 0x05, 0x97, 0x79, 0x5f, 0x40, 0x1e, 0x20, 0x42, 0x12,
+       0xa3, 0x38, 0xe8, 0xf3, 0xc9, 0xab, 0x73, 0xaa, 0x6e, 0xba, 0xeb, 0x76,
+       0x37, 0x69, 0xb7, 0xff, 0xf9, 0x7f, 0xff, 0x84, 0x0f, 0x8a, 0xba, 0x55,
+       0xf7, 0xd4, 0xa9, 0xb3, 0xd5, 0xa9, 0x53, 0x75, 0x4f, 0x14, 0x92, 0x42,
+       0x92, 0xfa, 0x13, 0x72, 0x09, 0x7e, 0x6e, 0x20, 0xe4, 0x55, 0x85, 0x10,
+       0xfa, 0xa8, 0xbb, 0xec, 0x90, 0x3a, 0x87, 0xcb, 0x03, 0x83, 0xed, 0x6b,
+       0xbd, 0x2e, 0xe2, 0x32, 0x12, 0xf2, 0x80, 0xd7, 0x84, 0xe5, 0x7a, 0x6f,
+       0x3a, 0x71, 0x5d, 0x41, 0x9f, 0x8f, 0xd6, 0x15, 0xf9, 0x2d, 0x84, 0xdc,
+       0xef, 0xb5, 0xe3, 0xf3, 0xc7, 0xbd, 0x25, 0x58, 0x3e, 0xea, 0x2d, 0xc5,
+       0xf2, 0x11, 0xaf, 0x1b, 0xfb, 0x3d, 0xe4, 0x2d, 0xc7, 0xf2, 0x57, 0xde,
+       0x1a, 0x2c, 0xef, 0xf5, 0x16, 0x61, 0x7b, 0x9d, 0x77, 0x15, 0xd6, 0x6f,
+       0x54, 0x16, 0xa4, 0xc1, 0xb8, 0x84, 0xb8, 0x4c, 0x59, 0xc9, 0x84, 0x78,
+       0x5e, 0x1e, 0x38, 0x72, 0x03, 0xad, 0xad, 0xcf, 0x1c, 0x9f, 0x20, 0x8f,
+       0xa6, 0xf5, 0xbf, 0xea, 0x89, 0x3e, 0x8b, 0xbe, 0x37, 0x5a, 0x2e, 0xf2,
+       0x0f, 0xa5, 0x0d, 0x72, 0x49, 0x51, 0xd6, 0xe8, 0x60, 0x3f, 0x15, 0xcf,
+       0x1b, 0x95, 0xbc, 0xbe, 0x00, 0xe7, 0xf1, 0xb1, 0x3a, 0xd6, 0xcf, 0x54,
+       0xf3, 0x5a, 0x76, 0xe4, 0x7e, 0x59, 0x64, 0x0c, 0xc5, 0x73, 0xac, 0x8c,
+       0xf8, 0x13, 0x4b, 0xc9, 0xe4, 0xec, 0xe4, 0x88, 0xfd, 0x06, 0x03, 0xbc,
+       0x47, 0x86, 0xb2, 0x79, 0x12, 0xbb, 0xf3, 0xb5, 0x41, 0x91, 0xe1, 0x5d,
+       0x0d, 0xf0, 0x1e, 0x1a, 0xca, 0xf1, 0x4b, 0xb6, 0x4f, 0x1e, 0x14, 0x19,
+       0x9e, 0x13, 0xfa, 0xfd, 0xca, 0xc9, 0xe1, 0xa5, 0x77, 0x1e, 0x1e, 0x18,
+       0xb9, 0xdf, 0x18, 0xe8, 0x57, 0xe7, 0xe4, 0xf0, 0xfa, 0xfa, 0x4c, 0x03,
+       0x22, 0x8f, 0x3b, 0x1e, 0xfa, 0xc5, 0xc0, 0x27, 0x8a, 0x13, 0x21, 0xbe,
+       0x16, 0xa3, 0x3f, 0x3b, 0xeb, 0xfb, 0xf3, 0x8b, 0xb8, 0xe8, 0x5f, 0x8a,
+       0x4f, 0xc7, 0x5e, 0xf3, 0xd6, 0x0d, 0x12, 0xf2, 0x6f, 0x1a, 0xd0, 0x69,
+       0xad, 0x7d, 0xf9, 0x99, 0x2d, 0x74, 0x9c, 0xf6, 0x96, 0x61, 0x4e, 0xbd,
+       0x83, 0x90, 0xcf, 0x5c, 0xce, 0x04, 0xbb, 0x25, 0x26, 0xbe, 0xdd, 0x02,
+       0xf3, 0x88, 0x81, 0x6f, 0xa5, 0x30, 0x4e, 0x0c, 0x7c, 0x9b, 0x1b, 0x23,
+       0xdf, 0x16, 0x40, 0xbf, 0x18, 0xf8, 0xb6, 0x04, 0xfa, 0xc5, 0xc0, 0xb7,
+       0xca, 0x18, 0xf9, 0xf6, 0xb3, 0x9f, 0x08, 0xdf, 0xee, 0x05, 0x3c, 0xbe,
+       0x07, 0xdf, 0x36, 0xc4, 0xa8, 0x6f, 0xbf, 0x8a, 0x91, 0x6f, 0x1b, 0x63,
+       0xe4, 0xdb, 0xa6, 0x18, 0xf5, 0xed, 0xc9, 0x18, 0xf9, 0xf6, 0x54, 0x28,
+       0xdf, 0xd4, 0xe7, 0x6a, 0xb9, 0x83, 0x48, 0x68, 0x17, 0x6f, 0x54, 0x4a,
+       0x76, 0x40, 0x3f, 0x4f, 0x66, 0x9b, 0x6d, 0x40, 0xd6, 0x4f, 0x82, 0x7f,
+       0x7b, 0xbe, 0xa7, 0xde, 0xed, 0x8f, 0x91, 0x7f, 0xaf, 0xc6, 0xc8, 0xbf,
+       0x23, 0x40, 0x9f, 0x18, 0xf8, 0x77, 0x34, 0x46, 0xfe, 0xbd, 0x13, 0x23,
+       0xff, 0x3e, 0x88, 0x51, 0xef, 0xda, 0x70, 0x9d, 0xb1, 0xc8, 0x5f, 0xb5,
+       0x0d, 0x21, 0xf8, 0x73, 0x69, 0x00, 0xfc, 0x6b, 0xb1, 0x9f, 0xba, 0x9a,
+       0xd7, 0xf5, 0x80, 0x77, 0x12, 0x21, 0x19, 0xe1, 0x72, 0xa0, 0x96, 0x94,
+       0xa3, 0x28, 0x0f, 0x32, 0x71, 0xb7, 0xb3, 0x75, 0xab, 0xe0, 0x9b, 0x4b,
+       0x39, 0x84, 0xac, 0x30, 0xd1, 0xff, 0xd2, 0xf7, 0x7d, 0x79, 0x24, 0xa0,
+       0xa7, 0xe3, 0xfb, 0x6c, 0xc4, 0x5f, 0x2b, 0x09, 0xfd, 0x3f, 0x07, 0x3c,
+       0x09, 0xc9, 0xff, 0xe6, 0x52, 0xaa, 0xd0, 0xdf, 0xa7, 0x8b, 0xd8, 0x9f,
+       0xe8, 0xa0, 0xfd, 0x61, 0x90, 0x2b, 0xca, 0xff, 0xcd, 0xde, 0x21, 0x58,
+       0xd6, 0x73, 0x39, 0xda, 0x5c, 0xa4, 0x43, 0x79, 0xf0, 0x25, 0x1b, 0x50,
+       0xbe, 0x9e, 0xf0, 0x3a, 0xb1, 0xbd, 0xc1, 0x3b, 0x16, 0xcb, 0xc7, 0xb8,
+       0x5c, 0x6e, 0xe4, 0x72, 0xf4, 0x00, 0xc8, 0xdd, 0x15, 0x20, 0x87, 0xa5,
+       0x5c, 0xae, 0x98, 0xdc, 0x11, 0x52, 0xe2, 0x28, 0xa7, 0x74, 0xed, 0xd8,
+       0x13, 0x4f, 0x36, 0x38, 0x50, 0xae, 0xcc, 0x12, 0xe0, 0x29, 0x33, 0x79,
+       0xbb, 0x77, 0xcf, 0x95, 0x5b, 0x37, 0x50, 0xf8, 0x9b, 0x6b, 0x74, 0x57,
+       0x6e, 0x0b, 0x91, 0xb3, 0x27, 0x8a, 0x54, 0xf9, 0xa2, 0x92, 0x99, 0x1c,
+       0xec, 0xf7, 0x44, 0xf9, 0x09, 0xdb, 0x82, 0xa1, 0x48, 0x6f, 0x1b, 0xc0,
+       0x69, 0x28, 0xd6, 0xa9, 0xfd, 0x7c, 0xa1, 0xfd, 0x1a, 0xdc, 0xdd, 0xfd,
+       0x7a, 0x41, 0xbf, 0xc7, 0x8a, 0xb9, 0x7c, 0xc9, 0x24, 0x10, 0x3a, 0xee,
+       0x63, 0xa5, 0xdd, 0xfd, 0xd2, 0x25, 0x4a, 0x97, 0x7b, 0x25, 0x52, 0xda,
+       0x64, 0x09, 0xe7, 0xcb, 0x14, 0x89, 0xe9, 0x29, 0x55, 0x14, 0xe4, 0x87,
+       0xcc, 0xe9, 0xbb, 0x3f, 0xef, 0x2c, 0x69, 0xa3, 0xef, 0xdb, 0xec, 0x23,
+       0xd3, 0x08, 0x2d, 0x9f, 0x04, 0xfd, 0x44, 0xfd, 0x73, 0x60, 0xa9, 0xbe,
+       0x5f, 0x4f, 0xe9, 0xec, 0xa6, 0xf4, 0xc8, 0x34, 0x92, 0x9a, 0x26, 0xc0,
+       0x97, 0xb4, 0x4a, 0x0a, 0xc5, 0x57, 0x1e, 0xeb, 0x48, 0x04, 0x39, 0x7a,
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+       0x07, 0x5f, 0xcc, 0x98, 0x1f, 0x82, 0xdf, 0x7d, 0x83, 0xe7, 0x60, 0x5d,
+       0xc5, 0xc7, 0x7c, 0x45, 0x25, 0xd6, 0xfb, 0xaf, 0xea, 0x4d, 0x3d, 0x31,
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+       0xe0, 0xcc, 0xd5, 0xc2, 0xd9, 0xc6, 0xe1, 0x90, 0x50, 0x3b, 0x1d, 0x06,
+       0x87, 0xdc, 0xa1, 0x9d, 0xc7, 0x6f, 0xf9, 0x7b, 0x01, 0x5d, 0xc8, 0xf8,
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+       0x8e, 0xbf, 0x1b, 0xec, 0x18, 0xcc, 0x43, 0x77, 0xd9, 0xf1, 0x1d, 0x1a,
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+       0xe1, 0x94, 0x6a, 0xe7, 0xf1, 0xba, 0xca, 0x57, 0x49, 0x58, 0xbf, 0x28,
+       0x3d, 0x86, 0x05, 0xdf, 0xeb, 0xc8, 0xeb, 0x3c, 0x85, 0x7e, 0xd0, 0x8b,
+       0x8a, 0x63, 0x3b, 0x6d, 0x97, 0xfe, 0x64, 0x0d, 0xdc, 0x40, 0xfb, 0x1f,
+       0xd9, 0x22, 0xf9, 0x8d, 0xb4, 0x1e, 0xd8, 0x1b, 0x8f, 0xeb, 0xc7, 0xf9,
+       0x6d, 0xd3, 0xb1, 0xbe, 0xef, 0x1a, 0x23, 0xae, 0x13, 0xe7, 0x9d, 0x93,
+       0xfd, 0x46, 0x6a, 0x4f, 0x26, 0xbd, 0xf0, 0xb6, 0x0d, 0xec, 0x4b, 0xd5,
+       0x0b, 0x7a, 0x19, 0xea, 0xba, 0xbd, 0x1f, 0xdb, 0xda, 0x28, 0x5e, 0x1e,
+       0x63, 0xeb, 0x83, 0xd7, 0xd1, 0xe7, 0x9d, 0x2f, 0xe8, 0xc9, 0x56, 0x94,
+       0xc6, 0x42, 0x1d, 0xd0, 0xfd, 0x14, 0x97, 0x4d, 0xb2, 0x8a, 0xd5, 0xcb,
+       0xcc, 0xac, 0x5a, 0xb5, 0x65, 0xdf, 0x9d, 0x00, 0xb7, 0xbc, 0xd9, 0x48,
+       0xcc, 0x14, 0x4e, 0xd5, 0x4b, 0x4b, 0xa6, 0x5d, 0x47, 0xeb, 0x4b, 0x0e,
+       0x2b, 0x04, 0xba, 0x54, 0x6d, 0x5f, 0x6d, 0xe8, 0x4d, 0xeb, 0x4b, 0xfd,
+       0x52, 0x13, 0xd4, 0x3b, 0xf2, 0x48, 0x39, 0xe8, 0xd3, 0x9a, 0xbd, 0xff,
+       0xd9, 0x0e, 0xeb, 0xd1, 0xf9, 0xdd, 0x4a, 0x36, 0x8c, 0x7f, 0x96, 0xae,
+       0x13, 0x0e, 0x6a, 0x8f, 0x8f, 0x58, 0x5b, 0x53, 0x67, 0x52, 0x3c, 0x2a,
+       0xfc, 0xbb, 0x0a, 0xe1, 0xbd, 0x8a, 0x9d, 0x92, 0x93, 0x5a, 0x38, 0x8a,
+       0xef, 0xf6, 0x43, 0x19, 0x80, 0xef, 0x0e, 0xc9, 0x69, 0xa4, 0xf4, 0x5e,
+       0xd6, 0x18, 0x4f, 0x1c, 0xaa, 0xbd, 0xa3, 0x7f, 0x4f, 0xed, 0xd6, 0xe3,
+       0xfc, 0x97, 0xd3, 0xf9, 0x13, 0x0a, 0x6f, 0x09, 0xa9, 0x2f, 0x04, 0x7a,
+       0x56, 0x01, 0x71, 0x60, 0x7c, 0xa7, 0xd1, 0x6f, 0x96, 0x82, 0xfa, 0x76,
+       0xd6, 0x7b, 0x18, 0xc7, 0x53, 0xeb, 0x55, 0x3b, 0xe8, 0x78, 0xf4, 0xfd,
+       0xea, 0xe7, 0x24, 0x27, 0x4c, 0xb5, 0x5a, 0x47, 0xdc, 0x80, 0x67, 0xfb,
+       0x4b, 0xe6, 0xd2, 0xa7, 0x2c, 0x30, 0xcf, 0xd5, 0x86, 0xc1, 0x56, 0x98,
+       0xdf, 0x7a, 0x03, 0xf4, 0x5b, 0xe2, 0x9f, 0xff, 0xa2, 0xd9, 0x01, 0x78,
+       0x6e, 0x31, 0x14, 0x02, 0xbe, 0x9b, 0xb7, 0x18, 0xca, 0x86, 0x02, 0xfd,
+       0xc8, 0xbc, 0x92, 0xa1, 0x80, 0xdf, 0x5f, 0x44, 0xfc, 0x1a, 0xf4, 0x2e,
+       0x98, 0xef, 0xf2, 0x6b, 0x8c, 0x5b, 0xf5, 0xc0, 0x4f, 0x4b, 0x60, 0xd0,
+       0x0c, 0x6b, 0xb8, 0x9d, 0x3d, 0x4b, 0xd7, 0x2b, 0x47, 0xc8, 0xfa, 0x59,
+       0x41, 0x98, 0xdd, 0x27, 0xb2, 0xdf, 0x30, 0x7d, 0x58, 0xf0, 0xf9, 0x4b,
+       0xfa, 0x44, 0x94, 0x83, 0x65, 0x8d, 0x7a, 0xe2, 0x08, 0xb5, 0x1b, 0x5c,
+       0x3e, 0x7c, 0x47, 0x09, 0xf3, 0x63, 0xf6, 0x58, 0xfd, 0xdb, 0xb3, 0x82,
+       0x7c, 0x5c, 0x6e, 0xe7, 0xf2, 0xca, 0xf9, 0xb8, 0x3c, 0x91, 0xf3, 0x55,
+       0xee, 0xcc, 0x99, 0x31, 0x2c, 0x1c, 0x9f, 0x07, 0x81, 0x2f, 0x46, 0xe6,
+       0x1f, 0x41, 0xf9, 0x30, 0x5d, 0x37, 0x1d, 0xe8, 0xff, 0x38, 0x90, 0x7e,
+       0x8f, 0x51, 0xff, 0xc9, 0x81, 0xfe, 0x91, 0x13, 0x9f, 0x3f, 0x41, 0xfd,
+       0x24, 0x28, 0x37, 0x53, 0x3f, 0x09, 0xca, 0x27, 0xa9, 0x9f, 0x04, 0xa5,
+       0x9f, 0xfa, 0x49, 0xd0, 0x6f, 0x2b, 0xf5, 0x93, 0xa0, 0xdc, 0x46, 0xfd,
+       0x24, 0x78, 0xfe, 0x34, 0xf5, 0xcf, 0xa1, 0x6c, 0xa4, 0xfe, 0x39, 0x3c,
+       0x7f, 0x86, 0xfa, 0xe5, 0x50, 0xee, 0xf4, 0xfa, 0xf0, 0xf9, 0x73, 0xde,
+       0x3a, 0x2c, 0x9b, 0xbc, 0xf5, 0x58, 0x3e, 0xef, 0x6d, 0xc0, 0x72, 0xb7,
+       0xd7, 0x8f, 0xfd, 0x5e, 0xf4, 0x36, 0x62, 0xd9, 0xec, 0x6d, 0xc2, 0xe7,
+       0x2f, 0x7b, 0x9b, 0xb1, 0x6c, 0xf1, 0x06, 0xb0, 0xdc, 0x0b, 0x7c, 0xa6,
+       0x65, 0xc0, 0xdb, 0x8a, 0xe5, 0x7e, 0xef, 0x31, 0x2c, 0x0f, 0x7a, 0xdb,
+       0xf0, 0xbd, 0x43, 0xde, 0x33, 0x58, 0xfe, 0x92, 0xd3, 0xdd, 0x36, 0x81,
+       0xe4, 0xca, 0x54, 0x5e, 0x6c, 0x2e, 0x62, 0x07, 0x36, 0x25, 0x15, 0xbb,
+       0x72, 0xc1, 0x5f, 0x49, 0x2a, 0x61, 0xf5, 0xd4, 0x3b, 0x7c, 0xb9, 0x06,
+       0x5a, 0x4f, 0x75, 0xd3, 0x3a, 0xa5, 0x63, 0xef, 0xca, 0x40, 0xae, 0x91,
+       0xd6, 0x7b, 0xd7, 0xb0, 0xf6, 0xcc, 0x7b, 0x48, 0x9e, 0x89, 0xd6, 0x33,
+       0x7d, 0xac, 0x7d, 0xc0, 0x2f, 0x5d, 0x79, 0x66, 0x5a, 0x1f, 0x50, 0xcf,
+       0xda, 0x07, 0x6f, 0xf6, 0xe5, 0xc5, 0xd1, 0xfa, 0x60, 0x3f, 0x6b, 0xbf,
+       0x6a, 0x67, 0x20, 0x2f, 0x9e, 0xd6, 0xaf, 0x6a, 0x62, 0xed, 0xc3, 0x5b,
+       0xc8, 0x24, 0x0b, 0xad, 0x0f, 0x0f, 0xb0, 0xfa, 0xc8, 0x23, 0xae, 0x49,
+       0x56, 0x5a, 0x1f, 0xd9, 0xca, 0xea, 0x39, 0x1f, 0xfa, 0x26, 0xd9, 0x68,
+       0x3d, 0xa7, 0x8d, 0xbd, 0x3f, 0xfe, 0x5c, 0x60, 0x52, 0x02, 0xad, 0x8f,
+       0xef, 0x64, 0xed, 0x13, 0xbf, 0x26, 0xf9, 0x76, 0x5a, 0x9f, 0x48, 0x24,
+       0xac, 0xe7, 0x59, 0x72, 0xf3, 0x13, 0x69, 0x3d, 0xcf, 0xce, 0xea, 0x85,
+       0x7d, 0xe7, 0xcb, 0x8e, 0x08, 0xeb, 0xfb, 0x5e, 0xa5, 0x6d, 0x21, 0x98,
+       0xb4, 0x9f, 0xeb, 0x72, 0x72, 0x65, 0xea, 0x27, 0xec, 0x35, 0xb4, 0xad,
+       0x00, 0x93, 0xbb, 0x5e, 0x77, 0x43, 0xae, 0x3c, 0x8e, 0xd2, 0x4f, 0x21,
+       0x8b, 0xa0, 0x7d, 0x93, 0xae, 0x88, 0xd5, 0x0d, 0x64, 0x25, 0xb4, 0xff,
+       0x56, 0x37, 0x1d, 0xeb, 0xfb, 0x15, 0x07, 0xb6, 0xef, 0xd1, 0xcd, 0x61,
+       0x75, 0x83, 0x03, 0xdb, 0xff, 0xaa, 0x5b, 0x88, 0xf5, 0x83, 0x8a, 0x0b,
+       0xdb, 0x8f, 0xeb, 0x2a, 0x59, 0xdd, 0xe0, 0xc2, 0xf6, 0xcf, 0x74, 0x3f,
+       0xc7, 0xf1, 0x0e, 0x29, 0x6e, 0x6c, 0x57, 0xf4, 0xff, 0x9b, 0xd5, 0x0d,
+       0x6e, 0x6c, 0x7f, 0x58, 0x5e, 0x9f, 0x9b, 0x4f, 0xfb, 0x57, 0xea, 0xdd,
+       0x1e, 0x1d, 0x95, 0xeb, 0x5a, 0xc9, 0x5d, 0x4e, 0x06, 0x82, 0xbc, 0x36,
+       0xa5, 0x83, 0x3d, 0x5c, 0xc7, 0xfd, 0xd6, 0x59, 0x3a, 0x07, 0xca, 0xfd,
+       0xba, 0x0c, 0x03, 0xea, 0xd9, 0xde, 0xff, 0xca, 0x79, 0x0a, 0xf5, 0x0c,
+       0x7e, 0x92, 0xa1, 0x5e, 0xf6, 0x34, 0xf8, 0xbd, 0x14, 0xce, 0x2a, 0x84,
+       0xa3, 0x50, 0x38, 0xfa, 0x9e, 0xe1, 0x4c, 0xfc, 0x66, 0xac, 0x00, 0x67,
+       0xe2, 0x37, 0xe5, 0x2a, 0x9c, 0xd5, 0x08, 0xc7, 0x1c, 0x1b, 0x9c, 0xbd,
+       0xdf, 0x8c, 0x17, 0xf1, 0xf9, 0xa6, 0x42, 0x85, 0xb3, 0x41, 0x47, 0xed,
+       0x7d, 0xad, 0x35, 0xb6, 0x79, 0x4d, 0xbc, 0x34, 0x41, 0xc4, 0xe7, 0x52,
+       0xa5, 0x0a, 0xe7, 0x11, 0xc4, 0x27, 0x31, 0x36, 0x7c, 0x02, 0xca, 0xb5,
+       0x02, 0x9c, 0x80, 0xb2, 0x44, 0x85, 0xb3, 0x19, 0xe1, 0xa4, 0xc4, 0x86,
+       0x8f, 0xcb, 0x30, 0x4e, 0x80, 0xe3, 0x32, 0x2c, 0x55, 0xe1, 0x6c, 0x47,
+       0x38, 0x19, 0xb1, 0xc1, 0x09, 0x18, 0xae, 0x13, 0xf1, 0x31, 0x2c, 0x53,
+       0xe1, 0x3c, 0x87, 0xf4, 0xe9, 0x17, 0xdb, 0xbc, 0x5c, 0xc6, 0xeb, 0x45,
+       0x7c, 0x8c, 0x55, 0x2a, 0x9c, 0x3f, 0x20, 0x3e, 0x59, 0xb1, 0xc1, 0xd9,
+       0x6f, 0x15, 0xe9, 0xb3, 0xdf, 0xda, 0x4d, 0x9f, 0x00, 0xc2, 0xc9, 0x8e,
+       0x6d, 0x5e, 0x79, 0x36, 0x91, 0x3e, 0x79, 0xb6, 0x6e, 0xfa, 0xbc, 0x86,
+       0x70, 0xae, 0x8c, 0x0d, 0xce, 0x7e, 0x9b, 0x48, 0x9f, 0xfd, 0xb6, 0x6e,
+       0xfa, 0xbc, 0x89, 0x70, 0x86, 0xc5, 0x36, 0xaf, 0xbc, 0x04, 0x91, 0x3e,
+       0x79, 0x09, 0xdd, 0xf4, 0xf9, 0x00, 0xe1, 0x5c, 0x13, 0x1b, 0x3e, 0x07,
+       0x53, 0x44, 0xfa, 0x1c, 0x4c, 0xe9, 0xa6, 0xcf, 0x49, 0x84, 0x33, 0x26,
+       0x36, 0x7c, 0xf2, 0x53, 0x45, 0xfa, 0xe4, 0xa7, 0x76, 0xd3, 0xe7, 0x3c,
+       0xc2, 0x19, 0x17, 0x1b, 0x9c, 0x83, 0xa9, 0x22, 0x7d, 0x0e, 0xa6, 0x76,
+       0xd3, 0xe7, 0x0b, 0x84, 0x73, 0x7d, 0x6c, 0xf3, 0xca, 0x4f, 0x13, 0xe9,
+       0x93, 0x9f, 0xd6, 0x4d, 0x9f, 0x4b, 0x08, 0x27, 0xd7, 0xdd, 0x88, 0xf8,
+       0x10, 0x0a, 0xc7, 0x1a, 0x1d, 0xce, 0xa1, 0x7e, 0x22, 0x7d, 0x0e, 0xf5,
+       0xeb, 0xa6, 0x8f, 0x49, 0x0f, 0x70, 0x0a, 0x28, 0x9c, 0x81, 0x3d, 0xc3,
+       0x29, 0xcc, 0x14, 0xe9, 0x53, 0x98, 0xd9, 0x4d, 0x9f, 0x44, 0x3d, 0xe8,
+       0xc5, 0xe4, 0xd8, 0xe0, 0x1c, 0xca, 0x14, 0xe9, 0x73, 0x28, 0xb3, 0x9b,
+       0x3e, 0xbd, 0x11, 0x9f, 0xa9, 0xb1, 0xcd, 0xab, 0xb0, 0xbf, 0x48, 0x9f,
+       0xc2, 0xfe, 0x8c, 0x3e, 0x1e, 0x63, 0xe7, 0x24, 0x3b, 0xf8, 0x8d, 0x89,
+       0xc4, 0xb9, 0x95, 0xbe, 0x32, 0x29, 0xf9, 0x67, 0x07, 0x61, 0xdd, 0x51,
+       0x2c, 0xc4, 0x09, 0x60, 0x8f, 0x48, 0x81, 0x6d, 0x00, 0x9f, 0xae, 0xad,
+       0xe8, 0x97, 0xca, 0x4e, 0xd5, 0x0f, 0x72, 0x12, 0xf0, 0x73, 0x8b, 0x6d,
+       0x0e, 0x27, 0xc4, 0x03, 0xf4, 0xaa, 0xbf, 0x43, 0x5a, 0x71, 0x3f, 0x62,
+       0xd9, 0x99, 0x28, 0xc4, 0x9b, 0x5e, 0xd2, 0xe7, 0x0d, 0x07, 0x7c, 0xad,
+       0xd4, 0x2b, 0x0c, 0xf5, 0x7b, 0x12, 0xc6, 0xc6, 0x09, 0xfe, 0x56, 0xa2,
+       0x2b, 0x49, 0xa8, 0xf7, 0x2a, 0xea, 0x2d, 0xf4, 0x4f, 0x29, 0x19, 0x20,
+       0xb4, 0xa7, 0x95, 0x5e, 0x25, 0xb4, 0x67, 0xb8, 0x47, 0x0a, 0xf5, 0x3e,
+       0xe5, 0xe3, 0x85, 0xfe, 0xfd, 0x6a, 0xf2, 0x84, 0x7a, 0xff, 0x55, 0x53,
+       0x84, 0xfe, 0x59, 0xbe, 0x19, 0x42, 0x7d, 0x60, 0xdd, 0x1c, 0xa1, 0x7f,
+       0x76, 0xfd, 0x02, 0xa1, 0xfd, 0x8a, 0x86, 0x0a, 0xa1, 0xfd, 0x4a, 0xff,
+       0x72, 0xa1, 0x7e, 0x75, 0xe3, 0xbf, 0x0a, 0xfd, 0x87, 0x35, 0xad, 0x11,
+       0xda, 0x47, 0x34, 0x6f, 0x10, 0xda, 0xaf, 0x09, 0x3c, 0x2c, 0xd4, 0x47,
+       0x1d, 0x7e, 0x42, 0xe8, 0x3f, 0xa6, 0x75, 0xab, 0xd0, 0x7e, 0xed, 0xb1,
+       0x67, 0x84, 0xf6, 0x71, 0x6d, 0xcf, 0x0b, 0xf5, 0xeb, 0xce, 0xbc, 0x2c,
+       0xf4, 0xbf, 0xbe, 0x73, 0xbf, 0x50, 0xbf, 0xe1, 0xe2, 0x9f, 0x85, 0xfe,
+       0xb9, 0xe4, 0x6f, 0x42, 0x7d, 0x92, 0xe9, 0x03, 0xa1, 0x7f, 0x81, 0xfd,
+       0x23, 0xa1, 0xfd, 0xc6, 0xf4, 0x4f, 0x34, 0x7e, 0xac, 0x18, 0xbf, 0xa8,
+       0xcd, 0x25, 0xcc, 0x9f, 0xcd, 0x30, 0xa0, 0x3f, 0x1b, 0xb0, 0x1a, 0xb0,
+       0x6e, 0xd8, 0x6b, 0x66, 0xfb, 0x1b, 0xa8, 0x27, 0x43, 0x1c, 0xa2, 0x18,
+       0xeb, 0x86, 0xfd, 0x0b, 0x1d, 0xc9, 0x10, 0x0f, 0x00, 0x00, 0xd4, 0x9f,
+       0xc8, 0xed, 0x5d, 0x7e, 0x05, 0xc4, 0xab, 0x7e, 0x31, 0xde, 0x7d, 0x05,
+       0xc4, 0x71, 0x7f, 0x61, 0x70, 0x8f, 0xb0, 0x47, 0xf0, 0x83, 0xda, 0x65,
+       0xf7, 0x3d, 0x7a, 0x8c, 0x27, 0xb6, 0x4a, 0x24, 0x1d, 0x4a, 0x87, 0x0e,
+       0xca, 0x38, 0x3d, 0x8f, 0x27, 0x18, 0x99, 0xfc, 0xae, 0xcf, 0xca, 0x79,
+       0xca, 0x17, 0xa2, 0x07, 0x75, 0xfd, 0xa8, 0x7f, 0x41, 0xeb, 0xeb, 0xf5,
+       0x14, 0x8f, 0x31, 0x41, 0xfd, 0x59, 0xdf, 0xaf, 0x2c, 0x7d, 0x7e, 0xc8,
+       0x38, 0xeb, 0xfa, 0x19, 0x4a, 0xb7, 0x0e, 0x65, 0xcf, 0x17, 0x5a, 0x60,
+       0xbc, 0x92, 0xfb, 0x60, 0x3c, 0x8f, 0xa1, 0x73, 0x30, 0xe0, 0xa5, 0x1d,
+       0xc7, 0x38, 0x60, 0xac, 0x30, 0x8e, 0x29, 0xb3, 0x1c, 0xc7, 0xd9, 0x08,
+       0xe3, 0xa4, 0x04, 0xc7, 0x31, 0x66, 0x96, 0x6b, 0xc6, 0x31, 0x95, 0x6e,
+       0xe5, 0xcf, 0xf9, 0x38, 0x8f, 0x81, 0xde, 0x44, 0x1b, 0x67, 0xfd, 0x80,
+       0xf1, 0xe2, 0x7c, 0x32, 0x2b, 0x70, 0x9c, 0x2d, 0x9a, 0x71, 0xd6, 0x67,
+       0x56, 0x68, 0xc6, 0x89, 0x63, 0xf3, 0xa1, 0xcf, 0xf9, 0x38, 0x4f, 0x5d,
+       0x6e, 0x1c, 0xe3, 0xc0, 0x09, 0xe2, 0x7c, 0xfa, 0x57, 0xe2, 0x38, 0xcf,
+       0x69, 0xe7, 0xd3, 0xbf, 0x52, 0x33, 0x8e, 0x05, 0xc7, 0x81, 0xe7, 0x30,
+       0x0e, 0xe9, 0x4b, 0x77, 0x31, 0x69, 0x94, 0xcf, 0xc6, 0xce, 0x32, 0x94,
+       0x83, 0x3f, 0x99, 0x31, 0x4e, 0x66, 0xe8, 0x53, 0xf1, 0x1b, 0xa8, 0x93,
+       0x0f, 0xcc, 0x24, 0x1b, 0xc6, 0x71, 0xd0, 0x71, 0x69, 0x3f, 0x32, 0x24,
+       0x89, 0x0a, 0x35, 0x21, 0xff, 0xa2, 0x4f, 0x42, 0xfe, 0x7c, 0x11, 0x47,
+       0xf9, 0x1f, 0x12, 0x4f, 0x0b, 0xee, 0xc7, 0x7d, 0xb8, 0xaf, 0x5f, 0xcc,
+       0x51, 0x24, 0x7e, 0x8a, 0x11, 0xdd, 0x27, 0x55, 0x73, 0xd9, 0x5c, 0xb4,
+       0x73, 0x7a, 0xe6, 0x0a, 0x07, 0x2d, 0x9b, 0x0f, 0x0c, 0x7a, 0x04, 0xc6,
+       0xd9, 0x68, 0x75, 0x66, 0xd3, 0x7a, 0x7b, 0xf3, 0x24, 0xc3, 0xc2, 0x08,
+       0xf2, 0xb4, 0xb8, 0x5e, 0x39, 0xd5, 0x16, 0x22, 0xe7, 0xdd, 0xfb, 0xb3,
+       0x3c, 0x32, 0xa4, 0x86, 0x8e, 0xbf, 0x22, 0xce, 0x8e, 0xf8, 0xa8, 0x75,
+       0xb5, 0x4c, 0xd2, 0x89, 0xcf, 0x4f, 0xd0, 0x7d, 0x17, 0xa1, 0xfb, 0x93,
+       0x0f, 0xe9, 0x3e, 0x85, 0xd0, 0xfd, 0xca, 0x47, 0x0a, 0xdb, 0x67, 0xfe,
+       0x3b, 0xdd, 0x9f, 0x41, 0xbd, 0x8d, 0xee, 0xcf, 0xa0, 0x9d, 0x90, 0xd5,
+       0xf8, 0xde, 0x09, 0x1e, 0x67, 0x3e, 0xf1, 0x4b, 0xc9, 0x0f, 0xf4, 0xfe,
+       0xe2, 0xae, 0x9f, 0x29, 0xb8, 0x4e, 0xf8, 0xc8, 0x5b, 0xe9, 0xa9, 0x10,
+       0x4d, 0x60, 0x3f, 0xf3, 0x56, 0xc5, 0x53, 0x26, 0x04, 0xf1, 0x9b, 0xef,
+       0xeb, 0x25, 0xd4, 0xa9, 0x39, 0xee, 0xa3, 0x4b, 0xc7, 0x7d, 0x2d, 0xc6,
+       0x0f, 0x3a, 0x5f, 0x32, 0xfa, 0xb7, 0x02, 0x5d, 0xeb, 0xfa, 0x50, 0x9a,
+       0xf2, 0x7e, 0x03, 0x08, 0x79, 0x77, 0xef, 0xd4, 0x43, 0x92, 0x0d, 0xab,
+       0x7d, 0x74, 0x63, 0x09, 0x99, 0x59, 0x33, 0xbd, 0x20, 0x0d, 0xb5, 0x48,
+       0xea, 0xb7, 0x9c, 0xe2, 0x39, 0x63, 0xf7, 0x35, 0x0a, 0x7d, 0x83, 0xb4,
+       0x2b, 0x6d, 0x77, 0x3a, 0x2d, 0x41, 0xb8, 0xc4, 0xa5, 0x9c, 0x00, 0xfa,
+       0x98, 0xe8, 0x1f, 0x80, 0x73, 0x4b, 0x11, 0xad, 0x87, 0x8c, 0x7f, 0x6b,
+       0x89, 0x58, 0x9f, 0x45, 0xe4, 0x60, 0x9d, 0xf2, 0xfb, 0xa4, 0x7e, 0x00,
+       0x61, 0xf1, 0x7f, 0x3e, 0xae, 0xc3, 0xa5, 0x00, 0x5f, 0x4b, 0xe8, 0x1c,
+       0x33, 0x28, 0xab, 0x67, 0x41, 0x39, 0x12, 0x9a, 0x59, 0xbc, 0xa6, 0xd4,
+       0xce, 0xde, 0x55, 0xf1, 0xf1, 0x2c, 0x54, 0x48, 0x00, 0xf7, 0xd7, 0xbe,
+       0x14, 0x88, 0x63, 0x13, 0x5f, 0x32, 0xf6, 0x9b, 0xa3, 0xee, 0x93, 0x35,
+       0xf8, 0x95, 0x2a, 0x26, 0x57, 0x09, 0xa5, 0x6b, 0xe9, 0x7c, 0x3d, 0xd2,
+       0x55, 0x8b, 0xef, 0xfb, 0x7b, 0xe3, 0x5d, 0xba, 0xe1, 0xb4, 0xac, 0x7b,
+       0x44, 0x81, 0xd0, 0x6c, 0x4f, 0xf8, 0xcf, 0x76, 0x8b, 0xed, 0xa4, 0x9c,
+       0x8d, 0xa7, 0xd2, 0x55, 0x95, 0x97, 0x53, 0x9c, 0xbf, 0x27, 0x80, 0xff,
+       0xb4, 0x3c, 0x0d, 0xfc, 0xa7, 0x78, 0x9f, 0xe4, 0xfc, 0x0f, 0xca, 0x31,
+       0xe3, 0xbf, 0xc7, 0xe8, 0x9e, 0x06, 0xfc, 0xef, 0xdc, 0xa4, 0x27, 0xc8,
+       0x2f, 0xce, 0xf7, 0xdb, 0x38, 0xdf, 0x17, 0xd7, 0x8b, 0x7c, 0xbf, 0x0d,
+       0xce, 0xe3, 0x68, 0xff, 0xdb, 0x56, 0x66, 0xb1, 0x78, 0x53, 0x43, 0x2f,
+       0x81, 0xbf, 0x74, 0xe2, 0x22, 0x1d, 0xea, 0x1f, 0x2a, 0xa0, 0x66, 0x35,
+       0x0c, 0xff, 0xbf, 0x73, 0x39, 0x98, 0x53, 0xb7, 0xeb, 0x15, 0x60, 0xef,
+       0xed, 0xe5, 0x9a, 0xf9, 0x71, 0x3e, 0xdc, 0xc9, 0xf9, 0x30, 0x57, 0x43,
+       0x8f, 0xdb, 0x38, 0xdf, 0xe6, 0x72, 0xbe, 0x2d, 0x21, 0xbe, 0x7b, 0x33,
+       0x30, 0x7e, 0xe1, 0x57, 0x20, 0xae, 0x37, 0xbb, 0x5c, 0x22, 0x60, 0x2f,
+       0x3c, 0x77, 0xab, 0x7c, 0x6b, 0x13, 0xf8, 0xe6, 0x56, 0xf9, 0xa6, 0xc1,
+       0xf7, 0x4e, 0xce, 0xb7, 0x3b, 0xef, 0x62, 0x7c, 0xd3, 0xe2, 0xdd, 0xc6,
+       0xf9, 0xd6, 0xd6, 0xf0, 0x99, 0x42, 0x06, 0x84, 0xe3, 0xad, 0xc5, 0x73,
+       0xde, 0x2a, 0xcd, 0xbc, 0x7c, 0x5a, 0xbe, 0xd5, 0x73, 0xb9, 0xb4, 0x1b,
+       0xc0, 0x9f, 0x9a, 0xee, 0xca, 0x5d, 0x71, 0x32, 0xa4, 0xff, 0x2d, 0x45,
+       0x93, 0x57, 0x9c, 0x0c, 0xb1, 0x0b, 0xb7, 0x96, 0x4c, 0x17, 0xea, 0xb3,
+       0x4a, 0x67, 0x0b, 0xfd, 0x67, 0xbb, 0xe7, 0x0b, 0xed, 0xb7, 0x97, 0x2f,
+       0x15, 0xda, 0xe7, 0xd6, 0xfc, 0x4c, 0xa8, 0xcf, 0x5b, 0x75, 0x97, 0xd0,
+       0x7f, 0xbe, 0x6f, 0xb5, 0xd0, 0xbe, 0xb0, 0xee, 0x3e, 0xa1, 0x7d, 0x71,
+       0xfd, 0x43, 0x42, 0x7d, 0x49, 0xc3, 0x26, 0xa1, 0xff, 0x52, 0xff, 0x16,
+       0xa1, 0x7d, 0x59, 0xe3, 0x0e, 0xa1, 0xbd, 0xaa, 0x69, 0x97, 0x50, 0xf7,
+       0x34, 0xbf, 0x24, 0xf4, 0xd7, 0xed, 0xbd, 0xf2, 0x66, 0x90, 0xaf, 0x23,
+       0x6f, 0xeb, 0x09, 0xc4, 0xfb, 0x2e, 0x38, 0x4f, 0x63, 0x9c, 0xf1, 0x82,
+       0x53, 0x71, 0x42, 0x9f, 0x93, 0x5e, 0x07, 0xca, 0xf1, 0x29, 0xef, 0x10,
+       0x2c, 0xcf, 0x78, 0x9d, 0x28, 0xe7, 0x67, 0xbd, 0x63, 0xb1, 0xac, 0x06,
+       0x99, 0x1c, 0x07, 0x76, 0xf6, 0x80, 0x05, 0xe2, 0xa7, 0x9e, 0x38, 0x6a,
+       0xf7, 0x13, 0xe9, 0x3a, 0x2e, 0x8f, 0x5b, 0x53, 0x37, 0x01, 0xd6, 0x1b,
+       0xda, 0x3e, 0x9e, 0x90, 0x7f, 0x95, 0x6f, 0x58, 0xe3, 0xeb, 0x4b, 0xb5,
+       0x00, 0xe2, 0xde, 0x94, 0xfe, 0xc5, 0x0d, 0x06, 0x12, 0x18, 0x45, 0xa8,
+       0x74, 0xf7, 0xee, 0x96, 0xe7, 0x4e, 0x7d, 0x48, 0x7b, 0x5b, 0x0f, 0xed,
+       0x0d, 0x32, 0x09, 0xf4, 0x0a, 0x6f, 0x2f, 0x6e, 0x8b, 0xfc, 0xbc, 0x43,
+       0xea, 0x1c, 0x9c, 0x01, 0x71, 0xd9, 0xf7, 0x8c, 0x64, 0x7b, 0x48, 0xbc,
+       0x31, 0xfc, 0xbc, 0x85, 0xf4, 0x01, 0xbf, 0x22, 0x5a, 0xfb, 0x39, 0x1d,
+       0x29, 0x0f, 0x3d, 0xef, 0xd9, 0x2a, 0xb3, 0x73, 0x9e, 0x23, 0xfa, 0xbc,
+       0xad, 0x32, 0xc5, 0xab, 0xd2, 0xc0, 0xf4, 0xbf, 0xf2, 0xf9, 0x8c, 0x3c,
+       0x62, 0x83, 0x7a, 0x60, 0x70, 0x8d, 0xe5, 0x32, 0xe3, 0x35, 0x51, 0x64,
+       0xd2, 0x80, 0xcf, 0x03, 0x05, 0xbd, 0x5f, 0xd2, 0x70, 0x75, 0x50, 0xcf,
+       0x09, 0x8c, 0xc3, 0xec, 0xe9, 0x52, 0xff, 0x28, 0xe1, 0xf9, 0xb2, 0xc6,
+       0xeb, 0x84, 0xf7, 0xde, 0x90, 0xdc, 0x5b, 0x00, 0x8f, 0x73, 0xfb, 0xf4,
+       0xb8, 0x5e, 0x93, 0xc0, 0x81, 0xcc, 0x5b, 0x86, 0x01, 0x7e, 0xae, 0xad,
+       0x32, 0xac, 0xa3, 0xcd, 0x29, 0xe8, 0x77, 0xb5, 0x7a, 0x5d, 0x2b, 0x4e,
+       0x2a, 0x84, 0xbc, 0xe9, 0x2d, 0xc2, 0xf2, 0x2d, 0x6f, 0x09, 0x96, 0xef,
+       0x78, 0x4b, 0xb1, 0x3c, 0xe6, 0x75, 0x63, 0xf9, 0xbe, 0xb7, 0x1c, 0xcb,
+       0x0f, 0xbd, 0x35, 0x58, 0xfe, 0xbb, 0x77, 0x15, 0x96, 0x6d, 0x5e, 0x1f,
+       0x96, 0x27, 0xbc, 0x75, 0x58, 0x9e, 0xf4, 0xd6, 0x63, 0x79, 0xca, 0xdb,
+       0x80, 0xe5, 0x19, 0xaf, 0x1f, 0xcb, 0xb3, 0xde, 0x46, 0x2c, 0xcf, 0x79,
+       0x9b, 0xb0, 0x6c, 0xf7, 0x36, 0x63, 0xa9, 0xda, 0xcf, 0x9e, 0xe4, 0xef,
+       0x0c, 0x5f, 0x5f, 0xcf, 0x82, 0x1c, 0x1a, 0xc3, 0xe5, 0xec, 0xe0, 0xda,
+       0x79, 0x6b, 0xea, 0xfa, 0x06, 0xe5, 0xec, 0xb0, 0x5c, 0x86, 0x72, 0xa6,
+       0xd2, 0xb7, 0xb8, 0xc1, 0xc8, 0xe5, 0x21, 0x55, 0x90, 0x87, 0xbf, 0xc2,
+       0x3a, 0x9c, 0x02, 0xf2, 0xd2, 0x43, 0x7b, 0x83, 0xc2, 0xe5, 0x30, 0xda,
+       0xfb, 0x91, 0xdb, 0x41, 0xde, 0x7a, 0xff, 0x08, 0xf2, 0x46, 0xc8, 0x1a,
+       0x94, 0x03, 0x0b, 0xc8, 0xdd, 0xf7, 0x90, 0x37, 0x02, 0xa7, 0x08, 0x29,
+       0x20, 0x4f, 0x7d, 0x34, 0xf2, 0x24, 0xca, 0xa1, 0x2a, 0x47, 0xaa, 0x9e,
+       0xbf, 0x21, 0x95, 0x9c, 0x03, 0xf9, 0x52, 0xe5, 0xca, 0x22, 0x33, 0x7f,
+       0x48, 0x95, 0xab, 0xfb, 0xc1, 0x4f, 0x8c, 0xe0, 0x6f, 0xf5, 0x56, 0x24,
+       0xbe, 0xfe, 0x31, 0xff, 0x88, 0x04, 0x72, 0x75, 0x40, 0xb2, 0xe5, 0xfc,
+       0xbc, 0x82, 0xf8, 0x5c, 0x58, 0xef, 0xe2, 0x63, 0xd7, 0x52, 0x70, 0xad,
+       0xd0, 0x4f, 0xf6, 0x0f, 0x81, 0x75, 0xa4, 0x6b, 0xc8, 0x57, 0x83, 0x21,
+       0xbe, 0xdf, 0x75, 0x8c, 0x0a, 0x41, 0x56, 0xf4, 0xf9, 0x69, 0xe5, 0x25,
+       0x3a, 0xdd, 0x5d, 0xb8, 0x7f, 0x28, 0xf3, 0x53, 0xe6, 0xf7, 0x0a, 0x6f,
+       0x37, 0xc7, 0x31, 0xba, 0x9a, 0x75, 0xa4, 0x88, 0x8c, 0x84, 0xf3, 0xe5,
+       0x9c, 0x63, 0x6e, 0xca, 0xcf, 0xb8, 0x3f, 0x5d, 0x3d, 0x12, 0xf6, 0xcd,
+       0xf4, 0xb9, 0x4c, 0x92, 0x00, 0x8e, 0xdf, 0x39, 0x3d, 0xc2, 0x79, 0x01,
+       0x19, 0x44, 0x90, 0xce, 0x3d, 0xd1, 0x57, 0xed, 0x7f, 0xea, 0x89, 0xff,
+       0xcc, 0x81, 0x73, 0x7f, 0x0b, 0xe8, 0x39, 0x9d, 0x7b, 0xdc, 0x01, 0x7d,
+       0x0d, 0xd3, 0xdf, 0xa7, 0x9c, 0xb7, 0x84, 0x9c, 0x2f, 0x79, 0x8c, 0xce,
+       0x74, 0x88, 0x83, 0x77, 0x66, 0x1b, 0xec, 0xcc, 0x7f, 0x98, 0x24, 0xd2,
+       0x91, 0x4c, 0xc2, 0xf3, 0x03, 0x95, 0x8e, 0x07, 0xb2, 0xbf, 0x18, 0x0c,
+       0xe7, 0x33, 0xf7, 0x51, 0x39, 0x04, 0xfd, 0xea, 0x1a, 0x34, 0x38, 0x81,
+       0x5c, 0x46, 0x3e, 0x7a, 0xb2, 0xf7, 0x3d, 0xd1, 0x73, 0x01, 0xcc, 0x37,
+       0x26, 0x7a, 0x1a, 0x08, 0x9c, 0x73, 0x51, 0x7a, 0x6e, 0x85, 0xfb, 0x8e,
+       0xb1, 0xd2, 0xb3, 0x27, 0x3b, 0xd9, 0x93, 0x7d, 0x3c, 0xb1, 0x81, 0xd1,
+       0xf9, 0x08, 0xf7, 0x4f, 0xa3, 0xd1, 0x59, 0x3d, 0x0f, 0xd3, 0xe2, 0x71,
+       0x8b, 0x22, 0x73, 0x3e, 0x70, 0x39, 0x26, 0x77, 0x68, 0xe8, 0x5f, 0x2a,
+       0xd0, 0xbf, 0xaf, 0xd5, 0x81, 0xfd, 0x0f, 0xee, 0xfd, 0x20, 0x13, 0xce,
+       0xf1, 0xba, 0x76, 0x5f, 0x91, 0x40, 0x86, 0x86, 0xbe, 0x5f, 0xc0, 0xce,
+       0x7b, 0xba, 0xdf, 0xcf, 0x17, 0xf4, 0x40, 0xfa, 0xd3, 0xdf, 0x33, 0x61,
+       0x7f, 0x7c, 0xf0, 0x85, 0x77, 0xb1, 0x5c, 0x4b, 0x98, 0x1e, 0x6e, 0xb4,
+       0x94, 0xcc, 0x55, 0xc6, 0x04, 0xe1, 0xc5, 0x7a, 0x8f, 0x20, 0xda, 0xbc,
+       0x3c, 0x8a, 0x24, 0xce, 0xab, 0x07, 0xfd, 0xec, 0x48, 0x55, 0xf5, 0xb3,
+       0x35, 0x13, 0xe4, 0x69, 0x37, 0xb7, 0x03, 0x61, 0xf3, 0xeb, 0x41, 0x3e,
+       0xd5, 0xf9, 0x1d, 0x80, 0xf9, 0x51, 0x38, 0x53, 0x41, 0xa6, 0xe9, 0x3c,
+       0xf2, 0xe5, 0x92, 0xbb, 0x84, 0xf9, 0x8d, 0x4e, 0xc1, 0x79, 0xf7, 0x34,
+       0x3f, 0x4f, 0x82, 0x81, 0x48, 0x23, 0x28, 0x7e, 0x56, 0x83, 0x81, 0x24,
+       0x50, 0x79, 0x54, 0xdc, 0x6b, 0x15, 0xdc, 0xd7, 0x39, 0xdb, 0x7c, 0x10,
+       0xa7, 0xd8, 0x1b, 0xef, 0xac, 0xa5, 0x2c, 0xf1, 0xd8, 0xce, 0xbe, 0x11,
+       0x70, 0xc0, 0x7b, 0x62, 0x3c, 0x63, 0x59, 0xa3, 0xb9, 0x46, 0xf4, 0x9f,
+       0x12, 0x6b, 0x44, 0xff, 0x29, 0xa3, 0x26, 0xd4, 0x7f, 0xea, 0x3a, 0xfc,
+       0x94, 0xcd, 0x4d, 0xf1, 0x5b, 0x9e, 0xae, 0xaf, 0x39, 0xd9, 0x0b, 0xd6,
+       0x39, 0x17, 0x5f, 0xe7, 0xd8, 0xba, 0xaa, 0xe2, 0x57, 0xd5, 0x94, 0x55,
+       0x63, 0x11, 0xe0, 0x88, 0xf5, 0xae, 0x7a, 0xa9, 0x88, 0xdd, 0xc3, 0x71,
+       0x24, 0xcc, 0x8c, 0x70, 0xde, 0xa7, 0x96, 0xcb, 0xd3, 0x0d, 0x38, 0xce,
+       0xd9, 0xc6, 0x81, 0x09, 0x30, 0xee, 0x59, 0xaf, 0xa9, 0x86, 0xad, 0xaf,
+       0xf6, 0x1a, 0x36, 0x6e, 0x7a, 0x4d, 0xe8, 0xfa, 0x5a, 0xb9, 0x2a, 0xbe,
+       0xe6, 0xe4, 0xa8, 0x20, 0x7e, 0xd1, 0xe0, 0xfe, 0xd0, 0xf8, 0x51, 0x89,
+       0x20, 0x1f, 0x99, 0x60, 0x5d, 0xa4, 0x6d, 0x03, 0xa3, 0xf7, 0x8f, 0xca,
+       0x4f, 0xf9, 0x73, 0x03, 0x9e, 0xab, 0xb7, 0x28, 0x5f, 0x80, 0xff, 0x6e,
+       0x1e, 0xa2, 0xfa, 0xef, 0x32, 0xd6, 0x55, 0xb8, 0x9e, 0x26, 0xbd, 0xcf,
+       0x38, 0x02, 0x9e, 0xef, 0x14, 0xc6, 0xa3, 0xef, 0x39, 0xd4, 0xb3, 0x71,
+       0x78, 0x2f, 0xba, 0xdc, 0xc8, 0xe4, 0x94, 0xca, 0x4f, 0x3d, 0x9c, 0x77,
+       0x11, 0xbe, 0x3f, 0x30, 0x21, 0x9f, 0xdd, 0x14, 0x62, 0x02, 0x85, 0xd7,
+       0x21, 0x5b, 0xea, 0x40, 0xae, 0xfc, 0x0a, 0xd3, 0x67, 0x0f, 0x97, 0xd3,
+       0x2a, 0x53, 0x9b, 0xc1, 0xed, 0x40, 0x72, 0xb7, 0x82, 0x5c, 0x2f, 0x18,
+       0xab, 0xca, 0xb9, 0x63, 0xd6, 0x07, 0xd4, 0x4e, 0x7f, 0xfc, 0x17, 0x05,
+       0xef, 0x99, 0x91, 0xaf, 0x29, 0xf4, 0x9c, 0xe0, 0x55, 0x87, 0x45, 0xa4,
+       0xc4, 0x06, 0x41, 0xd5, 0x05, 0xbb, 0x97, 0x15, 0xc3, 0xba, 0xfd, 0xf1,
+       0x8b, 0x37, 0xf1, 0x7d, 0x7a, 0x7d, 0x0e, 0xcc, 0xfb, 0x3c, 0xd1, 0x15,
+       0x81, 0x5d, 0x3a, 0x4f, 0xde, 0xb4, 0x8d, 0x0a, 0xd1, 0xd7, 0xd3, 0x0a,
+       0x8b, 0x63, 0x91, 0x3a, 0xb6, 0xcf, 0xf1, 0xd1, 0x3f, 0x30, 0xbf, 0xc5,
+       0xf5, 0xe2, 0xbe, 0x67, 0x49, 0x83, 0x58, 0x2f, 0x23, 0x33, 0x52, 0xc1,
+       0xde, 0x96, 0x6d, 0x54, 0x88, 0x9f, 0xe2, 0xbe, 0x14, 0xf6, 0x4d, 0xea,
+       0xbc, 0xa9, 0xfd, 0x7d, 0x57, 0xb1, 0x23, 0x72, 0x4b, 0x48, 0xcd, 0x3a,
+       0xd8, 0xa7, 0x3f, 0xa6, 0xb0, 0x78, 0xcf, 0x02, 0x3b, 0x91, 0xfb, 0x50,
+       0x7b, 0x5d, 0xf5, 0x87, 0x5f, 0xe7, 0x40, 0xdc, 0xa7, 0x5d, 0x61, 0xfe,
+       0xae, 0x7a, 0x1e, 0xbe, 0x34, 0x89, 0xed, 0x07, 0x2b, 0x66, 0xfa, 0x0d,
+       0x2e, 0xda, 0xff, 0xa3, 0xdd, 0xa3, 0x6e, 0xa3, 0x16, 0x97, 0xbe, 0xef,
+       0x5f, 0x87, 0xfe, 0xcf, 0x74, 0xe2, 0xdc, 0x4e, 0xc2, 0xe9, 0xbe, 0xb0,
+       0x4e, 0xc4, 0xaf, 0x27, 0xfc, 0xb5, 0xf8, 0xaa, 0x7e, 0x50, 0xd8, 0xb9,
+       0x3c, 0xc7, 0x23, 0xb9, 0x51, 0x8a, 0x78, 0x5f, 0xea, 0x6b, 0x6e, 0xe7,
+       0x54, 0xfd, 0x48, 0x32, 0xd8, 0x85, 0xb8, 0x4f, 0x9a, 0xa6, 0xae, 0xca,
+       0x81, 0xc2, 0xe5, 0xc0, 0xaf, 0xb8, 0xad, 0x86, 0x14, 0xc6, 0x77, 0xe0,
+       0xa3, 0x24, 0x77, 0x1a, 0xdc, 0x21, 0xfd, 0x0c, 0xc1, 0x7e, 0x49, 0x86,
+       0x31, 0xd1, 0xfb, 0x19, 0xa1, 0x9f, 0x1e, 0xfb, 0xa5, 0xb1, 0x7e, 0x9d,
+       0x85, 0xb8, 0x3f, 0x26, 0x54, 0x9e, 0x86, 0x06, 0xfb, 0x99, 0x83, 0xf0,
+       0xfa, 0xb2, 0x71, 0xc5, 0x7e, 0x55, 0x7f, 0x78, 0xf6, 0x45, 0x1f, 0x95,
+       0x97, 0x8a, 0xdf, 0x3d, 0x6a, 0x23, 0x74, 0xdd, 0xfc, 0x58, 0xae, 0x4f,
+       0x75, 0xd2, 0xe7, 0x95, 0xdb, 0xef, 0xb5, 0xb9, 0x68, 0x79, 0x46, 0xf6,
+       0xd9, 0x80, 0x9f, 0x1f, 0xfb, 0xf5, 0x11, 0xef, 0xfb, 0xde, 0x62, 0x50,
+       0xe9, 0xe1, 0xb2, 0x48, 0x10, 0x4f, 0xe3, 0xf2, 0x49, 0xea, 0x7c, 0x18,
+       0xa7, 0xf8, 0x62, 0xbb, 0x62, 0xc7, 0x73, 0x84, 0x46, 0x63, 0xc0, 0x48,
+       0xe5, 0xb3, 0x7a, 0xf7, 0xd2, 0x62, 0x32, 0x1c, 0xeb, 0xc7, 0x59, 0x7d,
+       0xfd, 0xa7, 0x7a, 0xa8, 0x37, 0x8b, 0xfc, 0xaa, 0xf8, 0xcd, 0xa3, 0xa9,
+       0x0e, 0x76, 0x4f, 0x88, 0xc5, 0x93, 0x48, 0x00, 0xfd, 0xdc, 0xea, 0x6d,
+       0xff, 0x51, 0x08, 0xeb, 0x85, 0x87, 0x74, 0xa2, 0x9c, 0x69, 0xdf, 0x83,
+       0xf1, 0x2f, 0x26, 0xa1, 0x5e, 0xcf, 0x37, 0x24, 0x84, 0xb7, 0xe3, 0xc5,
+       0xe0, 0x54, 0x78, 0x9f, 0xfd, 0x78, 0x76, 0xdf, 0xff, 0xa9, 0xde, 0x06,
+       0xe5, 0xe4, 0xd3, 0xa0, 0x47, 0x1e, 0x8d, 0x9c, 0x94, 0x73, 0xbf, 0x15,
+       0xe8, 0x05, 0xfb, 0xfd, 0x7c, 0x83, 0x35, 0x19, 0xed, 0xfd, 0xb5, 0xe4,
+       0x5a, 0xd0, 0x77, 0x95, 0x2e, 0xc4, 0xcf, 0xfc, 0xd7, 0xda, 0x1d, 0x8f,
+       0x0f, 0x3f, 0x4e, 0xf1, 0x3a, 0xb7, 0xed, 0x2f, 0x36, 0x69, 0x68, 0xa8,
+       0x9d, 0x60, 0xf2, 0xd6, 0xd5, 0xb4, 0xf0, 0xdf, 0x4c, 0xba, 0xe8, 0xf6,
+       0xa4, 0x9d, 0xca, 0x63, 0xa8, 0x9f, 0x44, 0x01, 0xe3, 0x7b, 0x8e, 0x66,
+       0xee, 0x77, 0xb7, 0xb0, 0xb2, 0x52, 0x09, 0xd8, 0xe0, 0x3e, 0x4e, 0xe5,
+       0x16, 0xc5, 0x49, 0x25, 0x91, 0x54, 0x3e, 0xab, 0x27, 0x70, 0x3f, 0x81,
+       0xbc, 0x67, 0xf4, 0x43, 0x7c, 0x74, 0xd9, 0xb3, 0xaf, 0xbc, 0x33, 0x9e,
+       0xd2, 0x7f, 0xd9, 0x2e, 0x25, 0xb9, 0x98, 0x4d, 0xc7, 0x22, 0xa5, 0x06,
+       0xf9, 0xe3, 0xa1, 0x7f, 0x57, 0x8d, 0x0c, 0xf2, 0xa3, 0xe2, 0xf7, 0xaf,
+       0x18, 0x1c, 0xc3, 0xd8, 0xf3, 0x7b, 0x92, 0x82, 0x7c, 0x59, 0xb6, 0x6b,
+       0x9f, 0x81, 0x0c, 0x0b, 0xa7, 0xe3, 0xa4, 0xa6, 0x7d, 0x86, 0x36, 0x4b,
+       0x04, 0xfe, 0x34, 0x1d, 0x2f, 0x84, 0xf5, 0xb6, 0x76, 0xc7, 0x3f, 0x0c,
+       0x10, 0x57, 0xfc, 0x78, 0xaf, 0x44, 0xd2, 0xb2, 0xc2, 0xdf, 0x2f, 0xdf,
+       0xf2, 0x0a, 0xae, 0x7b, 0x40, 0x27, 0xe4, 0x27, 0xe7, 0x57, 0x37, 0xff,
+       0xc2, 0xf8, 0x16, 0x98, 0xf6, 0xf2, 0x68, 0xec, 0x67, 0x07, 0x7b, 0xd8,
+       0x13, 0xdf, 0xb2, 0x61, 0x3f, 0x97, 0x82, 0xf2, 0xfd, 0xdc, 0xcb, 0x70,
+       0x8f, 0xe9, 0x7d, 0xa3, 0x13, 0xe8, 0x50, 0xfe, 0xdc, 0x0a, 0x1b, 0xcc,
+       0xe7, 0xb4, 0x5c, 0xc3, 0xe4, 0xfc, 0xd7, 0xf7, 0xa6, 0x82, 0xbe, 0x97,
+       0x2b, 0xbe, 0x54, 0x3b, 0x96, 0xec, 0x79, 0xf9, 0x93, 0x3f, 0x47, 0xf9,
+       0x5b, 0x72, 0xf4, 0xe7, 0xa9, 0xe8, 0x3f, 0x10, 0x57, 0x86, 0x0e, 0x6d,
+       0xb3, 0x2f, 0x03, 0xe6, 0xb9, 0x78, 0xf3, 0xad, 0x38, 0xcf, 0x32, 0xe2,
+       0x46, 0x39, 0x2c, 0xff, 0xb5, 0xbe, 0x04, 0xee, 0x99, 0x5e, 0x90, 0x49,
+       0xd1, 0xae, 0x08, 0x7a, 0xf2, 0x17, 0x03, 0xdb, 0xbf, 0x9c, 0xde, 0x4a,
+       0x99, 0x4b, 0xe7, 0x79, 0x1a, 0xf0, 0x03, 0xfb, 0xf6, 0xa6, 0xde, 0xbf,
+       0x1d, 0xe3, 0xe6, 0x3f, 0xc3, 0x7b, 0x70, 0x3f, 0xe7, 0x73, 0xa6, 0x2b,
+       0x21, 0xd6, 0x2f, 0x98, 0x18, 0xbf, 0xb6, 0x18, 0x74, 0x6a, 0x3c, 0xd4,
+       0x24, 0xc8, 0xef, 0xb6, 0xf5, 0xad, 0xc0, 0xa7, 0xb3, 0xfd, 0x5c, 0x69,
+       0x70, 0xee, 0x41, 0xe9, 0xe0, 0xe3, 0x74, 0x93, 0x2e, 0x51, 0xb8, 0xfa,
+       0xa3, 0x05, 0x69, 0x8c, 0x4f, 0xc4, 0x21, 0xe7, 0xf0, 0xf7, 0xa8, 0xbd,
+       0x9f, 0x04, 0xcf, 0xa1, 0x7f, 0xab, 0xe2, 0x32, 0x0f, 0x17, 0xde, 0xe3,
+       0xf6, 0x91, 0x8d, 0xbf, 0x92, 0x8f, 0x4f, 0xf1, 0x8e, 0x83, 0xf5, 0xeb,
+       0x74, 0x6a, 0x64, 0xff, 0xef, 0x1f, 0x7c, 0x7e, 0xf4, 0xa7, 0x95, 0x84,
+       0xc8, 0x59, 0x88, 0xbe, 0x33, 0xfd, 0xdf, 0x76, 0x1f, 0xd3, 0x77, 0x55,
+       0xff, 0xfd, 0xd3, 0x8b, 0xa0, 0xfd, 0xf3, 0xb7, 0x98, 0x1e, 0xc1, 0x7b,
+       0xb0, 0x5e, 0x50, 0xbc, 0x02, 0x69, 0xd8, 0xbe, 0x6f, 0xa6, 0x84, 0xf6,
+       0x81, 0xee, 0xb3, 0x23, 0xe9, 0xf9, 0x36, 0x85, 0xeb, 0xb9, 0xd8, 0x4e,
+       0x77, 0x38, 0xb8, 0xfe, 0xab, 0x72, 0x42, 0xf1, 0x97, 0xa5, 0x84, 0x50,
+       0x79, 0xa1, 0xe3, 0x24, 0x21, 0x1f, 0x70, 0x7f, 0x5c, 0xb6, 0x91, 0xbe,
+       0x1f, 0xe2, 0x97, 0x79, 0x60, 0x5c, 0xec, 0x67, 0x08, 0x3e, 0x0f, 0x59,
+       0x37, 0x96, 0x70, 0xbb, 0x70, 0x48, 0x63, 0x0f, 0xc8, 0xe6, 0x94, 0x98,
+       0xfc, 0xe8, 0x4a, 0xc5, 0xff, 0xf4, 0x13, 0xa0, 0xbf, 0xef, 0x19, 0x9d,
+       0x3e, 0x07, 0xe8, 0xaf, 0x52, 0x02, 0xf3, 0xff, 0x64, 0xe7, 0x81, 0x77,
+       0xe6, 0x50, 0x39, 0xff, 0xa4, 0x49, 0xd5, 0x5b, 0xd1, 0xae, 0x6a, 0xf5,
+       0xb6, 0xfc, 0xf9, 0x31, 0x24, 0x92, 0xde, 0x7e, 0x62, 0xa1, 0xfb, 0xae,
+       0x48, 0x7a, 0x4b, 0x9f, 0x47, 0xd4, 0x5b, 0x4b, 0x1b, 0xca, 0xf3, 0xff,
+       0x2d, 0xbb, 0xaa, 0xd2, 0xaf, 0x5d, 0x43, 0x3f, 0xb0, 0x8f, 0x2f, 0x3b,
+       0xa2, 0xd3, 0x51, 0x6b, 0x1f, 0x37, 0x18, 0x1c, 0x11, 0xed, 0x23, 0xfd,
+       0x79, 0x8b, 0xe4, 0x84, 0xcb, 0xa1, 0x2a, 0x7f, 0xaa, 0xdc, 0x55, 0xfc,
+       0xb6, 0xaa, 0x3f, 0xd8, 0xa1, 0x6e, 0xf9, 0x54, 0xe5, 0xaf, 0x5b, 0x3e,
+       0x55, 0xf9, 0xd3, 0xce, 0x57, 0xa4, 0x9f, 0xb6, 0xfd, 0x0f, 0xa0, 0xdf,
+       0x14, 0xaf, 0xdb, 0x4d, 0x9b, 0xa6, 0x81, 0xff, 0x6c, 0xea, 0x24, 0x18,
+       0x87, 0xcf, 0x9d, 0xa9, 0xc7, 0x7b, 0x9a, 0xa6, 0xcf, 0x09, 0xbb, 0xa7,
+       0x71, 0x47, 0x3c, 0xd6, 0x67, 0xe9, 0xdb, 0x7e, 0x0f, 0x3e, 0xe1, 0x07,
+       0x55, 0xb3, 0x86, 0xc1, 0x3a, 0x7f, 0x3b, 0xf1, 0x29, 0xec, 0xdc, 0xbe,
+       0x5e, 0x41, 0x3f, 0xf6, 0xeb, 0x4b, 0x97, 0x26, 0xd0, 0xf9, 0xcc, 0xe1,
+       0xf4, 0xbd, 0x9d, 0x92, 0x7b, 0x2a, 0xe5, 0x47, 0xa9, 0x2c, 0x05, 0xe2,
+       0x28, 0x9e, 0xb3, 0x65, 0xe2, 0x4b, 0x48, 0x82, 0x78, 0xb2, 0x44, 0x4e,
+       0x84, 0xe0, 0x71, 0x7b, 0xb9, 0x58, 0x87, 0x9f, 0x89, 0xa9, 0x41, 0x38,
+       0x3d, 0xf5, 0xff, 0xb6, 0x7e, 0xf7, 0x77, 0x2d, 0x8f, 0x52, 0xbe, 0x9e,
+       0xc8, 0x26, 0xe4, 0x6f, 0x50, 0xe2, 0xfe, 0x83, 0x3a, 0xd6, 0x21, 0xf2,
+       0x34, 0xbd, 0x85, 0x9d, 0x63, 0x78, 0x46, 0x4b, 0xfe, 0x01, 0xa8, 0x87,
+       0x6d, 0x72, 0x49, 0xc8, 0x3e, 0xc2, 0x63, 0x64, 0xf6, 0xe7, 0x68, 0xfe,
+       0x2d, 0x63, 0x80, 0x7e, 0xb9, 0xb3, 0x86, 0x25, 0x30, 0x39, 0x1f, 0x8c,
+       0xfb, 0x45, 0x0f, 0xb7, 0x63, 0x5d, 0x3e, 0x47, 0x02, 0xd8, 0xf7, 0xae,
+       0x96, 0x81, 0xb8, 0x2f, 0xec, 0x3a, 0xbc, 0xd0, 0xea, 0x8e, 0x60, 0xcf,
+       0x0e, 0x70, 0x39, 0x7b, 0x85, 0x9f, 0xc3, 0x74, 0x58, 0xa4, 0x7a, 0x3d,
+       0x95, 0xfb, 0x0e, 0xd2, 0x89, 0x7e, 0x8d, 0xcf, 0x62, 0x8e, 0x18, 0x97,
+       0x9b, 0x63, 0x54, 0xed, 0x34, 0xe7, 0x1b, 0xfd, 0xd1, 0xd3, 0xf1, 0x4b,
+       0xb9, 0x1c, 0xce, 0xa6, 0xaf, 0x26, 0x8c, 0x0c, 0xe1, 0xdb, 0xcc, 0xa9,
+       0x1f, 0xcb, 0xb6, 0x70, 0x3e, 0xc0, 0xcf, 0x89, 0x90, 0x7d, 0xc5, 0xf7,
+       0xa5, 0x2f, 0xc8, 0x35, 0xd0, 0xf7, 0x80, 0xb9, 0xad, 0xb0, 0x24, 0x42,
+       0xfc, 0xa6, 0x92, 0xd3, 0x6f, 0xe2, 0xfe, 0x2f, 0x0d, 0xb0, 0xee, 0xe5,
+       0xb7, 0xe4, 0xca, 0x40, 0xc7, 0x7c, 0x8b, 0x5e, 0x88, 0x87, 0x2c, 0x32,
+       0x72, 0x7d, 0x1d, 0x4a, 0x86, 0x02, 0x5e, 0x13, 0xf7, 0x2f, 0x7d, 0x60,
+       0x0c, 0x95, 0x63, 0xcf, 0x61, 0xbd, 0xd3, 0x4c, 0xe7, 0xe7, 0x69, 0xf9,
+       0xd4, 0xe0, 0x8e, 0xb0, 0xbf, 0xd3, 0xd2, 0x13, 0xe0, 0x83, 0x7f, 0xb9,
+       0xd5, 0xc8, 0xfc, 0xe5, 0xb7, 0x95, 0x92, 0xc5, 0x40, 0xd7, 0xb7, 0x6f,
+       0x65, 0xe7, 0xbd, 0x7f, 0x33, 0x38, 0xab, 0x22, 0xe1, 0x99, 0x6e, 0x66,
+       0xfe, 0xe6, 0x6c, 0x52, 0x72, 0x61, 0xb4, 0xf4, 0xd3, 0xa3, 0x6f, 0xee,
+       0x2c, 0x6b, 0x20, 0x8f, 0xd2, 0xa3, 0xcb, 0xc2, 0xee, 0x6b, 0x87, 0xcb,
+       0x1f, 0xd3, 0xfb, 0x2e, 0xbb, 0xe4, 0x5f, 0x2d, 0x81, 0x1c, 0xea, 0x59,
+       0x3d, 0x99, 0xdd, 0x6f, 0x2e, 0x24, 0xee, 0x07, 0x26, 0x48, 0xa8, 0xef,
+       0x37, 0x84, 0xda, 0xaf, 0xdc, 0xe6, 0xe9, 0xcf, 0xc2, 0x7d, 0x9a, 0xea,
+       0x16, 0xc9, 0xae, 0xa3, 0xed, 0xd5, 0x72, 0x9b, 0x01, 0xe4, 0xd8, 0xd3,
+       0xbc, 0x4b, 0x06, 0xbf, 0xfd, 0x26, 0x07, 0x71, 0xe1, 0xfe, 0x5a, 0xae,
+       0x19, 0x36, 0x33, 0x24, 0xfe, 0x45, 0x97, 0x3d, 0xa4, 0xd7, 0x81, 0xaf,
+       0xe6, 0xcc, 0x05, 0xfa, 0x7e, 0x36, 0xd3, 0x48, 0x00, 0x2f, 0xd7, 0xd0,
+       0x4f, 0x6d, 0xb0, 0xfe, 0x7f, 0xd6, 0x32, 0x0a, 0xf5, 0x20, 0xda, 0xbc,
+       0x5e, 0xf7, 0x92, 0x69, 0xf9, 0x0a, 0xc0, 0x61, 0xf6, 0x4c, 0x2b, 0x0f,
+       0x85, 0xc9, 0xf1, 0x42, 0xfd, 0xd6, 0x49, 0xa4, 0x2f, 0x9c, 0x03, 0x4f,
+       0x34, 0xb6, 0xad, 0x70, 0x46, 0xe0, 0x5f, 0xbe, 0x89, 0xc9, 0x59, 0xcc,
+       0xf6, 0xcd, 0xf4, 0xff, 0x99, 0x7d, 0x9b, 0x40, 0xed, 0x1b, 0x93, 0x6b,
+       0x25, 0xd4, 0xbe, 0x59, 0x4c, 0x61, 0xf6, 0x2d, 0x2d, 0x92, 0x7d, 0x5b,
+       0xbe, 0xda, 0x91, 0x06, 0x72, 0xb1, 0x7c, 0xcf, 0x40, 0xfc, 0x7e, 0x6b,
+       0xf9, 0x6b, 0x8b, 0x53, 0x22, 0xd9, 0xb7, 0x57, 0xf9, 0xbe, 0xf7, 0x35,
+       0x7e, 0x0f, 0xbc, 0xa3, 0x2f, 0xb5, 0x6f, 0x23, 0x42, 0xec, 0x5b, 0x5f,
+       0x6a, 0xdf, 0x22, 0xc4, 0xc9, 0xbf, 0x88, 0xd5, 0xbe, 0x99, 0xfe, 0x67,
+       0xf4, 0xef, 0x55, 0xb0, 0x6f, 0x11, 0xe6, 0x6b, 0x36, 0x89, 0xf6, 0xad,
+       0xa8, 0x65, 0x35, 0xda, 0xb7, 0xa2, 0xbe, 0x7a, 0xe1, 0xbe, 0x12, 0x31,
+       0x51, 0xfb, 0x16, 0x7f, 0x39, 0xfb, 0x36, 0xff, 0xd1, 0x5b, 0xb1, 0xae,
+       0x38, 0xe3, 0x23, 0xc8, 0x0f, 0xd0, 0x15, 0xec, 0xdb, 0x6b, 0xdc, 0xce,
+       0xc1, 0x38, 0x60, 0xe7, 0x6e, 0x30, 0xb1, 0xf8, 0x66, 0xac, 0x76, 0xae,
+       0x5f, 0xac, 0x76, 0xee, 0x7f, 0x88, 0xce, 0xaa, 0x9d, 0x5b, 0xde, 0x4f,
+       0x42, 0xff, 0x25, 0x5c, 0x0e, 0x99, 0x9d, 0x5b, 0x9e, 0xc5, 0xec, 0xdc,
+       0xf2, 0x3d, 0xcc, 0xce, 0x2d, 0xcf, 0x66, 0x76, 0x4e, 0x6b, 0xdf, 0xf2,
+       0xc2, 0xec, 0x1b, 0x7b, 0xbf, 0x7a, 0x08, 0x7d, 0x1f, 0xf7, 0x8f, 0x59,
+       0x8f, 0xdf, 0x01, 0xf7, 0x09, 0x4b, 0x15, 0xa7, 0x89, 0xf6, 0x2f, 0x76,
+       0xa8, 0xdf, 0x4f, 0xd4, 0x8c, 0x09, 0xb5, 0x77, 0x37, 0x98, 0x64, 0xa4,
+       0x73, 0x98, 0xbd, 0x73, 0x7e, 0x8a, 0xdf, 0xc1, 0xf4, 0x64, 0xef, 0xfe,
+       0x0a, 0xf6, 0x2e, 0x1b, 0xed, 0xd8, 0x20, 0xd0, 0x23, 0xad, 0x7c, 0x4c,
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+       0x56, 0x85, 0xc0, 0x7d, 0xf6, 0xb3, 0x4d, 0xfa, 0x22, 0x7f, 0x84, 0x71,
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+       0x1a, 0x3a, 0xda, 0x93, 0xed, 0xb9, 0xb0, 0x0f, 0xb7, 0xe7, 0x97, 0x8c,
+       0x06, 0xb1, 0xd2, 0xda, 0x83, 0x44, 0x97, 0x4e, 0xc0, 0x7b, 0xa5, 0xb5,
+       0x28, 0xcd, 0x61, 0x81, 0xbc, 0x5e, 0xcc, 0x4f, 0x21, 0xb2, 0x13, 0xbf,
+       0x33, 0xd4, 0xdb, 0x0a, 0x8b, 0x60, 0x1e, 0x7a, 0xbb, 0xce, 0x6e, 0x8e,
+       0xb8, 0xbe, 0x32, 0x78, 0x8a, 0x85, 0xe5, 0xcd, 0x50, 0xec, 0xe2, 0x77,
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+       0xa7, 0x26, 0x0f, 0x46, 0xf9, 0x8d, 0xff, 0xaf, 0xe5, 0xc1, 0xf0, 0xc1,
+       0x38, 0x3f, 0x81, 0x3c, 0x18, 0x01, 0x8c, 0xef, 0xa8, 0x79, 0x30, 0x92,
+       0x7f, 0xe4, 0x3c, 0x18, 0x10, 0x5f, 0x1a, 0x1d, 0x92, 0x07, 0xa3, 0x53,
+       0x93, 0x07, 0x83, 0xf3, 0xf1, 0x9f, 0x79, 0x30, 0xfe, 0x99, 0x07, 0x03,
+       0x4a, 0x35, 0x0f, 0xc6, 0x3b, 0x1b, 0xca, 0x0a, 0x20, 0x4f, 0x85, 0x9a,
+       0x07, 0xe3, 0xcc, 0x06, 0x4f, 0x01, 0xe4, 0xa5, 0x50, 0xf3, 0x60, 0x7c,
+       0xb5, 0x61, 0x15, 0xab, 0xf3, 0x3c, 0x18, 0x96, 0xfb, 0x57, 0x17, 0x84,
+       0xe6, 0xc1, 0xc8, 0xbc, 0x7f, 0x03, 0xb6, 0xab, 0x79, 0x30, 0x9c, 0xf7,
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+       0x30, 0x66, 0xde, 0xbf, 0xbd, 0x20, 0x34, 0x0f, 0x46, 0xd9, 0xfd, 0xcf,
+       0x15, 0x08, 0x79, 0x30, 0xd6, 0xfe, 0xa1, 0x00, 0xf2, 0x60, 0xbc, 0x1e,
+       0xef, 0x6e, 0x8d, 0x4b, 0x89, 0x9e, 0x07, 0xa3, 0x39, 0xce, 0x11, 0x53,
+       0x1e, 0x0c, 0x0a, 0xe7, 0x3d, 0x84, 0x13, 0x25, 0x0f, 0x86, 0x16, 0x4e,
+       0xb4, 0x3c, 0x18, 0x14, 0xce, 0x89, 0xb8, 0x31, 0xd1, 0xf3, 0x60, 0x84,
+       0xe1, 0x13, 0x25, 0x0f, 0x06, 0x85, 0xf3, 0x09, 0xc2, 0x89, 0x92, 0x07,
+       0x23, 0x0c, 0x9f, 0x28, 0x79, 0x30, 0x28, 0x9c, 0xcf, 0x71, 0x5e, 0x51,
+       0xf2, 0x60, 0x68, 0xe1, 0x44, 0xcb, 0x83, 0x41, 0xe1, 0xfc, 0x17, 0xc2,
+       0x89, 0x92, 0x07, 0x43, 0x0b, 0x27, 0x5a, 0x1e, 0x0c, 0x0a, 0xc7, 0x10,
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+       0x80, 0xb5, 0x36, 0xe2, 0x4a, 0x4c, 0x02, 0x67, 0x8f, 0x38, 0xf4, 0x03,
+       0x61, 0x1f, 0x76, 0x8d, 0x09, 0xe2, 0x35, 0x55, 0xbb, 0x3f, 0x7d, 0xe3,
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+       0xa0, 0x70, 0xde, 0x1a, 0x1a, 0x37, 0xe8, 0x55, 0x24, 0xc6, 0x81, 0x1a,
+       0xcc, 0xb6, 0xe1, 0x70, 0x6f, 0x2f, 0x5d, 0xbd, 0xbf, 0xe7, 0x73, 0xb5,
+       0x82, 0x1f, 0xbe, 0x88, 0xc3, 0x4d, 0x29, 0x11, 0xe3, 0x44, 0x9f, 0x2c,
+       0x28, 0x3a, 0x0c, 0xfe, 0xf3, 0x22, 0x77, 0x19, 0xde, 0xab, 0x48, 0x2b,
+       0x15, 0xe3, 0x46, 0x84, 0x7f, 0x47, 0x0f, 0xdb, 0x32, 0xf0, 0x33, 0x65,
+       0xc2, 0xef, 0x75, 0xfa, 0xd9, 0x7d, 0xcf, 0xb0, 0xef, 0xea, 0x9b, 0xb7,
+       0x20, 0x9e, 0x4b, 0xfd, 0x9a, 0xfb, 0x4b, 0x8d, 0x62, 0x5d, 0xa5, 0xdb,
+       0x39, 0x2b, 0xbf, 0x97, 0x62, 0x21, 0x96, 0x98, 0xe8, 0xd6, 0x36, 0xf8,
+       0xf1, 0x09, 0xa3, 0xbf, 0x3d, 0xdd, 0x8c, 0xe9, 0x22, 0xdd, 0xcc, 0x0e,
+       0x91, 0x6e, 0xf1, 0x43, 0x44, 0xba, 0x68, 0xe9, 0x66, 0x75, 0x8a, 0x74,
+       0xd1, 0xd2, 0x2d, 0x61, 0xac, 0x18, 0x5f, 0x53, 0xe9, 0xa6, 0xde, 0xa7,
+       0xfc, 0xa1, 0xe8, 0x96, 0x64, 0xe3, 0xf7, 0x3c, 0x82, 0xf4, 0x2a, 0x31,
+       0xa5, 0xa2, 0xc9, 0x47, 0x3c, 0x33, 0xe4, 0x00, 0xca, 0xb7, 0x56, 0x1f,
+       0xfa, 0x58, 0x02, 0xf0, 0x1b, 0x7e, 0x48, 0xbf, 0x64, 0xff, 0x6a, 0x7c,
+       0xcb, 0x69, 0x95, 0xc1, 0x6e, 0xa5, 0x33, 0xd0, 0x44, 0x5a, 0xc4, 0xde,
+       0x8b, 0x07, 0x7d, 0x80, 0xfc, 0xbd, 0xc4, 0x89, 0xfa, 0xa0, 0xfe, 0x3e,
+       0x8a, 0x78, 0xf2, 0x21, 0x97, 0xfb, 0x8f, 0xc8, 0x25, 0x5a, 0xae, 0x98,
+       0x7e, 0xf0, 0xf8, 0x02, 0xda, 0xba, 0x19, 0xe4, 0x6d, 0x04, 0xfb, 0x3d,
+       0x1a, 0x18, 0xaf, 0x4a, 0x22, 0xb8, 0x9f, 0x53, 0x88, 0xd3, 0x0e, 0xfb,
+       0xa8, 0x26, 0xaf, 0xc9, 0xb9, 0x48, 0x81, 0x73, 0x4d, 0xe2, 0x5c, 0x94,
+       0x0d, 0xe7, 0x99, 0x76, 0x2c, 0x1f, 0xe4, 0xdf, 0x3b, 0x77, 0x0c, 0x25,
+       0xb8, 0xef, 0x6f, 0x0a, 0x7c, 0x9e, 0x0a, 0xf7, 0x06, 0x1e, 0x1c, 0xd9,
+       0x39, 0x0d, 0xe2, 0x0f, 0x9e, 0xc5, 0xa4, 0x04, 0xd6, 0xaf, 0x59, 0x09,
+       0x6c, 0x7d, 0x5d, 0xc6, 0x4b, 0x5b, 0x02, 0x8b, 0xcf, 0x6c, 0x28, 0xd1,
+       0x11, 0xd7, 0x68, 0xf8, 0x7d, 0x4a, 0x7a, 0xbf, 0x44, 0xc7, 0x6b, 0xb7,
+       0xbb, 0x5e, 0xbb, 0x01, 0xfc, 0xd1, 0x16, 0x76, 0x3f, 0x80, 0xd8, 0x3b,
+       0xdf, 0xb8, 0x1d, 0xdb, 0x47, 0xe1, 0xf7, 0xe1, 0x19, 0xba, 0xfa, 0x6b,
+       0x00, 0x1f, 0xda, 0x1f, 0xbf, 0x2b, 0xee, 0x68, 0xf9, 0xc8, 0xb6, 0x30,
+       0xc4, 0x0e, 0xb7, 0x37, 0x3f, 0x72, 0x25, 0xdc, 0x6b, 0xdd, 0xa4, 0x8b,
+       0xfc, 0x3d, 0x73, 0x81, 0x8d, 0xff, 0xfe, 0x1d, 0x7e, 0x3f, 0x65, 0x44,
+       0x30, 0xdf, 0x42, 0x81, 0x6d, 0x0c, 0xe6, 0x65, 0x78, 0x70, 0x00, 0x1d,
+       0xa7, 0x7a, 0x7a, 0x17, 0xf2, 0x51, 0x95, 0xcb, 0xeb, 0x38, 0xfd, 0x0f,
+       0x96, 0x4d, 0x41, 0xfc, 0x5e, 0x68, 0x91, 0x1c, 0x10, 0xaf, 0x2b, 0xd4,
+       0xdf, 0x71, 0xd3, 0x30, 0x8a, 0xdf, 0xb8, 0xb7, 0x65, 0x7e, 0xaf, 0x97,
+       0xdd, 0x5f, 0x1f, 0xcd, 0xfb, 0xd7, 0x9a, 0xa9, 0xfe, 0xa2, 0xfd, 0xaa,
+       0xff, 0x1b, 0xfc, 0x9e, 0x95, 0x97, 0x4e, 0xca, 0x98, 0x0f, 0x71, 0x74,
+       0x4d, 0x19, 0xde, 0x13, 0xfc, 0xa3, 0xad, 0xf0, 0x30, 0xf0, 0x2b, 0xc7,
+       0xd5, 0x34, 0x0a, 0xe4, 0x29, 0xbf, 0x25, 0x11, 0xcf, 0x71, 0x3d, 0x1f,
+       0x12, 0x27, 0x7e, 0x9a, 0xd5, 0x2a, 0xde, 0x07, 0xcc, 0xe1, 0xf7, 0xb6,
+       0x73, 0xda, 0x88, 0x1f, 0x84, 0xe2, 0xda, 0x63, 0x62, 0xfb, 0xb8, 0x36,
+       0xb1, 0x7e, 0x9d, 0x66, 0xff, 0x39, 0xdf, 0xc6, 0xf5, 0xd4, 0x46, 0x52,
+       0x41, 0xee, 0x36, 0x7e, 0xad, 0x97, 0x60, 0xfd, 0xe8, 0xe8, 0x24, 0xce,
+       0x35, 0x14, 0xdf, 0x8e, 0x45, 0xbd, 0x71, 0xfc, 0x8e, 0xcf, 0x09, 0xfa,
+       0x89, 0x1d, 0x5f, 0xeb, 0x8b, 0x22, 0xdd, 0x8f, 0x59, 0x6e, 0x63, 0xfc,
+       0xdb, 0x64, 0x20, 0x68, 0xbf, 0x37, 0x95, 0x59, 0xf0, 0xde, 0xf9, 0xfe,
+       0xb2, 0x8a, 0xfe, 0xe0, 0x5f, 0x7c, 0x71, 0x97, 0xbb, 0x7f, 0xa4, 0x38,
+       0x65, 0x88, 0x9f, 0x96, 0xc0, 0xbe, 0xbb, 0x77, 0x25, 0x90, 0xb1, 0x20,
+       0x87, 0x6b, 0x25, 0x46, 0xef, 0xfa, 0x8c, 0x92, 0x08, 0xeb, 0x96, 0x2a,
+       0x77, 0xaa, 0x1c, 0xaa, 0xf2, 0x97, 0x51, 0x16, 0xe7, 0x8e, 0x74, 0x0f,
+       0xf5, 0x33, 0x9b, 0x84, 0x72, 0x96, 0x57, 0x36, 0x44, 0x32, 0x80, 0xfc,
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+       0x47, 0xd6, 0xf4, 0x01, 0x7c, 0x3c, 0xcd, 0x9f, 0xe1, 0x7d, 0x32, 0x53,
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+       0xe9, 0xa8, 0x3c, 0x2d, 0xe8, 0xd3, 0x9a, 0x03, 0xf2, 0xfb, 0xba, 0xe2,
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+       0xb5, 0xf0, 0x3e, 0x73, 0xce, 0x3c, 0x92, 0x99, 0x24, 0x33, 0x79, 0x4e,
+       0x1e, 0xc0, 0x09, 0xe1, 0x9d, 0x10, 0x87, 0x24, 0xbc, 0x1f, 0x4e, 0x9e,
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+       0x29, 0x62, 0x0b, 0xc9, 0x08, 0xea, 0xc5, 0xd6, 0x7b, 0xfd, 0xd7, 0x5a,
+       0x7b, 0x9f, 0xcc, 0xcc, 0x49, 0x22, 0xd8, 0xde, 0x4e, 0x3e, 0xbf, 0xed,
+       0x3e, 0x8f, 0xbd, 0xd7, 0x5e, 0xef, 0xb5, 0xf6, 0xda, 0x87, 0x2e, 0xc9,
+       0x77, 0x13, 0x4b, 0x64, 0xcc, 0xb7, 0xd8, 0xc0, 0xb6, 0x4a, 0x8c, 0x7d,
+       0x87, 0xbf, 0x1b, 0x43, 0xad, 0xd9, 0x6e, 0x60, 0x2c, 0x89, 0xb1, 0x96,
+       0x38, 0x3b, 0xb5, 0x4e, 0xe7, 0x0c, 0xc7, 0xd2, 0x84, 0xf0, 0x7e, 0x85,
+       0x63, 0x69, 0x3e, 0x63, 0xd5, 0xd6, 0xd8, 0x5c, 0x16, 0x87, 0x6d, 0x7f,
+       0x3f, 0x8b, 0x85, 0xf1, 0x8a, 0x58, 0xea, 0xd2, 0x02, 0x68, 0x5b, 0xac,
+       0xae, 0x5a, 0x95, 0xb1, 0x25, 0x46, 0xaf, 0xdd, 0x0e, 0xcf, 0x77, 0x4e,
+       0xba, 0x3c, 0xa4, 0x8e, 0xe1, 0x2f, 0xd8, 0xdf, 0x33, 0x92, 0xb1, 0x2e,
+       0x23, 0x6b, 0x94, 0xe2, 0xb0, 0x1f, 0x60, 0x6c, 0x0c, 0x43, 0x50, 0xf8,
+       0xcf, 0xed, 0x56, 0xed, 0xd0, 0x97, 0xf0, 0xff, 0xe1, 0xfd, 0x44, 0x8b,
+       0x2d, 0x20, 0xc3, 0xb8, 0xcc, 0xa3, 0x5c, 0xec, 0xb0, 0xf0, 0x47, 0xbe,
+       0x1b, 0x28, 0x1e, 0x4d, 0x66, 0xcc, 0x28, 0x5e, 0x93, 0x9a, 0xde, 0xf8,
+       0x46, 0xca, 0x65, 0x2c, 0x76, 0x72, 0x11, 0x63, 0x70, 0xdf, 0xca, 0x5c,
+       0x8f, 0xb2, 0x2c, 0xb8, 0x31, 0x8c, 0xa9, 0x9e, 0x18, 0xc6, 0xa2, 0xd8,
+       0x33, 0xf6, 0xf3, 0xd9, 0x8c, 0x19, 0xf0, 0x7d, 0x58, 0x47, 0x57, 0xf3,
+       0xbb, 0xfd, 0x7c, 0x00, 0xc7, 0x1f, 0xfe, 0xe5, 0x4a, 0x0c, 0x83, 0xfb,
+       0x1f, 0x29, 0xc1, 0x18, 0x57, 0x0e, 0x63, 0x17, 0x1e, 0x3c, 0x15, 0xe3,
+       0xb6, 0xc1, 0xf5, 0x07, 0xe5, 0x72, 0x3f, 0xf4, 0x6f, 0x47, 0x40, 0xc6,
+       0x87, 0xf0, 0x92, 0x6f, 0x87, 0x0b, 0xa3, 0x19, 0x7b, 0xc4, 0xee, 0x19,
+       0x81, 0xeb, 0xba, 0x63, 0xdd, 0x7f, 0x8f, 0xf1, 0xda, 0x42, 0xf7, 0xd9,
+       0x03, 0x70, 0x31, 0x95, 0xb1, 0x15, 0x7e, 0x19, 0xe7, 0xe6, 0xf0, 0xc2,
+       0x7f, 0xab, 0xb6, 0x59, 0x19, 0xb3, 0x84, 0xfa, 0x95, 0xf5, 0x09, 0x11,
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+       0x90, 0x11, 0xf1, 0x5e, 0x4e, 0xed, 0x9f, 0xd7, 0x79, 0xdc, 0x83, 0x06,
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+       0x5d, 0x96, 0x3c, 0x33, 0xcb, 0x84, 0xfc, 0xcc, 0x1e, 0xe0, 0xf8, 0xb4,
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+       0x5a, 0x9d, 0xec, 0x61, 0x9c, 0x8f, 0xeb, 0x19, 0xf2, 0xf1, 0x1b, 0x62,
+       0x1c, 0x97, 0xd9, 0xb0, 0x47, 0x05, 0x7e, 0x6d, 0x74, 0x7c, 0x40, 0xfc,
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+       0x38, 0x2e, 0xd7, 0x67, 0x6c, 0xbb, 0x3b, 0x1b, 0xe7, 0x51, 0x0c, 0x12,
+       0xc9, 0xa9, 0x72, 0xc0, 0xe4, 0xaf, 0x85, 0xff, 0xad, 0x8b, 0xe5, 0xfc,
+       0x54, 0x07, 0x3c, 0x82, 0xfc, 0xf7, 0x86, 0xb0, 0xb3, 0xeb, 0x6b, 0x8a,
+       0x5e, 0xb6, 0x02, 0xff, 0x2b, 0x45, 0x6e, 0x75, 0x0d, 0x8c, 0xe3, 0xc7,
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+       0x22, 0x5e, 0xf3, 0xdb, 0xda, 0xa7, 0xa0, 0x3e, 0x6e, 0x78, 0xfb, 0xfd,
+       0x31, 0xe8, 0xaf, 0x22, 0xbd, 0x70, 0x9c, 0xfc, 0x36, 0x88, 0xdd, 0x60,
+       0x3d, 0x97, 0x5e, 0xeb, 0xb7, 0x45, 0x0e, 0x8b, 0x47, 0x3f, 0x70, 0x14,
+       0xbe, 0xe3, 0x00, 0x39, 0x96, 0xdc, 0xdc, 0x9f, 0x94, 0x54, 0x3b, 0x5b,
+       0x04, 0x72, 0x57, 0xeb, 0x66, 0xaa, 0x09, 0xd6, 0x95, 0xa2, 0x8b, 0xeb,
+       0x1a, 0x18, 0xd7, 0x2f, 0xcf, 0xdb, 0x3d, 0x7f, 0xc4, 0xf7, 0x58, 0x46,
+       0x80, 0xec, 0x4d, 0xa1, 0xc3, 0xfb, 0x31, 0xce, 0xaf, 0x8f, 0x57, 0x59,
+       0x7b, 0x7c, 0xaf, 0x7a, 0x59, 0xaf, 0xb7, 0x4c, 0xb9, 0x0f, 0xc8, 0xe8,
+       0xe7, 0xc4, 0xa7, 0x37, 0xbe, 0xb7, 0x04, 0xf5, 0xfb, 0xef, 0xcd, 0xae,
+       0xc1, 0x2a, 0xc2, 0xe5, 0x66, 0x0f, 0x00, 0x3c, 0x3b, 0x0d, 0x4c, 0x61,
+       0xf1, 0xc4, 0x26, 0xc3, 0x94, 0x02, 0x8c, 0x3f, 0xa3, 0x5d, 0x1b, 0x50,
+       0xee, 0x5d, 0xcc, 0xe9, 0x03, 0x39, 0xc3, 0x30, 0x8d, 0x80, 0x84, 0x5f,
+       0xe2, 0x98, 0xb0, 0xb8, 0x55, 0xac, 0x07, 0xde, 0x2f, 0x61, 0xd0, 0x8e,
+       0x45, 0xf8, 0x6e, 0xa0, 0xf5, 0xc9, 0xc8, 0x57, 0xa3, 0x98, 0x47, 0x46,
+       0xfd, 0x35, 0x86, 0xf9, 0xad, 0xd8, 0x76, 0x35, 0xbf, 0xe6, 0x44, 0xbc,
+       0x3d, 0x19, 0xc5, 0xee, 0x40, 0xbf, 0xcf, 0xb2, 0x8d, 0xb9, 0xfd, 0x61,
+       0xfa, 0x63, 0x40, 0x3c, 0xf7, 0xf7, 0x26, 0x25, 0x18, 0x09, 0xee, 0x68,
+       0x63, 0xfd, 0x6c, 0xe4, 0xd7, 0xe8, 0x2f, 0x98, 0x1d, 0xfd, 0xaa, 0xae,
+       0xff, 0x34, 0x29, 0x38, 0x3e, 0x08, 0xc8, 0x74, 0xbc, 0xee, 0x3a, 0x6c,
+       0x60, 0x08, 0xe7, 0x0b, 0x46, 0xbf, 0x3d, 0x0e, 0xfa, 0xc1, 0xe1, 0x8a,
+       0xfa, 0x2c, 0x0b, 0x8d, 0xd7, 0x25, 0xe8, 0xad, 0x8d, 0xfb, 0xa4, 0x49,
+       0x1d, 0xee, 0x40, 0x7d, 0x93, 0xc0, 0xfb, 0x2f, 0x14, 0x72, 0xfb, 0x1c,
+       0xfc, 0xdc, 0xe4, 0x7f, 0x36, 0x13, 0xf1, 0x63, 0x59, 0xe3, 0x0f, 0x93,
+       0x2f, 0x67, 0x3c, 0xf7, 0x5b, 0xbd, 0x49, 0x45, 0xf1, 0xf1, 0xd0, 0xd6,
+       0x37, 0x47, 0x33, 0x9c, 0x7f, 0x6c, 0x4b, 0xb4, 0x01, 0xe9, 0xf0, 0xf2,
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+       0x94, 0x99, 0x3b, 0x6c, 0xde, 0x9b, 0x54, 0x2b, 0x73, 0x87, 0xe5, 0x03,
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+       0x16, 0x3d, 0xf4, 0x7c, 0xdb, 0x02, 0xeb, 0xf4, 0xc1, 0xfa, 0x02, 0xb0,
+       0x4e, 0x1f, 0xf8, 0x5d, 0x07, 0xd6, 0xd9, 0xa9, 0x7f, 0x68, 0x9d, 0x93,
+       0xfa, 0x1a, 0xbf, 0x56, 0x37, 0xff, 0x36, 0x01, 0xfd, 0x36, 0x8d, 0x4f,
+       0x4b, 0x13, 0x38, 0xdf, 0x8c, 0xdf, 0xb7, 0x29, 0x81, 0xd9, 0x42, 0xf4,
+       0xd2, 0xf0, 0xf5, 0xa1, 0xb0, 0x57, 0x7b, 0xa3, 0x34, 0x7f, 0xc3, 0x35,
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+       0x63, 0x42, 0xf6, 0x6b, 0xfe, 0xe9, 0x32, 0xf2, 0x37, 0x34, 0xfb, 0x35,
+       0x5f, 0x5e, 0x54, 0x4a, 0x6a, 0x53, 0xd8, 0x2f, 0x4c, 0x23, 0xa3, 0x5e,
+       0xd3, 0xdb, 0xa9, 0xb9, 0xea, 0x62, 0x23, 0xeb, 0xcd, 0x3e, 0x2d, 0x88,
+       0xec, 0x97, 0xb7, 0x6d, 0x54, 0x62, 0xa8, 0x67, 0x20, 0x3a, 0x49, 0x92,
+       0xc0, 0x87, 0xf0, 0xb3, 0x35, 0x38, 0xce, 0x30, 0x0f, 0xc1, 0xa9, 0xa7,
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+       0x6f, 0xce, 0xa0, 0x4c, 0x23, 0xc2, 0xdf, 0xc3, 0xae, 0x8a, 0x75, 0xe2,
+       0x40, 0x98, 0x87, 0xb8, 0x5e, 0xbb, 0xfa, 0xb5, 0x8e, 0x9f, 0xaf, 0x5c,
+       0x28, 0x79, 0x2b, 0xb7, 0x17, 0xbe, 0xed, 0x8b, 0x7f, 0xf5, 0xf7, 0x35,
+       0x7d, 0x50, 0x86, 0x13, 0xe4, 0x51, 0xeb, 0x43, 0xbf, 0xc2, 0x98, 0x98,
+       0x4c, 0x74, 0x2b, 0xbb, 0x6a, 0x62, 0x6e, 0xb0, 0x1b, 0x2c, 0x23, 0x8a,
+       0x7d, 0x1a, 0x66, 0x57, 0x58, 0xc5, 0x50, 0xe2, 0x9f, 0x7b, 0x85, 0x1d,
+       0xee, 0x8b, 0x7f, 0xaa, 0xae, 0xca, 0xcc, 0x9b, 0x1f, 0xe2, 0x23, 0x63,
+       0xe3, 0x13, 0x56, 0xe4, 0xa3, 0x7d, 0xca, 0x46, 0x2b, 0xe6, 0x27, 0x27,
+       0xdb, 0x66, 0xd5, 0xc6, 0x01, 0x9e, 0x4a, 0xfe, 0x54, 0x34, 0x17, 0xfd,
+       0xbc, 0xea, 0x0e, 0x03, 0xc3, 0x14, 0x56, 0x69, 0xd3, 0x17, 0x07, 0x31,
+       0xae, 0xaf, 0x7e, 0x8f, 0xb9, 0x50, 0x2f, 0x16, 0x35, 0xb5, 0x16, 0x23,
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+       0x7f, 0xb1, 0xb1, 0xa9, 0xd6, 0x8a, 0xfe, 0x54, 0x63, 0xa2, 0x4c, 0x71,
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+       0xcf, 0x5d, 0x9e, 0xe1, 0xee, 0xe5, 0xfe, 0x19, 0x71, 0xbf, 0xe4, 0xe3,
+       0x3c, 0xe2, 0xa3, 0xb2, 0x47, 0x41, 0xae, 0x31, 0x0e, 0x4d, 0x8a, 0xa1,
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+       0x32, 0xf9, 0xb3, 0xc1, 0x5b, 0x25, 0xca, 0x8b, 0x94, 0x01, 0xbb, 0x60,
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+       0x18, 0xb5, 0x81, 0x78, 0x4a, 0xeb, 0x0f, 0xce, 0xdb, 0xc0, 0x04, 0x23,
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+       0x9e, 0x66, 0x8e, 0x8b, 0xec, 0xcf, 0x72, 0xf7, 0xa8, 0x37, 0x88, 0x90,
+       0x7f, 0xbd, 0x5e, 0xd7, 0xe4, 0x7e, 0x5e, 0xb3, 0x4c, 0xfb, 0x72, 0xf3,
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+       0x97, 0x2e, 0xb0, 0x77, 0xe6, 0x5e, 0xf8, 0x45, 0xb3, 0x17, 0x5a, 0x3c,
+       0x5e, 0x06, 0xf2, 0x4a, 0xf2, 0x7e, 0x91, 0xef, 0x67, 0x94, 0x5e, 0x4d,
+       0x65, 0xbe, 0xfc, 0x50, 0x3c, 0xde, 0xad, 0x2f, 0xc0, 0x9f, 0x70, 0xf5,
+       0xe2, 0xe7, 0x3c, 0x9d, 0x98, 0x45, 0x72, 0xd4, 0xad, 0x5f, 0x34, 0xfd,
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+       0x85, 0x43, 0x98, 0x97, 0x73, 0x7e, 0x41, 0xf9, 0x96, 0x6a, 0x88, 0xf3,
+       0x29, 0xde, 0x67, 0xbf, 0x25, 0xb8, 0x50, 0xcf, 0x49, 0xf1, 0x21, 0x39,
+       0xd0, 0xfb, 0x19, 0x5a, 0x5e, 0xd7, 0x2a, 0xf2, 0x08, 0x7a, 0xbe, 0xe8,
+       0xce, 0xf3, 0xcd, 0x35, 0x52, 0x1d, 0x8c, 0xc6, 0x17, 0x65, 0x76, 0x2e,
+       0x1f, 0x65, 0x73, 0x65, 0xca, 0xbb, 0xeb, 0xf9, 0x44, 0x9b, 0x4f, 0xcf,
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+       0x47, 0x73, 0xa2, 0xd8, 0x57, 0x1d, 0xc4, 0x06, 0x5d, 0x0f, 0x5f, 0x68,
+       0xfc, 0xa0, 0xf1, 0x87, 0xde, 0x8e, 0x1c, 0xd3, 0xe5, 0x67, 0xfa, 0xb2,
+       0x23, 0x6f, 0xa2, 0x1d, 0x19, 0xdd, 0xb7, 0x1d, 0x79, 0x7d, 0x98, 0x91,
+       0xf4, 0xb5, 0xde, 0x7e, 0x68, 0xf6, 0xe2, 0x77, 0x49, 0x5c, 0x2f, 0x67,
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+       0x16, 0x37, 0x3d, 0xb1, 0x89, 0xf7, 0x8d, 0x94, 0x9f, 0x2b, 0x54, 0x5a,
+       0x15, 0x0b, 0x8c, 0x3b, 0xd3, 0x25, 0xb9, 0x30, 0xaf, 0xe3, 0x16, 0xf9,
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+       0xc6, 0xd7, 0xec, 0x80, 0x36, 0xaf, 0x5e, 0xff, 0xf6, 0x15, 0xb7, 0x69,
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+       0xc8, 0xc3, 0xce, 0x4f, 0xe2, 0xf1, 0xc1, 0xad, 0x49, 0x3c, 0xee, 0xec,
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+       0xfd, 0x1b, 0xd4, 0x07, 0xa5, 0x72, 0x9b, 0x8c, 0xf9, 0xfb, 0xae, 0x20,
+       0xc8, 0x08, 0x3c, 0x3f, 0x69, 0x41, 0xa0, 0x18, 0xe3, 0xa0, 0xc9, 0xac,
+       0xbd, 0x16, 0xe5, 0x7b, 0x02, 0xd2, 0xb1, 0x17, 0xfa, 0xfd, 0x2a, 0x49,
+       0x8b, 0xb3, 0x7b, 0xcf, 0xef, 0x17, 0x37, 0x73, 0x3f, 0xae, 0x38, 0x46,
+       0x26, 0x3f, 0x6e, 0x8a, 0xaf, 0xbd, 0x18, 0xf7, 0xad, 0xa6, 0x28, 0x92,
+       0xab, 0x16, 0x9f, 0xd5, 0xe5, 0xf7, 0x5f, 0xd1, 0xc5, 0x1f, 0xa1, 0xfc,
+       0xbe, 0xaa, 0xf0, 0xfa, 0x43, 0x5d, 0xfe, 0xbe, 0x91, 0xeb, 0x99, 0xeb,
+       0xcd, 0xeb, 0x4f, 0x40, 0xdd, 0x06, 0x7c, 0xbc, 0x5e, 0xe3, 0x73, 0xa1,
+       0x6f, 0x58, 0x1f, 0xf9, 0xfd, 0x9d, 0x26, 0xbe, 0xef, 0x13, 0x3c, 0x69,
+       0x64, 0xe8, 0x07, 0xb3, 0x0b, 0x89, 0xbd, 0xe6, 0x63, 0xae, 0x95, 0xe7,
+       0xdf, 0xd7, 0x12, 0xed, 0x56, 0x63, 0x71, 0x9f, 0x8e, 0xfb, 0xeb, 0xfb,
+       0x5a, 0xd2, 0xdc, 0x6a, 0x6e, 0xdf, 0xcf, 0xe7, 0x76, 0x04, 0x8b, 0xd0,
+       0x3c, 0xee, 0xdc, 0x3e, 0x5b, 0xa1, 0xfa, 0x35, 0x91, 0x1f, 0xed, 0xb1,
+       0x7f, 0xd2, 0xc7, 0xfe, 0x88, 0xbb, 0xd1, 0x7e, 0x08, 0xd5, 0x69, 0x5f,
+       0xfb, 0x21, 0xc5, 0x5f, 0xaa, 0x94, 0xf6, 0xb9, 0x5e, 0xbc, 0x69, 0x75,
+       0x0b, 0x4c, 0xd4, 0x3f, 0xdd, 0xc8, 0xb4, 0x9f, 0x9b, 0xe4, 0x74, 0xe7,
+       0xf9, 0x68, 0x37, 0xf2, 0xf9, 0xce, 0xf3, 0x69, 0x6e, 0x84, 0xeb, 0x79,
+       0xc1, 0xa7, 0x1a, 0xdf, 0xef, 0x3b, 0x77, 0x39, 0x9a, 0xf6, 0x41, 0x4d,
+       0x6e, 0x15, 0xf7, 0x8f, 0x83, 0x0e, 0x8b, 0xeb, 0x59, 0xe2, 0x5b, 0xce,
+       0xef, 0xf5, 0xa9, 0x43, 0xfc, 0xb8, 0x4f, 0xfb, 0x1b, 0x21, 0x17, 0x3b,
+       0xa3, 0x83, 0xc7, 0xb2, 0x13, 0xc3, 0xf7, 0x3d, 0xf8, 0x3e, 0x47, 0xcb,
+       0xba, 0x47, 0x67, 0x9f, 0x33, 0xd2, 0x7e, 0xb9, 0x84, 0xf9, 0x48, 0x6d,
+       0x7f, 0xd9, 0x07, 0x72, 0x43, 0x75, 0x3d, 0xf1, 0x8c, 0xe2, 0x0f, 0x23,
+       0xab, 0x67, 0x38, 0x6f, 0xad, 0x9b, 0xfd, 0x1a, 0xdb, 0x29, 0x93, 0xd4,
+       0x38, 0xc4, 0xfb, 0xe5, 0x44, 0x6d, 0x1f, 0x53, 0x8d, 0xa3, 0x3c, 0xc4,
+       0xb7, 0x57, 0xa8, 0xce, 0x50, 0x8f, 0xff, 0xdd, 0xeb, 0x98, 0x07, 0xeb,
+       0x51, 0x1a, 0xd6, 0x59, 0x3c, 0x0a, 0xc8, 0xff, 0xab, 0xeb, 0xec, 0xd4,
+       0x6f, 0x5c, 0xe7, 0xa4, 0x76, 0xff, 0x3a, 0x95, 0xda, 0x87, 0x8e, 0xc7,
+       0x3e, 0x80, 0x76, 0xbf, 0xda, 0x6d, 0xf2, 0x28, 0x61, 0xfa, 0xe3, 0x9d,
+       0x64, 0xee, 0x77, 0xe5, 0x65, 0x7f, 0x52, 0x4c, 0xc5, 0xdf, 0x7f, 0x63,
+       0x54, 0x87, 0x3e, 0xe5, 0xc1, 0x0e, 0x19, 0xf5, 0xc5, 0x8d, 0x57, 0x61,
+       0x1d, 0x11, 0x75, 0x27, 0xca, 0x65, 0xc4, 0x37, 0xe5, 0x37, 0xb3, 0x42,
+       0xfd, 0x4c, 0x69, 0x71, 0x0c, 0xf6, 0x6f, 0xbc, 0x0a, 0xfd, 0xb0, 0xe7,
+       0xaf, 0x24, 0x39, 0xb8, 0x3d, 0xaa, 0x53, 0xea, 0x46, 0x27, 0x93, 0xb4,
+       0x10, 0x5f, 0xfc, 0x2d, 0xc9, 0xdd, 0x91, 0x04, 0xd7, 0xef, 0x71, 0x78,
+       0x3e, 0xc1, 0x76, 0xb7, 0x34, 0xff, 0xe0, 0x25, 0x46, 0xfd, 0x73, 0xbc,
+       0x7f, 0xab, 0x7c, 0x09, 0x9e, 0xcb, 0x0f, 0x14, 0x52, 0x5e, 0x39, 0x1f,
+       0xf3, 0xca, 0x79, 0x34, 0xec, 0x42, 0xc4, 0xdf, 0xe8, 0x56, 0x13, 0xed,
+       0x97, 0x6b, 0xf9, 0xdd, 0x3c, 0x4d, 0xfe, 0xbe, 0x8e, 0xcc, 0x33, 0xe7,
+       0x8b, 0xbc, 0xee, 0xab, 0xac, 0x83, 0xf2, 0xcd, 0x05, 0x16, 0x08, 0xb4,
+       0x0c, 0x08, 0x17, 0xa7, 0x9f, 0x5b, 0x9a, 0xe7, 0x94, 0x30, 0x1f, 0x98,
+       0x64, 0x72, 0x61, 0xbd, 0xc3, 0xe8, 0x2c, 0x4f, 0x3e, 0xe6, 0x63, 0x5b,
+       0x93, 0x18, 0xc5, 0x47, 0xad, 0xad, 0xc9, 0x19, 0x6a, 0x0e, 0x72, 0x0f,
+       0xcf, 0xfb, 0xba, 0xb5, 0xbc, 0x2f, 0xfb, 0xfe, 0xbc, 0xef, 0x91, 0x8f,
+       0x62, 0x7d, 0xa4, 0xb7, 0xae, 0x9a, 0x68, 0x7f, 0xfa, 0xc8, 0xa9, 0x58,
+       0x57, 0x80, 0xf6, 0x0b, 0x2d, 0xe4, 0xff, 0x69, 0xf5, 0xc8, 0x2d, 0xd1,
+       0xbc, 0xce, 0x80, 0x65, 0x2c, 0xa0, 0x3c, 0xd3, 0x8d, 0xa2, 0x9e, 0xd1,
+       0x62, 0xf6, 0x9a, 0x93, 0x49, 0x5f, 0x05, 0x0e, 0x9e, 0x80, 0xf7, 0x7e,
+       0x7f, 0x99, 0xf1, 0x7d, 0xc7, 0xf6, 0x0f, 0x69, 0x5f, 0xbb, 0xd8, 0x30,
+       0x3c, 0x05, 0xeb, 0x7e, 0x0f, 0x4a, 0x43, 0xe3, 0xb0, 0x7d, 0xea, 0xa3,
+       0xd8, 0x1c, 0x6a, 0x4f, 0xc5, 0x5e, 0x44, 0xfc, 0xb4, 0x18, 0xac, 0x2a,
+       0xce, 0x7b, 0x66, 0x9d, 0x5a, 0x82, 0x75, 0x6d, 0x27, 0xd6, 0xb1, 0x12,
+       0xac, 0x63, 0x7b, 0x6b, 0x9d, 0x85, 0xda, 0x93, 0xeb, 0xec, 0xd4, 0x9e,
+       0x5a, 0xe7, 0xa4, 0xf6, 0x75, 0xb8, 0x8e, 0xfc, 0x73, 0x1c, 0x9e, 0x47,
+       0x7e, 0x71, 0xbf, 0x65, 0xa3, 0x7d, 0x92, 0x29, 0x6f, 0xd9, 0x14, 0x6c,
+       0xf3, 0x16, 0xc6, 0x50, 0xbb, 0xfb, 0xb6, 0x18, 0x13, 0xc2, 0xdb, 0x12,
+       0xcb, 0xb6, 0x6b, 0xf3, 0x60, 0xbd, 0x5a, 0x20, 0x3a, 0xd0, 0x80, 0xc9,
+       0xfe, 0xd6, 0xa7, 0xbc, 0x8f, 0x59, 0xfa, 0x81, 0xdd, 0x33, 0x7b, 0x47,
+       0x4a, 0xa3, 0x18, 0x6b, 0x7b, 0xca, 0x3b, 0x5d, 0x99, 0x0c, 0xe3, 0x4e,
+       0xed, 0xff, 0x93, 0xaf, 0xe0, 0xfe, 0x9b, 0xc9, 0xcb, 0x1e, 0xb3, 0x00,
+       0x5c, 0x73, 0x4f, 0xd9, 0x1a, 0xda, 0xa0, 0xff, 0x76, 0xf2, 0xf2, 0xc7,
+       0x6c, 0xa8, 0x6f, 0x8f, 0x47, 0x83, 0xd2, 0xc3, 0xf5, 0xae, 0x38, 0xee,
+       0x1e, 0x04, 0x74, 0x43, 0xa5, 0x90, 0xc6, 0x05, 0x97, 0x8d, 0x83, 0x7e,
+       0x82, 0xd6, 0x5f, 0x31, 0xbd, 0x64, 0x12, 0x63, 0xb7, 0x14, 0x77, 0x64,
+       0x33, 0x60, 0xad, 0xec, 0xe4, 0x95, 0xd3, 0x2d, 0x80, 0xc7, 0x5b, 0xac,
+       0xde, 0x1f, 0x63, 0xdf, 0xe4, 0x4b, 0x9a, 0x5e, 0xd2, 0x0f, 0xfb, 0xcc,
+       0x87, 0xf5, 0x60, 0x41, 0xc9, 0x48, 0x71, 0x3f, 0xcb, 0x90, 0x12, 0xb1,
+       0xfe, 0x65, 0xa6, 0xc3, 0xfb, 0x46, 0x72, 0x58, 0xfd, 0x9e, 0x5b, 0xfa,
+       0x13, 0xed, 0x33, 0x8d, 0x71, 0x4b, 0xcc, 0x41, 0x87, 0x1f, 0x8c, 0xb4,
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+       0x44, 0x1a, 0x7f, 0x0e, 0xe1, 0xcf, 0x89, 0x1b, 0x85, 0xd7, 0xca, 0x33,
+       0x1c, 0x11, 0xf7, 0xdb, 0x6e, 0xb3, 0x92, 0x9d, 0xa8, 0x78, 0x2b, 0x87,
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+       0xdb, 0x36, 0x03, 0xf7, 0xd3, 0x2b, 0xde, 0xaa, 0x28, 0xa7, 0xfb, 0x06,
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+       0x3c, 0xcc, 0xaf, 0x4d, 0x1b, 0x94, 0x5a, 0xa2, 0x44, 0xf8, 0x81, 0x03,
+       0x49, 0xfe, 0xf3, 0x44, 0x7e, 0xaf, 0xd0, 0x30, 0x7c, 0xd3, 0x24, 0x80,
+       0xff, 0xde, 0xa3, 0x7c, 0x9f, 0xa2, 0x22, 0x27, 0x33, 0xe2, 0xf9, 0x19,
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+       0x89, 0xa3, 0x24, 0xbc, 0x0e, 0x75, 0x6e, 0x45, 0x6a, 0x44, 0xff, 0x96,
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+       0x94, 0x80, 0x1e, 0x38, 0x0a, 0xed, 0x52, 0x60, 0xc1, 0x02, 0x51, 0x07,
+       0xa5, 0xe5, 0x9f, 0x0a, 0x05, 0x4b, 0x15, 0xb6, 0x8b, 0xbc, 0xac, 0xc2,
+       0xe3, 0xeb, 0x61, 0xf0, 0x87, 0x7a, 0xb0, 0xc4, 0x16, 0x69, 0xa7, 0x77,
+       0x47, 0x73, 0x3b, 0x5f, 0xce, 0xd6, 0xd0, 0x06, 0x49, 0xf9, 0x11, 0xbe,
+       0xbf, 0x5d, 0x96, 0x68, 0xfc, 0x24, 0xdc, 0x4e, 0x94, 0xcb, 0x15, 0x36,
+       0x5e, 0x97, 0x15, 0x89, 0x87, 0xbc, 0xa3, 0x46, 0xb2, 0x97, 0x79, 0x31,
+       0x92, 0x1f, 0xe3, 0xfa, 0x92, 0xa3, 0x4b, 0xeb, 0xd0, 0xf4, 0x96, 0x67,
+       0x44, 0xbe, 0xaf, 0xf9, 0x61, 0xe5, 0x02, 0x3e, 0x6d, 0x5e, 0xe6, 0x73,
+       0xb7, 0xa3, 0x3f, 0xa2, 0xc1, 0xad, 0xcd, 0xaf, 0xc1, 0x5f, 0x2e, 0x2f,
+       0x2a, 0xa1, 0x7c, 0xf7, 0x35, 0xd6, 0xa1, 0x87, 0x97, 0xc1, 0x7a, 0x50,
+       0x3f, 0xe8, 0xe1, 0x68, 0x4a, 0x16, 0xfe, 0x1a, 0xf8, 0x1f, 0xe4, 0xaf,
+       0x89, 0x73, 0x24, 0xf0, 0x4b, 0xec, 0xcd, 0x7e, 0x6b, 0xfe, 0x7a, 0x05,
+       0xe8, 0x2b, 0x47, 0xb8, 0xbe, 0xb2, 0x49, 0x89, 0x58, 0xb7, 0xd7, 0x97,
+       0xbe, 0xd2, 0xc6, 0xed, 0xcb, 0x2f, 0xd3, 0xc6, 0x9d, 0xe9, 0xf0, 0xd0,
+       0xfb, 0xee, 0x1d, 0x9f, 0x9e, 0x9a, 0x20, 0x87, 0xf5, 0x33, 0x3f, 0x4e,
+       0x88, 0x0f, 0xef, 0xbf, 0xf8, 0xe9, 0xa6, 0x88, 0xfb, 0x49, 0x1f, 0xcf,
+       0x71, 0x84, 0xf7, 0xb7, 0x7e, 0x3a, 0x07, 0xef, 0x4f, 0x51, 0xd4, 0x5a,
+       0x1b, 0xf0, 0xe5, 0x31, 0x26, 0xb9, 0x7c, 0xc8, 0x07, 0x6d, 0xaa, 0x12,
+       0x03, 0xf4, 0x28, 0x3e, 0xed, 0xae, 0xc3, 0xb6, 0xf4, 0x43, 0x2f, 0x96,
+       0xab, 0xb2, 0xa9, 0xe7, 0x7c, 0x75, 0xd8, 0x4e, 0xbc, 0xe8, 0x6f, 0x33,
+       0xc3, 0xba, 0x6e, 0x1a, 0x26, 0xab, 0x18, 0xbf, 0x6b, 0x7e, 0x88, 0x1e,
+       0xde, 0xbf, 0x26, 0xf3, 0xbc, 0xc3, 0xb1, 0xab, 0xaa, 0x15, 0xf7, 0x59,
+       0x77, 0xfb, 0x54, 0x2b, 0xfa, 0xf3, 0xbb, 0x1f, 0x54, 0xad, 0xe8, 0x87,
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+       0xf3, 0x7a, 0xc5, 0xbf, 0x24, 0xf3, 0xba, 0x83, 0x4e, 0xf1, 0xbe, 0xd6,
+       0xfa, 0x8d, 0xde, 0x4e, 0x84, 0x1b, 0xeb, 0xcc, 0xd1, 0x37, 0xa8, 0xfa,
+       0x26, 0x48, 0x75, 0xe5, 0xc7, 0xd0, 0xbf, 0xca, 0xe9, 0xe9, 0x5f, 0x1d,
+       0x53, 0xfc, 0x36, 0x9c, 0xef, 0xd8, 0x83, 0x7e, 0x5b, 0xf8, 0x7e, 0xe2,
+       0xf5, 0xfa, 0x57, 0x7f, 0x04, 0x1e, 0x43, 0x38, 0x0a, 0x99, 0xe4, 0x09,
+       0xd7, 0x23, 0xc5, 0x96, 0x28, 0x4f, 0xb8, 0xdc, 0x96, 0xda, 0x1d, 0x11,
+       0xfd, 0x93, 0xc2, 0x0f, 0x99, 0xea, 0x4c, 0x8d, 0x78, 0xef, 0x26, 0x35,
+       0x33, 0xe2, 0x39, 0xf0, 0x1b, 0x87, 0xa1, 0x5f, 0x52, 0x6b, 0x62, 0x54,
+       0x6f, 0xeb, 0x33, 0xf0, 0x7a, 0x5b, 0x3d, 0x1e, 0x57, 0xa4, 0xf0, 0xf8,
+       0xce, 0x65, 0xb3, 0xa3, 0x3b, 0x83, 0xfb, 0x66, 0x72, 0x6f, 0xe7, 0x91,
+       0x5c, 0xc5, 0x86, 0x5e, 0xcf, 0xb7, 0xa5, 0xa4, 0x70, 0x7f, 0xf0, 0x3f,
+       0x52, 0x18, 0xc1, 0x35, 0x2b, 0x85, 0xc3, 0xa7, 0xaf, 0xaf, 0xd5, 0xf7,
+       0x6b, 0xf1, 0x7c, 0x0f, 0xe2, 0x93, 0xb9, 0x9c, 0xc8, 0xe7, 0x2e, 0xab,
+       0xe1, 0x0a, 0xb8, 0xbc, 0xac, 0xe0, 0xe9, 0x27, 0xa6, 0x53, 0x5d, 0x6d,
+       0xbe, 0xe1, 0xde, 0x2c, 0xe8, 0x57, 0x3c, 0xbd, 0x75, 0x3a, 0xaf, 0xab,
+       0x35, 0xec, 0xc1, 0x3a, 0xdb, 0x19, 0x4f, 0x3f, 0xcf, 0xef, 0xdf, 0x60,
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+       0x8a, 0xe2, 0xf5, 0x09, 0x55, 0x51, 0xa2, 0x3e, 0xb4, 0x6e, 0x74, 0x44,
+       0xdc, 0xa3, 0x18, 0x3e, 0x7e, 0x6a, 0x21, 0xc6, 0x9f, 0xfb, 0x8d, 0x0c,
+       0xf3, 0xfc, 0x8f, 0x99, 0xc0, 0x0e, 0xe6, 0x85, 0xf6, 0xd9, 0xad, 0x66,
+       0x1e, 0xaf, 0x5a, 0x4d, 0xbc, 0x0e, 0x7c, 0x7d, 0xe6, 0xa9, 0xf5, 0xa8,
+       0x3f, 0x3e, 0x8b, 0xf2, 0xe6, 0xa5, 0x50, 0x9e, 0xb1, 0x48, 0x45, 0x3c,
+       0x5e, 0xb4, 0x5b, 0xa8, 0x3e, 0xf4, 0xbe, 0x7d, 0xa5, 0x29, 0xc8, 0x07,
+       0xb3, 0x52, 0x78, 0xde, 0x2b, 0x7b, 0xcf, 0x44, 0x27, 0x9d, 0x2f, 0xfb,
+       0xe7, 0xc1, 0x51, 0xfc, 0x7d, 0x70, 0x60, 0xfd, 0x30, 0x8e, 0x73, 0x71,
+       0x77, 0x36, 0xf9, 0xe5, 0xd9, 0x03, 0x18, 0x9d, 0x27, 0xd1, 0xe8, 0x01,
+       0xe1, 0x33, 0x5d, 0x8f, 0x82, 0xf0, 0x81, 0xce, 0x63, 0x30, 0xb7, 0x13,
+       0xf3, 0x6f, 0xb5, 0x0e, 0x13, 0x8d, 0x33, 0x2b, 0x85, 0xf3, 0xe3, 0xf5,
+       0xb6, 0x3d, 0xea, 0x89, 0xe3, 0x0c, 0x6b, 0x76, 0x41, 0xbb, 0x20, 0x85,
+       0xc7, 0xcd, 0xb7, 0xe2, 0xbc, 0x04, 0x6f, 0xb0, 0xff, 0x2c, 0xdc, 0xd0,
+       0xb3, 0x07, 0xfb, 0xcf, 0x1e, 0xc9, 0xfb, 0x48, 0x6f, 0x59, 0xce, 0x0b,
+       0xa2, 0x7f, 0x1b, 0xfc, 0x51, 0x0c, 0xed, 0xc3, 0xbc, 0x1f, 0xcd, 0xf1,
+       0xc6, 0x32, 0x82, 0xb4, 0x6f, 0xf3, 0xee, 0xa2, 0x6c, 0xd7, 0x06, 0xba,
+       0xce, 0xf1, 0xb8, 0xc0, 0x3f, 0xb0, 0xb6, 0x43, 0xc5, 0xfa, 0x0f, 0x7f,
+       0x3f, 0xac, 0xb7, 0x18, 0xe8, 0xf4, 0x2e, 0x45, 0x7c, 0xdc, 0x66, 0xf6,
+       0x0f, 0x26, 0xbe, 0xb2, 0xad, 0x89, 0xc1, 0x79, 0xae, 0xb7, 0xde, 0xb8,
+       0xef, 0xf9, 0x21, 0xe0, 0x04, 0x7b, 0x32, 0x7f, 0x3c, 0xa7, 0x97, 0x36,
+       0x3f, 0xe0, 0xd8, 0x82, 0x74, 0x7c, 0x57, 0x9c, 0x3b, 0xd1, 0xe0, 0x01,
+       0x38, 0x7e, 0x8c, 0x70, 0x68, 0x70, 0x75, 0xc3, 0xa3, 0xab, 0x3f, 0xef,
+       0x14, 0x7e, 0x7b, 0x27, 0x8e, 0x97, 0x1b, 0xca, 0x53, 0x57, 0xff, 0xc9,
+       0x40, 0x79, 0x8a, 0x6a, 0x09, 0xf4, 0x24, 0xf4, 0xf7, 0x7c, 0xc8, 0x5c,
+       0x3e, 0x95, 0xe8, 0x43, 0x79, 0x50, 0xdc, 0xd2, 0xc2, 0xf9, 0xc6, 0x9f,
+       0x58, 0x52, 0x6c, 0x83, 0xb6, 0xa0, 0x71, 0x15, 0x8f, 0x8f, 0xdb, 0x95,
+       0x88, 0xbc, 0x98, 0x66, 0xcf, 0x26, 0x8a, 0xe7, 0xc7, 0xbe, 0xa7, 0x44,
+       0xd8, 0xa3, 0x89, 0x22, 0xfe, 0x1d, 0xaf, 0xcb, 0x4f, 0x4e, 0x6c, 0x9c,
+       0x4e, 0xe7, 0xf8, 0x26, 0xea, 0xe2, 0xe2, 0x5f, 0xa4, 0x88, 0xbc, 0x65,
+       0x1a, 0x4b, 0x0b, 0xcf, 0x23, 0xac, 0x15, 0xf1, 0xc6, 0xe5, 0xb6, 0x81,
+       0x71, 0xe8, 0x9f, 0x2a, 0x10, 0xe7, 0xca, 0x80, 0x6f, 0x93, 0x2a, 0xb3,
+       0x71, 0xf1, 0x21, 0xbd, 0xd0, 0xb0, 0x8e, 0x45, 0x9c, 0x53, 0xd4, 0xf8,
+       0x70, 0xe4, 0x69, 0xfb, 0x9d, 0x38, 0xdf, 0xc8, 0xd3, 0xec, 0x0e, 0xf2,
+       0x07, 0xb4, 0x71, 0xbb, 0xf3, 0x13, 0x1c, 0x2f, 0x97, 0xdf, 0xe3, 0x78,
+       0x19, 0xd5, 0x31, 0xec, 0xe9, 0x49, 0xd0, 0x37, 0x1e, 0x31, 0x32, 0xbf,
+       0x1a, 0x5a, 0xe7, 0x04, 0x0e, 0x2a, 0x83, 0x30, 0x87, 0xe2, 0xa4, 0xcb,
+       0x17, 0x6c, 0x64, 0x5f, 0xc6, 0x1c, 0x9d, 0x43, 0xf5, 0xde, 0x66, 0xa7,
+       0x81, 0xa9, 0x61, 0xeb, 0x8f, 0x52, 0xa3, 0x99, 0x1a, 0xa6, 0x2f, 0xad,
+       0xc3, 0xe2, 0x23, 0xfa, 0xb2, 0xa0, 0x4f, 0x5d, 0x54, 0xa4, 0x1f, 0x90,
+       0x2f, 0xe6, 0x89, 0x71, 0xa5, 0x45, 0x8c, 0xb7, 0x3f, 0xbe, 0xec, 0x08,
+       0xfa, 0x05, 0xf9, 0xb6, 0xe5, 0xe4, 0x17, 0xc4, 0x8d, 0x1b, 0x18, 0x31,
+       0x1e, 0x6b, 0x53, 0x22, 0xfc, 0x83, 0x3c, 0xe6, 0x71, 0x63, 0xdc, 0xe8,
+       0x02, 0xfa, 0xe2, 0x7e, 0xd9, 0x98, 0xd3, 0x4a, 0x84, 0x1f, 0x30, 0x2e,
+       0xb0, 0x91, 0xce, 0xa1, 0x8e, 0xfb, 0x30, 0xf2, 0xfa, 0x84, 0x73, 0x91,
+       0xfd, 0x03, 0x7d, 0xd1, 0xa5, 0x2f, 0xfc, 0xb1, 0xdc, 0xa7, 0xd1, 0x2f,
+       0xfc, 0xa1, 0xf8, 0x73, 0xb8, 0x23, 0xf1, 0x97, 0x50, 0x1e, 0x89, 0xbf,
+       0x24, 0x4f, 0x24, 0xfe, 0x52, 0x16, 0x44, 0xe2, 0x27, 0xd5, 0x1b, 0x89,
+       0x8f, 0xf4, 0xe5, 0x23, 0x22, 0xee, 0xf7, 0x5b, 0x93, 0x17, 0xd1, 0x1f,
+       0xf0, 0xc0, 0x84, 0x88, 0xe7, 0x33, 0xc1, 0x80, 0x85, 0xf7, 0xb3, 0x1e,
+       0x9d, 0x16, 0xf1, 0xfc, 0xe0, 0x8d, 0xb3, 0x23, 0xfa, 0x43, 0x37, 0xdf,
+       0x16, 0xf1, 0xfc, 0x70, 0xff, 0x92, 0x88, 0xfb, 0xd9, 0xdb, 0x56, 0xfe,
+       0x20, 0x7a, 0x8f, 0xac, 0x5f, 0x1b, 0xf1, 0xbc, 0x9e, 0xde, 0x37, 0x34,
+       0xfe, 0x34, 0x62, 0x7c, 0x8d, 0xde, 0x3e, 0xf8, 0xfb, 0xdf, 0xa4, 0x37,
+       0x73, 0x0a, 0xff, 0x50, 0xd0, 0x3b, 0x51, 0xd8, 0x59, 0x87, 0x9b, 0xd7,
+       0xad, 0x75, 0x19, 0x6d, 0x8f, 0xe2, 0x79, 0x7c, 0x3c, 0x36, 0x82, 0xfa,
+       0xce, 0x81, 0xe7, 0xe9, 0x63, 0xd1, 0xfe, 0xab, 0x54, 0x97, 0xe7, 0x9b,
+       0xc6, 0x68, 0x5f, 0xfb, 0x97, 0xb2, 0x47, 0x42, 0xbd, 0x94, 0x0e, 0xa8,
+       0x35, 0x64, 0x51, 0xbd, 0x3c, 0xd5, 0xf5, 0xfd, 0xdc, 0x60, 0x88, 0xd8,
+       0x67, 0xb7, 0x3b, 0xb9, 0x3f, 0x64, 0x77, 0x72, 0x3d, 0xfe, 0x6b, 0x13,
+       0x3f, 0x2f, 0x95, 0x0e, 0xfe, 0x26, 0xd9, 0x29, 0x03, 0x0b, 0xc5, 0xd9,
+       0x16, 0xac, 0x77, 0x64, 0x82, 0x99, 0xac, 0x8f, 0x63, 0x9c, 0x5d, 0xe7,
+       0xe8, 0x18, 0xa6, 0x3a, 0x30, 0x6f, 0x07, 0xfd, 0xc9, 0x21, 0xbd, 0xaa,
+       0xe9, 0xd1, 0xdb, 0xcc, 0x6a, 0x6d, 0x07, 0xe8, 0x97, 0x51, 0x32, 0xd7,
+       0x93, 0xa0, 0x3f, 0xfb, 0x39, 0x61, 0x9e, 0xf7, 0xa5, 0x07, 0x8d, 0xdc,
+       0xff, 0xf0, 0x19, 0xd1, 0xff, 0x48, 0xb7, 0x30, 0x5f, 0x6c, 0x1e, 0xd9,
+       0x19, 0xca, 0x43, 0x3b, 0x58, 0xa2, 0x84, 0xe7, 0x00, 0xe2, 0x42, 0x7a,
+       0x5c, 0xfd, 0x0e, 0x88, 0x75, 0x70, 0x65, 0x36, 0x9d, 0xc3, 0x7a, 0x13,
+       0x41, 0x40, 0xbf, 0x59, 0x75, 0xd1, 0x7e, 0xd3, 0xad, 0x9a, 0x9e, 0x5a,
+       0x3e, 0x9c, 0xf4, 0xd4, 0x65, 0x5b, 0xa4, 0xff, 0x76, 0x79, 0x69, 0x16,
+       0x5d, 0x3f, 0x7b, 0xbb, 0x99, 0xea, 0x07, 0xce, 0x8a, 0x3a, 0x47, 0x0d,
+       0x0f, 0xfa, 0xf3, 0xd6, 0xda, 0x39, 0x6c, 0xed, 0xfe, 0xf2, 0x2d, 0x9b,
+       0x62, 0xd0, 0xef, 0x3c, 0x2b, 0xce, 0xff, 0x6a, 0xd7, 0x27, 0x0b, 0xfc,
+       0x4d, 0x76, 0xca, 0xc2, 0xfe, 0x59, 0xd6, 0x60, 0x3e, 0x6c, 0x11, 0x18,
+       0xf1, 0x38, 0xc0, 0x7b, 0xe5, 0x91, 0x8e, 0xd8, 0xdb, 0x18, 0xf9, 0x9b,
+       0x93, 0x70, 0xdd, 0x55, 0x5b, 0xae, 0xdc, 0xfe, 0x2a, 0xf4, 0xab, 0x0d,
+       0xc1, 0x64, 0x6e, 0x37, 0x7c, 0xf4, 0xde, 0xfc, 0x77, 0xf9, 0xb9, 0xee,
+       0xf9, 0x7f, 0x8b, 0xfc, 0xae, 0x40, 0x85, 0x93, 0xc7, 0xf9, 0x15, 0x62,
+       0xfc, 0x5b, 0xa0, 0xb1, 0x03, 0x9e, 0x6e, 0x01, 0x3a, 0x38, 0xb0, 0x7d,
+       0x63, 0x52, 0x19, 0xf2, 0x27, 0x5c, 0xa7, 0xf3, 0x71, 0x33, 0x8f, 0x30,
+       0x23, 0xca, 0xf3, 0x2c, 0x6f, 0x26, 0xd5, 0x4d, 0x9c, 0x62, 0xae, 0x33,
+       0x7b, 0x01, 0xc4, 0xf9, 0x4e, 0x95, 0xe0, 0x9c, 0xcb, 0x3c, 0x46, 0xcc,
+       0x5b, 0xbd, 0x73, 0x7b, 0x65, 0x0c, 0x3e, 0xd7, 0x3d, 0x9e, 0x36, 0x0e,
+       0x30, 0x0c, 0xfa, 0x25, 0xef, 0x3a, 0x7c, 0xc6, 0x64, 0xcc, 0x1b, 0x4c,
+       0xe6, 0x75, 0x13, 0x30, 0x9f, 0x05, 0xaf, 0x7b, 0x16, 0xa5, 0x3f, 0x8c,
+       0x76, 0x49, 0x9b, 0xef, 0x1d, 0xe6, 0xbd, 0x74, 0x06, 0xe8, 0x3b, 0x9b,
+       0xb9, 0x68, 0x5c, 0x6d, 0x7c, 0x86, 0xe9, 0xf9, 0x30, 0x3d, 0xb5, 0x7b,
+       0xf9, 0xaa, 0x8f, 0x12, 0x60, 0xbe, 0xb5, 0x47, 0x0d, 0x94, 0x8f, 0x58,
+       0xdb, 0x6c, 0xa6, 0x78, 0xad, 0x6b, 0xe5, 0x7f, 0xed, 0x78, 0x0a, 0xee,
+       0xdf, 0x91, 0xde, 0xd1, 0x0f, 0xed, 0xf6, 0xfb, 0x2b, 0xff, 0x36, 0x04,
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+       0x33, 0x6c, 0x5f, 0xe5, 0xec, 0xd2, 0x2b, 0x31, 0x78, 0x1f, 0xec, 0xee,
+       0xd6, 0xa7, 0xd0, 0x58, 0xbe, 0x6c, 0xa6, 0x3a, 0xe2, 0xf7, 0x57, 0xbe,
+       0x3c, 0x24, 0xdc, 0x8f, 0xad, 0x74, 0x16, 0x2e, 0xc7, 0xf7, 0xd8, 0xb8,
+       0xeb, 0x3b, 0xef, 0x58, 0xfc, 0xd2, 0xf0, 0x14, 0xaa, 0xf7, 0x12, 0xfc,
+       0xb4, 0x42, 0xf0, 0xd3, 0xda, 0x17, 0x87, 0x92, 0xbf, 0xb5, 0x36, 0xa6,
+       0x9b, 0x9f, 0x78, 0x7f, 0x2b, 0xaf, 0x1b, 0xd1, 0xd6, 0x71, 0x46, 0xf0,
+       0xe3, 0xca, 0x97, 0xbe, 0x89, 0xf8, 0xce, 0xc4, 0x6e, 0xe0, 0x23, 0xd5,
+       0xcc, 0xf7, 0xc5, 0xd4, 0xa1, 0x60, 0xef, 0xdb, 0x2e, 0xe7, 0xd2, 0x77,
+       0x1f, 0x8c, 0xde, 0x7f, 0x75, 0xc2, 0xbc, 0x2d, 0x57, 0x3f, 0x89, 0xc5,
+       0xfe, 0x9e, 0x37, 0xff, 0x4a, 0xf0, 0xb3, 0xb9, 0xd7, 0x07, 0x2f, 0xca,
+       0xa2, 0x6f, 0x4c, 0x68, 0x7f, 0x5a, 0x3b, 0xef, 0xb9, 0xa0, 0x29, 0x21,
+       0x1f, 0xe9, 0x0e, 0x72, 0xb6, 0x01, 0xc7, 0xbf, 0xed, 0x77, 0x2f, 0x5e,
+       0xfa, 0x00, 0xf1, 0xd3, 0xfc, 0xf2, 0xd6, 0x9f, 0xe1, 0x33, 0xd7, 0x79,
+       0xfe, 0x73, 0x97, 0x96, 0x77, 0x14, 0xf6, 0xc6, 0x25, 0xf0, 0x01, 0xf6,
+       0x86, 0xe2, 0x8b, 0x2e, 0x16, 0xcd, 0xcf, 0x93, 0x08, 0xff, 0x46, 0xc1,
+       0x1d, 0xf9, 0x2c, 0xfa, 0x9e, 0x87, 0x4a, 0x7c, 0xed, 0x66, 0xc7, 0x71,
+       0x1f, 0xa7, 0xb6, 0xd5, 0x40, 0x75, 0x26, 0xb1, 0xb8, 0x09, 0x14, 0x96,
+       0xaf, 0x8b, 0x95, 0x0d, 0x9a, 0x51, 0x72, 0x5b, 0x9c, 0xa0, 0xaf, 0x85,
+       0x9e, 0xf9, 0x7f, 0xce, 0xdb, 0x2a, 0xea, 0xa8, 0x3e, 0x20, 0xd2, 0x1f,
+       0x2a, 0x38, 0xb4, 0x32, 0xc2, 0x0f, 0xf2, 0xc0, 0x5f, 0xaf, 0x7e, 0xd0,
+       0x33, 0xde, 0x5a, 0xcc, 0x2f, 0xe9, 0xfd, 0xa1, 0xf1, 0x01, 0xc3, 0x62,
+       0x53, 0xdc, 0xf7, 0xf8, 0x45, 0x87, 0xa6, 0xf5, 0xea, 0x17, 0x41, 0x40,
+       0xed, 0x96, 0xc6, 0x88, 0xad, 0x21, 0xf8, 0x35, 0xe8, 0xf4, 0xf3, 0x7e,
+       0x21, 0x57, 0xf5, 0x38, 0x16, 0xe6, 0xff, 0x03, 0xd1, 0xfc, 0xfc, 0x33,
+       0x98, 0x0e, 0xf4, 0x7b, 0x7f, 0x9a, 0xca, 0xf5, 0xb7, 0x2d, 0x83, 0xf1,
+       0xf3, 0x69, 0x52, 0xe7, 0x30, 0x0b, 0xe8, 0xcb, 0x16, 0xe7, 0xa2, 0xc7,
+       0x1f, 0x85, 0x6b, 0x96, 0x41, 0x7c, 0xdd, 0xd8, 0xaf, 0xa5, 0x33, 0x35,
+       0xf9, 0xc4, 0x7f, 0xdd, 0x7e, 0xd7, 0xa1, 0x11, 0xa4, 0xb7, 0xd8, 0xb7,
+       0x30, 0x1b, 0xe2, 0x43, 0xe4, 0x3d, 0xf4, 0x74, 0x2b, 0xc0, 0xf3, 0xec,
+       0xf9, 0x61, 0x72, 0x27, 0xde, 0x0f, 0x1c, 0xfe, 0x6b, 0x2c, 0xe6, 0x7d,
+       0x77, 0xc4, 0xab, 0x6f, 0x21, 0x3d, 0x82, 0x47, 0x65, 0xda, 0xff, 0x89,
+       0x52, 0x3a, 0x4c, 0x8e, 0x5e, 0xe2, 0xbb, 0x57, 0x51, 0x0f, 0x02, 0x9f,
+       0xca, 0xa9, 0xdc, 0x1e, 0x58, 0x1a, 0x79, 0x7e, 0xd1, 0xa2, 0xba, 0x19,
+       0xc6, 0x0f, 0x51, 0x76, 0xfb, 0xa8, 0xf0, 0x73, 0x7f, 0x8d, 0x4e, 0x1e,
+       0x4f, 0x56, 0x1e, 0x7e, 0xbf, 0xbf, 0x09, 0xe8, 0x71, 0xc9, 0xd0, 0x16,
+       0x9b, 0x03, 0xe3, 0xaf, 0xde, 0xbb, 0x3b, 0x16, 0xdd, 0xff, 0x0c, 0x93,
+       0xf7, 0x03, 0xe4, 0xc3, 0x55, 0x67, 0xdf, 0x1e, 0x63, 0xa7, 0xfc, 0xcd,
+       0x96, 0xfe, 0x18, 0x0f, 0xd6, 0x07, 0xf8, 0x77, 0x30, 0x46, 0x2a, 0xcc,
+       0xa7, 0xe4, 0xf5, 0x84, 0xa3, 0x7a, 0x33, 0x2c, 0x26, 0x01, 0xcf, 0xe9,
+       0x27, 0x50, 0x3b, 0xb2, 0x29, 0x7f, 0x19, 0xf2, 0x59, 0x75, 0x80, 0xaf,
+       0x13, 0xc7, 0xc6, 0x42, 0xbe, 0xe1, 0x8d, 0x12, 0xf5, 0x3b, 0x1b, 0x6b,
+       0xe3, 0x71, 0xbc, 0xea, 0xdf, 0x37, 0xa7, 0xa1, 0x3c, 0xbd, 0x9c, 0xc4,
+       0xe3, 0xcd, 0x97, 0xae, 0x66, 0xf3, 0xf7, 0x15, 0xa6, 0xe0, 0xf3, 0x41,
+       0xa7, 0x43, 0x10, 0xd3, 0x6f, 0xc0, 0xf8, 0xe4, 0x65, 0x11, 0xd7, 0x74,
+       0x5e, 0x95, 0xe9, 0x39, 0x6d, 0xfe, 0x91, 0x8d, 0x85, 0xb2, 0x1d, 0xf8,
+       0x21, 0x27, 0xb0, 0xf1, 0x00, 0xc5, 0x51, 0x4d, 0x66, 0x15, 0xe9, 0x1a,
+       0xf5, 0x1c, 0xe3, 0x78, 0x68, 0x8a, 0x22, 0xb9, 0xaf, 0x6e, 0x99, 0xca,
+       0xd0, 0xee, 0x77, 0x39, 0x98, 0x4b, 0x82, 0xfb, 0x3b, 0xa2, 0x83, 0x7f,
+       0xa4, 0xf3, 0x6e, 0xcd, 0x66, 0x15, 0xf3, 0xad, 0x51, 0xf6, 0x8d, 0x2c,
+       0x1e, 0xc6, 0xdf, 0x21, 0xf6, 0x59, 0x87, 0x03, 0x47, 0xe1, 0x79, 0x29,
+       0xed, 0xba, 0x36, 0x5f, 0x54, 0xd3, 0xd3, 0x18, 0x73, 0x20, 0x3f, 0x50,
+       0xde, 0x37, 0x4a, 0xd9, 0xc8, 0x26, 0xdb, 0xc2, 0xf1, 0x1c, 0x43, 0x78,
+       0x76, 0xa4, 0x72, 0x3e, 0xda, 0x11, 0x1d, 0x30, 0x60, 0x9e, 0x25, 0x38,
+       0x98, 0xb1, 0x67, 0x09, 0xae, 0x10, 0x9c, 0x8c, 0xe6, 0xd5, 0xe0, 0x1c,
+       0xee, 0xc7, 0xf3, 0x84, 0x3b, 0x4c, 0xc1, 0xf3, 0x78, 0x6e, 0x06, 0xe0,
+       0xb2, 0x23, 0xfd, 0x87, 0x33, 0x0e, 0x27, 0x6b, 0x1a, 0xaa, 0x62, 0x9e,
+       0x20, 0xca, 0xee, 0xa6, 0x75, 0x44, 0xd9, 0x55, 0x97, 0x4f, 0xea, 0x09,
+       0x57, 0x75, 0x2e, 0xf3, 0xa3, 0x5d, 0xff, 0xf9, 0x43, 0xac, 0x5b, 0x6e,
+       0x51, 0x8e, 0xab, 0xa3, 0x43, 0x7d, 0x0b, 0xc8, 0xc0, 0x8e, 0x81, 0x4c,
+       0xc8, 0xf9, 0xcf, 0x1f, 0x2f, 0xc9, 0x08, 0xef, 0x83, 0x62, 0x19, 0x17,
+       0x7a, 0x7f, 0xc8, 0xaf, 0x36, 0x3e, 0x5e, 0x37, 0x89, 0xe2, 0x09, 0x9f,
+       0x8c, 0xf1, 0x2f, 0xb4, 0x31, 0xf1, 0xb8, 0x4e, 0x95, 0xd6, 0xa7, 0x60,
+       0x8a, 0x29, 0x8f, 0xe3, 0x01, 0xf7, 0xdb, 0xad, 0x16, 0x7e, 0xbf, 0xfb,
+       0x79, 0xe0, 0x6f, 0x1b, 0xf6, 0x6d, 0xfc, 0x39, 0x57, 0x9c, 0xdd, 0x3a,
+       0x4d, 0x22, 0x39, 0xe1, 0xf5, 0xb8, 0x42, 0x1f, 0xdc, 0x27, 0x05, 0xce,
+       0xdf, 0x08, 0xa4, 0xfd, 0x2a, 0x70, 0x20, 0x57, 0x05, 0x58, 0x56, 0xbf,
+       0xb1, 0x9f, 0xf8, 0x74, 0x95, 0xa1, 0xe9, 0xa9, 0x91, 0x70, 0xff, 0xee,
+       0x28, 0xaf, 0x2b, 0x15, 0xe6, 0x7b, 0xed, 0x43, 0x03, 0x9d, 0x6b, 0xfd,
+       0xf3, 0x8b, 0x51, 0xfe, 0x0a, 0xc0, 0xc7, 0xb0, 0x7d, 0x5b, 0x92, 0xdd,
+       0xbd, 0xc8, 0x87, 0x7e, 0xfc, 0x47, 0xde, 0x7b, 0xe8, 0xc9, 0x74, 0xa4,
+       0xff, 0x3e, 0x49, 0xc5, 0x3c, 0x6c, 0x97, 0x31, 0x48, 0xdf, 0x37, 0xa9,
+       0x6a, 0xfa, 0xcc, 0x44, 0xf5, 0x0d, 0x8d, 0x1f, 0x53, 0xdd, 0xd3, 0x9b,
+       0xa9, 0xde, 0x49, 0x38, 0xcf, 0xb8, 0xc6, 0x1a, 0xda, 0x8f, 0x1e, 0xcf,
+       0x36, 0xd2, 0x7e, 0x74, 0xb6, 0x38, 0x0f, 0x5e, 0xef, 0xe4, 0xfa, 0xe3,
+       0xf2, 0xe9, 0x21, 0xcf, 0xd6, 0x84, 0xe1, 0x7f, 0x49, 0x2a, 0x97, 0x2f,
+       0x16, 0xf4, 0x0e, 0x40, 0xb9, 0x69, 0x12, 0xf2, 0xd9, 0x82, 0x7e, 0x0a,
+       0xb4, 0x7b, 0x85, 0xbf, 0xb4, 0xb7, 0xf5, 0xd6, 0x2c, 0x35, 0x2c, 0x7f,
+       0x58, 0xc3, 0x0e, 0xa4, 0x23, 0xbe, 0x1f, 0x62, 0x87, 0xa8, 0xd5, 0xae,
+       0x77, 0xf9, 0xf9, 0xb9, 0xca, 0xec, 0x77, 0x2c, 0x77, 0xb8, 0xc3, 0xf8,
+       0x6f, 0x91, 0x90, 0xf7, 0x45, 0xa9, 0x22, 0x4f, 0x96, 0xea, 0x9d, 0x8d,
+       0xf0, 0xae, 0x6a, 0xfd, 0xc4, 0x14, 0xab, 0xe2, 0x39, 0x99, 0xfa, 0xfe,
+       0x68, 0x57, 0xea, 0xc1, 0x9f, 0xb2, 0xf7, 0x82, 0x97, 0x6e, 0xb9, 0xd5,
+       0xc9, 0x51, 0xb5, 0x12, 0x34, 0xe1, 0xf3, 0xd5, 0x17, 0xf8, 0xf9, 0x57,
+       0xa0, 0x73, 0x1d, 0x9e, 0x37, 0x78, 0xf9, 0x9d, 0xc6, 0x11, 0x8b, 0xe1,
+       0xfa, 0x5e, 0xc0, 0x35, 0xd6, 0x95, 0xfa, 0xce, 0x9a, 0xa9, 0xbe, 0x72,
+       0xaf, 0xd1, 0x93, 0x8e, 0xcf, 0xd7, 0x9c, 0xf9, 0x3a, 0x17, 0xf5, 0x56,
+       0x09, 0x02, 0x01, 0xf0, 0x7c, 0xdd, 0xbc, 0x6a, 0x00, 0xe2, 0x0d, 0xf8,
+       0xbe, 0x28, 0x1a, 0xe5, 0x6b, 0x17, 0x23, 0x3d, 0xa6, 0xc9, 0x67, 0x0e,
+       0xca, 0x27, 0xbc, 0x9f, 0x83, 0x7c, 0x5f, 0x80, 0xfd, 0xe1, 0xa4, 0x87,
+       0x77, 0x98, 0xda, 0xf9, 0xf9, 0xd3, 0xbd, 0xfc, 0xfc, 0x29, 0xf0, 0x3d,
+       0xc9, 0x01, 0xf0, 0xbd, 0x1d, 0xfd, 0x86, 0x1c, 0x3b, 0xc8, 0x01, 0xbd,
+       0x3f, 0x94, 0xe4, 0x7b, 0x47, 0xbb, 0x81, 0xce, 0xc9, 0xfa, 0x40, 0x8f,
+       0x0f, 0xa6, 0x7e, 0xd1, 0x1c, 0xec, 0xef, 0x68, 0x2f, 0xb1, 0x93, 0x7c,
+       0x63, 0x5e, 0x3f, 0x0f, 0xe5, 0x34, 0x70, 0x80, 0xc6, 0xa9, 0x87, 0xd8,
+       0x04, 0x49, 0x27, 0x31, 0x4f, 0xb8, 0x3f, 0xd9, 0xe8, 0x8c, 0x25, 0xba,
+       0x69, 0xfa, 0xf1, 0xb0, 0x93, 0x09, 0x3b, 0xa1, 0xc6, 0xe1, 0x79, 0x03,
+       0xab, 0x2c, 0x47, 0xc8, 0x45, 0x98, 0x3d, 0xe4, 0x7d, 0x61, 0x2f, 0x4f,
+       0xfc, 0x2a, 0xf0, 0xf8, 0x2f, 0xd1, 0x76, 0xb8, 0x85, 0x5d, 0x10, 0xfe,
+       0x14, 0xf3, 0xe6, 0x93, 0x9e, 0xbf, 0x57, 0xd8, 0xaa, 0xb5, 0xaf, 0x4f,
+       0x98, 0xb9, 0x1d, 0xd6, 0xb9, 0xf6, 0x84, 0xdc, 0x5d, 0x3f, 0x8e, 0xfe,
+       0x6b, 0x40, 0xf0, 0xc9, 0x01, 0xe1, 0xcf, 0xa2, 0x9d, 0x50, 0x13, 0x78,
+       0x3d, 0x0e, 0x5e, 0x1f, 0xbd, 0x99, 0xd7, 0xd5, 0x8e, 0x71, 0xaf, 0x29,
+       0xc6, 0xb3, 0xcf, 0xe3, 0xca, 0x37, 0x1e, 0xc4, 0x76, 0x82, 0xa7, 0xbe,
+       0x18, 0xcf, 0x3e, 0x4f, 0x5a, 0xd0, 0x7e, 0x90, 0x9f, 0x81, 0xe6, 0xe7,
+       0xd9, 0x1b, 0x0e, 0xdc, 0x94, 0x8d, 0xfb, 0xde, 0x5d, 0x67, 0xcd, 0x0c,
+       0xf7, 0x5d, 0x1a, 0xfe, 0x1a, 0xfc, 0xe3, 0x4b, 0x80, 0x87, 0xfb, 0x5b,
+       0x00, 0xff, 0xbd, 0xd8, 0x25, 0x58, 0x0e, 0xf1, 0x1f, 0x58, 0xec, 0x74,
+       0xe6, 0xec, 0x79, 0xbf, 0x4b, 0xd2, 0xf4, 0xc7, 0xa9, 0x0a, 0xe4, 0xc7,
+       0xce, 0x06, 0x39, 0xd4, 0x07, 0x40, 0xaa, 0x80, 0xc1, 0xb1, 0xff, 0xdb,
+       0xd4, 0x93, 0x8f, 0xfb, 0xa0, 0x9f, 0x95, 0xe6, 0x7e, 0x3e, 0x15, 0xfd,
+       0xed, 0x74, 0x2f, 0xb5, 0x5d, 0x27, 0xff, 0x9a, 0x8c, 0xb6, 0x60, 0xef,
+       0x69, 0xee, 0x47, 0x35, 0x98, 0xdc, 0xd9, 0xc8, 0x3f, 0x0d, 0x03, 0x23,
+       0xbf, 0x1f, 0xa0, 0xb5, 0x4f, 0xa6, 0x1a, 0x89, 0x0e, 0x05, 0x7d, 0x7c,
+       0xbf, 0xeb, 0x48, 0x2a, 0xcf, 0x6f, 0x0e, 0xf1, 0xb1, 0xc7, 0x90, 0x8f,
+       0xaa, 0x1a, 0x64, 0xbb, 0x1f, 0xe8, 0x7e, 0xa9, 0x41, 0x76, 0x9b, 0xc0,
+       0x1f, 0x3a, 0xef, 0xf6, 0x26, 0xe3, 0xd9, 0x9c, 0x0b, 0xcc, 0x77, 0xcb,
+       0x44, 0xb4, 0xf3, 0x22, 0x8e, 0xd4, 0xbe, 0xf7, 0x72, 0x17, 0xfa, 0x29,
+       0x60, 0xa7, 0xee, 0xfe, 0x65, 0xef, 0xfb, 0x0f, 0xab, 0x99, 0xf6, 0x5b,
+       0x63, 0x40, 0xbe, 0x5a, 0xd6, 0x24, 0xb1, 0xff, 0x00, 0x1c, 0x2c, 0x7f,
+       0x26, 0xf2, 0xf9, 0xd5, 0xda, 0xf7, 0x6a, 0x1a, 0xb7, 0x1c, 0xc6, 0xef,
+       0x88, 0xad, 0x7c, 0x4e, 0x77, 0x1f, 0xfd, 0x15, 0xfa, 0x0e, 0x46, 0xa4,
+       0x1f, 0x73, 0x24, 0x55, 0xf8, 0x27, 0x59, 0x2c, 0x0b, 0xfd, 0x13, 0xe0,
+       0x23, 0xd2, 0x0f, 0x46, 0x85, 0x1d, 0x31, 0x03, 0xdf, 0xae, 0x48, 0xf7,
+       0xee, 0x43, 0x7b, 0xfc, 0xb2, 0xf8, 0xbe, 0x02, 0xe8, 0x51, 0x92, 0xc7,
+       0x7d, 0x4e, 0x61, 0x57, 0x44, 0xfd, 0x41, 0x70, 0x07, 0xaf, 0x2b, 0x1e,
+       0xbe, 0xcd, 0x2f, 0x1b, 0xe0, 0xfd, 0x09, 0x8a, 0x5f, 0x46, 0x7b, 0xc5,
+       0xa0, 0xc5, 0x7d, 0x87, 0x71, 0x6e, 0x6f, 0x19, 0x7d, 0x87, 0xc9, 0xe7,
+       0x3e, 0x8d, 0xfb, 0x3e, 0xcb, 0x85, 0x3e, 0x5c, 0xae, 0xf9, 0x69, 0x7e,
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+       0x82, 0x9f, 0xfb, 0xf6, 0x13, 0xfe, 0x57, 0x6d, 0x93, 0x23, 0xbe, 0x0f,
+       0x5b, 0x59, 0x1f, 0xf9, 0xfd, 0xd7, 0x9a, 0xb7, 0x6f, 0xa3, 0xef, 0x08,
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+       0x89, 0xd3, 0xd5, 0xd0, 0xcc, 0x5b, 0x98, 0xff, 0x16, 0x9e, 0x27, 0x31,
+       0xd2, 0xfc, 0x3d, 0xee, 0x17, 0xf9, 0x56, 0xe3, 0xfd, 0xaf, 0x33, 0xad,
+       0x7c, 0xff, 0xfa, 0xaa, 0xaf, 0x02, 0xfb, 0xf7, 0x0f, 0x94, 0xa9, 0xae,
+       0xf3, 0xfe, 0xb7, 0x57, 0x0e, 0x0d, 0xd7, 0xa3, 0x0c, 0xe1, 0x04, 0xba,
+       0x56, 0x1b, 0x83, 0xc9, 0x14, 0x6f, 0x9e, 0x34, 0x10, 0x7c, 0xd5, 0x27,
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+       0x2e, 0xf4, 0xdf, 0xe1, 0x81, 0xd6, 0xe5, 0xc8, 0xcf, 0x3e, 0x9c, 0x37,
+       0x25, 0x34, 0xce, 0xcb, 0x69, 0xbc, 0x7e, 0x8f, 0xe1, 0x7a, 0x9d, 0xe8,
+       0x6d, 0xfc, 0x92, 0x8f, 0x2b, 0xd6, 0xfb, 0x10, 0x9b, 0x2d, 0xe2, 0x6a,
+       0xce, 0x4f, 0x39, 0x69, 0x7c, 0xbd, 0x10, 0x8f, 0x8c, 0x4b, 0xef, 0x25,
+       0x1e, 0xb9, 0x5e, 0xbf, 0x13, 0xec, 0xc3, 0xa9, 0x85, 0x12, 0xd6, 0x33,
+       0x29, 0x3e, 0x8c, 0x87, 0xf7, 0xbc, 0xc7, 0xf5, 0x42, 0x4d, 0xf3, 0xb2,
+       0x8f, 0x90, 0xdf, 0xab, 0xdf, 0x37, 0x53, 0x9d, 0xd7, 0xfd, 0x2d, 0xcb,
+       0x86, 0x52, 0xbd, 0xaf, 0xd7, 0x7b, 0x03, 0xfa, 0x1b, 0x5f, 0xb7, 0xac,
+       0xb8, 0x81, 0xf2, 0x83, 0xd2, 0x43, 0x04, 0x97, 0x0f, 0xe1, 0x73, 0xa2,
+       0x5f, 0x73, 0x26, 0x19, 0xeb, 0x52, 0x2b, 0x9b, 0xcf, 0x24, 0x93, 0xdd,
+       0xdd, 0x3b, 0x7a, 0x93, 0x2f, 0x06, 0xfd, 0x97, 0xbc, 0xe9, 0x78, 0x1d,
+       0xfc, 0x09, 0xe2, 0x3f, 0xf0, 0x6b, 0x88, 0xff, 0xf6, 0xb4, 0x15, 0x68,
+       0x7e, 0x8c, 0x15, 0xc7, 0xad, 0x3c, 0xaa, 0x78, 0x10, 0x3f, 0x95, 0x47,
+       0x0b, 0x8e, 0x57, 0xa0, 0x7f, 0x71, 0xa2, 0xa8, 0x00, 0xd5, 0xb9, 0x74,
+       0xa2, 0x80, 0xfc, 0x98, 0x7c, 0xf4, 0x63, 0x6c, 0x21, 0xbf, 0xa6, 0x5b,
+       0x4f, 0xa6, 0x73, 0x3f, 0xa6, 0xab, 0x35, 0x8a, 0xf2, 0x0b, 0x12, 0x1b,
+       0xc8, 0xf9, 0x87, 0x0d, 0x8a, 0xe0, 0x9f, 0xd5, 0x0d, 0xaf, 0x93, 0xbd,
+       0x5f, 0xdd, 0x28, 0x47, 0xd4, 0x2f, 0x6a, 0xef, 0xdd, 0x99, 0xae, 0xd0,
+       0x38, 0xcb, 0x34, 0xfe, 0xa9, 0x97, 0xdc, 0xc4, 0x1f, 0xbb, 0x78, 0xbb,
+       0xba, 0x71, 0x0f, 0xad, 0x6f, 0x95, 0xb1, 0x9e, 0xe8, 0x5d, 0xb3, 0xdd,
+       0xc8, 0xef, 0xef, 0xe0, 0xad, 0xf6, 0x7d, 0x58, 0x1f, 0x8b, 0xf7, 0x21,
+       0x3e, 0x8e, 0xe3, 0x25, 0xa0, 0xc3, 0x34, 0x93, 0x3f, 0x03, 0xf3, 0xd3,
+       0xc7, 0x32, 0xb9, 0x9f, 0xaf, 0xa7, 0xc7, 0xe7, 0xe9, 0x3c, 0xff, 0x71,
+       0xec, 0xac, 0x77, 0x00, 0xf2, 0xcb, 0xb1, 0x42, 0xef, 0x50, 0x7b, 0x2f,
+       0x76, 0xc2, 0xc7, 0x8a, 0x78, 0x5c, 0x2b, 0x09, 0x7c, 0x37, 0xf0, 0x73,
+       0x53, 0xfa, 0xe7, 0x3e, 0x4b, 0x97, 0xc4, 0x77, 0x42, 0x22, 0xcf, 0xb7,
+       0x6a, 0xed, 0xa9, 0x74, 0xae, 0x3f, 0xa7, 0x99, 0x7a, 0xff, 0x2e, 0xe0,
+       0x6f, 0xd2, 0xb5, 0x73, 0x09, 0xec, 0x31, 0x43, 0x01, 0x46, 0xc5, 0x46,
+       0xfb, 0x06, 0xe1, 0xd7, 0xa7, 0x86, 0x7d, 0xd7, 0x61, 0xce, 0xcd, 0x46,
+       0xf2, 0x17, 0x4e, 0x31, 0xfb, 0xeb, 0x58, 0xef, 0x38, 0x43, 0xd3, 0xb3,
+       0xe3, 0xb8, 0x7d, 0xd5, 0xe7, 0xcb, 0xe7, 0x89, 0xf7, 0x3c, 0x9b, 0x55,
+       0xbe, 0x5f, 0xa4, 0x3b, 0x3f, 0x33, 0x4f, 0x3b, 0xdf, 0xa4, 0x3b, 0xef,
+       0x36, 0x4f, 0xf8, 0x3b, 0xf3, 0x74, 0xfe, 0xce, 0xd3, 0xe9, 0xc2, 0x8f,
+       0x1f, 0xc2, 0x86, 0xa0, 0x1e, 0xac, 0x17, 0xe7, 0xef, 0xd6, 0x0e, 0x8f,
+       0xf2, 0x87, 0xe7, 0xb3, 0xf4, 0xed, 0x61, 0xb1, 0x2f, 0x82, 0xe7, 0x87,
+       0xb0, 0xad, 0x19, 0xfe, 0x2e, 0xe5, 0x7d, 0x8e, 0xb5, 0x9e, 0x7d, 0x85,
+       0xea, 0xdd, 0xce, 0x46, 0xb1, 0x81, 0x3c, 0xaf, 0x47, 0xf9, 0xef, 0xca,
+       0x3e, 0xf2, 0xdf, 0x35, 0xdd, 0x72, 0x39, 0x37, 0x82, 0xcf, 0x34, 0xba,
+       0x5c, 0x12, 0xdf, 0x83, 0xd1, 0xd3, 0x65, 0xb7, 0xa6, 0xaf, 0xc4, 0xbe,
+       0x5d, 0xb4, 0xd8, 0xb7, 0xf3, 0x1b, 0xbd, 0xbb, 0x51, 0x9e, 0x2b, 0x2d,
+       0x17, 0x4d, 0xbc, 0xee, 0x30, 0x68, 0x42, 0x7d, 0x56, 0x33, 0x9c, 0xfb,
+       0x4d, 0x97, 0x4a, 0x25, 0xda, 0x6f, 0x07, 0x38, 0xfb, 0x9b, 0xc3, 0xf4,
+       0xfb, 0xa5, 0x54, 0x1e, 0x7f, 0xdd, 0x7f, 0x8b, 0x44, 0x79, 0xd7, 0x56,
+       0x7c, 0x1e, 0xe3, 0xac, 0x7a, 0x89, 0xea, 0xbc, 0x2b, 0x03, 0xed, 0x26,
+       0xe4, 0xa7, 0x21, 0x0d, 0x8b, 0x1f, 0x26, 0xb9, 0xf5, 0xb1, 0xd3, 0x2c,
+       0xec, 0xbb, 0x1a, 0x33, 0x2d, 0xdc, 0x4e, 0x76, 0xd3, 0x4f, 0x5b, 0x77,
+       0xb7, 0x1d, 0x8b, 0xf7, 0x71, 0x7d, 0x9c, 0x48, 0x2d, 0x3e, 0x8f, 0x76,
+       0x71, 0x86, 0xb0, 0x83, 0xfa, 0x73, 0x51, 0x43, 0x59, 0x7b, 0x59, 0x3a,
+       0xc0, 0x33, 0xdf, 0x2d, 0xb9, 0xb0, 0x1e, 0xa0, 0x2f, 0x3a, 0xcf, 0x5e,
+       0x30, 0xea, 0x75, 0x44, 0xc3, 0xf5, 0xd2, 0xbb, 0x33, 0xdd, 0xfb, 0x4e,
+       0x3a, 0xca, 0x79, 0xfb, 0xe5, 0x5b, 0x30, 0x8f, 0x7a, 0x6c, 0xf8, 0x67,
+       0xfd, 0xd1, 0x8e, 0x56, 0xf5, 0xc1, 0xc7, 0x1f, 0x0b, 0x3c, 0xeb, 0xbf,
+       0x2b, 0xe3, 0x1a, 0xaa, 0xd6, 0xe2, 0xf7, 0x55, 0x6a, 0x9d, 0xde, 0x0e,
+       0xd2, 0x9f, 0x86, 0x6f, 0x63, 0x47, 0x30, 0x1c, 0xa7, 0xe3, 0x37, 0x6b,
+       0x25, 0xa4, 0x13, 0x23, 0xfe, 0xef, 0x4b, 0x7e, 0x3e, 0x13, 0xe3, 0x7e,
+       0x96, 0xce, 0xbf, 0x77, 0x0f, 0xb8, 0xa7, 0x7d, 0x97, 0x55, 0xe9, 0xbc,
+       0x4e, 0xeb, 0x98, 0xd1, 0x9f, 0x41, 0x79, 0x8a, 0x9c, 0xeb, 0xdb, 0xf7,
+       0xaa, 0xd9, 0xf7, 0x46, 0x2e, 0xea, 0xb3, 0xce, 0xd6, 0xa3, 0xb9, 0xa6,
+       0x30, 0xba, 0x5e, 0x5c, 0x0b, 0x7a, 0x00, 0xed, 0x4a, 0xf3, 0xc1, 0x64,
+       0xd5, 0x16, 0xce, 0x77, 0x06, 0xe2, 0x37, 0x49, 0xd2, 0xf8, 0x4f, 0x11,
+       0xf6, 0x32, 0x92, 0x0f, 0x2f, 0x22, 0x1f, 0xe6, 0x60, 0x7b, 0x26, 0x76,
+       0x10, 0xea, 0xe3, 0x5d, 0xa7, 0x62, 0x07, 0xe3, 0x78, 0x7b, 0x79, 0xdb,
+       0xcd, 0xaf, 0x4d, 0xfc, 0x7b, 0xf6, 0x10, 0x1f, 0x0d, 0x99, 0x17, 0x13,
+       0x0e, 0xdf, 0xc3, 0x04, 0xdf, 0xa5, 0x7a, 0x3e, 0x0e, 0x63, 0x1d, 0x43,
+       0xe6, 0x8c, 0x0c, 0xbf, 0x5f, 0xdb, 0x17, 0x1f, 0x5b, 0x33, 0x88, 0x8f,
+       0x3b, 0x22, 0xf8, 0x58, 0x5b, 0x6f, 0x3d, 0x7e, 0xcf, 0x07, 0xe3, 0x80,
+       0x16, 0x33, 0x7d, 0xcf, 0x07, 0xf3, 0xd7, 0x8e, 0x30, 0x39, 0x19, 0x9a,
+       0xc1, 0xf5, 0xcf, 0x58, 0xf1, 0xfd, 0x9e, 0xf1, 0xcc, 0x47, 0xdf, 0x39,
+       0x1c, 0x2b, 0xbe, 0xe3, 0x33, 0x5e, 0x61, 0x01, 0x25, 0x1e, 0xf7, 0xcd,
+       0x02, 0x32, 0xdf, 0xf7, 0xe5, 0xe7, 0x2d, 0xc6, 0x08, 0x7e, 0x1e, 0xab,
+       0x04, 0x5a, 0xb1, 0x8e, 0x62, 0xbc, 0xd8, 0xe7, 0x99, 0xc0, 0xda, 0xe9,
+       0xb9, 0x29, 0x2c, 0x48, 0xad, 0x9b, 0xd9, 0xe9, 0x1c, 0x45, 0x11, 0x73,
+       0x51, 0x3b, 0xce, 0x12, 0x98, 0x8e, 0xee, 0x54, 0x4e, 0x7d, 0x3d, 0xd5,
+       0x25, 0x06, 0x92, 0x15, 0xc7, 0x79, 0x8b, 0x38, 0xaf, 0xd1, 0x0b, 0xdd,
+       0x42, 0xeb, 0x57, 0xe8, 0xbb, 0x3d, 0xc4, 0x9f, 0x32, 0x9e, 0xd7, 0xe9,
+       0xfd, 0xbb, 0x2f, 0xb3, 0x33, 0xb8, 0xdc, 0xd3, 0xc7, 0x45, 0x90, 0xbe,
+       0x97, 0x18, 0xe5, 0xb9, 0xf0, 0x7b, 0x6d, 0x38, 0xc9, 0x44, 0x85, 0x95,
+       0x63, 0x7d, 0xd3, 0x64, 0x85, 0x59, 0xa2, 0x01, 0xde, 0x5d, 0x87, 0x0c,
+       0x24, 0xcf, 0x2d, 0x1d, 0xaa, 0x1f, 0xeb, 0x53, 0x5d, 0x09, 0xe2, 0xbd,
+       0xcf, 0x19, 0xd5, 0xe1, 0x8e, 0x75, 0x73, 0x79, 0x45, 0x93, 0x83, 0xf5,
+       0x18, 0xda, 0x7a, 0xf5, 0x78, 0x98, 0x00, 0xe3, 0x61, 0x9e, 0x6d, 0xac,
+       0x02, 0x91, 0x28, 0xe1, 0x31, 0x40, 0xf3, 0xdd, 0xc8, 0xf8, 0x39, 0x92,
+       0x42, 0xa6, 0x52, 0xfd, 0x73, 0x69, 0x46, 0xa6, 0xd0, 0xf7, 0x41, 0x8a,
+       0xa3, 0x8a, 0x21, 0x8e, 0x42, 0x7d, 0x6f, 0xb0, 0xf8, 0x08, 0x1f, 0xd3,
+       0x33, 0x54, 0xba, 0x8f, 0xfb, 0x25, 0xb1, 0x30, 0xce, 0x84, 0x8d, 0x12,
+       0x7b, 0x0f, 0xf7, 0x3f, 0xb2, 0xf8, 0x7a, 0xb5, 0xf1, 0x27, 0x00, 0x23,
+       0xe0, 0xf9, 0xc2, 0xe9, 0x19, 0xdc, 0x9e, 0x61, 0x4a, 0xf5, 0xbd, 0x78,
+       0xbe, 0x8f, 0x12, 0x4b, 0x05, 0xcd, 0x25, 0x76, 0xfe, 0x9d, 0xa3, 0x64,
+       0xfa, 0xce, 0xd1, 0xf5, 0xe2, 0xb5, 0x2b, 0x99, 0x7f, 0xef, 0x32, 0xf6,
+       0xce, 0x60, 0xe7, 0xcf, 0x0a, 0x42, 0xfb, 0x49, 0x2e, 0xfc, 0xee, 0x51,
+       0x6c, 0xe8, 0x3b, 0x9b, 0x2e, 0xed, 0xdf, 0x83, 0x08, 0x44, 0xfe, 0x7b,
+       0x10, 0x77, 0x64, 0x2c, 0xf9, 0x11, 0xf2, 0xa3, 0x56, 0xaf, 0xc7, 0xbc,
+       0xfc, 0xdf, 0x7d, 0xd0, 0xd7, 0xeb, 0x85, 0xd5, 0xe7, 0xb1, 0x0b, 0x61,
+       0xe7, 0xb0, 0xb5, 0xba, 0x92, 0x6d, 0xfe, 0xd9, 0x2a, 0x9e, 0xf3, 0x5b,
+       0x90, 0x68, 0xa1, 0x73, 0xbf, 0x79, 0x96, 0xfe, 0xf9, 0x68, 0xc7, 0x06,
+       0x3a, 0xbd, 0x34, 0xfe, 0xfb, 0xd2, 0xf6, 0xc1, 0x34, 0x98, 0xe2, 0x1f,
+       0xed, 0x89, 0x09, 0xf1, 0xbb, 0x95, 0xb9, 0xc7, 0x21, 0xbe, 0x43, 0x75,
+       0x83, 0xfc, 0x3b, 0x50, 0xdd, 0xe7, 0xae, 0x92, 0x19, 0x9d, 0x57, 0xb4,
+       0x9a, 0x79, 0x7d, 0xe5, 0x63, 0x20, 0x1f, 0xf8, 0x1d, 0x26, 0x90, 0x2e,
+       0x15, 0xeb, 0x68, 0xd8, 0x83, 0xc5, 0x54, 0x8f, 0xb9, 0xde, 0x61, 0x71,
+       0xe1, 0x79, 0x09, 0x33, 0xc2, 0x6d, 0x0d, 0xc1, 0x5d, 0x6b, 0x11, 0xdf,
+       0x05, 0xb5, 0xf0, 0x7d, 0x71, 0x7d, 0x3d, 0x68, 0xad, 0xcd, 0x40, 0xdf,
+       0x1d, 0xad, 0x65, 0xd1, 0x74, 0x0e, 0x3d, 0x29, 0xda, 0xbb, 0x2e, 0x03,
+       0xe0, 0xba, 0x2f, 0xa6, 0x88, 0xce, 0x77, 0x67, 0xef, 0x9c, 0xe4, 0x44,
+       0xbf, 0x31, 0x7c, 0xfd, 0x93, 0xb4, 0xf5, 0x1b, 0x7a, 0xd6, 0x47, 0xc2,
+       0x7a, 0x1f, 0xc9, 0xe8, 0xa5, 0x1e, 0x51, 0x5b, 0xa7, 0xf6, 0xef, 0x76,
+       0xd8, 0x05, 0xfe, 0xb4, 0x75, 0xdb, 0xb5, 0x73, 0x4a, 0x6e, 0x25, 0xe2,
+       0x9c, 0x92, 0x86, 0x8f, 0xc7, 0xa2, 0xf9, 0xba, 0x8d, 0xb8, 0xf3, 0x9f,
+       0x45, 0xef, 0xaa, 0xa8, 0x37, 0xf4, 0xeb, 0xfd, 0xff, 0xdc, 0x29, 0xbc,
+       0x16, 0xa0, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 xsem_int_table_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xd3, 0xd7,
+       0x66, 0x60, 0xf8, 0x51, 0x8f, 0xc0, 0x2e, 0x9a, 0x0c, 0x0c, 0x5d, 0xd2,
+       0xa8, 0x62, 0xb4, 0xc4, 0x1d, 0x12, 0x0c, 0x0c, 0x97, 0x80, 0xf8, 0x0b,
+       0x10, 0x67, 0x02, 0xed, 0xf5, 0x92, 0x64, 0x60, 0xf0, 0x06, 0xe2, 0x6d,
+       0x40, 0xbc, 0x1d, 0x88, 0xc5, 0xa5, 0x18, 0x18, 0x02, 0x80, 0x38, 0x10,
+       0x88, 0xfb, 0x80, 0xfc, 0x7e, 0x20, 0x4e, 0x07, 0xe2, 0x24, 0xa8, 0x1b,
+       0xb3, 0x05, 0x19, 0x18, 0x72, 0x81, 0x38, 0x1f, 0x88, 0x0b, 0x81, 0x58,
+       0x48, 0x80, 0x81, 0x41, 0x58, 0x80, 0x78, 0xfb, 0xcb, 0x15, 0x19, 0x18,
+       0x5e, 0xab, 0x22, 0xf8, 0x5a, 0x6a, 0x0c, 0x0c, 0xc9, 0x1a, 0xf4, 0xf3,
+       0xff, 0x60, 0xc3, 0x8e, 0xb6, 0xf4, 0xb5, 0xef, 0x14, 0xd0, 0xbe, 0xe5,
+       0x6e, 0x08, 0xbe, 0x04, 0x90, 0xbd, 0xc2, 0x0d, 0x55, 0xcd, 0x4a, 0x37,
+       0xfc, 0x66, 0xac, 0x42, 0x93, 0x5f, 0x8d, 0xc6, 0x5f, 0x83, 0x47, 0x7f,
+       0xa2, 0x0d, 0x2a, 0x7f, 0x99, 0x29, 0x2a, 0x7f, 0x9d, 0x39, 0x03, 0xc3,
+       0x43, 0x24, 0x35, 0xcb, 0x4d, 0xf1, 0xbb, 0x05, 0x1d, 0x0b, 0x02, 0xfd,
+       0x27, 0x84, 0x27, 0x4c, 0x97, 0x30, 0xa2, 0xf2, 0x27, 0x32, 0xa1, 0xf2,
+       0xf9, 0xa1, 0x7c, 0x00, 0xba, 0x0b, 0x80, 0x74, 0xa8, 0x03, 0x00, 0x00,
+       0x00, 0x00, 0x00, 0x00
+};
+
+static const u8 xsem_pram_data_e1h[] = {
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
+       0x0d, 0x78, 0x54, 0xd5, 0x99, 0xf0, 0xb9, 0x3f, 0x73, 0x67, 0x26, 0x99,
+       0x99, 0xdc, 0x24, 0x43, 0x32, 0x60, 0x12, 0x6e, 0x7e, 0xd0, 0xa0, 0x01,
+       0x87, 0x98, 0x60, 0xb0, 0x58, 0x6e, 0x20, 0xe1, 0x47, 0xa3, 0x0e, 0x08,
+       0x2c, 0xb4, 0x40, 0x26, 0x28, 0x88, 0x16, 0x6d, 0xc4, 0x9f, 0xc6, 0xdd,
+       0x50, 0x06, 0x09, 0xbf, 0x09, 0x21, 0xe1, 0x4f, 0x70, 0xd1, 0x1d, 0x10,
+       0x5d, 0xea, 0x63, 0xfb, 0xc5, 0x56, 0x5b, 0x75, 0xbb, 0x76, 0x82, 0xd6,
+       0x46, 0xab, 0x35, 0x68, 0xd7, 0x87, 0x76, 0x77, 0x65, 0xa0, 0x15, 0xbf,
+       0xba, 0x76, 0x1b, 0xd9, 0x6d, 0x97, 0x6e, 0xbb, 0xf5, 0x7b, 0xdf, 0xf7,
+       0x9c, 0xcb, 0xcc, 0xbd, 0x99, 0x00, 0xfe, 0xec, 0xb7, 0xbb, 0xdf, 0xf3,
+       0xc5, 0xc7, 0xe7, 0x70, 0xee, 0x3d, 0x3f, 0xef, 0x79, 0xcf, 0xfb, 0x7f,
+       0xde, 0x73, 0xc7, 0xc5, 0x46, 0xb1, 0xe0, 0x58, 0xc6, 0x3e, 0xc6, 0xbf,
+       0x69, 0x8c, 0x4d, 0xcc, 0x65, 0x8c, 0xd5, 0xa6, 0xca, 0x16, 0x0f, 0x8b,
+       0x65, 0xe7, 0x30, 0x96, 0xdb, 0x21, 0x31, 0x56, 0xc3, 0xd8, 0xca, 0x76,
+       0x25, 0x3e, 0x0b, 0xfe, 0x59, 0xd8, 0xd1, 0xf2, 0x0a, 0xd6, 0x97, 0xb7,
+       0xb9, 0x0d, 0x77, 0x29, 0x63, 0xfd, 0x0f, 0xb8, 0xfd, 0x35, 0x50, 0x3f,
+       0xbd, 0x5d, 0x09, 0xbb, 0xa1, 0x6b, 0xa3, 0xe2, 0xa3, 0xfa, 0xb2, 0x2e,
+       0x57, 0xd8, 0x6d, 0xc0, 0xf3, 0xad, 0x1f, 0xbd, 0x9c, 0x8f, 0xef, 0x37,
+       0x4a, 0x61, 0x06, 0x75, 0xc6, 0xee, 0x66, 0x6c, 0x32, 0x63, 0x6b, 0x3c,
+       0xf0, 0x4f, 0xa8, 0x2f, 0xab, 0x48, 0x76, 0xe0, 0xfb, 0x77, 0xb7, 0x48,
+       0xe1, 0x18, 0xbe, 0x66, 0xa6, 0x6f, 0x12, 0xbc, 0xbf, 0x95, 0xf1, 0xf7,
+       0xcd, 0x0f, 0x28, 0x1a, 0x93, 0xa1, 0xbe, 0xef, 0xb6, 0x26, 0x36, 0x91,
+       0xb1, 0x5b, 0x7a, 0x60, 0x16, 0x0f, 0x35, 0x64, 0x1f, 0xf3, 0xf6, 0x8c,
+       0x15, 0x30, 0x16, 0xe1, 0x8f, 0x58, 0xcb, 0x16, 0x78, 0x5f, 0x99, 0x7a,
+       0x1f, 0x61, 0x5d, 0x1f, 0x29, 0xd0, 0xaf, 0x39, 0xe6, 0x78, 0xbe, 0x6f,
+       0xd6, 0xfb, 0x2c, 0x80, 0xef, 0xb5, 0xd4, 0x73, 0x58, 0xcf, 0x31, 0xfc,
+       0xc7, 0x14, 0xc6, 0x2e, 0x65, 0xfe, 0xe0, 0xe9, 0x6c, 0xf8, 0x77, 0x98,
+       0x85, 0x3f, 0x56, 0xa0, 0x6c, 0xc8, 0x67, 0x6c, 0x74, 0x0a, 0x5f, 0xce,
+       0x92, 0x31, 0x80, 0x7e, 0x14, 0x63, 0x73, 0x19, 0x73, 0xb1, 0x72, 0x18,
+       0xa7, 0xf6, 0x32, 0x17, 0x2b, 0x83, 0xf5, 0x59, 0x78, 0x6c, 0xe3, 0x78,
+       0x5c, 0xd6, 0x24, 0x11, 0x1e, 0x97, 0xf9, 0x18, 0xd5, 0xdf, 0x9d, 0x2b,
+       0xc5, 0x1f, 0x2c, 0xa5, 0x7e, 0x6c, 0x7a, 0x35, 0x94, 0xf0, 0xbc, 0x20,
+       0x0f, 0xca, 0x20, 0x33, 0x0b, 0xa1, 0x8c, 0x78, 0x58, 0x22, 0x1b, 0xe0,
+       0x9f, 0xdb, 0x76, 0xd9, 0x7b, 0xb8, 0xfe, 0x0d, 0x38, 0xd5, 0x68, 0x6a,
+       0x9f, 0x08, 0xc0, 0xfb, 0x05, 0x2c, 0xea, 0x62, 0x00, 0xdf, 0x9f, 0xb1,
+       0x18, 0x95, 0x8b, 0x59, 0x9c, 0xca, 0x2f, 0xb3, 0x04, 0xc1, 0xb1, 0x94,
+       0x0d, 0x95, 0xa8, 0x50, 0xbf, 0x4b, 0x49, 0x6c, 0x62, 0x30, 0x4f, 0x38,
+       0x14, 0x9d, 0x8e, 0xfb, 0xfb, 0xbb, 0xfa, 0x63, 0xef, 0x4a, 0xf0, 0xfe,
+       0xfe, 0x6a, 0xa9, 0x76, 0x0a, 0x94, 0xcc, 0x97, 0x47, 0xeb, 0xbe, 0xd0,
+       0xfa, 0xac, 0xf9, 0x55, 0x16, 0xb9, 0x0e, 0xc7, 0x61, 0x4c, 0x76, 0x45,
+       0xfc, 0x8c, 0x8d, 0xb7, 0xd6, 0x79, 0x98, 0xc5, 0x2a, 0x82, 0x8c, 0xe9,
+       0x3d, 0x3e, 0x4e, 0x2f, 0x87, 0x59, 0x3f, 0x83, 0xfa, 0xf8, 0x06, 0x41,
+       0x2f, 0x8d, 0xef, 0xcb, 0x21, 0x58, 0x77, 0xcf, 0xf3, 0x2c, 0x8c, 0xf5,
+       0x10, 0x6c, 0xe6, 0x14, 0xa8, 0x87, 0xba, 0xb2, 0xe2, 0x1b, 0xa0, 0xde,
+       0xf3, 0x78, 0xac, 0x1e, 0xf1, 0x72, 0xac, 0x05, 0x30, 0x0f, 0xfd, 0x8f,
+       0x35, 0xba, 0xa5, 0x68, 0x15, 0x94, 0x2e, 0xdd, 0x15, 0x81, 0x32, 0xa4,
+       0x32, 0xa6, 0x00, 0x9e, 0xea, 0x1b, 0xd6, 0x4b, 0x0a, 0xb4, 0x9b, 0x1b,
+       0xe5, 0xe3, 0x8c, 0x37, 0x35, 0x99, 0x5d, 0x09, 0xf5, 0xc3, 0x31, 0x49,
+       0x15, 0xcf, 0xb1, 0xbf, 0xae, 0xc7, 0x24, 0x1d, 0xea, 0xe3, 0xa1, 0xfe,
+       0xa0, 0x84, 0xef, 0x75, 0x17, 0x83, 0x71, 0x1a, 0x1a, 0x72, 0x5d, 0xc9,
+       0x2a, 0xc4, 0x77, 0xcf, 0x18, 0x1d, 0xca, 0x8a, 0xc3, 0x5a, 0x42, 0x06,
+       0xfc, 0xd6, 0x9b, 0x3a, 0x3d, 0x67, 0x6c, 0x11, 0xd1, 0xd5, 0x78, 0x41,
+       0x6b, 0x73, 0x4d, 0xde, 0x6f, 0xee, 0xe1, 0x3c, 0x3f, 0xa3, 0xf7, 0xec,
+       0x4f, 0x1f, 0x5b, 0xef, 0x01, 0xbf, 0x97, 0x14, 0xf1, 0x7d, 0x3b, 0x76,
+       0xb8, 0x2c, 0x07, 0xe1, 0x65, 0x51, 0x7b, 0xff, 0x22, 0x95, 0xc5, 0x3c,
+       0x79, 0x29, 0x3c, 0xef, 0x5c, 0x07, 0x2f, 0xdc, 0x29, 0xfc, 0xee, 0x3a,
+       0x5c, 0xb6, 0x15, 0xf1, 0x76, 0xac, 0x4f, 0x0d, 0x0b, 0x52, 0xb6, 0x8d,
+       0x0f, 0xe3, 0xf6, 0x36, 0xc0, 0xfb, 0x33, 0x55, 0x72, 0x58, 0x31, 0x90,
+       0xcf, 0x8a, 0x38, 0xfc, 0x15, 0xba, 0x5f, 0xf7, 0xa5, 0xc6, 0xd9, 0xb9,
+       0x0e, 0xda, 0x5f, 0x96, 0x82, 0xa3, 0x51, 0x99, 0xda, 0x4f, 0xf8, 0x30,
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+       0xca, 0x19, 0x8b, 0x8e, 0x97, 0x09, 0xb9, 0x03, 0x72, 0xb5, 0x52, 0x05,
+       0xfa, 0x6a, 0x66, 0x59, 0x61, 0xd4, 0x9b, 0xcd, 0x6d, 0xe5, 0xe7, 0xb5,
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+       0xb4, 0xcb, 0xff, 0x9b, 0x67, 0x5f, 0x62, 0x6b, 0xbf, 0x20, 0x52, 0x6e,
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+       0xd4, 0x97, 0x26, 0x57, 0x7c, 0xb2, 0x44, 0xf8, 0xfc, 0x0d, 0xb0, 0x09,
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+       0x01, 0xd4, 0xdf, 0xc9, 0x92, 0x25, 0xb8, 0x6f, 0xee, 0x5c, 0x83, 0xde,
+       0xdf, 0x25, 0x27, 0x0b, 0xb0, 0xfe, 0x1b, 0x36, 0xb4, 0x37, 0x1f, 0xf7,
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+       0x0b, 0x7b, 0xdc, 0x30, 0x1f, 0x58, 0x43, 0xac, 0x0d, 0xe8, 0xa3, 0xa5,
+       0xed, 0x47, 0xc7, 0xd1, 0x8e, 0x93, 0x8c, 0x20, 0x5b, 0x82, 0x75, 0x8f,
+       0x2f, 0x81, 0xfc, 0xcd, 0x3a, 0x5c, 0x1f, 0x26, 0x2d, 0xbc, 0x03, 0x1f,
+       0xf6, 0x86, 0xa2, 0x1f, 0x4a, 0x00, 0x87, 0xd4, 0xde, 0xff, 0x7b, 0x09,
+       0xdf, 0x7f, 0x9f, 0x19, 0xa8, 0x87, 0x59, 0xb2, 0x28, 0x17, 0xfd, 0x47,
+       0x9c, 0x2a, 0x9d, 0x0f, 0x9b, 0x66, 0xb0, 0x56, 0xc4, 0xd7, 0x89, 0x46,
+       0x3b, 0xde, 0xbc, 0x62, 0x1d, 0x3f, 0x97, 0x64, 0x6a, 0xf7, 0x1c, 0x33,
+       0x7f, 0x8b, 0x7c, 0x74, 0x52, 0xd2, 0xf9, 0xfa, 0x04, 0xbc, 0xdb, 0x24,
+       0xf3, 0x2c, 0xce, 0x67, 0xc1, 0xfd, 0x6e, 0xae, 0xae, 0xb1, 0x4f, 0x07,
+       0xb7, 0x22, 0xd7, 0x22, 0xdc, 0x3f, 0x22, 0xb8, 0x37, 0xb4, 0xb2, 0x64,
+       0xb6, 0x32, 0x32, 0xdc, 0x57, 0x30, 0xd3, 0x2d, 0x8f, 0x1a, 0x0e, 0xcf,
+       0x59, 0x66, 0x66, 0x65, 0x7a, 0x3e, 0x0b, 0xd8, 0x35, 0xd3, 0xf3, 0xcb,
+       0xdd, 0xac, 0x12, 0xed, 0xd5, 0x13, 0x52, 0x56, 0x78, 0x7d, 0x29, 0x96,
+       0x43, 0xff, 0xf8, 0x35, 0xe0, 0xab, 0xd8, 0x37, 0x7c, 0xe1, 0xc7, 0x8d,
+       0xe1, 0x74, 0x31, 0x55, 0xce, 0xa5, 0xf9, 0x9b, 0x85, 0xbd, 0x5b, 0xd8,
+       0x2e, 0x25, 0xb2, 0xd1, 0x3e, 0x65, 0x1e, 0xb2, 0x5f, 0x59, 0xcf, 0x43,
+       0xa6, 0x07, 0xe5, 0x9a, 0x10, 0x71, 0x2d, 0x6d, 0xd2, 0x49, 0x5c, 0x3f,
+       0xeb, 0x68, 0x34, 0x93, 0x9e, 0xd4, 0x7a, 0x99, 0x21, 0xb1, 0xf4, 0x76,
+       0xe7, 0xf6, 0xbd, 0xcd, 0x4d, 0xed, 0x2d, 0x79, 0x63, 0xc9, 0x2d, 0x0b,
+       0x9f, 0x96, 0x5c, 0xb1, 0xe4, 0x97, 0x85, 0x57, 0xe7, 0xf8, 0x23, 0xc9,
+       0x19, 0x1c, 0x4f, 0xcd, 0x43, 0xf8, 0xa3, 0x93, 0xe4, 0x74, 0x3a, 0xd1,
+       0x01, 0x1f, 0x13, 0x10, 0x1e, 0xb3, 0x1a, 0xf7, 0xcf, 0xda, 0x37, 0x70,
+       0x23, 0x63, 0x9e, 0xea, 0x91, 0xf7, 0xcd, 0x92, 0x53, 0xd0, 0x8e, 0xa1,
+       0xff, 0x3f, 0xd2, 0x7e, 0x01, 0x9e, 0xc8, 0xae, 0x73, 0x85, 0x19, 0xe1,
+       0xe9, 0xdd, 0xe0, 0xd0, 0xd2, 0xa7, 0x60, 0xdd, 0x03, 0x6d, 0x5c, 0x5f,
+       0xbf, 0x5b, 0xc4, 0xc8, 0x3e, 0x3c, 0xd3, 0x76, 0xd5, 0x40, 0x0e, 0xe2,
+       0xc7, 0xe3, 0xa9, 0x40, 0xfc, 0x14, 0xf2, 0xa9, 0x58, 0x61, 0x70, 0x68,
+       0x1d, 0xca, 0x57, 0x9f, 0x9a, 0xe8, 0x47, 0xb8, 0x0a, 0x85, 0xfe, 0xf2,
+       0x32, 0xae, 0xbf, 0x0a, 0x99, 0xb1, 0xe3, 0x6a, 0xf4, 0xef, 0xdb, 0x4f,
+       0x2e, 0xc1, 0x76, 0xd6, 0xfe, 0xe4, 0x8a, 0xfd, 0x69, 0x86, 0xfd, 0x41,
+       0x7f, 0xa4, 0xd9, 0x37, 0x54, 0x8c, 0x76, 0x92, 0x1b, 0xf5, 0x1a, 0xb4,
+       0x73, 0x83, 0xdc, 0x45, 0xb9, 0x5c, 0xd8, 0xfe, 0xfe, 0x7f, 0xa0, 0x5e,
+       0x2c, 0x74, 0xe8, 0x45, 0x84, 0x84, 0xa5, 0xc3, 0x91, 0x55, 0xb5, 0xe3,
+       0x6a, 0x23, 0x7d, 0xfc, 0x8f, 0x36, 0xa2, 0x7d, 0x69, 0x8d, 0x4b, 0x1d,
+       0xd2, 0xf7, 0x3f, 0xa8, 0x9d, 0x44, 0xfc, 0x16, 0xb6, 0x6f, 0xbe, 0x5b,
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+       0xb9, 0x79, 0x4a, 0xd1, 0x5e, 0x95, 0x13, 0xee, 0x40, 0x8a, 0x2e, 0x9c,
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+       0x02, 0xc4, 0x2b, 0xd8, 0x0d, 0x03, 0x6e, 0x5e, 0x7a, 0x70, 0x1c, 0xff,
+       0xfa, 0x9b, 0x4b, 0x25, 0x80, 0xdb, 0x63, 0x0c, 0xf5, 0xbb, 0xb1, 0x7d,
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+       0xc8, 0x2a, 0xcd, 0xb7, 0xa3, 0x62, 0xe7, 0x6c, 0xdc, 0xef, 0x58, 0x4c,
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+       0x76, 0x5f, 0xd6, 0x22, 0xf4, 0xaf, 0x00, 0x75, 0x2a, 0xc6, 0x6b, 0x42,
+       0x31, 0x7d, 0xde, 0x6c, 0x8c, 0x47, 0x4e, 0xcd, 0x9b, 0x84, 0x3e, 0xf6,
+       0x8f, 0x51, 0xff, 0xc0, 0xbc, 0xbb, 0x23, 0x67, 0xf4, 0x16, 0xdf, 0x27,
+       0xc2, 0x47, 0x41, 0x48, 0x19, 0x19, 0x1f, 0x6f, 0xca, 0x32, 0xdf, 0x47,
+       0x07, 0xdf, 0xee, 0x01, 0x77, 0x0d, 0xe5, 0x67, 0x52, 0xf2, 0x50, 0xfc,
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+       0xff, 0xf4, 0x6a, 0x85, 0xe3, 0xa9, 0x3f, 0xc6, 0xe3, 0x14, 0xaa, 0x29,
+       0x93, 0xde, 0x9a, 0xa9, 0x34, 0x31, 0x09, 0xf0, 0xb4, 0x21, 0xc8, 0x48,
+       0x1e, 0xe4, 0xe1, 0x5e, 0x23, 0xdf, 0x36, 0xb0, 0x38, 0xa0, 0x80, 0xe5,
+       0xb3, 0xf0, 0x80, 0x0f, 0xe5, 0x49, 0x50, 0x66, 0x09, 0xf2, 0x5b, 0x9d,
+       0x7e, 0xa0, 0xd9, 0x84, 0x7e, 0x60, 0x90, 0x83, 0xc6, 0xf4, 0x51, 0x65,
+       0xfd, 0x85, 0xf0, 0x3c, 0x38, 0x7f, 0x25, 0x9d, 0x33, 0xb0, 0x08, 0x97,
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+       0xc6, 0x26, 0x51, 0x9c, 0x33, 0xaf, 0xc9, 0x2e, 0xc7, 0xdd, 0xe8, 0x07,
+       0x82, 0x7c, 0xd4, 0x1b, 0x1c, 0xcf, 0xe7, 0xcf, 0xa4, 0xf3, 0x06, 0x37,
+       0x4b, 0x7b, 0x0e, 0xeb, 0xb8, 0x4a, 0xf1, 0x07, 0x4f, 0x83, 0x69, 0xcf,
+       0xaa, 0x59, 0x0d, 0xf2, 0x67, 0xf5, 0xfe, 0xab, 0x76, 0x2d, 0x86, 0xf1,
+       0x6b, 0x1e, 0xb9, 0xf9, 0x6d, 0x2c, 0x27, 0x1f, 0xbc, 0x27, 0xff, 0x4b,
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+       0x5f, 0xc5, 0xc2, 0x09, 0xec, 0xdf, 0xde, 0x8f, 0xb8, 0x85, 0xf5, 0x9a,
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+       0x6d, 0x20, 0xa1, 0x2e, 0xd8, 0x53, 0x36, 0xab, 0x68, 0xbd, 0x8a, 0xb4,
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+       0x67, 0x64, 0x37, 0x6e, 0x04, 0xfe, 0x8b, 0x95, 0x66, 0xe2, 0x9f, 0x6a,
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+       0xf9, 0xbd, 0xf8, 0xc6, 0xeb, 0xaf, 0x81, 0xf9, 0x6f, 0x7f, 0x7c, 0x4f,
+       0x36, 0xee, 0xf3, 0xa3, 0xaf, 0x02, 0x3f, 0x9d, 0xc7, 0x8f, 0xb7, 0xf8,
+       0xa9, 0x19, 0x6d, 0xd8, 0xf3, 0xc4, 0xd9, 0x8c, 0xb5, 0x76, 0x7e, 0x32,
+       0xd6, 0x57, 0x10, 0x3f, 0xbd, 0xa5, 0x70, 0xfd, 0xd5, 0xbf, 0xe0, 0x77,
+       0x6f, 0x5c, 0xfd, 0xff, 0xf9, 0xe9, 0x7c, 0xfc, 0xf4, 0xb6, 0x02, 0xf4,
+       0x39, 0xed, 0x4f, 0x67, 0x8b, 0xa3, 0xe7, 0x91, 0x6f, 0xcd, 0x45, 0x4c,
+       0x43, 0x7b, 0x0b, 0xda, 0x98, 0x48, 0xe7, 0xd1, 0xa0, 0xbd, 0xf4, 0xa9,
+       0x59, 0x84, 0xef, 0x75, 0x2e, 0x2e, 0xc7, 0xfc, 0x2e, 0x2f, 0xb7, 0x3b,
+       0x42, 0xfc, 0xbd, 0x73, 0xbc, 0xbf, 0x51, 0x3f, 0x79, 0xfc, 0x60, 0x41,
+       0xf9, 0x67, 0xe7, 0xd3, 0x75, 0x3e, 0xf3, 0xa3, 0xcf, 0x83, 0xdf, 0x41,
+       0xee, 0x90, 0xbc, 0x39, 0x31, 0xce, 0xce, 0xf7, 0x9d, 0x2e, 0x4e, 0x77,
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+       0xd7, 0x93, 0x7d, 0x77, 0x9d, 0xca, 0x0c, 0xf4, 0x03, 0x26, 0xbe, 0xe0,
+       0x21, 0x61, 0xf1, 0xea, 0xb8, 0x8d, 0x47, 0x90, 0x25, 0xa6, 0xc1, 0xf3,
+       0x50, 0x1e, 0x7f, 0xef, 0xce, 0x23, 0x79, 0x19, 0x47, 0x3b, 0x66, 0x48,
+       0xa9, 0xa4, 0xfe, 0x26, 0xe3, 0x76, 0x7c, 0x53, 0xcd, 0xe6, 0x23, 0xfc,
+       0x5c, 0x62, 0xb0, 0x62, 0x11, 0xf8, 0xcb, 0x73, 0xe0, 0x5f, 0x68, 0x8f,
+       0x5c, 0xe7, 0xe3, 0x7e, 0x05, 0x8c, 0xc3, 0x42, 0x30, 0xfe, 0x6a, 0x6f,
+       0xb4, 0x58, 0x1d, 0x45, 0xe3, 0x91, 0x7f, 0xf9, 0xea, 0xf3, 0xfb, 0x82,
+       0x28, 0x5f, 0x5e, 0xf7, 0x98, 0x25, 0xf8, 0x9c, 0x25, 0xd5, 0x5c, 0x3c,
+       0x1f, 0xb0, 0xec, 0x8e, 0x91, 0xf9, 0x5d, 0x65, 0xa7, 0xd3, 0xfc, 0xac,
+       0xa7, 0x35, 0x46, 0x70, 0x9c, 0xba, 0x54, 0xa3, 0x78, 0x25, 0x8a, 0xb1,
+       0x00, 0xd4, 0xb7, 0x96, 0x5e, 0x4a, 0x71, 0x4a, 0x16, 0x8e, 0x1d, 0x97,
+       0xb0, 0x3e, 0x4a, 0x67, 0x28, 0xc7, 0x95, 0x60, 0x64, 0x31, 0xd9, 0x21,
+       0x6d, 0x6e, 0x63, 0x16, 0xd4, 0xb7, 0x82, 0x01, 0x15, 0x0b, 0x12, 0xdd,
+       0x92, 0xdc, 0x54, 0xda, 0x7b, 0x43, 0x01, 0x94, 0x03, 0x60, 0x97, 0xe0,
+       0x7b, 0x35, 0x36, 0xd7, 0xa3, 0xa1, 0xff, 0x32, 0x4a, 0xc6, 0x20, 0x34,
+       0x73, 0xb7, 0x7d, 0x44, 0x7e, 0xf7, 0x89, 0x62, 0x2e, 0x6f, 0x3b, 0xa6,
+       0x30, 0x3a, 0xa7, 0x19, 0x78, 0xe0, 0xdf, 0x96, 0xca, 0x68, 0xef, 0xb4,
+       0xbb, 0xe9, 0xdc, 0x02, 0xec, 0x46, 0xe2, 0xd7, 0xa8, 0x90, 0x1b, 0xc9,
+       0xe0, 0xf4, 0x50, 0x0b, 0xfa, 0x19, 0x45, 0x5a, 0x58, 0x82, 0xfa, 0xa6,
+       0xd8, 0x2f, 0x8e, 0x7f, 0x8d, 0xcb, 0x13, 0xd3, 0x33, 0x39, 0x3d, 0x3e,
+       0xc2, 0xe3, 0x1d, 0x2d, 0x21, 0xee, 0xef, 0x3a, 0xed, 0xbe, 0xcd, 0x5f,
+       0xbf, 0xec, 0x4d, 0x03, 0xc7, 0xfb, 0xe1, 0x6b, 0x5d, 0x97, 0x43, 0xf9,
+       0xfa, 0x93, 0x3f, 0x7f, 0xfd, 0x72, 0x78, 0xf7, 0xc6, 0xb7, 0x5e, 0xab,
+       0xc1, 0xb8, 0xb7, 0xbb, 0x4e, 0xb3, 0xc5, 0x1d, 0xdd, 0xcc, 0x78, 0x13,
+       0xed, 0x2d, 0xf0, 0x99, 0x12, 0x1a, 0xca, 0xe7, 0xd8, 0xc9, 0x25, 0xb8,
+       0x99, 0x29, 0xbf, 0x4e, 0x8a, 0x21, 0x7e, 0xa2, 0x35, 0xfe, 0x38, 0xae,
+       0x17, 0x79, 0x1b, 0xf1, 0x93, 0x9c, 0xa2, 0xf0, 0xf3, 0x45, 0xf8, 0x0b,
+       0x01, 0x7c, 0x01, 0x01, 0x5f, 0x77, 0xf0, 0x54, 0x15, 0xcd, 0x13, 0x7b,
+       0xff, 0x3f, 0x32, 0xc9, 0x7b, 0xfa, 0x9b, 0x2c, 0xf4, 0x08, 0xb4, 0xdb,
+       0x9c, 0x77, 0x7f, 0x1c, 0xe5, 0x48, 0x6a, 0xbe, 0x49, 0x24, 0x9f, 0xa2,
+       0x20, 0x9f, 0xd0, 0x8f, 0x8c, 0xfa, 0x7a, 0x96, 0xac, 0xa1, 0xf9, 0xfc,
+       0xe1, 0x07, 0xb1, 0xcf, 0x1f, 0x61, 0x57, 0x27, 0xa7, 0xce, 0x0b, 0x0f,
+       0x6d, 0x99, 0xd7, 0x82, 0x78, 0x9e, 0xbb, 0xc0, 0xa3, 0x23, 0x9d, 0xb9,
+       0x63, 0x9b, 0xef, 0x46, 0x3a, 0x77, 0xae, 0xf3, 0x8c, 0xef, 0xc1, 0x4b,
+       0x31, 0x34, 0x67, 0x9b, 0x1f, 0xf8, 0xc4, 0x5d, 0xa1, 0x99, 0x5e, 0xb2,
+       0x7f, 0xd9, 0x61, 0xda, 0x0f, 0xd1, 0xc4, 0x82, 0x5b, 0x07, 0x05, 0x82,
+       0x71, 0x07, 0xe8, 0xbf, 0x6c, 0x05, 0xcb, 0xd0, 0xdf, 0x80, 0xfe, 0xb8,
+       0x4e, 0x90, 0x67, 0x68, 0x6f, 0x5b, 0xfd, 0x80, 0x8c, 0x4d, 0x5c, 0xef,
+       0x19, 0xdf, 0xf4, 0x4b, 0x29, 0xde, 0x2f, 0xe2, 0x15, 0x56, 0xbf, 0x9b,
+       0x62, 0x12, 0x9d, 0x13, 0xdc, 0x54, 0x0e, 0x6c, 0x50, 0x3e, 0x1c, 0x4f,
+       0x1b, 0x7c, 0xf2, 0x4f, 0xbe, 0x86, 0xe7, 0x2e, 0x31, 0x45, 0x57, 0x38,
+       0x1d, 0x84, 0x2a, 0xd2, 0xf0, 0x86, 0x7f, 0xf6, 0xb8, 0x19, 0xa7, 0x8b,
+       0xcb, 0xf6, 0xd9, 0xf5, 0x2e, 0xcc, 0xbf, 0xb0, 0x14, 0xdf, 0xc7, 0x14,
+       0xa2, 0x17, 0x27, 0xbf, 0x8c, 0x8f, 0xdb, 0xdb, 0x6f, 0xf0, 0x9d, 0xff,
+       0x5c, 0x7f, 0xf8, 0x7e, 0x72, 0x3c, 0x4f, 0x14, 0xfc, 0x66, 0xf5, 0xb7,
+       0xe0, 0x23, 0x78, 0xa5, 0x4c, 0xf1, 0x75, 0xfb, 0xb9, 0xcc, 0x4d, 0x75,
+       0xf6, 0xfa, 0xdc, 0x61, 0xf8, 0x38, 0x3f, 0x5c, 0xd3, 0x55, 0xfb, 0xb9,
+       0x4d, 0x83, 0xcf, 0x3e, 0xde, 0xcc, 0xa0, 0xfd, 0xfd, 0xec, 0x22, 0x7b,
+       0x7d, 0x03, 0xc6, 0x6f, 0x3e, 0xc9, 0xba, 0x1d, 0x7c, 0xf7, 0xf4, 0x18,
+       0xf3, 0x3b, 0xea, 0x67, 0xf0, 0xeb, 0x2d, 0xb9, 0xfb, 0xbe, 0x27, 0xf2,
+       0xb7, 0x34, 0x8e, 0x1a, 0x66, 0x38, 0x4e, 0xff, 0x82, 0xbd, 0xf3, 0xe7,
+       0x01, 0x1d, 0x14, 0xea, 0xdc, 0xee, 0x28, 0x9c, 0xbf, 0xb0, 0x21, 0xb7,
+       0x06, 0xe5, 0x14, 0x13, 0x79, 0x26, 0x99, 0xed, 0x8f, 0x42, 0xa1, 0xef,
+       0x95, 0xf6, 0x97, 0x94, 0x1c, 0xf4, 0x47, 0x4d, 0xde, 0x3e, 0xb9, 0xe4,
+       0xad, 0x19, 0x39, 0x78, 0x5e, 0x5c, 0xc7, 0xe8, 0x3c, 0x3d, 0xaa, 0xde,
+       0x13, 0xcb, 0x31, 0x52, 0xf6, 0x48, 0xbf, 0x5a, 0x9e, 0x85, 0x78, 0xfe,
+       0xfc, 0xed, 0x91, 0xbb, 0xbd, 0xe9, 0x79, 0x37, 0x29, 0x7b, 0xe4, 0x81,
+       0x57, 0x8d, 0x9a, 0x0c, 0xf6, 0x88, 0x7a, 0x8f, 0x64, 0xc2, 0x38, 0xb3,
+       0x96, 0x80, 0x3d, 0x52, 0x95, 0x6e, 0x8f, 0xb4, 0x4a, 0x28, 0x83, 0xb2,
+       0x97, 0x80, 0x3d, 0x42, 0x76, 0x47, 0xf4, 0x3d, 0xc4, 0xd7, 0x48, 0x76,
+       0xc9, 0x8f, 0x2d, 0xfb, 0xde, 0x9f, 0xd9, 0xae, 0xfe, 0x83, 0xca, 0xf5,
+       0x2c, 0xe8, 0x99, 0x7f, 0xfa, 0x2c, 0x7a, 0x66, 0x9c, 0xd7, 0xfc, 0x17,
+       0xf5, 0x73, 0xb0, 0x07, 0xa6, 0x95, 0x18, 0x2b, 0x23, 0x19, 0xe8, 0xf0,
+       0x03, 0x95, 0xc7, 0x3b, 0x2c, 0xfd, 0xd9, 0x18, 0x4c, 0x28, 0x78, 0x76,
+       0x0e, 0x7a, 0x53, 0x75, 0xc1, 0xf3, 0x6b, 0xeb, 0x92, 0x2f, 0xa1, 0x38,
+       0xee, 0xd0, 0x77, 0x06, 0x71, 0xdd, 0xb0, 0x1e, 0x97, 0xab, 0xf6, 0xd3,
+       0xaf, 0xe7, 0x8c, 0xca, 0xe1, 0x99, 0xa8, 0xf2, 0x3c, 0x98, 0x91, 0xfa,
+       0x7d, 0x6b, 0x04, 0x7f, 0xc5, 0xab, 0x79, 0x85, 0xdd, 0x62, 0xdf, 0xef,
+       0xfe, 0x05, 0xef, 0xe8, 0x32, 0xfa, 0x2f, 0xe0, 0xc7, 0xa0, 0xff, 0x92,
+       0xf4, 0x95, 0x6d, 0xc3, 0xb8, 0xe0, 0x99, 0x98, 0x4a, 0xf1, 0x3a, 0x75,
+       0xfe, 0xca, 0xdd, 0x73, 0x91, 0x9e, 0xc0, 0xce, 0xe6, 0xf4, 0x7c, 0x7e,
+       0xfb, 0xfa, 0xda, 0x21, 0xd9, 0xc6, 0xc7, 0xd3, 0xce, 0x66, 0xd9, 0xf8,
+       0xbe, 0x9e, 0xd9, 0xcf, 0xe9, 0x66, 0x78, 0xec, 0xe7, 0x74, 0x8d, 0xba,
+       0xfd, 0x9c, 0x6e, 0x56, 0xc8, 0x7e, 0x4e, 0x37, 0xc7, 0xb0, 0x9f, 0xd3,
+       0x5d, 0x5f, 0x69, 0x3f, 0xa7, 0x73, 0xda, 0xf7, 0x33, 0x47, 0xbb, 0xfe,
+       0x7b, 0xda, 0xf7, 0xa1, 0x46, 0x46, 0xfc, 0x74, 0x01, 0xfb, 0x1e, 0xf8,
+       0xe9, 0x26, 0xa4, 0xa7, 0x91, 0xf8, 0xe9, 0xba, 0x7c, 0xe3, 0xfe, 0x48,
+       0x86, 0xfd, 0xae, 0xd6, 0xb8, 0x9d, 0xba, 0xda, 0x1b, 0x59, 0x80, 0x74,
+       0x37, 0xcd, 0xe0, 0x76, 0x5d, 0x34, 0xb6, 0x9e, 0xf2, 0x01, 0xf3, 0xa2,
+       0x20, 0x6f, 0x4a, 0x29, 0x6e, 0x48, 0x71, 0x2f, 0x2b, 0xae, 0x65, 0xc5,
+       0xbd, 0xac, 0xbc, 0x40, 0x2b, 0x9e, 0xe5, 0x8c, 0x5f, 0x59, 0x71, 0x2f,
+       0x2b, 0x8e, 0x25, 0xc5, 0x78, 0xdc, 0xaa, 0xd9, 0x13, 0x5d, 0x81, 0xf0,
+       0x36, 0xb7, 0x9f, 0x94, 0x51, 0x8e, 0xe8, 0xcf, 0xc1, 0x3c, 0xc8, 0x08,
+       0xd6, 0x39, 0xde, 0xb0, 0xf8, 0x1c, 0x97, 0x07, 0x2d, 0xed, 0x99, 0xe3,
+       0x72, 0xce, 0xf8, 0xdb, 0x88, 0xed, 0x3e, 0x25, 0x5f, 0x7d, 0x0e, 0xfa,
+       0x61, 0x3d, 0xae, 0xd7, 0xd2, 0x0f, 0xc0, 0xe7, 0x0f, 0x7e, 0x16, 0x3e,
+       0x07, 0xb9, 0xb5, 0x0d, 0xc7, 0xfb, 0x17, 0xe4, 0xf7, 0x51, 0x24, 0x4f,
+       0xba, 0x69, 0xff, 0x2a, 0x00, 0xd7, 0x68, 0xa7, 0xc3, 0x3e, 0x68, 0x18,
+       0xa7, 0x5f, 0x70, 0x7a, 0x3f, 0xc6, 0xe3, 0xd4, 0xe3, 0x6e, 0xe2, 0xdb,
+       0x8b, 0xf5, 0x7f, 0x31, 0xd1, 0x41, 0x86, 0x4d, 0x8b, 0x82, 0x0f, 0x8e,
+       0xf1, 0xac, 0x68, 0xac, 0x94, 0xf4, 0x8b, 0xc5, 0x37, 0x16, 0x9f, 0x38,
+       0xfd, 0xe3, 0x61, 0xfc, 0xf1, 0x5f, 0xcd, 0x3f, 0x17, 0xe9, 0x1f, 0x03,
+       0xff, 0x7c, 0xcf, 0x75, 0x1e, 0x7d, 0x04, 0xfc, 0xf1, 0x3c, 0xe2, 0x7b,
+       0x5a, 0x25, 0xc7, 0xaf, 0x93, 0x1f, 0x2c, 0xfa, 0x07, 0x92, 0x48, 0x48,
+       0xd5, 0xb8, 0xdf, 0xd1, 0x04, 0xb6, 0xb7, 0xe8, 0x9d, 0xbd, 0x18, 0x36,
+       0x11, 0xce, 0x89, 0xc2, 0xaf, 0x39, 0x31, 0x5a, 0x23, 0xff, 0xe2, 0xc4,
+       0xf3, 0xff, 0xce, 0xcf, 0x61, 0x9f, 0xf7, 0x84, 0xc7, 0x89, 0x35, 0xe2,
+       0xfb, 0x89, 0xdd, 0x05, 0xf1, 0x6d, 0xa5, 0x29, 0x3e, 0xb3, 0xf8, 0xa9,
+       0xdd, 0x13, 0xfd, 0xb1, 0x2b, 0x2d, 0x0f, 0xc4, 0xca, 0x77, 0x3c, 0xec,
+       0x31, 0x5f, 0xc7, 0xe7, 0x21, 0xb5, 0x2f, 0x81, 0xfe, 0x4a, 0x68, 0x36,
+       0x0b, 0x6f, 0x30, 0x88, 0xcf, 0x8e, 0xf1, 0xe7, 0x9c, 0x4f, 0x7d, 0x61,
+       0x46, 0xf1, 0xd3, 0xcf, 0xec, 0x97, 0xed, 0x75, 0xc5, 0xf1, 0x7c, 0xa8,
+       0x45, 0x1a, 0x5a, 0xca, 0xc8, 0x6f, 0x65, 0x1a, 0xf2, 0xad, 0x2a, 0xe4,
+       0xc9, 0x8b, 0x59, 0xd1, 0x93, 0x88, 0xcf, 0xe6, 0xe9, 0x91, 0x12, 0x4e,
+       0x4f, 0x43, 0xe3, 0x7c, 0x00, 0xd7, 0x2f, 0x3a, 0x14, 0xf2, 0xd7, 0x3e,
+       0x2b, 0x3f, 0x35, 0x8f, 0x84, 0xff, 0x73, 0xf8, 0x88, 0x0e, 0xb9, 0x6a,
+       0x87, 0xe7, 0x07, 0xa4, 0xcb, 0x2d, 0x94, 0x6f, 0xa1, 0x90, 0x16, 0xdf,
+       0x20, 0x65, 0x90, 0x57, 0x02, 0x5f, 0x71, 0x16, 0x1e, 0x83, 0xeb, 0x83,
+       0xfd, 0xfc, 0x77, 0xc4, 0x63, 0x5e, 0x15, 0x93, 0x68, 0x39, 0x82, 0x8f,
+       0x9b, 0x3d, 0xe6, 0x1f, 0x5c, 0x9f, 0xcd, 0xfe, 0x50, 0xb4, 0xda, 0x14,
+       0x1f, 0x03, 0xde, 0x3c, 0x1a, 0xca, 0xc5, 0x6a, 0xc0, 0x5b, 0xf9, 0x70,
+       0xbc, 0x9d, 0x74, 0xf1, 0xf5, 0x3b, 0xe9, 0x2f, 0xa4, 0x26, 0x65, 0xa4,
+       0xff, 0x10, 0xc8, 0xd1, 0x0d, 0x52, 0xda, 0x39, 0xa9, 0xc0, 0x8b, 0xb5,
+       0x9e, 0x91, 0xe4, 0xb3, 0x45, 0xa7, 0x69, 0xe7, 0x0d, 0x21, 0x2d, 0x7d,
+       0xbd, 0xff, 0x8f, 0xca, 0x65, 0x4b, 0x5e, 0x5e, 0xee, 0x89, 0x4e, 0xc6,
+       0x7d, 0x70, 0x9b, 0x11, 0x21, 0xff, 0x4c, 0xda, 0x5f, 0xa7, 0x9c, 0x19,
+       0x6e, 0x07, 0xc9, 0x74, 0xce, 0x78, 0x06, 0xec, 0x1e, 0xec, 0x76, 0xb1,
+       0xf2, 0x75, 0xda, 0x59, 0x2f, 0x1e, 0x96, 0xb0, 0xa9, 0x67, 0x15, 0x2a,
+       0xaf, 0x3d, 0x4b, 0x87, 0x27, 0xec, 0x8b, 0x67, 0xb3, 0xa9, 0x34, 0xcf,
+       0xe6, 0x53, 0x59, 0x7f, 0x36, 0x97, 0xca, 0xe9, 0x67, 0x2f, 0xa1, 0x72,
+       0xc6, 0xd9, 0xd1, 0x54, 0x36, 0x9c, 0x05, 0x60, 0xc0, 0xc4, 0x69, 0x3c,
+       0x5b, 0x4a, 0xe5, 0xcc, 0xb3, 0x57, 0x50, 0x39, 0xeb, 0xec, 0x78, 0x2a,
+       0x67, 0x9f, 0xbd, 0x8a, 0xda, 0xcd, 0x39, 0x3b, 0x89, 0xca, 0xeb, 0xce,
+       0x7e, 0x81, 0xca, 0xeb, 0xcf, 0x4e, 0xa1, 0xd2, 0x69, 0xff, 0x18, 0xeb,
+       0x55, 0x92, 0xdf, 0x96, 0xfc, 0xb2, 0xe4, 0xbb, 0x53, 0x7e, 0x5b, 0xf2,
+       0xef, 0xff, 0x9a, 0xfc, 0x8e, 0x35, 0x5c, 0x94, 0xfd, 0x03, 0xfa, 0xef,
+       0xab, 0xda, 0x79, 0xe4, 0xf7, 0x48, 0xf2, 0x02, 0xf8, 0xfa, 0x3e, 0x2d,
+       0x5d, 0x4e, 0xa4, 0xf4, 0xf3, 0xfd, 0xda, 0x67, 0xe0, 0xeb, 0xe3, 0x82,
+       0x4f, 0x81, 0x7f, 0xdf, 0xc3, 0x38, 0x8c, 0x07, 0xbc, 0x38, 0x8a, 0x53,
+       0x85, 0x79, 0x9c, 0x2a, 0x60, 0x68, 0x06, 0xe6, 0x69, 0xec, 0xc3, 0x26,
+       0xb0, 0xa5, 0xfe, 0xd2, 0xc8, 0x49, 0x8c, 0x1b, 0x34, 0x2f, 0xf0, 0xe8,
+       0x31, 0x80, 0x7b, 0xa0, 0x54, 0x23, 0xf9, 0xb4, 0x2d, 0xa8, 0xd1, 0xb9,
+       0xdb, 0x66, 0x49, 0x1f, 0xcd, 0xe5, 0x41, 0x32, 0x81, 0xf4, 0xb7, 0x33,
+       0xa4, 0xd1, 0x78, 0xdb, 0xfe, 0xa8, 0x78, 0x31, 0x7f, 0xe1, 0xa5, 0x51,
+       0x05, 0x01, 0x9c, 0xa7, 0xdb, 0x2f, 0xeb, 0xd8, 0xfe, 0x5b, 0xb9, 0xc9,
+       0x7d, 0xb7, 0xe0, 0x39, 0xfe, 0x14, 0x16, 0x3e, 0x04, 0xe3, 0xad, 0xd8,
+       0xb3, 0xc7, 0x93, 0xee, 0x87, 0xef, 0x47, 0xe3, 0x00, 0xe0, 0x0b, 0xc4,
+       0x9e, 0x66, 0x0c, 0xf8, 0x7a, 0xe3, 0xa8, 0xdf, 0x2d, 0xc5, 0xf9, 0x7c,
+       0x53, 0x19, 0xc5, 0x63, 0xa0, 0x34, 0x33, 0xe5, 0x8b, 0x7d, 0xd3, 0x2d,
+       0xce, 0xa7, 0xd5, 0xa1, 0x10, 0xe2, 0x69, 0xab, 0x4f, 0x26, 0x7d, 0xd0,
+       0xad, 0x7b, 0x44, 0x1e, 0x6a, 0x72, 0xa0, 0x05, 0xfd, 0xdc, 0x3a, 0x99,
+       0x6d, 0x83, 0x79, 0x37, 0x8c, 0x7e, 0x67, 0x0b, 0x82, 0xad, 0x8e, 0x2b,
+       0xdb, 0x51, 0x06, 0xf5, 0x9d, 0x75, 0x65, 0x5e, 0xdc, 0xa4, 0xa7, 0x5f,
+       0xf9, 0x20, 0x44, 0xf6, 0x04, 0xbc, 0x43, 0x50, 0xa0, 0x4c, 0x88, 0xd2,
+       0xcc, 0x81, 0xfd, 0xe9, 0xf4, 0x86, 0x8d, 0xf3, 0x9d, 0xb7, 0x29, 0xc6,
+       0xd0, 0x3a, 0x24, 0x56, 0xec, 0xef, 0xae, 0x1e, 0xb9, 0xdd, 0x26, 0xff,
+       0x40, 0x08, 0xe9, 0xa3, 0x63, 0xd2, 0xe4, 0xca, 0x5b, 0x60, 0xfe, 0xde,
+       0x49, 0x05, 0xa3, 0x71, 0xfe, 0xed, 0x35, 0x47, 0x6d, 0xf8, 0x50, 0x74,
+       0x7b, 0x3c, 0x45, 0xc1, 0x80, 0x23, 0xfa, 0xe1, 0x75, 0x49, 0x8a, 0xab,
+       0x6d, 0x90, 0x8d, 0x1d, 0x65, 0xb0, 0xbe, 0x80, 0xc8, 0xb7, 0x06, 0x30,
+       0x2b, 0x23, 0x69, 0x79, 0x07, 0x16, 0x1c, 0x4a, 0x18, 0xd6, 0xc1, 0xe1,
+       0x4a, 0x28, 0x7c, 0x3d, 0xac, 0x00, 0x9e, 0xe7, 0xd6, 0x25, 0x62, 0x49,
+       0xbe, 0x5e, 0x13, 0xe3, 0xae, 0x3e, 0x5f, 0x32, 0x84, 0xfe, 0xa2, 0x52,
+       0x77, 0x9a, 0xe2, 0x6d, 0x9d, 0xfe, 0xe4, 0x22, 0xaa, 0x3b, 0xe0, 0xb0,
+       0xc6, 0xff, 0xad, 0x66, 0xe5, 0x05, 0x70, 0xbe, 0xf1, 0x09, 0xbe, 0x69,
+       0x9e, 0xf4, 0xed, 0x45, 0x94, 0x47, 0x5e, 0xa5, 0xd1, 0xbe, 0x75, 0xbb,
+       0x86, 0x16, 0x60, 0x3d, 0xb6, 0xd6, 0xc5, 0x1e, 0xcf, 0x10, 0xbf, 0xd9,
+       0x20, 0xf8, 0x79, 0x5b, 0xe5, 0xf9, 0xe3, 0x32, 0xaa, 0xcf, 0x0e, 0x47,
+       0xb7, 0xd7, 0xee, 0x2f, 0x5a, 0xf0, 0xbc, 0x2f, 0x4a, 0x27, 0x1c, 0xcd,
+       0xae, 0xa1, 0x51, 0x99, 0xf6, 0xef, 0xd3, 0xce, 0x7f, 0xa1, 0x75, 0x7f,
+       0xde, 0xf3, 0x75, 0x8e, 0x90, 0x3f, 0x70, 0xb9, 0xdb, 0xbe, 0x0f, 0x01,
+       0x21, 0xcf, 0x9b, 0xa7, 0x7c, 0x3b, 0x84, 0xe7, 0xe2, 0x16, 0x3c, 0x9d,
+       0x12, 0xec, 0x43, 0xcd, 0xe7, 0xbf, 0x0f, 0xcd, 0x53, 0xb8, 0xbc, 0xfe,
+       0xbc, 0xd7, 0xfb, 0x3f, 0x6d, 0xdc, 0xdf, 0x6b, 0x3c, 0xae, 0x02, 0x7c,
+       0x3a, 0xbb, 0x1c, 0xe3, 0x8c, 0x63, 0x26, 0x87, 0x30, 0x5e, 0xeb, 0xb3,
+       0xe2, 0xd1, 0xe1, 0x38, 0xe5, 0x27, 0x05, 0x30, 0x1e, 0x4d, 0xbd, 0x0c,
+       0xd2, 0x43, 0xaa, 0xce, 0xc7, 0x50, 0x54, 0x96, 0x40, 0x3e, 0x94, 0xb3,
+       0x3f, 0x4c, 0xe0, 0x3e, 0x29, 0xd5, 0x9a, 0xa1, 0x90, 0x9c, 0xcd, 0xbc,
+       0xef, 0x4a, 0x78, 0x13, 0xe5, 0xb5, 0x39, 0xf9, 0xd3, 0x82, 0x9b, 0xfe,
+       0x26, 0x0b, 0xd3, 0x81, 0xce, 0x0f, 0xbd, 0x56, 0x7c, 0xda, 0x50, 0x27,
+       0xf3, 0xfb, 0x12, 0x18, 0xff, 0x55, 0x98, 0x75, 0x3e, 0xcb, 0xe3, 0xd3,
+       0x56, 0x7f, 0xb5, 0x42, 0xa6, 0x78, 0x34, 0x05, 0xb2, 0xd3, 0xc6, 0x51,
+       0x41, 0x0f, 0xe3, 0x39, 0x8e, 0x82, 0x71, 0xea, 0xbc, 0xe1, 0xf3, 0x7f,
+       0x37, 0x45, 0x8f, 0xf6, 0xf9, 0x8b, 0x78, 0x7c, 0x5c, 0x51, 0xb9, 0x1f,
+       0xf8, 0x9e, 0xc4, 0xf1, 0x11, 0x7b, 0x55, 0xa1, 0x7c, 0xcf, 0xae, 0xe7,
+       0xb9, 0x7c, 0x63, 0xc7, 0x19, 0xc9, 0xef, 0xae, 0x5a, 0x83, 0xce, 0x55,
+       0x76, 0xc0, 0xff, 0xe8, 0x3f, 0xc4, 0x6a, 0x7d, 0x71, 0xa4, 0x5b, 0xc5,
+       0x91, 0x8f, 0x77, 0xa6, 0x72, 0x7a, 0x08, 0xe5, 0xa8, 0x15, 0x17, 0xa7,
+       0xf9, 0xf8, 0xf9, 0x00, 0xc5, 0xb9, 0x31, 0x4f, 0x91, 0xe2, 0xe6, 0x06,
+       0xab, 0xc0, 0xf7, 0xdd, 0x02, 0x34, 0x6b, 0x1c, 0xd5, 0x8a, 0xcb, 0x57,
+       0xae, 0x99, 0x84, 0xed, 0xfc, 0x06, 0xf3, 0x3c, 0x07, 0xeb, 0xf3, 0xd7,
+       0xb1, 0xc4, 0x25, 0x00, 0x6f, 0xd0, 0xdd, 0xba, 0xf5, 0xf2, 0xd2, 0x0c,
+       0xf1, 0xf0, 0xca, 0x35, 0xdf, 0x78, 0x12, 0xe6, 0xdd, 0xfd, 0xd4, 0xf4,
+       0x5f, 0x3d, 0x09, 0xf5, 0x5d, 0x72, 0xf8, 0xd5, 0x3a, 0x68, 0x97, 0xff,
+       0xe5, 0x3a, 0xc2, 0xab, 0x33, 0x1e, 0xbe, 0xad, 0x52, 0x36, 0x75, 0x94,
+       0x0f, 0x3e, 0xdf, 0x21, 0xdc, 0x57, 0xb0, 0xa1, 0x89, 0x2e, 0x6e, 0xed,
+       0x91, 0x62, 0xf8, 0x3c, 0xdb, 0xe7, 0x3b, 0xc8, 0xf7, 0xbb, 0x35, 0xa4,
+       0x20, 0x5e, 0x40, 0x4f, 0x22, 0x5e, 0xbc, 0xce, 0xbc, 0xc8, 0x74, 0x7c,
+       0x97, 0x21, 0x1c, 0x3b, 0x07, 0xe6, 0xc1, 0xbf, 0xbd, 0x5b, 0xe7, 0x2d,
+       0xc3, 0x79, 0x11, 0x6e, 0xcc, 0xaf, 0x5c, 0xd1, 0x5b, 0xaf, 0xa1, 0x9e,
+       0x09, 0x2e, 0xb1, 0x9f, 0x5f, 0xf8, 0x9b, 0xec, 0x75, 0x6f, 0x95, 0x1d,
+       0xce, 0xad, 0x62, 0xff, 0x2e, 0x44, 0xff, 0xce, 0x3c, 0xc4, 0x1e, 0x73,
+       0xde, 0x22, 0xa4, 0xdb, 0x33, 0x41, 0x8d, 0xa1, 0xbc, 0xd9, 0xb8, 0xf6,
+       0xea, 0x1b, 0x49, 0xee, 0x6f, 0x57, 0xd8, 0xb8, 0xd2, 0x0c, 0xf4, 0xeb,
+       0x58, 0x57, 0xa7, 0xe6, 0x22, 0xfd, 0xdf, 0x6d, 0xd4, 0xef, 0xad, 0x40,
+       0xbd, 0xd1, 0xa0, 0x51, 0x5e, 0x4f, 0x77, 0xdc, 0x1b, 0xc7, 0x14, 0xef,
+       0xed, 0x75, 0xa9, 0x73, 0x13, 0x9b, 0xfd, 0x6e, 0x68, 0xfc, 0x1c, 0xab,
+       0x46, 0x4e, 0xb8, 0x33, 0xd9, 0xf1, 0xe2, 0x7c, 0x2c, 0x20, 0x9e, 0x31,
+       0xc7, 0x39, 0x58, 0xf7, 0x6c, 0x99, 0xec, 0x9a, 0xee, 0x1e, 0x3e, 0x8f,
+       0x35, 0x5e, 0x77, 0xdd, 0x5b, 0x1e, 0x94, 0x13, 0x23, 0x8d, 0xfb, 0xf4,
+       0x18, 0xf3, 0x88, 0x1b, 0xed, 0xa9, 0x68, 0xde, 0x45, 0xdd, 0xbb, 0xb8,
+       0x6f, 0xa3, 0x8b, 0xd3, 0xf5, 0x14, 0x2d, 0x2e, 0x95, 0xa2, 0x3d, 0xaa,
+       0x2f, 0x5c, 0x04, 0xf5, 0xcd, 0xe3, 0x64, 0xb2, 0x87, 0x98, 0xf0, 0xff,
+       0xba, 0xaf, 0xe5, 0xe7, 0x89, 0x0f, 0x6b, 0x86, 0xed, 0x7e, 0xc5, 0xa6,
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+       0xc3, 0xef, 0x79, 0x99, 0x83, 0x95, 0x05, 0x5c, 0xcd, 0x21, 0xde, 0xff,
+       0xab, 0xcf, 0x2b, 0x9c, 0x74, 0xa1, 0x5b, 0xfb, 0xef, 0xd8, 0x6f, 0x1f,
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+       0x9b, 0xa9, 0xf2, 0x7a, 0x6c, 0xbc, 0x68, 0xef, 0xe2, 0x24, 0xc4, 0x06,
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+       0x47, 0xec, 0x72, 0x7b, 0x9c, 0xe3, 0x5e, 0x74, 0xc0, 0x91, 0xf7, 0x92,
+       0xeb, 0x15, 0xf9, 0xee, 0x96, 0xdc, 0x2e, 0xe2, 0x9b, 0x3a, 0x41, 0x1d,
+       0x94, 0x33, 0xf9, 0xe5, 0x29, 0xfd, 0xea, 0x80, 0x0f, 0x65, 0x58, 0x75,
+       0xaa, 0x7f, 0xc0, 0xaa, 0x7f, 0x46, 0xf8, 0x80, 0x10, 0x88, 0x9e, 0x2d,
+       0x78, 0xf0, 0x2a, 0x25, 0xca, 0xdd, 0x3d, 0x2e, 0xfd, 0x2b, 0x4f, 0xa1,
+       0x7e, 0xae, 0xd7, 0x78, 0x1e, 0x99, 0xb8, 0x2f, 0x97, 0x2d, 0xf0, 0xee,
+       0x43, 0x87, 0x19, 0xda, 0x0d, 0x4c, 0x79, 0xc5, 0xc4, 0x7d, 0xdd, 0x11,
+       0xe6, 0xdf, 0xa5, 0x39, 0x33, 0x75, 0x1e, 0xf9, 0xa1, 0xd9, 0x75, 0xd6,
+       0x7d, 0x3a, 0x7e, 0x5f, 0x19, 0xca, 0x18, 0xc6, 0xe9, 0xb2, 0xc5, 0xfc,
+       0xd6, 0xbd, 0xba, 0x6c, 0x66, 0xbc, 0x59, 0x0e, 0xf4, 0x90, 0x6d, 0x26,
+       0xe9, 0x5e, 0x9d, 0x6e, 0x7d, 0x57, 0xc1, 0x64, 0x09, 0xcc, 0xc3, 0xd1,
+       0x7d, 0x32, 0xe5, 0xd1, 0xe9, 0xbe, 0x08, 0xc9, 0xa7, 0x9e, 0x05, 0x1e,
+       0x1d, 0xbf, 0xf3, 0xa1, 0x89, 0x7b, 0x7a, 0x2e, 0x71, 0x7f, 0x3c, 0xdb,
+       0x3c, 0x4d, 0xf7, 0xeb, 0xb2, 0x87, 0xad, 0x8f, 0xdf, 0xaf, 0xb3, 0xe0,
+       0xce, 0xce, 0xaa, 0x7a, 0xb3, 0xdc, 0xb0, 0xcd, 0xb3, 0x1e, 0xe3, 0xdb,
+       0xb0, 0xf6, 0xd1, 0x19, 0xef, 0xd7, 0xd5, 0x71, 0x3f, 0x29, 0xdb, 0xe4,
+       0x71, 0x88, 0xb4, 0xf1, 0xe9, 0x7e, 0xdd, 0x8e, 0xa9, 0x65, 0xb6, 0xfb,
+       0x75, 0x34, 0x0f, 0xfa, 0x71, 0x82, 0xfe, 0xac, 0x7b, 0x76, 0x4e, 0xb8,
+       0xce, 0xf5, 0xab, 0xc9, 0x6c, 0xa7, 0x4d, 0x08, 0xdb, 0xed, 0x88, 0x0b,
+       0xdd, 0xaf, 0x73, 0x85, 0xec, 0xed, 0x77, 0x5c, 0x20, 0x3f, 0xeb, 0x13,
+       0xdf, 0xaf, 0x13, 0x78, 0x18, 0xd6, 0xce, 0x61, 0x0f, 0xba, 0x2c, 0x3b,
+       0x74, 0x94, 0xcc, 0x70, 0xff, 0xce, 0x34, 0xc8, 0xf4, 0x1d, 0x91, 0xdc,
+       0x8f, 0x92, 0x91, 0x19, 0x12, 0xc5, 0x25, 0x48, 0xdf, 0x5b, 0x76, 0x5e,
+       0x1e, 0x1f, 0xea, 0xbf, 0x9d, 0x9d, 0x97, 0x67, 0xe5, 0xf5, 0x3b, 0xec,
+       0x3c, 0xcb, 0x7e, 0xcb, 0x9d, 0x6d, 0xc7, 0xb7, 0xd3, 0xee, 0x73, 0x57,
+       0x45, 0xa8, 0xcf, 0xc5, 0xda, 0x79, 0xbb, 0xf0, 0x1f, 0x40, 0x2f, 0x0f,
+       0x79, 0x1d, 0x76, 0x5e, 0x53, 0x66, 0xfa, 0x70, 0xca, 0x8b, 0x7c, 0x36,
+       0xb8, 0xfb, 0x4a, 0x18, 0xe7, 0x68, 0xed, 0x8f, 0x14, 0xcc, 0x57, 0xdb,
+       0x95, 0xcb, 0xbf, 0x7f, 0xc4, 0x86, 0xf9, 0x07, 0x6f, 0xcd, 0xa0, 0x7d,
+       0xf1, 0xf1, 0xef, 0x1d, 0xed, 0x9a, 0xd2, 0xaf, 0xe2, 0xf7, 0x6f, 0x7e,
+       0xb7, 0x94, 0x91, 0x9d, 0x64, 0xc5, 0x11, 0xdc, 0x02, 0xe6, 0x5d, 0x45,
+       0xf2, 0x7a, 0x0a, 0xbb, 0x77, 0x3d, 0x44, 0xf8, 0x09, 0x0a, 0x3c, 0x34,
+       0xe1, 0x07, 0xc8, 0x6a, 0x08, 0x57, 0xf1, 0x71, 0xc4, 0x67, 0xa6, 0x17,
+       0xf3, 0x16, 0xf2, 0x9b, 0x18, 0x35, 0x2a, 0xac, 0x08, 0xd3, 0xbe, 0xe3,
+       0x67, 0x09, 0x64, 0xba, 0xb4, 0x15, 0x53, 0x51, 0x8f, 0xd7, 0x23, 0x56,
+       0xd2, 0xf0, 0x34, 0xc3, 0x63, 0xff, 0x4e, 0x40, 0xa3, 0x9e, 0xef, 0xd8,
+       0x47, 0xfb, 0x3e, 0x9f, 0x3b, 0x07, 0x7f, 0x90, 0x7f, 0x4f, 0x61, 0x8e,
+       0x61, 0xdf, 0x77, 0xcb, 0x4f, 0x42, 0x73, 0x16, 0xe7, 0xbb, 0xbe, 0xd2,
+       0x4e, 0x07, 0x27, 0xa4, 0xc8, 0xa0, 0x02, 0x5d, 0x9e, 0xce, 0x2a, 0x15,
+       0xf6, 0xcf, 0xa0, 0x8e, 0xfa, 0xb2, 0x7b, 0xad, 0x8b, 0xec, 0xc6, 0x87,
+       0x96, 0x94, 0x6d, 0xbd, 0x12, 0xfd, 0xd5, 0xa0, 0xac, 0xf3, 0xe3, 0xc8,
+       0xa1, 0x71, 0x68, 0x1f, 0x35, 0x1f, 0x35, 0xbd, 0x68, 0xe7, 0x6d, 0x8f,
+       0x4c, 0xf7, 0x8e, 0x83, 0xf7, 0x0f, 0x75, 0x28, 0x61, 0x34, 0x0f, 0x9f,
+       0x5a, 0xb2, 0xe6, 0x55, 0xac, 0xc7, 0x76, 0xbb, 0xc8, 0x0e, 0x7a, 0xaa,
+       0x6f, 0x5e, 0xc1, 0x8a, 0x34, 0xbe, 0xdb, 0xbc, 0x7b, 0xc1, 0xc2, 0xc5,
+       0xf8, 0xbe, 0xc3, 0x45, 0xfa, 0x7d, 0xc5, 0x9e, 0xfb, 0x06, 0x4a, 0x83,
+       0xd8, 0xdf, 0x55, 0x9b, 0xfe, 0xbd, 0xa9, 0x96, 0x8d, 0xf7, 0xe9, 0xe8,
+       0xb7, 0xbd, 0x51, 0xeb, 0xcd, 0x68, 0xc7, 0x5c, 0x9d, 0xc5, 0xed, 0x92,
+       0x8d, 0x5a, 0x92, 0xe2, 0x4f, 0x1b, 0xe7, 0x69, 0x0c, 0x5d, 0xae, 0x8d,
+       0x25, 0xf5, 0xa3, 0x57, 0xa0, 0xfd, 0x70, 0x8d, 0x96, 0xf1, 0x3e, 0xf9,
+       0x5d, 0x59, 0x6e, 0x7e, 0x9f, 0xcf, 0xd5, 0x2a, 0xa1, 0x7c, 0x2f, 0x8c,
+       0x66, 0xbe, 0x17, 0x60, 0xb5, 0x1b, 0x5b, 0xf3, 0x5b, 0x3a, 0xc7, 0x08,
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+       0xf6, 0x55, 0x97, 0x52, 0xf4, 0x94, 0x27, 0xe8, 0x69, 0x63, 0xd1, 0xbd,
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+       0x30, 0x84, 0xf3, 0xf6, 0x8e, 0x8a, 0x84, 0xf2, 0x28, 0x3f, 0x65, 0x0c,
+       0xd9, 0x03, 0x1b, 0x47, 0x6d, 0x5a, 0x8c, 0xf1, 0xa7, 0x8e, 0xe5, 0x1a,
+       0x4b, 0xb7, 0x93, 0x86, 0xcd, 0x17, 0xb4, 0xdb, 0xd7, 0x56, 0x9c, 0x51,
+       0x6d, 0xe0, 0xf9, 0x23, 0x1d, 0x32, 0xf7, 0x2f, 0x73, 0xc5, 0xf9, 0x34,
+       0xf0, 0x55, 0x25, 0xe2, 0x2d, 0x7d, 0x9d, 0x08, 0xa7, 0x6a, 0xf2, 0xfc,
+       0x11, 0x5c, 0xaf, 0xc2, 0xd7, 0x4b, 0xdf, 0x37, 0xcd, 0x6d, 0x00, 0xff,
+       0xb0, 0x8a, 0xaf, 0x1f, 0xfd, 0x57, 0xdd, 0xa7, 0x8f, 0x46, 0xf9, 0xa1,
+       0x36, 0xf0, 0xfc, 0x91, 0xcd, 0x7e, 0x7d, 0x31, 0xfa, 0x8d, 0x4e, 0x38,
+       0xac, 0xf1, 0xaf, 0xcd, 0x96, 0x6c, 0xfe, 0x91, 0x6e, 0xe5, 0x2d, 0xd4,
+       0xaf, 0xe1, 0xe7, 0x88, 0x45, 0x3c, 0x6f, 0xa1, 0xd7, 0x75, 0xfe, 0xbc,
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+       0x18, 0x29, 0x5f, 0xe0, 0xd3, 0xce, 0x7f, 0xa1, 0x75, 0x7f, 0xde, 0xf3,
+       0x8d, 0x94, 0x47, 0xb0, 0x26, 0x5b, 0xb2, 0xdd, 0xaf, 0xc8, 0xb5, 0xf2,
+       0x59, 0x1a, 0xd7, 0x84, 0x50, 0x4e, 0x58, 0xf0, 0x6c, 0xbe, 0x40, 0xfe,
+       0xc8, 0xa7, 0x85, 0xab, 0xb9, 0x91, 0xb7, 0xff, 0xbc, 0xd7, 0xfb, 0x3f,
+       0x6d, 0xdc, 0xfa, 0x6c, 0xae, 0x1f, 0x81, 0x4f, 0x07, 0xf0, 0x1e, 0x65,
+       0xc7, 0xc4, 0x99, 0x21, 0x94, 0x43, 0xa9, 0x78, 0xcc, 0xd0, 0x40, 0x39,
+       0xda, 0x73, 0xe2, 0x3e, 0xa3, 0x95, 0x3f, 0xe2, 0xd2, 0xf9, 0x3f, 0x55,
+       0x95, 0x7f, 0xe7, 0x4e, 0xce, 0x2e, 0xa2, 0xef, 0x2c, 0xab, 0xd3, 0x79,
+       0xfe, 0x08, 0xfd, 0x65, 0xc8, 0x03, 0xd9, 0xc4, 0xd8, 0x6c, 0xf4, 0x77,
+       0x54, 0x11, 0xbf, 0x71, 0xf2, 0xe9, 0x85, 0xe0, 0x77, 0xe6, 0x8d, 0xdc,
+       0xec, 0x13, 0x7e, 0x63, 0xd4, 0x31, 0x9f, 0xc8, 0x13, 0x61, 0x8e, 0xbc,
+       0x13, 0x35, 0xc4, 0xf3, 0x4b, 0xac, 0x7c, 0x92, 0x2e, 0x09, 0xd6, 0x17,
+       0x4c, 0xe5, 0x83, 0x8c, 0x38, 0xaf, 0x03, 0x6f, 0xe3, 0x85, 0xdc, 0x7f,
+       0xcf, 0xd1, 0x7f, 0xd8, 0xba, 0xc3, 0xfc, 0x7e, 0xa5, 0x95, 0x7f, 0x32,
+       0x2c, 0x8f, 0x64, 0xaa, 0xbc, 0x1f, 0xb7, 0x60, 0x58, 0x1e, 0x89, 0xc8,
+       0x47, 0xe9, 0xc9, 0x35, 0xe2, 0x3c, 0x4f, 0x9c, 0xe7, 0x95, 0xa0, 0xda,
+       0xc4, 0x78, 0xde, 0xb0, 0x3c, 0x92, 0xa9, 0xd3, 0x43, 0xf8, 0x4d, 0xc9,
+       0x69, 0x25, 0xa2, 0xdf, 0x0d, 0x8c, 0xbe, 0xbf, 0xdb, 0xe3, 0xe5, 0xf5,
+       0xde, 0x39, 0x2c, 0x8e, 0xdf, 0x3b, 0xeb, 0xc5, 0x3a, 0xf2, 0x53, 0x2d,
+       0xa3, 0xbc, 0x96, 0x61, 0xf9, 0x25, 0x53, 0xd7, 0x10, 0x9e, 0x34, 0x16,
+       0x59, 0xc6, 0xcf, 0x77, 0xf8, 0x79, 0xbf, 0x85, 0x07, 0x67, 0x7e, 0xc9,
+       0x05, 0xe9, 0xed, 0x02, 0x79, 0x24, 0x41, 0x9f, 0xf5, 0x3d, 0x8a, 0x08,
+       0xcd, 0xd3, 0xe3, 0x0f, 0xff, 0xa4, 0x8e, 0xe0, 0x93, 0xe9, 0x3c, 0xbe,
+       0xe0, 0x4b, 0xc7, 0xc3, 0xe9, 0xe3, 0x5f, 0xe2, 0xe3, 0x72, 0xb2, 0x47,
+       0xe4, 0xe1, 0xf5, 0xe4, 0xda, 0xf3, 0xf1, 0xee, 0x13, 0xfb, 0x52, 0x21,
+       0xda, 0x39, 0xf7, 0x57, 0x2f, 0xe2, 0x74, 0xdd, 0x55, 0xaf, 0x53, 0xdc,
+       0xdd, 0xdd, 0xc0, 0xe3, 0x95, 0xc3, 0xbe, 0x03, 0x51, 0x63, 0xf7, 0x07,
+       0x9c, 0xf1, 0xbc, 0x13, 0x42, 0x5e, 0x5f, 0x68, 0xfd, 0xce, 0xb8, 0xde,
+       0xb6, 0x11, 0xee, 0x9b, 0x2d, 0xf0, 0xf1, 0x3c, 0xae, 0x87, 0x96, 0x1c,
+       0xa2, 0xbc, 0xd8, 0x33, 0xab, 0x40, 0xcf, 0x02, 0xbe, 0x1e, 0xc6, 0x7c,
+       0x96, 0x9a, 0x8b, 0xcf, 0x67, 0x79, 0x3d, 0x8b, 0xe7, 0xb3, 0xf4, 0x1a,
+       0xf5, 0x0b, 0x2f, 0x45, 0x3d, 0x16, 0xd5, 0x18, 0xca, 0xd3, 0x5e, 0xcc,
+       0x67, 0x81, 0xf7, 0x1b, 0x1a, 0x46, 0xc8, 0x67, 0x11, 0xf1, 0x44, 0x2b,
+       0x3e, 0x3a, 0x52, 0x3e, 0x4b, 0xee, 0xb9, 0xf3, 0x78, 0x7b, 0x3e, 0x4b,
+       0xef, 0xad, 0x3c, 0x9f, 0xa5, 0xb7, 0x87, 0xcf, 0x63, 0x8d, 0xd7, 0xdb,
+       0x50, 0x4d, 0x76, 0xd6, 0x48, 0xe3, 0x3e, 0x3d, 0xc6, 0x94, 0x7d, 0xb8,
+       0xff, 0x15, 0x17, 0x77, 0x7e, 0x3a, 0xad, 0x24, 0xf2, 0x67, 0x98, 0xbf,
+       0xd2, 0x53, 0xaa, 0xe9, 0x0f, 0x1a, 0x48, 0x2f, 0x9c, 0x9e, 0xbb, 0x1a,
+       0x35, 0xa2, 0xef, 0x2e, 0x17, 0xf7, 0x63, 0x63, 0xa3, 0xb9, 0xdf, 0xcc,
+       0xd4, 0x78, 0x68, 0x21, 0xb4, 0xd9, 0xe2, 0x4f, 0x2c, 0xa2, 0x78, 0xb2,
+       0xc8, 0xcb, 0xe8, 0x15, 0xf7, 0xe7, 0xff, 0x3e, 0xcb, 0xb0, 0xd9, 0xc7,
+       0x9d, 0x8d, 0xdf, 0x0d, 0xa1, 0x5d, 0x0f, 0x74, 0xf8, 0xb2, 0xce, 0xf9,
+       0x84, 0xc6, 0xc9, 0x57, 0x4b, 0xd7, 0x83, 0x0d, 0xc8, 0xdc, 0x7a, 0x8b,
+       0x89, 0x3e, 0xe5, 0x40, 0x36, 0x8f, 0x23, 0xb8, 0x42, 0xc7, 0x06, 0xea,
+       0xd2, 0xe8, 0x74, 0x8b, 0xd0, 0x77, 0x88, 0x1f, 0x19, 0xf0, 0x93, 0x2b,
+       0x9d, 0xc3, 0x57, 0x54, 0x2e, 0xa0, 0xe8, 0x3e, 0xfd, 0xad, 0x11, 0xf4,
+       0xf9, 0x46, 0x36, 0x9f, 0xdf, 0xa2, 0x43, 0xa6, 0x4e, 0x0a, 0xf3, 0xf3,
+       0x3f, 0x56, 0x81, 0x72, 0xc4, 0xf2, 0x5f, 0x87, 0xb5, 0xf3, 0xf0, 0x76,
+       0xc3, 0xe4, 0x8f, 0x43, 0x8e, 0xf4, 0x60, 0x7e, 0x1b, 0x56, 0x2c, 0x79,
+       0x72, 0x83, 0x25, 0x4f, 0xec, 0x74, 0x69, 0xc9, 0x0f, 0xe6, 0x90, 0x33,
+       0xe7, 0xe4, 0xc9, 0x1c, 0x6e, 0xa7, 0x9f, 0x93, 0x27, 0x20, 0x3f, 0xf0,
+       0x53, 0x67, 0x4e, 0x39, 0xd4, 0xeb, 0xe5, 0xfa, 0xc2, 0x82, 0xc7, 0x8d,
+       0x82, 0x19, 0xe4, 0xc8, 0x7b, 0xae, 0xb0, 0x2d, 0x4e, 0xe3, 0x94, 0x3b,
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+       0x77, 0x96, 0xd0, 0x7e, 0xbc, 0x68, 0x1f, 0x93, 0xce, 0xdb, 0xee, 0x34,
+       0xb5, 0x1b, 0x29, 0xde, 0x34, 0x10, 0xe0, 0xf1, 0xa6, 0x80, 0xb0, 0x57,
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+       0x73, 0x71, 0xdb, 0x9f, 0xdc, 0xe9, 0xf2, 0xfa, 0xe6, 0x40, 0xa9, 0xb8,
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+       0x79, 0x74, 0xce, 0x2b, 0x12, 0xe2, 0xb3, 0xe8, 0x39, 0x9e, 0xa7, 0x6d,
+       0xd9, 0xcb, 0xd3, 0x6b, 0x12, 0x21, 0x7c, 0xde, 0xf5, 0x6a, 0xf4, 0x32,
+       0xe2, 0xcf, 0x11, 0xec, 0x4f, 0xcb, 0xde, 0x74, 0xae, 0xe7, 0x92, 0xfa,
+       0x07, 0x49, 0x1e, 0x8c, 0x8d, 0x32, 0x2f, 0x9e, 0xaf, 0xf9, 0x57, 0xab,
+       0x94, 0xc7, 0x5a, 0x12, 0x05, 0xb8, 0xaa, 0x50, 0x2e, 0x00, 0x49, 0x17,
+       0x02, 0xfc, 0x35, 0xb1, 0xf5, 0x48, 0x37, 0x46, 0x94, 0xd7, 0x8d, 0xd5,
+       0xa2, 0x5c, 0x05, 0xe5, 0xd5, 0x60, 0xdf, 0xae, 0x1b, 0x28, 0xff, 0xa5,
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+       0xb9, 0x01, 0xed, 0x95, 0x56, 0xb0, 0x46, 0x0c, 0xb4, 0x17, 0x4f, 0x79,
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+       0xc0, 0xbb, 0x00, 0xe7, 0x2d, 0x28, 0x47, 0x80, 0x8e, 0xfd, 0x45, 0x5c,
+       0x9e, 0x83, 0x1c, 0xe6, 0x72, 0xce, 0xd2, 0x27, 0x77, 0x73, 0xbd, 0x6f,
+       0xc9, 0xcf, 0x0a, 0x31, 0xce, 0x2d, 0x28, 0x6f, 0xa1, 0x5f, 0x77, 0xed,
+       0x13, 0xb9, 0x37, 0xa0, 0x5c, 0x11, 0x72, 0xd6, 0x1f, 0x32, 0x66, 0xe2,
+       0xf9, 0x5c, 0x85, 0x90, 0xaf, 0x4c, 0x8d, 0x49, 0x38, 0xdf, 0x81, 0x29,
+       0xfc, 0x7b, 0x95, 0x01, 0x87, 0x3c, 0xad, 0x68, 0xe5, 0xe3, 0x74, 0x85,
+       0x18, 0xd1, 0x13, 0xe8, 0xa1, 0x83, 0x48, 0x37, 0x07, 0x8a, 0x12, 0x74,
+       0x4f, 0xfc, 0x40, 0xeb, 0x51, 0x29, 0xfd, 0x9e, 0xa9, 0xa5, 0xef, 0x02,
+       0xad, 0x49, 0x86, 0xfb, 0x3f, 0xae, 0x8e, 0xcb, 0xc1, 0x71, 0x42, 0xae,
+       0x7e, 0xc7, 0x6f, 0x70, 0xfa, 0xf4, 0x70, 0xb9, 0x7a, 0x4e, 0xef, 0x09,
+       0x79, 0xbb, 0xd5, 0x3c, 0xca, 0xc4, 0x77, 0x61, 0x33, 0xe6, 0x61, 0xfd,
+       0xbd, 0xd0, 0xe7, 0x3d, 0x15, 0x87, 0xc8, 0x2f, 0xd8, 0x76, 0xeb, 0x29,
+       0xc2, 0xa7, 0x15, 0x0f, 0x0d, 0x89, 0x78, 0x68, 0x77, 0xd5, 0x5b, 0xf4,
+       0x7e, 0x7b, 0x94, 0xdf, 0x03, 0xd8, 0x65, 0x4e, 0x9f, 0x43, 0xf0, 0x47,
+       0x96, 0x6b, 0x94, 0x7f, 0x5a, 0x73, 0x74, 0x4e, 0x19, 0xfa, 0x1b, 0x4d,
+       0xcb, 0x35, 0xb4, 0xeb, 0x4e, 0x06, 0x0a, 0xac, 0xf3, 0x2f, 0xef, 0x42,
+       0xb4, 0x27, 0x5b, 0x57, 0x91, 0xfd, 0xeb, 0x13, 0xfb, 0xf8, 0x50, 0x98,
+       0x09, 0xbf, 0x53, 0x23, 0x3f, 0xeb, 0xbe, 0xa5, 0xdf, 0x1e, 0xc0, 0xfe,
+       0x21, 0xf0, 0x8b, 0x24, 0x03, 0x1b, 0xf5, 0x79, 0xdc, 0x48, 0xe7, 0xf8,
+       0x3d, 0x05, 0xc4, 0x77, 0x74, 0x90, 0x3a, 0xfb, 0x6a, 0x0c, 0xfa, 0x0e,
+       0x84, 0x73, 0x1d, 0xdf, 0x0b, 0xf0, 0xef, 0xd2, 0xfa, 0xa3, 0xc9, 0x81,
+       0x71, 0xb4, 0xaf, 0x32, 0x5d, 0xe9, 0xf1, 0xd5, 0x30, 0xf2, 0x3b, 0x97,
+       0x83, 0x5f, 0x87, 0xc3, 0xee, 0x56, 0xc3, 0xde, 0x09, 0xf0, 0x7e, 0x77,
+       0x93, 0xac, 0xaf, 0x67, 0xa9, 0xfe, 0xff, 0x2b, 0xc0, 0xf3, 0xd1, 0x26,
+       0xfa, 0xf9, 0x3d, 0x85, 0x9d, 0x8b, 0x4f, 0x6f, 0xc1, 0x38, 0xdf, 0xce,
+       0xa5, 0xe2, 0x3b, 0x67, 0x0e, 0xf8, 0xef, 0x6b, 0xec, 0xf3, 0x28, 0x34,
+       0x0f, 0xc6, 0x04, 0x28, 0x8f, 0x39, 0xe3, 0xf7, 0xf6, 0xab, 0xfc, 0x59,
+       0xfc, 0xfb, 0x0b, 0x35, 0x7d, 0x03, 0x68, 0xcf, 0x07, 0xaa, 0x38, 0x5c,
+       0x2f, 0x06, 0x0c, 0x8e, 0xf7, 0x41, 0x8e, 0xc7, 0x9e, 0x88, 0x4c, 0x7c,
+       0xb4, 0x6b, 0xb0, 0xda, 0x8b, 0xfa, 0xce, 0x69, 0x37, 0x3e, 0x92, 0xfd,
+       0xee, 0x24, 0x9e, 0xd7, 0x62, 0xd7, 0x37, 0x17, 0xaa, 0x17, 0x3b, 0xe4,
+       0xfe, 0x04, 0x77, 0xdf, 0x75, 0x24, 0xef, 0xbe, 0x29, 0x93, 0xbc, 0x62,
+       0x8c, 0xcb, 0x3b, 0x89, 0xc9, 0x06, 0xfe, 0xae, 0x46, 0x4b, 0x80, 0xd3,
+       0x53, 0x95, 0x90, 0xd7, 0x1d, 0xae, 0xc4, 0x7e, 0xcc, 0x2b, 0xe8, 0x78,
+       0xd6, 0xc7, 0xd6, 0x1b, 0x29, 0xba, 0x28, 0x12, 0x63, 0x76, 0xb6, 0xca,
+       0x19, 0x7f, 0x3f, 0xed, 0x50, 0x40, 0xe1, 0xfb, 0x3f, 0x7c, 0xdf, 0xb9,
+       0xfd, 0x20, 0xf6, 0xfd, 0x49, 0x81, 0x87, 0x0b, 0xed, 0x3f, 0x86, 0x59,
+       0xd0, 0x9e, 0xee, 0x8b, 0x6f, 0x1a, 0x73, 0x07, 0xca, 0xf1, 0x56, 0xee,
+       0x3f, 0xf7, 0x25, 0xde, 0xa2, 0xbc, 0xa3, 0xa2, 0xd9, 0x0b, 0xc9, 0xef,
+       0x39, 0x72, 0xf0, 0x52, 0xf2, 0x07, 0x8a, 0xaa, 0x4c, 0xdb, 0xef, 0x6b,
+       0x66, 0x8f, 0xe0, 0xb7, 0x56, 0xe4, 0x78, 0xce, 0x1b, 0x0f, 0x18, 0x49,
+       0x1e, 0xef, 0x5b, 0xdd, 0x41, 0x7e, 0xf6, 0xbe, 0xc1, 0xcc, 0xf7, 0x62,
+       0x0a, 0x72, 0x78, 0x5e, 0x5a, 0x1f, 0xc8, 0x4b, 0xfc, 0xbe, 0xc9, 0x48,
+       0xf3, 0xeb, 0x39, 0x9c, 0xff, 0xfe, 0x29, 0x20, 0xe8, 0x6e, 0xce, 0x3b,
+       0xf4, 0xbd, 0x8c, 0x34, 0x3d, 0xfb, 0xb2, 0xd0, 0xb3, 0xa4, 0x6f, 0x8b,
+       0x55, 0x16, 0x53, 0xd2, 0xf2, 0x1c, 0x26, 0x08, 0xfc, 0x39, 0xf5, 0x27,
+       0x53, 0xe3, 0x9e, 0x4b, 0x6b, 0x88, 0xce, 0x09, 0x7f, 0xfb, 0xc4, 0xf9,
+       0xc5, 0x43, 0xa6, 0x4c, 0x78, 0xb7, 0xe8, 0x1c, 0xcf, 0x0f, 0x10, 0xaf,
+       0xb0, 0x0e, 0x53, 0xd0, 0x21, 0x9d, 0x6f, 0xf4, 0xb0, 0xb8, 0x07, 0xf9,
+       0x26, 0xd6, 0xc4, 0xf3, 0x3c, 0x9c, 0x70, 0x4f, 0xf0, 0xcb, 0x17, 0xb5,
+       0xbe, 0x60, 0x0e, 0xf7, 0x43, 0xce, 0xcd, 0x27, 0xfc, 0xf5, 0x89, 0x7e,
+       0x0e, 0xf7, 0xce, 0xda, 0xfb, 0xe9, 0x9e, 0x23, 0xcc, 0x17, 0x42, 0xfa,
+       0x90, 0x7e, 0xf0, 0x1f, 0xa7, 0xe9, 0x3e, 0xd4, 0xb3, 0x2e, 0xfa, 0x3d,
+       0xdb, 0x19, 0xcf, 0xba, 0x12, 0x18, 0xd3, 0xba, 0xf3, 0x20, 0xff, 0xbd,
+       0x45, 0xf9, 0x45, 0x2f, 0xc1, 0xf9, 0xcf, 0x87, 0xf9, 0xf7, 0xd5, 0x13,
+       0x7e, 0x6e, 0x8f, 0xfd, 0x5a, 0xe7, 0xbf, 0x57, 0xf4, 0x55, 0xf7, 0x60,
+       0xf7, 0x17, 0xa0, 0x3e, 0xf4, 0xac, 0xc2, 0xc8, 0x9e, 0x8c, 0x83, 0xe2,
+       0x02, 0x7a, 0x3d, 0x2d, 0xe8, 0x95, 0x3d, 0xc7, 0xeb, 0x2b, 0xbd, 0xbc,
+       0x7a, 0xe7, 0xc1, 0xfe, 0x65, 0x38, 0xde, 0xaa, 0xe7, 0x78, 0x1e, 0xe6,
+       0x9d, 0xcf, 0xdf, 0x76, 0xe3, 0x17, 0xa0, 0x7e, 0xdb, 0x80, 0x8b, 0xee,
+       0x0c, 0xdc, 0xf9, 0xf8, 0x7a, 0x6d, 0x0c, 0xd4, 0x6f, 0x8f, 0x4b, 0x7d,
+       0x58, 0xff, 0xcd, 0x74, 0x46, 0xbf, 0xf7, 0x19, 0xcb, 0xd3, 0x28, 0xce,
+       0xf5, 0x9b, 0xc0, 0x60, 0xc1, 0x02, 0xc0, 0xf7, 0x07, 0xeb, 0x3c, 0xcc,
+       0xb8, 0x0c, 0xe3, 0xa4, 0x83, 0x05, 0xf3, 0x01, 0x0f, 0x77, 0xc4, 0x9f,
+       0x9e, 0x89, 0xfd, 0xee, 0x78, 0x4a, 0x0a, 0x23, 0xdb, 0xce, 0x78, 0xf6,
+       0xf1, 0x57, 0x46, 0x03, 0x5c, 0x77, 0x7e, 0x43, 0xa2, 0xfc, 0xaf, 0xaf,
+       0x1c, 0xc9, 0xb6, 0xd9, 0x85, 0xa7, 0x61, 0x29, 0xd3, 0xe0, 0xfd, 0x9a,
+       0x83, 0xfc, 0x77, 0x23, 0x6f, 0x63, 0x3d, 0x33, 0x11, 0x1f, 0x77, 0x3e,
+       0xde, 0x4b, 0xbf, 0x7f, 0x68, 0xe1, 0xf3, 0x83, 0x75, 0x95, 0xcc, 0x48,
+       0xfb, 0xdd, 0xb0, 0x3b, 0xbf, 0xf1, 0x34, 0xfd, 0x9e, 0xe1, 0x5d, 0xdf,
+       0x92, 0xe8, 0xf7, 0x15, 0xef, 0x92, 0xf9, 0x3d, 0xa2, 0x7f, 0x7e, 0xde,
+       0xbb, 0xe8, 0x31, 0x1f, 0xae, 0x6f, 0xbd, 0x76, 0xa9, 0x1f, 0xd7, 0xb5,
+       0x59, 0xc3, 0x76, 0xb7, 0xc5, 0x5b, 0xbe, 0x8b, 0x29, 0x4d, 0x77, 0xc4,
+       0x0f, 0x6a, 0x33, 0xe1, 0xfd, 0x1d, 0x07, 0x0e, 0x6a, 0x2b, 0xd1, 0x2f,
+       0x73, 0xb3, 0x66, 0xd4, 0x3f, 0x5f, 0x39, 0x72, 0x85, 0x4d, 0xee, 0x9c,
+       0xde, 0xa7, 0x90, 0x7f, 0xb0, 0x26, 0xd7, 0x43, 0xf7, 0xeb, 0x99, 0xcf,
+       0x0c, 0xcd, 0x9b, 0x30, 0x7c, 0x9f, 0x3f, 0x58, 0xc7, 0x6c, 0x70, 0xdd,
+       0x61, 0xc5, 0x09, 0xd4, 0xb8, 0x36, 0x37, 0xad, 0xbd, 0x4b, 0xe7, 0xfe,
+       0xef, 0x57, 0x8e, 0x28, 0xb6, 0x79, 0x2c, 0x3b, 0x20, 0x76, 0x8c, 0xeb,
+       0x85, 0xd8, 0xdf, 0xfa, 0x29, 0x7e, 0x6e, 0xed, 0xdf, 0x1a, 0xe1, 0x77,
+       0x5b, 0xfb, 0xb7, 0xc6, 0x0a, 0xc4, 0xab, 0x43, 0x93, 0x33, 0xc1, 0xd3,
+       0x8d, 0xfb, 0x01, 0xf0, 0xf4, 0xac, 0xd3, 0xa9, 0xdc, 0xb9, 0x2e, 0x44,
+       0xe5, 0xee, 0x75, 0x06, 0xed, 0xd3, 0x5e, 0xc4, 0x23, 0x94, 0x5d, 0x02,
+       0xee, 0xc0, 0x54, 0x56, 0x8f, 0xdf, 0xe7, 0x0f, 0x98, 0x3c, 0xed, 0x38,
+       0xaf, 0xc9, 0xac, 0xc7, 0xbb, 0x65, 0x79, 0x11, 0x5e, 0x2f, 0x58, 0x12,
+       0x25, 0x3f, 0x64, 0x24, 0x3b, 0xc6, 0x2a, 0xf7, 0xba, 0xa2, 0x2d, 0xe8,
+       0x43, 0x76, 0xee, 0xe8, 0x9f, 0xa5, 0x82, 0xdd, 0xb3, 0x57, 0x8b, 0xde,
+       0x8d, 0x91, 0x2f, 0xbd, 0xe3, 0xd5, 0x59, 0x0d, 0x50, 0xff, 0x9b, 0x9c,
+       0xc8, 0xc6, 0x1c, 0x92, 0x37, 0x61, 0x03, 0xf9, 0xce, 0xf2, 0xcf, 0xbf,
+       0x9e, 0xc3, 0xe5, 0xee, 0xa6, 0xd1, 0x1a, 0xe1, 0x7b, 0xef, 0xd2, 0xc9,
+       0x8f, 0x29, 0x96, 0xff, 0x85, 0x71, 0xbf, 0xa5, 0x2b, 0x9f, 0x40, 0x7b,
+       0x02, 0xfa, 0x6f, 0xcf, 0x21, 0xbe, 0x0d, 0xd3, 0x77, 0xba, 0x46, 0xea,
+       0x5f, 0xb0, 0xac, 0xce, 0xd6, 0xbf, 0x60, 0xd9, 0x2a, 0xab, 0xff, 0x1e,
+       0xea, 0xef, 0x39, 0x7f, 0xff, 0xbd, 0xcb, 0xae, 0xb1, 0xcf, 0xbf, 0xec,
+       0x0e, 0xab, 0xff, 0x23, 0x04, 0xbf, 0xef, 0xfc, 0xf0, 0x17, 0x34, 0x4f,
+       0xb5, 0xcf, 0xdf, 0xbc, 0x9a, 0xfa, 0x7f, 0xd5, 0xcd, 0xf7, 0x77, 0x28,
+       0xd7, 0x43, 0xf9, 0xf4, 0x1d, 0xde, 0x70, 0xc2, 0x45, 0xfe, 0x33, 0xa3,
+       0xef, 0x73, 0xa8, 0x79, 0x97, 0x1e, 0xa2, 0xef, 0x27, 0x9d, 0x8b, 0x33,
+       0x0d, 0x9a, 0xa8, 0x67, 0x7d, 0x4f, 0xe5, 0x56, 0xa3, 0x1c, 0x4b, 0xd1,
+       0xd1, 0xf4, 0x6f, 0xe2, 0x3a, 0xfc, 0xc0, 0x5d, 0xe9, 0x74, 0x94, 0x53,
+       0x97, 0x65, 0xe3, 0xab, 0x5c, 0x33, 0xcf, 0x56, 0xcf, 0x9f, 0x3d, 0xc6,
+       0xd6, 0x7e, 0x54, 0xa4, 0xcc, 0xf6, 0xbe, 0x70, 0xd1, 0xe5, 0x0e, 0xba,
+       0xf4, 0xe9, 0x94, 0x07, 0xcb, 0xb8, 0x3e, 0x35, 0x31, 0xce, 0x09, 0x70,
+       0x6a, 0x63, 0xf8, 0xf7, 0x9a, 0xea, 0xc7, 0x78, 0x68, 0x7d, 0xf7, 0xbf,
+       0xe8, 0xa5, 0xfa, 0xfd, 0xd7, 0xf0, 0xf5, 0xdd, 0x3f, 0xc6, 0x47, 0x7c,
+       0x4c, 0xba, 0x0b, 0xf6, 0xfd, 0x7e, 0x2d, 0x7a, 0x65, 0xba, 0x7d, 0x0c,
+       0xeb, 0x92, 0x30, 0xe4, 0xf5, 0x8c, 0x1e, 0x1d, 0xc8, 0xa9, 0x4d, 0x7f,
+       0x6e, 0xc8, 0xf8, 0x3c, 0x4b, 0xe1, 0xbf, 0x63, 0x97, 0xe5, 0xe6, 0xfa,
+       0x72, 0x73, 0xe9, 0xe4, 0xc7, 0x62, 0x69, 0xf8, 0xdc, 0x52, 0x0c, 0xf4,
+       0x00, 0xf5, 0xb7, 0x73, 0x34, 0x5b, 0x9c, 0x67, 0x73, 0xf1, 0xca, 0x50,
+       0x4b, 0xda, 0x3c, 0x9b, 0x8a, 0xb5, 0x45, 0x87, 0xaa, 0xf8, 0xf3, 0x5b,
+       0xd0, 0x8e, 0xd7, 0x23, 0x7f, 0x87, 0xf3, 0x7d, 0x55, 0x1b, 0xba, 0x14,
+       0xed, 0x57, 0xe7, 0x3c, 0xee, 0xb2, 0x3a, 0xdb, 0x3c, 0x9e, 0x92, 0x55,
+       0x34, 0x4f, 0xd2, 0x31, 0x8f, 0xbb, 0x64, 0x95, 0x63, 0x1e, 0xcf, 0xa2,
+       0x43, 0xe2, 0xb9, 0x98, 0xe7, 0x14, 0xd2, 0xc9, 0x48, 0xf3, 0x6c, 0x2e,
+       0xbb, 0xc6, 0xbe, 0x9e, 0x92, 0x3b, 0x68, 0x9e, 0x5f, 0xe3, 0x3c, 0xb5,
+       0x69, 0xeb, 0x29, 0xb9, 0xc3, 0x31, 0x4f, 0x16, 0x5f, 0x0f, 0x3c, 0x17,
+       0xf3, 0xfc, 0xe6, 0xbc, 0xeb, 0x29, 0x9f, 0x6a, 0x5f, 0xcf, 0xd8, 0xd5,
+       0x34, 0xcf, 0xbf, 0x3b, 0xe6, 0x71, 0x8f, 0x5d, 0xed, 0x98, 0xc7, 0x47,
+       0xf3, 0xe0, 0x73, 0x9c, 0x87, 0x15, 0x71, 0x3f, 0x4a, 0x73, 0x0f, 0xad,
+       0xa4, 0xfd, 0xff, 0x81, 0x97, 0x61, 0x1c, 0x48, 0x73, 0x47, 0xff, 0x9a,
+       0x2e, 0xa9, 0xfc, 0xbd, 0x97, 0xe2, 0xc2, 0xd0, 0xca, 0xc4, 0x76, 0xff,
+       0x07, 0xfe, 0x22, 0x63, 0x96, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d,
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+       0x01, 0x5c, 0xa6, 0x59, 0xe4, 0xa1, 0x22, 0x06, 0x57, 0x70, 0x81, 0x0e,
+       0x4b, 0xf6, 0xa4, 0xa3, 0xe2, 0x3c, 0x1c, 0x75, 0xd2, 0x10, 0x45, 0x54,
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+       0x68, 0x80, 0x80, 0x0d, 0xa8, 0x83, 0x33, 0x2e, 0x71, 0x9e, 0xe3, 0x32,
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+       0x39, 0x75, 0xaa, 0x9a, 0x0c, 0x4f, 0x22, 0x64, 0x1c, 0x21, 0xfb, 0x12,
+       0x68, 0x39, 0x86, 0x90, 0x6f, 0xe3, 0x3c, 0x17, 0x39, 0x6d, 0x84, 0xfc,
+       0x00, 0x7f, 0x3f, 0x26, 0xf4, 0xcf, 0x47, 0x48, 0x2a, 0x2f, 0xd3, 0x08,
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+       0x65, 0x5e, 0x5e, 0x64, 0x3c, 0xad, 0x5c, 0xe0, 0x97, 0x8f, 0x84, 0x86,
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+       0xfb, 0x65, 0x09, 0x4e, 0x9c, 0x8f, 0x56, 0x3f, 0x52, 0x4f, 0xeb, 0x66,
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+       0x7b, 0xe1, 0xed, 0xe6, 0xc0, 0x3a, 0x01, 0x9e, 0xba, 0x07, 0x98, 0x32,
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+       0xd5, 0x6f, 0x09, 0x0e, 0xac, 0x0e, 0x30, 0x8d, 0x25, 0xe4, 0xe6, 0x65,
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+       0x3c, 0xb4, 0xae, 0xfb, 0xfe, 0x2d, 0xe5, 0xc6, 0xfa, 0x6d, 0x44, 0x8a,
+       0xd4, 0x73, 0x09, 0xb9, 0xd0, 0x39, 0x98, 0xe3, 0x83, 0x7f, 0x57, 0x0d,
+       0xc8, 0x80, 0xaf, 0x1b, 0xe9, 0x9a, 0x32, 0x29, 0x0a, 0x6f, 0x83, 0x72,
+       0x14, 0x34, 0x3b, 0x11, 0x5f, 0xb3, 0x9d, 0xec, 0x5d, 0x6d, 0x3e, 0xde,
+       0x7b, 0x64, 0x12, 0x84, 0xf9, 0x48, 0xa1, 0x54, 0x92, 0x07, 0x2d, 0xa9,
+       0xd8, 0xcf, 0x03, 0xfd, 0xd4, 0xbe, 0xf3, 0x9b, 0x2d, 0x5b, 0xdc, 0xc5,
+       0x14, 0x9f, 0xb3, 0xef, 0x16, 0x11, 0x8e, 0xd1, 0xf3, 0x0d, 0xed, 0x8e,
+       0x77, 0x9b, 0xf2, 0x69, 0xd9, 0xf8, 0xb5, 0x4c, 0x06, 0x9f, 0x7d, 0xfe,
+       0x73, 0x16, 0x19, 0xdb, 0x89, 0x8f, 0x7d, 0x4f, 0x83, 0xab, 0x46, 0x07,
+       0x37, 0xcd, 0x9c, 0xf0, 0xe4, 0x61, 0x1d, 0x7d, 0xcc, 0xf2, 0x5c, 0xf1,
+       0xe4, 0x61, 0x03, 0x9c, 0x66, 0x18, 0xea, 0xb7, 0xd5, 0xcd, 0x32, 0xf4,
+       0x9f, 0xb3, 0xa8, 0xc4, 0xd0, 0x5e, 0xe2, 0xab, 0x30, 0xb4, 0xcf, 0x5b,
+       0x76, 0xbb, 0xa1, 0xbe, 0xc0, 0x7f, 0xb7, 0xa1, 0x7f, 0x59, 0xe3, 0x62,
+       0x43, 0x7b, 0x45, 0xe0, 0x21, 0x43, 0x7b, 0xd5, 0x86, 0x15, 0x86, 0x7a,
+       0x4d, 0xcb, 0x2a, 0x43, 0x7f, 0x6f, 0xdb, 0x5a, 0x43, 0xbb, 0x69, 0xf7,
+       0x88, 0x6b, 0x08, 0x85, 0x63, 0xc3, 0xef, 0x44, 0x62, 0xa6, 0x70, 0xfc,
+       0xc6, 0x76, 0xe4, 0xb1, 0x8b, 0x53, 0xa0, 0x94, 0x5c, 0x00, 0xf7, 0xa3,
+       0xf5, 0x19, 0x48, 0xd7, 0xc7, 0xea, 0x55, 0x2c, 0x6b, 0x81, 0xf6, 0xc6,
+       0x01, 0xff, 0x8c, 0xb6, 0x78, 0x28, 0x9e, 0xbc, 0x71, 0xe1, 0x52, 0x92,
+       0x48, 0xc8, 0x7d, 0xfe, 0x4b, 0x96, 0x2d, 0xbb, 0x84, 0xd6, 0x15, 0xda,
+       0x3e, 0x9e, 0x52, 0xbb, 0x7f, 0xe2, 0x32, 0x5f, 0x36, 0x21, 0xcb, 0x9c,
+       0x2a, 0xd2, 0xbd, 0xd8, 0xa8, 0x90, 0x20, 0x25, 0x55, 0x81, 0x24, 0xf5,
+       0xd2, 0x75, 0x58, 0xd4, 0xb5, 0x87, 0xce, 0xd2, 0xde, 0x28, 0x91, 0xe0,
+       0xe8, 0xbe, 0xed, 0x62, 0x28, 0xf6, 0xf3, 0x1e, 0x21, 0x3c, 0x34, 0x8b,
+       0xae, 0xc3, 0xf7, 0xa9, 0x99, 0xac, 0x17, 0xfa, 0xf2, 0x79, 0x84, 0x2f,
+       0xc9, 0x00, 0x92, 0xd1, 0x7f, 0x7b, 0x97, 0x89, 0x94, 0xb7, 0xe8, 0xe4,
+       0xce, 0x7a, 0xa7, 0x09, 0xe7, 0x93, 0xea, 0x9c, 0xb8, 0xde, 0x49, 0xe9,
+       0xa1, 0x5a, 0x61, 0xfc, 0x5e, 0xbd, 0x35, 0x73, 0x22, 0x71, 0x40, 0x3d,
+       0x38, 0xb4, 0xce, 0x76, 0x86, 0xef, 0xb5, 0xd0, 0xc9, 0xa4, 0xc3, 0x38,
+       0x8c, 0x5f, 0x2a, 0x02, 0x03, 0x22, 0xfc, 0x8b, 0xf8, 0x1b, 0x62, 0xe0,
+       0xfb, 0x61, 0x09, 0x9e, 0x66, 0x27, 0xfd, 0x5e, 0xd7, 0x1e, 0x71, 0x26,
+       0xcc, 0x83, 0x04, 0xf7, 0xe5, 0x5c, 0x37, 0x12, 0xbe, 0xef, 0x5e, 0x0f,
+       0xcf, 0x49, 0x1b, 0x1d, 0x24, 0x93, 0xf2, 0x77, 0xbd, 0xfb, 0xc9, 0xc3,
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+       0x61, 0x99, 0x90, 0x3f, 0xd6, 0xcf, 0xc4, 0xfa, 0x81, 0x7a, 0x0f, 0x96,
+       0xa1, 0xfa, 0x72, 0x2c, 0x0f, 0xd5, 0xd7, 0x61, 0xfb, 0xe1, 0xfa, 0x45,
+       0x58, 0x3f, 0x52, 0xef, 0xc3, 0xf2, 0x68, 0xfd, 0x32, 0x2c, 0x8f, 0xd5,
+       0xfb, 0xb1, 0xbd, 0xab, 0xbe, 0x11, 0xeb, 0xdd, 0xf5, 0x01, 0x2c, 0x35,
+       0x3e, 0xa0, 0xf2, 0x68, 0x4e, 0x31, 0xf0, 0x69, 0x71, 0xb1, 0x09, 0xf8,
+       0xf4, 0x0e, 0x2b, 0xe1, 0x7f, 0xac, 0x7e, 0x92, 0xaf, 0x41, 0xa4, 0xff,
+       0xee, 0x40, 0xbe, 0x76, 0x65, 0x00, 0x5f, 0x9f, 0xb4, 0x7d, 0x3b, 0x34,
+       0x8b, 0xd2, 0xdb, 0xc9, 0x4f, 0x28, 0x31, 0xe5, 0xf6, 0x0f, 0xa7, 0x68,
+       0xba, 0xeb, 0x1f, 0x7f, 0x6e, 0x13, 0xe0, 0xaf, 0x34, 0x40, 0x89, 0x27,
+       0xb9, 0x6f, 0xbb, 0x35, 0x8e, 0xe1, 0xc7, 0x6a, 0x22, 0x53, 0x09, 0x95,
+       0x3f, 0x0f, 0x9d, 0xaf, 0x10, 0x89, 0x7e, 0x3f, 0xee, 0xf5, 0x0b, 0xd7,
+       0x89, 0xb9, 0xf8, 0x5c, 0x02, 0xd2, 0xa1, 0x8a, 0xc3, 0x35, 0xc3, 0x1e,
+       0x63, 0xfc, 0xf3, 0x08, 0xe2, 0xeb, 0x6c, 0x78, 0xd2, 0xfa, 0x1f, 0x79,
+       0xf6, 0xcf, 0x45, 0x73, 0xf3, 0x00, 0x3f, 0x83, 0x91, 0x4e, 0xe2, 0xf6,
+       0x89, 0x75, 0x0c, 0x6f, 0xcf, 0xbb, 0x00, 0x6f, 0x67, 0x83, 0x9f, 0xc4,
+       0xf9, 0x2b, 0x1a, 0x8e, 0xc2, 0xeb, 0x7f, 0xca, 0x09, 0xd1, 0xfe, 0x5f,
+       0xa5, 0x6a, 0xf0, 0xec, 0xc8, 0x21, 0xb4, 0xbc, 0xce, 0x59, 0x7c, 0x14,
+       0xe8, 0xe0, 0x64, 0xab, 0x19, 0xd7, 0x75, 0xb2, 0x3d, 0x3e, 0x40, 0x60,
+       0x0c, 0x67, 0x0a, 0xd2, 0x45, 0xff, 0x70, 0x63, 0xf3, 0xa8, 0xda, 0x60,
+       0xf5, 0xeb, 0xe5, 0x43, 0x4d, 0x4b, 0xa2, 0xdf, 0x28, 0x2f, 0x32, 0xfd,
+       0x7a, 0x79, 0x71, 0x72, 0xff, 0xf3, 0x0e, 0xe0, 0xfb, 0x3b, 0x32, 0x44,
+       0xff, 0xe1, 0xd1, 0x40, 0x1f, 0x6e, 0x4e, 0x1f, 0x8c, 0xee, 0xb4, 0xf1,
+       0x6b, 0x5a, 0x72, 0xfd, 0x36, 0xc3, 0x38, 0xc6, 0xfa, 0x49, 0xbf, 0x30,
+       0xb5, 0x05, 0xe5, 0xbc, 0x9a, 0x70, 0xfd, 0xc8, 0xfe, 0xe7, 0x79, 0x47,
+       0x86, 0x82, 0xdf, 0x39, 0xb6, 0x61, 0x48, 0x02, 0x7c, 0xf7, 0x58, 0xbd,
+       0xc5, 0x0f, 0xdf, 0xe9, 0xaa, 0x77, 0xfa, 0xd9, 0x77, 0x33, 0xfc, 0x7a,
+       0xba, 0xac, 0x5e, 0x14, 0xef, 0x3f, 0x9c, 0x1c, 0x99, 0x5f, 0x7f, 0xe3,
+       0xfe, 0xb3, 0xe7, 0x47, 0x48, 0x2b, 0xf9, 0xdc, 0x42, 0x10, 0xf4, 0x3f,
+       0x0c, 0xe9, 0xbf, 0x7f, 0xbf, 0xf8, 0x90, 0x4e, 0x29, 0xc5, 0x40, 0x1f,
+       0xed, 0xf2, 0xb7, 0xa0, 0x77, 0xe2, 0x86, 0x6b, 0x7a, 0x47, 0xc2, 0xba,
+       0x36, 0xae, 0xb7, 0x45, 0xf4, 0x99, 0x2f, 0x82, 0xe7, 0x9b, 0x0c, 0xdf,
+       0xa3, 0xef, 0xa9, 0x47, 0x34, 0x3c, 0x0d, 0x3e, 0x13, 0xde, 0x25, 0x72,
+       0x44, 0x5b, 0x27, 0x95, 0x93, 0x23, 0xa9, 0xec, 0x06, 0x3a, 0xa5, 0xc4,
+       0x8c, 0x78, 0xf6, 0xd0, 0x11, 0x13, 0xe8, 0x78, 0x3d, 0x92, 0x6d, 0x99,
+       0x40, 0xbf, 0x63, 0x4e, 0x54, 0xb1, 0xdd, 0x0b, 0x1f, 0xa2, 0xf4, 0x54,
+       0x63, 0x09, 0x29, 0x1e, 0x15, 0xc1, 0xdd, 0x01, 0x76, 0xd6, 0xdc, 0xb1,
+       0x1a, 0xdf, 0xab, 0x37, 0xfd, 0x81, 0x92, 0xdc, 0x97, 0xbf, 0x91, 0xc9,
+       0xc3, 0xd0, 0xfe, 0x17, 0x3a, 0x3a, 0x6d, 0x97, 0x79, 0xeb, 0x7c, 0x52,
+       0xec, 0x20, 0xf4, 0x7b, 0x73, 0x5b, 0xab, 0xa6, 0x81, 0x9c, 0xfc, 0xf2,
+       0xd5, 0xab, 0xb8, 0x9d, 0xe2, 0x2f, 0x82, 0x75, 0x7f, 0x45, 0x4c, 0x53,
+       0x81, 0x4f, 0xbe, 0x22, 0xbf, 0x75, 0x8c, 0xd6, 0xd9, 0x65, 0xd3, 0x13,
+       0x15, 0x36, 0xbf, 0x65, 0x4c, 0x3f, 0xfb, 0xe8, 0x7f, 0xb0, 0x3e, 0x6a,
+       0xa7, 0x19, 0xf4, 0x75, 0x59, 0xa3, 0xb1, 0x5e, 0x4a, 0xae, 0x4d, 0x03,
+       0x7e, 0x28, 0x5d, 0x29, 0x93, 0x00, 0x9d, 0x7b, 0x05, 0xe8, 0x7b, 0x6d,
+       0xdd, 0x94, 0xef, 0x2f, 0x4b, 0x64, 0x76, 0x5c, 0x19, 0xa9, 0x5b, 0x0a,
+       0x76, 0xca, 0xc3, 0x32, 0x99, 0x09, 0xf8, 0x9e, 0xeb, 0x24, 0xd2, 0x00,
+       0x2a, 0x27, 0x6a, 0x5e, 0x5b, 0x5d, 0x54, 0x42, 0xeb, 0x37, 0x24, 0x9a,
+       0x90, 0xae, 0x8e, 0x51, 0xfb, 0x4e, 0xa5, 0x72, 0xa8, 0x22, 0x89, 0xd9,
+       0x31, 0x95, 0x29, 0x01, 0xc5, 0x4d, 0xdb, 0x3f, 0x6f, 0x1d, 0x7d, 0xe3,
+       0xc5, 0x04, 0xde, 0x0f, 0x2c, 0x05, 0xb9, 0xe6, 0xb3, 0x13, 0xd7, 0x7a,
+       0xd2, 0x17, 0xee, 0xf3, 0x96, 0x19, 0xe7, 0x77, 0xb6, 0xf9, 0x47, 0xcf,
+       0x97, 0x90, 0x25, 0x38, 0x5f, 0x6d, 0x1e, 0xda, 0xb8, 0xda, 0x3c, 0xc4,
+       0x0d, 0x82, 0x3b, 0x10, 0xc3, 0x9e, 0x9d, 0x97, 0x28, 0x44, 0xec, 0x64,
+       0x5a, 0xde, 0x99, 0x68, 0xb4, 0x5f, 0x17, 0x41, 0x5d, 0x67, 0xdf, 0xde,
+       0x17, 0x55, 0x5f, 0x12, 0x55, 0xd7, 0xe8, 0x44, 0xe6, 0x74, 0x62, 0x4e,
+       0xf4, 0x2c, 0x4a, 0x4c, 0x05, 0xba, 0x08, 0x4f, 0x41, 0x3b, 0x8d, 0x50,
+       0xfa, 0xc8, 0x8b, 0xf4, 0x53, 0x22, 0xfd, 0xee, 0x3b, 0x53, 0x3f, 0x33,
+       0xf4, 0x13, 0xb1, 0xdf, 0x92, 0x33, 0xf5, 0xb3, 0x46, 0xc6, 0x7b, 0x30,
+       0x56, 0xbf, 0x9a, 0xd7, 0x36, 0xbf, 0xea, 0xa3, 0xf4, 0x54, 0xf9, 0xca,
+       0x53, 0x0e, 0x42, 0xe5, 0xf9, 0x97, 0x92, 0x3f, 0xcd, 0x45, 0x9f, 0x57,
+       0xaf, 0x7f, 0xc0, 0x01, 0x70, 0x3a, 0x2a, 0xf9, 0x1c, 0x80, 0xef, 0x2f,
+       0x03, 0xe2, 0xd4, 0x58, 0xf0, 0xda, 0xdd, 0x0b, 0x2f, 0xb7, 0x4d, 0x00,
+       0x3f, 0x02, 0x49, 0x9b, 0xc2, 0xfd, 0xa5, 0x47, 0xa6, 0x83, 0x9d, 0xf4,
+       0xed, 0x7a, 0xd9, 0x29, 0xd2, 0x2e, 0xde, 0x0d, 0xe6, 0xa0, 0x99, 0xd2,
+       0x6f, 0x6d, 0x6b, 0xc5, 0x34, 0x92, 0x8f, 0xf5, 0x83, 0xac, 0xfe, 0xe0,
+       0x09, 0x11, 0xea, 0x6d, 0x46, 0x7c, 0x56, 0xbe, 0xf8, 0x54, 0x9a, 0x6a,
+       0x47, 0x3c, 0x30, 0x7b, 0x9b, 0x04, 0xd1, 0xee, 0xa8, 0x6d, 0xfe, 0x62,
+       0x0a, 0xc8, 0x71, 0x2f, 0x09, 0x23, 0x1d, 0x46, 0xbf, 0x07, 0xdf, 0x3f,
+       0x9d, 0x84, 0x7c, 0x5f, 0xa2, 0x24, 0xf4, 0x6d, 0xa7, 0xf3, 0x44, 0x3b,
+       0xd9, 0xcb, 0xf9, 0xcc, 0xdb, 0xfa, 0xc8, 0x09, 0xd1, 0x01, 0xe5, 0x15,
+       0x9d, 0xc0, 0x67, 0xde, 0x28, 0x3a, 0x2a, 0xef, 0xd5, 0x2f, 0x21, 0xa5,
+       0x98, 0xce, 0xe7, 0x95, 0x44, 0x7b, 0xca, 0x91, 0x0b, 0x69, 0xf5, 0x47,
+       0xe4, 0x47, 0x20, 0x0f, 0x34, 0xb8, 0x90, 0x00, 0xb3, 0x2b, 0x1a, 0x36,
+       0x3e, 0x93, 0x7f, 0x90, 0xce, 0xab, 0xab, 0xf9, 0x37, 0x0e, 0x21, 0x4f,
+       0x2f, 0x47, 0x18, 0x3d, 0x9e, 0x6c, 0x99, 0xf7, 0xf3, 0x1d, 0x6a, 0xff,
+       0xf2, 0xa6, 0x9b, 0xfb, 0x45, 0x91, 0xf7, 0x02, 0xf8, 0x9e, 0xda, 0xc6,
+       0xec, 0x20, 0xd2, 0xce, 0xca, 0x6a, 0x39, 0xe8, 0x00, 0xbb, 0xb3, 0x7a,
+       0xad, 0xec, 0xa2, 0x94, 0x4a, 0xaa, 0x37, 0x3f, 0xff, 0xc2, 0xb3, 0xe0,
+       0xaf, 0x7d, 0x6a, 0x46, 0x7f, 0xad, 0x6a, 0xf3, 0x9b, 0x1f, 0x8d, 0xa7,
+       0xf5, 0xaa, 0x2d, 0x72, 0xca, 0x34, 0xb6, 0x1c, 0x9b, 0x90, 0x16, 0xc1,
+       0x8f, 0x97, 0xfe, 0x6f, 0xd1, 0xa8, 0x08, 0x3e, 0x2a, 0x7f, 0xf9, 0xa6,
+       0xa2, 0x8e, 0x64, 0xcf, 0xef, 0x4d, 0x8a, 0xe0, 0xa5, 0x6a, 0xcb, 0x1e,
+       0x85, 0x8c, 0xec, 0x0b, 0xc7, 0x49, 0x2d, 0x7b, 0x94, 0x90, 0x2d, 0x06,
+       0x7e, 0x5a, 0x0e, 0x4e, 0x01, 0xbb, 0xa5, 0x61, 0xe3, 0x77, 0x0a, 0xf8,
+       0x5f, 0x5f, 0xee, 0x16, 0x48, 0x7a, 0x6e, 0xdf, 0xf7, 0xcb, 0xd7, 0xbe,
+       0x89, 0x7a, 0x11, 0xe0, 0x84, 0xf8, 0xe4, 0xf8, 0xea, 0xc5, 0x5f, 0x1f,
+       0xbc, 0x05, 0xa7, 0xef, 0x28, 0xc4, 0x7e, 0x4e, 0x90, 0x97, 0x67, 0xc3,
+       0x9b, 0x9f, 0xcb, 0xe9, 0x9a, 0xd7, 0xec, 0x24, 0x91, 0xce, 0xa3, 0xfc,
+       0xf7, 0xe6, 0xc0, 0x34, 0xc0, 0xe7, 0xcb, 0x77, 0x3a, 0x60, 0x3d, 0x9d,
+       0x52, 0x1d, 0xa3, 0xf3, 0xd5, 0x0f, 0xa4, 0xb9, 0xe9, 0xf7, 0xcb, 0x65,
+       0x5f, 0x9a, 0x13, 0x4b, 0xf6, 0xbc, 0x7c, 0xcd, 0x5d, 0x48, 0x7f, 0x65,
+       0x42, 0x5d, 0x9a, 0x13, 0xf9, 0xc9, 0x9d, 0x69, 0x42, 0xd9, 0xed, 0xcb,
+       0x84, 0x75, 0x2e, 0x68, 0xba, 0x01, 0xd7, 0x59, 0x4a, 0x3c, 0x48, 0x87,
+       0xe5, 0xab, 0xc5, 0xe2, 0x00, 0x2d, 0xbf, 0x91, 0xc8, 0xd4, 0x2d, 0x31,
+       0xf8, 0xa4, 0x28, 0x89, 0xf1, 0x49, 0xe7, 0x3a, 0x8a, 0x5c, 0xba, 0xce,
+       0x4e, 0xb0, 0xfb, 0xc1, 0xde, 0xfe, 0xad, 0x18, 0x58, 0x8f, 0xfe, 0xe9,
+       0xed, 0x04, 0xe4, 0xff, 0x5d, 0x7c, 0xcd, 0x54, 0x53, 0x62, 0xfd, 0x1b,
+       0x0b, 0xc3, 0x97, 0x2d, 0xc9, 0xa4, 0xf9, 0x8b, 0x16, 0x03, 0xfd, 0x36,
+       0x3f, 0xd8, 0x01, 0x78, 0x3a, 0x36, 0xd0, 0x9d, 0x0e, 0xf3, 0xa4, 0x70,
+       0xf0, 0x71, 0xb8, 0x09, 0x3f, 0xd0, 0x71, 0xc5, 0x0f, 0x2e, 0x4f, 0x67,
+       0x78, 0x22, 0xaa, 0x54, 0xc4, 0xdf, 0xa3, 0xfa, 0x60, 0x12, 0x3c, 0x87,
+       0xfe, 0x1d, 0xb2, 0xdb, 0x9a, 0x6f, 0x78, 0x8f, 0xcb, 0x4f, 0xf6, 0xfd,
+       0x85, 0xfc, 0xfb, 0x74, 0xde, 0x71, 0xa0, 0xdf, 0x3a, 0xd3, 0xa8, 0x7d,
+       0x1f, 0x63, 0x7d, 0x73, 0x61, 0x7d, 0xa8, 0x17, 0xa9, 0x9e, 0xd3, 0xd1,
+       0x99, 0x8e, 0xdf, 0x19, 0xff, 0x37, 0x3f, 0xc4, 0xf8, 0x5d, 0xe3, 0xff,
+       0xc0, 0x8c, 0xa9, 0xd0, 0x7e, 0xea, 0x43, 0xc6, 0x47, 0xf0, 0x1e, 0xe8,
+       0x13, 0x3a, 0xaf, 0x60, 0x3a, 0xb6, 0xef, 0xb9, 0x5e, 0x40, 0xf9, 0x60,
+       0x26, 0xc1, 0x58, 0x7c, 0xde, 0x2c, 0x73, 0x3e, 0x37, 0xb6, 0x7b, 0x29,
+       0xbf, 0x42, 0x9c, 0x40, 0xa3, 0x13, 0x3a, 0x7f, 0x49, 0x48, 0xd0, 0xd3,
+       0x0b, 0xfd, 0x4e, 0x12, 0xe2, 0x01, 0xfd, 0x95, 0xd2, 0x95, 0xf4, 0x7d,
+       0xbd, 0x7d, 0x03, 0xdf, 0xc5, 0x7e, 0x4a, 0xe4, 0xb9, 0x4e, 0xaf, 0x94,
+       0x71, 0xb9, 0x50, 0x90, 0x44, 0xe5, 0x41, 0x7c, 0x44, 0x1e, 0x90, 0xa6,
+       0xd4, 0x73, 0xb2, 0x23, 0xab, 0x65, 0xe2, 0x03, 0x93, 0xb3, 0xfa, 0x53,
+       0x33, 0xfa, 0xe3, 0xd5, 0x9b, 0xe5, 0x62, 0x58, 0xff, 0xf1, 0x4d, 0xfb,
+       0x3e, 0xba, 0x99, 0xd2, 0xf9, 0xf1, 0x16, 0x8d, 0x6f, 0x8d, 0x72, 0x35,
+       0x9a, 0x6f, 0xcb, 0xb7, 0xae, 0x17, 0x80, 0x4e, 0xa3, 0xf9, 0xf6, 0x78,
+       0x39, 0xd5, 0xe2, 0xb1, 0xf8, 0x96, 0x3e, 0x8f, 0xc9, 0xb7, 0xe5, 0xa1,
+       0xff, 0xa7, 0x72, 0x55, 0x83, 0xdf, 0xac, 0x24, 0xa3, 0x3c, 0xa5, 0xf2,
+       0x71, 0x10, 0x98, 0x10, 0xfd, 0xc1, 0x31, 0x5a, 0x3e, 0x7e, 0x03, 0xf6,
+       0x56, 0x6a, 0x5f, 0xf9, 0x48, 0xff, 0x3e, 0x24, 0x45, 0x7d, 0xe9, 0x50,
+       0xa3, 0x3f, 0x8d, 0xee, 0xa8, 0x05, 0x37, 0x08, 0xe4, 0x7a, 0x2f, 0x7d,
+       0x6a, 0xf4, 0xd7, 0x4b, 0x9f, 0x1a, 0xfd, 0x45, 0xaf, 0xd7, 0x08, 0xbf,
+       0xe8, 0xf6, 0xc1, 0xe0, 0x23, 0x51, 0x3a, 0x29, 0xde, 0x4e, 0x2d, 0x3a,
+       0x8a, 0xcf, 0xea, 0x76, 0x21, 0x60, 0x46, 0x3e, 0xf7, 0xbd, 0x35, 0xa0,
+       0x10, 0xe1, 0xe4, 0x46, 0xf5, 0x46, 0xfc, 0x6f, 0x0d, 0x48, 0xd1, 0xd7,
+       0x03, 0x51, 0xf5, 0x96, 0xa8, 0xfe, 0xee, 0xa8, 0x7a, 0x71, 0x54, 0x7f,
+       0x4f, 0x54, 0xbd, 0xce, 0xd0, 0xbf, 0xba, 0x6d, 0x9f, 0x42, 0x10, 0xff,
+       0x41, 0x43, 0x3f, 0xf3, 0xa2, 0xe7, 0xc8, 0xe7, 0x31, 0xfc, 0x41, 0x4d,
+       0xff, 0x78, 0x5b, 0x4f, 0x28, 0x3e, 0xa0, 0x8b, 0xec, 0xb0, 0x02, 0x72,
+       0x4f, 0x5e, 0x42, 0x4d, 0x37, 0x88, 0xaf, 0xed, 0x12, 0x31, 0xbe, 0xd6,
+       0xa3, 0x86, 0x1d, 0x49, 0xf4, 0xf9, 0x03, 0x56, 0xe6, 0xa7, 0xf5, 0x38,
+       0x79, 0x3d, 0x91, 0xd5, 0xc3, 0xa9, 0xca, 0x52, 0x90, 0x7b, 0xda, 0xf3,
+       0xb0, 0x95, 0xa0, 0x7f, 0xde, 0x53, 0x1c, 0x76, 0x24, 0xea, 0xfc, 0xff,
+       0x83, 0xed, 0xa2, 0x43, 0xa5, 0xed, 0xa1, 0x00, 0x99, 0xaa, 0x8f, 0x23,
+       0x44, 0xe6, 0xd3, 0x80, 0xf8, 0x0e, 0x91, 0xfe, 0xda, 0x59, 0xdc, 0xb0,
+       0x27, 0xce, 0x91, 0x8f, 0xdf, 0x8b, 0xcb, 0x09, 0x00, 0xfd, 0x5d, 0x2e,
+       0xda, 0x72, 0x16, 0x81, 0xbf, 0xe7, 0x17, 0x5d, 0x94, 0x7c, 0xc8, 0xfc,
+       0xc5, 0x37, 0x39, 0x08, 0xa5, 0xb3, 0x9e, 0xf6, 0x21, 0xd7, 0xcc, 0xa4,
+       0xcf, 0x17, 0xbc, 0x2d, 0x82, 0xb9, 0x4d, 0xd1, 0xe3, 0x96, 0x32, 0x29,
+       0xdd, 0xcc, 0xe3, 0x74, 0x7c, 0x94, 0xf8, 0x9e, 0xbe, 0x84, 0xae, 0x6f,
+       0x5e, 0x3b, 0xb3, 0xc3, 0xe7, 0x2f, 0x8f, 0x4d, 0xf7, 0x95, 0xbc, 0x7f,
+       0xa9, 0x6d, 0xa1, 0x02, 0xf2, 0x95, 0xda, 0xd1, 0x87, 0xf4, 0x71, 0xd1,
+       0x4a, 0xb2, 0x1c, 0xe9, 0xae, 0xbc, 0x29, 0xea, 0x79, 0xfb, 0x55, 0xc8,
+       0x1f, 0x95, 0x51, 0xfc, 0xe1, 0xe1, 0xfe, 0xc3, 0x2e, 0x8d, 0x3f, 0x0a,
+       0x48, 0x01, 0xca, 0x17, 0x42, 0x98, 0xff, 0xcb, 0xe5, 0xf2, 0xe5, 0x62,
+       0xde, 0x35, 0x33, 0x29, 0x1e, 0x7a, 0xf6, 0x8b, 0xc4, 0xac, 0x82, 0x3f,
+       0x2b, 0x92, 0xa5, 0xb0, 0xce, 0x4d, 0x42, 0x00, 0xe2, 0x05, 0xc4, 0x97,
+       0x8a, 0x7c, 0x56, 0x4b, 0xc2, 0x28, 0x0f, 0x35, 0x38, 0x75, 0x01, 0x1f,
+       0x0d, 0xeb, 0x5f, 0x4e, 0x75, 0x6d, 0xfb, 0x53, 0xd1, 0x3d, 0x40, 0x2f,
+       0xaf, 0xfe, 0x21, 0xff, 0x39, 0x5a, 0x76, 0xbd, 0xfa, 0xe9, 0xd0, 0x9d,
+       0x50, 0x7f, 0xed, 0xe3, 0x9c, 0x3f, 0x90, 0xbe, 0xfd, 0x27, 0xed, 0xfe,
+       0x7e, 0x36, 0xe8, 0xb3, 0x9e, 0xdd, 0x66, 0x8c, 0x8b, 0xf5, 0xec, 0xfe,
+       0x55, 0xce, 0x3d, 0x50, 0xdf, 0x61, 0xc6, 0xb8, 0x58, 0xcf, 0x12, 0xb3,
+       0x1b, 0xf8, 0xc0, 0xb7, 0xdb, 0x1e, 0x38, 0x1f, 0xda, 0x07, 0x32, 0xff,
+       0xa1, 0x61, 0xd7, 0x77, 0xf9, 0x21, 0xd4, 0xaf, 0xf7, 0x23, 0xde, 0x8e,
+       0x26, 0x31, 0xff, 0xe5, 0x64, 0xfb, 0x9f, 0x0f, 0x08, 0x29, 0x50, 0xd2,
+       0x55, 0x81, 0xfd, 0xb0, 0x3b, 0x1e, 0xf9, 0xc8, 0xbb, 0xc3, 0x8a, 0xfe,
+       0x7a, 0xcf, 0xae, 0xef, 0x8a, 0x3c, 0xb6, 0x7f, 0xde, 0x7a, 0x6a, 0x15,
+       0xe2, 0x41, 0x7a, 0xb4, 0x93, 0x99, 0x5b, 0x81, 0x7e, 0x13, 0x59, 0xfc,
+       0xd8, 0xbb, 0x73, 0xdc, 0xf3, 0x8b, 0xe9, 0xf7, 0x6b, 0x5a, 0xf7, 0x28,
+       0xf3, 0x68, 0xfb, 0xa4, 0xd7, 0xff, 0x9a, 0x0f, 0xf2, 0xb3, 0x67, 0x2b,
+       0xb3, 0x8b, 0xba, 0xe5, 0xd0, 0x1a, 0xe2, 0x22, 0xe4, 0xeb, 0xa4, 0xb2,
+       0x87, 0x64, 0x88, 0xf3, 0x01, 0x33, 0x65, 0x11, 0xf2, 0x78, 0xf2, 0x86,
+       0x2b, 0x7c, 0x79, 0xb1, 0xe0, 0xc2, 0xe0, 0xd0, 0x43, 0xe1, 0x00, 0xeb,
+       0xa2, 0x70, 0x29, 0x07, 0xb9, 0xdf, 0x1f, 0x3c, 0xe2, 0x92, 0x15, 0xa4,
+       0xf7, 0x7f, 0x3d, 0x78, 0x9c, 0x98, 0xcd, 0xe4, 0xda, 0x8f, 0x08, 0xc4,
+       0x85, 0x22, 0x70, 0x11, 0xdc, 0xec, 0xb9, 0x3d, 0x60, 0x11, 0x70, 0xfd,
+       0xec, 0xf9, 0xee, 0xef, 0xf2, 0x41, 0xee, 0x1c, 0x6f, 0x59, 0x8c, 0xf6,
+       0xca, 0xd9, 0xd6, 0x3d, 0x22, 0xf9, 0x5f, 0x95, 0x0e, 0xfe, 0xab, 0xeb,
+       0x16, 0x82, 0xe7, 0xb2, 0xee, 0xa9, 0xff, 0xb2, 0xf8, 0x66, 0xf4, 0xff,
+       0x5e, 0x92, 0x8a, 0xf3, 0x8c, 0xe6, 0x83, 0xbe, 0x74, 0xfe, 0xda, 0x4f,
+       0xb0, 0xfe, 0xb2, 0xdd, 0x85, 0xf3, 0x3d, 0x47, 0xfe, 0x2f, 0xff, 0xdf,
+       0x86, 0xf7, 0xad, 0x14, 0xef, 0x8e, 0xb3, 0xe3, 0xfd, 0xc1, 0xff, 0xb1,
+       0x78, 0x7f, 0x9b, 0xe3, 0xdd, 0xee, 0x34, 0x83, 0x3c, 0xdb, 0xf5, 0x57,
+       0x8c, 0xb3, 0x6a, 0xeb, 0x3f, 0xdb, 0xba, 0x5f, 0xf8, 0x1f, 0xba, 0x6e,
+       0xcd, 0x8e, 0xff, 0x95, 0x49, 0xfd, 0xb0, 0x80, 0xf6, 0x7f, 0x9b, 0xf8,
+       0x3f, 0x1c, 0x4a, 0xe7, 0xd9, 0x94, 0xbd, 0xef, 0x83, 0x02, 0xda, 0x3a,
+       0x51, 0x20, 0xc5, 0xb1, 0xec, 0x93, 0x8f, 0x92, 0x99, 0x1f, 0x38, 0x51,
+       0x30, 0xa1, 0xff, 0x47, 0x12, 0x05, 0xee, 0xff, 0x31, 0xbf, 0x69, 0x00,
+       0xb7, 0x23, 0x06, 0x2c, 0x2c, 0x45, 0x7b, 0x63, 0x40, 0xf6, 0xa3, 0x68,
+       0x37, 0x10, 0x49, 0x5d, 0x09, 0xfb, 0x77, 0xbf, 0xca, 0x99, 0xe7, 0x7a,
+       0x18, 0x7b, 0x8c, 0xfa, 0xc4, 0x03, 0x75, 0xe7, 0xa5, 0xbc, 0x6e, 0xf4,
+       0x1f, 0x9f, 0x13, 0x88, 0x5b, 0xa0, 0x36, 0xe8, 0x80, 0x9c, 0xab, 0xf6,
+       0x83, 0xfd, 0x9a, 0x9d, 0x2d, 0xa2, 0x7d, 0x4b, 0x4b, 0xb4, 0x6b, 0xdf,
+       0x70, 0x4c, 0x65, 0xcf, 0xab, 0x15, 0x83, 0xdf, 0x74, 0x05, 0xd1, 0xd5,
+       0xe9, 0xba, 0xa6, 0xa4, 0x18, 0xfd, 0xa2, 0xc9, 0x7c, 0xbc, 0xcb, 0xc9,
+       0xe0, 0x0f, 0x0b, 0xe8, 0xfc, 0x2f, 0xb7, 0xc8, 0xce, 0x00, 0x05, 0xd1,
+       0x15, 0x13, 0x3c, 0x12, 0xac, 0xe7, 0x8a, 0x4c, 0x81, 0xf8, 0x75, 0xfb,
+       0x47, 0x93, 0xa3, 0xfc, 0xa7, 0xad, 0xd4, 0xc6, 0xd4, 0xc7, 0xd7, 0xfe,
+       0x5e, 0xf8, 0x59, 0x52, 0x98, 0x9f, 0x39, 0x51, 0x18, 0xbc, 0xb2, 0x18,
+       0xe0, 0x37, 0x50, 0xc4, 0xf8, 0xe1, 0x59, 0xe1, 0x07, 0xc6, 0x1e, 0xc2,
+       0xab, 0x20, 0xf0, 0x30, 0xd8, 0x45, 0x92, 0x8b, 0xc1, 0x2f, 0xa9, 0xc6,
+       0x85, 0xf1, 0x57, 0xee, 0x57, 0xc3, 0x76, 0x33, 0xd8, 0x2b, 0x92, 0x6d,
+       0x69, 0x07, 0xf0, 0xad, 0x44, 0xa8, 0x5f, 0xcc, 0xe6, 0x8f, 0xfe, 0xb4,
+       0xe6, 0x17, 0xf7, 0x07, 0x67, 0xc2, 0xfd, 0x6c, 0x89, 0x7f, 0x52, 0x83,
+       0xbb, 0x94, 0x2d, 0xba, 0xad, 0xc6, 0xf1, 0x10, 0x1e, 0x1a, 0x3e, 0xfe,
+       0x5e, 0x3c, 0x68, 0xf8, 0xfb, 0x47, 0xf1, 0xf1, 0x7b, 0xc0, 0xc7, 0x98,
+       0x08, 0x3e, 0xb2, 0x4f, 0x39, 0x25, 0xe0, 0xcf, 0x49, 0xdc, 0x1f, 0x98,
+       0x7c, 0xaa, 0x43, 0xc4, 0x7a, 0xb6, 0x4b, 0xc2, 0xfd, 0x17, 0xee, 0x0f,
+       0x4c, 0xb0, 0x25, 0x4a, 0xe0, 0x0f, 0x5c, 0x2a, 0x7d, 0x20, 0x02, 0x5f,
+       0x96, 0x59, 0xb6, 0x57, 0xc2, 0x3e, 0x82, 0xc5, 0x25, 0x20, 0x5d, 0x0f,
+       0xeb, 0x32, 0xa1, 0xbf, 0x63, 0x29, 0x14, 0x10, 0xee, 0xc3, 0x1b, 0x25,
+       0xac, 0x7f, 0x60, 0x72, 0x8e, 0x01, 0x43, 0x7b, 0xfa, 0xc5, 0xaf, 0x1d,
+       0xbf, 0x9b, 0x40, 0x3c, 0xd9, 0xad, 0x30, 0xc3, 0xbb, 0x98, 0xc5, 0xf3,
+       0xff, 0xf2, 0xc3, 0x0f, 0x97, 0x14, 0x41, 0x5c, 0x85, 0xfd, 0x95, 0xd1,
+       0xff, 0x5d, 0x4d, 0xfd, 0xb1, 0xf9, 0x4d, 0x24, 0x18, 0x47, 0xe1, 0xb4,
+       0x40, 0x22, 0x3e, 0x48, 0x71, 0x58, 0x40, 0x17, 0x75, 0xc8, 0x10, 0x0f,
+       0x36, 0xd6, 0xe1, 0xef, 0xb2, 0xb4, 0xc8, 0x38, 0x67, 0xeb, 0xdf, 0x9f,
+       0x1c, 0xf9, 0x67, 0x97, 0xaf, 0x51, 0xb9, 0x75, 0xe8, 0x7c, 0x42, 0xb6,
+       0x43, 0xc9, 0x82, 0xfd, 0x92, 0xde, 0x6f, 0xfe, 0x51, 0x3b, 0x83, 0x97,
+       0xf7, 0x1d, 0x12, 0x18, 0x8c, 0xf1, 0x06, 0xb7, 0x58, 0xac, 0xdb, 0x67,
+       0xfb, 0xf7, 0x14, 0x26, 0x3f, 0x5e, 0xfb, 0xe3, 0xd6, 0xd1, 0x10, 0x3f,
+       0x9b, 0xd0, 0x93, 0x97, 0xc0, 0xe4, 0x69, 0xa1, 0x09, 0xe8, 0xd2, 0xcb,
+       0xfd, 0x82, 0x93, 0x44, 0x4d, 0x80, 0x7c, 0x85, 0x93, 0xed, 0x43, 0x12,
+       0x70, 0x1f, 0x71, 0xbf, 0x68, 0xf7, 0xc4, 0x88, 0xdb, 0x6c, 0xe4, 0xfe,
+       0xf4, 0x2f, 0xea, 0x31, 0xa8, 0x4c, 0x7a, 0x9a, 0x89, 0x5f, 0x04, 0xbf,
+       0x89, 0x84, 0x31, 0x7e, 0xeb, 0x6b, 0xb6, 0xc4, 0xdc, 0x0f, 0x9e, 0x9b,
+       0x62, 0xe2, 0x74, 0xc3, 0xf1, 0x46, 0xff, 0xc4, 0x22, 0xd8, 0xb7, 0x60,
+       0xdf, 0x5f, 0x40, 0x5f, 0x4d, 0xd0, 0xe3, 0xad, 0x6b, 0xda, 0x97, 0x52,
+       0x7e, 0x5f, 0x3c, 0xc0, 0xdf, 0x21, 0xdd, 0xfe, 0xca, 0x3f, 0x0a, 0x5f,
+       0xf0, 0xdf, 0x01, 0xbe, 0x1b, 0xad, 0xa1, 0x29, 0xc5, 0x31, 0xe4, 0xc7,
+       0x42, 0x0e, 0xbf, 0xe9, 0x7b, 0xbf, 0xc7, 0x78, 0xe7, 0x05, 0xed, 0x6b,
+       0x4d, 0x40, 0xbf, 0x17, 0x34, 0x9b, 0x0c, 0xfb, 0x93, 0xd5, 0x29, 0xdc,
+       0xef, 0x1a, 0x45, 0x46, 0xc1, 0xbc, 0xa6, 0xef, 0xb5, 0xda, 0x0b, 0x01,
+       0x2f, 0xfb, 0x45, 0x97, 0x95, 0xae, 0xcf, 0xdb, 0x7e, 0x42, 0xf1, 0xc4,
+       0xd8, 0xe7, 0x8a, 0x86, 0x27, 0x8c, 0x0f, 0x71, 0xf4, 0x97, 0x52, 0xd8,
+       0xbe, 0xc0, 0x4e, 0xb9, 0x65, 0x1e, 0xc0, 0x75, 0xe7, 0x57, 0x16, 0xe2,
+       0xa3, 0xf8, 0xdd, 0xae, 0xf8, 0xab, 0x62, 0xcd, 0x33, 0x25, 0x8d, 0xc9,
+       0xb9, 0x05, 0xa4, 0xe5, 0xce, 0xfc, 0xdc, 0x7f, 0x3d, 0xf8, 0x4e, 0xe8,
+       0xb1, 0x05, 0x27, 0x82, 0x9f, 0xd9, 0x4c, 0x78, 0x5c, 0x23, 0x9a, 0xfe,
+       0x08, 0xd2, 0xf1, 0xc9, 0x0d, 0x24, 0x00, 0xfa, 0x14, 0xfc, 0x52, 0x90,
+       0x0b, 0x27, 0x37, 0x11, 0xd4, 0xe7, 0x14, 0x24, 0x8f, 0x82, 0x5f, 0x4d,
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+       0x54, 0x90, 0x17, 0xb5, 0x4d, 0x2b, 0xa6, 0x60, 0xff, 0x66, 0x41, 0x85,
+       0xf1, 0x5b, 0xd7, 0x96, 0xa0, 0x9e, 0x2f, 0x1f, 0x2b, 0x12, 0x6c, 0x6f,
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+       0x52, 0xd1, 0xfc, 0x3e, 0x21, 0x9d, 0xd9, 0x9f, 0x5d, 0xdb, 0xe3, 0x67,
+       0xc2, 0x3a, 0x84, 0x0d, 0x7b, 0x70, 0xbf, 0xb5, 0xb2, 0xe5, 0x26, 0x19,
+       0xe8, 0xaf, 0x57, 0x7e, 0xa4, 0xcb, 0x5a, 0x3f, 0xdc, 0xc7, 0xf4, 0x51,
+       0xfa, 0x85, 0x7d, 0x76, 0x98, 0xdf, 0x8c, 0x91, 0xfa, 0xf9, 0x2d, 0x46,
+       0x3c, 0x75, 0x6d, 0x64, 0xfc, 0x5f, 0xd9, 0x26, 0x07, 0xac, 0x30, 0xbf,
+       0x0d, 0x6b, 0x31, 0x9e, 0xed, 0xdd, 0x70, 0x02, 0xf3, 0xe3, 0x27, 0xbd,
+       0xb2, 0x19, 0xe3, 0x08, 0xde, 0x36, 0xd1, 0x98, 0x17, 0xb9, 0x41, 0x0c,
+       0x9a, 0x31, 0x7f, 0x53, 0x3c, 0x68, 0x46, 0xbf, 0xc6, 0x98, 0x9f, 0x58,
+       0xdb, 0x5a, 0x83, 0xfb, 0x6e, 0xb5, 0x2d, 0x3c, 0xff, 0x2f, 0x2a, 0x2f,
+       0xae, 0xea, 0x95, 0x5d, 0xaf, 0xfa, 0x28, 0x68, 0xaa, 0x7e, 0xf9, 0xa2,
+       0x03, 0xe4, 0xc1, 0xb1, 0x8e, 0xf5, 0x0e, 0x80, 0x27, 0x1d, 0x0f, 0xf3,
+       0x0a, 0x2f, 0x3b, 0x25, 0x19, 0xf2, 0xa3, 0xfa, 0xcf, 0x07, 0x76, 0x1b,
+       0xf3, 0x0d, 0x5b, 0x1e, 0xe2, 0xf9, 0x86, 0x57, 0x77, 0x92, 0xfc, 0xbe,
+       0xf9, 0x86, 0xc7, 0xe0, 0x1f, 0xa0, 0x6f, 0xd2, 0xa3, 0xf2, 0x35, 0x37,
+       0x24, 0xf3, 0xfc, 0xee, 0x60, 0x51, 0x71, 0x8c, 0x78, 0x7e, 0xef, 0xb9,
+       0x9f, 0xcd, 0xdf, 0xac, 0x81, 0x3c, 0xf9, 0xae, 0xad, 0xc7, 0xd7, 0xc0,
+       0xfc, 0xab, 0xff, 0xf6, 0xf5, 0x1a, 0xc8, 0x6f, 0x22, 0xbb, 0xad, 0xa8,
+       0xa7, 0xbc, 0x2f, 0xfd, 0x0e, 0xf3, 0x8a, 0xb5, 0xf7, 0x16, 0xa7, 0x33,
+       0x7a, 0xeb, 0xde, 0xf8, 0x22, 0xe6, 0x65, 0x77, 0x7f, 0x6a, 0x46, 0x7f,
+       0xa7, 0x7b, 0x57, 0x67, 0x0e, 0xe4, 0xb7, 0x75, 0x6f, 0xf9, 0x3e, 0x0d,
+       0xe2, 0x73, 0x0b, 0x77, 0x5d, 0x8e, 0xf1, 0xcb, 0x85, 0xdb, 0x26, 0xa5,
+       0x93, 0x18, 0xf2, 0x5e, 0x2b, 0x81, 0x3e, 0x03, 0xe7, 0x90, 0x17, 0x1e,
+       0x8d, 0x8f, 0x7d, 0xad, 0xfb, 0x30, 0x0f, 0xeb, 0xab, 0x4f, 0xcc, 0x28,
+       0xdf, 0x7a, 0xf3, 0x47, 0x5b, 0x6a, 0x58, 0x5e, 0xae, 0xca, 0xf3, 0x46,
+       0x37, 0xc5, 0xce, 0xc3, 0xd7, 0xf2, 0x1c, 0x6b, 0x5b, 0xaf, 0xbb, 0xe6,
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+       0x81, 0x69, 0x02, 0xd8, 0x81, 0xdf, 0xe4, 0xc0, 0xf9, 0x88, 0xa3, 0x72,
+       0x18, 0xf3, 0x40, 0xc2, 0xbb, 0xcc, 0x4e, 0xc8, 0x7b, 0xac, 0xdc, 0xf5,
+       0x31, 0xf2, 0x4b, 0xf7, 0xb6, 0x0f, 0x30, 0xde, 0x4a, 0x78, 0x9e, 0x7d,
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+       0xd1, 0xb1, 0x96, 0x87, 0xda, 0x5f, 0xfe, 0x69, 0x28, 0x9d, 0x9f, 0x1f,
+       0xe6, 0xe7, 0x0e, 0x6a, 0xa8, 0xdf, 0xc4, 0xf2, 0xd4, 0x23, 0x79, 0xa9,
+       0xc2, 0x58, 0xc0, 0xd7, 0x41, 0x43, 0x5e, 0xaf, 0xb6, 0xee, 0xe8, 0xf1,
+       0x9c, 0x5c, 0x8e, 0x46, 0xf2, 0xaa, 0x63, 0xe7, 0xf9, 0x6a, 0x79, 0x84,
+       0x7d, 0xf1, 0xc5, 0xf4, 0x8a, 0x96, 0x37, 0xdd, 0xbd, 0x96, 0xe7, 0x5b,
+       0xd3, 0xe7, 0xd9, 0xa3, 0x20, 0x4f, 0x8e, 0xe9, 0x73, 0x6f, 0x40, 0xf8,
+       0x38, 0x16, 0x7e, 0xb5, 0xbc, 0xea, 0x3f, 0x44, 0xe1, 0x57, 0x5b, 0x5f,
+       0x7f, 0x7c, 0xa1, 0xf1, 0xe7, 0xd9, 0xe6, 0xfd, 0x5f, 0x85, 0xcb, 0xbb,
+       0xe9, 0x2c, 0x9e, 0xad, 0xc1, 0xa7, 0xeb, 0x2f, 0xb1, 0xe5, 0xf4, 0xb7,
+       0x9c, 0xdf, 0xa9, 0xdf, 0xfa, 0x4d, 0xba, 0xce, 0xbf, 0x9d, 0xc3, 0xfd,
+       0x56, 0x0d, 0x6e, 0xda, 0x7c, 0x97, 0xb6, 0x30, 0xbb, 0xa2, 0x6b, 0x03,
+       0xf3, 0x1f, 0xa2, 0xf9, 0x9b, 0xae, 0xc7, 0x1d, 0x2b, 0xcf, 0x5e, 0xca,
+       0x60, 0xf6, 0x6f, 0x6d, 0xdb, 0x9e, 0x7c, 0x90, 0x43, 0x5d, 0x7b, 0xb7,
+       0x73, 0xba, 0x63, 0x74, 0x5d, 0xbb, 0xe9, 0x20, 0xcb, 0xd3, 0xa5, 0x72,
+       0x3b, 0xa0, 0x97, 0xdb, 0x84, 0xc5, 0x91, 0xa3, 0xc7, 0x73, 0xf0, 0xf1,
+       0xbc, 0xed, 0xb1, 0xc7, 0xf3, 0x6e, 0x3a, 0x11, 0x73, 0xbc, 0x63, 0x92,
+       0xfb, 0x26, 0x98, 0xff, 0xb1, 0x0e, 0x66, 0x47, 0x1d, 0x6b, 0x11, 0xa7,
+       0x06, 0x62, 0x8c, 0x7f, 0x9a, 0xeb, 0xa5, 0xde, 0x75, 0xdb, 0x15, 0xcc,
+       0x97, 0x12, 0x1d, 0x71, 0x68, 0x4f, 0x2d, 0xb4, 0x8f, 0xfd, 0x24, 0x21,
+       0x05, 0x4a, 0x05, 0xf3, 0x7e, 0x1a, 0x16, 0xf3, 0x3c, 0xa1, 0xfb, 0x5c,
+       0x19, 0x00, 0xe7, 0x06, 0xfb, 0x95, 0x04, 0xe6, 0xf3, 0x00, 0xc0, 0x47,
+       0x17, 0x7f, 0x90, 0x9d, 0x1e, 0x02, 0x76, 0x9c, 0x9c, 0x51, 0x5c, 0x28,
+       0xaa, 0x91, 0xf9, 0x6a, 0xed, 0x4a, 0x8a, 0x89, 0x04, 0xf4, 0xf8, 0x97,
+       0x82, 0xd9, 0x20, 0xdf, 0x0f, 0x14, 0x74, 0xca, 0x30, 0xde, 0x67, 0x51,
+       0x71, 0x93, 0xcf, 0x24, 0xb2, 0x34, 0x9d, 0xce, 0xeb, 0x33, 0x9f, 0xe0,
+       0x5a, 0xac, 0xf6, 0x6f, 0x77, 0x6b, 0x75, 0xcf, 0xbd, 0xa2, 0x21, 0xce,
+       0x51, 0x6b, 0x0e, 0x1f, 0x00, 0xfb, 0x9d, 0xbc, 0x6e, 0xc5, 0xb8, 0xb5,
+       0xb8, 0xdb, 0xea, 0xc3, 0xb8, 0xd9, 0x1a, 0x2b, 0xae, 0x73, 0xdf, 0xb6,
+       0xef, 0x5e, 0x00, 0x78, 0x75, 0xff, 0xdc, 0x4c, 0xd8, 0x3e, 0x02, 0x25,
+       0x0c, 0x2a, 0x17, 0xca, 0x78, 0xfc, 0xa2, 0x73, 0xdb, 0x77, 0x6b, 0xfe,
+       0x0c, 0x76, 0x26, 0xbc, 0x4c, 0xbf, 0x5f, 0xb6, 0x86, 0xf6, 0x07, 0xfb,
+       0x7a, 0x53, 0x3c, 0xfa, 0x03, 0x3d, 0x5b, 0x13, 0xf2, 0xd1, 0x9e, 0x7c,
+       0xfd, 0x9e, 0xe9, 0x20, 0x37, 0xca, 0x40, 0x87, 0x81, 0x9d, 0xf7, 0x4a,
+       0x7a, 0xa0, 0x81, 0x8e, 0x77, 0x24, 0x95, 0xd5, 0x8f, 0x6c, 0x1e, 0x88,
+       0xe7, 0x09, 0xaa, 0xb6, 0xda, 0x31, 0xdf, 0x70, 0xdf, 0xb6, 0xd7, 0x6a,
+       0x41, 0xfe, 0x77, 0xbf, 0x12, 0x0f, 0xdb, 0xd1, 0xe4, 0x2b, 0x39, 0xf4,
+       0x37, 0xa8, 0x7b, 0x77, 0x26, 0x90, 0xb5, 0x2a, 0xda, 0x81, 0xaa, 0x5e,
+       0xdf, 0x56, 0x10, 0x49, 0xd5, 0xdb, 0x79, 0x55, 0x50, 0x37, 0xe4, 0xbf,
+       0x10, 0xf4, 0xd3, 0x31, 0x1e, 0x47, 0xe9, 0xb9, 0xaa, 0x2d, 0x01, 0xcf,
+       0x8f, 0xe8, 0xfa, 0x71, 0x7e, 0xf6, 0x65, 0xb1, 0xf3, 0x32, 0xc1, 0x2c,
+       0xe0, 0x3b, 0x6a, 0x4f, 0x1a, 0xbe, 0xa3, 0xb5, 0x5f, 0x9f, 0x31, 0x98,
+       0x9f, 0xef, 0x0d, 0xff, 0x84, 0xdd, 0xaf, 0xc0, 0xfa, 0x7b, 0x95, 0x70,
+       0x29, 0xab, 0xfb, 0xb3, 0x18, 0xdf, 0x76, 0x60, 0xff, 0x12, 0x8d, 0x5e,
+       0x79, 0x7b, 0xdf, 0x71, 0x59, 0xff, 0x39, 0x19, 0x83, 0x0d, 0xfd, 0xb4,
+       0xf7, 0x6b, 0xcd, 0xa4, 0x2e, 0x16, 0x1f, 0x54, 0x67, 0x08, 0xfc, 0x7c,
+       0xef, 0x5f, 0x87, 0xc5, 0xba, 0xcf, 0x22, 0xc6, 0xfc, 0xf1, 0xf9, 0x5d,
+       0x02, 0xf1, 0x99, 0xc0, 0x0e, 0xd8, 0x62, 0x0d, 0x40, 0x5c, 0xa3, 0x5a,
+       0x09, 0x0e, 0x85, 0xfc, 0xf6, 0x57, 0x15, 0xb6, 0x3f, 0x52, 0xed, 0x08,
+       0x0e, 0x85, 0xfc, 0xf6, 0x9d, 0x5c, 0xfe, 0x55, 0xc7, 0xd1, 0x3a, 0x7d,
+       0x9e, 0xc5, 0xe7, 0x01, 0xfd, 0xa1, 0x4e, 0x2c, 0xa1, 0x97, 0x01, 0xdf,
+       0x35, 0xaf, 0x59, 0x09, 0xe4, 0x27, 0xd5, 0xbc, 0x6e, 0x77, 0x03, 0x9e,
+       0x6b, 0x5e, 0xfd, 0xee, 0xc8, 0x73, 0x85, 0x90, 0xcf, 0x16, 0x8f, 0x71,
+       0xab, 0x9a, 0xd7, 0xff, 0x1d, 0xf1, 0x5f, 0x63, 0x0e, 0xce, 0x06, 0xfa,
+       0x0f, 0x6f, 0x31, 0x93, 0x75, 0xb4, 0x7f, 0xd7, 0x96, 0xb7, 0x73, 0xc0,
+       0x8e, 0xe8, 0x92, 0x83, 0x39, 0x49, 0x67, 0xd8, 0xf7, 0xa9, 0x69, 0x31,
+       0x1b, 0xf6, 0xb1, 0xb5, 0x75, 0x1c, 0xab, 0x0f, 0x9c, 0x07, 0xe7, 0xd7,
+       0xb5, 0x73, 0x8b, 0x95, 0xfd, 0xc8, 0x8b, 0x5d, 0x19, 0xcc, 0x1e, 0x5d,
+       0x91, 0xe1, 0x7e, 0x3c, 0x03, 0xf9, 0xda, 0xe6, 0x44, 0x79, 0x0d, 0xe3,
+       0x89, 0x30, 0x4e, 0xdb, 0x10, 0xfd, 0xb9, 0xe6, 0x4a, 0x35, 0xb6, 0x1c,
+       0x6b, 0xca, 0x90, 0x0d, 0xe7, 0x68, 0xc5, 0xc8, 0x39, 0xc5, 0x26, 0x18,
+       0xf7, 0x2b, 0x12, 0x5a, 0x9a, 0x45, 0x51, 0x52, 0x23, 0x84, 0x71, 0xff,
+       0xbc, 0x72, 0xc3, 0x89, 0x91, 0xe0, 0x0f, 0x7f, 0xf6, 0xb3, 0x0b, 0x71,
+       0x5f, 0xeb, 0x33, 0x25, 0x3c, 0x12, 0xe4, 0xf6, 0x67, 0x39, 0xe1, 0x91,
+       0x7a, 0x79, 0x7c, 0xb4, 0xde, 0xa2, 0x4a, 0x32, 0xc6, 0x25, 0xb0, 0xec,
+       0x59, 0x7b, 0xa2, 0x34, 0x8b, 0x40, 0xfe, 0xa0, 0x75, 0x66, 0x2c, 0xf9,
+       0xb4, 0x39, 0x23, 0x1e, 0xe7, 0x51, 0x79, 0x6f, 0x7c, 0xcc, 0xf3, 0xa0,
+       0x3b, 0x38, 0xbd, 0xad, 0x06, 0x1a, 0x4c, 0x65, 0xdf, 0x85, 0x38, 0x84,
+       0xf6, 0xdd, 0xcf, 0x94, 0x80, 0x02, 0xf3, 0xc8, 0xcb, 0x54, 0xb1, 0xbd,
+       0x32, 0x3b, 0xa0, 0xc0, 0xf3, 0xaa, 0x0d, 0xdb, 0x87, 0x18, 0xee, 0x9d,
+       0x90, 0xfc, 0xd8, 0x8f, 0xf2, 0x17, 0xc2, 0xa3, 0x82, 0xac, 0x54, 0x0a,
+       0x6d, 0x7d, 0xe5, 0x4a, 0xc5, 0x22, 0x9b, 0x2a, 0xe1, 0xf9, 0x68, 0xe9,
+       0x3f, 0x7b, 0xe9, 0x4d, 0x8c, 0xe0, 0x09, 0x83, 0x9c, 0x90, 0xa7, 0xc6,
+       0x71, 0x48, 0x35, 0x13, 0xc6, 0x41, 0xb5, 0xf3, 0x00, 0x92, 0x5c, 0x6c,
+       0x01, 0x78, 0x29, 0xa4, 0xd8, 0x29, 0x89, 0x80, 0x6a, 0x3f, 0xf2, 0x69,
+       0x1c, 0x69, 0xc1, 0xd2, 0x46, 0xcd, 0x11, 0xa6, 0x87, 0xea, 0x08, 0xe4,
+       0x15, 0x1d, 0xe5, 0xfb, 0xb7, 0x66, 0x49, 0x7d, 0x1c, 0xe4, 0x87, 0x79,
+       0xbf, 0x88, 0xf2, 0xfc, 0x6c, 0x70, 0xfb, 0x55, 0x86, 0x03, 0xe7, 0x6d,
+       0x96, 0xea, 0x88, 0x0b, 0xed, 0x8e, 0x69, 0x4e, 0xb0, 0xab, 0x05, 0x9f,
+       0x87, 0xfc, 0x40, 0xe9, 0xa1, 0xa1, 0x7e, 0xc3, 0x90, 0xc3, 0x6c, 0xff,
+       0xdf, 0x0d, 0xf9, 0x70, 0x0e, 0xc2, 0xe6, 0xe7, 0x70, 0xbe, 0xf5, 0x3d,
+       0xd8, 0x07, 0x94, 0xce, 0xd0, 0xcf, 0xf6, 0x5d, 0x46, 0x02, 0x0d, 0xf4,
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+       0x78, 0x20, 0xbe, 0x3d, 0x28, 0x7f, 0x6c, 0x24, 0xf2, 0x17, 0xa6, 0xf5,
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+       0x30, 0xd2, 0x0e, 0xf9, 0xe2, 0xa2, 0x2e, 0x5f, 0x80, 0x40, 0xf4, 0x5d,
+       0x77, 0xfe, 0x9b, 0x14, 0xaa, 0x68, 0x97, 0x6a, 0xf7, 0x9e, 0x51, 0xbf,
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+       0x5e, 0x90, 0x05, 0x59, 0x97, 0x2f, 0x07, 0x39, 0xb0, 0x20, 0xcb, 0xfd,
+       0x14, 0xe2, 0xc9, 0xc6, 0xee, 0x29, 0xed, 0x9f, 0x1f, 0xd8, 0xf7, 0x8f,
+       0xc0, 0x26, 0x33, 0xec, 0x63, 0x3d, 0xcb, 0xef, 0x47, 0x91, 0x3c, 0x8e,
+       0x19, 0x86, 0x7d, 0x36, 0xb6, 0x8f, 0x75, 0x84, 0xc7, 0x59, 0x88, 0xa5,
+       0x9f, 0xf6, 0x38, 0xde, 0xae, 0xf6, 0xd3, 0xee, 0x60, 0xf9, 0x22, 0xc4,
+       0x19, 0xbb, 0x5d, 0xf3, 0x33, 0xe2, 0x23, 0x7e, 0x46, 0x0b, 0xac, 0xa3,
+       0xa6, 0xf1, 0xf8, 0xd2, 0x4f, 0x11, 0x5e, 0xdc, 0xcf, 0xe0, 0xf3, 0x3e,
+       0x2a, 0xb3, 0x79, 0x1f, 0x7d, 0xc1, 0x1c, 0x58, 0x12, 0x83, 0xfe, 0x8f,
+       0xf2, 0xfc, 0x94, 0x0a, 0x81, 0xc1, 0x57, 0xe3, 0x83, 0xa3, 0xbd, 0xf6,
+       0x91, 0x07, 0xef, 0xc3, 0x89, 0xa6, 0x53, 0x61, 0xdd, 0x88, 0x67, 0xc6,
+       0xd1, 0x71, 0xbf, 0xde, 0x2f, 0xa3, 0xde, 0xa8, 0xa6, 0xf4, 0x85, 0x74,
+       0xb5, 0x6e, 0x1c, 0xe6, 0xc7, 0x0b, 0x4f, 0x8c, 0x7b, 0x1c, 0xf2, 0x86,
+       0x4f, 0xbd, 0x23, 0x62, 0x7b, 0xe5, 0x69, 0x2b, 0xb6, 0x77, 0xdd, 0xe7,
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+       0x97, 0x27, 0xb0, 0x38, 0x91, 0x31, 0x8e, 0x7d, 0xdb, 0x00, 0x26, 0x17,
+       0x0e, 0x71, 0xf9, 0x50, 0x7a, 0xfa, 0x11, 0xa4, 0xdf, 0x5e, 0x3a, 0xf1,
+       0x2f, 0x50, 0x80, 0xff, 0x4a, 0x4f, 0x3f, 0xc6, 0xe8, 0x7b, 0x83, 0x80,
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+       0xde, 0xaf, 0xb8, 0x7a, 0x09, 0xc0, 0xfb, 0x12, 0x3f, 0xee, 0x93, 0x94,
+       0xad, 0x37, 0xbb, 0xc0, 0x1e, 0x88, 0xc6, 0xf3, 0xa1, 0x2c, 0xd5, 0x10,
+       0xf7, 0x28, 0x0b, 0x2d, 0xc7, 0x71, 0x09, 0xb5, 0xbf, 0x52, 0x74, 0xfb,
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+       0x5f, 0x4e, 0xdc, 0x54, 0xbe, 0x95, 0x2b, 0xac, 0x5f, 0xa9, 0xff, 0x2e,
+       0x05, 0xe4, 0x4e, 0x69, 0x53, 0x62, 0x92, 0xa0, 0x5b, 0x57, 0x59, 0x63,
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+       0x29, 0x3f, 0xc2, 0x7e, 0x7f, 0xa7, 0xff, 0x2e, 0x47, 0xac, 0xfc, 0xa2,
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+       0x2f, 0x65, 0x5f, 0x0e, 0xe4, 0x95, 0xf9, 0x56, 0x58, 0xd1, 0x1f, 0x39,
+       0xba, 0xee, 0x91, 0x1c, 0x3d, 0x9c, 0x17, 0x64, 0x4d, 0xb8, 0x0d, 0xf0,
+       0x42, 0x9a, 0x53, 0xcf, 0x49, 0x7f, 0xf8, 0x26, 0xba, 0xf6, 0x83, 0x7f,
+       0xe9, 0x7b, 0x42, 0xc6, 0x78, 0xda, 0x96, 0x2c, 0x4f, 0x19, 0xbc, 0x5f,
+       0xce, 0xfd, 0xf0, 0xfb, 0x13, 0xa7, 0x0c, 0x8d, 0x65, 0x1f, 0x3c, 0x50,
+       0xbf, 0x7f, 0x04, 0xc4, 0xe9, 0x1a, 0xea, 0x3b, 0xb0, 0x94, 0xb9, 0x7d,
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+       0xd4, 0x9f, 0x27, 0x26, 0xcc, 0x7e, 0xfa, 0x4f, 0xc2, 0xe2, 0x35, 0xda,
+       0x7b, 0x8a, 0xec, 0x71, 0x42, 0xfc, 0x54, 0xe1, 0xe7, 0x9d, 0x65, 0xc9,
+       0xb3, 0x2c, 0xb7, 0x10, 0xe2, 0x1e, 0x29, 0x05, 0x3e, 0x1d, 0xfc, 0x96,
+       0x0e, 0x60, 0xe7, 0x91, 0x96, 0x67, 0xec, 0x75, 0xc2, 0xb9, 0x62, 0x33,
+       0x1d, 0x1f, 0xe2, 0x39, 0x96, 0x6c, 0xe9, 0xa4, 0x71, 0x9f, 0x93, 0xd5,
+       0x0b, 0x84, 0x4f, 0x45, 0xc8, 0x6f, 0x96, 0x53, 0x5a, 0x08, 0xc6, 0x43,
+       0xf3, 0xe8, 0x73, 0x1d, 0xbc, 0x95, 0x94, 0x0e, 0x43, 0x7c, 0x3a, 0x1a,
+       0x0e, 0x92, 0xc5, 0x81, 0xfb, 0x4d, 0x12, 0x61, 0xf6, 0x9c, 0xb6, 0x7e,
+       0xfa, 0x04, 0xf5, 0xd2, 0x83, 0x5c, 0x2f, 0xad, 0xe4, 0x71, 0xcd, 0xa7,
+       0xeb, 0x5b, 0x30, 0xee, 0xbf, 0x24, 0xde, 0x81, 0xfa, 0x6f, 0xe9, 0x20,
+       0x13, 0xf3, 0xa7, 0x2c, 0x12, 0xde, 0x57, 0x63, 0x4e, 0x64, 0xfd, 0x95,
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+       0xdc, 0xdf, 0x6b, 0xa6, 0x74, 0x29, 0xe9, 0xf6, 0x55, 0xce, 0x93, 0xdc,
+       0x26, 0xa0, 0x9b, 0xf3, 0xfd, 0xf4, 0xb9, 0x7e, 0x9e, 0x31, 0xe2, 0x71,
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+       0xd5, 0x13, 0x89, 0xf6, 0x87, 0xfe, 0xd7, 0xa7, 0xbd, 0xf6, 0xe8, 0xfd,
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+       0xe6, 0xc7, 0x69, 0xf3, 0x98, 0xd5, 0xfe, 0x60, 0x07, 0xd8, 0xa9, 0xb3,
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+       0xfe, 0xdd, 0x1b, 0x72, 0x3c, 0x2d, 0xb7, 0x7d, 0xb8, 0x0e, 0xcf, 0x33,
+       0x7f, 0xc1, 0xe5, 0xe9, 0x6c, 0x12, 0xc6, 0x7b, 0xe1, 0x3d, 0xc4, 0xc9,
+       0xf7, 0xd9, 0x03, 0xf8, 0x7c, 0x2e, 0x71, 0xf1, 0x7a, 0x8b, 0x0c, 0x7e,
+       0xfd, 0xad, 0xc1, 0xc0, 0x0d, 0x57, 0xd3, 0xda, 0x6d, 0x6f, 0x04, 0xae,
+       0x06, 0xb3, 0x6d, 0xf6, 0xfe, 0xf0, 0x9b, 0x20, 0x06, 0x3c, 0x2d, 0xce,
+       0x29, 0xb8, 0x87, 0xa0, 0xbd, 0xd7, 0xe6, 0x7a, 0x8b, 0xd5, 0xd9, 0x7b,
+       0xbd, 0xeb, 0x97, 0x2c, 0xb8, 0x9e, 0xc8, 0x7a, 0x2d, 0xb8, 0x7e, 0x6d,
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+       0x88, 0x73, 0xe9, 0xba, 0x29, 0xbd, 0xcc, 0x4a, 0xb8, 0xf1, 0x4a, 0x72,
+       0x06, 0xbb, 0x7c, 0x96, 0x6d, 0xf8, 0x17, 0x6c, 0xd3, 0x84, 0xcd, 0x27,
+       0x1a, 0x3e, 0xa7, 0xa0, 0x89, 0xda, 0x8f, 0x5d, 0x03, 0xdc, 0x24, 0x9b,
+       0xe2, 0xef, 0x0f, 0x03, 0xdc, 0x02, 0x94, 0xd5, 0x96, 0x70, 0x8e, 0x34,
+       0x18, 0xf9, 0x44, 0x86, 0x7a, 0xad, 0xe8, 0x19, 0x04, 0xa9, 0xcf, 0x5f,
+       0x0d, 0xf4, 0x0c, 0x4b, 0x05, 0x38, 0x74, 0x24, 0x9f, 0x93, 0xfc, 0x3c,
+       0x60, 0x65, 0xfc, 0x7f, 0x00, 0xe8, 0x19, 0xf2, 0xbc, 0x4e, 0xa7, 0xe0,
+       0xba, 0xb4, 0x7b, 0xe8, 0xf7, 0xdd, 0xdd, 0x69, 0x07, 0xbb, 0x73, 0xe9,
+       0xb6, 0x8f, 0xf1, 0x9e, 0xe5, 0x1a, 0x31, 0xf4, 0xe8, 0x4d, 0x18, 0x0f,
+       0x15, 0xd1, 0x6f, 0x3a, 0xd9, 0x3a, 0xec, 0x8c, 0xe7, 0xcf, 0x0e, 0x40,
+       0x9c, 0x8a, 0xea, 0xbf, 0x81, 0xd9, 0xda, 0x39, 0x4b, 0xb6, 0xce, 0x39,
+       0x12, 0xe3, 0x93, 0x39, 0xad, 0xf1, 0x98, 0x8f, 0x3f, 0x67, 0x91, 0x68,
+       0xb8, 0x47, 0x7a, 0xce, 0x22, 0x96, 0xcf, 0x47, 0xa4, 0x8e, 0xfc, 0xeb,
+       0x0d, 0xf6, 0xfa, 0xfd, 0xfd, 0x8e, 0x03, 0xf1, 0x82, 0xe8, 0x71, 0xe6,
+       0x2d, 0x9a, 0x44, 0x3e, 0x1f, 0x0d, 0xfb, 0xb4, 0xce, 0x09, 0x18, 0x3f,
+       0x58, 0xc3, 0xe8, 0x6b, 0xde, 0x64, 0xb7, 0x08, 0xf9, 0xce, 0xe3, 0x97,
+       0x09, 0xb8, 0xdf, 0x3a, 0xee, 0xb0, 0xda, 0x16, 0xa2, 0xf5, 0x79, 0x81,
+       0x44, 0x17, 0xb0, 0xe7, 0xbc, 0xbb, 0xff, 0x63, 0x08, 0xdc, 0x73, 0x50,
+       0xdb, 0xc1, 0xe2, 0x81, 0xe9, 0xe2, 0xed, 0x05, 0xf7, 0x41, 0x9c, 0x65,
+       0x2f, 0xd3, 0xe3, 0x50, 0xbf, 0x1d, 0xe8, 0xc4, 0xe6, 0x56, 0x6d, 0xba,
+       0xfd, 0x82, 0x2e, 0xb9, 0xae, 0x00, 0xee, 0xfb, 0xf3, 0xdd, 0x66, 0x73,
+       0x03, 0xff, 0x97, 0x5c, 0xef, 0xfe, 0x14, 0xef, 0xf3, 0xe5, 0xf1, 0x0a,
+       0x4d, 0xaf, 0xbe, 0xd6, 0x58, 0x82, 0x79, 0xb2, 0x25, 0xb7, 0xaa, 0x63,
+       0x01, 0xff, 0x25, 0x2d, 0x56, 0x37, 0x96, 0x16, 0x22, 0xc5, 0x51, 0x39,
+       0x56, 0x22, 0x11, 0x0b, 0x94, 0xe9, 0x0a, 0x91, 0xac, 0x50, 0xc6, 0x11,
+       0x0b, 0x94, 0x45, 0x4b, 0xd8, 0xbd, 0xdd, 0xa5, 0x8d, 0x33, 0xd0, 0x3e,
+       0x70, 0x8c, 0x2d, 0x56, 0xe0, 0x3e, 0xde, 0x92, 0xf6, 0x17, 0xbf, 0x81,
+       0xf7, 0xcb, 0xa4, 0xe0, 0x1e, 0x76, 0x3f, 0x05, 0x83, 0x4f, 0x49, 0xfb,
+       0xdb, 0xdf, 0x03, 0x5e, 0x17, 0xb8, 0x8b, 0x31, 0x9f, 0xf1, 0xc2, 0x0d,
+       0x8a, 0xc1, 0x0f, 0x1c, 0xd9, 0x62, 0xac, 0x5f, 0xd4, 0x66, 0xac, 0x17,
+       0x04, 0x8d, 0xf5, 0xd1, 0xfb, 0x8d, 0xf5, 0xf5, 0xd9, 0x04, 0xe9, 0x68,
+       0xae, 0xe5, 0xba, 0x3c, 0x80, 0xd7, 0xde, 0x5d, 0x66, 0xaa, 0x8b, 0x20,
+       0xff, 0xcf, 0x8c, 0xf9, 0x2e, 0x87, 0x04, 0x86, 0x1f, 0xdf, 0x46, 0x2b,
+       0xca, 0xc3, 0x49, 0x55, 0xed, 0x45, 0xe0, 0x07, 0x1f, 0x7f, 0xd9, 0x6e,
+       0x02, 0x3f, 0x7a, 0xe7, 0x5f, 0x7f, 0x89, 0xfb, 0xe1, 0xe1, 0xcd, 0xf1,
+       0x04, 0xf2, 0xac, 0xf6, 0xfc, 0x3e, 0x8e, 0xc4, 0x41, 0xbe, 0xe2, 0x2b,
+       0xd6, 0x75, 0xd0, 0x5e, 0x45, 0x71, 0x07, 0xf1, 0xcb, 0xaa, 0x57, 0xac,
+       0x6b, 0xc1, 0x0f, 0x7f, 0xf5, 0x02, 0xcd, 0x8f, 0x0f, 0xe4, 0xc3, 0x7a,
+       0x5e, 0xfd, 0x1b, 0xcb, 0xaf, 0x09, 0x6f, 0x34, 0x07, 0x60, 0x7f, 0xfc,
+       0xf8, 0xf6, 0x17, 0x5f, 0x86, 0xfd, 0xb4, 0xe3, 0x1b, 0x07, 0xa0, 0x7d,
+       0x75, 0x48, 0xf0, 0x99, 0xe2, 0xe0, 0xfb, 0x5f, 0xb2, 0xf8, 0x67, 0x88,
+       0xdf, 0x17, 0x17, 0xe2, 0xf7, 0xc5, 0x55, 0x6d, 0x30, 0xfa, 0xc5, 0x77,
+       0x64, 0x33, 0x39, 0x13, 0x5a, 0x72, 0x71, 0x42, 0x2c, 0xbb, 0x49, 0x2b,
+       0x87, 0x67, 0x24, 0xe7, 0x4d, 0xa6, 0x73, 0xeb, 0x79, 0xc8, 0x3c, 0x07,
+       0xe2, 0x40, 0xc3, 0x1a, 0x8d, 0x70, 0xd1, 0xfa, 0x8d, 0x08, 0x18, 0x9f,
+       0xdf, 0xc3, 0xc7, 0x1f, 0x4f, 0x94, 0x08, 0x9d, 0xe6, 0x42, 0x9e, 0x40,
+       0xa0, 0xc1, 0x01, 0xfa, 0xf7, 0xf9, 0xd8, 0xf7, 0x24, 0x2f, 0xe1, 0xfc,
+       0xf3, 0xd2, 0x4b, 0xbd, 0xef, 0x89, 0xfc, 0x9e, 0x38, 0xa2, 0xea, 0xce,
+       0x4d, 0x45, 0xe4, 0x37, 0x59, 0x38, 0x00, 0xf2, 0x37, 0x00, 0xfe, 0x83,
+       0x23, 0xcf, 0xab, 0x88, 0x6e, 0x3e, 0x3a, 0xfb, 0x64, 0x2a, 0x1f, 0xff,
+       0x6b, 0x0b, 0xcb, 0x67, 0x4e, 0xe1, 0xf7, 0xf7, 0x1f, 0xab, 0xdf, 0x8f,
+       0x7a, 0xbf, 0xd7, 0xee, 0xab, 0x77, 0xbb, 0x27, 0xeb, 0xea, 0xa5, 0x8d,
+       0x7b, 0xd2, 0x4a, 0xc0, 0x7f, 0x6a, 0xda, 0x93, 0x36, 0x57, 0x07, 0xaf,
+       0xea, 0x8d, 0xfb, 0xd2, 0x6e, 0xc1, 0xbc, 0x27, 0x09, 0x22, 0xb8, 0xa4,
+       0x7a, 0xd6, 0x0b, 0x8f, 0x41, 0xbc, 0xa2, 0x7a, 0xa3, 0xd8, 0x02, 0xf3,
+       0x84, 0x76, 0x80, 0x5b, 0x57, 0xcb, 0x9b, 0x0e, 0xe8, 0x47, 0xed, 0xe1,
+       0x51, 0x10, 0x07, 0x89, 0xd8, 0xa3, 0x97, 0xbb, 0x27, 0xeb, 0xf8, 0xf8,
+       0xef, 0xa5, 0x5b, 0x8d, 0xdf, 0xaa, 0xb9, 0xfd, 0xf2, 0xda, 0xd8, 0x8e,
+       0x29, 0x90, 0xa7, 0x5e, 0xd5, 0x28, 0xb8, 0xa0, 0x5b, 0x55, 0xcb, 0x0d,
+       0xd7, 0x5d, 0x0d, 0xf0, 0x6e, 0x62, 0xe7, 0x5c, 0x8b, 0x24, 0x52, 0x2c,
+       0x52, 0xfe, 0xaa, 0xde, 0x72, 0xc3, 0x55, 0x23, 0x21, 0x6f, 0x66, 0xf5,
+       0x18, 0x17, 0xcc, 0x87, 0x0e, 0x71, 0x3d, 0x3c, 0xaf, 0xda, 0x74, 0x02,
+       0xcf, 0x33, 0x3c, 0x1c, 0xf5, 0xbb, 0x07, 0x5a, 0xb9, 0x23, 0x9b, 0xd9,
+       0x85, 0xb4, 0x7f, 0xd0, 0x44, 0xfb, 0x3f, 0x7c, 0xa3, 0xad, 0x1c, 0xe4,
+       0x17, 0x1d, 0xf7, 0x0d, 0xa8, 0xef, 0x1d, 0xbe, 0x0e, 0xef, 0x57, 0x71,
+       0x1c, 0x65, 0xfb, 0x0f, 0xf4, 0xf9, 0x27, 0x26, 0x6a, 0xb7, 0x1c, 0x9d,
+       0xe8, 0x7b, 0xef, 0x16, 0xfa, 0xea, 0x71, 0xd2, 0xf2, 0xd1, 0xd5, 0x10,
+       0x57, 0x6a, 0x34, 0xd2, 0x23, 0xa5, 0x6f, 0x01, 0xec, 0xb2, 0xf0, 0x7a,
+       0xc1, 0xb5, 0x0e, 0x9f, 0x2e, 0x29, 0xba, 0x16, 0x4c, 0x6e, 0xf7, 0x62,
+       0xcc, 0xf7, 0xa5, 0xed, 0x73, 0x62, 0x9d, 0xb7, 0xae, 0x08, 0x18, 0xc7,
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+       0xa6, 0xb6, 0x7d, 0x61, 0x1e, 0x7b, 0xff, 0x8f, 0x03, 0xbf, 0x7a, 0x6f,
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+       0x51, 0x75, 0x1b, 0xad, 0x8f, 0xd4, 0xd5, 0x9d, 0x51, 0xed, 0x29, 0x51,
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+       0x84, 0x74, 0x0e, 0x3c, 0x31, 0x5d, 0x1a, 0x07, 0xfb, 0xd8, 0xc1, 0xd9,
+       0x70, 0xa3, 0xc0, 0xf2, 0x86, 0xaf, 0xa7, 0x4f, 0xa6, 0xf5, 0x9a, 0xc2,
+       0x0e, 0xcc, 0x9f, 0xa9, 0x6d, 0x17, 0x5c, 0xb8, 0xad, 0xaf, 0xe5, 0xc7,
+       0xbb, 0x98, 0x9d, 0x65, 0x73, 0x85, 0xf0, 0xf7, 0xec, 0xe2, 0x0b, 0x3b,
+       0xde, 0x02, 0x39, 0x50, 0xdd, 0x26, 0x38, 0x05, 0x4a, 0xef, 0xb6, 0x96,
+       0x2d, 0x98, 0x57, 0x53, 0x0d, 0xef, 0xa9, 0xba, 0xf7, 0x5a, 0x98, 0xdf,
+       0x59, 0xdd, 0x72, 0x10, 0xdf, 0xeb, 0x77, 0xfc, 0xe1, 0x26, 0xe4, 0xe7,
+       0x87, 0x87, 0x1f, 0xc2, 0x7e, 0xda, 0xfe, 0xd1, 0x4d, 0xa4, 0xf7, 0xf7,
+       0x3a, 0x4e, 0x0f, 0x04, 0x3c, 0xb6, 0x74, 0x32, 0x3d, 0x1c, 0xb5, 0x7f,
+       0xd4, 0x9d, 0xe9, 0xde, 0x87, 0xf2, 0x30, 0xea, 0xfc, 0xab, 0x17, 0xc6,
+       0xb5, 0x45, 0xe8, 0x5e, 0xeb, 0xff, 0x87, 0x91, 0xed, 0xbf, 0x83, 0x61,
+       0xe2, 0x17, 0x9e, 0x58, 0x2c, 0xd1, 0xfe, 0x7f, 0xaa, 0xe9, 0x1c, 0x03,
+       0xf6, 0x12, 0xdc, 0x71, 0x09, 0x72, 0xff, 0x69, 0x21, 0x30, 0x02, 0xf4,
+       0xf3, 0xb3, 0xc4, 0x33, 0x02, 0xf4, 0xd1, 0x6d, 0x35, 0xe7, 0xef, 0x31,
+       0xd1, 0x7e, 0x07, 0xe4, 0xd0, 0x6a, 0xb8, 0xaa, 0x61, 0x68, 0x8e, 0xf5,
+       0x1a, 0x89, 0xca, 0xe9, 0x03, 0xf6, 0xd0, 0x40, 0x81, 0xca, 0x92, 0xe1,
+       0x6b, 0x92, 0xaf, 0x01, 0x78, 0x1e, 0x48, 0x0d, 0xe1, 0x0d, 0x0d, 0x3f,
+       0x5b, 0x93, 0xc2, 0xda, 0x07, 0x86, 0x06, 0xc2, 0xbe, 0x6b, 0x5e, 0xce,
+       0x8f, 0x59, 0xfd, 0xfc, 0xd0, 0x6a, 0xa8, 0x5f, 0xbf, 0xe6, 0x02, 0x56,
+       0x1f, 0x19, 0x1a, 0x28, 0xd2, 0xf7, 0x07, 0xfb, 0x2e, 0xbc, 0x06, 0xe0,
+       0xbf, 0xde, 0x19, 0x9b, 0x6f, 0x07, 0xe6, 0x30, 0x79, 0xae, 0xcd, 0x6f,
+       0x66, 0x81, 0x3b, 0x23, 0x07, 0xec, 0xcd, 0x6a, 0xa6, 0x2f, 0xe0, 0xf8,
+       0xa5, 0x85, 0xca, 0xc5, 0xd9, 0x95, 0xc7, 0x36, 0xaf, 0xa7, 0x70, 0x98,
+       0xfd, 0xd3, 0x78, 0x94, 0x57, 0xeb, 0xbb, 0xae, 0xbb, 0xb2, 0x18, 0xd7,
+       0xef, 0x2b, 0x86, 0x3c, 0x37, 0x76, 0xc5, 0x3b, 0xd7, 0x67, 0x28, 0x97,
+       0x25, 0xb4, 0x03, 0x32, 0x41, 0x87, 0x25, 0x45, 0xf0, 0x61, 0xcf, 0xe9,
+       0x50, 0x51, 0xde, 0x5f, 0x50, 0xb7, 0x05, 0xf4, 0x7e, 0xfa, 0xec, 0x3c,
+       0x94, 0xf7, 0xa7, 0xb2, 0xdd, 0xf5, 0x39, 0x63, 0x22, 0xe5, 0x9f, 0x87,
+       0xb0, 0xb2, 0x3e, 0x87, 0x9d, 0xf7, 0x48, 0x17, 0x4d, 0x98, 0x6f, 0x90,
+       0x7e, 0x8f, 0x1d, 0xed, 0xa0, 0xc7, 0xf9, 0x7e, 0x12, 0xe5, 0x1b, 0xc4,
+       0xaf, 0x8d, 0xe3, 0x63, 0x54, 0x0e, 0x93, 0x7f, 0xa3, 0x72, 0x98, 0x9f,
+       0x94, 0x35, 0xf0, 0xf2, 0x7a, 0x58, 0xcf, 0xcd, 0xdc, 0x3e, 0x5d, 0xf9,
+       0x50, 0x60, 0xa3, 0x95, 0xc2, 0xff, 0xf7, 0x40, 0x24, 0x29, 0x18, 0xdf,
+       0x46, 0x7b, 0xf7, 0x96, 0xb5, 0x54, 0x6e, 0x24, 0x40, 0x3e, 0x85, 0x3b,
+       0x13, 0xe4, 0xc1, 0x2d, 0x10, 0xff, 0xcd, 0x8b, 0xd4, 0x35, 0xfb, 0x7d,
+       0x65, 0x01, 0xad, 0xdb, 0x22, 0x7e, 0xda, 0xca, 0x19, 0xee, 0x4c, 0x7d,
+       0x1e, 0xd0, 0xca, 0xb5, 0xac, 0x5d, 0x93, 0x37, 0x2b, 0x73, 0xd9, 0xfb,
+       0x9a, 0xde, 0x49, 0x6f, 0x60, 0xf0, 0x49, 0x7f, 0x7c, 0xc4, 0x3a, 0x58,
+       0x47, 0xbc, 0x44, 0xf0, 0xfc, 0xc5, 0x82, 0x99, 0x43, 0xd7, 0x2d, 0x46,
+       0xfd, 0x7d, 0x2d, 0xae, 0x9b, 0xb8, 0xdd, 0x99, 0xe0, 0x7f, 0x1f, 0xae,
+       0x18, 0x6c, 0x02, 0xbb, 0x52, 0xc3, 0xcf, 0xa2, 0x02, 0xf7, 0x34, 0x5c,
+       0x8f, 0xc8, 0xf2, 0xd5, 0x35, 0x3c, 0x69, 0xdf, 0xaf, 0xe7, 0xeb, 0x9e,
+       0x27, 0x52, 0xfd, 0x4f, 0xd7, 0x59, 0x3f, 0xc8, 0x83, 0xeb, 0xa7, 0xf6,
+       0x40, 0x3e, 0x4b, 0x2e, 0x60, 0xf6, 0x40, 0x3d, 0x04, 0x62, 0x53, 0x23,
+       0xf0, 0x25, 0x52, 0x68, 0x0c, 0x3c, 0xff, 0x5f, 0x04, 0xa7, 0xdb, 0xa1,
+       0xfd, 0x1f, 0x85, 0x53, 0x0c, 0x79, 0xf1, 0x33, 0xe8, 0x57, 0xb3, 0x88,
+       0xca, 0x0b, 0x93, 0x4e, 0x5e, 0x70, 0xf8, 0x3d, 0x2d, 0x04, 0xe5, 0xf4,
+       0x42, 0xdd, 0xfd, 0x25, 0xf4, 0x39, 0xf8, 0x81, 0x37, 0x0d, 0xf4, 0x3c,
+       0x90, 0xa3, 0xdb, 0xc7, 0x99, 0x7d, 0x4f, 0x0d, 0xda, 0x7f, 0xda, 0xbc,
+       0xe2, 0xff, 0xfd, 0xb5, 0xa9, 0x37, 0x91, 0xbe, 0x7c, 0x16, 0x6d, 0x9f,
+       0x1d, 0xf8, 0xbd, 0x65, 0x39, 0xc6, 0x01, 0x95, 0x16, 0x94, 0x8b, 0x07,
+       0xae, 0x24, 0xae, 0xc5, 0x20, 0x3f, 0xf8, 0xbe, 0xac, 0x66, 0x5f, 0x16,
+       0xfd, 0xb4, 0xea, 0x1d, 0xf0, 0xa3, 0x4e, 0xe6, 0x88, 0xf8, 0x9e, 0x55,
+       0xc3, 0xab, 0x50, 0xbc, 0xa5, 0x94, 0xc2, 0xe9, 0x21, 0xaa, 0x56, 0xe1,
+       0x3c, 0xba, 0x6f, 0x06, 0xcb, 0xef, 0xd1, 0xf4, 0xe6, 0x4a, 0x7e, 0xef,
+       0xee, 0xca, 0xbb, 0x2f, 0xc4, 0x3c, 0xbf, 0x1e, 0x12, 0xc2, 0xdf, 0x65,
+       0xf3, 0x8d, 0x25, 0x28, 0xff, 0x7a, 0xdb, 0x67, 0x0d, 0xc5, 0x76, 0x8a,
+       0x6f, 0x9f, 0x15, 0xf8, 0xbd, 0x22, 0x0e, 0x7f, 0x77, 0x60, 0x65, 0x01,
+       0xc1, 0x73, 0x36, 0x2b, 0x67, 0x5d, 0x80, 0xed, 0x3b, 0xb5, 0xb8, 0xd2,
+       0x2c, 0x0b, 0x7e, 0x67, 0xe5, 0x0c, 0x46, 0x4f, 0x2b, 0x2b, 0x58, 0x1e,
+       0x26, 0xe8, 0x11, 0x80, 0x5b, 0x7f, 0xf4, 0x90, 0xd6, 0xc0, 0xe2, 0x1b,
+       0x44, 0x72, 0xe7, 0xeb, 0xf3, 0x01, 0xde, 0xe5, 0xf8, 0x8b, 0x2f, 0x0c,
+       0x6d, 0xfb, 0x18, 0xec, 0xca, 0xe5, 0x56, 0xb4, 0x2b, 0x41, 0x77, 0xe2,
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+       0x47, 0x3d, 0x99, 0xc9, 0xee, 0x9b, 0x25, 0x2e, 0xf4, 0xcf, 0x1f, 0xb4,
+       0xbb, 0x4b, 0x50, 0x5e, 0xdd, 0x17, 0xaf, 0xc2, 0xfc, 0x9b, 0xac, 0x64,
+       0x99, 0x65, 0x14, 0xb8, 0x23, 0xe4, 0x7e, 0x94, 0x7b, 0x7c, 0x3e, 0xc4,
+       0xff, 0x0c, 0xe6, 0x79, 0xcc, 0xe1, 0xf6, 0xda, 0x67, 0xe5, 0x27, 0xed,
+       0x60, 0x0f, 0xbc, 0xc1, 0xe5, 0x0d, 0x10, 0x0c, 0xf8, 0xcb, 0x73, 0x09,
+       0x6b, 0x9f, 0x7b, 0x6f, 0xfc, 0x41, 0xf0, 0x6f, 0xe6, 0xde, 0xcb, 0xee,
+       0x9b, 0x25, 0xcb, 0x2e, 0x77, 0x1b, 0xf7, 0x3b, 0xe8, 0x5c, 0xd3, 0x20,
+       0x3e, 0xce, 0xff, 0x1a, 0xc3, 0x76, 0x80, 0x83, 0x07, 0xde, 0x73, 0xc0,
+       0xf8, 0xff, 0x69, 0x87, 0xfb, 0x4c, 0x3c, 0xf7, 0xb2, 0xf3, 0xbd, 0xc4,
+       0x47, 0xdf, 0xd7, 0xe5, 0x43, 0x7f, 0x0c, 0xfc, 0x0b, 0x71, 0x76, 0x91,
+       0xcd, 0x9f, 0xd4, 0xc7, 0xab, 0xb1, 0xee, 0x05, 0xfd, 0x98, 0xcb, 0x77,
+       0x3a, 0x7f, 0xb7, 0xfe, 0x7b, 0xda, 0x77, 0xa2, 0xc7, 0xa5, 0xfe, 0xdd,
+       0x27, 0x40, 0xa7, 0x14, 0xee, 0x41, 0x38, 0x07, 0x16, 0xbe, 0x4f, 0xe4,
+       0xbf, 0xd7, 0x6a, 0x9c, 0x6f, 0x8a, 0x12, 0x7e, 0xd4, 0x4a, 0xdb, 0x67,
+       0xd7, 0x8b, 0x89, 0x4b, 0x28, 0x3c, 0x3d, 0x8b, 0xec, 0xb8, 0x5e, 0x6d,
+       0xbe, 0x73, 0xd2, 0xc3, 0x97, 0xb2, 0xdf, 0x85, 0x35, 0x8e, 0x7f, 0x24,
+       0xbe, 0xb6, 0x08, 0xe2, 0xe1, 0x9a, 0x3f, 0x42, 0xee, 0x35, 0xfa, 0x63,
+       0x10, 0x97, 0xe8, 0xad, 0x8b, 0x98, 0x27, 0x8d, 0x7e, 0x4d, 0x9f, 0xe7,
+       0xdc, 0x9f, 0x8d, 0xf6, 0x03, 0x09, 0xf9, 0x9b, 0x59, 0xdf, 0xaf, 0xf7,
+       0x9c, 0x86, 0x2a, 0x44, 0xcd, 0x9f, 0xd3, 0x95, 0x2a, 0x48, 0x80, 0x37,
+       0x0f, 0xcf, 0x5f, 0x50, 0x94, 0xf0, 0x6c, 0xbc, 0x57, 0x2a, 0x6a, 0xde,
+       0x1a, 0x3c, 0x95, 0x41, 0x26, 0x0e, 0x77, 0x46, 0x17, 0xd1, 0xf0, 0x56,
+       0x06, 0x71, 0x7a, 0x88, 0x82, 0x77, 0x8a, 0x12, 0x1a, 0x08, 0xe3, 0x7a,
+       0x16, 0x99, 0x11, 0x4e, 0xd1, 0xe3, 0x6b, 0xfa, 0xf1, 0x19, 0x2b, 0xf1,
+       0x81, 0x1f, 0xd9, 0x28, 0x08, 0x48, 0xaf, 0x8d, 0x77, 0xc7, 0xa3, 0xbe,
+       0x23, 0x16, 0x86, 0x67, 0x6f, 0x65, 0x9c, 0x0a, 0xf4, 0xfb, 0xac, 0x12,
+       0xc6, 0x3c, 0x27, 0xdf, 0x0e, 0xf6, 0xfb, 0xa0, 0x3d, 0xd6, 0xf0, 0xab,
+       0x28, 0xb7, 0xce, 0x63, 0xf1, 0x86, 0x9e, 0xf7, 0xc4, 0xb5, 0xd0, 0xaf,
+       0x3b, 0x95, 0xd1, 0x7d, 0xf7, 0x76, 0x99, 0xf3, 0x1b, 0x61, 0xf7, 0x4c,
+       0xbc, 0x27, 0xae, 0xc3, 0x76, 0x81, 0x8d, 0xdb, 0xbd, 0x38, 0x1e, 0xf3,
+       0xa7, 0xe0, 0x7c, 0xa8, 0x02, 0xe7, 0x36, 0x7d, 0x7f, 0xae, 0x87, 0xf8,
+       0x8b, 0xe6, 0xe7, 0x7f, 0xfe, 0x2a, 0xbb, 0x6f, 0x01, 0x7e, 0xd7, 0x47,
+       0xef, 0x27, 0xc3, 0xb9, 0xda, 0xf2, 0x51, 0x11, 0xf9, 0x81, 0xf7, 0xc7,
+       0x00, 0xbf, 0xb7, 0xc5, 0xf3, 0x38, 0x92, 0xa7, 0x02, 0xbf, 0x77, 0x4b,
+       0x1c, 0x81, 0x3c, 0x8d, 0x5a, 0x93, 0x80, 0x79, 0xbf, 0xb5, 0x95, 0x17,
+       0xe0, 0x39, 0x13, 0xc2, 0xef, 0x79, 0xae, 0xe6, 0x53, 0xab, 0x35, 0x51,
+       0x7f, 0x71, 0x54, 0x44, 0x0e, 0xd4, 0x9a, 0x0e, 0x0d, 0x05, 0x7f, 0xab,
+       0xda, 0xb2, 0x1c, 0xef, 0x7f, 0xa6, 0xed, 0x6f, 0x80, 0x9f, 0x06, 0x3f,
+       0xc3, 0xdb, 0xfb, 0x3b, 0x1f, 0xb9, 0x7d, 0xf1, 0x50, 0xbb, 0xfc, 0xf8,
+       0x5f, 0xf1, 0xdc, 0x7b, 0xab, 0x91, 0x3e, 0xaa, 0x23, 0x74, 0x84, 0xe7,
+       0xe7, 0x2a, 0xf5, 0x74, 0x95, 0x1b, 0xa1, 0x17, 0xb4, 0xc7, 0x41, 0x8e,
+       0x4c, 0x26, 0x78, 0x6e, 0xdf, 0xce, 0xeb, 0xf1, 0x53, 0x3b, 0x02, 0x10,
+       0xc7, 0xf1, 0xf2, 0xb8, 0x46, 0xea, 0x5e, 0x76, 0xaf, 0xad, 0xbd, 0xb0,
+       0x85, 0x40, 0x5c, 0xd5, 0x7b, 0x94, 0xd9, 0x23, 0xe3, 0xdb, 0xd7, 0xee,
+       0x03, 0xff, 0x38, 0x71, 0x6a, 0x07, 0x78, 0x64, 0xb4, 0x3f, 0x8b, 0xcb,
+       0x45, 0x9f, 0x2f, 0x1a, 0xd7, 0xbe, 0x42, 0x04, 0xbf, 0x4f, 0xb3, 0x63,
+       0x74, 0x7e, 0xe7, 0x88, 0x6b, 0x47, 0xea, 0x4b, 0x76, 0x1e, 0x17, 0xfc,
+       0x58, 0xf8, 0x5e, 0x08, 0x1e, 0x01, 0xff, 0x48, 0x4c, 0xff, 0x3d, 0xcd,
+       0xf5, 0x1f, 0xd5, 0x93, 0x28, 0xaf, 0x17, 0xf8, 0x87, 0xa1, 0x9e, 0x04,
+       0x3d, 0x06, 0x72, 0x4e, 0xf3, 0x83, 0x41, 0xee, 0x81, 0x9c, 0x79, 0x71,
+       0xd0, 0xc4, 0x5b, 0x07, 0xa5, 0xc2, 0x7d, 0x86, 0x13, 0x6f, 0x1a, 0xc4,
+       0xf6, 0x69, 0x46, 0xa0, 0xdd, 0xef, 0x3b, 0xb7, 0xfd, 0x28, 0xad, 0x1f,
+       0xf8, 0xc3, 0x67, 0x8e, 0x97, 0x31, 0xb8, 0x85, 0x57, 0x25, 0x30, 0x39,
+       0x02, 0x3f, 0x10, 0x0a, 0x71, 0xe4, 0xdf, 0xc8, 0x6b, 0x1f, 0xc6, 0xf9,
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+       0x8f, 0x63, 0x95, 0xf2, 0xb8, 0x4f, 0x29, 0x8f, 0xfb, 0x40, 0xdc, 0x55,
+       0x9f, 0x17, 0x0b, 0x71, 0x4d, 0x7d, 0xbd, 0x9a, 0xcb, 0x85, 0x1a, 0xf8,
+       0xbd, 0x29, 0xbc, 0x4f, 0xc0, 0x1c, 0xc9, 0x8b, 0x85, 0x78, 0xcf, 0x64,
+       0x12, 0xb4, 0x43, 0x3b, 0xc4, 0x7d, 0x1c, 0xec, 0xfc, 0x9d, 0xfe, 0x7d,
+       0x2f, 0x09, 0x4c, 0x92, 0x90, 0xce, 0x7f, 0x30, 0x1b, 0xee, 0xcd, 0x5a,
+       0xc9, 0xd6, 0x3b, 0x87, 0xe3, 0x7d, 0x95, 0x95, 0xc5, 0x7b, 0xc6, 0xdf,
+       0xbb, 0x56, 0x64, 0x41, 0x2c, 0xb6, 0xde, 0x84, 0x51, 0xee, 0xdc, 0x07,
+       0x0a, 0x23, 0xf7, 0x77, 0x7d, 0xc1, 0xf1, 0xa4, 0xc1, 0x25, 0x6e, 0xd0,
+       0xc4, 0x12, 0x80, 0x7b, 0x9c, 0xc8, 0xee, 0x3f, 0x0f, 0x3f, 0xc0, 0x7e,
+       0x0f, 0xfb, 0x30, 0xd5, 0xdf, 0x5b, 0x78, 0x3c, 0xe4, 0x5a, 0x1b, 0x9e,
+       0x3f, 0x76, 0x9f, 0x07, 0x79, 0x0b, 0x92, 0x33, 0xe7, 0xda, 0x18, 0xbf,
+       0xeb, 0xfa, 0xf0, 0x0e, 0x2b, 0xde, 0xe3, 0xef, 0xe7, 0xf2, 0x48, 0x7b,
+       0x3e, 0x65, 0x10, 0xcb, 0xf7, 0xc5, 0x38, 0x11, 0xc0, 0x7d, 0x71, 0x3c,
+       0xda, 0xe1, 0x14, 0xcc, 0xf9, 0x40, 0x47, 0x45, 0x83, 0x35, 0x7d, 0x4a,
+       0xf2, 0x21, 0x3e, 0x75, 0x90, 0xe7, 0x7f, 0xd6, 0xde, 0x68, 0xf3, 0xc0,
+       0x78, 0x21, 0x1e, 0x37, 0x5f, 0x3d, 0x88, 0xe9, 0x8d, 0xd5, 0x83, 0xd8,
+       0xef, 0x3f, 0x68, 0xf5, 0x5e, 0xbf, 0x8f, 0xd3, 0x8b, 0xb6, 0xcf, 0x05,
+       0xf1, 0x1a, 0x7d, 0x7c, 0xbb, 0xb9, 0xb7, 0x3f, 0x8b, 0xaf, 0x68, 0xfa,
+       0xf7, 0xe9, 0x8a, 0xb8, 0xb5, 0xec, 0xbe, 0x77, 0x8d, 0x6e, 0x4d, 0x78,
+       0xbe, 0x32, 0x3e, 0xaf, 0x58, 0x81, 0x38, 0xd3, 0x0e, 0x2e, 0x47, 0x4a,
+       0xb8, 0x3f, 0xbf, 0x03, 0x36, 0x70, 0x41, 0x9e, 0xb4, 0xf0, 0xb8, 0xb4,
+       0xe4, 0x9c, 0x0d, 0xbf, 0x1b, 0xb4, 0xe3, 0x68, 0x1e, 0xe6, 0x53, 0xa6,
+       0x28, 0x4c, 0xbe, 0xec, 0xb8, 0x39, 0x8e, 0x40, 0x7e, 0xdf, 0xfe, 0x63,
+       0x2f, 0x3d, 0xf2, 0x1e, 0x6d, 0x3f, 0x79, 0x54, 0xc1, 0xfb, 0xf2, 0xe6,
+       0xf3, 0x78, 0xec, 0x0e, 0xb8, 0x17, 0x1e, 0xe4, 0xe5, 0x36, 0x33, 0xc6,
+       0x19, 0xab, 0x15, 0x66, 0x4f, 0x56, 0xef, 0x1e, 0xc9, 0xec, 0x18, 0xc5,
+       0xb3, 0x0a, 0xf2, 0xbe, 0x7d, 0x5b, 0x65, 0x8c, 0x7b, 0x55, 0x3b, 0x02,
+       0x1b, 0x5f, 0xc0, 0xf6, 0x4c, 0x17, 0xc5, 0x2c, 0x9c, 0x17, 0x65, 0x76,
+       0xf0, 0xf6, 0x78, 0xf6, 0x7e, 0x5c, 0xe0, 0x17, 0x2f, 0x83, 0x5f, 0xba,
+       0x3b, 0xdd, 0xe5, 0xa3, 0xfd, 0x17, 0x65, 0x78, 0xf6, 0x02, 0x1f, 0x65,
+       0x99, 0xd5, 0x04, 0xa2, 0xed, 0xbb, 0x0a, 0x91, 0xf3, 0xa4, 0x87, 0x02,
+       0xcc, 0x6e, 0x3e, 0x04, 0x82, 0x07, 0xbe, 0xd3, 0x6e, 0xe7, 0xbf, 0x33,
+       0xe0, 0xce, 0x5c, 0x40, 0xc7, 0xf9, 0xfc, 0xa1, 0x74, 0x5c, 0x0f, 0x95,
+       0xb7, 0x68, 0x5f, 0x7d, 0xfe, 0x98, 0x19, 0xf7, 0xd5, 0x9e, 0xee, 0xfd,
+       0x2e, 0x8b, 0x8f, 0x1e, 0x92, 0x8b, 0xf1, 0x3e, 0x99, 0x43, 0xdb, 0x0a,
+       0x5c, 0xd4, 0xf3, 0x24, 0x3d, 0xc5, 0x4a, 0x10, 0xe2, 0xdf, 0xde, 0xc7,
+       0x99, 0xbd, 0x37, 0xcf, 0xa4, 0xae, 0x01, 0xf8, 0x90, 0xdd, 0xf1, 0x2e,
+       0x83, 0xbf, 0xfa, 0x58, 0x19, 0xbb, 0x5f, 0xa2, 0xf2, 0xde, 0xe9, 0x67,
+       0xda, 0xe7, 0x06, 0xf9, 0xae, 0x8f, 0xff, 0x76, 0x93, 0x70, 0x0e, 0xfa,
+       0xab, 0xe5, 0x83, 0x5b, 0x20, 0xdf, 0xb4, 0xbb, 0x7d, 0x84, 0x8b, 0x6d,
+       0x67, 0x65, 0xe0, 0x26, 0x4a, 0x2d, 0xdf, 0x7f, 0x3e, 0x2c, 0x33, 0xf8,
+       0x86, 0x77, 0xc9, 0x48, 0xcf, 0xe7, 0x3a, 0x3e, 0xd0, 0x45, 0xef, 0xef,
+       0xe0, 0x89, 0x04, 0x7f, 0xdf, 0x4d, 0xbf, 0xdf, 0x16, 0xbd, 0x4f, 0xd1,
+       0xb7, 0xce, 0xf0, 0xe8, 0xdd, 0x91, 0xce, 0xed, 0x3a, 0x63, 0xfb, 0x75,
+       0xd9, 0x9e, 0x53, 0xc0, 0x6f, 0xb5, 0x4f, 0x7c, 0x77, 0x60, 0x91, 0x0a,
+       0xdf, 0x0b, 0xa3, 0x3c, 0x24, 0x7e, 0x16, 0x6f, 0x3f, 0x2c, 0xbb, 0x67,
+       0x03, 0xdd, 0x26, 0x4e, 0x0e, 0x1a, 0xf2, 0xb8, 0x6c, 0x2a, 0xf7, 0x0f,
+       0xcc, 0xdc, 0xfe, 0x23, 0x41, 0x45, 0xcf, 0x87, 0x5a, 0x7b, 0xd1, 0x44,
+       0x12, 0x73, 0x5f, 0xe7, 0xff, 0x00, 0x2e, 0x3f, 0xe0, 0x29, 0x00, 0x80,
+       0x00, 0x00, 0x00, 0x00, 0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x00, 0x0b, 0xc5, 0x7d, 0x0b, 0x78, 0x54, 0xd5, 0xb5, 0xf0, 0x3e, 0x73,
+       0xce, 0xbc, 0x92, 0x99, 0x64, 0x66, 0x32, 0x09, 0x93, 0x17, 0x39, 0x79,
+       0x07, 0x92, 0xc0, 0x10, 0x43, 0x44, 0x8b, 0x3a, 0x09, 0x01, 0x03, 0x46,
+       0x9d, 0x00, 0x2a, 0x5a, 0x8b, 0xc3, 0x1b, 0x94, 0x3c, 0x04, 0x6d, 0x63,
+       0x4b, 0x9b, 0x81, 0x44, 0x08, 0x88, 0x1a, 0x2e, 0x01, 0x01, 0x01, 0x27,
+       0x08, 0x4a, 0xaf, 0xd8, 0x06, 0x2f, 0x20, 0xd6, 0x48, 0x07, 0x44, 0x8a,
+       0xad, 0xde, 0x3f, 0x3e, 0xda, 0x8b, 0x7a, 0x2f, 0x5f, 0x50, 0x8a, 0x68,
+       0x05, 0x22, 0x5a, 0x7e, 0xda, 0xab, 0xf5, 0x5f, 0x6b, 0xed, 0x7d, 0x92,
+       0x39, 0x43, 0x22, 0xd8, 0xdb, 0xdb, 0x3f, 0x7c, 0xb0, 0xd9, 0x67, 0xbf,
+       0xd6, 0x5e, 0x6b, 0xed, 0xb5, 0xd6, 0x5e, 0x7b, 0xed, 0x9d, 0x58, 0x55,
+       0x62, 0x2c, 0x91, 0x31, 0x7b, 0x37, 0xf3, 0x85, 0x8a, 0x18, 0xfb, 0x06,
+       0x7f, 0x6e, 0xe8, 0x4f, 0x63, 0x55, 0x03, 0x95, 0x33, 0x36, 0xc5, 0xcc,
+       0x92, 0x18, 0xbb, 0x96, 0xf1, 0x9f, 0x8c, 0xd3, 0x50, 0xdf, 0xc6, 0x98,
+       0x4d, 0x55, 0x19, 0x1b, 0x0d, 0xdf, 0x4f, 0x87, 0x4d, 0xb3, 0x20, 0x9f,
+       0xb1, 0x24, 0x6c, 0x9a, 0x2b, 0xd2, 0x00, 0xa4, 0x27, 0x8d, 0x2c, 0x6c,
+       0x29, 0x85, 0x74, 0xa3, 0x3d, 0xb4, 0x2d, 0x13, 0x5b, 0xfa, 0x18, 0xf6,
+       0x33, 0x77, 0x0c, 0xfc, 0x17, 0x9a, 0xce, 0x95, 0x59, 0x8b, 0xa5, 0x04,
+       0xbf, 0xab, 0xfb, 0x7b, 0xdc, 0x8c, 0x9d, 0xda, 0xeb, 0xf4, 0xae, 0x82,
+       0xef, 0xec, 0xab, 0x6f, 0x64, 0x56, 0xc6, 0xd8, 0x0c, 0x26, 0xea, 0x99,
+       0x59, 0xab, 0xc5, 0xc5, 0xd8, 0x8b, 0x2d, 0x52, 0xd8, 0x02, 0xf5, 0x66,
+       0x6c, 0x30, 0x6f, 0xb3, 0x42, 0x7f, 0x65, 0xcb, 0x7c, 0xb2, 0x1d, 0xf2,
+       0xbd, 0x5b, 0x24, 0xef, 0x36, 0xa8, 0x37, 0xa3, 0xa5, 0x3c, 0x6f, 0x23,
+       0xe4, 0xef, 0xdd, 0x53, 0xec, 0x95, 0xa1, 0x69, 0x1c, 0x8e, 0x83, 0xf9,
+       0x90, 0x33, 0x24, 0x43, 0xfd, 0x6b, 0x1b, 0xc7, 0xb1, 0x8f, 0xae, 0x62,
+       0x6c, 0x96, 0x39, 0x64, 0x52, 0xe0, 0x3b, 0x7b, 0x4e, 0x62, 0x3b, 0x18,
+       0xf5, 0xdf, 0x82, 0xfd, 0x2f, 0x84, 0x46, 0xc9, 0x25, 0x97, 0xe2, 0x61,
+       0xde, 0x06, 0x33, 0x63, 0x16, 0x3e, 0xf7, 0x6f, 0xf0, 0x9f, 0x50, 0x44,
+       0x3e, 0x0b, 0xfa, 0xed, 0xec, 0x90, 0x19, 0xcc, 0x97, 0xed, 0x84, 0xef,
+       0x05, 0xfd, 0xdf, 0x17, 0x2a, 0xe1, 0x83, 0x52, 0x1c, 0x63, 0xb5, 0x9d,
+       0x51, 0xed, 0xd9, 0xdf, 0xcc, 0x7d, 0xf5, 0x10, 0x50, 0x16, 0x24, 0x3c,
+       0xbb, 0x4d, 0xec, 0x1e, 0xbf, 0x8d, 0x26, 0x3d, 0xa4, 0xa6, 0x98, 0xb1,
+       0x3f, 0xe2, 0x7f, 0x93, 0x19, 0x8b, 0xc9, 0xf0, 0x5f, 0xad, 0x12, 0x1d,
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+       0x84, 0xd7, 0x5a, 0xd6, 0x60, 0x62, 0xd8, 0x4f, 0x7b, 0x02, 0x63, 0xd7,
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+       0x9c, 0x59, 0xd0, 0x2a, 0xb1, 0x10, 0x80, 0xf8, 0xe9, 0xcf, 0x5f, 0x1c,
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+       0x67, 0x1b, 0x7c, 0x24, 0xbf, 0xcf, 0xc1, 0x6a, 0x44, 0xbe, 0xd3, 0xda,
+       0x9d, 0x9b, 0x1f, 0xe3, 0x43, 0x3b, 0xf3, 0x1c, 0xb3, 0x84, 0x24, 0x18,
+       0x6a, 0x66, 0x97, 0x1c, 0x36, 0x63, 0x7f, 0x3e, 0x5f, 0x8e, 0x1b, 0xe8,
+       0x5d, 0xa7, 0xb5, 0x8f, 0xea, 0x7f, 0x03, 0xf2, 0x0f, 0xc0, 0x25, 0xed,
+       0x97, 0xc2, 0x76, 0xa8, 0x1f, 0x5b, 0xd4, 0x4b, 0xf2, 0x76, 0x81, 0xc5,
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+       0x84, 0xfc, 0xea, 0x33, 0xe1, 0xbc, 0x15, 0x89, 0xcb, 0xf3, 0x33, 0x0e,
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+       0x7c, 0x77, 0xb8, 0x89, 0xee, 0xa6, 0x3a, 0x9b, 0x82, 0xfa, 0x22, 0xa9,
+       0x99, 0x71, 0x3b, 0xf0, 0x41, 0x43, 0x08, 0xf5, 0xb5, 0x3b, 0x26, 0x6e,
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+       0xa6, 0xc5, 0x10, 0x8f, 0xdf, 0x87, 0x86, 0xb0, 0x7e, 0x7a, 0x4a, 0x01,
+       0xb5, 0x0b, 0x56, 0x70, 0xfe, 0x0e, 0x26, 0xb1, 0x50, 0xb3, 0x84, 0x5d,
+       0x36, 0x48, 0x64, 0x07, 0x3a, 0x7a, 0x98, 0x02, 0xdf, 0xd3, 0xc6, 0x30,
+       0xc7, 0x2a, 0x94, 0x45, 0x99, 0xdc, 0x4e, 0xf4, 0x30, 0xef, 0x06, 0x99,
+       0xec, 0xc4, 0x4e, 0x09, 0xed, 0x44, 0x0d, 0x0f, 0x9a, 0x7c, 0x47, 0xbe,
+       0x41, 0xb9, 0xf7, 0xa9, 0x64, 0x21, 0xbe, 0x91, 0xba, 0x24, 0xb2, 0xfb,
+       0x64, 0x43, 0xe7, 0x74, 0xec, 0x77, 0x30, 0x3e, 0xda, 0x12, 0xc5, 0x47,
+       0x5b, 0xfe, 0xc9, 0x7c, 0xf4, 0xec, 0xa0, 0x7c, 0x14, 0x50, 0x89, 0x8f,
+       0x3c, 0x96, 0x81, 0xf9, 0x08, 0xf6, 0x4d, 0xdf, 0xa9, 0x3e, 0x0b, 0xfa,
+       0x15, 0xc0, 0xd7, 0x10, 0x81, 0xaf, 0xc7, 0x85, 0x7c, 0xe9, 0x7d, 0xd0,
+       0x42, 0x74, 0x83, 0x1f, 0x09, 0xe7, 0x5b, 0x2d, 0xfa, 0xab, 0xb6, 0xd8,
+       0xc2, 0xf2, 0x08, 0x92, 0x13, 0x9f, 0xf5, 0xc9, 0x6f, 0xe8, 0x67, 0x33,
+       0xd8, 0x9f, 0xb8, 0x4f, 0x49, 0x46, 0xfb, 0x19, 0xd2, 0xd4, 0xe6, 0x19,
+       0x2a, 0xb7, 0xdf, 0xbb, 0x7b, 0x24, 0xe8, 0x2f, 0xf6, 0x6a, 0x0b, 0xe9,
+       0xbd, 0x47, 0x0c, 0xdd, 0x99, 0x68, 0xe7, 0x0f, 0x19, 0xde, 0xb0, 0x1b,
+       0xf9, 0x63, 0xc8, 0xf4, 0xa2, 0x92, 0x66, 0xb2, 0x4f, 0xd2, 0x9c, 0x28,
+       0xf7, 0x51, 0xd6, 0xe0, 0xfc, 0xeb, 0x1a, 0xc7, 0xf9, 0xb9, 0x1d, 0x00,
+       0xfd, 0x22, 0x1f, 0xd5, 0x98, 0x68, 0x3f, 0x51, 0xf7, 0x50, 0xb9, 0x9f,
+       0xdb, 0x01, 0x55, 0xb4, 0x3e, 0xea, 0x57, 0x5b, 0x55, 0xd4, 0x67, 0xe3,
+       0xba, 0x32, 0x97, 0x22, 0x7f, 0xd4, 0x2f, 0x01, 0xfb, 0x08, 0xe5, 0xef,
+       0xfe, 0x8e, 0x8d, 0x73, 0x21, 0x5f, 0x37, 0xd5, 0xe6, 0x45, 0x3b, 0xc5,
+       0x6a, 0x99, 0x52, 0x84, 0xed, 0x58, 0xab, 0x7e, 0x9d, 0xad, 0x94, 0x3a,
+       0xc9, 0x2e, 0x0e, 0x4e, 0x64, 0x5e, 0x94, 0xdb, 0xe7, 0x42, 0x86, 0xa0,
+       0x71, 0x24, 0xca, 0xd9, 0x9e, 0xad, 0x3f, 0x41, 0x3d, 0xbe, 0xa0, 0xc8,
+       0x1b, 0x54, 0x71, 0xbd, 0x09, 0xbe, 0xcc, 0x61, 0xa4, 0x17, 0xda, 0x9d,
+       0xbe, 0x64, 0x17, 0xe0, 0x75, 0xdf, 0xdf, 0x64, 0xda, 0x17, 0xb5, 0x8f,
+       0x82, 0x3c, 0xa4, 0x2f, 0x0b, 0x7a, 0xb6, 0xd7, 0xf8, 0x92, 0x9d, 0x90,
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+       0x33, 0x0b, 0x0c, 0x0c, 0xe9, 0x3b, 0x4b, 0xf6, 0xce, 0x45, 0x39, 0x72,
+       0xc6, 0xaa, 0xb7, 0xbf, 0xcf, 0xd8, 0x39, 0xbd, 0x76, 0x66, 0x6b, 0xf2,
+       0xdd, 0x9b, 0x87, 0x74, 0xee, 0xcb, 0x5f, 0x42, 0x67, 0x6f, 0x1e, 0xd2,
+       0x79, 0x96, 0x81, 0x05, 0x22, 0xfb, 0xa9, 0x45, 0x3a, 0x03, 0x7d, 0x17,
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+       0xe7, 0x21, 0x9d, 0xd7, 0x1b, 0xdb, 0x7c, 0xb8, 0x6e, 0x9e, 0xcd, 0x08,
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+       0xa6, 0xa1, 0x3c, 0x9c, 0x69, 0x31, 0x7f, 0xab, 0x5e, 0xc4, 0x9f, 0x01,
+       0xfd, 0x6b, 0x16, 0x33, 0xf9, 0x25, 0x0e, 0x7c, 0xf5, 0xc5, 0x63, 0xcf,
+       0xa0, 0x1d, 0xd2, 0x25, 0x93, 0x1d, 0xa2, 0xf5, 0x77, 0x40, 0x09, 0x64,
+       0xa3, 0x5f, 0xe1, 0xc0, 0x31, 0x8f, 0x37, 0x28, 0x0d, 0xde, 0xff, 0x83,
+       0xc2, 0x6e, 0xf5, 0x58, 0x58, 0x10, 0xfd, 0x1f, 0x9a, 0xdd, 0xaf, 0xd9,
+       0x8f, 0xd1, 0xf2, 0xf8, 0xb8, 0x98, 0xcf, 0xd9, 0x6c, 0x5f, 0x0d, 0xed,
+       0x17, 0x85, 0xbf, 0x76, 0xbe, 0xe8, 0xd3, 0x12, 0xfa, 0x82, 0xdb, 0xa9,
+       0xdb, 0x25, 0xf2, 0xc7, 0x5a, 0xd4, 0x4e, 0x1f, 0xda, 0xbd, 0x75, 0xaf,
+       0xcc, 0x70, 0xa0, 0xbf, 0xf6, 0x74, 0x88, 0xfb, 0x67, 0xeb, 0xf6, 0x8e,
+       0x22, 0xff, 0xed, 0x82, 0xd0, 0xab, 0xe1, 0x54, 0xb4, 0x0b, 0xbb, 0x24,
+       0x07, 0xee, 0x1f, 0x16, 0x6c, 0x3f, 0x11, 0x87, 0xe7, 0xdd, 0xb0, 0x1f,
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+       0xf4, 0x51, 0x1c, 0x9e, 0x8b, 0xc3, 0xf8, 0x37, 0xe3, 0x3e, 0x22, 0xd6,
+       0xdd, 0x6b, 0x42, 0xfe, 0xad, 0x83, 0x7d, 0x1a, 0x54, 0x61, 0x75, 0x4a,
+       0xef, 0x11, 0xec, 0xaf, 0xce, 0xcd, 0xbc, 0x41, 0x14, 0x15, 0xfb, 0xf5,
+       0xfb, 0x36, 0xed, 0xfc, 0x72, 0x93, 0xdf, 0x44, 0xf2, 0x6e, 0x53, 0x97,
+       0x14, 0xc2, 0x7d, 0x5a, 0x92, 0x29, 0x90, 0x99, 0x86, 0xfa, 0x89, 0xa5,
+       0x39, 0x4e, 0xc5, 0xf6, 0xaf, 0x97, 0xff, 0xce, 0xf6, 0xa5, 0xe0, 0xb9,
+       0x66, 0xff, 0xb9, 0xb1, 0xef, 0x6b, 0x84, 0xcb, 0x8d, 0xe7, 0x4d, 0xd0,
+       0xbe, 0x67, 0x63, 0x3c, 0xf1, 0x61, 0x8f, 0x91, 0xf9, 0xc8, 0x0e, 0xd8,
+       0x68, 0x17, 0x72, 0x49, 0x21, 0x39, 0xf5, 0xe7, 0xcd, 0x4e, 0xda, 0xf7,
+       0xd0, 0x0f, 0xd4, 0xff, 0x73, 0x28, 0x93, 0xf2, 0x9a, 0xbe, 0x9e, 0xab,
+       0xb0, 0xb0, 0x02, 0x78, 0x9f, 0x3b, 0xd5, 0xf7, 0x1e, 0xd2, 0x0d, 0xe5,
+       0x77, 0x38, 0x4a, 0x7e, 0x47, 0xe6, 0xfb, 0xce, 0xa3, 0x59, 0x37, 0xd7,
+       0x2f, 0x20, 0xcf, 0xc3, 0x03, 0x9d, 0x8f, 0x8b, 0x73, 0x6a, 0x3c, 0xdf,
+       0x8d, 0x6c, 0x5f, 0xc7, 0x7a, 0xa9, 0x1d, 0x9e, 0xf3, 0xea, 0xfa, 0xd5,
+       0xf6, 0x01, 0xac, 0x61, 0x94, 0x0a, 0x70, 0xdf, 0x77, 0xb7, 0xcd, 0x8b,
+       0xf6, 0x4b, 0x3d, 0xf0, 0x75, 0x63, 0x49, 0x3f, 0x1f, 0x2e, 0x14, 0x53,
+       0xd1, 0xf8, 0xb0, 0x4e, 0xf8, 0x79, 0xeb, 0xe7, 0x7f, 0x48, 0xfb, 0x81,
+       0xfa, 0xfd, 0x92, 0x03, 0xfd, 0xbb, 0x0b, 0xbd, 0x9c, 0x0f, 0x17, 0xc2,
+       0x3e, 0xc9, 0x3c, 0xe2, 0xd2, 0x75, 0xcb, 0x3a, 0x81, 0x0f, 0x23, 0xe0,
+       0x1e, 0x6c, 0x1d, 0x5f, 0x9d, 0xa3, 0x5f, 0xc7, 0x7d, 0xf9, 0x7f, 0x92,
+       0x3f, 0xb3, 0x22, 0x47, 0x6f, 0xcf, 0x6a, 0xf3, 0xd7, 0xfc, 0xe2, 0x7d,
+       0xf3, 0xec, 0x92, 0xf8, 0xfa, 0x8a, 0x9a, 0x57, 0xf4, 0xfe, 0x32, 0xda,
+       0x9f, 0xad, 0xed, 0x0f, 0xaf, 0x54, 0xae, 0xdd, 0xd9, 0x07, 0x0f, 0xc7,
+       0x47, 0x5f, 0xfe, 0x9f, 0x2c, 0xd7, 0xe6, 0x44, 0xe1, 0x65, 0xb0, 0xf3,
+       0x82, 0xef, 0x2c, 0xd7, 0xa2, 0xcf, 0x0d, 0x72, 0xb8, 0x1f, 0x1c, 0xcf,
+       0x0d, 0xf0, 0x5c, 0xf7, 0x7f, 0x7a, 0x6e, 0xf0, 0x89, 0xda, 0x96, 0x64,
+       0x20, 0x3d, 0xe8, 0xd3, 0x9d, 0xa7, 0xa2, 0x9d, 0x8e, 0xe3, 0xb4, 0x6e,
+       0x91, 0xc9, 0x3e, 0x98, 0x20, 0xf3, 0x73, 0xe8, 0x5a, 0xbb, 0x99, 0xfc,
+       0xb4, 0xd1, 0xe7, 0xad, 0xf5, 0xea, 0x04, 0x71, 0xbe, 0xd8, 0xfd, 0x87,
+       0x6b, 0x50, 0x7f, 0xee, 0x31, 0x32, 0xd4, 0xeb, 0xf3, 0x6d, 0xf3, 0xe8,
+       0x3c, 0xb3, 0x5e, 0xde, 0x65, 0x72, 0xa8, 0x03, 0x9c, 0x33, 0x2a, 0x07,
+       0xc9, 0x7e, 0xff, 0xae, 0xe7, 0xef, 0x8f, 0xe6, 0xf4, 0x9d, 0xbf, 0x67,
+       0xe2, 0xf9, 0x7b, 0x59, 0x85, 0x5e, 0x3e, 0xbf, 0x6a, 0xfb, 0x22, 0x21,
+       0x10, 0x41, 0xe7, 0x8a, 0x22, 0x30, 0xfc, 0x07, 0xe0, 0x67, 0x8b, 0x12,
+       0x64, 0xae, 0x88, 0xef, 0x4f, 0xe6, 0x70, 0x7b, 0xf8, 0x55, 0x11, 0x27,
+       0xe3, 0x31, 0xb1, 0x56, 0x8c, 0xbf, 0x78, 0xdc, 0x1e, 0xeb, 0xc3, 0x7d,
+       0x87, 0xc7, 0xc0, 0xe3, 0x78, 0x9a, 0xb3, 0xfc, 0x5b, 0x50, 0x0e, 0x5a,
+       0x54, 0x8e, 0xc7, 0xa7, 0x5e, 0xba, 0x83, 0x19, 0x60, 0x7e, 0x4f, 0x19,
+       0x3b, 0x49, 0x5e, 0x04, 0x6b, 0x6d, 0x5e, 0x94, 0x7b, 0x9a, 0x9f, 0x45,
+       0xeb, 0xdf, 0x2e, 0xfc, 0x05, 0x57, 0xca, 0xdf, 0x7b, 0xa3, 0xd6, 0xfb,
+       0xde, 0x7f, 0xf2, 0x7a, 0xff, 0xb5, 0x36, 0xde, 0x77, 0x3d, 0x07, 0xdb,
+       0x00, 0xb8, 0xd1, 0xad, 0x03, 0x46, 0xe7, 0x5d, 0x6f, 0xe0, 0xf9, 0x4d,
+       0xe6, 0xa5, 0xfc, 0x3a, 0x58, 0x3f, 0x83, 0xf1, 0xed, 0xdb, 0x39, 0xfe,
+       0x37, 0x73, 0x68, 0xbd, 0xf9, 0x46, 0xd0, 0xb9, 0xfe, 0x15, 0xca, 0x95,
+       0xd8, 0xd2, 0xde, 0x8f, 0xd0, 0x9f, 0xc3, 0xf6, 0x98, 0x55, 0xdc, 0x57,
+       0xa0, 0x5f, 0x83, 0xf4, 0xe1, 0xea, 0x64, 0xae, 0xa7, 0x14, 0x6f, 0x19,
+       0xe2, 0x19, 0xec, 0xb9, 0x32, 0x8c, 0x83, 0x3a, 0x8e, 0xff, 0xbd, 0x66,
+       0x70, 0xfb, 0xef, 0x74, 0xdf, 0xba, 0xe7, 0xf6, 0xdf, 0xe9, 0x41, 0xe5,
+       0xcf, 0xdf, 0x67, 0xff, 0x35, 0x65, 0xf8, 0x3f, 0xc5, 0x79, 0x9e, 0x2c,
+       0xf7, 0xe5, 0xa1, 0x7e, 0x5c, 0x61, 0x07, 0xf8, 0x71, 0x5f, 0xf7, 0x73,
+       0x1e, 0x3f, 0xb3, 0xd9, 0xca, 0xf9, 0x73, 0xb3, 0xc4, 0xf9, 0x92, 0x35,
+       0x26, 0x68, 0xfe, 0x11, 0x9a, 0x57, 0xf0, 0x79, 0x7e, 0xfe, 0x1d, 0xcd,
+       0x57, 0x2c, 0x57, 0xcf, 0x57, 0x7d, 0xf9, 0x7f, 0xb2, 0xdc, 0xb4, 0xf5,
+       0xc1, 0xf1, 0xbf, 0x2c, 0x37, 0xe7, 0xff, 0x35, 0x0e, 0xfd, 0x9c, 0x83,
+       0xf7, 0x13, 0x24, 0xba, 0x95, 0x55, 0x74, 0x13, 0xde, 0x7a, 0x5f, 0x91,
+       0xd8, 0xb6, 0x08, 0xff, 0x73, 0x7d, 0x37, 0x8f, 0x43, 0x4b, 0x17, 0xf0,
+       0x6a, 0xdf, 0xff, 0x2a, 0xec, 0xbf, 0xb9, 0xb9, 0xbe, 0xa1, 0x18, 0xcf,
+       0xf5, 0xd9, 0x7b, 0x16, 0x0b, 0x8b, 0x07, 0x53, 0x07, 0x79, 0x0c, 0xed,
+       0x2e, 0xbf, 0x8d, 0xfc, 0xff, 0x75, 0x9d, 0x3c, 0x4e, 0xa4, 0x6e, 0x09,
+       0xa3, 0xf3, 0xde, 0x3a, 0xf4, 0x6f, 0x16, 0xa1, 0xdf, 0xaf, 0x86, 0xa1,
+       0x7d, 0xb7, 0x4f, 0x0d, 0x14, 0x60, 0xfb, 0x15, 0xef, 0xdb, 0x82, 0x72,
+       0x3c, 0xfa, 0xc5, 0x27, 0x33, 0xb2, 0xeb, 0xde, 0xe3, 0xf9, 0x45, 0x6a,
+       0xa0, 0x88, 0xe2, 0xc5, 0x96, 0xf4, 0xe8, 0xce, 0x19, 0xca, 0xbe, 0xf9,
+       0x62, 0x39, 0xfa, 0x2d, 0x00, 0x5e, 0xf2, 0x03, 0xb8, 0xd1, 0x2f, 0x13,
+       0x41, 0xa7, 0x69, 0xb9, 0xfc, 0x7c, 0x40, 0x4b, 0x6f, 0x8b, 0x82, 0x1f,
+       0xfd, 0xf4, 0xc4, 0xff, 0x9d, 0x72, 0x08, 0xed, 0xc1, 0x58, 0xb5, 0x9b,
+       0xfc, 0xfe, 0x75, 0x7b, 0xb8, 0x91, 0x56, 0x26, 0xfb, 0xc8, 0x3f, 0xcf,
+       0xee, 0x73, 0x31, 0xe4, 0xa3, 0xba, 0x3d, 0xe5, 0xa3, 0x5e, 0xa3, 0xfa,
+       0xd6, 0x51, 0x68, 0xcf, 0x96, 0x7d, 0x50, 0xed, 0x40, 0x3f, 0xc4, 0x67,
+       0xd7, 0xb9, 0x29, 0xbe, 0x60, 0xa8, 0xdc, 0xb3, 0x00, 0xed, 0xa9, 0xa3,
+       0x59, 0x81, 0x71, 0x08, 0xaf, 0xbd, 0x34, 0x34, 0x11, 0xed, 0xd1, 0x0c,
+       0xb0, 0x47, 0xd1, 0xbe, 0xfd, 0x6c, 0xf7, 0xc4, 0x51, 0x08, 0xb7, 0x26,
+       0xff, 0xd6, 0xa3, 0x7f, 0x1b, 0xfa, 0x5d, 0x6f, 0xd7, 0xfb, 0xaf, 0x99,
+       0xc5, 0x97, 0xf9, 0x30, 0xfa, 0xb7, 0xb7, 0x0d, 0xa1, 0xfd, 0xe1, 0xee,
+       0x94, 0xc0, 0xcd, 0xb9, 0xb8, 0x4f, 0xb3, 0x72, 0x78, 0x83, 0x6b, 0xac,
+       0x7c, 0xbd, 0x0a, 0xbf, 0x76, 0xf4, 0xfa, 0xd7, 0xd6, 0xfd, 0x10, 0xd9,
+       0x40, 0xe3, 0x0c, 0xf9, 0xbe, 0x85, 0xce, 0xa1, 0x35, 0xb9, 0xb0, 0xde,
+       0xc8, 0x02, 0x96, 0xec, 0x7e, 0x79, 0x72, 0x95, 0x88, 0x97, 0x03, 0x7c,
+       0xf0, 0x78, 0xbd, 0xae, 0x1a, 0x1e, 0xe7, 0x21, 0xf2, 0x36, 0xb7, 0x3e,
+       0x6e, 0xf1, 0x6c, 0xf6, 0xf8, 0xab, 0x70, 0x7e, 0x57, 0xe5, 0xf2, 0xb8,
+       0x94, 0x39, 0x96, 0x5e, 0x09, 0xfd, 0xec, 0x73, 0xc4, 0xf9, 0xfb, 0x8d,
+       0x22, 0x8e, 0x42, 0x8b, 0xa3, 0x3a, 0xe3, 0xf0, 0xcf, 0xc6, 0xfa, 0x6c,
+       0x49, 0x55, 0xff, 0xb9, 0x7b, 0x16, 0xb6, 0x77, 0x70, 0xfe, 0x17, 0xf1,
+       0x31, 0xb1, 0x17, 0xb9, 0x9d, 0x9c, 0xe5, 0x30, 0x11, 0xdf, 0xd8, 0x5b,
+       0x19, 0x3f, 0x37, 0x02, 0xbe, 0x41, 0xfa, 0x8c, 0xed, 0xed, 0x1e, 0x17,
+       0x0f, 0xf3, 0xc9, 0x69, 0x0f, 0x8f, 0x45, 0x7c, 0x1e, 0xb8, 0x68, 0x20,
+       0x7c, 0x28, 0x35, 0x6f, 0xd0, 0x79, 0x49, 0x3c, 0x92, 0x0d, 0xfa, 0xc9,
+       0x5e, 0xdd, 0xb3, 0x32, 0x1f, 0xfd, 0x25, 0x8e, 0x77, 0xaf, 0x43, 0xba,
+       0xa8, 0x6d, 0x8e, 0x0a, 0x44, 0xdd, 0x3e, 0xd5, 0xff, 0x00, 0xc1, 0xa1,
+       0x34, 0x14, 0xe0, 0xfe, 0xb1, 0xe2, 0xf7, 0x46, 0x1e, 0x0f, 0xf8, 0x4a,
+       0x2c, 0xe9, 0xf9, 0xf6, 0xa1, 0x0b, 0x29, 0x1e, 0xf0, 0xec, 0xfb, 0xc0,
+       0xaf, 0x99, 0x97, 0xea, 0x03, 0x2d, 0x0d, 0xb2, 0x65, 0x14, 0xff, 0x97,
+       0xb5, 0xff, 0x1d, 0xf2, 0xdb, 0xdb, 0xf7, 0x48, 0x03, 0xc6, 0x75, 0x3e,
+       0x9e, 0x6b, 0xe3, 0xe7, 0x49, 0xc1, 0x6e, 0x8a, 0x33, 0x63, 0x63, 0xdd,
+       0x84, 0x0f, 0xe5, 0x95, 0x0f, 0x82, 0x68, 0x5f, 0x28, 0x2b, 0x15, 0xf2,
+       0x54, 0xb4, 0x18, 0x7d, 0x06, 0x2b, 0xd2, 0x75, 0x29, 0x23, 0x3f, 0x7b,
+       0x6e, 0xbb, 0xc3, 0x80, 0x74, 0xc9, 0x10, 0x71, 0x25, 0xe7, 0x0e, 0xfc,
+       0xf7, 0x88, 0x00, 0xed, 0x47, 0x34, 0x3f, 0x7d, 0x88, 0x52, 0xc5, 0xd8,
+       0xb3, 0x1c, 0xf7, 0x57, 0xca, 0xd2, 0x9e, 0xeb, 0x61, 0x05, 0xb3, 0xda,
+       0x3d, 0x4e, 0x43, 0x1d, 0xfa, 0x35, 0x8d, 0xbd, 0x75, 0xe4, 0x17, 0x79,
+       0x25, 0x96, 0xfc, 0x9f, 0x19, 0xfb, 0xb3, 0x97, 0x7d, 0x0f, 0xf2, 0x19,
+       0xad, 0x0e, 0x26, 0xa1, 0xfc, 0xf9, 0xd5, 0x7d, 0x19, 0xc8, 0xd7, 0x41,
+       0x98, 0x67, 0xee, 0x00, 0xf3, 0x6c, 0xcc, 0xe5, 0x71, 0x3b, 0xca, 0x2b,
+       0xb1, 0x06, 0xd4, 0x5b, 0xca, 0x1a, 0x46, 0x71, 0x88, 0x8a, 0x33, 0xa9,
+       0x82, 0xe0, 0x5e, 0x07, 0x79, 0xe8, 0x67, 0x91, 0xe0, 0x1b, 0xed, 0xfc,
+       0x11, 0xc0, 0xf5, 0xa0, 0x3e, 0x9a, 0x9b, 0x1b, 0xd8, 0x8e, 0x78, 0x8e,
+       0x15, 0x72, 0x80, 0x35, 0xc6, 0x90, 0xbf, 0xd0, 0xae, 0x70, 0xbf, 0x86,
+       0xbd, 0xf1, 0xfd, 0xe7, 0x97, 0x42, 0x7e, 0xab, 0xf0, 0xb7, 0x1e, 0x3a,
+       0x50, 0x38, 0x99, 0xfc, 0x73, 0x2b, 0x15, 0x09, 0xe9, 0x70, 0xc1, 0x39,
+       0x23, 0xc3, 0x01, 0xdf, 0x7f, 0x99, 0xcb, 0xed, 0x11, 0xbb, 0xd2, 0xcd,
+       0x1c, 0xb6, 0x48, 0xfc, 0x1f, 0xa2, 0xb8, 0xcb, 0xac, 0x57, 0x78, 0x5c,
+       0x9a, 0x62, 0xe4, 0x7c, 0xa2, 0xac, 0x74, 0x77, 0xa0, 0xff, 0xef, 0xcb,
+       0xb4, 0x00, 0xc5, 0x97, 0x5e, 0xd7, 0x12, 0x96, 0xe9, 0xfc, 0xca, 0x71,
+       0x72, 0x6d, 0x95, 0x1a, 0xb1, 0x7f, 0xd9, 0xc0, 0xf5, 0x48, 0xdd, 0x4e,
+       0xbe, 0x6f, 0x8e, 0xde, 0xaf, 0x5c, 0x4e, 0x7f, 0x1c, 0xcd, 0xd5, 0xdb,
+       0xdd, 0x7d, 0xf9, 0x7f, 0x92, 0x5d, 0xf2, 0x4e, 0xdf, 0xf8, 0x7f, 0xe7,
+       0x3e, 0x84, 0xe9, 0xf7, 0x6f, 0xd1, 0xf6, 0x49, 0xf4, 0x7e, 0xed, 0x12,
+       0xfb, 0x3a, 0xaa, 0xbf, 0xc1, 0xec, 0x14, 0x2d, 0x8e, 0xa3, 0xa2, 0x7f,
+       0x1c, 0xe2, 0x87, 0x57, 0xed, 0x9a, 0x1d, 0x14, 0xd4, 0xc5, 0xb9, 0x54,
+       0xd8, 0xf8, 0xb8, 0xcc, 0xa2, 0xef, 0xff, 0xf9, 0x4c, 0x2e, 0x27, 0xb4,
+       0xb8, 0x97, 0xa4, 0x66, 0x75, 0x29, 0xc6, 0x97, 0xf7, 0xfe, 0x94, 0x91,
+       0x3f, 0x4d, 0x8b, 0xcb, 0xd1, 0xe2, 0x70, 0x82, 0x15, 0x7c, 0x9f, 0x10,
+       0x34, 0x80, 0xdc, 0xcb, 0xc4, 0xf3, 0x9f, 0x36, 0x8a, 0xbf, 0x49, 0x65,
+       0x61, 0x49, 0x22, 0x7b, 0xbf, 0x87, 0x61, 0xfb, 0x21, 0x18, 0x87, 0x03,
+       0xed, 0x7b, 0x72, 0xb3, 0xa8, 0xff, 0x2d, 0xcc, 0xdb, 0x2a, 0x93, 0x5c,
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+       0x5c, 0x1c, 0xef, 0x36, 0x1b, 0x8d, 0x67, 0xc5, 0xf8, 0x8d, 0x04, 0xda,
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+       0xc4, 0x80, 0xe2, 0x23, 0x7b, 0x3d, 0x30, 0x55, 0xba, 0x0d, 0xe0, 0x6e,
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+       0x3b, 0xca, 0xd9, 0xc5, 0xef, 0x7f, 0x69, 0xeb, 0x59, 0x93, 0x2f, 0xd1,
+       0xeb, 0x19, 0xa4, 0x60, 0x8e, 0x3b, 0x89, 0x71, 0x10, 0x55, 0xfc, 0x07,
+       0xa6, 0x91, 0x84, 0x7a, 0x9f, 0x91, 0x3d, 0xaf, 0x9d, 0x0f, 0xa6, 0x5b,
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+       0x44, 0x3e, 0x35, 0x3f, 0x93, 0xd6, 0x1b, 0x54, 0x09, 0x1b, 0x4a, 0xd0,
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+       0xf8, 0xcf, 0x4f, 0xc3, 0x75, 0x28, 0xc7, 0xe4, 0xa7, 0xa1, 0xbe, 0x6b,
+       0x76, 0x7a, 0x55, 0x7f, 0x44, 0xbe, 0x00, 0x96, 0xd1, 0x34, 0x17, 0xe2,
+       0x07, 0xea, 0x41, 0x7e, 0x4a, 0xd5, 0x89, 0x1c, 0x25, 0xc2, 0xff, 0x97,
+       0x9a, 0xaf, 0x92, 0xb0, 0x84, 0x7a, 0xbe, 0x04, 0x80, 0xe3, 0x90, 0x55,
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+       0xb8, 0x1e, 0x18, 0x17, 0xea, 0x1d, 0xb2, 0xc3, 0xb8, 0x50, 0x6f, 0xbb,
+       0xd5, 0x1c, 0x36, 0xc4, 0x0d, 0x34, 0xfe, 0x18, 0x15, 0xc7, 0xbb, 0xdc,
+       0xb8, 0x80, 0x4e, 0x42, 0xea, 0x24, 0x81, 0x67, 0xe0, 0x8b, 0x20, 0xfa,
+       0xa5, 0x0e, 0xd9, 0x0d, 0xc4, 0x9f, 0x93, 0x44, 0x7c, 0xee, 0xa1, 0x44,
+       0x3e, 0x1e, 0x2b, 0xd0, 0xc7, 0xcf, 0xe4, 0xc4, 0xc0, 0xf8, 0xe4, 0x6f,
+       0xd5, 0xc7, 0xcb, 0xdc, 0x28, 0x6d, 0x6e, 0x41, 0xbd, 0xfc, 0x84, 0x35,
+       0x6e, 0x1b, 0xf2, 0xe3, 0x6f, 0x04, 0x9f, 0x1c, 0x89, 0xfd, 0x59, 0x0e,
+       0xda, 0x55, 0xbf, 0x99, 0x9e, 0x77, 0x18, 0xe5, 0xca, 0x84, 0xf8, 0xa5,
+       0x2d, 0xc8, 0x24, 0x93, 0x58, 0x27, 0xc9, 0x1b, 0x4d, 0xee, 0x5d, 0x48,
+       0x3e, 0x51, 0x86, 0x79, 0x90, 0x7f, 0xd7, 0xe6, 0x03, 0xdd, 0x7f, 0x98,
+       0xf5, 0xd6, 0x74, 0xec, 0xfc, 0xb0, 0xf3, 0x89, 0x1c, 0xd4, 0x7f, 0x20,
+       0x1f, 0xbe, 0x97, 0x9f, 0x78, 0x29, 0xfc, 0x1a, 0x3f, 0x6a, 0x70, 0x23,
+       0x1f, 0xe2, 0x3a, 0xe8, 0xe3, 0xc3, 0x28, 0xf8, 0x35, 0x3e, 0x62, 0xb7,
+       0x74, 0x52, 0x80, 0xe1, 0x16, 0xb0, 0x4b, 0x31, 0xd5, 0xec, 0x54, 0xc6,
+       0x1a, 0x78, 0x1c, 0xb8, 0x9a, 0xde, 0x3f, 0x3f, 0x60, 0xe2, 0x09, 0x96,
+       0x06, 0x3e, 0x8f, 0xa5, 0x41, 0x82, 0xfb, 0x46, 0xe7, 0x5a, 0x8a, 0x37,
+       0x1b, 0x31, 0x2c, 0xe0, 0x47, 0xb8, 0xa6, 0x8d, 0xfc, 0x7c, 0xa8, 0x82,
+       0x95, 0x3d, 0x33, 0xf2, 0x71, 0x1f, 0x06, 0xf0, 0xd6, 0xfc, 0xff, 0x84,
+       0x37, 0xda, 0x2e, 0xbf, 0x5c, 0x3c, 0xb4, 0x06, 0x57, 0xf4, 0x3a, 0xd6,
+       0xc6, 0x97, 0x26, 0xef, 0xa4, 0x78, 0xe8, 0xfa, 0xa9, 0x36, 0x8a, 0x8f,
+       0x1e, 0x27, 0xe2, 0x4a, 0xeb, 0xe7, 0x1b, 0x28, 0x4e, 0x08, 0xf6, 0x6f,
+       0x64, 0xf7, 0xd7, 0x31, 0x4b, 0x08, 0xe5, 0xf0, 0xb5, 0xc2, 0x8e, 0xd6,
+       0xe2, 0xf4, 0x7f, 0x25, 0x71, 0xff, 0x67, 0x70, 0xaf, 0x59, 0xdd, 0x11,
+       0x61, 0x8f, 0x5f, 0x1a, 0x27, 0xad, 0x52, 0x1c, 0x76, 0x70, 0x09, 0x8f,
+       0xa7, 0xee, 0xb3, 0xb7, 0x6b, 0xb9, 0xbd, 0xdd, 0xa7, 0xd7, 0xc4, 0xbd,
+       0x80, 0xf6, 0x51, 0x5c, 0x96, 0xb7, 0xdf, 0xaf, 0x52, 0xbc, 0xc4, 0xcb,
+       0x12, 0xaf, 0x1f, 0x9c, 0xc1, 0xb8, 0xbd, 0x5e, 0x23, 0xca, 0xe7, 0x38,
+       0x44, 0x3c, 0x05, 0xcc, 0x25, 0xa9, 0x3f, 0x5e, 0xbd, 0xbd, 0x83, 0x11,
+       0xff, 0xb7, 0xdb, 0xb3, 0xa8, 0x3c, 0x45, 0xe6, 0xfa, 0x87, 0x7d, 0x8f,
+       0xeb, 0x9f, 0xf6, 0x4c, 0x6e, 0x4f, 0xb6, 0xdf, 0x99, 0x47, 0xe5, 0xb0,
+       0x2f, 0x18, 0x86, 0x78, 0x9f, 0x25, 0x83, 0xfd, 0xcc, 0xcf, 0xe7, 0xf9,
+       0xfe, 0x20, 0x97, 0x8f, 0x17, 0xed, 0xa7, 0x5d, 0x9f, 0xcf, 0xed, 0xb2,
+       0x3e, 0x3b, 0x47, 0xe4, 0xa3, 0xfd, 0xb2, 0xcf, 0x66, 0x04, 0x36, 0x22,
+       0xdf, 0xcf, 0x29, 0xf2, 0x0d, 0x95, 0x80, 0xaf, 0x66, 0x99, 0xb8, 0xdf,
+       0x15, 0xf8, 0x6e, 0x33, 0xde, 0x89, 0xa9, 0x62, 0x0d, 0xdb, 0x95, 0x6c,
+       0xbc, 0x5f, 0xd1, 0xf0, 0xae, 0x21, 0x9b, 0xf8, 0xee, 0x29, 0xe2, 0xbb,
+       0x42, 0xe0, 0xbb, 0x6c, 0x1d, 0xdf, 0x85, 0xf2, 0x47, 0x73, 0xf9, 0x8b,
+       0xc2, 0x54, 0xe3, 0xbb, 0x3e, 0x7e, 0x2b, 0x88, 0x8e, 0x87, 0x0b, 0xfc,
+       0x1c, 0xfb, 0x69, 0x77, 0x76, 0x7e, 0x50, 0x87, 0xfb, 0x8a, 0x2e, 0x33,
+       0xd1, 0x41, 0x8b, 0x6b, 0x8c, 0x5e, 0xe7, 0x11, 0xf0, 0x9c, 0x34, 0x72,
+       0x78, 0xdc, 0xb2, 0x4c, 0xf0, 0xec, 0x1e, 0x08, 0x9e, 0x2b, 0xe1, 0xff,
+       0x48, 0x7e, 0x1b, 0xc2, 0x38, 0x9f, 0x0f, 0xb6, 0x0e, 0x86, 0x28, 0x2c,
+       0x68, 0x2f, 0xe9, 0x5f, 0x07, 0x6b, 0x3c, 0x81, 0x30, 0x8e, 0xdb, 0xb7,
+       0x1e, 0x96, 0xf3, 0x7d, 0xe4, 0x25, 0x70, 0xcb, 0x36, 0xe2, 0x8b, 0xdb,
+       0xef, 0x94, 0x39, 0xbf, 0xc6, 0x72, 0x7d, 0x8e, 0xe7, 0x49, 0xc9, 0x30,
+       0x7e, 0x8d, 0x18, 0xff, 0xf6, 0x95, 0xfe, 0x4a, 0x27, 0xd6, 0xab, 0x91,
+       0x08, 0x0f, 0x35, 0x5d, 0xb5, 0x14, 0xf7, 0xc5, 0x2a, 0xf9, 0xb9, 0x90,
+       0x17, 0xfe, 0x20, 0x3c, 0xcd, 0x42, 0xce, 0x69, 0xe7, 0x57, 0xd3, 0x44,
+       0xfb, 0x29, 0x8e, 0x1a, 0x23, 0xfa, 0xe3, 0xa6, 0x56, 0xeb, 0xcf, 0x91,
+       0xa6, 0xd9, 0xf8, 0x39, 0xd5, 0xed, 0x53, 0x8d, 0x1f, 0x46, 0xda, 0x3d,
+       0xd3, 0xd8, 0xea, 0xcf, 0x31, 0x4e, 0x71, 0x1a, 0x9e, 0x33, 0x69, 0xf5,
+       0x81, 0x8f, 0xde, 0xcf, 0xb7, 0xbb, 0xe9, 0xfc, 0x5b, 0x65, 0xf9, 0x78,
+       0xce, 0x74, 0x58, 0xf8, 0x59, 0xce, 0x01, 0x5f, 0x23, 0xdf, 0xbf, 0x96,
+       0x38, 0x6f, 0xf3, 0xfd, 0xc0, 0x77, 0xf9, 0x4f, 0x16, 0x95, 0xa0, 0x3f,
+       0x6e, 0x7c, 0xd2, 0x82, 0xed, 0x6b, 0x20, 0xff, 0xec, 0xa6, 0xe1, 0x94,
+       0x7f, 0x2d, 0xe9, 0xfb, 0x0f, 0xbc, 0x85, 0xe5, 0x5b, 0xf3, 0x28, 0x5f,
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+       0xae, 0xf1, 0x63, 0xf4, 0x74, 0x75, 0xfa, 0xf4, 0x74, 0x4d, 0xa8, 0xd2,
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+       0xba, 0xe7, 0x33, 0x11, 0xef, 0xf8, 0x3f, 0xa4, 0x7b, 0xf2, 0x30, 0x3d,
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+       0xe7, 0xbd, 0x98, 0x42, 0xf2, 0x0b, 0xdc, 0xc5, 0x3a, 0x8d, 0xd8, 0xff,
+       0xdd, 0xac, 0x9b, 0xd2, 0xe9, 0xac, 0x97, 0xd2, 0x00, 0x73, 0x90, 0x1e,
+       0x9d, 0xc9, 0xbc, 0x94, 0xce, 0x66, 0x7e, 0x93, 0xf0, 0x13, 0xdc, 0x30,
+       0x2c, 0x11, 0xfd, 0x07, 0x3d, 0x65, 0xa8, 0x87, 0x2f, 0xcc, 0x78, 0xeb,
+       0x38, 0x9d, 0x2f, 0xbd, 0x91, 0x70, 0x45, 0xef, 0x3d, 0x7c, 0x88, 0xe7,
+       0x18, 0xb9, 0x8c, 0x9d, 0x12, 0xf2, 0xe0, 0x24, 0x9e, 0x67, 0x40, 0xfe,
+       0xac, 0x55, 0xf8, 0xd3, 0x7c, 0x4c, 0x75, 0x47, 0xe0, 0xed, 0x94, 0xf0,
+       0xfb, 0xcd, 0x1c, 0x27, 0x91, 0x3e, 0x64, 0x72, 0x0c, 0xc5, 0x59, 0xcd,
+       0xbc, 0x43, 0x22, 0x7d, 0x32, 0xf3, 0xff, 0xf2, 0xf4, 0x8e, 0x61, 0xdc,
+       0x1e, 0x8d, 0x4e, 0x9b, 0x1b, 0x35, 0xfc, 0xf1, 0x7d, 0xca, 0xda, 0x61,
+       0x2a, 0xc9, 0xf7, 0x34, 0xd6, 0x29, 0xf4, 0x1e, 0x0b, 0xd8, 0xb2, 0xa9,
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+       0x79, 0x89, 0x29, 0x63, 0x5c, 0x74, 0xed, 0x8c, 0xe8, 0xea, 0xb1, 0x70,
+       0x78, 0x9e, 0x37, 0x32, 0x0b, 0xe2, 0xf3, 0x39, 0x16, 0x50, 0x91, 0x18,
+       0x8f, 0x28, 0x20, 0xa2, 0xf8, 0x7d, 0x87, 0xe1, 0xc8, 0x1f, 0x33, 0xff,
+       0xef, 0x5b, 0x59, 0xe8, 0x2f, 0x8b, 0x59, 0xb5, 0x7b, 0x6a, 0xe5, 0x35,
+       0x78, 0x3e, 0x12, 0x5c, 0x4a, 0xfe, 0xea, 0x1f, 0x30, 0xbd, 0xbf, 0xfa,
+       0xee, 0x06, 0x89, 0xfc, 0xd5, 0x3f, 0x00, 0x38, 0x21, 0xf5, 0x38, 0xbc,
+       0x1e, 0xd4, 0x97, 0x5a, 0x3e, 0x88, 0xf0, 0xc2, 0x3c, 0x2a, 0xb1, 0x1e,
+       0x7c, 0x1f, 0xe2, 0x69, 0x90, 0xd0, 0x3f, 0xf4, 0x0f, 0xeb, 0x6f, 0xcf,
+       0x8f, 0x79, 0xbd, 0xbf, 0xb3, 0xbf, 0xbe, 0x7e, 0x18, 0x87, 0x0b, 0x7f,
+       0x90, 0x7e, 0x9a, 0xff, 0xb1, 0xc0, 0xc0, 0xe3, 0x15, 0x7a, 0xef, 0xe7,
+       0xfb, 0x94, 0xed, 0x3f, 0x60, 0xdc, 0x8f, 0xd6, 0x18, 0x2c, 0x0f, 0xe2,
+       0xf9, 0xa4, 0x0c, 0x1b, 0x4a, 0x8c, 0x67, 0x32, 0xf2, 0x7b, 0xe8, 0x6b,
+       0x87, 0x65, 0xf2, 0xfb, 0x6e, 0xac, 0x9b, 0xf6, 0xf9, 0xec, 0x88, 0x66,
+       0x5f, 0x06, 0x48, 0xfe, 0x16, 0x89, 0x7b, 0x0e, 0x67, 0xc5, 0xf9, 0xde,
+       0xdc, 0x0e, 0x0b, 0xc3, 0x78, 0x99, 0xa2, 0xdd, 0x07, 0x5d, 0x78, 0x9e,
+       0x37, 0x17, 0x78, 0xb0, 0x1b, 0xf5, 0xb0, 0x12, 0xa0, 0x77, 0x56, 0x8a,
+       0x36, 0xbe, 0xe6, 0xe2, 0xfe, 0x37, 0xa3, 0x13, 0xef, 0x2f, 0x6a, 0xfa,
+       0x7f, 0x70, 0x3e, 0x55, 0xd8, 0xa9, 0x88, 0xfb, 0x02, 0xc0, 0x77, 0x0d,
+       0x03, 0xd9, 0x1f, 0x7b, 0x86, 0xf3, 0x73, 0xfa, 0xe6, 0xa6, 0xee, 0x61,
+       0x78, 0x1e, 0xa7, 0xc1, 0xf3, 0x70, 0xd3, 0x51, 0xca, 0xcb, 0x8a, 0x97,
+       0xe2, 0x0c, 0xf1, 0x1d, 0x26, 0x67, 0x44, 0x7b, 0x93, 0x1b, 0xca, 0x23,
+       0xe4, 0x9d, 0x62, 0x83, 0xf6, 0x11, 0x72, 0xc8, 0x68, 0xf3, 0xd3, 0x63,
+       0x26, 0xcb, 0x9b, 0xba, 0xe9, 0x9c, 0xcf, 0x28, 0xde, 0x8b, 0x5a, 0x91,
+       0xb6, 0xc8, 0x11, 0x88, 0xd8, 0xc7, 0xbd, 0x30, 0x8c, 0x8f, 0xcf, 0x2c,
+       0x41, 0xe6, 0x48, 0x62, 0xc2, 0x04, 0xc7, 0x54, 0x39, 0x85, 0x72, 0xed,
+       0xaf, 0x8c, 0xef, 0x67, 0xcd, 0x1e, 0xe8, 0x27, 0x52, 0x7e, 0x5e, 0x4c,
+       0x64, 0x91, 0x7e, 0xfa, 0xd6, 0xa6, 0x63, 0x04, 0xef, 0x72, 0x29, 0x10,
+       0xc0, 0x4e, 0xcc, 0x39, 0x2c, 0x6c, 0x05, 0xfa, 0x98, 0x15, 0xbc, 0x73,
+       0x0b, 0xdf, 0x37, 0xde, 0x78, 0x14, 0xe3, 0xa9, 0x4c, 0xf6, 0x45, 0xde,
+       0xb0, 0x3a, 0x38, 0xde, 0xcc, 0x1e, 0xe5, 0x42, 0xa4, 0x3c, 0x7d, 0x75,
+       0x98, 0xd8, 0x47, 0x0b, 0x79, 0xfa, 0x2f, 0x4d, 0xbd, 0x85, 0x38, 0x4e,
+       0x73, 0x53, 0x8f, 0x86, 0x2f, 0x86, 0xe7, 0xa6, 0xc1, 0x64, 0x7e, 0x8f,
+       0xbe, 0xb9, 0xe9, 0x13, 0xfa, 0x6e, 0xa8, 0x52, 0x89, 0xdf, 0x5e, 0xdd,
+       0x98, 0x7f, 0x50, 0x85, 0xf2, 0xe3, 0xf0, 0x17, 0xdf, 0xb5, 0x31, 0xbb,
+       0x39, 0x5c, 0xec, 0xa2, 0x9b, 0xf4, 0xea, 0x74, 0xc1, 0x07, 0xe8, 0x13,
+       0x4b, 0x07, 0xfe, 0x39, 0xde, 0x68, 0x24, 0x3e, 0x5b, 0x9c, 0x6e, 0x23,
+       0x7f, 0xfd, 0xe2, 0x37, 0x73, 0x0f, 0xfa, 0x60, 0x3d, 0x9b, 0x60, 0xba,
+       0xf2, 0x77, 0x80, 0xbb, 0x7f, 0x1c, 0x8e, 0x27, 0x93, 0x90, 0xa7, 0xc0,
+       0x4f, 0x7e, 0x94, 0x0f, 0xa6, 0x14, 0x85, 0xfc, 0xf6, 0x2e, 0xc7, 0x64,
+       0xa2, 0xd3, 0xdf, 0xdb, 0x9f, 0x86, 0x5f, 0x93, 0x95, 0xd1, 0x7b, 0x44,
+       0xa6, 0x74, 0x1b, 0xd9, 0x05, 0x57, 0x0a, 0xe7, 0xb9, 0x28, 0x7d, 0x05,
+       0x78, 0x21, 0xf9, 0xbf, 0x58, 0xe0, 0x45, 0x7b, 0x5f, 0xe9, 0xf8, 0x03,
+       0x8c, 0xf6, 0x0b, 0x8b, 0x1f, 0xe2, 0xfe, 0xbb, 0xc5, 0xb5, 0x8c, 0xe2,
+       0xfd, 0x59, 0x23, 0xfc, 0x94, 0xf5, 0xf3, 0x8d, 0xa6, 0x67, 0x12, 0xf1,
+       0x25, 0x18, 0xf8, 0xd8, 0xd6, 0x04, 0x2b, 0x0e, 0xba, 0x78, 0xac, 0xc9,
+       0xc2, 0x02, 0xf9, 0x60, 0x87, 0x60, 0x7c, 0x7c, 0x76, 0x3f, 0x1d, 0xdb,
+       0x7c, 0x8a, 0x13, 0x8f, 0xfa, 0xd7, 0x54, 0xba, 0x6b, 0x30, 0x7d, 0x6c,
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+       0xd5, 0xe3, 0xf8, 0x8e, 0x06, 0x16, 0x42, 0xfb, 0x98, 0xce, 0xe0, 0x61,
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+       0x2a, 0xe7, 0xf7, 0xd2, 0xa3, 0xe9, 0xf8, 0xf0, 0x70, 0x49, 0xf7, 0x5e,
+       0x9c, 0xbd, 0x3f, 0x7e, 0xe4, 0xe1, 0xe1, 0x18, 0x3f, 0xd2, 0xd9, 0x43,
+       0x76, 0xb8, 0x16, 0x3f, 0x82, 0xf3, 0xa6, 0xfe, 0xac, 0x7c, 0xfe, 0xd1,
+       0xfd, 0x6d, 0x1a, 0xce, 0xfd, 0x09, 0xc3, 0x59, 0xf7, 0xd2, 0x58, 0xbe,
+       0x9e, 0xe9, 0x9c, 0x36, 0x77, 0xbf, 0x77, 0x59, 0x2c, 0xf0, 0x7d, 0x6a,
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+       0xc0, 0x22, 0xcf, 0x31, 0xb5, 0xb4, 0xb8, 0x90, 0xcb, 0xdf, 0x97, 0x86,
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+       0xd2, 0x16, 0x36, 0x09, 0xf5, 0xb6, 0xd3, 0x40, 0x71, 0xa0, 0x72, 0x47,
+       0x0c, 0xdd, 0x4f, 0x95, 0x9d, 0x0a, 0xc5, 0x9f, 0xb7, 0xd8, 0x2a, 0x1d,
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+       0x31, 0x7e, 0x47, 0x4e, 0x57, 0x18, 0xfa, 0xbd, 0x5a, 0x1c, 0x0a, 0xb7,
+       0x43, 0xd2, 0x0c, 0x14, 0x97, 0xa7, 0x38, 0x2b, 0x2d, 0x78, 0xbe, 0x93,
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+       0x50, 0xff, 0xc1, 0x34, 0x45, 0xbc, 0xeb, 0xe2, 0xab, 0x1e, 0x95, 0x24,
+       0x8e, 0x26, 0x54, 0xdc, 0x0f, 0x55, 0x7d, 0x82, 0xfb, 0xed, 0xc3, 0x8e,
+       0xf3, 0x56, 0xdc, 0x17, 0xa8, 0xb6, 0xb9, 0xe4, 0x0f, 0xac, 0x2b, 0xe4,
+       0xfb, 0x44, 0x23, 0x9e, 0xe3, 0x41, 0xfe, 0xa9, 0x25, 0xe7, 0x9d, 0x28,
+       0xbf, 0x5e, 0xef, 0x58, 0xee, 0xca, 0x44, 0x7b, 0x3a, 0xa4, 0x90, 0x2d,
+       0x52, 0xf0, 0x75, 0x73, 0x0a, 0xbd, 0x3b, 0xd0, 0x61, 0xa2, 0x77, 0x11,
+       0x34, 0xbc, 0x66, 0x04, 0x15, 0xdd, 0x79, 0x60, 0x7a, 0xa3, 0x3e, 0x6f,
+       0x8e, 0x3a, 0x17, 0x34, 0x46, 0xdd, 0x47, 0x9b, 0x85, 0xe3, 0x93, 0x9f,
+       0x78, 0x1a, 0x0b, 0x47, 0xcc, 0xc7, 0xe8, 0xe1, 0xfb, 0x37, 0xe6, 0xb6,
+       0xd1, 0xfe, 0xa7, 0xae, 0x50, 0xbc, 0x87, 0x29, 0xf2, 0x73, 0x30, 0x0f,
+       0xa4, 0xd8, 0x69, 0x0c, 0xa6, 0x78, 0x01, 0x3f, 0x87, 0x3a, 0xe6, 0x66,
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+       0x42, 0x55, 0x8c, 0x17, 0xb4, 0x1a, 0xe8, 0xfd, 0xdd, 0xb0, 0x15, 0xe3,
+       0xc1, 0xb7, 0x37, 0x31, 0x2f, 0xda, 0x79, 0x96, 0x90, 0x42, 0xf1, 0xf8,
+       0x3b, 0x84, 0x3c, 0xcb, 0xb1, 0x71, 0xfe, 0xf7, 0x17, 0x71, 0x3e, 0x8f,
+       0x4e, 0x73, 0xda, 0xf8, 0xba, 0x53, 0x76, 0xc5, 0x84, 0x62, 0x91, 0x6e,
+       0x8e, 0xce, 0x92, 0x20, 0xac, 0xf3, 0xc2, 0x57, 0x27, 0x32, 0x15, 0xf4,
+       0x60, 0x8e, 0xc3, 0x67, 0x40, 0x7f, 0x7c, 0x4e, 0xa3, 0xc9, 0x8b, 0xf6,
+       0xe7, 0x84, 0x5f, 0xda, 0x88, 0x4f, 0xce, 0xdb, 0x78, 0x3c, 0x95, 0xd2,
+       0xf8, 0x88, 0x8a, 0xdf, 0x9b, 0xb7, 0x95, 0x15, 0x44, 0xde, 0xb3, 0x0b,
+       0x35, 0x39, 0xbc, 0x28, 0x9f, 0xb6, 0x35, 0x59, 0xbc, 0x18, 0xa3, 0x1e,
+       0x1a, 0x44, 0xbe, 0x66, 0x3b, 0x0d, 0x14, 0xc7, 0xae, 0x1a, 0x78, 0x5c,
+       0x65, 0xbb, 0x58, 0x8f, 0xed, 0x85, 0xb1, 0x94, 0xae, 0x15, 0x72, 0xe6,
+       0x69, 0x25, 0x38, 0x19, 0xe1, 0x7c, 0x1a, 0xe8, 0x89, 0xf1, 0xf3, 0x07,
+       0x57, 0x73, 0xfb, 0x78, 0xd1, 0x52, 0x0b, 0xc1, 0xb1, 0xe8, 0xf5, 0x6c,
+       0xb2, 0xaf, 0x06, 0xc3, 0xdb, 0x33, 0x4d, 0x1e, 0x6f, 0x0e, 0xc2, 0xb3,
+       0xda, 0x90, 0x82, 0xfe, 0xaa, 0xf2, 0x95, 0x39, 0xab, 0xf0, 0x9d, 0x8c,
+       0x45, 0x76, 0xfe, 0x8e, 0xb0, 0x1c, 0x3f, 0x9c, 0xfc, 0xb6, 0xec, 0x77,
+       0x46, 0x86, 0xf6, 0x7c, 0x73, 0xdc, 0xb5, 0xde, 0x59, 0x11, 0xf2, 0x5d,
+       0x8e, 0x1f, 0x5b, 0x80, 0x7c, 0x25, 0xcb, 0xc1, 0x14, 0xf4, 0xe7, 0xfc,
+       0xbc, 0xf0, 0xdc, 0x6d, 0x18, 0x57, 0x0b, 0xf4, 0xdb, 0x84, 0xf9, 0xdd,
+       0xcf, 0xfd, 0xe1, 0x36, 0x8c, 0xa3, 0xdd, 0x69, 0x0f, 0xa6, 0x60, 0x9c,
+       0xed, 0x4b, 0xcf, 0xbd, 0xcf, 0xcb, 0x13, 0x83, 0x9b, 0x30, 0xce, 0xf6,
+       0xe0, 0x73, 0xc7, 0x79, 0x79, 0x7a, 0x30, 0xc5, 0x00, 0xf9, 0xd7, 0x9f,
+       0xfb, 0x90, 0x97, 0xe7, 0x06, 0x37, 0x61, 0xfe, 0xad, 0xe7, 0x4e, 0xf1,
+       0x72, 0x3c, 0x03, 0x03, 0xd9, 0xf9, 0xde, 0x73, 0x9f, 0xde, 0x16, 0x44,
+       0x7f, 0x8b, 0xc9, 0x3b, 0x1f, 0x05, 0xf2, 0x2f, 0x00, 0xfe, 0x22, 0x58,
+       0x62, 0x9d, 0x22, 0xfd, 0x40, 0xe0, 0x45, 0x2b, 0x7f, 0x01, 0xbf, 0xc3,
+       0x06, 0x6c, 0x8f, 0x48, 0xa3, 0xcb, 0xf7, 0x89, 0x76, 0xfb, 0x07, 0x29,
+       0xff, 0x95, 0x28, 0xef, 0x1a, 0xa4, 0xff, 0x03, 0xa2, 0x5d, 0x78, 0x90,
+       0xf6, 0x87, 0x44, 0xbb, 0xc3, 0x83, 0xb4, 0x3f, 0x22, 0xda, 0x1d, 0x1d,
+       0xa4, 0xfc, 0xb7, 0xa2, 0xfc, 0x8d, 0x41, 0xfa, 0xff, 0x77, 0xd1, 0xae,
+       0x7b, 0x90, 0xf6, 0x6f, 0x8b, 0x76, 0xef, 0x0e, 0xd2, 0xfe, 0x0f, 0xa2,
+       0xdd, 0xb1, 0x41, 0xca, 0xdf, 0x17, 0xe5, 0xff, 0x19, 0xd5, 0xff, 0x71,
+       0x51, 0xbf, 0x47, 0x7c, 0xcf, 0xb2, 0xaf, 0x7e, 0x1f, 0xfd, 0xf7, 0x59,
+       0x20, 0x47, 0x50, 0x2e, 0x15, 0xd8, 0x57, 0xbb, 0x70, 0x9d, 0x6f, 0x6b,
+       0x2d, 0x25, 0xfe, 0x6f, 0x2e, 0xe3, 0xe7, 0x54, 0x1a, 0xbf, 0x67, 0x49,
+       0x8c, 0xde, 0xf7, 0xad, 0x2e, 0xe2, 0xef, 0x8a, 0x55, 0x17, 0x71, 0xf9,
+       0xfb, 0x67, 0xd1, 0x3f, 0xf0, 0xe1, 0xe3, 0xc8, 0x77, 0x8b, 0xde, 0x94,
+       0x29, 0xae, 0xa7, 0xd9, 0xe0, 0x3d, 0x1d, 0x42, 0x39, 0xba, 0xca, 0x40,
+       0xf6, 0xc0, 0xa2, 0xd7, 0xf9, 0x7e, 0x7d, 0xd1, 0x4a, 0x25, 0x14, 0x79,
+       0x2f, 0xe7, 0xcf, 0x51, 0xf0, 0x2f, 0x47, 0xf8, 0x80, 0x71, 0x5b, 0x30,
+       0x85, 0xf5, 0x76, 0xa6, 0x90, 0xc7, 0xf5, 0x9b, 0x3d, 0x1e, 0x6f, 0x75,
+       0x84, 0x3c, 0x33, 0x3a, 0xf4, 0x79, 0x90, 0x17, 0x0c, 0xe5, 0x2e, 0xc8,
+       0x6f, 0x8a, 0xdf, 0x2e, 0x58, 0x59, 0xd1, 0x5a, 0x00, 0xf9, 0x54, 0x97,
+       0x81, 0x2c, 0x10, 0xa5, 0xd6, 0x12, 0xc6, 0xf7, 0x3a, 0x14, 0xbb, 0xd0,
+       0x0b, 0x8e, 0xd2, 0xb6, 0x02, 0x84, 0xcf, 0xa6, 0xd0, 0x3b, 0x05, 0x9a,
+       0x9c, 0x67, 0x36, 0x8f, 0xce, 0xaf, 0xd1, 0x62, 0x53, 0xe8, 0xdd, 0x36,
+       0xd9, 0xce, 0xcb, 0x27, 0xfc, 0x72, 0xac, 0x03, 0xed, 0xac, 0x16, 0x16,
+       0xe8, 0xf6, 0x61, 0x7b, 0x8f, 0x42, 0x76, 0xfc, 0xc1, 0xd6, 0x12, 0x07,
+       0xca, 0x3d, 0x93, 0x7d, 0xb6, 0x03, 0xd7, 0xef, 0xbb, 0xc5, 0x7c, 0x5e,
+       0x95, 0x75, 0x05, 0x31, 0x28, 0xaf, 0xe5, 0x47, 0x0d, 0x24, 0xbf, 0x0f,
+       0x3b, 0xf8, 0x7a, 0xdf, 0xea, 0xe1, 0xf1, 0x4e, 0xa0, 0x57, 0xe8, 0x9e,
+       0x13, 0xc8, 0x6b, 0x2f, 0xea, 0x88, 0x7c, 0x16, 0x5e, 0x8a, 0x72, 0x73,
+       0xe7, 0x63, 0xfb, 0x66, 0x70, 0x3f, 0x1f, 0xb3, 0x8f, 0x2a, 0xa3, 0x7b,
+       0x44, 0xda, 0xf9, 0xb6, 0xa4, 0x44, 0xec, 0x03, 0xae, 0x2b, 0xe2, 0xf8,
+       0xc9, 0x10, 0x7a, 0x44, 0x41, 0xfd, 0x02, 0xe9, 0xd3, 0xa5, 0xe2, 0xfe,
+       0x4b, 0x90, 0xfb, 0xa3, 0x32, 0x14, 0xe6, 0x49, 0x8d, 0xb8, 0xc7, 0x7b,
+       0x5d, 0x91, 0xcc, 0xef, 0x1f, 0x29, 0x88, 0x23, 0xe8, 0x4b, 0xae, 0xa6,
+       0xf7, 0xab, 0x86, 0x2e, 0x51, 0x74, 0xe7, 0x08, 0x69, 0x0f, 0xe8, 0xf3,
+       0xa6, 0x28, 0xbd, 0xa1, 0x44, 0xe9, 0x95, 0xec, 0x56, 0x90, 0x93, 0xba,
+       0xf3, 0x13, 0x87, 0x2e, 0x5f, 0x54, 0x24, 0xfc, 0x3c, 0x5e, 0xe6, 0x45,
+       0x3b, 0x76, 0xc2, 0x2f, 0x57, 0x93, 0x3c, 0x3c, 0x8f, 0xfa, 0x4d, 0x1a,
+       0x5c, 0xee, 0xf5, 0xc9, 0x5f, 0x21, 0x8f, 0x9f, 0x46, 0x04, 0xa0, 0x1c,
+       0x0d, 0xf2, 0x7b, 0xe4, 0x07, 0x57, 0x97, 0xfc, 0x16, 0xe9, 0xbd, 0x68,
+       0xa5, 0x81, 0xde, 0x8d, 0xbe, 0x52, 0x39, 0xfa, 0x67, 0x84, 0x05, 0xf0,
+       0x90, 0x1b, 0x90, 0x48, 0x2f, 0xc0, 0x84, 0x52, 0x70, 0xdf, 0x74, 0x39,
+       0x3c, 0xe4, 0x1a, 0xfd, 0x2e, 0x7a, 0x57, 0xe3, 0x32, 0xf8, 0xc8, 0x5d,
+       0x57, 0xea, 0x42, 0x79, 0x9b, 0x1b, 0x50, 0xa8, 0xff, 0x4b, 0xf4, 0xc6,
+       0x65, 0xf0, 0xf5, 0xbc, 0xe4, 0x3d, 0x16, 0x40, 0x3a, 0x3a, 0x63, 0x84,
+       0x5d, 0x0d, 0x0c, 0x80, 0x7e, 0x3b, 0x57, 0x4c, 0x07, 0xc6, 0x17, 0x9b,
+       0x84, 0x3f, 0x45, 0x8b, 0x17, 0x56, 0x86, 0x28, 0xfc, 0x5d, 0x7c, 0x71,
+       0x5f, 0x55, 0x16, 0x7c, 0xfc, 0x30, 0xf3, 0xa9, 0xae, 0x6c, 0x7c, 0x17,
+       0xa8, 0x81, 0xfc, 0xfb, 0x8b, 0x77, 0x3f, 0xe0, 0x41, 0xbb, 0x7d, 0x85,
+       0x21, 0xe0, 0xc0, 0xfc, 0x51, 0xd7, 0xa4, 0x5e, 0x1c, 0x67, 0x11, 0x6c,
+       0xfa, 0x11, 0x7f, 0x3b, 0xb1, 0x0f, 0x7a, 0x1f, 0xf3, 0xb7, 0xb7, 0xfb,
+       0x00, 0xfe, 0xce, 0x90, 0x49, 0x7b, 0xbf, 0x32, 0x8c, 0xff, 0xec, 0xc6,
+       0x38, 0x20, 0xed, 0x7d, 0x4c, 0x0f, 0xd9, 0x6b, 0xa2, 0xfe, 0xb5, 0xb7,
+       0x57, 0x02, 0xde, 0x3b, 0x15, 0x47, 0x21, 0x9a, 0xa0, 0x4b, 0x77, 0x5d,
+       0xb7, 0xde, 0x78, 0x1d, 0xd4, 0x37, 0xb1, 0xbe, 0xfa, 0x78, 0xef, 0xee,
+       0xb9, 0xc3, 0x06, 0xf1, 0x7e, 0xe6, 0xb8, 0xf5, 0x95, 0x20, 0x97, 0x76,
+       0xc7, 0x30, 0xdd, 0xfb, 0xa0, 0xbb, 0xd1, 0xcf, 0x4e, 0xfd, 0x4d, 0x58,
+       0x8f, 0xef, 0x81, 0xc2, 0x78, 0x37, 0xc9, 0xb0, 0x37, 0x5b, 0x5b, 0x74,
+       0xf3, 0x7a, 0x5b, 0x72, 0x3f, 0x3c, 0xeb, 0x8a, 0xa7, 0xac, 0x5f, 0x8a,
+       0x0e, 0x3b, 0xb1, 0x4f, 0x71, 0x32, 0xfe, 0xae, 0xfb, 0x19, 0xb5, 0x27,
+       0x0e, 0x97, 0x0f, 0xec, 0x57, 0x7e, 0x52, 0x04, 0xf4, 0xad, 0xed, 0x38,
+       0x99, 0x14, 0xb9, 0x5f, 0xd7, 0xea, 0xc7, 0x8b, 0xfa, 0x75, 0x5d, 0xbd,
+       0x75, 0xbb, 0x54, 0xaa, 0xbf, 0x94, 0xea, 0xef, 0xef, 0x8d, 0x2b, 0x22,
+       0x7c, 0xf7, 0x96, 0x45, 0xd6, 0x8f, 0x13, 0x7e, 0x80, 0x88, 0xfa, 0x2b,
+       0xbe, 0xad, 0x7e, 0x81, 0x06, 0xcf, 0xae, 0xb7, 0x6f, 0x2f, 0xe2, 0xf5,
+       0x1f, 0xc5, 0xfa, 0x67, 0xd5, 0x9e, 0x24, 0x8a, 0xad, 0x89, 0x82, 0x27,
+       0xe1, 0xd2, 0xfe, 0xd7, 0x7e, 0x5b, 0xff, 0xc3, 0x45, 0xfd, 0x33, 0xe1,
+       0xb7, 0xa9, 0xfe, 0x59, 0xd6, 0x93, 0x54, 0x9c, 0x49, 0xed, 0x36, 0x61,
+       0xbb, 0x73, 0x6f, 0xbc, 0x5d, 0x26, 0xe6, 0x9d, 0x84, 0xe7, 0x38, 0xef,
+       0xda, 0x7c, 0x4f, 0x16, 0x81, 0x5c, 0x6a, 0xc0, 0x3e, 0xd0, 0x7e, 0x56,
+       0x1a, 0x54, 0xfc, 0xde, 0x69, 0x69, 0x73, 0xa0, 0xfd, 0x66, 0x35, 0xb6,
+       0xf9, 0x51, 0x0e, 0xe7, 0xe0, 0x3b, 0x5f, 0x63, 0xfa, 0xd3, 0xad, 0xa8,
+       0x3c, 0x46, 0x5f, 0xfa, 0x3d, 0x9a, 0x9f, 0x3b, 0x2d, 0x2c, 0xa1, 0x1a,
+       0xf9, 0xb5, 0xd1, 0x40, 0xfb, 0x9b, 0xfd, 0x3d, 0x86, 0x47, 0x90, 0x2f,
+       0xb7, 0xa6, 0x8d, 0x75, 0xe0, 0xfe, 0x79, 0xb7, 0xa9, 0xbb, 0xa4, 0x08,
+       0xed, 0xd7, 0xbd, 0x36, 0xb2, 0x5f, 0x0d, 0x19, 0x9f, 0x59, 0xd1, 0x6f,
+       0x6e, 0xce, 0xe7, 0xeb, 0xdf, 0xea, 0x6c, 0xf0, 0x16, 0x41, 0xde, 0x9a,
+       0x5e, 0x44, 0xef, 0x74, 0xca, 0x0f, 0x2d, 0xea, 0xa4, 0xf7, 0xc2, 0x7f,
+       0xca, 0xdf, 0xd1, 0x52, 0x7e, 0x66, 0x0a, 0x6c, 0x47, 0x7e, 0x0c, 0x2f,
+       0x2a, 0x98, 0x13, 0xb1, 0xbe, 0xd7, 0x15, 0x1b, 0x09, 0xbe, 0x95, 0xaf,
+       0xd9, 0x56, 0xe3, 0xfe, 0x60, 0xa5, 0xd1, 0xdb, 0x96, 0x8f, 0x76, 0xb8,
+       0x5d, 0xa1, 0xf8, 0x4b, 0xe5, 0x67, 0xfb, 0x26, 0x91, 0x7d, 0xf8, 0x0b,
+       0x03, 0x23, 0xf9, 0x0f, 0xf3, 0xac, 0x80, 0x7e, 0x5b, 0x66, 0x28, 0xf4,
+       0xfb, 0x0e, 0x4e, 0x14, 0xcf, 0x3c, 0x58, 0x44, 0xf8, 0xf0, 0xfb, 0x2b,
+       0xa0, 0xde, 0xd0, 0x44, 0x45, 0xc2, 0x7b, 0x3a, 0x0f, 0x2b, 0x7e, 0x0b,
+       0x9e, 0x77, 0x98, 0x85, 0x5d, 0xb7, 0xd5, 0xcb, 0xef, 0x69, 0x69, 0xe3,
+       0x7e, 0x2c, 0xec, 0xcf, 0x8f, 0x8b, 0xf8, 0xbb, 0xee, 0x5b, 0xd3, 0x2e,
+       0xbc, 0x37, 0xcf, 0x8d, 0xef, 0x30, 0x98, 0xe8, 0x7e, 0xa5, 0x6d, 0xa1,
+       0x21, 0x6c, 0x8a, 0xc3, 0xfb, 0x66, 0xdb, 0x4e, 0xcf, 0x43, 0x7a, 0xc6,
+       0xf6, 0xac, 0xc4, 0xfb, 0xc6, 0x31, 0x29, 0x8a, 0x03, 0xe7, 0xf7, 0x64,
+       0x35, 0x94, 0xd1, 0xb9, 0x5c, 0x27, 0x7d, 0x0f, 0xd6, 0x1a, 0x68, 0xdf,
+       0x90, 0xb0, 0xd0, 0xe0, 0x43, 0xff, 0x63, 0x4c, 0x8e, 0x49, 0xe7, 0xef,
+       0xb0, 0xc1, 0x38, 0x91, 0xfe, 0x90, 0x6f, 0x8a, 0x03, 0xc7, 0x10, 0xee,
+       0xab, 0xde, 0x54, 0x6e, 0x42, 0x3c, 0x7b, 0xee, 0x37, 0xd0, 0x3b, 0xa4,
+       0x8f, 0x7a, 0xde, 0xb5, 0x18, 0x00, 0xce, 0xb8, 0x52, 0x7d, 0x7b, 0xc7,
+       0x58, 0x7d, 0x7b, 0x57, 0xa5, 0xbe, 0xdc, 0x5d, 0xad, 0x2f, 0x4f, 0x9a,
+       0xaa, 0x2f, 0xf7, 0xdc, 0x6d, 0x8a, 0xf2, 0xeb, 0xe8, 0xf3, 0x33, 0x34,
+       0xbe, 0x02, 0x99, 0x60, 0x03, 0x3d, 0x15, 0xc3, 0x8b, 0x58, 0x8c, 0xed,
+       0x42, 0x13, 0xee, 0x7b, 0x56, 0xbc, 0x16, 0xc3, 0x88, 0x3e, 0x4b, 0xd6,
+       0xb7, 0xe5, 0xe3, 0xfa, 0x8c, 0xed, 0x25, 0x7c, 0xc5, 0x0c, 0x8f, 0x21,
+       0xbf, 0xc0, 0x8a, 0x64, 0x13, 0xc9, 0xf5, 0x15, 0xc5, 0xdc, 0xaf, 0x7f,
+       0x28, 0xdd, 0x74, 0x13, 0xe5, 0x61, 0x5e, 0xc8, 0x1f, 0x5b, 0xd3, 0x8e,
+       0xd0, 0x7e, 0xe4, 0x12, 0xbc, 0xd8, 0x4e, 0x7f, 0x8d, 0xfd, 0xdb, 0x58,
+       0xc4, 0x77, 0xb4, 0x33, 0x8a, 0x7d, 0x7f, 0x29, 0x1a, 0xcd, 0xf3, 0x9e,
+       0x32, 0xf4, 0xe3, 0x31, 0x92, 0x87, 0xcf, 0x4b, 0x3e, 0xef, 0x41, 0xc4,
+       0xf7, 0x5b, 0xdc, 0x5f, 0xb1, 0xb5, 0x91, 0xfb, 0xb1, 0x1f, 0x9d, 0xca,
+       0xe3, 0x11, 0x69, 0x06, 0x65, 0xb8, 0xde, 0x79, 0xfd, 0x38, 0xcb, 0xea,
+       0x6e, 0xdc, 0x97, 0xc5, 0xd9, 0x5a, 0xef, 0xc7, 0x38, 0xcb, 0x68, 0xbc,
+       0x26, 0x89, 0xf3, 0x86, 0xad, 0x78, 0xcb, 0x16, 0xf9, 0x2e, 0xc0, 0xdf,
+       0x67, 0x5e, 0xae, 0xdd, 0x77, 0xc2, 0xef, 0x65, 0x74, 0x7b, 0x81, 0xde,
+       0x1f, 0x1b, 0x3f, 0x82, 0xf3, 0x8b, 0x53, 0xd8, 0x09, 0xf1, 0x9e, 0x84,
+       0xa2, 0x96, 0x88, 0x7b, 0x13, 0x49, 0xc2, 0x6f, 0xf2, 0xf8, 0xd8, 0x99,
+       0x56, 0xd4, 0x1f, 0xbb, 0xc5, 0x7b, 0x1e, 0x7d, 0xfd, 0xa9, 0x34, 0x28,
+       0x0f, 0x3d, 0x45, 0xbf, 0x72, 0xb1, 0x24, 0xf6, 0x53, 0xbc, 0xfd, 0x7a,
+       0xed, 0x9c, 0x47, 0xe4, 0x13, 0x9d, 0x3c, 0xbf, 0xfb, 0xb0, 0xeb, 0x26,
+       0x5c, 0x5f, 0xeb, 0xa7, 0xba, 0x4a, 0x70, 0xbf, 0xbf, 0x42, 0xd8, 0x77,
+       0xf1, 0x69, 0x26, 0xdf, 0x30, 0x98, 0xd7, 0xda, 0xa3, 0xa6, 0xa0, 0x34,
+       0x12, 0xf2, 0x0a, 0x3b, 0x6c, 0x04, 0xbb, 0x60, 0xb7, 0x8b, 0x8f, 0x6b,
+       0x7a, 0x3d, 0x26, 0x88, 0xf7, 0xf3, 0xd6, 0x7a, 0x4a, 0xe9, 0xbe, 0xdf,
+       0x75, 0x62, 0xbc, 0x17, 0xca, 0xbd, 0xef, 0xe0, 0x7a, 0xef, 0x85, 0x75,
+       0x84, 0x71, 0x5f, 0x6b, 0xdd, 0x5e, 0x6b, 0x89, 0x38, 0x37, 0x0d, 0x02,
+       0x7c, 0x68, 0x5a, 0xe0, 0x3e, 0xe5, 0x60, 0x75, 0x09, 0xed, 0x77, 0xd7,
+       0xfa, 0xbc, 0x56, 0xd4, 0x9b, 0x6b, 0xd3, 0xbc, 0x56, 0x8c, 0x97, 0xb6,
+       0x26, 0x2b, 0x0e, 0x8c, 0x07, 0x75, 0x79, 0x14, 0x7a, 0x8f, 0x6d, 0xad,
+       0x25, 0xe0, 0x40, 0xfb, 0xc7, 0x05, 0x8a, 0xd4, 0x84, 0xe7, 0x49, 0xe9,
+       0x6d, 0x13, 0xe9, 0x9e, 0x1b, 0xe0, 0xda, 0x50, 0xc6, 0x8f, 0x1a, 0x98,
+       0x88, 0x33, 0xc4, 0x38, 0xbf, 0x04, 0x81, 0xcf, 0xad, 0x9e, 0xd9, 0x0e,
+       0x7c, 0x1f, 0xc1, 0x9d, 0xb3, 0xe7, 0x47, 0xe8, 0xa7, 0x4f, 0xc0, 0xfe,
+       0xe2, 0x78, 0x3b, 0xc4, 0x93, 0x53, 0xe0, 0x69, 0x7c, 0xb1, 0x4a, 0x70,
+       0xbb, 0x45, 0xff, 0x09, 0xb3, 0x5f, 0xa0, 0xfa, 0xf8, 0xd3, 0x52, 0x16,
+       0xd1, 0x9f, 0xa0, 0xa3, 0x69, 0x22, 0x0b, 0xe1, 0x3e, 0x4d, 0x1b, 0x5f,
+       0xeb, 0xa7, 0xaf, 0x7f, 0xe6, 0xa3, 0x73, 0x80, 0xe5, 0xbf, 0xe5, 0x78,
+       0x5b, 0x9a, 0xce, 0xdf, 0xa1, 0x32, 0xdd, 0xc7, 0x68, 0x3f, 0xf7, 0x42,
+       0x79, 0x60, 0x27, 0xf2, 0x59, 0x6f, 0x72, 0x0c, 0xc9, 0xbb, 0x14, 0x4f,
+       0x4a, 0x05, 0xf2, 0x51, 0xca, 0xd1, 0x4d, 0x93, 0xf1, 0xfe, 0xc3, 0xf2,
+       0xdf, 0xc6, 0xf0, 0x71, 0xe6, 0x70, 0x7e, 0x4f, 0x51, 0x98, 0xe5, 0x7a,
+       0x9c, 0x77, 0x62, 0xc0, 0x81, 0x78, 0x8c, 0x5e, 0xaf, 0xc9, 0x87, 0xdb,
+       0x6a, 0x90, 0x29, 0x35, 0xba, 0x44, 0xaf, 0xdf, 0x64, 0x85, 0xb5, 0xca,
+       0xae, 0x4b, 0xd7, 0x71, 0xb2, 0xc7, 0x5d, 0x91, 0x37, 0x62, 0x80, 0xf5,
+       0x1c, 0xb5, 0x5e, 0x92, 0x8f, 0xf6, 0x3e, 0x88, 0xfd, 0x47, 0xaf, 0xeb,
+       0x2d, 0xb1, 0xc7, 0x47, 0x71, 0x3d, 0x12, 0xf1, 0x5d, 0xbe, 0x7c, 0xbe,
+       0x45, 0xea, 0x59, 0x49, 0x72, 0x38, 0x59, 0xa1, 0x75, 0x96, 0x1e, 0x35,
+       0x1e, 0xbe, 0x67, 0x87, 0x79, 0x89, 0x19, 0x54, 0x8c, 0x4f, 0x5e, 0x57,
+       0xec, 0xd4, 0xde, 0xad, 0x52, 0x11, 0xaf, 0xbb, 0x4d, 0x8e, 0x71, 0x36,
+       0x7e, 0xde, 0x4e, 0xfc, 0x55, 0xf1, 0xe2, 0xea, 0xbb, 0x7e, 0x07, 0xf9,
+       0x0b, 0xf8, 0x7b, 0x73, 0xa0, 0x56, 0xea, 0xd1, 0xb6, 0x6e, 0xd2, 0x8b,
+       0xfb, 0x03, 0xf9, 0x58, 0x7f, 0xb3, 0x12, 0x78, 0x0a, 0xfd, 0xe9, 0x9b,
+       0x8f, 0x0d, 0xa1, 0x77, 0x22, 0xcd, 0xb1, 0xfc, 0x9d, 0x4f, 0x53, 0xd4,
+       0xbb, 0x25, 0x9a, 0xbe, 0x58, 0x57, 0xcc, 0xf7, 0x31, 0x6a, 0xd4, 0xfb,
+       0x96, 0xdf, 0x35, 0xed, 0x4c, 0x4b, 0x2b, 0x74, 0x00, 0xcf, 0xac, 0x7b,
+       0xfe, 0xb7, 0x7f, 0xb0, 0x24, 0xfe, 0xe3, 0xed, 0x9f, 0xb4, 0xc3, 0x9d,
+       0x4b, 0x6d, 0xb0, 0xa6, 0xb7, 0xec, 0xba, 0x65, 0x3d, 0xc6, 0x47, 0x5a,
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+       0x7e, 0xb4, 0x56, 0x3f, 0xec, 0x9e, 0x82, 0xf5, 0x17, 0xf2, 0xfa, 0xdf,
+       0x3b, 0xad, 0xaf, 0xef, 0x2f, 0xdf, 0x1b, 0x5d, 0x9f, 0xe0, 0xbb, 0xe1,
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+       0x2b, 0xab, 0x17, 0x3d, 0x8f, 0x29, 0x55, 0xe6, 0x41, 0xf0, 0xce, 0xeb,
+       0xdf, 0x31, 0xed, 0xca, 0xfa, 0xfd, 0xfe, 0xfc, 0x6f, 0xaf, 0x77, 0x4f,
+       0x63, 0xf4, 0x38, 0x41, 0xed, 0xfc, 0x48, 0x67, 0x8f, 0x24, 0x34, 0x72,
+       0xfb, 0xdd, 0xc1, 0x7a, 0x29, 0xce, 0x44, 0xb3, 0x3b, 0x5c, 0xcc, 0x21,
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+       0xb8, 0x6f, 0x9f, 0x35, 0xf9, 0xd0, 0x2e, 0x7d, 0x5b, 0xc4, 0x23, 0xdf,
+       0xc1, 0x82, 0xf4, 0xfd, 0x4e, 0x16, 0xa2, 0xf4, 0xfb, 0x2c, 0x4c, 0xf5,
+       0x7f, 0x80, 0x2f, 0xb7, 0x42, 0xfe, 0xad, 0xd8, 0x11, 0xe9, 0x8d, 0x00,
+       0x5f, 0xcd, 0x13, 0xf9, 0xb9, 0xb8, 0x1e, 0x23, 0xf0, 0xfe, 0x8a, 0xe0,
+       0x97, 0x7b, 0xdc, 0x9c, 0x5f, 0x3e, 0x1e, 0x82, 0x78, 0x6f, 0x4f, 0xbc,
+       0x22, 0xfe, 0xad, 0x91, 0x38, 0xfe, 0x96, 0x8c, 0x08, 0x1c, 0xc1, 0x79,
+       0x8f, 0xb3, 0xa8, 0x6e, 0x2f, 0xc2, 0xe4, 0x18, 0x97, 0x86, 0x7e, 0x94,
+       0xbe, 0xf5, 0x53, 0x99, 0xc8, 0xf9, 0x4f, 0x71, 0xe4, 0x7e, 0xdb, 0xfa,
+       0xe9, 0x3e, 0xaf, 0xdd, 0xbb, 0xf7, 0xd9, 0x92, 0xcb, 0xf0, 0xdd, 0x2d,
+       0xfe, 0x73, 0xa3, 0xef, 0x3e, 0x8a, 0x17, 0xc7, 0xb8, 0x7c, 0x37, 0xd0,
+       0xa1, 0x5b, 0xe5, 0xf7, 0x0d, 0x41, 0x6c, 0xd8, 0x83, 0x40, 0xa7, 0xaa,
+       0x72, 0x99, 0xe2, 0xf6, 0x56, 0x7c, 0x2e, 0xee, 0x49, 0xa3, 0x13, 0x03,
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+       0xfe, 0x6e, 0x49, 0xe3, 0xf7, 0x06, 0xab, 0xcb, 0xa7, 0xb4, 0xc4, 0x03,
+       0x5e, 0x26, 0x7c, 0xd5, 0x53, 0x1a, 0x86, 0xb4, 0x2a, 0x4d, 0x7f, 0x8f,
+       0x70, 0xa2, 0xbb, 0x83, 0x9e, 0x0e, 0x9f, 0x94, 0xa3, 0xff, 0x7e, 0x13,
+       0x6b, 0xa3, 0x03, 0xe2, 0xea, 0x22, 0x7d, 0x9c, 0xf9, 0x2d, 0x51, 0xfe,
+       0xcf, 0x83, 0x38, 0x36, 0xf0, 0xd5, 0x27, 0x23, 0x44, 0xbc, 0xe4, 0x70,
+       0x36, 0x3c, 0xf2, 0xbe, 0xc1, 0xad, 0xa2, 0xed, 0xf9, 0xea, 0x2f, 0x4c,
+       0xe7, 0x60, 0xfc, 0xf4, 0x91, 0x81, 0x5e, 0xc4, 0xe3, 0xa2, 0x9b, 0xff,
+       0x38, 0x9d, 0xf6, 0x75, 0x0a, 0x7b, 0xf3, 0x2a, 0x98, 0x5f, 0xdd, 0xbf,
+       0xcb, 0x64, 0x4f, 0x7e, 0xd8, 0x04, 0x33, 0xc9, 0xc7, 0xb8, 0x6a, 0x0b,
+       0xf3, 0x81, 0xc1, 0x7f, 0x0a, 0xec, 0x0a, 0xcc, 0x9f, 0x6e, 0xf2, 0x50,
+       0xfa, 0x29, 0xd8, 0x01, 0x98, 0x7e, 0xd6, 0x54, 0x40, 0xe5, 0x67, 0x9b,
+       0xbc, 0x94, 0x1f, 0x3f, 0xd2, 0xff, 0x17, 0xa4, 0xf3, 0xcc, 0xd6, 0xcf,
+       0x15, 0xd4, 0x47, 0x2b, 0xb4, 0x78, 0x6c, 0x01, 0x87, 0x16, 0x57, 0xb8,
+       0x42, 0xc4, 0x4f, 0x2c, 0xb6, 0x2f, 0x3a, 0x86, 0xf1, 0x0b, 0x8b, 0x29,
+       0xe0, 0x9d, 0xc1, 0x62, 0x6f, 0x9b, 0x80, 0xe0, 0xdf, 0xbb, 0xbf, 0xf3,
+       0x08, 0xa6, 0xf0, 0x5d, 0xc6, 0x7d, 0xc8, 0xe2, 0x35, 0x12, 0xf9, 0x75,
+       0xe6, 0x1c, 0x0e, 0x2c, 0x47, 0x32, 0xcf, 0x7b, 0xa3, 0xe7, 0x16, 0x14,
+       0x13, 0xa3, 0x7f, 0x7f, 0x32, 0x09, 0xf7, 0xe9, 0xb5, 0x68, 0xc7, 0x02,
+       0xeb, 0x2f, 0x76, 0xf9, 0x2c, 0x23, 0x61, 0x7c, 0x5f, 0xd7, 0x89, 0x23,
+       0x09, 0x50, 0xff, 0xe3, 0xa6, 0x31, 0x04, 0xdf, 0x27, 0x4d, 0x3e, 0x82,
+       0xef, 0x4f, 0x4d, 0x55, 0x94, 0x4e, 0x1f, 0xe9, 0x8f, 0xa3, 0x7a, 0xec,
+       0x73, 0x7a, 0x6f, 0xe9, 0xe6, 0x5d, 0x27, 0x14, 0xfc, 0x3d, 0x68, 0xe3,
+       0x7d, 0x12, 0xf9, 0xef, 0xaf, 0xf7, 0xb1, 0x50, 0x08, 0xf0, 0xba, 0xc1,
+       0xc8, 0xe5, 0xfb, 0x06, 0x90, 0xef, 0xb8, 0x3e, 0xcb, 0x8b, 0x27, 0x6f,
+       0x79, 0x00, 0xe1, 0x1b, 0x11, 0xf0, 0x8c, 0x04, 0xfc, 0xdd, 0xe6, 0x9a,
+       0x35, 0x3e, 0x01, 0xbe, 0xdf, 0x32, 0x66, 0x86, 0x82, 0xf5, 0xee, 0xf8,
+       0x0a, 0x74, 0x50, 0x66, 0x3f, 0x1f, 0x5e, 0x8e, 0xaf, 0xcf, 0x1c, 0x90,
+       0x08, 0x3f, 0x67, 0x0e, 0x38, 0x09, 0x1f, 0x1a, 0x9e, 0x6a, 0x05, 0xbd,
+       0xce, 0xec, 0x2b, 0xbc, 0x15, 0xdf, 0x1f, 0x3b, 0x70, 0x54, 0xa6, 0xf8,
+       0xd3, 0xf3, 0x17, 0x0d, 0x04, 0xdf, 0xf9, 0x63, 0x31, 0x14, 0x9f, 0x1a,
+       0xdd, 0x7e, 0xd1, 0xde, 0xec, 0x21, 0x68, 0x8f, 0xfd, 0x09, 0xe8, 0x87,
+       0x07, 0x1f, 0x8b, 0xf6, 0x16, 0x92, 0x3f, 0xfe, 0x4f, 0xcf, 0xff, 0x48,
+       0x8d, 0x8c, 0xfb, 0xfd, 0x93, 0xab, 0xf3, 0xc2, 0xfb, 0x28, 0xa7, 0xfe,
+       0x8b, 0xcb, 0x29, 0xb0, 0x37, 0x4f, 0x6d, 0x42, 0x39, 0x96, 0x96, 0x42,
+       0xef, 0xe8, 0xf4, 0xc5, 0xab, 0xb1, 0x86, 0x58, 0xd4, 0x63, 0x75, 0x26,
+       0xb1, 0xbe, 0x40, 0xce, 0x60, 0xfe, 0x4f, 0x31, 0x7c, 0x1f, 0x5c, 0xf6,
+       0x8b, 0xd4, 0x0a, 0x5c, 0x2f, 0x38, 0x1e, 0xc6, 0x7b, 0x99, 0xc5, 0xef,
+       0x9b, 0x80, 0xfe, 0x8e, 0xff, 0x18, 0xfa, 0xdb, 0xb7, 0xc9, 0x43, 0xef,
+       0xee, 0x7c, 0xb6, 0xfb, 0x89, 0x2c, 0x1c, 0x7f, 0x67, 0xe7, 0x9c, 0xf7,
+       0x37, 0x41, 0xff, 0x67, 0x42, 0xfc, 0xf7, 0x4d, 0x9c, 0x61, 0x9d, 0x67,
+       0x7f, 0x85, 0xf2, 0x74, 0xbb, 0x8d, 0xfc, 0x96, 0x2b, 0x24, 0x80, 0x0b,
+       0xf5, 0xe9, 0x8e, 0x14, 0xca, 0x17, 0x48, 0x4a, 0x4c, 0x23, 0x39, 0x33,
+       0x42, 0xb4, 0x6e, 0x0b, 0x24, 0x55, 0xc1, 0x77, 0xc8, 0x16, 0xbe, 0xb0,
+       0x31, 0x05, 0xf9, 0x0b, 0xef, 0x8b, 0x63, 0x5c, 0xfd, 0xcb, 0x6b, 0x62,
+       0x49, 0x4e, 0xbd, 0x6c, 0xf4, 0x1e, 0x6f, 0xc4, 0xfe, 0xb6, 0xf0, 0xfe,
+       0x9e, 0x7d, 0xec, 0xa1, 0x0f, 0xf7, 0x63, 0xfa, 0x68, 0x6d, 0xc9, 0x43,
+       0x90, 0xde, 0x3e, 0xd2, 0x45, 0x78, 0x9f, 0xfd, 0x2f, 0x0b, 0x86, 0x63,
+       0x7b, 0xd0, 0xd7, 0xf4, 0x7b, 0x95, 0x9f, 0x7b, 0x51, 0x0a, 0xa3, 0x1f,
+       0xa4, 0xb8, 0xfd, 0xe0, 0x32, 0x8c, 0x63, 0x1a, 0xb9, 0xf9, 0x84, 0x21,
+       0x05, 0xd2, 0x51, 0xdb, 0xa5, 0x66, 0x4c, 0x0b, 0xd3, 0x27, 0x1d, 0x45,
+       0xff, 0xc1, 0xdd, 0x23, 0x55, 0x82, 0xe3, 0xaa, 0x5d, 0x99, 0x32, 0xc6,
+       0xa6, 0x0f, 0x4f, 0x09, 0xbd, 0x7f, 0x03, 0x8f, 0x1b, 0xd1, 0xe9, 0xf7,
+       0xa2, 0xf6, 0xcf, 0x2b, 0x70, 0x9b, 0xa9, 0xe9, 0xf9, 0xe1, 0x52, 0xe7,
+       0xa7, 0x1d, 0xb8, 0x2f, 0x1e, 0x7a, 0xac, 0x84, 0xdf, 0xef, 0xe2, 0xef,
+       0x44, 0xef, 0xed, 0x9a, 0xf2, 0xce, 0xf7, 0x19, 0xce, 0x03, 0x2c, 0x08,
+       0x84, 0x7b, 0x86, 0x89, 0xe2, 0x2e, 0x58, 0x28, 0xd8, 0x81, 0x74, 0x3e,
+       0x13, 0x28, 0xf0, 0xd2, 0xfb, 0x26, 0xfe, 0xe0, 0x46, 0xe4, 0xaf, 0x33,
+       0x81, 0x24, 0x7a, 0x4f, 0x7a, 0x9f, 0x21, 0x18, 0x87, 0xbf, 0x2f, 0x29,
+       0x78, 0x9c, 0xff, 0x5e, 0x9f, 0x17, 0xb7, 0xbf, 0x15, 0x87, 0xf1, 0x14,
+       0xf1, 0x7b, 0x8c, 0x0c, 0x7f, 0xff, 0x74, 0xed, 0xa8, 0xde, 0x09, 0x14,
+       0x1f, 0x92, 0xae, 0xd2, 0x7e, 0x3c, 0x7d, 0xeb, 0x8d, 0x55, 0x88, 0x9f,
+       0xba, 0x3d, 0x7b, 0x3b, 0xa8, 0x9f, 0x85, 0x16, 0x2f, 0xfa, 0x63, 0xe7,
+       0xef, 0xfd, 0x82, 0xee, 0xbd, 0xb0, 0x89, 0x3c, 0x0e, 0xf5, 0xcc, 0x1e,
+       0x9e, 0x7f, 0xa4, 0xd2, 0x47, 0xef, 0x8a, 0xcf, 0xef, 0xf8, 0x33, 0xcf,
+       0x77, 0xfb, 0x29, 0xef, 0x97, 0x83, 0x99, 0x74, 0x7f, 0x62, 0x16, 0xb7,
+       0x77, 0x9e, 0x10, 0xfa, 0x8c, 0xf5, 0x8c, 0x60, 0x91, 0xef, 0x12, 0x69,
+       0xf4, 0x7a, 0x04, 0x8a, 0xb1, 0x7c, 0x43, 0x66, 0x30, 0x19, 0xdf, 0x9f,
+       0xd2, 0xf4, 0x20, 0xe8, 0xaf, 0x26, 0x5c, 0x7f, 0xe8, 0x76, 0xa4, 0xf6,
+       0x8e, 0x29, 0xfc, 0xbe, 0xfa, 0x15, 0xea, 0x2f, 0x93, 0xd0, 0x47, 0x5a,
+       0x7f, 0x4f, 0x98, 0xf8, 0x7b, 0xb9, 0x28, 0x46, 0xf0, 0xf7, 0xcf, 0x6c,
+       0x36, 0x71, 0xbd, 0xbb, 0x03, 0xe4, 0x0d, 0xf2, 0x8b, 0xa6, 0x77, 0x61,
+       0xdc, 0xc7, 0x71, 0x5c, 0x93, 0xb8, 0x2f, 0x93, 0x0a, 0x4a, 0x76, 0x14,
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+       0xc5, 0x10, 0xd6, 0xab, 0x93, 0xc1, 0x8e, 0xca, 0x8e, 0xb0, 0xa3, 0x2c,
+       0x57, 0xa6, 0x17, 0xff, 0x96, 0xea, 0x7b, 0x06, 0xdb, 0x5f, 0x69, 0xfd,
+       0x68, 0x39, 0x3c, 0x56, 0xc0, 0xbf, 0xd8, 0x6e, 0x20, 0x3c, 0x2c, 0x5e,
+       0x67, 0x26, 0x7f, 0xd8, 0x58, 0x71, 0xbf, 0x74, 0xec, 0xf9, 0x63, 0xb1,
+       0x28, 0x4f, 0x16, 0xff, 0xb9, 0x84, 0xe4, 0x4a, 0x33, 0x63, 0x03, 0xe2,
+       0xe7, 0x95, 0x26, 0x1e, 0xe7, 0xfd, 0x6b, 0xf4, 0x23, 0x40, 0x7a, 0xdd,
+       0x97, 0x3d, 0x32, 0xed, 0x47, 0x0e, 0x1b, 0x16, 0x1e, 0x01, 0xfd, 0x4a,
+       0x20, 0x90, 0xff, 0xb0, 0xb7, 0x39, 0xbe, 0x94, 0xf2, 0x3e, 0x24, 0xf7,
+       0xf5, 0x5f, 0x1a, 0x06, 0xdc, 0x2f, 0x6a, 0x29, 0xd0, 0xeb, 0x35, 0x9c,
+       0x9f, 0xef, 0x2b, 0xbd, 0xff, 0xe1, 0x86, 0xaf, 0x1c, 0xf4, 0xfb, 0x29,
+       0x99, 0xcd, 0x75, 0x45, 0xf3, 0xee, 0x7f, 0x67, 0x47, 0x3f, 0x7f, 0xed,
+       0xbd, 0x2b, 0x98, 0x5f, 0x0f, 0xea, 0xf7, 0xc5, 0x9f, 0x1b, 0x88, 0x7f,
+       0x17, 0x7f, 0x5e, 0x42, 0x72, 0xb3, 0xeb, 0x0a, 0xe7, 0x6b, 0x75, 0xfb,
+       0xfe, 0x03, 0xe9, 0x1a, 0x3d, 0x1f, 0x80, 0xff, 0xbf, 0x06, 0x82, 0xbf,
+       0x8f, 0xdf, 0x7b, 0xaf, 0x0c, 0xfe, 0x07, 0x25, 0x46, 0xbf, 0xd7, 0x07,
+       0xd4, 0x15, 0xf9, 0xb7, 0xbb, 0xc4, 0x7b, 0x02, 0x5d, 0x0b, 0x8a, 0xe8,
+       0x5d, 0x8b, 0x7d, 0xf8, 0x2e, 0x08, 0xca, 0xcd, 0xc9, 0xfc, 0xde, 0x51,
+       0x17, 0xf6, 0x0d, 0xf5, 0xbb, 0x12, 0x1d, 0xf4, 0xee, 0xc6, 0xcb, 0x46,
+       0x9e, 0x0f, 0xde, 0x29, 0xda, 0x8b, 0x77, 0x1a, 0xbb, 0xee, 0x4c, 0xe1,
+       0xef, 0x66, 0x98, 0x1b, 0x7e, 0x57, 0x8c, 0xfd, 0x37, 0xf3, 0xf8, 0xb8,
+       0x2e, 0x63, 0x88, 0x7e, 0x1f, 0x6c, 0xd7, 0x4f, 0x13, 0xe8, 0x3e, 0x81,
+       0x16, 0x3f, 0x7e, 0x4c, 0xc8, 0xed, 0x66, 0x29, 0xfc, 0x7d, 0x7a, 0x0f,
+       0xe4, 0x73, 0x13, 0xe3, 0xef, 0xea, 0x85, 0x53, 0xeb, 0x4b, 0xf1, 0x1d,
+       0x90, 0xe1, 0x54, 0xff, 0x98, 0xf8, 0xfd, 0xc9, 0x57, 0xfa, 0xae, 0xde,
+       0x5d, 0x82, 0x3e, 0xed, 0x1d, 0xa1, 0x1d, 0xeb, 0x01, 0x8e, 0xff, 0x07,
+       0x35, 0x8a, 0x15, 0xa9, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+       0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
+       0x0b, 0x78, 0x94, 0xd5, 0xb5, 0xe8, 0xfe, 0xe7, 0x9f, 0x99, 0xcc, 0x24,
+       0x93, 0x64, 0x12, 0x42, 0x1e, 0x84, 0x84, 0xc9, 0x83, 0x10, 0x24, 0xe0,
+       0xe4, 0x05, 0x01, 0x42, 0x18, 0x20, 0xa1, 0xa8, 0x68, 0x03, 0x08, 0x02,
+       0xc6, 0x38, 0x21, 0x21, 0x84, 0xbc, 0x08, 0x48, 0xcf, 0x49, 0x2d, 0x35,
+       0x83, 0x09, 0x0f, 0x15, 0x6b, 0x38, 0x46, 0x8d, 0x8a, 0x3a, 0x58, 0xa0,
+       0xa0, 0x60, 0x07, 0x05, 0x44, 0x0d, 0x9e, 0x01, 0xd4, 0x52, 0x1f, 0x35,
+       0xd5, 0xea, 0xb1, 0xda, 0x62, 0x02, 0x88, 0x0f, 0x1e, 0x09, 0x41, 0xfd,
+       0xb0, 0xd7, 0xdb, 0xde, 0xb5, 0xd6, 0xde, 0x3b, 0x33, 0xff, 0x24, 0x51,
+       0xdb, 0x73, 0xfd, 0xee, 0x77, 0xbe, 0xef, 0xa6, 0x5f, 0xdd, 0xec, 0x7f,
+       0xbf, 0xd7, 0x5a, 0x7b, 0xed, 0xb5, 0xd7, 0x63, 0x4f, 0xdb, 0xbc, 0x74,
+       0xbb, 0xcb, 0xc6, 0xd8, 0x08, 0x95, 0x35, 0x78, 0x32, 0x18, 0x6b, 0x4b,
+       0x72, 0xc4, 0x45, 0x42, 0xfa, 0xa1, 0x81, 0x2d, 0xc6, 0xfc, 0x9f, 0x19,
+       0xfc, 0xc5, 0x31, 0xf6, 0x98, 0x81, 0xb9, 0xcc, 0x91, 0x8c, 0x5d, 0x65,
+       0x5f, 0x16, 0x6d, 0x1f, 0xce, 0x98, 0xf3, 0x86, 0x10, 0x3d, 0x0b, 0xc7,
+       0x42, 0x47, 0x9c, 0x92, 0xc3, 0xd8, 0x23, 0x15, 0xa3, 0xd9, 0xdd, 0x0a,
+       0x64, 0x5b, 0x1f, 0x62, 0x2c, 0x9a, 0xb1, 0xc5, 0x26, 0x46, 0x7f, 0x4b,
+       0x83, 0xc3, 0x26, 0xb0, 0xab, 0xe9, 0x9f, 0x0e, 0xd3, 0x44, 0xc6, 0x16,
+       0xf2, 0xcf, 0x6c, 0xc9, 0xf2, 0x9d, 0x66, 0xa7, 0x05, 0xf2, 0x55, 0xe6,
+       0x6e, 0x65, 0x02, 0x63, 0x1f, 0x54, 0xdd, 0x19, 0x6a, 0x83, 0xf1, 0x16,
+       0x3a, 0x55, 0x6f, 0x50, 0x18, 0x54, 0xb8, 0xb1, 0xc8, 0xd1, 0x95, 0xce,
+       0xeb, 0xfe, 0x23, 0x19, 0xc7, 0x75, 0xd0, 0xb8, 0xac, 0x62, 0x18, 0x63,
+       0x93, 0x21, 0xd5, 0x7b, 0xcb, 0x19, 0x8c, 0xfb, 0x72, 0xaf, 0x89, 0xdd,
+       0x9d, 0x04, 0x75, 0xf0, 0x6f, 0xba, 0x2f, 0x65, 0xcc, 0xc5, 0x18, 0xd4,
+       0xff, 0xcc, 0xcc, 0xc7, 0xaf, 0xf3, 0xcc, 0xb8, 0xff, 0x8c, 0xec, 0x0f,
+       0xfe, 0x5f, 0x65, 0xb4, 0x6c, 0x56, 0xc2, 0xb1, 0x3c, 0xd1, 0xcd, 0x60,
+       0xfc, 0xfd, 0x23, 0x9c, 0xa3, 0xed, 0xb9, 0x8c, 0xad, 0x3a, 0x7c, 0xcd,
+       0xfd, 0x67, 0x4c, 0xbe, 0x7a, 0x15, 0xcb, 0x8b, 0xd2, 0x98, 0xce, 0x37,
+       0x6e, 0xe0, 0x38, 0x81, 0xe3, 0x35, 0xbb, 0x75, 0x2e, 0x03, 0x8c, 0x37,
+       0xca, 0xb4, 0x20, 0xe3, 0x0c, 0x34, 0x69, 0x86, 0x02, 0x1d, 0xcc, 0xd3,
+       0xe5, 0x31, 0xbb, 0x77, 0x26, 0xe1, 0xbc, 0x7b, 0xff, 0xbc, 0x02, 0xf2,
+       0xcd, 0x8b, 0xaf, 0xb2, 0xdf, 0x0d, 0xd9, 0x39, 0xf3, 0x4d, 0x0e, 0x25,
+       0x8a, 0xb1, 0xbe, 0x03, 0x41, 0xee, 0x20, 0x05, 0xbf, 0x07, 0x3b, 0x70,
+       0x5d, 0xcd, 0x47, 0x42, 0xdd, 0x3a, 0xc8, 0xdf, 0xaa, 0x70, 0xf8, 0x37,
+       0x2b, 0x8c, 0xbe, 0xbb, 0xf6, 0x1b, 0xdc, 0x3b, 0xe1, 0x5b, 0xad, 0xd1,
+       0xbd, 0x67, 0x17, 0xb4, 0xab, 0x7d, 0x79, 0xac, 0x1d, 0x46, 0x66, 0x87,
+       0x8c, 0xf0, 0x1f, 0x2c, 0x7f, 0x31, 0x84, 0x97, 0x87, 0x39, 0x92, 0x36,
+       0xe4, 0x60, 0x79, 0x0c, 0xe1, 0xf7, 0x25, 0x83, 0x2d, 0x9c, 0xca, 0x7f,
+       0xaf, 0x32, 0x2a, 0x0f, 0xf6, 0xa6, 0x45, 0x00, 0xbc, 0x1b, 0x63, 0x9d,
+       0xb3, 0x10, 0xae, 0x23, 0x82, 0x00, 0xff, 0x16, 0xec, 0x97, 0x7f, 0x3f,
+       0x89, 0xeb, 0x00, 0xf8, 0x9c, 0x84, 0x6e, 0x11, 0xbf, 0xae, 0x86, 0x50,
+       0xea, 0x97, 0x89, 0xbc, 0xf3, 0x17, 0xc3, 0xdc, 0x77, 0xd3, 0x7a, 0x1c,
+       0x71, 0xcb, 0x31, 0x7f, 0xdb, 0x38, 0x5a, 0x8f, 0x13, 0xe7, 0x01, 0xf3,
+       0x62, 0xf5, 0x0a, 0xad, 0xf7, 0xa4, 0xd5, 0x7d, 0x57, 0x1a, 0x94, 0x9f,
+       0xec, 0x18, 0x4e, 0xf3, 0x88, 0x12, 0xf4, 0x70, 0xb2, 0xf8, 0xeb, 0xb7,
+       0x26, 0x41, 0xbd, 0x93, 0x87, 0x55, 0x3b, 0xf6, 0xf9, 0x97, 0x46, 0xd5,
+       0x6b, 0x0c, 0xc3, 0x72, 0x8e, 0x0f, 0x65, 0xbe, 0x29, 0xad, 0x1d, 0xda,
+       0x9d, 0x7e, 0x31, 0xd4, 0x1e, 0x04, 0xe5, 0x25, 0xf7, 0xd5, 0xbc, 0x89,
+       0xdf, 0x4b, 0xee, 0xac, 0x9b, 0x4b, 0x69, 0xf5, 0xba, 0x1b, 0x18, 0xd4,
+       0xef, 0xba, 0xf3, 0xa3, 0x44, 0x67, 0xc6, 0x40, 0x7c, 0x94, 0xd4, 0x42,
+       0x2b, 0x3f, 0x3c, 0xae, 0xb2, 0x3b, 0x4a, 0x11, 0xbf, 0xf7, 0xd8, 0x9d,
+       0x65, 0xb8, 0xde, 0x55, 0x19, 0x5d, 0x95, 0x0c, 0xe8, 0xea, 0xa2, 0xb1,
+       0xf3, 0x71, 0xa6, 0x32, 0xf6, 0xfe, 0x48, 0x67, 0x05, 0x7e, 0xef, 0x79,
+       0xe1, 0xd3, 0x5d, 0xf8, 0x1d, 0xf0, 0x94, 0x56, 0x3c, 0x1e, 0x96, 0xa1,
+       0x07, 0x3a, 0x41, 0xfa, 0xed, 0x9a, 0x40, 0x74, 0xbd, 0x4a, 0xd0, 0xef,
+       0xb0, 0x4c, 0x67, 0x35, 0xf6, 0x07, 0x70, 0x2c, 0x65, 0x29, 0x8c, 0x85,
+       0x64, 0x74, 0x1a, 0x71, 0x1e, 0x6c, 0xdd, 0xf0, 0x1f, 0x44, 0x27, 0x5f,
+       0x74, 0xec, 0x3c, 0xa4, 0xc0, 0x38, 0x35, 0xc1, 0x1d, 0xf5, 0x94, 0xaa,
+       0xee, 0x09, 0xd8, 0xcf, 0x39, 0xc5, 0x1b, 0xa6, 0xa4, 0x10, 0x1c, 0x9d,
+       0xb8, 0xff, 0xce, 0x5b, 0xbd, 0x61, 0x88, 0x0f, 0xa7, 0x0e, 0xf2, 0x80,
+       0x9f, 0x9a, 0xdd, 0xda, 0x75, 0xe1, 0x9f, 0x1e, 0xe6, 0x55, 0x83, 0xff,
+       0x80, 0x76, 0x35, 0x1e, 0xd5, 0x61, 0xc6, 0xfd, 0xc3, 0xdc, 0x46, 0x9c,
+       0x7f, 0x0d, 0x33, 0xfa, 0xea, 0x27, 0xf1, 0x7d, 0x88, 0x74, 0x00, 0xfd,
+       0x3c, 0x49, 0xfb, 0xd5, 0xf2, 0x97, 0xd2, 0x5f, 0x00, 0x1e, 0xaa, 0xf7,
+       0x8c, 0xcd, 0xba, 0x1b, 0xf0, 0x53, 0x13, 0x71, 0xf8, 0x57, 0x53, 0xa9,
+       0x1e, 0xb4, 0x93, 0xfb, 0x45, 0x1d, 0x98, 0x97, 0xeb, 0x19, 0x38, 0x1f,
+       0xbe, 0xbe, 0xf3, 0x62, 0x1f, 0x9c, 0x87, 0x2f, 0x06, 0xa4, 0x9f, 0xbd,
+       0x41, 0x9c, 0xfe, 0x19, 0xa7, 0x8f, 0x8b, 0x7b, 0xe2, 0x04, 0xfd, 0x70,
+       0xba, 0xbd, 0xb8, 0x67, 0x8c, 0x1b, 0xe7, 0x13, 0x2d, 0xf6, 0xcd, 0x45,
+       0xc5, 0xa5, 0x0b, 0xc6, 0x76, 0xbf, 0x64, 0xf6, 0x9d, 0x30, 0x2f, 0x66,
+       0xf7, 0x4c, 0x9c, 0x37, 0x1e, 0x67, 0xef, 0x99, 0x38, 0x3f, 0x94, 0xb1,
+       0x07, 0x15, 0xce, 0x9f, 0x6a, 0x86, 0x79, 0x26, 0x22, 0xbf, 0x92, 0xfc,
+       0x8b, 0x99, 0x3c, 0x13, 0xe6, 0x41, 0x39, 0x4b, 0xf7, 0x4c, 0x98, 0x0f,
+       0xf5, 0x5f, 0x12, 0xf5, 0x58, 0xb1, 0x27, 0x8d, 0xbe, 0xbb, 0x3d, 0x69,
+       0xd8, 0xfe, 0x90, 0x8e, 0x55, 0x21, 0x3c, 0xe5, 0x7c, 0xaa, 0x9f, 0x8e,
+       0xdf, 0x4e, 0xf0, 0x30, 0xf1, 0xfd, 0x5a, 0xfd, 0xf4, 0x38, 0x82, 0x8f,
+       0x1c, 0xa7, 0x19, 0xf9, 0x48, 0x38, 0xa6, 0x40, 0x9f, 0x61, 0x03, 0xd7,
+       0xfd, 0x5b, 0xbb, 0xc2, 0xf7, 0x7f, 0xe8, 0xc4, 0x18, 0xe4, 0x6b, 0x43,
+       0xe1, 0x3f, 0x3d, 0x76, 0x58, 0x06, 0xb2, 0x92, 0x8b, 0x4b, 0x8c, 0xb7,
+       0x3a, 0xa0, 0xdf, 0x31, 0xed, 0x46, 0x4d, 0x3f, 0xb2, 0xde, 0x58, 0xb7,
+       0xf6, 0xfb, 0x61, 0xd1, 0xff, 0xa8, 0x00, 0x7c, 0x8e, 0x50, 0x7b, 0x8f,
+       0x06, 0xc1, 0x7c, 0xd9, 0xaf, 0x01, 0x4e, 0x6c, 0xe0, 0x78, 0xff, 0x89,
+       0xed, 0x80, 0x4e, 0x9f, 0x7a, 0xaa, 0x1f, 0x7f, 0x2a, 0xc7, 0x27, 0x63,
+       0x36, 0x49, 0x37, 0x36, 0x82, 0x13, 0xc7, 0xd3, 0x9f, 0x8d, 0x12, 0x4f,
+       0x6b, 0xe3, 0x81, 0x5f, 0xd7, 0x20, 0x4c, 0x92, 0x7d, 0xf0, 0x3a, 0x94,
+       0xe9, 0x8c, 0x8f, 0x84, 0xf4, 0x22, 0xe6, 0x61, 0xfe, 0x87, 0x22, 0x20,
+       0x0f, 0x69, 0xbd, 0x80, 0xbf, 0xcc, 0x4b, 0xb8, 0x07, 0xd2, 0xdf, 0x9d,
+       0x7f, 0xae, 0x8c, 0xef, 0x82, 0xf6, 0xe7, 0xed, 0x3a, 0x9a, 0x57, 0x20,
+       0x5c, 0xd7, 0x03, 0xfc, 0xb0, 0xbc, 0xd9, 0xc0, 0x6e, 0x2d, 0x86, 0xf6,
+       0x5f, 0x34, 0x9d, 0x48, 0x39, 0x63, 0xf0, 0xad, 0xe7, 0x6c, 0x93, 0xc3,
+       0x01, 0x47, 0x4d, 0x7f, 0xbe, 0xb2, 0x3d, 0xd3, 0x84, 0xfb, 0x6e, 0xc5,
+       0xb6, 0x4c, 0xd3, 0x32, 0x3f, 0xb8, 0x37, 0xef, 0xce, 0x3e, 0x61, 0x03,
+       0xbc, 0x9e, 0xdf, 0xad, 0xc7, 0x91, 0x58, 0xb3, 0xde, 0xfd, 0xab, 0x29,
+       0x51, 0xf8, 0x5d, 0xf5, 0xb8, 0x18, 0x95, 0x9b, 0x1c, 0x38, 0x0f, 0xcb,
+       0xb1, 0x3f, 0x60, 0xbd, 0xca, 0x6d, 0x11, 0x59, 0xaa, 0xcd, 0xd7, 0x7e,
+       0x45, 0x7b, 0x91, 0xa3, 0xc2, 0x0f, 0xfe, 0xe3, 0x76, 0x6b, 0xf1, 0x31,
+       0xde, 0xa3, 0xcd, 0x5f, 0x7d, 0x58, 0x9b, 0xff, 0x1a, 0xb9, 0x5a, 0xee,
+       0x3f, 0xdf, 0x2e, 0xd3, 0xab, 0xcd, 0x67, 0x9f, 0xd0, 0xe6, 0x3f, 0xfd,
+       0xd3, 0xda, 0x45, 0xb8, 0x0d, 0x9e, 0xcf, 0xe3, 0xfb, 0xe6, 0x33, 0x77,
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+       0xd9, 0xb8, 0x5f, 0xcb, 0xee, 0x51, 0x48, 0xde, 0x28, 0x7b, 0x6e, 0xcc,
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+       0x32, 0x13, 0xd4, 0xdf, 0x16, 0x0c, 0x29, 0xcd, 0xdf, 0x4d, 0x70, 0x54,
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+       0x96, 0x70, 0x7e, 0xd7, 0x16, 0xe1, 0xf1, 0x22, 0xdf, 0x6f, 0x7b, 0x20,
+       0x89, 0xcb, 0x53, 0x7f, 0x57, 0x09, 0x2e, 0xbd, 0xf7, 0x9a, 0xdd, 0x4f,
+       0x42, 0xfd, 0xb6, 0x4c, 0x2e, 0xf7, 0xb4, 0x6d, 0x1d, 0x43, 0xed, 0x91,
+       0x5f, 0x92, 0x3c, 0x75, 0x6f, 0x28, 0x6f, 0x3f, 0x8f, 0xc3, 0xb5, 0x6d,
+       0xb8, 0xd5, 0xed, 0x82, 0xfc, 0x87, 0x38, 0x45, 0x80, 0x4f, 0xdb, 0x76,
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+       0x93, 0xc6, 0x06, 0x03, 0xfd, 0x41, 0x3f, 0x67, 0x8a, 0xbc, 0x06, 0xc4,
+       0x6f, 0x68, 0x4e, 0xb1, 0x11, 0xcf, 0x43, 0x38, 0xc3, 0x89, 0x9f, 0x07,
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+       0x17, 0xc7, 0xf3, 0xc4, 0xff, 0x30, 0xdb, 0x9b, 0x69, 0xdd, 0x7c, 0x7e,
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+       0x0f, 0x28, 0x17, 0xdc, 0x70, 0xa3, 0x4a, 0xf5, 0x6f, 0x60, 0x9e, 0xaf,
+       0x3f, 0x44, 0xbe, 0xd0, 0xc2, 0xc7, 0xb9, 0xde, 0x75, 0x49, 0x1f, 0x0b,
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+       0x5a, 0x70, 0x5e, 0x09, 0x69, 0xc9, 0xf0, 0xfd, 0x7a, 0x94, 0x54, 0x07,
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+       0x07, 0xd4, 0xfb, 0x5a, 0xec, 0x2b, 0x99, 0x07, 0xb8, 0x52, 0xfd, 0x8a,
+       0xcd, 0x41, 0xdd, 0x29, 0x61, 0x98, 0x1a, 0xbc, 0x63, 0x20, 0x5d, 0x94,
+       0x33, 0xf3, 0x6f, 0xb8, 0xce, 0xb9, 0xc9, 0x6c, 0x36, 0xde, 0x9b, 0x7a,
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+       0x6c, 0xb8, 0xef, 0x9d, 0x8c, 0x79, 0x89, 0xef, 0xb9, 0xc7, 0x12, 0xdd,
+       0x77, 0xcf, 0xe8, 0xed, 0xde, 0x04, 0xf9, 0xee, 0xed, 0x63, 0xec, 0xcd,
+       0xc4, 0xd7, 0xf9, 0xfd, 0x7d, 0xb9, 0x95, 0xd1, 0xf9, 0xde, 0x3d, 0x83,
+       0xf3, 0x35, 0xc9, 0x5f, 0x4e, 0x5a, 0xbb, 0x42, 0x89, 0x5e, 0xc5, 0x7d,
+       0xbe, 0x5c, 0x90, 0xc6, 0x27, 0x8d, 0xb3, 0x1e, 0x9c, 0x04, 0xf5, 0xcb,
+       0x2d, 0xc6, 0x6e, 0x3c, 0x0f, 0x96, 0x3f, 0xb0, 0x20, 0xcc, 0x06, 0xf3,
+       0x2c, 0x6f, 0x83, 0xfb, 0x3c, 0x9c, 0x63, 0x6c, 0x8b, 0xf6, 0x3e, 0x0f,
+       0xf7, 0xed, 0xa8, 0xac, 0xdc, 0x81, 0xf7, 0xf2, 0xc0, 0xfb, 0x37, 0xd2,
+       0x0c, 0xd2, 0x51, 0xc5, 0x16, 0x85, 0xe8, 0x70, 0x54, 0xb3, 0xdd, 0x18,
+       0x47, 0x7c, 0x4c, 0xb1, 0xe2, 0xfa, 0x2a, 0x2c, 0xde, 0x54, 0x3c, 0xff,
+       0x2a, 0xec, 0x66, 0x3b, 0x96, 0x9f, 0x6f, 0x72, 0xdc, 0x7f, 0x06, 0xe4,
+       0xc3, 0x8b, 0x4d, 0x73, 0x28, 0x65, 0xdf, 0x02, 0xdc, 0x61, 0x9e, 0x57,
+       0x21, 0xf2, 0x60, 0xdf, 0xa7, 0x67, 0x3b, 0x93, 0xb2, 0x00, 0x8e, 0x65,
+       0xad, 0x65, 0x74, 0x9f, 0x0c, 0xc9, 0x70, 0x12, 0x7f, 0x72, 0x0a, 0xba,
+       0x9b, 0x0b, 0x60, 0x56, 0x90, 0xdf, 0xe8, 0xbb, 0xe2, 0x70, 0x1f, 0xbe,
+       0x93, 0x29, 0xbe, 0x47, 0x5a, 0xd3, 0x2c, 0x44, 0xcf, 0x66, 0x86, 0x70,
+       0xe8, 0x36, 0x58, 0xd3, 0x70, 0x5e, 0xdd, 0x1b, 0xcc, 0x3a, 0x3c, 0x37,
+       0xe7, 0xde, 0xc9, 0xe9, 0x1a, 0xf6, 0x99, 0x49, 0x0f, 0xed, 0xef, 0xd2,
+       0xb3, 0x60, 0xdc, 0xef, 0x3d, 0xd8, 0x1e, 0xc6, 0x2b, 0x59, 0xaf, 0x2f,
+       0xde, 0x0e, 0xf9, 0x91, 0x26, 0xa6, 0x0f, 0x8d, 0x44, 0xba, 0xca, 0x24,
+       0xba, 0x6e, 0xcf, 0x71, 0x7e, 0x8d, 0xfc, 0xe0, 0xb3, 0x5f, 0xb2, 0x3c,
+       0x94, 0x0b, 0xca, 0xb7, 0x6c, 0xa5, 0xf9, 0x48, 0xba, 0x60, 0xfa, 0xce,
+       0xc2, 0x61, 0x28, 0xe7, 0xed, 0x4c, 0xca, 0xc2, 0xfb, 0xb5, 0xa4, 0xa3,
+       0xf6, 0x9c, 0x99, 0x79, 0x08, 0xbf, 0x7e, 0x7a, 0xb8, 0x51, 0x21, 0x3a,
+       0x80, 0xf4, 0x68, 0x0a, 0xd1, 0xc3, 0xfc, 0x69, 0x58, 0x3e, 0x77, 0xa6,
+       0x37, 0x75, 0x0d, 0xcc, 0xab, 0x48, 0xad, 0x65, 0x0e, 0xd4, 0x33, 0xc4,
+       0x32, 0x7b, 0x10, 0xcc, 0xbf, 0x8f, 0xf5, 0x92, 0x3c, 0xd1, 0x07, 0xf2,
+       0x04, 0x9e, 0x67, 0x92, 0x9f, 0x48, 0xbe, 0x01, 0x74, 0xe0, 0x30, 0x45,
+       0xfb, 0xf0, 0xbb, 0xab, 0x09, 0xa6, 0x02, 0x3c, 0x79, 0x77, 0x93, 0x89,
+       0xd2, 0xa7, 0x9a, 0xac, 0x4c, 0x0f, 0xf0, 0xdd, 0xdb, 0x14, 0x4b, 0xf9,
+       0x67, 0x9a, 0x6c, 0x94, 0x7a, 0x9a, 0xd2, 0xe9, 0xfb, 0xb3, 0x4d, 0x76,
+       0xca, 0x1f, 0x68, 0xca, 0xa3, 0xfc, 0xa1, 0x26, 0x07, 0xe5, 0x0f, 0x37,
+       0xcd, 0xa1, 0xf4, 0xc5, 0xa6, 0x62, 0xfa, 0x2e, 0xf9, 0x12, 0xc0, 0x85,
+       0xf8, 0x90, 0xe4, 0x2b, 0x92, 0x1f, 0x49, 0x7a, 0x92, 0x7c, 0x29, 0x90,
+       0x8e, 0x4a, 0x01, 0xbc, 0x05, 0x59, 0xd4, 0x9e, 0xf8, 0x9e, 0xe4, 0x77,
+       0xb8, 0x0e, 0x5d, 0x96, 0x8f, 0x1f, 0x49, 0xfc, 0x26, 0x2b, 0xc5, 0xae,
+       0xd8, 0x24, 0xe4, 0x63, 0x5d, 0x4b, 0x90, 0x5f, 0x14, 0xa9, 0xe7, 0xf7,
+       0x3d, 0x0f, 0xf0, 0xed, 0xab, 0xb2, 0xd8, 0x83, 0x6c, 0x08, 0x17, 0xce,
+       0xf7, 0xfa, 0x2c, 0x26, 0x3a, 0xe7, 0x13, 0x8d, 0xec, 0x30, 0xde, 0xff,
+       0x9b, 0x57, 0x3b, 0xba, 0x37, 0xf9, 0x9d, 0xab, 0x37, 0x57, 0x29, 0x4c,
+       0xef, 0x47, 0xb7, 0xb7, 0x34, 0x98, 0x99, 0xde, 0x8f, 0x6e, 0x6f, 0x6d,
+       0x8c, 0xd0, 0xe4, 0x4b, 0x1a, 0xdf, 0x7d, 0x35, 0x06, 0xfa, 0xff, 0x47,
+       0x82, 0x73, 0x35, 0xd2, 0xdf, 0xc9, 0x3b, 0xce, 0x3e, 0xf6, 0x5f, 0xf0,
+       0xfd, 0x89, 0x3b, 0xbe, 0x18, 0x8d, 0xf8, 0x86, 0x79, 0xec, 0x7c, 0x08,
+       0xc7, 0x5d, 0x17, 0xdc, 0x3f, 0x8f, 0x48, 0xcc, 0xb7, 0x18, 0xe8, 0x9c,
+       0x19, 0x15, 0xcc, 0xef, 0x49, 0xa3, 0x82, 0xf9, 0x3d, 0x09, 0xff, 0x10,
+       0x3f, 0xcb, 0x18, 0xdf, 0xa7, 0x4f, 0xdc, 0xf1, 0x37, 0xda, 0xe7, 0xdd,
+       0x8d, 0x41, 0x36, 0x15, 0xe5, 0x0f, 0xc4, 0x17, 0xc0, 0xf7, 0x2f, 0x02,
+       0x5f, 0xcb, 0x1a, 0x83, 0x08, 0x8e, 0x65, 0x1b, 0x4e, 0xef, 0x7b, 0x1e,
+       0xf7, 0xfb, 0x3a, 0x23, 0xf1, 0xbb, 0x65, 0x2d, 0x62, 0x7f, 0x6e, 0x06,
+       0xb8, 0xfa, 0xc9, 0x6d, 0xa7, 0xe2, 0x18, 0xc9, 0x67, 0x8a, 0x83, 0xb1,
+       0x46, 0x80, 0xdf, 0xa9, 0x5f, 0x1a, 0xbd, 0x70, 0xf6, 0xb3, 0x53, 0x8a,
+       0xc9, 0xad, 0x40, 0x43, 0x05, 0x2e, 0x4d, 0x25, 0x08, 0xd7, 0xcd, 0xbf,
+       0xfb, 0x00, 0xe5, 0x6d, 0xa5, 0xf1, 0x04, 0xc9, 0xc7, 0x4e, 0x93, 0xc5,
+       0xab, 0xe2, 0xfc, 0x5c, 0x86, 0xf3, 0xfe, 0xfd, 0x29, 0x8d, 0xaf, 0x51,
+       0x3d, 0xd6, 0x35, 0x32, 0xe2, 0x6c, 0x08, 0x6d, 0x45, 0x86, 0x70, 0x0c,
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+       0x63, 0xb8, 0xbf, 0x59, 0xab, 0x62, 0x1d, 0x0d, 0xeb, 0xaa, 0x10, 0xdf,
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+       0x5f, 0xbf, 0x43, 0xc1, 0x61, 0x59, 0x1d, 0xeb, 0x24, 0x38, 0xd5, 0x1f,
+       0x50, 0x99, 0xc9, 0xff, 0x3c, 0x43, 0xfd, 0xce, 0xb0, 0xa1, 0xe7, 0x59,
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+       0x82, 0x3c, 0x13, 0x09, 0xae, 0x62, 0xfe, 0xbd, 0x82, 0x9f, 0xc9, 0x7a,
+       0x2b, 0x3b, 0xee, 0x37, 0x22, 0xbe, 0xa0, 0xde, 0x45, 0x92, 0x5f, 0x7e,
+       0x1b, 0xc2, 0x48, 0x6f, 0xc6, 0x7a, 0xff, 0x80, 0xf3, 0x3c, 0xb7, 0x2d,
+       0xdb, 0x8e, 0xfa, 0xbd, 0x95, 0x9e, 0xfd, 0xf5, 0x74, 0xfe, 0xef, 0x0d,
+       0xb1, 0x8e, 0x86, 0x75, 0x7c, 0x21, 0xf4, 0xfc, 0xb2, 0x1f, 0x63, 0x36,
+       0xdf, 0x4f, 0xc6, 0x6c, 0x2e, 0x6f, 0x9c, 0x13, 0xfa, 0xdc, 0x73, 0xcf,
+       0xa8, 0xc4, 0x87, 0x70, 0x9e, 0xb8, 0x0f, 0xbf, 0x40, 0x39, 0xd7, 0x6f,
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+       0xfd, 0x95, 0x9e, 0xee, 0xb0, 0x54, 0xa8, 0xff, 0xe9, 0xe1, 0x77, 0x29,
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+       0xcf, 0x8c, 0x28, 0xc5, 0x6f, 0x5f, 0xa5, 0x64, 0x1b, 0x38, 0x3e, 0xb6,
+       0xa9, 0x73, 0x10, 0x5e, 0xcc, 0x3d, 0x4c, 0xc8, 0xf9, 0x1e, 0x5a, 0xcf,
+       0xb9, 0xbd, 0xf1, 0x0a, 0xdd, 0x6f, 0x11, 0xde, 0x20, 0xe7, 0x9f, 0x3b,
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+       0x5d, 0xd6, 0xa7, 0xfd, 0x16, 0x87, 0xf7, 0xef, 0x5e, 0xd2, 0x6b, 0xc0,
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+       0x4e, 0x3e, 0x3f, 0x9c, 0x17, 0xca, 0xcf, 0x2b, 0x8d, 0xad, 0x69, 0x28,
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+       0x43, 0x38, 0xfe, 0x17, 0x7b, 0xc6, 0x32, 0x3c, 0xc7, 0xbb, 0x93, 0xdc,
+       0x95, 0x87, 0xa9, 0x1c, 0xe4, 0x37, 0xc0, 0x47, 0xf5, 0x53, 0x41, 0x5e,
+       0x9c, 0xef, 0xe7, 0x7b, 0x42, 0xdd, 0x0c, 0xea, 0x7f, 0x6e, 0xe0, 0xf2,
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+       0x67, 0x59, 0x94, 0xce, 0x61, 0x91, 0x58, 0x3e, 0x96, 0xf4, 0x2d, 0x9f,
+       0xff, 0x1e, 0xf6, 0xa9, 0x42, 0xdf, 0x37, 0xe3, 0x77, 0x27, 0x6b, 0x2d,
+       0xbd, 0x1d, 0xf7, 0xdd, 0xee, 0x10, 0xd2, 0xbb, 0x7d, 0xf1, 0xd4, 0xff,
+       0x1a, 0x3b, 0x98, 0xdd, 0xa2, 0x7a, 0x87, 0x56, 0xbf, 0x24, 0xe9, 0x40,
+       0x96, 0xdf, 0x9e, 0xcd, 0xef, 0x1b, 0xb7, 0x67, 0xf3, 0x7b, 0xc1, 0x1d,
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+       0x15, 0xf0, 0x40, 0xf7, 0x2e, 0xd8, 0x1f, 0xd1, 0xa8, 0xef, 0x3e, 0xe9,
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+       0xf3, 0xfb, 0xcd, 0x17, 0x7b, 0x0d, 0x64, 0x77, 0xa9, 0x7e, 0x3e, 0xd4,
+       0x41, 0x7a, 0x9c, 0x4d, 0x93, 0x74, 0x78, 0x5e, 0x54, 0xab, 0x5c, 0x0e,
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+       0xaa, 0x18, 0x87, 0x8f, 0xfb, 0xf9, 0xae, 0x04, 0xae, 0xd7, 0xf7, 0x8a,
+       0xfc, 0xa1, 0xf1, 0xa4, 0xd7, 0x9f, 0x1b, 0xc9, 0x6e, 0x9d, 0x4f, 0x72,
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+       0x8e, 0x43, 0x01, 0xf8, 0x54, 0xdf, 0xfe, 0x0b, 0x0e, 0xcf, 0xf0, 0x4a,
+       0x92, 0xcb, 0x61, 0xff, 0x11, 0xbf, 0xac, 0x15, 0xfc, 0xb2, 0x6e, 0xd3,
+       0xd4, 0xf0, 0xa9, 0xb8, 0x9f, 0xde, 0x56, 0x19, 0xca, 0x05, 0x97, 0xf5,
+       0xf6, 0x18, 0xe4, 0x87, 0x81, 0xf0, 0x7a, 0x4b, 0xf0, 0x95, 0x9a, 0x43,
+       0x8f, 0x19, 0xd1, 0x6e, 0x57, 0x0b, 0xfb, 0xc6, 0x09, 0xfb, 0xa6, 0x46,
+       0xd8, 0xc7, 0x6a, 0x9e, 0x52, 0x48, 0xae, 0xab, 0xd9, 0x38, 0xf5, 0x21,
+       0xe2, 0x83, 0x7f, 0x30, 0xb0, 0xd1, 0x30, 0x8f, 0xf3, 0x9e, 0xfb, 0xc3,
+       0xfc, 0xf1, 0xf1, 0xbc, 0xe0, 0x67, 0xbe, 0xf6, 0x76, 0xaa, 0x5f, 0x03,
+       0xf5, 0x79, 0xfb, 0x37, 0xc2, 0x68, 0x3e, 0xbb, 0x0c, 0x76, 0x9c, 0x4f,
+       0x20, 0x1e, 0x7f, 0x70, 0xfb, 0xa7, 0xd4, 0x1f, 0xd4, 0xbe, 0x9f, 0x3e,
+       0x3c, 0x70, 0xae, 0x4f, 0x18, 0xb8, 0xee, 0xcb, 0xac, 0xf3, 0xdf, 0x3e,
+       0x42, 0x7e, 0xb2, 0xd7, 0x4c, 0xfa, 0x2b, 0xc0, 0x7b, 0x22, 0xca, 0x1d,
+       0xe7, 0x0c, 0x9e, 0x4a, 0x5c, 0xf7, 0xb9, 0x7d, 0x66, 0xe2, 0x33, 0xe7,
+       0x22, 0xf8, 0x7e, 0xff, 0x14, 0xf8, 0xa1, 0x6b, 0x0c, 0xce, 0xe3, 0xba,
+       0xfb, 0x48, 0xbf, 0xf1, 0xce, 0x02, 0x86, 0xe7, 0xc1, 0x0a, 0xb7, 0xb6,
+       0x5f, 0x39, 0x6e, 0x87, 0xe0, 0xbf, 0x75, 0xc3, 0xec, 0xe1, 0xa8, 0x27,
+       0xab, 0x03, 0x3c, 0x60, 0x7f, 0x80, 0x97, 0x9f, 0x52, 0xfb, 0xb7, 0x0d,
+       0xd4, 0x3e, 0x70, 0x1d, 0x8f, 0x8a, 0x76, 0xfd, 0xfb, 0x73, 0x5f, 0x08,
+       0xd1, 0xcb, 0xb9, 0x11, 0x1c, 0x1f, 0xe7, 0x9e, 0x19, 0x43, 0xe7, 0x4a,
+       0x77, 0x04, 0xa7, 0x73, 0x98, 0x6f, 0x22, 0xde, 0x57, 0xce, 0x45, 0xf0,
+       0x94, 0xa1, 0x30, 0x02, 0x74, 0x50, 0x2d, 0xee, 0xa3, 0xe7, 0x66, 0x78,
+       0xe8, 0xfe, 0x7d, 0x4e, 0xd9, 0x4f, 0x69, 0xb7, 0x81, 0xb7, 0xab, 0x6e,
+       0x14, 0x76, 0x63, 0xa0, 0xbb, 0x58, 0xa4, 0x1b, 0xa4, 0x49, 0xb4, 0x87,
+       0x99, 0xb6, 0x74, 0xa2, 0x3c, 0x81, 0xfa, 0xea, 0x89, 0x59, 0x94, 0x7a,
+       0x83, 0x22, 0x07, 0xea, 0x9d, 0x91, 0x3e, 0xf1, 0x1c, 0x8a, 0xca, 0xe1,
+       0xfb, 0x8b, 0xe1, 0x78, 0xd1, 0xc2, 0xfe, 0x41, 0x72, 0x8a, 0xc7, 0x88,
+       0x7c, 0xd9, 0x29, 0xe4, 0xb8, 0xda, 0xbd, 0x03, 0xed, 0x70, 0x88, 0xdf,
+       0xda, 0xbd, 0x0a, 0xd9, 0x91, 0x2e, 0x8b, 0x73, 0x10, 0x67, 0x1d, 0x25,
+       0xf5, 0xe5, 0x40, 0x8f, 0x35, 0x2e, 0xc5, 0x61, 0xc6, 0xf9, 0xb4, 0xac,
+       0x5e, 0x49, 0x76, 0xa4, 0x86, 0xad, 0x37, 0x23, 0xbd, 0xcb, 0x75, 0xd4,
+       0xe8, 0xd9, 0x1c, 0xbc, 0x0f, 0x75, 0x2b, 0x2a, 0xcd, 0xa7, 0xdb, 0x0c,
+       0xfb, 0x06, 0xe1, 0xe0, 0x3f, 0x9e, 0x9f, 0xdc, 0xf5, 0x77, 0xc1, 0x0f,
+       0xf0, 0xcf, 0x1a, 0x4d, 0x72, 0x26, 0x09, 0xd7, 0xba, 0x1c, 0x1b, 0xa7,
+       0x1f, 0xc8, 0xb6, 0x42, 0x7f, 0xb5, 0x2d, 0xca, 0x16, 0x1a, 0x27, 0x49,
+       0xde, 0x2b, 0xf9, 0xfa, 0x24, 0x9c, 0x00, 0x2c, 0x46, 0xd4, 0x97, 0xc1,
+       0x7d, 0x9f, 0x97, 0x0f, 0xb1, 0x7e, 0x39, 0xcf, 0xc0, 0xf5, 0xcb, 0xf9,
+       0x44, 0xe7, 0x70, 0xfe, 0xde, 0x9d, 0x64, 0xbb, 0x2f, 0x1f, 0xf1, 0xfd,
+       0x96, 0x6a, 0xc7, 0x7b, 0xfa, 0xe5, 0x6f, 0xb3, 0xc3, 0x23, 0xbf, 0x43,
+       0x2e, 0xc3, 0x9b, 0x5b, 0xbf, 0xde, 0x18, 0xe6, 0x9f, 0x82, 0x34, 0x05,
+       0xeb, 0x3a, 0x8b, 0xfc, 0x0d, 0xf7, 0x33, 0xea, 0xa5, 0x61, 0x9e, 0x69,
+       0xdb, 0xb4, 0xf6, 0x90, 0xf4, 0x1d, 0xda, 0xfc, 0x55, 0x7b, 0xb5, 0xf9,
+       0x8c, 0x03, 0xda, 0xfc, 0x84, 0x0e, 0x6d, 0xde, 0xfe, 0x8a, 0x36, 0x1f,
+       0x22, 0xc6, 0x95, 0x70, 0xc2, 0x7b, 0xaf, 0x6d, 0x0c, 0xbf, 0xf7, 0x62,
+       0x8a, 0xf7, 0x5e, 0x5b, 0x10, 0xbf, 0xf7, 0x62, 0x1e, 0xef, 0xbd, 0x98,
+       0xe2, 0xbd, 0x17, 0xbf, 0xe3, 0xbd, 0x17, 0xf3, 0x78, 0xef, 0xc5, 0x3c,
+       0xde, 0x7b, 0x31, 0x8f, 0xf7, 0x5e, 0x4c, 0xf1, 0xde, 0x8b, 0xdf, 0x6f,
+       0x14, 0x70, 0xaa, 0x15, 0x7a, 0x47, 0xc4, 0x03, 0xda, 0x65, 0xd8, 0x0b,
+       0x66, 0x69, 0x67, 0xa7, 0xfd, 0xd2, 0xb3, 0x24, 0x9a, 0xf8, 0xa7, 0xb4,
+       0x93, 0xf6, 0xac, 0xcc, 0xa0, 0x7c, 0xbf, 0x5e, 0x67, 0x9e, 0x89, 0xf4,
+       0x3a, 0xa4, 0xbb, 0x01, 0xb9, 0x64, 0xc1, 0x48, 0x67, 0x41, 0xce, 0x70,
+       0xb4, 0x9f, 0x76, 0x6e, 0x8c, 0x43, 0xbc, 0xe9, 0xbb, 0x48, 0x9f, 0xbb,
+       0xea, 0x45, 0xae, 0xcf, 0xad, 0xcd, 0x32, 0x5b, 0x50, 0xcf, 0xd0, 0xb5,
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+       0x9a, 0x72, 0x35, 0x38, 0xec, 0x49, 0x8a, 0x3b, 0x75, 0x39, 0x3a, 0xd3,
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+       0x4d, 0x20, 0x3e, 0xf8, 0x7d, 0x78, 0x76, 0x5e, 0xa5, 0xc1, 0x73, 0x20,
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+       0x80, 0xfe, 0x67, 0x35, 0x30, 0xd2, 0x9b, 0x7d, 0x1f, 0x5e, 0x1e, 0x9b,
+       0x24, 0xce, 0x27, 0x81, 0x17, 0xc0, 0x03, 0xc5, 0xf5, 0xf5, 0x8d, 0x0c,
+       0x25, 0x3c, 0x3c, 0x26, 0xe6, 0x5f, 0xe0, 0x1d, 0x47, 0x71, 0xb1, 0x45,
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+       0x6f, 0x4e, 0xea, 0x5a, 0x15, 0xe4, 0xcb, 0xde, 0x04, 0xe7, 0x21, 0xe4,
+       0x1b, 0xb7, 0x66, 0x34, 0x10, 0x9d, 0xc6, 0xb2, 0xe2, 0xfd, 0x95, 0x30,
+       0xbf, 0xd2, 0xff, 0x0c, 0x22, 0x3b, 0x4e, 0xe9, 0x28, 0x1e, 0xaf, 0xcb,
+       0x32, 0xba, 0x28, 0xce, 0x41, 0xf2, 0xbb, 0xd2, 0x78, 0xee, 0x47, 0xf4,
+       0xf2, 0x24, 0x61, 0x17, 0xb6, 0x73, 0x7f, 0xa2, 0xa3, 0x93, 0xb8, 0x3c,
+       0x1b, 0x6a, 0xb7, 0x92, 0xdf, 0x71, 0x59, 0x06, 0x8f, 0xe3, 0x80, 0x6b,
+       0x57, 0x62, 0xe9, 0x78, 0x84, 0xcf, 0x9b, 0xe6, 0x31, 0x08, 0x9f, 0x36,
+       0x6e, 0x37, 0xe9, 0xc2, 0x78, 0xe1, 0x28, 0x5f, 0xbc, 0x30, 0xca, 0x9b,
+       0x28, 0xdf, 0x25, 0x08, 0xf9, 0xaa, 0xf9, 0xcf, 0x26, 0x13, 0xae, 0x63,
+       0x4c, 0x3b, 0xd3, 0x9c, 0x93, 0x63, 0xdd, 0x26, 0x8d, 0xdf, 0xeb, 0xb8,
+       0xdd, 0x56, 0x4d, 0x7e, 0xbc, 0x27, 0x56, 0x53, 0xff, 0xea, 0xc3, 0x36,
+       0x4d, 0x79, 0xa6, 0x37, 0x5d, 0x53, 0x9e, 0x7d, 0xc2, 0xae, 0xc9, 0xe7,
+       0x76, 0xe6, 0x69, 0xea, 0x4f, 0xfa, 0xc0, 0xa1, 0xc9, 0x4f, 0xee, 0x9a,
+       0xa3, 0xa9, 0x3f, 0xf5, 0xb3, 0x62, 0x4d, 0x3e, 0x9e, 0xf5, 0x3e, 0x8c,
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+       0x55, 0xb2, 0xe3, 0x95, 0x6e, 0x8a, 0xe0, 0x71, 0xa0, 0x42, 0x0f, 0x20,
+       0xe5, 0x69, 0xe9, 0x0f, 0xed, 0x14, 0xf4, 0x1d, 0x28, 0xa7, 0x8f, 0x32,
+       0x72, 0x39, 0xb5, 0x39, 0x8e, 0xf1, 0x7b, 0x98, 0x49, 0xdc, 0xb7, 0x98,
+       0x56, 0x5e, 0x77, 0x0a, 0x7f, 0x66, 0x29, 0xa7, 0x32, 0x97, 0xd6, 0x9f,
+       0x59, 0xfa, 0x31, 0xf7, 0xcb, 0xf5, 0x42, 0x6e, 0x97, 0xf2, 0xb1, 0x9f,
+       0x1f, 0xb3, 0xc3, 0xdf, 0x8f, 0xb9, 0x54, 0xc4, 0x6f, 0x07, 0x9e, 0x7f,
+       0x86, 0x3c, 0xae, 0x1f, 0x09, 0x9c, 0xff, 0x28, 0x23, 0x5f, 0x6f, 0xf3,
+       0xcf, 0x8d, 0x14, 0x37, 0x22, 0xe7, 0x15, 0x38, 0x1f, 0x67, 0x16, 0xa7,
+       0xdb, 0x9d, 0xa6, 0xc1, 0xe3, 0x77, 0x86, 0xe5, 0x71, 0x3d, 0xc1, 0xf8,
+       0xcc, 0xe2, 0x90, 0x3c, 0x48, 0x1f, 0x37, 0xd8, 0xdd, 0xa4, 0x47, 0x19,
+       0x30, 0x9e, 0xbd, 0xcb, 0x85, 0xf7, 0xca, 0x5f, 0x1a, 0xed, 0x77, 0xda,
+       0xbe, 0x7f, 0xbc, 0xd2, 0xab, 0xf9, 0x7a, 0x4a, 0x74, 0xba, 0x5b, 0xe7,
+       0x65, 0x90, 0xbf, 0xd8, 0xe2, 0x67, 0xfd, 0xc6, 0x4f, 0x11, 0xe3, 0x06,
+       0x4d, 0x51, 0x06, 0x5d, 0x5f, 0x69, 0x38, 0xf7, 0xe7, 0x62, 0xe1, 0x46,
+       0x1b, 0xd2, 0xef, 0xd0, 0xe3, 0x71, 0x78, 0xc6, 0x1a, 0x59, 0x0b, 0xc5,
+       0x19, 0x09, 0xbf, 0xff, 0x5b, 0xb6, 0x78, 0xee, 0x1d, 0x03, 0x45, 0x25,
+       0xc6, 0x56, 0x03, 0x29, 0x2f, 0x98, 0xdb, 0x80, 0xf4, 0x30, 0x77, 0x26,
+       0xc8, 0x53, 0x99, 0x8c, 0x1d, 0xda, 0xff, 0xec, 0x23, 0x16, 0x90, 0x67,
+       0x1e, 0x6f, 0xd4, 0x93, 0x9e, 0xe7, 0xaa, 0xc3, 0x31, 0x25, 0xae, 0x54,
+       0x5f, 0x1c, 0xc7, 0x28, 0xb8, 0x6f, 0x20, 0x7d, 0xa0, 0xcc, 0x82, 0xf7,
+       0x94, 0x47, 0x27, 0x73, 0x7f, 0xe5, 0xeb, 0xf2, 0xf8, 0xfa, 0x8a, 0xd4,
+       0x6f, 0xfb, 0xfd, 0xef, 0xc9, 0x7e, 0xc1, 0x98, 0x38, 0x27, 0x18, 0xf9,
+       0xc3, 0x0c, 0x42, 0x6f, 0x44, 0x87, 0x72, 0x1d, 0x3f, 0x96, 0x3f, 0xbe,
+       0xa4, 0xdb, 0x40, 0x38, 0xc9, 0xfb, 0x25, 0x13, 0xfe, 0x8e, 0xa9, 0x62,
+       0x5e, 0x12, 0x7e, 0x72, 0x3f, 0x48, 0xf8, 0xc9, 0x78, 0x08, 0xdb, 0x6a,
+       0x43, 0xf1, 0x93, 0x16, 0x8a, 0xab, 0x98, 0x83, 0x7e, 0x64, 0x12, 0x7f,
+       0xbf, 0x9d, 0xcc, 0xf9, 0xd1, 0x2f, 0x05, 0x3c, 0xb0, 0x1e, 0xf2, 0xa3,
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+       0x18, 0x3b, 0x5f, 0xc5, 0x77, 0xb2, 0x24, 0x1c, 0x3f, 0x6a, 0xfc, 0x0f,
+       0x03, 0xe9, 0xff, 0x99, 0x77, 0x34, 0xbe, 0xff, 0xb5, 0xb4, 0xc1, 0x6c,
+       0x47, 0xfe, 0xfc, 0xc9, 0xd4, 0xe2, 0x8a, 0x29, 0xc3, 0x11, 0x1f, 0x76,
+       0xc2, 0xc7, 0x24, 0xd8, 0x66, 0xd8, 0xff, 0xc9, 0x84, 0xe2, 0x15, 0xf8,
+       0xbd, 0x6e, 0xcb, 0xd1, 0xc7, 0x31, 0x6e, 0x7f, 0x55, 0x47, 0x12, 0xc5,
+       0x91, 0x96, 0x1d, 0xce, 0xdc, 0x88, 0xef, 0x89, 0x7c, 0x32, 0xd5, 0x59,
+       0x8b, 0xeb, 0x2d, 0xb3, 0x58, 0x8d, 0x78, 0x8e, 0xd7, 0xb7, 0x44, 0xd0,
+       0xb9, 0x56, 0x1a, 0x23, 0xe2, 0x3a, 0x59, 0x2f, 0xd9, 0xa9, 0x24, 0xfc,
+       0x5b, 0xa6, 0xf0, 0xf3, 0x74, 0x4a, 0x3e, 0xef, 0xbf, 0x47, 0xdc, 0x47,
+       0x90, 0x61, 0xce, 0xd3, 0xd4, 0x13, 0x7e, 0xdc, 0x01, 0xfb, 0x44, 0xea,
+       0x05, 0x03, 0xf5, 0x0b, 0x81, 0xef, 0x38, 0x0c, 0xb5, 0x7f, 0xa4, 0x1e,
+       0x01, 0xf5, 0x06, 0x46, 0x3f, 0xbd, 0xa2, 0xd4, 0x4b, 0x18, 0xd2, 0x4f,
+       0x2d, 0xc1, 0x73, 0xb4, 0xc4, 0xa8, 0x8d, 0x3f, 0x94, 0xe9, 0x41, 0xa9,
+       0x77, 0x13, 0xf7, 0xc1, 0xe5, 0xfd, 0xe7, 0x58, 0xc6, 0xec, 0x18, 0x94,
+       0x9b, 0xb7, 0x2a, 0x56, 0x3c, 0xc7, 0x2a, 0x2c, 0xb6, 0x9b, 0x26, 0x43,
+       0xbe, 0xe2, 0x84, 0x01, 0x3d, 0x30, 0xd9, 0xdc, 0x48, 0x1b, 0x7f, 0xbf,
+       0xe3, 0x2e, 0xfe, 0x7e, 0xc7, 0x32, 0xd8, 0xaf, 0xc8, 0x6f, 0x4a, 0x84,
+       0x3f, 0x56, 0x45, 0xfb, 0x64, 0xda, 0x6f, 0x15, 0x6e, 0x48, 0xb3, 0x87,
+       0xde, 0x97, 0x37, 0x6f, 0x3d, 0x9e, 0xf0, 0x02, 0xd2, 0x8f, 0xd7, 0x41,
+       0x71, 0xf9, 0x15, 0x56, 0x87, 0x31, 0xd2, 0x6f, 0xdf, 0x97, 0xb7, 0x2a,
+       0x9a, 0xb8, 0x7e, 0x99, 0xdf, 0x39, 0x45, 0xa5, 0x79, 0x97, 0x80, 0x98,
+       0x8e, 0xf0, 0xbb, 0x65, 0x6d, 0x92, 0x11, 0xdf, 0xd0, 0x29, 0x01, 0xf1,
+       0x02, 0xfd, 0xfb, 0x0e, 0x4e, 0xb1, 0x69, 0xe2, 0xaa, 0xa1, 0x1e, 0xf9,
+       0x35, 0xcc, 0x4d, 0x66, 0xaf, 0xf1, 0xf7, 0x93, 0x60, 0xde, 0x49, 0x7c,
+       0xbc, 0x2c, 0xbf, 0xfe, 0x97, 0xb5, 0x6a, 0xdf, 0x27, 0x80, 0xfa, 0x24,
+       0x17, 0xfd, 0x76, 0x4a, 0x28, 0xe1, 0xaf, 0xcc, 0x0a, 0xeb, 0x4e, 0xc2,
+       0xd4, 0x4a, 0xf3, 0x04, 0x38, 0x10, 0x9c, 0x7a, 0xef, 0x85, 0xfe, 0x6c,
+       0x34, 0x0e, 0xe1, 0xa3, 0xdc, 0xeb, 0x36, 0xe0, 0xbd, 0xbb, 0x04, 0xfd,
+       0x29, 0x20, 0xbf, 0xd4, 0xea, 0x36, 0xe0, 0x38, 0xcb, 0x5a, 0xf8, 0x7b,
+       0x21, 0xce, 0x2d, 0x7c, 0x1c, 0xe7, 0xe6, 0x08, 0xe3, 0x78, 0x94, 0x9b,
+       0xf4, 0x56, 0x63, 0x02, 0xc2, 0x0f, 0x2f, 0xcb, 0x51, 0x34, 0x3f, 0xe2,
+       0x83, 0x15, 0x00, 0x17, 0x8c, 0xb7, 0x92, 0x71, 0x97, 0x81, 0xf0, 0x29,
+       0x13, 0xf3, 0xad, 0x68, 0x8d, 0xd0, 0xca, 0x63, 0xad, 0x5b, 0x0d, 0x88,
+       0x8f, 0x25, 0x43, 0xbc, 0x57, 0xd0, 0x2d, 0xe8, 0x76, 0x59, 0xcb, 0x0c,
+       0x8a, 0x37, 0xaf, 0xd0, 0x3b, 0x28, 0x9e, 0xc1, 0x29, 0xe0, 0xfb, 0xc9,
+       0x6a, 0xf3, 0xdd, 0x68, 0x17, 0x58, 0xd2, 0xf6, 0x90, 0x21, 0x09, 0xf2,
+       0x7f, 0x14, 0xf4, 0xdb, 0x2d, 0xf6, 0xdd, 0xdc, 0x64, 0xef, 0x68, 0x7a,
+       0x17, 0x68, 0xb5, 0xd9, 0x8e, 0xf3, 0x5c, 0x62, 0x6d, 0xa5, 0xf5, 0xf5,
+       0xc3, 0xf7, 0x01, 0x80, 0x87, 0x82, 0xef, 0xcf, 0x14, 0x13, 0x7c, 0x81,
+       0x2e, 0x5c, 0xe8, 0x9f, 0x57, 0xd1, 0xa6, 0xc5, 0xa7, 0x6f, 0x3e, 0x1c,
+       0xbe, 0x15, 0x6d, 0x65, 0xb4, 0xdf, 0x2a, 0xf5, 0x4e, 0xa3, 0xd5, 0x7f,
+       0x1e, 0xed, 0x47, 0x47, 0xa3, 0x1f, 0xca, 0x12, 0xd8, 0xdf, 0xf8, 0xde,
+       0x11, 0xb3, 0x3a, 0x29, 0xbe, 0xe9, 0xec, 0x03, 0x37, 0x25, 0xd2, 0x3a,
+       0x61, 0x9e, 0xe4, 0x07, 0x65, 0xb7, 0xcd, 0xc6, 0x77, 0x7e, 0x80, 0x4e,
+       0x88, 0x8e, 0x25, 0xbd, 0xc8, 0xb8, 0x6c, 0x39, 0xde, 0x37, 0x53, 0x78,
+       0x5c, 0xe6, 0x37, 0xdf, 0xbb, 0x2f, 0x1d, 0x24, 0xd7, 0x34, 0x03, 0x7e,
+       0x51, 0xdf, 0x3d, 0xd4, 0xbe, 0x34, 0x62, 0x60, 0x17, 0x8c, 0x6b, 0xac,
+       0xe0, 0xef, 0xaf, 0x05, 0xee, 0x53, 0xb9, 0x3f, 0xfb, 0xed, 0x07, 0x62,
+       0x9f, 0xca, 0xfd, 0xfb, 0xb8, 0xa1, 0xd8, 0x1b, 0xab, 0xf8, 0xf8, 0x0c,
+       0x9c, 0xb7, 0x0d, 0xcf, 0x0e, 0x02, 0xa7, 0x49, 0x53, 0xf9, 0x7c, 0x97,
+       0x0a, 0xbc, 0x02, 0x5c, 0x5f, 0xf1, 0x8f, 0xe3, 0xb2, 0x4d, 0xe5, 0x78,
+       0x2d, 0x49, 0xd6, 0xee, 0x77, 0xec, 0x0f, 0xfb, 0x0d, 0x93, 0xe5, 0x33,
+       0xbd, 0xa3, 0x31, 0xee, 0x52, 0xd6, 0x97, 0xe3, 0x96, 0x44, 0xf2, 0x76,
+       0x48, 0xf7, 0x48, 0x6f, 0x61, 0x62, 0x3c, 0xac, 0xbf, 0x86, 0xea, 0x6b,
+       0xe3, 0x51, 0xca, 0xfb, 0xf9, 0xc5, 0xde, 0x0d, 0xd1, 0xc8, 0x2f, 0xf6,
+       0x2b, 0x24, 0xf7, 0xae, 0xb9, 0xf7, 0x78, 0xc2, 0xbf, 0xa3, 0x3c, 0xbb,
+       0x8f, 0xcb, 0xb3, 0xe7, 0x6a, 0x77, 0xd6, 0xc7, 0xa1, 0xdc, 0xa8, 0x77,
+       0x27, 0xfa, 0xbf, 0x8b, 0x55, 0xe1, 0xe5, 0xfc, 0x61, 0x39, 0xc8, 0x3f,
+       0xc8, 0x2f, 0x2a, 0xc5, 0x39, 0xbd, 0x2f, 0xcb, 0x99, 0x30, 0xd5, 0xcf,
+       0x7f, 0xa2, 0xe2, 0xfe, 0x7d, 0x69, 0x4e, 0xce, 0x5f, 0xbc, 0xc8, 0x5f,
+       0xfe, 0xb2, 0xef, 0xa5, 0xf7, 0xa6, 0xd8, 0x7c, 0xe7, 0xa7, 0x9c, 0xff,
+       0xb2, 0xcd, 0x7f, 0x34, 0x94, 0x59, 0xfc, 0xe1, 0xc5, 0xd7, 0x77, 0x77,
+       0x7a, 0x1f, 0xc5, 0xd9, 0x95, 0x5b, 0x8c, 0x36, 0xf4, 0x5f, 0x2e, 0x6f,
+       0x29, 0x23, 0x7e, 0xcb, 0x62, 0xe1, 0x5e, 0xa1, 0xf8, 0xf0, 0x1d, 0x48,
+       0x07, 0x65, 0x2d, 0x0a, 0xbd, 0x2f, 0x56, 0xde, 0x38, 0xd1, 0xad, 0xfe,
+       0x5f, 0xe4, 0xcb, 0xe5, 0x5b, 0xe6, 0xd1, 0x9b, 0x48, 0x12, 0x4f, 0xf2,
+       0xbd, 0x13, 0x79, 0x9e, 0xca, 0xf9, 0x3b, 0xc4, 0xfc, 0x97, 0x0a, 0x3a,
+       0x9e, 0x35, 0x95, 0xef, 0xbf, 0xa5, 0x55, 0x49, 0xc6, 0x4a, 0xda, 0xf7,
+       0x49, 0xc6, 0x72, 0xa4, 0x7f, 0x51, 0xbe, 0xa4, 0x42, 0xfb, 0xbd, 0x1f,
+       0x4f, 0xfd, 0x76, 0xec, 0x8c, 0x8d, 0xb8, 0x3f, 0x30, 0x6e, 0x88, 0xee,
+       0x27, 0x5b, 0x0c, 0x5c, 0xcf, 0xb7, 0x37, 0x94, 0xe4, 0xd5, 0x73, 0x6b,
+       0x9e, 0xff, 0xc3, 0x22, 0xa8, 0xf7, 0xc5, 0x83, 0xdb, 0x13, 0x51, 0x3e,
+       0x91, 0xf3, 0x58, 0x21, 0xf4, 0x79, 0xcb, 0x85, 0x5e, 0xae, 0x52, 0xc8,
+       0xad, 0x80, 0xa7, 0xf9, 0x53, 0xfd, 0xf8, 0xec, 0x8a, 0x27, 0x38, 0x9e,
+       0xca, 0x9f, 0x79, 0xeb, 0xaf, 0xf8, 0x2e, 0x57, 0x49, 0xb2, 0xe0, 0x67,
+       0xf7, 0xf2, 0x78, 0xfe, 0x65, 0x9e, 0xfd, 0x84, 0xb7, 0x25, 0x9b, 0xb7,
+       0x1a, 0x92, 0x10, 0x5f, 0xf8, 0x48, 0xad, 0x5f, 0xfb, 0xf2, 0x06, 0xb8,
+       0xe8, 0x02, 0x3c, 0x97, 0x6e, 0xde, 0x6e, 0x40, 0x3e, 0xb0, 0x4c, 0xae,
+       0x37, 0x80, 0xde, 0x4b, 0x84, 0xbf, 0xaf, 0x84, 0x2b, 0x9e, 0x3b, 0x8a,
+       0x9f, 0xdd, 0x42, 0xd6, 0x47, 0xfe, 0xb7, 0x1f, 0xc6, 0x59, 0xbb, 0xda,
+       0x1c, 0x86, 0xfa, 0x69, 0x39, 0xce, 0x3d, 0x53, 0xb9, 0xdc, 0x54, 0xde,
+       0x10, 0x11, 0x89, 0xe3, 0x95, 0x37, 0x94, 0xfd, 0x0a, 0xef, 0x1d, 0x92,
+       0xdf, 0x07, 0xee, 0xbb, 0xd3, 0x66, 0xbe, 0x1f, 0x96, 0x41, 0x7f, 0xb8,
+       0x2f, 0x4f, 0xcf, 0xb0, 0x53, 0x5c, 0x33, 0xda, 0xb5, 0x06, 0x3b, 0x57,
+       0xef, 0x9c, 0xca, 0xcf, 0xd5, 0x47, 0x0d, 0xfc, 0xfd, 0xc6, 0xf8, 0x10,
+       0xcf, 0x1e, 0x84, 0x43, 0xfc, 0xaa, 0x60, 0x3b, 0xf2, 0x87, 0xd4, 0xd4,
+       0x2e, 0xb2, 0x1b, 0x23, 0x3d, 0xe3, 0xbc, 0x8d, 0x3a, 0xfe, 0xde, 0x63,
+       0x6a, 0x6d, 0xd7, 0x25, 0x9c, 0x07, 0x88, 0xd4, 0xe4, 0x9f, 0x82, 0x29,
+       0xbe, 0x33, 0x85, 0x22, 0x76, 0x34, 0xe4, 0x9f, 0xd4, 0xf1, 0xf8, 0xab,
+       0x64, 0x95, 0xa7, 0xbb, 0x05, 0x7c, 0xa0, 0xdc, 0x8b, 0xe5, 0x2c, 0xaa,
+       0x8b, 0xde, 0x9d, 0xeb, 0x7f, 0x37, 0x29, 0x80, 0x5e, 0x8d, 0x6c, 0xc7,
+       0x66, 0x7c, 0xef, 0xc6, 0x18, 0xc5, 0xec, 0xcd, 0x36, 0x1f, 0x7d, 0xca,
+       0x7e, 0x24, 0x7d, 0x4a, 0xfa, 0x1d, 0x6a, 0x7d, 0xee, 0x1f, 0xb8, 0xbe,
+       0xd3, 0x49, 0x42, 0x1f, 0x91, 0x6e, 0x4f, 0xc4, 0x38, 0x95, 0xd2, 0xfb,
+       0xc6, 0xd8, 0x51, 0x3f, 0xf3, 0x7d, 0xeb, 0x34, 0x8a, 0xf7, 0x07, 0xfb,
+       0xd7, 0x0b, 0xc4, 0x9a, 0x17, 0x39, 0xc8, 0x7a, 0x53, 0xf9, 0xbd, 0x65,
+       0xe8, 0xf5, 0xb6, 0x15, 0x45, 0x0f, 0xb2, 0xde, 0xc0, 0x75, 0xca, 0x7d,
+       0x22, 0x7d, 0xda, 0xfb, 0xed, 0x0b, 0xad, 0xdc, 0xbe, 0x70, 0x5a, 0x81,
+       0xf3, 0x0b, 0xda, 0x9d, 0x5e, 0x6d, 0x26, 0xff, 0x2f, 0xb9, 0x2e, 0xa9,
+       0xff, 0xfe, 0xa1, 0x71, 0x08, 0xaf, 0x4c, 0x8d, 0x14, 0x7a, 0x9d, 0xae,
+       0x50, 0x94, 0x23, 0x4b, 0x82, 0xc5, 0xfe, 0xf7, 0xf2, 0x3c, 0x7e, 0x9f,
+       0xe7, 0xf7, 0x5d, 0x9e, 0xfb, 0xf2, 0xbd, 0x36, 0xc9, 0x9f, 0xcf, 0x34,
+       0x88, 0x73, 0x91, 0x75, 0xdd, 0x8b, 0xfb, 0x99, 0x35, 0xa6, 0xd0, 0xfb,
+       0x24, 0x27, 0x5b, 0x4f, 0x87, 0xe2, 0x7b, 0x29, 0xa7, 0x67, 0xf0, 0xf9,
+       0xc9, 0x76, 0x6b, 0x0d, 0x3c, 0xce, 0x98, 0x85, 0x1a, 0x6d, 0xf8, 0xfe,
+       0x21, 0xdc, 0xaf, 0x4e, 0x36, 0xa2, 0xdd, 0xa7, 0x25, 0x86, 0xee, 0x91,
+       0xb7, 0x34, 0xa6, 0x10, 0x5f, 0xb8, 0xc5, 0x15, 0xc1, 0xf5, 0x0f, 0x42,
+       0xbe, 0xaf, 0x14, 0x7c, 0x30, 0x64, 0x6d, 0xd9, 0x46, 0x7c, 0xe7, 0x7b,
+       0x79, 0x7b, 0x92, 0x55, 0x81, 0x71, 0x96, 0x5b, 0xec, 0x67, 0xdb, 0xa9,
+       0xfd, 0x38, 0x3b, 0xca, 0x83, 0x21, 0x6d, 0xf3, 0x8c, 0xc9, 0x24, 0xf7,
+       0xf2, 0x7b, 0x80, 0xb4, 0x13, 0xad, 0x55, 0x58, 0x31, 0xc5, 0x8d, 0x21,
+       0x9f, 0xc4, 0xfd, 0xa5, 0x3b, 0x9a, 0x8a, 0xe7, 0xce, 0x8a, 0x76, 0x7e,
+       0x0f, 0x98, 0xab, 0x63, 0x9b, 0xd1, 0x4e, 0x38, 0xaa, 0xb9, 0x78, 0x76,
+       0x1c, 0xf2, 0x89, 0x87, 0x15, 0x8a, 0x33, 0x67, 0xdb, 0xb4, 0xef, 0x58,
+       0xa5, 0x67, 0x17, 0x7f, 0x4c, 0xf7, 0xbf, 0x80, 0x77, 0xe0, 0xd6, 0x1a,
+       0x3c, 0x8e, 0x18, 0xe4, 0xe3, 0x20, 0x6f, 0xa0, 0xbe, 0x69, 0xb9, 0xa5,
+       0x98, 0xe4, 0xf6, 0x52, 0x41, 0x27, 0x27, 0xdb, 0xba, 0xe9, 0x3d, 0x7a,
+       0x09, 0xd7, 0x01, 0xf1, 0x3f, 0x46, 0x1e, 0x07, 0xdc, 0x1b, 0xaa, 0x23,
+       0x3d, 0xdc, 0x0f, 0x8d, 0x03, 0xaa, 0x10, 0x76, 0x25, 0x49, 0x37, 0xd2,
+       0x2e, 0xf5, 0x08, 0xfe, 0x67, 0x32, 0xc2, 0x49, 0xa5, 0x73, 0xad, 0x48,
+       0x2d, 0xa1, 0xf7, 0x94, 0x36, 0xb6, 0xcd, 0xa2, 0xb4, 0x62, 0x6b, 0xd1,
+       0x83, 0xae, 0xf1, 0x18, 0x7f, 0x5c, 0x1c, 0x3d, 0x85, 0xe6, 0x6d, 0x20,
+       0x3d, 0x59, 0x45, 0xdd, 0x2c, 0x1e, 0xaf, 0xfb, 0x64, 0x50, 0x04, 0xde,
+       0x6f, 0x12, 0x0d, 0xae, 0x44, 0x7f, 0xb9, 0xb4, 0x62, 0xfb, 0x26, 0x8a,
+       0xff, 0xf9, 0x6c, 0xbb, 0x99, 0xe2, 0x7f, 0x0a, 0xad, 0xf3, 0x0a, 0x23,
+       0xa2, 0xe8, 0xbd, 0x63, 0x8a, 0xaf, 0x93, 0xf5, 0xc2, 0xf3, 0xf9, 0x79,
+       0x51, 0x5d, 0x37, 0x4b, 0x13, 0xbf, 0xb3, 0x1c, 0xfa, 0xc4, 0x77, 0x36,
+       0xbf, 0xf2, 0x84, 0x90, 0x1f, 0x9a, 0x8c, 0xcb, 0xa9, 0x8d, 0x71, 0x06,
+       0xe7, 0xe7, 0xf2, 0xf8, 0x9c, 0xc9, 0x36, 0x1e, 0x97, 0x13, 0x47, 0xf5,
+       0x6d, 0x83, 0xea, 0xc5, 0x65, 0x7a, 0xb6, 0x89, 0xc7, 0x79, 0xf8, 0xc5,
+       0x1b, 0xdd, 0xb0, 0x04, 0xda, 0xd7, 0xd6, 0x3d, 0x17, 0x86, 0xfd, 0xd4,
+       0x3c, 0xf0, 0xee, 0x44, 0xab, 0x8e, 0xf4, 0x50, 0xd1, 0xf9, 0xc3, 0xfd,
+       0xe2, 0x8d, 0xda, 0x79, 0xbc, 0x51, 0x8c, 0xb8, 0x2f, 0xcd, 0x8d, 0x2c,
+       0x5e, 0xb4, 0x04, 0xe1, 0xff, 0x7b, 0x95, 0xe0, 0x3f, 0xd4, 0x78, 0x55,
+       0x87, 0x15, 0x8d, 0x1d, 0xef, 0x16, 0x77, 0x38, 0xc9, 0xad, 0x4e, 0x2f,
+       0x33, 0xa2, 0x1d, 0xd9, 0x69, 0x65, 0x24, 0x17, 0x7f, 0xa6, 0xb2, 0x46,
+       0x94, 0x03, 0xa4, 0xfc, 0x22, 0xbf, 0x5f, 0x95, 0xcf, 0xf9, 0xd5, 0x67,
+       0xe1, 0xad, 0x89, 0x48, 0x1f, 0x2b, 0x77, 0x3d, 0x94, 0x88, 0xe7, 0xcb,
+       0xe7, 0xa1, 0x3c, 0x5f, 0xb2, 0xeb, 0xa6, 0xd7, 0x91, 0x5f, 0x39, 0x77,
+       0x04, 0x71, 0xf9, 0x5c, 0xcf, 0x48, 0x1e, 0x2e, 0x77, 0x71, 0xf9, 0x9a,
+       0x55, 0x45, 0xca, 0xf7, 0x48, 0xcd, 0xa5, 0x40, 0x47, 0x39, 0xf9, 0x21,
+       0xfc, 0xdd, 0xa3, 0x76, 0x6d, 0xbc, 0xb9, 0x7c, 0xe7, 0xf6, 0x73, 0x3d,
+       0x7f, 0x9f, 0x07, 0xe3, 0x8d, 0x90, 0xde, 0x3f, 0xd2, 0x7b, 0x97, 0x23,
+       0x7e, 0x3f, 0x02, 0xf9, 0x15, 0xef, 0xb1, 0xe1, 0xf9, 0x9c, 0x3e, 0x3f,
+       0x6a, 0x55, 0x67, 0x93, 0xdf, 0x10, 0x6c, 0x14, 0x94, 0x43, 0x3e, 0x6a,
+       0x7d, 0x2e, 0x14, 0xe3, 0xa1, 0xa5, 0xbc, 0x56, 0xa4, 0xfe, 0xc5, 0x81,
+       0xef, 0xff, 0xac, 0x39, 0xc8, 0xe3, 0x82, 0xf1, 0x7d, 0x7a, 0x7a, 0x2b,
+       0x54, 0xe8, 0x41, 0xea, 0x85, 0x1e, 0x64, 0xcd, 0x0b, 0x86, 0xd9, 0xf1,
+       0x51, 0x24, 0x7f, 0xd1, 0x97, 0x5a, 0xbd, 0xd7, 0x38, 0x18, 0xfe, 0xaa,
+       0x85, 0x7c, 0xd5, 0x9f, 0x3f, 0xb0, 0x9f, 0xee, 0x6d, 0xb5, 0x7b, 0xb9,
+       0xfc, 0x50, 0xeb, 0xe9, 0x26, 0xf9, 0x41, 0xca, 0x23, 0x32, 0xee, 0xb0,
+       0x66, 0x6f, 0x37, 0xc9, 0x13, 0xb2, 0x5d, 0xfd, 0x01, 0x0e, 0x97, 0xba,
+       0x03, 0xfc, 0x7b, 0x59, 0xba, 0x4e, 0xea, 0x51, 0x1c, 0x4a, 0x2a, 0xde,
+       0xa7, 0x15, 0xca, 0xaf, 0x9e, 0x92, 0x51, 0xba, 0x5e, 0x93, 0x1f, 0x57,
+       0xba, 0x5e, 0x8f, 0xa9, 0xd0, 0xdb, 0xeb, 0x7b, 0x49, 0x1e, 0xbc, 0x3b,
+       0xfd, 0x1d, 0xba, 0x87, 0xd7, 0xb5, 0x88, 0x7e, 0x21, 0x6f, 0xf0, 0x1b,
+       0x6f, 0x09, 0x12, 0xd1, 0x70, 0xfe, 0x3d, 0xc5, 0x82, 0xed, 0x6d, 0x1a,
+       0xff, 0xda, 0xba, 0x03, 0x11, 0xd4, 0xde, 0x5b, 0x17, 0xbc, 0x19, 0xcf,
+       0x79, 0x47, 0xbd, 0x45, 0x8f, 0x69, 0x73, 0x9d, 0x85, 0xce, 0xfd, 0x6d,
+       0x0d, 0xba, 0x74, 0xf4, 0x53, 0x77, 0x28, 0xc1, 0x76, 0x94, 0xe3, 0x3a,
+       0x84, 0xff, 0xd6, 0xf0, 0x9a, 0xf7, 0xcd, 0xa8, 0x3f, 0x88, 0x63, 0xbd,
+       0xc7, 0xf1, 0xbd, 0x5d, 0x6f, 0x82, 0xb3, 0x16, 0xf7, 0x43, 0x0c, 0xbe,
+       0xee, 0xa2, 0xfa, 0xe2, 0x89, 0x7a, 0x8e, 0x7c, 0x9a, 0x8d, 0xfd, 0x17,
+       0x8c, 0xea, 0xba, 0x8c, 0x6f, 0x6a, 0x18, 0xd6, 0x4f, 0x2a, 0x45, 0x3b,
+       0xc5, 0xda, 0x7c, 0xb1, 0x8e, 0x8c, 0xae, 0x6c, 0xa4, 0xeb, 0xe1, 0xc7,
+       0x38, 0x7f, 0x7e, 0xcc, 0xc0, 0x36, 0xd3, 0xbb, 0xcd, 0xfa, 0x62, 0x86,
+       0xfa, 0x7b, 0xaf, 0xb0, 0x2f, 0xba, 0xbe, 0xd1, 0xd1, 0xfb, 0xb3, 0x1d,
+       0x8a, 0xf7, 0xd7, 0xfe, 0xf2, 0xd5, 0x1e, 0xb1, 0x6f, 0x8b, 0x83, 0xb8,
+       0x9d, 0xf1, 0xfe, 0x09, 0xce, 0x5f, 0xe2, 0x3c, 0x7e, 0xaa, 0x18, 0xc6,
+       0x67, 0x92, 0x7f, 0xa3, 0x3a, 0x1a, 0xfb, 0xef, 0x11, 0x76, 0x48, 0x29,
+       0xa7, 0xce, 0x14, 0xfc, 0x39, 0x41, 0xdc, 0xaf, 0x8c, 0x23, 0x62, 0x2d,
+       0x48, 0xc7, 0xd2, 0xaf, 0x4f, 0x71, 0x38, 0x28, 0xde, 0xf3, 0xce, 0x8c,
+       0x63, 0xe5, 0x78, 0x3e, 0xdf, 0xd3, 0x6b, 0xa2, 0x78, 0x81, 0x99, 0xbd,
+       0xc1, 0x24, 0xb7, 0x26, 0x8c, 0x98, 0x43, 0xe7, 0x99, 0x7c, 0xb7, 0x5d,
+       0xb1, 0xe9, 0x59, 0x09, 0xd4, 0x3f, 0x96, 0xa1, 0xf3, 0x62, 0x5c, 0xdc,
+       0x3d, 0xcc, 0xc4, 0xfd, 0x02, 0x4c, 0x01, 0xf2, 0xad, 0xce, 0x4c, 0xfe,
+       0xc9, 0x4a, 0xc7, 0xef, 0xbe, 0x41, 0xbe, 0x1e, 0xaf, 0x5e, 0x3a, 0x1e,
+       0x8e, 0xfe, 0xb2, 0xff, 0xae, 0xd0, 0xfb, 0xa3, 0xa5, 0x7d, 0x67, 0x1f,
+       0x7b, 0x9b, 0xe1, 0x7d, 0xd8, 0x9d, 0x49, 0xf1, 0xd0, 0x09, 0xce, 0x87,
+       0x10, 0x85, 0x27, 0xfb, 0xe6, 0x74, 0x3b, 0x01, 0x75, 0xf7, 0x58, 0x3d,
+       0x26, 0x3b, 0x3f, 0x2f, 0x98, 0xff, 0x3a, 0x3a, 0x7e, 0xfe, 0x4d, 0x58,
+       0xa4, 0xce, 0x37, 0xbf, 0x9e, 0xde, 0xb3, 0xf4, 0xae, 0x63, 0x4f, 0xaf,
+       0x89, 0xf4, 0xb6, 0x33, 0x3b, 0xc4, 0x3b, 0x87, 0x01, 0xf3, 0xe9, 0x89,
+       0xb5, 0x91, 0x9f, 0x34, 0xd4, 0x23, 0x79, 0xb3, 0xc7, 0xa2, 0xa3, 0xf7,
+       0xdd, 0x66, 0x76, 0x1c, 0xa7, 0xf7, 0x0a, 0x67, 0xca, 0xf7, 0x0c, 0x4d,
+       0xda, 0xf7, 0x0c, 0x99, 0x2d, 0x21, 0x02, 0xf5, 0xca, 0xa4, 0x4b, 0x05,
+       0xe1, 0x20, 0xba, 0x99, 0xe3, 0xaf, 0x20, 0x5c, 0x7b, 0x5f, 0xec, 0xc8,
+       0xe7, 0xf2, 0x62, 0x87, 0xe0, 0x23, 0x81, 0xef, 0xdd, 0xcb, 0xb8, 0x15,
+       0x79, 0xae, 0xbc, 0x6c, 0xd9, 0x75, 0x0b, 0xd7, 0x4b, 0xf1, 0x7d, 0xba,
+       0x4a, 0xda, 0xf9, 0xaf, 0x24, 0x93, 0x3c, 0xd1, 0xd7, 0x91, 0xf2, 0x9d,
+       0xef, 0x58, 0xbc, 0x8b, 0x72, 0x05, 0xc8, 0x0b, 0xa7, 0xae, 0x76, 0xbc,
+       0x92, 0x3f, 0xdc, 0x77, 0xae, 0x2e, 0x14, 0x70, 0x92, 0xe7, 0xb3, 0x8c,
+       0x5b, 0x58, 0x28, 0xe0, 0xb5, 0xd0, 0xa2, 0xe3, 0xf0, 0x09, 0xf8, 0xdd,
+       0x15, 0x49, 0x37, 0x81, 0x74, 0xe1, 0xc3, 0x3b, 0x8f, 0xf7, 0x92, 0xf8,
+       0x64, 0xb7, 0x77, 0xbe, 0x8a, 0xf1, 0x58, 0x80, 0xc7, 0xf1, 0xf7, 0x31,
+       0xc2, 0xdf, 0xdb, 0x48, 0x8f, 0x27, 0xbf, 0x79, 0x73, 0x03, 0x3e, 0xbb,
+       0x30, 0x42, 0x75, 0x74, 0x3b, 0x93, 0x7e, 0x14, 0xfc, 0xd1, 0xfb, 0xdd,
+       0x3f, 0x18, 0x7f, 0x9d, 0x81, 0xf8, 0xf3, 0x9a, 0xc7, 0xa0, 0x1c, 0xf1,
+       0x80, 0x8e, 0xe4, 0x08, 0xe9, 0xef, 0xe8, 0x14, 0xef, 0xb5, 0x4b, 0xbf,
+       0x47, 0x96, 0xce, 0x88, 0x1f, 0x94, 0xaa, 0xc1, 0xa4, 0x2f, 0x74, 0x8a,
+       0x77, 0xda, 0x81, 0x0f, 0xbc, 0x8a, 0x7c, 0x40, 0xee, 0xff, 0x51, 0x73,
+       0xba, 0xc6, 0xe3, 0x39, 0x7a, 0x12, 0xae, 0xe8, 0x38, 0xbf, 0x2e, 0x9d,
+       0x87, 0xbe, 0x87, 0x4f, 0xe3, 0xfe, 0x86, 0x23, 0x59, 0x67, 0x9c, 0xf0,
+       0xcf, 0xc9, 0x45, 0xf9, 0x4d, 0xf5, 0xbd, 0x4f, 0x4d, 0x74, 0xdf, 0xac,
+       0xb8, 0x1f, 0xae, 0x44, 0xff, 0xcb, 0x85, 0x16, 0xf2, 0x73, 0xef, 0x71,
+       0x07, 0xbc, 0x4f, 0x2d, 0xde, 0x31, 0xef, 0x61, 0x82, 0x3f, 0x2c, 0x96,
+       0xef, 0x98, 0xc3, 0x7e, 0x86, 0x76, 0x6d, 0x4b, 0x78, 0x79, 0xff, 0x3b,
+       0xe6, 0xa3, 0x19, 0xdd, 0xa3, 0xda, 0x32, 0x59, 0x1a, 0xca, 0x5f, 0x6d,
+       0xe2, 0x77, 0x7f, 0x86, 0x7c, 0xc7, 0x7c, 0x65, 0x24, 0xe9, 0x4d, 0x1f,
+       0x79, 0xc4, 0x3d, 0x16, 0xcf, 0x03, 0xf9, 0x7e, 0xf5, 0xf4, 0x04, 0xa7,
+       0x79, 0xda, 0xf0, 0x81, 0xef, 0x57, 0x3f, 0xa8, 0x14, 0x2f, 0xc1, 0xdf,
+       0x81, 0x71, 0x8d, 0xe7, 0xf3, 0xed, 0x5a, 0x12, 0xfc, 0xcc, 0x2e, 0x0e,
+       0x6e, 0x2f, 0xea, 0x7b, 0x4e, 0x36, 0x86, 0xd2, 0xbb, 0xdd, 0x92, 0x4e,
+       0xa5, 0x9e, 0x7b, 0x94, 0xab, 0xfb, 0x61, 0x84, 0x93, 0x8c, 0xab, 0xfd,
+       0x58, 0xd0, 0x9b, 0x84, 0xbf, 0x8c, 0x2b, 0x8c, 0x0a, 0xc0, 0x83, 0xa4,
+       0xbb, 0xfe, 0xdf, 0x8b, 0x59, 0xc7, 0xe9, 0xaf, 0xdf, 0x9f, 0xb6, 0x9e,
+       0x91, 0x3e, 0x65, 0x24, 0x4c, 0x25, 0x84, 0xfc, 0x23, 0xed, 0x36, 0x84,
+       0xeb, 0x3d, 0x89, 0xce, 0x24, 0x9c, 0x7f, 0xf3, 0x6a, 0x80, 0x33, 0xe9,
+       0xd1, 0xb9, 0x9f, 0xe7, 0x49, 0xf1, 0x7b, 0x16, 0x81, 0xfb, 0x29, 0x63,
+       0x9a, 0x4e, 0xda, 0x89, 0x29, 0x5e, 0xa0, 0x54, 0x9c, 0x6b, 0xa5, 0x32,
+       0x3e, 0xa0, 0x51, 0x1b, 0x1f, 0x10, 0xf8, 0xbe, 0x69, 0xf0, 0xc8, 0xe2,
+       0x09, 0xd3, 0x60, 0x9d, 0x17, 0x94, 0x77, 0x27, 0xe2, 0xc7, 0x37, 0xff,
+       0xb7, 0x3a, 0xa8, 0xdf, 0xc9, 0xa4, 0x69, 0x9c, 0x8f, 0xa7, 0xc6, 0x3a,
+       0x27, 0x4e, 0xa3, 0xf3, 0x6d, 0xa6, 0x46, 0x8e, 0x7c, 0x33, 0xf3, 0xd3,
+       0x04, 0xfa, 0x7d, 0x99, 0x6f, 0x8f, 0x8f, 0xc4, 0x73, 0xef, 0xa6, 0x84,
+       0xe2, 0xc9, 0xd8, 0xaf, 0x39, 0x95, 0xdb, 0x0d, 0x3e, 0x8e, 0xeb, 0xa2,
+       0xf8, 0x8e, 0x8f, 0x97, 0xfc, 0x2d, 0x81, 0xf4, 0xce, 0xeb, 0xf8, 0xbb,
+       0xac, 0x3f, 0x74, 0x9e, 0x03, 0xe3, 0x99, 0x39, 0x1d, 0xdc, 0xb6, 0x9c,
+       0xfb, 0x23, 0xc6, 0xb3, 0x06, 0xa2, 0xdf, 0x58, 0x5f, 0x9c, 0xac, 0x19,
+       0xe7, 0xf1, 0x3f, 0x2d, 0x9e, 0xd9, 0x17, 0x6f, 0xbc, 0x9b, 0x7e, 0x57,
+       0xe4, 0xe5, 0x26, 0x4f, 0xca, 0x99, 0xd1, 0x03, 0xf1, 0x91, 0x1f, 0x74,
+       0xec, 0x39, 0x1b, 0xdc, 0x68, 0x1a, 0x8e, 0x1c, 0x2a, 0xa5, 0xf8, 0xde,
+       0xf0, 0x63, 0xb7, 0x25, 0x41, 0xbe, 0xf1, 0xc8, 0x4b, 0x3c, 0x1f, 0x7f,
+       0xec, 0x72, 0x12, 0xe0, 0xe6, 0xf6, 0x23, 0x1d, 0x3c, 0x3f, 0xee, 0xd8,
+       0x65, 0x8c, 0x07, 0x5e, 0x77, 0xe4, 0x48, 0x29, 0xc5, 0xff, 0xa2, 0xdd,
+       0x60, 0x04, 0x63, 0x77, 0x1c, 0x79, 0xb9, 0xd4, 0x05, 0xf8, 0xa8, 0x9e,
+       0xe0, 0x6c, 0x42, 0x7c, 0x2d, 0xba, 0xd2, 0xf0, 0x2a, 0x1e, 0xc3, 0xef,
+       0xad, 0x9f, 0xbf, 0x3c, 0x89, 0xe2, 0x59, 0xe7, 0x25, 0xa4, 0xf3, 0x78,
+       0xd6, 0xb5, 0x58, 0xbe, 0x30, 0x7a, 0xd9, 0x86, 0x70, 0xc5, 0x17, 0xcf,
+       0xba, 0x6d, 0x1a, 0xb4, 0x03, 0x7a, 0xe8, 0xb9, 0xc4, 0xe9, 0xbf, 0xe7,
+       0x12, 0xa7, 0xf7, 0x20, 0xe4, 0x03, 0xc3, 0xff, 0xf5, 0x54, 0xc6, 0xf5,
+       0x4a, 0xfe, 0x3b, 0x14, 0x9f, 0x94, 0xfb, 0xef, 0xc7, 0x8a, 0x4b, 0x96,
+       0xfb, 0x98, 0xed, 0xb2, 0x6f, 0x36, 0x20, 0x31, 0xba, 0xfe, 0xe5, 0x78,
+       0xe1, 0x47, 0x68, 0xdf, 0x04, 0xc4, 0x0b, 0xf7, 0x18, 0x7a, 0x1f, 0x27,
+       0x7b, 0xd2, 0x25, 0x66, 0xc3, 0x38, 0xc4, 0xa3, 0xa1, 0xef, 0xdb, 0xf0,
+       0x9c, 0x68, 0xce, 0xe5, 0xf1, 0x8c, 0x4a, 0x6f, 0xa7, 0x0d, 0xfd, 0x30,
+       0xf2, 0x73, 0x78, 0xbe, 0xf9, 0x52, 0xa7, 0x0d, 0xf9, 0x3b, 0xe6, 0x51,
+       0xaf, 0xd5, 0x13, 0xc1, 0xe3, 0x1c, 0x65, 0x3c, 0x6c, 0xf3, 0x25, 0x6f,
+       0x1c, 0xee, 0x93, 0x7c, 0x8c, 0x5b, 0x84, 0xfa, 0x85, 0xbd, 0xbd, 0xa5,
+       0xc8, 0x6f, 0xf2, 0xd1, 0x8f, 0x37, 0x09, 0xfb, 0x7f, 0xed, 0xb8, 0x18,
+       0x8f, 0x61, 0x7f, 0x3b, 0x2e, 0xf1, 0x78, 0xc3, 0x1e, 0x73, 0xa7, 0xcd,
+       0x2a, 0xc6, 0xc1, 0x7e, 0x60, 0xdc, 0x24, 0xe4, 0x8b, 0xf9, 0x6b, 0x4d,
+       0xe4, 0x6f, 0xd4, 0x7c, 0xa9, 0x61, 0x35, 0xf5, 0x53, 0x62, 0xe9, 0x1f,
+       0x57, 0x09, 0x18, 0xd7, 0xf4, 0xdd, 0xe3, 0xce, 0x52, 0xfc, 0xc6, 0x4d,
+       0xed, 0xe3, 0x71, 0x9d, 0x38, 0xae, 0x4d, 0x33, 0xae, 0x97, 0xe2, 0x81,
+       0xa1, 0x3f, 0x8a, 0x3b, 0xed, 0x89, 0xb0, 0xc7, 0xe2, 0x7d, 0x5f, 0xe6,
+       0x0b, 0xb1, 0x1c, 0xf2, 0x0f, 0x89, 0xdf, 0xa7, 0xc8, 0xb7, 0x79, 0x55,
+       0xe4, 0xff, 0x32, 0x3e, 0x2a, 0xc6, 0x28, 0xde, 0xe1, 0x16, 0xf7, 0x15,
+       0xa8, 0x47, 0xf1, 0x98, 0x3b, 0xfa, 0xf8, 0x3a, 0x2f, 0x36, 0x79, 0xab,
+       0x71, 0x3f, 0x15, 0x0a, 0x7e, 0x5d, 0x68, 0xe4, 0xe7, 0x25, 0xd3, 0x05,
+       0xdb, 0xd1, 0x0f, 0xbb, 0x48, 0xfd, 0xf6, 0xb5, 0x78, 0xbc, 0x97, 0xbc,
+       0xc0, 0xef, 0x25, 0x85, 0x41, 0xc5, 0xdb, 0x70, 0x3f, 0xd6, 0xeb, 0x39,
+       0xbf, 0x61, 0x51, 0xf2, 0x77, 0xd2, 0x3a, 0x57, 0xfe, 0x06, 0xea, 0xbd,
+       0x13, 0x1d, 0x4f, 0xbf, 0x2b, 0x36, 0x32, 0xf6, 0x10, 0x4b, 0xc5, 0x7b,
+       0xf1, 0xaa, 0x39, 0x19, 0x78, 0x5e, 0x80, 0xbc, 0xfd, 0x11, 0xe2, 0xfb,
+       0x1d, 0xd6, 0xaa, 0xf0, 0xdf, 0xdf, 0xe2, 0xed, 0x17, 0xcc, 0x09, 0x21,
+       0xff, 0x93, 0x9e, 0x23, 0x63, 0x72, 0x71, 0xff, 0xcc, 0x0f, 0xb2, 0x1d,
+       0x64, 0xb0, 0x6f, 0x4f, 0x4d, 0xbb, 0x44, 0xfb, 0x74, 0x7e, 0xb8, 0x2d,
+       0x17, 0x6f, 0x3a, 0xa7, 0x8e, 0x5c, 0xe6, 0xf9, 0x18, 0xdb, 0x41, 0xb4,
+       0xeb, 0x9a, 0xd8, 0xa5, 0xd2, 0x42, 0xba, 0xa7, 0x71, 0x3b, 0xed, 0x4d,
+       0x3e, 0x3b, 0xed, 0xa7, 0xb8, 0x2f, 0xeb, 0xe6, 0x5c, 0x30, 0x72, 0xb9,
+       0xac, 0x97, 0xde, 0x67, 0x3e, 0x37, 0x8d, 0x9f, 0x5f, 0x20, 0xb7, 0x93,
+       0xdc, 0xd1, 0x7b, 0x8d, 0x78, 0x6f, 0x33, 0xc3, 0x96, 0x8b, 0xe5, 0x89,
+       0x86, 0xde, 0x30, 0x84, 0x5b, 0xcf, 0xb7, 0x7a, 0xfe, 0x5e, 0x2d, 0xeb,
+       0x0d, 0xbb, 0xd1, 0xcf, 0x2e, 0xfb, 0x78, 0x07, 0x7f, 0xc7, 0x36, 0x90,
+       0xae, 0xf7, 0x15, 0xf0, 0x73, 0x60, 0x55, 0xaa, 0x85, 0xde, 0x39, 0xab,
+       0x8f, 0x35, 0x99, 0x28, 0xed, 0xb8, 0x34, 0x9b, 0x7e, 0x07, 0x46, 0x5f,
+       0x9c, 0x8a, 0xf7, 0x02, 0x87, 0x71, 0x70, 0x7d, 0xe3, 0x13, 0x05, 0x5c,
+       0xde, 0x4c, 0xda, 0x68, 0xf4, 0xd9, 0xdd, 0xe1, 0xfc, 0x70, 0x04, 0x33,
+       0x99, 0x77, 0xb1, 0x3c, 0xc6, 0xb6, 0xff, 0x5b, 0x70, 0xff, 0xbd, 0x0b,
+       0x8f, 0x18, 0xe3, 0x68, 0x71, 0x0f, 0x73, 0x59, 0x9f, 0x28, 0x4c, 0xd5,
+       0xd4, 0x77, 0x60, 0xfd, 0xfe, 0x72, 0xc6, 0x9f, 0x67, 0x93, 0xed, 0x47,
+       0xbe, 0xac, 0x7f, 0x02, 0xed, 0xf8, 0x34, 0x1e, 0xe2, 0xb9, 0x92, 0xfb,
+       0x4d, 0x04, 0x9e, 0x17, 0xa5, 0xd3, 0x23, 0x35, 0xfe, 0x56, 0x8f, 0x45,
+       0x99, 0xc9, 0xdf, 0x2a, 0x55, 0x15, 0x7a, 0x3c, 0xa8, 0x6b, 0x25, 0x7d,
+       0x20, 0xb7, 0xdb, 0xc6, 0xff, 0xa7, 0x99, 0xe2, 0xe7, 0x76, 0x98, 0x39,
+       0x1d, 0xa6, 0xea, 0x78, 0xba, 0x43, 0x27, 0xe2, 0x7c, 0x85, 0x9e, 0x4f,
+       0xde, 0x5f, 0x7e, 0x31, 0xdd, 0x39, 0x7e, 0x7a, 0x2e, 0xf5, 0xe3, 0xa5,
+       0x7e, 0xd4, 0xfd, 0x99, 0x28, 0x4f, 0xc4, 0x31, 0x0f, 0x8d, 0x2f, 0xe5,
+       0x32, 0x59, 0x0f, 0xe4, 0x2f, 0x33, 0x31, 0x19, 0xf1, 0x3b, 0x6f, 0xf9,
+       0xaa, 0x6e, 0x50, 0x78, 0xbe, 0x52, 0x30, 0xc3, 0x51, 0x90, 0x8b, 0x74,
+       0xed, 0x62, 0x9f, 0xf8, 0x9d, 0x13, 0x17, 0x43, 0xc2, 0x1a, 0xfd, 0xf1,
+       0x57, 0xaf, 0x6a, 0xf5, 0x9d, 0xaf, 0x14, 0xcc, 0xa4, 0x76, 0xb2, 0x7d,
+       0x5d, 0xe3, 0x2c, 0xf6, 0x09, 0xc5, 0x21, 0x7a, 0x89, 0x7e, 0xea, 0x52,
+       0x75, 0x74, 0x5f, 0xad, 0x57, 0xd9, 0x2b, 0xf4, 0x7b, 0x03, 0xac, 0x93,
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+       0xbe, 0xdf, 0x72, 0x8d, 0x4d, 0xfb, 0xfb, 0x4c, 0xd7, 0xa5, 0x6b, 0x7f,
+       0x9f, 0xa9, 0xcf, 0x22, 0xe0, 0x23, 0xe4, 0x41, 0x29, 0xa7, 0xee, 0x9e,
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+       0xff, 0x9f, 0xfe, 0xbf, 0x49, 0xff, 0x0f, 0x42, 0x61, 0x39, 0x64, 0x00,
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+       0xf3, 0xcc, 0x73, 0x08, 0x21, 0x09, 0x04, 0xc2, 0x24, 0x24, 0x21, 0x60,
+       0x88, 0x03, 0x24, 0x54, 0x2b, 0x96, 0xc9, 0xd3, 0x00, 0xd6, 0x06, 0x5c,
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+       0x19, 0x04, 0x11, 0x10, 0x5b, 0xa8, 0xd1, 0xa2, 0x22, 0x4e, 0x82, 0xe1,
+       0xa1, 0x61, 0x9d, 0x08, 0xc1, 0x44, 0x43, 0x1d, 0x14, 0xb2, 0x88, 0xd6,
+       0x8d, 0x74, 0x8b, 0xfd, 0xfd, 0x56, 0xdc, 0xf8, 0x28, 0xf2, 0x32, 0x13,
+       0xa3, 0x74, 0xe5, 0x57, 0x2d, 0x7b, 0xfe, 0xe7, 0x7e, 0x1f, 0x99, 0x0c,
+       0xa1, 0xda, 0xee, 0x6e, 0xf2, 0xd3, 0x93, 0x73, 0x5f, 0xdf, 0xb9, 0xe7,
+       0x7d, 0xcf, 0xbd, 0xd4, 0x14, 0xe7, 0x18, 0xbe, 0x9a, 0x22, 0x44, 0x6e,
+       0xcc, 0x59, 0x73, 0x4f, 0x84, 0x10, 0xae, 0x95, 0x3d, 0x45, 0x89, 0xd9,
+       0x42, 0xf4, 0xbd, 0xa9, 0x8a, 0x26, 0x87, 0x10, 0xc2, 0xed, 0x3d, 0x56,
+       0x1f, 0x2b, 0x44, 0x6d, 0xc7, 0x70, 0xb1, 0x29, 0x99, 0xf0, 0x92, 0xbe,
+       0xb7, 0x0c, 0xc0, 0xdb, 0xc6, 0xd9, 0x37, 0x51, 0xff, 0xc6, 0xf6, 0x3f,
+       0xbc, 0x83, 0xfe, 0xde, 0x03, 0xaa, 0xc3, 0x42, 0xfd, 0xaf, 0xb7, 0x7f,
+       0x1c, 0x85, 0x75, 0x2e, 0x7c, 0x15, 0x2e, 0xc4, 0x70, 0xcc, 0xfb, 0x38,
+       0x4a, 0x10, 0x5e, 0x7d, 0x49, 0x61, 0x7c, 0x13, 0xf5, 0x3b, 0x08, 0x9f,
+       0xd9, 0xaa, 0x0a, 0x7f, 0x26, 0xad, 0x67, 0xf4, 0x99, 0xd1, 0x7f, 0x21,
+       0x55, 0xc7, 0xbd, 0x66, 0x41, 0xb0, 0xa4, 0xa5, 0xd5, 0xdc, 0x43, 0xb0,
+       0x6a, 0x4f, 0x2b, 0xf7, 0xbf, 0xe9, 0x33, 0x0d, 0xee, 0xdf, 0xd3, 0x38,
+       0xa8, 0xdf, 0x8e, 0xf1, 0x04, 0xab, 0x8c, 0xde, 0x28, 0x3b, 0xc1, 0x73,
+       0xed, 0xfa, 0x7a, 0x7e, 0x1e, 0x5f, 0x9d, 0xaa, 0xb8, 0xbc, 0x68, 0xdf,
+       0xf3, 0x87, 0xb8, 0xa5, 0x18, 0xd7, 0xf2, 0x6e, 0xdc, 0x12, 0x82, 0x97,
+       0xf1, 0x33, 0xe3, 0x6a, 0xf8, 0xd9, 0xc1, 0x17, 0x32, 0xdd, 0x34, 0xaf,
+       0xa6, 0x83, 0xd6, 0x89, 0x18, 0x58, 0xa7, 0xa6, 0xc3, 0xa4, 0xe1, 0x92,
+       0xee, 0xea, 0xd4, 0xd6, 0xa2, 0x18, 0xe2, 0x97, 0x68, 0x51, 0x44, 0x1a,
+       0x81, 0x0b, 0x62, 0x8b, 0x58, 0x45, 0xfc, 0xac, 0x6a, 0x6f, 0xae, 0x16,
+       0xd4, 0x5e, 0x95, 0x71, 0xb7, 0x49, 0x10, 0x5f, 0x02, 0x3e, 0xb5, 0x18,
+       0xdf, 0xa7, 0x1f, 0x83, 0x88, 0xa3, 0x79, 0x76, 0xfa, 0x8b, 0xf8, 0x77,
+       0xc1, 0xf7, 0x45, 0xd4, 0x12, 0x5a, 0xf7, 0x35, 0xdf, 0xd1, 0xdb, 0x5c,
+       0x04, 0x03, 0x9d, 0x6f, 0x44, 0xe1, 0xbb, 0x81, 0x03, 0x34, 0x3e, 0x73,
+       0x80, 0x9e, 0xe9, 0x2e, 0xe2, 0x5f, 0x0e, 0xa0, 0x59, 0x88, 0x11, 0x34,
+       0xef, 0xc0, 0x1b, 0x51, 0x0e, 0xea, 0xdf, 0xe8, 0x7b, 0x43, 0xf2, 0xdb,
+       0xe8, 0xe7, 0x7d, 0xbf, 0xae, 0xe1, 0x01, 0x82, 0xcc, 0xe7, 0x76, 0x95,
+       0xf7, 0x5d, 0xf1, 0x95, 0xca, 0xfc, 0xd7, 0xd7, 0xbb, 0xc5, 0xa5, 0xf2,
+       0x3a, 0x33, 0xdb, 0xd3, 0x22, 0xb1, 0xaf, 0x13, 0x3e, 0xf9, 0xbd, 0x39,
+       0x2e, 0x87, 0x6c, 0x4f, 0x5d, 0x54, 0x06, 0xfa, 0x8f, 0x27, 0xcc, 0xcf,
+       0x51, 0x93, 0x99, 0x6e, 0x17, 0xf0, 0xc0, 0xc4, 0xd9, 0xcd, 0x9b, 0x88,
+       0x94, 0x2a, 0x1f, 0xad, 0x9b, 0x79, 0x35, 0xdf, 0x96, 0x68, 0xeb, 0x76,
+       0x99, 0xc4, 0x3c, 0x1f, 0xe4, 0x96, 0xba, 0xbf, 0x6b, 0x14, 0xe9, 0xc7,
+       0xf1, 0xe2, 0xe1, 0x93, 0xa9, 0xe7, 0xca, 0xb8, 0xbb, 0x5d, 0x06, 0x1e,
+       0x57, 0x64, 0x76, 0xa7, 0x2e, 0xa7, 0x71, 0x27, 0x22, 0x1c, 0x91, 0x76,
+       0x5a, 0xef, 0xc1, 0xe2, 0x71, 0x91, 0x90, 0xeb, 0xeb, 0x80, 0x68, 0x2f,
+       0xde, 0x69, 0x76, 0x13, 0xac, 0x3c, 0x20, 0xbf, 0x77, 0xc2, 0xde, 0x1d,
+       0x05, 0x7d, 0x3b, 0x71, 0x60, 0xaa, 0xea, 0x51, 0x06, 0xd6, 0xbb, 0x43,
+       0xfb, 0xae, 0x10, 0x1e, 0x86, 0x03, 0x72, 0xf3, 0xb0, 0x9c, 0xca, 0xbd,
+       0x8d, 0x11, 0x58, 0x67, 0x40, 0x7e, 0xb2, 0x7d, 0x8e, 0xcb, 0xce, 0xe3,
+       0x8f, 0x7b, 0xdf, 0xbd, 0xf3, 0x6e, 0xda, 0xdf, 0x89, 0x8c, 0x70, 0x27,
+       0xe4, 0xd2, 0x65, 0x16, 0xe5, 0x3e, 0xd6, 0x13, 0xfa, 0x08, 0xbe, 0xd7,
+       0x99, 0xd8, 0x08, 0x3e, 0xe8, 0xdf, 0x9b, 0x03, 0x79, 0xd0, 0xbc, 0x40,
+       0x86, 0x81, 0xe5, 0xda, 0xdb, 0x6e, 0xd2, 0xc6, 0xdd, 0xdd, 0x2c, 0x06,
+       0x8d, 0x33, 0xb1, 0xdc, 0x2e, 0x3c, 0x37, 0x98, 0x1e, 0xbb, 0xf7, 0xc3,
+       0x5f, 0xdd, 0x4d, 0xe3, 0xab, 0x9f, 0x51, 0x85, 0x85, 0x9a, 0xab, 0x4d,
+       0xcb, 0xe3, 0xb0, 0xff, 0x4f, 0xb7, 0x0f, 0xa6, 0xaf, 0x5c, 0xe3, 0x73,
+       0xb5, 0xc9, 0x1f, 0x17, 0x17, 0xa4, 0xaf, 0xd5, 0x1d, 0x57, 0xec, 0x25,
+       0x82, 0xf5, 0xbb, 0x43, 0xb7, 0x0f, 0x07, 0xcb, 0x53, 0x97, 0xe3, 0x89,
+       0x0c, 0x55, 0xd2, 0x95, 0x60, 0xf1, 0x0a, 0x22, 0xb9, 0xba, 0xb5, 0x99,
+       0xf5, 0x9a, 0xcc, 0xcd, 0x63, 0x9b, 0xc2, 0x50, 0xd8, 0x09, 0x26, 0x86,
+       0x77, 0x27, 0x2b, 0xb4, 0xff, 0xc4, 0xfb, 0xad, 0xce, 0xb5, 0x44, 0xff,
+       0x73, 0x8a, 0xd6, 0x6f, 0x20, 0x18, 0x43, 0xb8, 0x41, 0xe2, 0x66, 0x82,
+       0x56, 0x82, 0xcf, 0x98, 0x64, 0x3b, 0xcc, 0x16, 0xf3, 0xc7, 0x90, 0x38,
+       0x15, 0xc2, 0x4d, 0xc5, 0xe3, 0x72, 0x0c, 0x29, 0xb4, 0x8e, 0xda, 0x3a,
+       0x19, 0x72, 0x7d, 0x71, 0x86, 0xeb, 0x51, 0x17, 0xed, 0xff, 0x97, 0x33,
+       0x4a, 0x26, 0xcd, 0x20, 0x78, 0x42, 0xf4, 0x2d, 0x15, 0xf4, 0xcd, 0x9a,
+       0x8b, 0x11, 0x1e, 0x11, 0x2d, 0x44, 0xa1, 0xfa, 0xfe, 0x13, 0xf8, 0x6e,
+       0xff, 0x01, 0x93, 0x80, 0xff, 0xa8, 0xb1, 0x76, 0x54, 0x7e, 0x42, 0x7a,
+       0xda, 0xef, 0x24, 0x43, 0x21, 0xba, 0xfb, 0xb7, 0x9b, 0xbc, 0x1e, 0xd6,
+       0x3f, 0x57, 0x84, 0x32, 0x4d, 0x88, 0xa5, 0x37, 0x48, 0xbb, 0xf9, 0xd4,
+       0xe1, 0x9e, 0xa6, 0x8e, 0xa3, 0xf1, 0x6b, 0x0c, 0xbc, 0xbf, 0xea, 0x16,
+       0xd5, 0x6b, 0xa3, 0x71, 0xbd, 0xf5, 0xc4, 0x02, 0x62, 0xf9, 0x67, 0xad,
+       0xc9, 0x3f, 0x82, 0xbe, 0x56, 0x1f, 0x53, 0xed, 0x56, 0xda, 0x77, 0xbe,
+       0x2f, 0xf9, 0xd7, 0xd3, 0x81, 0xb7, 0x98, 0x9c, 0x16, 0x9a, 0x5f, 0xeb,
+       0xa3, 0x46, 0xc2, 0x6b, 0xf7, 0x28, 0x5e, 0x87, 0x5c, 0x5f, 0xc0, 0x2e,
+       0x6b, 0x6e, 0x60, 0x5d, 0x17, 0xa7, 0x6d, 0xb5, 0x29, 0x22, 0x8b, 0xe0,
+       0x9a, 0x3e, 0x33, 0xc6, 0x9d, 0x3e, 0xa4, 0x88, 0xc7, 0x68, 0xdc, 0x23,
+       0x61, 0x51, 0x4d, 0xa0, 0xbb, 0x26, 0x73, 0xd6, 0x59, 0x25, 0x8a, 0xa0,
+       0xba, 0x79, 0x7d, 0x22, 0xad, 0xb7, 0x6c, 0x9b, 0xe9, 0xa3, 0x1e, 0xab,
+       0x9c, 0x7b, 0x99, 0xfe, 0xab, 0xeb, 0xdc, 0xca, 0x7a, 0x5b, 0xe1, 0x1d,
+       0xdc, 0x5e, 0xb5, 0x67, 0x30, 0x5e, 0x23, 0x8c, 0x03, 0x38, 0xad, 0xdf,
+       0x8c, 0x3f, 0x6e, 0x14, 0xa2, 0xcd, 0x15, 0x19, 0x7b, 0xfa, 0x3a, 0xfa,
+       0x7b, 0x82, 0x98, 0x70, 0x59, 0x05, 0x9f, 0xa6, 0xc7, 0xc3, 0x1e, 0x8e,
+       0x43, 0xae, 0xc4, 0x47, 0xd1, 0x40, 0xcc, 0x1e, 0x29, 0xc4, 0xbd, 0x93,
+       0x9c, 0xf1, 0xb0, 0xfb, 0x8d, 0x46, 0xc7, 0x2c, 0xf0, 0x21, 0xd0, 0x69,
+       0xb2, 0x83, 0x5f, 0x75, 0x87, 0xf6, 0x57, 0x80, 0x6e, 0x6f, 0x75, 0x98,
+       0xd3, 0x40, 0x5b, 0xad, 0x5d, 0xf5, 0x2a, 0xf3, 0x35, 0xf0, 0x25, 0xf1,
+       0xfd, 0x7a, 0x82, 0x09, 0x82, 0xf7, 0x1f, 0x10, 0x92, 0xbf, 0x81, 0x76,
+       0xa9, 0xe7, 0x75, 0x26, 0xc5, 0x6b, 0xc5, 0x7c, 0xe2, 0x21, 0xaf, 0x67,
+       0x55, 0xbc, 0x6b, 0xa8, 0x2b, 0xe0, 0xe9, 0x8f, 0x62, 0xff, 0x24, 0x44,
+       0x31, 0xec, 0x62, 0xe5, 0xfc, 0x1c, 0x03, 0xfc, 0x1c, 0xcc, 0x58, 0x10,
+       0x29, 0xbf, 0xd6, 0xed, 0x41, 0xb1, 0x19, 0x95, 0x68, 0x40, 0x69, 0xff,
+       0x3f, 0x30, 0xf6, 0xa8, 0xc3, 0x82, 0xfc, 0xc4, 0x7f, 0xb9, 0x52, 0x98,
+       0xfe, 0x02, 0xb3, 0x70, 0xfb, 0xa8, 0xfd, 0xde, 0x48, 0x67, 0x34, 0xf4,
+       0x7e, 0xac, 0x35, 0x2a, 0x0b, 0x74, 0x8d, 0xb5, 0x26, 0x79, 0xc1, 0xf7,
+       0xb1, 0xc6, 0xbe, 0x35, 0xf8, 0xfe, 0x23, 0xa3, 0x14, 0xc7, 0x83, 0xb4,
+       0xf4, 0xe1, 0xac, 0x57, 0x26, 0x2b, 0xc0, 0x6b, 0x23, 0x9c, 0xd0, 0x13,
+       0x25, 0x61, 0x91, 0x11, 0xfc, 0x78, 0x64, 0xd4, 0x22, 0x23, 0xf4, 0x7d,
+       0xac, 0xdd, 0x97, 0x51, 0x92, 0x39, 0x80, 0x17, 0xa0, 0x1f, 0xf6, 0x20,
+       0xbc, 0xfc, 0xbd, 0xa2, 0x08, 0xb7, 0x11, 0xdf, 0x79, 0x6e, 0xa4, 0xe2,
+       0x37, 0xd0, 0xfa, 0x01, 0x1b, 0xd1, 0x07, 0x3b, 0x31, 0xda, 0x4d, 0xa0,
+       0x2f, 0x60, 0x92, 0xb8, 0x10, 0x6b, 0x06, 0xd1, 0x47, 0x1e, 0x89, 0xf1,
+       0xff, 0x77, 0xfa, 0xec, 0x44, 0x5f, 0xc4, 0x00, 0x7d, 0x24, 0xef, 0x68,
+       0xcc, 0xff, 0x22, 0x9b, 0xf8, 0x43, 0x30, 0x69, 0x8e, 0x10, 0xdd, 0xec,
+       0x17, 0x96, 0xb3, 0x5f, 0xd0, 0xf9, 0x79, 0x81, 0xf4, 0xbd, 0x80, 0x64,
+       0x95, 0xa6, 0x48, 0xbd, 0xa9, 0xde, 0x7e, 0xb8, 0x08, 0xfd, 0x35, 0xa2,
+       0x7b, 0x3d, 0xe6, 0x15, 0x45, 0xc9, 0x7d, 0x14, 0x61, 0x3f, 0xc0, 0xc3,
+       0x24, 0x54, 0x73, 0xa5, 0xbc, 0x72, 0x35, 0x78, 0x5f, 0xae, 0x8c, 0x2f,
+       0xba, 0xff, 0xec, 0xc8, 0x75, 0x19, 0x73, 0x09, 0x6e, 0xcb, 0x2d, 0x31,
+       0x03, 0x16, 0xaa, 0x99, 0xf1, 0x3d, 0x43, 0xf8, 0xfb, 0x95, 0x8a, 0x95,
+       0xf5, 0xe4, 0x0b, 0xb2, 0x3f, 0xf8, 0xe3, 0x7b, 0x96, 0x2b, 0xf6, 0xd4,
+       0x8c, 0x01, 0xfd, 0xd6, 0xed, 0xaa, 0x4e, 0x36, 0x5d, 0xb1, 0x9f, 0xaa,
+       0xdf, 0xef, 0x34, 0x8b, 0x14, 0x7c, 0xce, 0xd5, 0x9d, 0x41, 0xfd, 0xe5,
+       0x42, 0xda, 0xf5, 0xc2, 0x55, 0x36, 0x7b, 0x6a, 0xb0, 0x1d, 0xc1, 0xce,
+       0x88, 0x1f, 0xe5, 0xf6, 0x8a, 0x5b, 0x05, 0xd9, 0x9b, 0x7b, 0x55, 0x9c,
+       0x3d, 0x75, 0x2a, 0xb5, 0xab, 0x17, 0xcc, 0x02, 0xba, 0xa7, 0xd9, 0x57,
+       0x2c, 0xfd, 0x5e, 0x4e, 0x19, 0xc2, 0xbe, 0x7c, 0x21, 0x76, 0xd9, 0x3e,
+       0x18, 0xf7, 0xdb, 0xa4, 0x9e, 0xfb, 0x23, 0x15, 0xef, 0x5a, 0xa2, 0x3f,
+       0x35, 0x77, 0xb0, 0xdd, 0x25, 0x69, 0x76, 0xd0, 0xe8, 0x56, 0x78, 0x7f,
+       0x8d, 0x5f, 0x1b, 0x19, 0xf7, 0x94, 0x2a, 0x5e, 0xf0, 0xfc, 0x0e, 0x6a,
+       0x5c, 0x15, 0xa3, 0x6d, 0x0e, 0xe3, 0xca, 0x73, 0xbd, 0x88, 0x8f, 0x77,
+       0x10, 0x5a, 0x8a, 0xf6, 0x86, 0x58, 0xb6, 0x53, 0xee, 0x24, 0xff, 0xf5,
+       0x2f, 0xda, 0x3e, 0xef, 0x30, 0xfa, 0x0f, 0xc3, 0x7f, 0x1c, 0x35, 0xf9,
+       0x92, 0xed, 0xd4, 0x75, 0xb4, 0xc6, 0xea, 0xc4, 0xfa, 0xf3, 0x05, 0x25,
+       0x3a, 0xe4, 0xd7, 0x4a, 0x45, 0x37, 0xc3, 0x93, 0xe1, 0xb5, 0x6d, 0x7e,
+       0x5e, 0xdc, 0x33, 0x06, 0xfa, 0xf5, 0x9e, 0xdb, 0xe2, 0x44, 0x1e, 0xd6,
+       0xb8, 0xae, 0x29, 0x12, 0x7e, 0x3c, 0x4b, 0xac, 0xb3, 0x9f, 0xce, 0x40,
+       0x52, 0x21, 0xf6, 0x5c, 0x9e, 0x7a, 0xed, 0x7c, 0x86, 0x14, 0x47, 0x9c,
+       0xd6, 0xe5, 0x82, 0x40, 0x4c, 0x79, 0x0a, 0xe4, 0xad, 0xcb, 0x75, 0x5b,
+       0xae, 0x2b, 0x2f, 0x37, 0xe7, 0xda, 0xf3, 0xab, 0xfe, 0xd8, 0x76, 0xdb,
+       0xf7, 0xe0, 0xbf, 0xee, 0x6b, 0x36, 0xc7, 0x4b, 0x35, 0xe9, 0xce, 0x98,
+       0x36, 0x20, 0x37, 0x5d, 0xae, 0x75, 0xc2, 0xc3, 0x74, 0xeb, 0xf2, 0xba,
+       0x22, 0x3f, 0xa2, 0x7d, 0x34, 0xf8, 0xa1, 0x5e, 0x98, 0xc3, 0x7e, 0xe6,
+       0x59, 0x55, 0x70, 0x5e, 0xa1, 0xc9, 0xcf, 0x4a, 0xbf, 0x43, 0xc9, 0x4f,
+       0xe7, 0xef, 0x0c, 0x4d, 0x0e, 0xcb, 0x3a, 0xa4, 0x3f, 0x0a, 0x95, 0xab,
+       0xce, 0xef, 0x1f, 0xd3, 0x82, 0xf8, 0x3e, 0xc5, 0xd1, 0xed, 0x2c, 0x0f,
+       0x61, 0x61, 0xff, 0x17, 0x2a, 0xf7, 0x6f, 0x93, 0x0b, 0x65, 0x98, 0xa5,
+       0xe8, 0xca, 0x8f, 0xb5, 0x08, 0xc8, 0x33, 0xd1, 0x20, 0xfd, 0x63, 0xe2,
+       0x52, 0xd2, 0x13, 0xa2, 0xfb, 0x6e, 0xe1, 0x3e, 0xd4, 0x43, 0xf0, 0xce,
+       0xf0, 0xb7, 0x4d, 0xac, 0x87, 0x9a, 0x7c, 0xee, 0x81, 0x7c, 0x68, 0xe8,
+       0x7b, 0xc2, 0xfb, 0xc3, 0x8c, 0xe4, 0xff, 0x3b, 0xf9, 0x74, 0xe4, 0x96,
+       0xdc, 0x1f, 0x6c, 0x87, 0xa1, 0x76, 0x77, 0x2d, 0x3b, 0xab, 0x76, 0x38,
+       0xff, 0x5d, 0x8f, 0x7b, 0xe4, 0x69, 0xc8, 0xbe, 0x42, 0xec, 0x33, 0xc4,
+       0xfe, 0x74, 0x79, 0xb9, 0x57, 0x45, 0xb1, 0x9d, 0x5d, 0x91, 0xa3, 0xda,
+       0x22, 0xed, 0x55, 0x93, 0x57, 0x04, 0xfd, 0x0e, 0x69, 0x6f, 0xf8, 0x83,
+       0xbe, 0x57, 0xd3, 0xae, 0x78, 0xfd, 0xc9, 0xdf, 0xc1, 0xfe, 0x14, 0x22,
+       0x9c, 0xe4, 0xf6, 0x58, 0x88, 0xdd, 0xe9, 0xf2, 0xb9, 0x96, 0xdf, 0xd1,
+       0xfd, 0xd4, 0x29, 0xe1, 0x3f, 0x6a, 0xa7, 0xfd, 0x9f, 0x4c, 0x91, 0x79,
+       0x80, 0xe7, 0x67, 0x16, 0x6f, 0x33, 0xf0, 0x74, 0x43, 0x39, 0xfc, 0xde,
+       0xc9, 0x89, 0x12, 0xee, 0xd7, 0xfc, 0x5b, 0x28, 0x3c, 0x45, 0x79, 0x8e,
+       0x42, 0x71, 0x6c, 0x53, 0xc6, 0x89, 0x11, 0x88, 0xd7, 0x27, 0xcd, 0xfa,
+       0x3a, 0x36, 0x6f, 0x33, 0xd1, 0x7f, 0x6a, 0x4d, 0xf7, 0x98, 0x15, 0x34,
+       0xff, 0x54, 0xae, 0x84, 0x27, 0x91, 0x17, 0x06, 0xe1, 0xae, 0x30, 0xb1,
+       0x10, 0x7e, 0xfd, 0xd4, 0x48, 0x8b, 0x07, 0x7c, 0x3a, 0xa5, 0x4c, 0xc8,
+       0x43, 0x7c, 0x38, 0xa5, 0xdc, 0x7f, 0x9b, 0xc4, 0xe3, 0xcd, 0x0e, 0xe0,
+       0xf3, 0xe3, 0xf3, 0xec, 0x84, 0x9f, 0x34, 0xc9, 0xf1, 0x7a, 0x5c, 0xd1,
+       0xfd, 0xff, 0xa9, 0xf9, 0xdf, 0x2b, 0xe0, 0x71, 0x8a, 0x38, 0x02, 0x7e,
+       0x38, 0x14, 0x51, 0xc2, 0xdf, 0x51, 0x94, 0x98, 0x62, 0xa2, 0xe7, 0xd4,
+       0x7d, 0x69, 0x53, 0xd6, 0x8a, 0x81, 0xfd, 0x37, 0xe5, 0x1a, 0x78, 0x9e,
+       0x57, 0xf3, 0xdf, 0x44, 0x07, 0xf3, 0xbd, 0xef, 0xe7, 0x8a, 0xb7, 0x89,
+       0x9a, 0x16, 0x22, 0xa4, 0x10, 0xfd, 0xc9, 0x79, 0xbf, 0x2d, 0x4e, 0xa1,
+       0xf6, 0x0f, 0x7e, 0x31, 0x6e, 0x32, 0xe4, 0xeb, 0x5a, 0x39, 0xf8, 0xfb,
+       0x88, 0xd7, 0xc9, 0xd7, 0x03, 0xdf, 0xca, 0xeb, 0xfc, 0xe0, 0xab, 0x3e,
+       0xd3, 0xa2, 0xa0, 0xb8, 0x74, 0x25, 0x4e, 0x16, 0x7c, 0x2e, 0xdb, 0xcb,
+       0x72, 0x0c, 0xb0, 0x97, 0x72, 0x4d, 0x86, 0xae, 0x98, 0x09, 0xd1, 0x90,
+       0x4f, 0xbf, 0x77, 0x5c, 0x34, 0xe2, 0x8e, 0x1e, 0x87, 0xfa, 0x8f, 0xed,
+       0x8f, 0x70, 0x07, 0xc9, 0xed, 0x2c, 0xc5, 0x29, 0x31, 0x3e, 0x08, 0x9f,
+       0xf0, 0x68, 0x52, 0x70, 0x1c, 0x3b, 0xbc, 0xeb, 0x91, 0x74, 0xac, 0x53,
+       0x6e, 0xf6, 0x64, 0x39, 0xa9, 0xfd, 0x4c, 0xe3, 0xd3, 0x49, 0xc8, 0x37,
+       0xca, 0x77, 0x3d, 0x9c, 0xce, 0x79, 0xf0, 0xae, 0x8d, 0xe9, 0x38, 0xcf,
+       0x94, 0x37, 0x3d, 0x92, 0xee, 0x62, 0x3c, 0xdc, 0xcd, 0xe7, 0x29, 0xa3,
+       0xdc, 0xf7, 0xf9, 0x7d, 0x37, 0xee, 0xdc, 0x14, 0x94, 0x77, 0x57, 0xe5,
+       0xab, 0x4c, 0x7f, 0xa9, 0xf5, 0x70, 0x21, 0xe2, 0xed, 0xac, 0xeb, 0x3e,
+       0x7b, 0xc8, 0x4e, 0xe3, 0xd2, 0x7e, 0xa1, 0xd8, 0xa1, 0x5e, 0xf7, 0x88,
+       0xee, 0x87, 0x10, 0x1f, 0x17, 0x20, 0x3f, 0xc6, 0xf9, 0xad, 0xc1, 0xca,
+       0xfe, 0x9c, 0xd6, 0x73, 0x41, 0xfe, 0xcd, 0x13, 0x7e, 0xf8, 0x1c, 0xec,
+       0xf8, 0x78, 0xc6, 0xc7, 0xa6, 0x32, 0x1a, 0x77, 0x29, 0xd7, 0xc8, 0xfc,
+       0x59, 0x20, 0xbc, 0x9b, 0xe3, 0xa9, 0x5f, 0x6c, 0x50, 0xec, 0xcd, 0x22,
+       0x78, 0xfc, 0x98, 0x46, 0x8c, 0x5f, 0xb4, 0x4e, 0x31, 0x27, 0xc0, 0x0f,
+       0x2c, 0x1f, 0x36, 0x59, 0x75, 0x60, 0xde, 0x30, 0xa6, 0x63, 0xf1, 0x86,
+       0xc9, 0x5d, 0x68, 0x5f, 0xb0, 0x5a, 0xb6, 0xcf, 0xb2, 0x78, 0x0f, 0x9c,
+       0xc0, 0x3a, 0xbf, 0x35, 0x3b, 0x9b, 0x1d, 0xec, 0x6f, 0x52, 0x4a, 0x26,
+       0x0d, 0xd0, 0x7f, 0x29, 0xd7, 0xcc, 0xf3, 0x16, 0x6e, 0x56, 0x38, 0xff,
+       0xd7, 0xbf, 0x93, 0xf6, 0x44, 0x5c, 0x63, 0xf0, 0x3e, 0x2f, 0x69, 0xf2,
+       0x17, 0x5f, 0x5b, 0x14, 0xc8, 0xe5, 0x47, 0x9a, 0x5c, 0x6e, 0x5d, 0xfd,
+       0xee, 0x91, 0x04, 0x5a, 0xd7, 0x1e, 0xeb, 0xbe, 0x0c, 0xbf, 0xf1, 0xce,
+       0xe3, 0xa7, 0x53, 0xfd, 0xd4, 0x5e, 0x10, 0x73, 0x36, 0x13, 0x7a, 0x9e,
+       0x66, 0x76, 0x3f, 0x55, 0x81, 0x7d, 0x37, 0x59, 0x9c, 0xd8, 0x47, 0x76,
+       0x56, 0xa2, 0x1a, 0x4f, 0xe3, 0xa7, 0xfc, 0x34, 0xf7, 0x31, 0xc0, 0x85,
+       0xab, 0x17, 0x3d, 0x55, 0x01, 0x7f, 0xbb, 0xcd, 0xca, 0xe7, 0x36, 0x9d,
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+       0xf8, 0xc1, 0xbf, 0xa9, 0xec, 0xaf, 0x6b, 0xa6, 0x10, 0x4e, 0xf0, 0x55,
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+       0x62, 0xc2, 0x37, 0x45, 0xf8, 0x97, 0x4a, 0xbf, 0xef, 0x4f, 0x67, 0x7f,
+       0x2d, 0xfc, 0xe9, 0x73, 0xe1, 0x17, 0x15, 0xdf, 0x07, 0xc2, 0x49, 0x79,
+       0x65, 0xc1, 0xd4, 0xc5, 0xc6, 0x91, 0xe0, 0x87, 0x6f, 0x07, 0xf0, 0xea,
+       0x82, 0x9c, 0xc5, 0xc6, 0x1b, 0xd1, 0xdf, 0xfa, 0x81, 0x3d, 0xb8, 0x7f,
+       0x84, 0x2f, 0x49, 0xb1, 0x03, 0xcf, 0x96, 0xfd, 0x23, 0x5a, 0x77, 0x0c,
+       0x73, 0x06, 0xe1, 0xa6, 0x97, 0x3e, 0x40, 0xbf, 0xd9, 0x90, 0xb3, 0xb8,
+       0x80, 0xf0, 0xd9, 0x16, 0xef, 0xb1, 0x7a, 0xe8, 0xcd, 0x8b, 0x52, 0xbf,
+       0x6c, 0xfb, 0xda, 0x4e, 0x83, 0x6f, 0x55, 0x1d, 0x32, 0x6f, 0xcf, 0xdb,
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+       0xfc, 0x64, 0xe6, 0xf7, 0xda, 0x8e, 0xdd, 0x9b, 0xa1, 0x6f, 0xbd, 0xad,
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+       0x4d, 0x42, 0xeb, 0xfa, 0xb2, 0x05, 0x7d, 0x67, 0xc5, 0x91, 0xff, 0x58,
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+       0x17, 0x6c, 0x5c, 0x87, 0xa8, 0xdc, 0x3f, 0xa1, 0x00, 0x76, 0xda, 0x1b,
+       0xd9, 0xbd, 0x00, 0xeb, 0xd7, 0x3e, 0x6f, 0x71, 0x42, 0x4f, 0x2b, 0xf7,
+       0xc7, 0xe7, 0xa1, 0x3e, 0x70, 0x30, 0x5f, 0xd6, 0xc3, 0x2b, 0x26, 0x6e,
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+       0x63, 0xe9, 0xe6, 0xf3, 0x47, 0xd5, 0x1e, 0xc5, 0x5e, 0x16, 0x7c, 0x9f,
+       0x7b, 0xc3, 0xe7, 0xec, 0x07, 0xd6, 0xda, 0xa2, 0x9a, 0x40, 0x67, 0x8d,
+       0xcf, 0x66, 0x2f, 0x1b, 0xe2, 0xfd, 0x07, 0xdf, 0x0b, 0x3b, 0xc4, 0x95,
+       0xfb, 0xe6, 0xa5, 0x72, 0x88, 0xa8, 0x89, 0x28, 0xe2, 0xfb, 0xe6, 0xa5,
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+       0x7d, 0xaf, 0x7f, 0x8b, 0x85, 0xf3, 0x8e, 0x15, 0xf9, 0xee, 0x65, 0xd0,
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+       0x2d, 0xc6, 0xad, 0x9c, 0xe4, 0xe0, 0xfa, 0x54, 0xa1, 0x45, 0xdc, 0xc7,
+       0xeb, 0x68, 0xef, 0xb4, 0x08, 0xb2, 0x3d, 0x15, 0xae, 0x55, 0xbc, 0x06,
+       0xc2, 0x17, 0x09, 0xa7, 0x19, 0xf6, 0xb3, 0x90, 0xd8, 0xc6, 0xfa, 0x62,
+       0x8a, 0xd8, 0x80, 0xf7, 0x54, 0x0b, 0x85, 0x7c, 0xdf, 0xa0, 0xeb, 0xcd,
+       0xca, 0xad, 0x0a, 0xe7, 0x05, 0x5c, 0x28, 0x88, 0xc3, 0xbd, 0xa4, 0xe4,
+       0xef, 0xc2, 0xce, 0x7f, 0xbb, 0x84, 0xf7, 0x0b, 0x4b, 0x2c, 0x32, 0x7f,
+       0x4d, 0x34, 0xc8, 0xfb, 0xec, 0xc4, 0x4d, 0xf2, 0x7d, 0xcb, 0x4f, 0x84,
+       0xdb, 0x8c, 0x78, 0xbb, 0x8c, 0xe2, 0x22, 0x20, 0xc5, 0xc9, 0xdf, 0xf5,
+       0x50, 0xbb, 0x3b, 0x7c, 0x74, 0x92, 0xcc, 0xcf, 0x1d, 0xf1, 0x58, 0x7f,
+       0xd1, 0x71, 0x13, 0xbf, 0xf7, 0x2d, 0x8c, 0xff, 0x61, 0xba, 0x9b, 0xe3,
+       0x75, 0x01, 0xbf, 0x63, 0x50, 0xfc, 0x77, 0xab, 0x97, 0xaf, 0xbb, 0xb6,
+       0xfd, 0x84, 0xbe, 0x63, 0x38, 0x6a, 0x92, 0xfe, 0x85, 0xf8, 0xc8, 0xe7,
+       0xa2, 0x2e, 0xe8, 0x25, 0xd7, 0x67, 0xdc, 0x0c, 0x8f, 0xd7, 0x97, 0x33,
+       0x9c, 0x34, 0x43, 0xfa, 0xc7, 0x2b, 0xef, 0x12, 0x49, 0x46, 0x76, 0xd0,
+       0x1f, 0xde, 0xf7, 0x01, 0xce, 0x8b, 0x89, 0xf1, 0x91, 0x4e, 0xf8, 0x3b,
+       0xdd, 0xee, 0xaf, 0x7a, 0x9f, 0x18, 0x26, 0xa1, 0xfe, 0x3e, 0x71, 0x0c,
+       0x41, 0x11, 0xf4, 0x3e, 0x71, 0xb3, 0xcb, 0xc1, 0xfe, 0x2e, 0xd1, 0x70,
+       0x62, 0xaa, 0x03, 0xfc, 0xf8, 0x4b, 0x84, 0x13, 0xfc, 0xd0, 0xdf, 0x29,
+       0xae, 0x9e, 0x51, 0xb2, 0x13, 0x72, 0x72, 0x45, 0x09, 0x0f, 0xbe, 0x8b,
+       0x7b, 0x94, 0x2d, 0xc4, 0xd7, 0x22, 0x6c, 0x44, 0x41, 0x9d, 0xdb, 0xe7,
+       0x52, 0x51, 0xb7, 0x3e, 0xa4, 0xd8, 0xf9, 0x5d, 0xf4, 0x55, 0x7e, 0x72,
+       0xeb, 0x43, 0x78, 0xc7, 0x53, 0x97, 0xaa, 0xd8, 0x15, 0x07, 0xea, 0xe1,
+       0x5b, 0x0a, 0xe3, 0x88, 0xee, 0xa2, 0x94, 0x64, 0xa6, 0xbb, 0xae, 0x5d,
+       0xd6, 0x4b, 0x99, 0x43, 0x71, 0xa8, 0xa7, 0x6b, 0xf6, 0xe0, 0x72, 0xb7,
+       0x15, 0x8e, 0x18, 0x68, 0x9f, 0xad, 0xd9, 0x45, 0x2f, 0x8d, 0x97, 0x7a,
+       0x72, 0x93, 0x17, 0xfa, 0xf6, 0x1d, 0xea, 0xa8, 0xcf, 0x61, 0xbc, 0x47,
+       0xd8, 0x9c, 0xcd, 0xda, 0x79, 0x0d, 0x72, 0x9f, 0x7d, 0xdd, 0x18, 0xae,
+       0xa7, 0xea, 0x7a, 0xd3, 0xdf, 0x12, 0xdf, 0x04, 0xbd, 0x79, 0xb3, 0x50,
+       0xc6, 0x99, 0xd2, 0xd2, 0x77, 0x4d, 0xc8, 0x03, 0xba, 0x72, 0xdd, 0x47,
+       0xb0, 0xff, 0x05, 0x65, 0x9f, 0x3f, 0x14, 0xc7, 0xfb, 0x1b, 0xba, 0x8e,
+       0x45, 0x7e, 0x94, 0xef, 0x25, 0x43, 0xeb, 0x58, 0xba, 0x5f, 0xde, 0xa5,
+       0xd5, 0xc1, 0xe1, 0x3f, 0x8d, 0x5a, 0x9d, 0xd5, 0xa8, 0xd5, 0x59, 0x8d,
+       0x5a, 0x9d, 0xd5, 0xa8, 0xd5, 0x59, 0x8d, 0x5a, 0x9d, 0xd5, 0xa8, 0xd5,
+       0x59, 0x8d, 0x5a, 0x9d, 0xd5, 0xa8, 0xd5, 0x59, 0x8d, 0x5a, 0x9d, 0xd5,
+       0xc8, 0xf5, 0xbb, 0xe5, 0x0c, 0xdf, 0xa9, 0x5f, 0xc5, 0xb0, 0xbb, 0xde,
+       0xc3, 0xfd, 0x41, 0xfe, 0xff, 0xfd, 0x6b, 0xf8, 0xff, 0xd0, 0x3a, 0xe8,
+       0xc7, 0x18, 0x17, 0x5a, 0x07, 0x15, 0x56, 0x47, 0x34, 0xc7, 0x51, 0xb2,
+       0x6f, 0x59, 0x7f, 0x0e, 0xa9, 0x7b, 0x16, 0x0f, 0x5f, 0xbc, 0x81, 0xf8,
+       0x97, 0xdf, 0x60, 0x76, 0xa2, 0x49, 0xaf, 0x83, 0xe2, 0xfd, 0xf2, 0xbd,
+       0x11, 0xec, 0x0f, 0x2e, 0x14, 0x0e, 0x59, 0xff, 0xd4, 0xf9, 0x16, 0xc1,
+       0xf5, 0xd2, 0x7e, 0x61, 0x9b, 0x02, 0xfe, 0xe7, 0x65, 0x8c, 0x33, 0x1a,
+       0xa8, 0xff, 0x2f, 0x9a, 0x1c, 0xf4, 0xfa, 0x23, 0xec, 0x03, 0xfb, 0x83,
+       0x7d, 0x00, 0xc2, 0x3e, 0x8c, 0x69, 0x03, 0xf6, 0xf1, 0x8c, 0x99, 0x4c,
+       0x38, 0x5b, 0xc6, 0x7b, 0x0f, 0xc7, 0x7b, 0x1b, 0xcb, 0x75, 0xfd, 0x1a,
+       0xf2, 0x1f, 0x84, 0x2f, 0x11, 0xf6, 0x41, 0xfe, 0xe3, 0x42, 0x88, 0xff,
+       0xa0, 0x83, 0xc7, 0x5d, 0xa0, 0x63, 0x69, 0xa7, 0x7c, 0xd7, 0xa4, 0xbf,
+       0xdf, 0xcc, 0x23, 0xf0, 0xd5, 0x94, 0x21, 0xfc, 0x89, 0x4f, 0xfa, 0x93,
+       0x31, 0x61, 0xbe, 0xbd, 0xf8, 0xce, 0x98, 0xda, 0x30, 0x7e, 0x1f, 0x7c,
+       0x54, 0x7b, 0x8f, 0x75, 0x74, 0xa3, 0x7c, 0x17, 0x57, 0x26, 0x4a, 0xf8,
+       0xbb, 0x43, 0xf8, 0x95, 0x28, 0xc8, 0x63, 0xc9, 0xf0, 0xbe, 0x0f, 0x9e,
+       0xa6, 0xf1, 0x4b, 0x1e, 0x89, 0xe0, 0xbc, 0x65, 0xfd, 0xc8, 0xa5, 0xd3,
+       0xfe, 0x37, 0x7e, 0xe5, 0xf3, 0x42, 0xc9, 0x8f, 0xdf, 0xd6, 0xfb, 0x2b,
+       0x3f, 0x21, 0x5a, 0x0a, 0xc2, 0xa4, 0xfe, 0x15, 0x98, 0x45, 0x06, 0xee,
+       0x6b, 0x84, 0x21, 0x8c, 0xed, 0xa0, 0x50, 0xdd, 0xac, 0xe0, 0x7e, 0x74,
+       0xe5, 0x3d, 0x62, 0x32, 0xe4, 0x5c, 0x60, 0x29, 0xd9, 0x0e, 0x3a, 0xe3,
+       0xb5, 0xfb, 0x6d, 0x11, 0xab, 0xd5, 0x5b, 0x8d, 0xdd, 0x15, 0xbb, 0x09,
+       0x3f, 0x11, 0x97, 0xe8, 0xc4, 0xbd, 0xd6, 0xe8, 0x84, 0x83, 0x02, 0xef,
+       0x9f, 0x0a, 0xeb, 0x8a, 0x33, 0xe1, 0x17, 0xfd, 0x63, 0xdc, 0x13, 0x8a,
+       0x72, 0xf0, 0x7e, 0x79, 0x8b, 0x82, 0xf9, 0xe1, 0x99, 0x72, 0xff, 0xb7,
+       0x17, 0x87, 0x37, 0x41, 0xaf, 0x02, 0x87, 0xc6, 0xe7, 0x40, 0xde, 0x73,
+       0x2d, 0x8e, 0x36, 0xd4, 0x01, 0x9c, 0x45, 0x09, 0x4b, 0x70, 0xce, 0x9f,
+       0x1b, 0xed, 0xc8, 0x41, 0x1d, 0xc0, 0xd9, 0x35, 0x4a, 0xe2, 0xf1, 0x8e,
+       0x36, 0xc5, 0x89, 0x54, 0x36, 0x61, 0x49, 0x01, 0xbf, 0x3f, 0xb3, 0x6e,
+       0xf9, 0xc4, 0x8a, 0x77, 0x6b, 0x8a, 0x88, 0xa6, 0x7d, 0x59, 0x86, 0xb9,
+       0x73, 0xf0, 0x9d, 0x9a, 0xe2, 0xcf, 0xe4, 0xb9, 0x59, 0xf4, 0x71, 0x1c,
+       0xbb, 0xb1, 0x48, 0x9e, 0xbf, 0x46, 0xbc, 0x2e, 0xfc, 0xb8, 0xb7, 0xea,
+       0x9b, 0x19, 0xc9, 0xf7, 0x67, 0x22, 0xd3, 0x91, 0x83, 0x7e, 0xca, 0x2b,
+       0xbf, 0x5f, 0x44, 0xfa, 0x77, 0xe4, 0x07, 0xae, 0x9b, 0x00, 0x13, 0x35,
+       0x3a, 0xe3, 0x71, 0x8b, 0xa8, 0x42, 0xaa, 0xdd, 0x36, 0xc0, 0xe3, 0xda,
+       0x7d, 0x5e, 0x97, 0xc1, 0x5d, 0x0a, 0x58, 0x14, 0xe5, 0x31, 0x72, 0xbb,
+       0xc1, 0x9b, 0x0d, 0xf8, 0x96, 0xc1, 0xf7, 0x53, 0xb4, 0x93, 0x3e, 0x17,
+       0x61, 0x9d, 0xa2, 0xc7, 0x26, 0x4f, 0xcc, 0x20, 0x3c, 0xd1, 0xe2, 0x63,
+       0x3f, 0xd9, 0xe1, 0x72, 0xdd, 0x02, 0xfa, 0x5e, 0x9c, 0xe1, 0x2a, 0x06,
+       0x0c, 0xad, 0x9f, 0x43, 0xb6, 0x38, 0xe7, 0x13, 0x3d, 0xb7, 0xa2, 0x3f,
+       0xf4, 0x1d, 0x96, 0x2e, 0xcf, 0x25, 0x45, 0x52, 0xef, 0xcb, 0x8a, 0xa4,
+       0xff, 0x98, 0xbe, 0x56, 0xde, 0xc7, 0x86, 0xca, 0xbd, 0xac, 0xc8, 0xa0,
+       0xf9, 0xb7, 0xbf, 0x4f, 0x37, 0xd1, 0x5b, 0x8a, 0xef, 0xe9, 0xf4, 0x8b,
+       0x2d, 0x8b, 0xb2, 0x41, 0x0f, 0xd1, 0x7b, 0x0f, 0xf6, 0x41, 0xf4, 0x2e,
+       0x00, 0x14, 0x11, 0x31, 0x5c, 0xef, 0xb8, 0xb6, 0x9e, 0x79, 0xf8, 0x7b,
+       0x65, 0x45, 0x52, 0xbf, 0xc8, 0x9f, 0x55, 0x7d, 0x22, 0xfd, 0x19, 0xc3,
+       0x74, 0xa3, 0x77, 0x18, 0xf2, 0xc7, 0x51, 0x0f, 0x78, 0x87, 0x81, 0xde,
+       0x51, 0x8d, 0x7d, 0x36, 0xfc, 0x3b, 0x8c, 0x67, 0x3d, 0x7d, 0x36, 0xc4,
+       0xf7, 0x67, 0x57, 0xf7, 0xd9, 0xd0, 0xfe, 0xac, 0x4b, 0xbe, 0x93, 0x0e,
+       0x5d, 0xbf, 0xb1, 0x48, 0xbe, 0x9f, 0x48, 0x9f, 0xde, 0xc7, 0xf3, 0xc7,
+       0xd2, 0xb7, 0xba, 0x39, 0x4f, 0xef, 0x1b, 0x86, 0x3c, 0x2a, 0xbd, 0xfc,
+       0x93, 0xf5, 0xf2, 0xde, 0x25, 0x83, 0xe3, 0xcb, 0x58, 0x2d, 0xbe, 0x8c,
+       0x7d, 0x20, 0xa5, 0xbd, 0x87, 0xf4, 0x6d, 0xec, 0x93, 0xd1, 0x7c, 0xbf,
+       0x2d, 0x0a, 0x62, 0xb9, 0xbf, 0xd2, 0x2a, 0xed, 0xb4, 0xf2, 0x81, 0xb2,
+       0x83, 0x6d, 0x04, 0xc7, 0x6f, 0x23, 0x7a, 0x83, 0xf2, 0xaf, 0x09, 0x5e,
+       0xa2, 0x7b, 0x50, 0x5e, 0x64, 0xec, 0x97, 0xef, 0x2d, 0x09, 0x07, 0x9f,
+       0xf6, 0x98, 0x18, 0x87, 0xce, 0x22, 0xbf, 0xaa, 0x11, 0xf2, 0xbd, 0xe5,
+       0x28, 0xcd, 0x6f, 0x20, 0x6f, 0x2b, 0x25, 0xbf, 0x50, 0x53, 0x7e, 0xe4,
+       0x12, 0xbf, 0x03, 0xc0, 0x7c, 0xac, 0x8f, 0x3b, 0x5b, 0xe8, 0x5f, 0xbb,
+       0x49, 0xe2, 0x14, 0xae, 0x71, 0x1e, 0x5d, 0x36, 0x6f, 0x4d, 0x17, 0x9f,
+       0x0f, 0xb7, 0x5d, 0x69, 0xd7, 0xce, 0x9b, 0xad, 0xeb, 0x71, 0x7e, 0xa6,
+       0xfc, 0x6d, 0x50, 0x7b, 0x65, 0xd9, 0xe1, 0x2e, 0xc4, 0x9b, 0xaa, 0x3d,
+       0x83, 0xdb, 0x6b, 0x96, 0x7f, 0xce, 0xe7, 0x58, 0xca, 0xdf, 0x06, 0xb5,
+       0xdf, 0xf3, 0xd3, 0x0f, 0xf9, 0x9d, 0x4d, 0x5d, 0xfb, 0xe0, 0x76, 0x92,
+       0xef, 0x53, 0x90, 0xbf, 0x2e, 0xdf, 0xa3, 0x26, 0xdf, 0x04, 0x9c, 0xf7,
+       0x8e, 0xd6, 0x84, 0x39, 0xe5, 0xbf, 0x1f, 0xf0, 0xad, 0x80, 0xbd, 0x37,
+       0x55, 0x47, 0xf0, 0xfb, 0xd9, 0x9d, 0xbf, 0xc9, 0x63, 0xbd, 0xd1, 0xe5,
+       0x4d, 0xf3, 0x9b, 0xbe, 0x9b, 0x7e, 0xac, 0xe5, 0xf1, 0x9e, 0x3c, 0x91,
+       0x01, 0x7b, 0xf8, 0x36, 0xd8, 0x0b, 0xff, 0x94, 0x36, 0xc8, 0x3f, 0x79,
+       0xb8, 0xce, 0x37, 0x2b, 0x92, 0xfd, 0x4e, 0x9d, 0x76, 0xbe, 0xaa, 0x2d,
+       0xb3, 0x73, 0x9c, 0x4f, 0xac, 0xb5, 0xb2, 0xff, 0x2a, 0x54, 0xc3, 0x9c,
+       0xc0, 0x6b, 0x8d, 0xd2, 0xcf, 0x88, 0x62, 0x55, 0xf3, 0x53, 0x3e, 0xb6,
+       0xff, 0x13, 0xb7, 0x0d, 0xe3, 0x7a, 0x1e, 0x6f, 0x00, 0x78, 0xcc, 0x24,
+       0x7e, 0x77, 0x1c, 0xb7, 0x56, 0xe2, 0x7d, 0x23, 0x2c, 0xec, 0x1f, 0x0a,
+       0x0d, 0x25, 0xd5, 0xbb, 0x09, 0x1e, 0x31, 0x2c, 0x67, 0x3f, 0x90, 0x80,
+       0x17, 0x97, 0x24, 0xf7, 0x67, 0xe0, 0x1f, 0x54, 0xd8, 0xaf, 0xbc, 0x7f,
+       0xa8, 0x33, 0xfb, 0x14, 0x79, 0xbf, 0xef, 0xc8, 0xc1, 0x79, 0x57, 0xbf,
+       0x6f, 0x6a, 0xd8, 0xe8, 0x6d, 0x3d, 0x80, 0xf3, 0xb2, 0xe2, 0x7d, 0x72,
+       0x29, 0xea, 0x8a, 0x77, 0x44, 0xf0, 0xfd, 0x41, 0x00, 0xf5, 0x46, 0xda,
+       0x4f, 0xc3, 0x30, 0xe9, 0x47, 0x1b, 0xe6, 0xa7, 0x73, 0x1c, 0x08, 0x88,
+       0x92, 0xd2, 0x15, 0xc8, 0x43, 0xe6, 0x85, 0x71, 0xfd, 0xb1, 0x61, 0x98,
+       0xe3, 0x51, 0xdc, 0x27, 0x36, 0x54, 0x4c, 0xe4, 0x3c, 0xfa, 0xe0, 0xdf,
+       0x64, 0xdc, 0xed, 0x9b, 0x63, 0x75, 0x22, 0x8f, 0x6a, 0x98, 0xec, 0x58,
+       0x83, 0xf7, 0x2a, 0x0d, 0x0f, 0x38, 0xb8, 0xff, 0x55, 0x45, 0xae, 0xe7,
+       0x79, 0x54, 0xf2, 0xa7, 0x61, 0x8e, 0xdc, 0x7f, 0x43, 0x45, 0x0c, 0x9f,
+       0x7b, 0x74, 0x39, 0x34, 0x34, 0xba, 0x46, 0xe2, 0x7e, 0x6a, 0xc6, 0x18,
+       0xf7, 0x7f, 0x42, 0x6e, 0xa3, 0xb4, 0xfb, 0xb9, 0x86, 0x64, 0x6a, 0x27,
+       0xf8, 0x84, 0x52, 0x32, 0xff, 0x27, 0x58, 0x67, 0x92, 0xa4, 0x77, 0xd2,
+       0x0c, 0x07, 0xcb, 0xed, 0xe8, 0xfc, 0x89, 0x8f, 0xee, 0x72, 0x70, 0x38,
+       0xf1, 0xe3, 0x9e, 0xa8, 0x6e, 0x56, 0xe4, 0xa0, 0x73, 0xf1, 0xff, 0x00,
+       0x87, 0x51, 0xd9, 0xf6, 0x10, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+void bnx2x_init_e1h_firmware(struct bnx2x *bp)
+{
+       INIT_OPS(bp)                  = (struct raw_op *)init_ops_e1h;
+       INIT_DATA(bp)                 = (u32 *)init_data_e1h;
+       INIT_OPS_OFFSETS(bp)          = (u16 *)init_ops_offsets_e1h;
+       INIT_TSEM_INT_TABLE_DATA(bp)  = tsem_int_table_data_e1h;
+       INIT_TSEM_PRAM_DATA(bp)       = tsem_pram_data_e1h;
+       INIT_USEM_INT_TABLE_DATA(bp)  = usem_int_table_data_e1h;
+       INIT_USEM_PRAM_DATA(bp)       = usem_pram_data_e1h;
+       INIT_XSEM_INT_TABLE_DATA(bp)  = xsem_int_table_data_e1h;
+       INIT_XSEM_PRAM_DATA(bp)       = xsem_pram_data_e1h;
+       INIT_CSEM_INT_TABLE_DATA(bp)  = csem_int_table_data_e1h;
+       INIT_CSEM_PRAM_DATA(bp)       = csem_pram_data_e1h;
+}
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_link.c linux-2.6.22-800/drivers/net/bnx2x/bnx2x_link.c
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_link.c        1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_link.c     2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,7881 @@
+/* Copyright 2008-2009 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
+ *
+ * Written by Yaniv Rosner
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#ifdef __LINUX_MUTEX_H  /* BNX2X_UPSTREAM */
+#include <linux/mutex.h>
+#endif
+#include <linux/version.h>
+
+#include "bnx2x.h"
+
+
+#define E2_PHASE0 1
+#define CHIP_IS_E2_NOT_PHASE0(_chip_id) (CHIP_IS_E2(bp) && \
+                                         !(E2_PHASE0))
+/********************************************************/
+#define ETH_HLEN               14
+#define ETH_OVREHEAD           (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
+#define ETH_MIN_PACKET_SIZE    60
+#define ETH_MAX_PACKET_SIZE    1500
+#define ETH_MAX_JUMBO_PACKET_SIZE      9600
+#define MDIO_ACCESS_TIMEOUT    1000
+#define BMAC_CONTROL_RX_ENABLE 2
+
+struct bnx2x_image_header {
+       u32 magic;
+               #define FILE_MAGIC                      0x669955aa
+       u32 version;
+               #define FORMAT_VERSION_2                0x2
+       u32 type;
+               #define IMAGE_HDR_TYPE_BCM8073  0x33373038
+               #define IMAGE_HDR_TYPE_BCM8726  0x36323738
+               #define IMAGE_HDR_TYPE_BCM8727  0x37323738
+               #define IMAGE_HDR_TYPE_BCM8481  0x31383438
+               #define IMAGE_HDR_TYPE_SFX7101  0x68706673
+       u32 image_info;
+       u32 byte_cnt;
+};
+/***********************************************************/
+/*                      Shortcut definitions              */
+/***********************************************************/
+
+#define NIG_LATCH_BC_ENABLE_MI_INT 0
+
+#define NIG_STATUS_EMAC0_MI_INT \
+               NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
+#define NIG_STATUS_XGXS0_LINK10G \
+               NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
+#define NIG_STATUS_XGXS0_LINK_STATUS \
+               NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
+#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
+               NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
+#define NIG_STATUS_SERDES0_LINK_STATUS \
+               NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
+#define NIG_MASK_MI_INT \
+               NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
+#define NIG_MASK_XGXS0_LINK10G \
+               NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
+#define NIG_MASK_XGXS0_LINK_STATUS \
+               NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
+#define NIG_MASK_SERDES0_LINK_STATUS \
+               NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
+
+#define MDIO_AN_CL73_OR_37_COMPLETE \
+               (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
+                MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
+
+#define XGXS_RESET_BITS \
+       (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
+
+#define SERDES_RESET_BITS \
+       (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
+        MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
+
+#define AUTONEG_CL37           SHARED_HW_CFG_AN_ENABLE_CL37
+#define AUTONEG_CL73           SHARED_HW_CFG_AN_ENABLE_CL73
+#define AUTONEG_BAM            SHARED_HW_CFG_AN_ENABLE_BAM
+#define AUTONEG_PARALLEL       \
+                               SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
+#define AUTONEG_SGMII_FIBER_AUTODET \
+                               SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
+#define AUTONEG_REMOTE_PHY     SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
+
+#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
+#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
+#define GP_STATUS_SPEED_MASK \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
+#define GP_STATUS_10M       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
+#define GP_STATUS_100M      MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
+#define GP_STATUS_1G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
+#define GP_STATUS_2_5G      MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
+#define GP_STATUS_5G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
+#define GP_STATUS_6G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
+#define GP_STATUS_10G_HIG \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
+#define GP_STATUS_10G_CX4 \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
+#define GP_STATUS_12G_HIG \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
+#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
+#define GP_STATUS_13G       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
+#define GP_STATUS_15G       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
+#define GP_STATUS_16G       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
+#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
+#define GP_STATUS_10G_KX4 \
+                       MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
+
+#define LINK_10THD             LINK_STATUS_SPEED_AND_DUPLEX_10THD
+#define LINK_10TFD             LINK_STATUS_SPEED_AND_DUPLEX_10TFD
+#define LINK_100TXHD           LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
+#define LINK_100T4             LINK_STATUS_SPEED_AND_DUPLEX_100T4
+#define LINK_100TXFD           LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
+#define LINK_1000THD           LINK_STATUS_SPEED_AND_DUPLEX_1000THD
+#define LINK_1000TFD           LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
+#define LINK_1000XFD           LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
+#define LINK_2500THD           LINK_STATUS_SPEED_AND_DUPLEX_2500THD
+#define LINK_2500TFD           LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
+#define LINK_2500XFD           LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
+#define LINK_10GTFD            LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
+#define LINK_10GXFD            LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
+#define LINK_12GTFD            LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
+#define LINK_12GXFD            LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
+#define LINK_12_5GTFD          LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
+#define LINK_12_5GXFD          LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
+#define LINK_13GTFD            LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
+#define LINK_13GXFD            LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
+#define LINK_15GTFD            LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
+#define LINK_15GXFD            LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
+#define LINK_16GTFD            LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
+#define LINK_16GXFD            LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
+
+#define PHY_XGXS_FLAG                  0x1
+#define PHY_SGMII_FLAG                 0x2
+#define PHY_SERDES_FLAG                0x4
+
+/* */
+#define SFP_EEPROM_CON_TYPE_ADDR               0x2
+       #define SFP_EEPROM_CON_TYPE_VAL_LC              0x7
+       #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
+
+
+#define SFP_EEPROM_COMP_CODE_ADDR              0x3
+       #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
+       #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
+       #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
+
+#define SFP_EEPROM_FC_TX_TECH_ADDR             0x8
+       #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
+       #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE      0x8
+
+#define SFP_EEPROM_OPTIONS_ADDR                0x40
+       #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
+#define SFP_EEPROM_OPTIONS_SIZE                2
+
+#define EDC_MODE_LINEAR                                0x0022
+#define EDC_MODE_LIMITING                              0x0044
+#define EDC_MODE_PASSIVE_DAC                   0x0055
+
+
+/**********************************************************/
+/*                  8073 Download definitions            */
+/**********************************************************/
+/* spi Parameters.*/
+#define SPI_CTRL_1_L   0xC000
+#define SPI_CTRL_1_H   0xC002
+#define SPI_CTRL_2_L   0xC400
+#define SPI_CTRL_2_H   0xC402
+#define SPI_TXFIFO     0xD000
+#define SPI_RXFIFO     0xD400
+
+/* Input Command Messages.*/
+#define WR_CPU_CTRL_REGS    0x11    /* Write CPU/SPI Control Regs, followed
+ by Count And CPU/SPI Controller Reg add/data pairs.*/
+#define RD_CPU_CTRL_REGS    0xEE    /* Read CPU/SPI Control Regs, followed
+by Count and CPU/SPI Controller Register Add.*/
+#define WR_CPU_CTRL_FIFO    0x66    /* Write CPU/SPI Control Regs
+Continously, followed by Count and CPU/SPI Controller Reg addr and data's.*/
+/* Output Command Messages.*/
+#define DONE     0x4321
+
+/* SPI Controller Commands (known As messages).*/
+#define MSGTYPE_HWR    0x40
+#define MSGTYPE_HRD    0x80
+#define WRSR_OPCODE            0x01
+#define WR_OPCODE      0x02
+#define RD_OPCODE      0x03
+#define WRDI_OPCODE    0x04
+#define RDSR_OPCODE    0x05
+#define WREN_OPCODE    0x06
+#define WR_BLOCK_SIZE  0x40 /* Maximum 64 Bytes Writes.*/
+
+#define BUF_SIZE_BCM   0x4000 /* Code Size is 16k bytes.*/
+#define UPGRADE_TIMEOUT_BCM 1000
+/**********************************************************/
+/*                    INTERFACE                          */
+/**********************************************************/
+#define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
+       bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
+               DEFAULT_PHY_DEV_ADDR, \
+               (_bank + (_addr & 0xf)), \
+               _val)
+
+#define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
+       bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
+               DEFAULT_PHY_DEV_ADDR, \
+               (_bank + (_addr & 0xf)), \
+               _val)
+
+static void bnx2x_set_serdes_access(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+       /* Set Clause 22 */
+       REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
+       REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
+       udelay(500);
+       REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
+       udelay(500);
+        /* Set Clause 45 */
+       REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
+}
+static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
+{
+       struct bnx2x *bp = params->bp;
+
+       if (phy_flags & PHY_XGXS_FLAG) {
+               REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
+                          params->port*0x18, 0);
+               REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
+                          DEFAULT_PHY_DEV_ADDR);
+       } else {
+               bnx2x_set_serdes_access(params);
+
+               REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
+                          params->port*0x10,
+                          DEFAULT_PHY_DEV_ADDR);
+       }
+}
+
+static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
+{
+       u32 val = REG_RD(bp, reg);
+
+       val |= bits;
+       REG_WR(bp, reg, val);
+       return val;
+}
+
+static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
+{
+       u32 val = REG_RD(bp, reg);
+
+       val &= ~bits;
+       REG_WR(bp, reg, val);
+       return val;
+}
+
+static void bnx2x_emac_init(struct link_params *params,
+                          struct link_vars *vars)
+{
+       /* reset and unreset the emac core */
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+       u32 val;
+       u16 timeout;
+
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+                  (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+       udelay(5);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+                  (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+
+       /* init emac - use read-modify-write */
+       /* self clear reset */
+       val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
+       EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
+
+       timeout = 200;
+       do {
+               val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
+               DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
+               if (!timeout) {
+                       DP(NETIF_MSG_LINK, "EMAC timeout!\n");
+                       return;
+               }
+               timeout--;
+       } while (val & EMAC_MODE_RESET);
+
+       /* Set mac address */
+       val = ((params->mac_addr[0] << 8) |
+               params->mac_addr[1]);
+       EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
+
+       val = ((params->mac_addr[2] << 24) |
+              (params->mac_addr[3] << 16) |
+              (params->mac_addr[4] << 8) |
+               params->mac_addr[5]);
+       EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
+}
+
+static u8 bnx2x_emac_enable(struct link_params *params,
+                         struct link_vars *vars, u8 lb)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+       u32 val;
+
+       DP(NETIF_MSG_LINK, "enabling EMAC\n");
+
+       /* enable emac and not bmac */
+       REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
+
+       /* for paladium */
+       if (CHIP_REV_IS_EMUL(bp)) {
+               /* Use lane 1 (of lanes 0-3) */
+               REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
+               REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
+                           port*4, 1);
+       }
+       /* for fpga */
+       else
+       if (CHIP_REV_IS_FPGA(bp)) {
+               /* Use lane 1 (of lanes 0-3) */
+               DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
+
+               REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
+               REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
+                           0);
+       } else
+       /* ASIC */
+       if (vars->phy_flags & PHY_XGXS_FLAG) {
+               u32 ser_lane = ((params->lane_config &
+                           PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+                           PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+               DP(NETIF_MSG_LINK, "XGXS\n");
+               /* select the master lanes (out of 0-3) */
+               REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
+                          port*4, ser_lane);
+               /* select XGXS */
+               REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
+                          port*4, 1);
+
+       } else { /* SerDes */
+               DP(NETIF_MSG_LINK, "SerDes\n");
+               /* select SerDes */
+               REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
+                          port*4, 0);
+       }
+
+       bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
+                   EMAC_RX_MODE_RESET);
+       bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
+                   EMAC_TX_MODE_RESET);
+
+       if (CHIP_REV_IS_SLOW(bp)) {
+               /* config GMII mode */
+               val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
+               EMAC_WR(bp, EMAC_REG_EMAC_MODE,
+                           (val | EMAC_MODE_PORT_GMII));
+       } else { /* ASIC */
+               /* pause enable/disable */
+               bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
+                              EMAC_RX_MODE_FLOW_EN);
+               if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
+                       bnx2x_bits_en(bp, emac_base +
+                                   EMAC_REG_EMAC_RX_MODE,
+                                   EMAC_RX_MODE_FLOW_EN);
+
+               bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
+                            (EMAC_TX_MODE_EXT_PAUSE_EN |
+                             EMAC_TX_MODE_FLOW_EN));
+               if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+                       bnx2x_bits_en(bp, emac_base +
+                                   EMAC_REG_EMAC_TX_MODE,
+                                  (EMAC_TX_MODE_EXT_PAUSE_EN |
+                                   EMAC_TX_MODE_FLOW_EN));
+       }
+
+       /* KEEP_VLAN_TAG, promiscuous */
+       val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
+       val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
+       EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
+
+       /* Set Loopback */
+       val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
+       if (lb)
+               val |= 0x810;
+       else
+               val &= ~0x810;
+       EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
+
+       /* enable emac */
+       REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
+
+       /* enable emac for jumbo packets */
+       EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
+               (EMAC_RX_MTU_SIZE_JUMBO_ENA |
+                (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
+
+       /* strip CRC */
+       REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
+
+       /* disable the NIG in/out to the bmac */
+       REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
+       REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
+       REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
+
+       /* enable the NIG in/out to the emac */
+       REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
+       val = 0;
+       if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+               val = 1;
+
+       REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
+       REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
+
+       if (CHIP_REV_IS_EMUL(bp)) {
+               /* take the BigMac out of reset */
+               REG_WR(bp,
+                          GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+                          (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+               /* enable access for bmac registers */
+               REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
+       }
+
+       vars->mac_type = MAC_TYPE_EMAC;
+       return 0;
+}
+
+
+static u8 bnx2x_bmac1_enable(struct link_params *params, struct link_vars *vars,
+                         u8 is_lb)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
+                              NIG_REG_INGRESS_BMAC0_MEM;
+       u32 wb_data[2];
+       u32 val;
+
+       DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
+
+       /* XGXS control */
+       wb_data[0] = 0x3c;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr +
+                     BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
+                     wb_data, 2);
+
+       /* tx MAC SA */
+       wb_data[0] = ((params->mac_addr[2] << 24) |
+                      (params->mac_addr[3] << 16) |
+                      (params->mac_addr[4] << 8) |
+                       params->mac_addr[5]);
+       wb_data[1] = ((params->mac_addr[0] << 8) |
+                       params->mac_addr[1]);
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
+                   wb_data, 2);
+
+       /* tx control */
+       val = 0xc0;
+       if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+               val |= 0x800000;
+       wb_data[0] = val;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
+                       wb_data, 2);
+
+       /* mac control */
+       val = 0x3;
+       if (is_lb) {
+               val |= 0x4;
+               DP(NETIF_MSG_LINK, "enable bmac loopback\n");
+       }
+       wb_data[0] = val;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
+                   wb_data, 2);
+
+       /* set rx mtu */
+       wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
+                       wb_data, 2);
+
+       /* rx control set to don't strip crc */
+       val = 0x14;
+       if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
+               val |= 0x20;
+       wb_data[0] = val;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
+                       wb_data, 2);
+
+       /* set tx mtu */
+       wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
+                       wb_data, 2);
+
+       /* set cnt max size */
+       wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
+                   wb_data, 2);
+
+       /* configure safc */
+       wb_data[0] = 0x1000200;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
+                   wb_data, 2);
+       /* fix for emulation */
+       if (CHIP_REV_IS_EMUL(bp)) {
+               wb_data[0] = 0xf000;
+               wb_data[1] = 0;
+               REG_WR_DMAE(bp,
+                           bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
+                           wb_data, 2);
+       }
+
+
+       return 0;
+}
+
+static u8 bnx2x_bmac2_enable(struct link_params *params, struct link_vars *vars,
+                         u8 is_lb)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
+                              NIG_REG_INGRESS_BMAC0_MEM;
+       u32 wb_data[2];
+       u32 val;
+
+       DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
+
+       wb_data[0] = 0;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
+                   wb_data, 2);
+       udelay(30);
+
+       /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
+       wb_data[0] = 0x3c;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr +
+                     BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
+                     wb_data, 2);
+
+       udelay(30);
+
+       /* tx MAC SA */
+       wb_data[0] = ((params->mac_addr[2] << 24) |
+                      (params->mac_addr[3] << 16) |
+                      (params->mac_addr[4] << 8) |
+                       params->mac_addr[5]);
+       wb_data[1] = ((params->mac_addr[0] << 8) |
+                       params->mac_addr[1]);
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
+                     wb_data, 2);
+
+       udelay(30);
+
+       /* Tx control */
+       val = 0xc0;
+       if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+               val |= 0x800000;
+       wb_data[0] = val;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL,
+                       wb_data, 2);
+
+       /* Configure SAFC */
+       wb_data[0] = 0x1000200;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
+                     wb_data, 2);
+       udelay(30);
+
+       /* set rx mtu */
+       wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,
+                     wb_data, 2);
+       udelay(30);
+
+       /* set tx mtu */
+       wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,
+                     wb_data, 2);
+       udelay(30);
+
+       /* Set rx control: Strip CRC and enable BigMAC to relay
+       control packets to the system as well*/
+       val = 0x54;
+       if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
+               val |= 0x20;
+       wb_data[0] = val;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,
+                     wb_data, 2);
+       udelay(30);
+
+       if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
+               wb_data[0] = 0xb; /* Enable RFC RX & TX and set 8 COS */
+               wb_data[1] = 0;
+               REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
+                             wb_data, 2);
+       }
+
+       /* mac control */
+       val = 0x3; /* Enable RX and TX */
+       if (is_lb) {
+               val |= 0x4; /* Local loopback */
+               DP(NETIF_MSG_LINK, "enable bmac loopback\n");
+       }
+       /* When PFC enabled, Pass pause frames towards the NIG. */
+       if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
+               val |= (1<<6);
+
+       wb_data[0] = val;
+       wb_data[1] = 0;
+       REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
+                     wb_data, 2);
+
+       return 0;
+}
+
+static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
+                         u8 is_lb)
+{
+       u8 rc, port = params->port;
+       struct bnx2x *bp = params->bp;
+       u32 val;
+       /* reset and unreset the BigMac */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+              (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+       msleep(1);
+
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+              (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+       /* enable access for bmac registers */
+       REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
+
+       /* Enable BMAC according to BMAC type*/
+       if (CHIP_IS_E2_NOT_PHASE0(params->chip_id))
+               rc = bnx2x_bmac2_enable(params, vars, is_lb);
+       else
+               rc = bnx2x_bmac1_enable(params, vars, is_lb);
+
+       REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
+       REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
+       REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
+       val = 0;
+       if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+               val = 1;
+       REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
+       REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
+       REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
+       REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
+       REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
+       REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
+
+       vars->mac_type = MAC_TYPE_BMAC;
+       return rc;
+}
+
+static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
+{
+       struct bnx2x *bp = params->bp;
+       u32 val;
+
+       if (phy_flags & PHY_XGXS_FLAG) {
+               DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
+               val = XGXS_RESET_BITS;
+
+       } else { /* SerDes */
+               DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
+               val = SERDES_RESET_BITS;
+       }
+
+       val = val << (params->port*16);
+
+       /* reset and unreset the SerDes/XGXS */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
+                   val);
+       udelay(500);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
+                   val);
+       bnx2x_set_phy_mdio(params, phy_flags);
+}
+
+void bnx2x_link_status_update(struct link_params *params,
+                           struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u8 link_10g;
+       u8 port = params->port;
+
+       if (params->switch_cfg ==  SWITCH_CFG_1G)
+               vars->phy_flags = PHY_SERDES_FLAG;
+       else
+               vars->phy_flags = PHY_XGXS_FLAG;
+       vars->link_status = REG_RD(bp, params->shmem_base +
+                                         offsetof(struct shmem_region,
+                                          port_mb[port].link_status));
+
+       vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
+
+       if (vars->link_up) {
+               DP(NETIF_MSG_LINK, "phy link up\n");
+
+               vars->phy_link_up = 1;
+               vars->duplex = DUPLEX_FULL;
+               switch (vars->link_status &
+                                       LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
+                       case LINK_10THD:
+                               vars->duplex = DUPLEX_HALF;
+                               /* fall thru */
+                       case LINK_10TFD:
+                               vars->line_speed = SPEED_10;
+                               break;
+
+                       case LINK_100TXHD:
+                               vars->duplex = DUPLEX_HALF;
+                               /* fall thru */
+                       case LINK_100T4:
+                       case LINK_100TXFD:
+                               vars->line_speed = SPEED_100;
+                               break;
+
+                       case LINK_1000THD:
+                               vars->duplex = DUPLEX_HALF;
+                               /* fall thru */
+                       case LINK_1000TFD:
+                               vars->line_speed = SPEED_1000;
+                               break;
+
+                       case LINK_2500THD:
+                               vars->duplex = DUPLEX_HALF;
+                               /* fall thru */
+                       case LINK_2500TFD:
+                               vars->line_speed = SPEED_2500;
+                               break;
+
+                       case LINK_10GTFD:
+                               vars->line_speed = SPEED_10000;
+                               break;
+
+                       case LINK_12GTFD:
+                               vars->line_speed = SPEED_12000;
+                               break;
+
+                       case LINK_12_5GTFD:
+                               vars->line_speed = SPEED_12500;
+                               break;
+
+                       case LINK_13GTFD:
+                               vars->line_speed = SPEED_13000;
+                               break;
+
+                       case LINK_15GTFD:
+                               vars->line_speed = SPEED_15000;
+                               break;
+
+                       case LINK_16GTFD:
+                               vars->line_speed = SPEED_16000;
+                               break;
+
+                       default:
+                               break;
+               }
+
+               if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
+                       vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
+               else
+                       vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
+
+               if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
+                       vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
+               else
+                       vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
+
+               if (vars->phy_flags & PHY_XGXS_FLAG) {
+                       if (vars->line_speed &&
+                           ((vars->line_speed == SPEED_10) ||
+                            (vars->line_speed == SPEED_100))) {
+                               vars->phy_flags |= PHY_SGMII_FLAG;
+                       } else {
+                               vars->phy_flags &= ~PHY_SGMII_FLAG;
+                       }
+               }
+
+               /* anything 10 and over uses the bmac */
+               link_10g = ((vars->line_speed == SPEED_10000) ||
+                           (vars->line_speed == SPEED_12000) ||
+                           (vars->line_speed == SPEED_12500) ||
+                           (vars->line_speed == SPEED_13000) ||
+                           (vars->line_speed == SPEED_15000) ||
+                           (vars->line_speed == SPEED_16000));
+               if (link_10g)
+                       vars->mac_type = MAC_TYPE_BMAC;
+               else
+                       vars->mac_type = MAC_TYPE_EMAC;
+
+       } else { /* link down */
+               DP(NETIF_MSG_LINK, "phy link down\n");
+
+               vars->phy_link_up = 0;
+
+               vars->line_speed = 0;
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+
+               /* indicate no mac active */
+               vars->mac_type = MAC_TYPE_NONE;
+       }
+
+       DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x\n",
+                vars->link_status, vars->phy_link_up);
+       DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
+                vars->line_speed, vars->duplex, vars->flow_ctrl);
+}
+
+static void bnx2x_update_mng(struct link_params *params, u32 link_status)
+{
+       struct bnx2x *bp = params->bp;
+
+       REG_WR(bp, params->shmem_base +
+                  offsetof(struct shmem_region,
+                           port_mb[params->port].link_status),
+                       link_status);
+}
+
+static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u32 chip_id, u8 port)
+{
+       u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
+                       NIG_REG_INGRESS_BMAC0_MEM;
+       u32 wb_data[2];
+       u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN +
+                                        port*4);
+
+       /* Only if the bmac is out of reset */
+       if (REG_RD(bp, MISC_REG_RESET_REG_2) &
+                       (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
+           nig_bmac_enable) {
+
+               if (CHIP_IS_E2_NOT_PHASE0(chip_id)) {
+                       /* Clear Rx Enable bit in BMAC_CONTROL register */
+                       REG_RD_DMAE(bp, bmac_addr +
+                                     BIGMAC2_REGISTER_BMAC_CONTROL,
+                                     wb_data, 2);
+                       wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
+                       REG_WR_DMAE(bp, bmac_addr +
+                                     BIGMAC2_REGISTER_BMAC_CONTROL,
+                                     wb_data, 2);
+               } else {
+                       /* Clear Rx Enable bit in BMAC_CONTROL register */
+                       REG_RD_DMAE(bp, bmac_addr +
+                                     BIGMAC_REGISTER_BMAC_CONTROL,
+                                     wb_data, 2);
+                       wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
+                       REG_WR_DMAE(bp, bmac_addr +
+                                     BIGMAC_REGISTER_BMAC_CONTROL,
+                                     wb_data, 2);
+               }
+               msleep(1);
+       }
+}
+
+static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
+                        u32 line_speed)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u32 init_crd, crd;
+       u32 count = 1000;
+
+       /* disable port */
+       REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
+
+       /* wait for init credit */
+       init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
+       crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
+       DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
+
+       while ((init_crd != crd) && count) {
+               msleep(5);
+
+               crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
+               count--;
+       }
+       crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
+       if (init_crd != crd) {
+               DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
+                         init_crd, crd);
+               return -EINVAL;
+       }
+
+       if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
+           line_speed == SPEED_10 ||
+           line_speed == SPEED_100 ||
+           line_speed == SPEED_1000 ||
+           line_speed == SPEED_2500) {
+               REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
+               /* update threshold */
+               REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
+               /* update init credit */
+               init_crd = 778;         /* (800-18-4) */
+
+       } else {
+               u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
+                             ETH_OVREHEAD)/16;
+               REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
+               /* update threshold */
+               REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
+               /* update init credit */
+               switch (line_speed) {
+               case SPEED_10000:
+                       init_crd = thresh + 553 - 22;
+                       break;
+
+               case SPEED_12000:
+                       init_crd = thresh + 664 - 22;
+                       break;
+
+               case SPEED_13000:
+                       init_crd = thresh + 742 - 22;
+                       break;
+
+               case SPEED_16000:
+                       init_crd = thresh + 778 - 22;
+                       break;
+               default:
+                       DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
+                                 line_speed);
+                       return -EINVAL;
+               }
+       }
+       REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
+       DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
+                line_speed, init_crd);
+
+       /* probe the credit changes */
+       REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
+       msleep(5);
+       REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
+
+       /* enable port */
+       REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
+       return 0;
+}
+
+static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
+{
+       u32 emac_base;
+
+       switch (ext_phy_type) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               /* All MDC/MDIO is directed through single EMAC */
+               if (REG_RD(bp, NIG_REG_PORT_SWAP))
+                       emac_base = GRCBASE_EMAC0;
+               else
+                       emac_base = GRCBASE_EMAC1;
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+               emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
+               break;
+       default:
+               emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+               break;
+       }
+       return emac_base;
+
+}
+
+u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
+                 u8 phy_addr, u8 devad, u16 reg, u16 val)
+{
+       u32 tmp, saved_mode;
+       u8 i, rc = 0;
+       u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
+
+       /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
+        * (a value of 49==0x31) and make sure that the AUTO poll is off
+        */
+
+       saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+       tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
+                            EMAC_MDIO_MODE_CLOCK_CNT);
+       tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
+               (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
+       REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
+       REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+       udelay(40);
+
+       /* address */
+
+       tmp = ((phy_addr << 21) | (devad << 16) | reg |
+              EMAC_MDIO_COMM_COMMAND_ADDRESS |
+              EMAC_MDIO_COMM_START_BUSY);
+       REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+       for (i = 0; i < 50; i++) {
+               udelay(10);
+
+               tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
+               if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+                       udelay(5);
+                       break;
+               }
+       }
+       if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+               DP(NETIF_MSG_LINK, "write phy register failed\n");
+               rc = -EFAULT;
+       } else {
+               /* data */
+               tmp = ((phy_addr << 21) | (devad << 16) | val |
+                      EMAC_MDIO_COMM_COMMAND_WRITE_45 |
+                      EMAC_MDIO_COMM_START_BUSY);
+               REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+               for (i = 0; i < 50; i++) {
+                       udelay(10);
+
+                       tmp = REG_RD(bp, mdio_ctrl +
+                                        EMAC_REG_EMAC_MDIO_COMM);
+                       if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+                               udelay(5);
+                               break;
+                       }
+               }
+               if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+                       DP(NETIF_MSG_LINK, "write phy register failed\n");
+                       rc = -EFAULT;
+               }
+       }
+
+       /* Restore the saved mode */
+       REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
+
+       return rc;
+}
+
+u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
+                u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
+{
+       u32 val, saved_mode;
+       u16 i;
+       u8 rc = 0;
+
+       u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
+       /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
+        * (a value of 49==0x31) and make sure that the AUTO poll is off
+        */
+
+       saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+       val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
+                            EMAC_MDIO_MODE_CLOCK_CNT));
+       val |= (EMAC_MDIO_MODE_CLAUSE_45 |
+               (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
+       REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
+       REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+       udelay(40);
+
+       /* address */
+       val = ((phy_addr << 21) | (devad << 16) | reg |
+              EMAC_MDIO_COMM_COMMAND_ADDRESS |
+              EMAC_MDIO_COMM_START_BUSY);
+       REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
+
+       for (i = 0; i < 50; i++) {
+               udelay(10);
+
+               val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
+               if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+                       udelay(5);
+                       break;
+               }
+       }
+       if (val & EMAC_MDIO_COMM_START_BUSY) {
+               DP(NETIF_MSG_LINK, "read phy register failed\n");
+
+               *ret_val = 0;
+               rc = -EFAULT;
+
+       } else {
+               /* data */
+               val = ((phy_addr << 21) | (devad << 16) |
+                      EMAC_MDIO_COMM_COMMAND_READ_45 |
+                      EMAC_MDIO_COMM_START_BUSY);
+               REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
+
+               for (i = 0; i < 50; i++) {
+                       udelay(10);
+
+                       val = REG_RD(bp, mdio_ctrl +
+                                         EMAC_REG_EMAC_MDIO_COMM);
+                       if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+                               *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
+                               break;
+                       }
+               }
+               if (val & EMAC_MDIO_COMM_START_BUSY) {
+                       DP(NETIF_MSG_LINK, "read phy register failed\n");
+
+                       *ret_val = 0;
+                       rc = -EFAULT;
+               }
+       }
+
+       /* Restore the saved mode */
+       REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
+
+       return rc;
+}
+
+static void bnx2x_set_aer_mmd(struct link_params *params,
+                           struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u32 ser_lane;
+       u16 offset;
+
+       ser_lane = ((params->lane_config &
+                    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+                    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+       offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
+               (params->phy_addr + ser_lane) : 0;
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_AER_BLOCK,
+                             MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
+}
+
+static void bnx2x_set_master_ln(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u16 new_master_ln, ser_lane;
+       ser_lane =  ((params->lane_config &
+                    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+                    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+       /* set the master_ln for AN */
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_XGXS_BLOCK2,
+                             MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+                             &new_master_ln);
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_XGXS_BLOCK2 ,
+                             MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+                             (new_master_ln | ser_lane));
+}
+
+static u8 bnx2x_reset_unicore(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u16 mii_control;
+       u16 i;
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
+
+       /* reset the unicore */
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL,
+                             (mii_control |
+                              MDIO_COMBO_IEEO_MII_CONTROL_RESET));
+       if (params->switch_cfg == SWITCH_CFG_1G)
+               bnx2x_set_serdes_access(params);
+
+       /* wait for the reset to self clear */
+       for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
+               udelay(5);
+
+               /* the reset erased the previous bank value */
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL,
+                             &mii_control);
+
+               if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
+                       udelay(5);
+                       return 0;
+               }
+       }
+
+       DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
+       return -EINVAL;
+
+}
+
+static void bnx2x_set_swap_lanes(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       /* Each two bits represents a lane number:
+          No swap is 0123 => 0x1b no need to enable the swap */
+       u16 ser_lane, rx_lane_swap, tx_lane_swap;
+
+       ser_lane = ((params->lane_config &
+                        PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+                       PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+       rx_lane_swap = ((params->lane_config &
+                            PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
+                           PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
+       tx_lane_swap = ((params->lane_config &
+                            PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
+                           PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
+
+       if (rx_lane_swap != 0x1b) {
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                   MDIO_REG_BANK_XGXS_BLOCK2,
+                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
+                                   (rx_lane_swap |
+                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
+                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
+       } else {
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_XGXS_BLOCK2,
+                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
+       }
+
+       if (tx_lane_swap != 0x1b) {
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_XGXS_BLOCK2,
+                                     MDIO_XGXS_BLOCK2_TX_LN_SWAP,
+                                     (tx_lane_swap |
+                                      MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
+       } else {
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_XGXS_BLOCK2,
+                                     MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
+       }
+}
+
+static void bnx2x_set_parallel_detection(struct link_params *params,
+                                      u8 phy_flags)
+{
+       struct bnx2x *bp = params->bp;
+       u16 control2;
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_SERDES_DIGITAL,
+                             MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+                             &control2);
+
+
+       control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
+
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_SERDES_DIGITAL,
+                             MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+                             control2);
+
+       if (phy_flags & PHY_XGXS_FLAG) {
+               DP(NETIF_MSG_LINK, "XGXS\n");
+
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                               MDIO_REG_BANK_10G_PARALLEL_DETECT,
+                               MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
+                               MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
+
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                               MDIO_REG_BANK_10G_PARALLEL_DETECT,
+                               MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
+                               &control2);
+
+
+               control2 |=
+                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
+
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                               MDIO_REG_BANK_10G_PARALLEL_DETECT,
+                               MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
+                               control2);
+
+               /* Disable parallel detection of HiG */
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                               MDIO_REG_BANK_XGXS_BLOCK2,
+                               MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
+                               MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
+                               MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
+       }
+}
+
+static void bnx2x_set_autoneg(struct link_params *params,
+                           struct link_vars *vars,
+                           u8 enable_cl73)
+{
+       struct bnx2x *bp = params->bp;
+       u16 reg_val;
+
+       /* CL37 Autoneg */
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
+
+       /* CL37 Autoneg Enabled */
+       if (vars->line_speed == SPEED_AUTO_NEG)
+               reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
+       else /* CL37 Autoneg Disabled */
+               reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+                            MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
+
+       /* Enable/Disable Autodetection */
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_SERDES_DIGITAL,
+                             MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
+       reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
+       if (vars->line_speed == SPEED_AUTO_NEG)
+               reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
+       else
+               reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_SERDES_DIGITAL,
+                             MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
+
+       /* Enable TetonII and BAM autoneg */
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_BAM_NEXT_PAGE,
+                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+                         &reg_val);
+       if (vars->line_speed == SPEED_AUTO_NEG) {
+               /* Enable BAM aneg Mode and TetonII aneg Mode */
+               reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
+                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
+       } else {
+               /* TetonII and BAM Autoneg Disabled */
+               reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
+                            MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
+       }
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_BAM_NEXT_PAGE,
+                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+                             reg_val);
+
+       if (enable_cl73) {
+
+               /* Enable BAM Station Manager*/
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_CL73_USERB0,
+                                     0x10,
+                                     &reg_val);
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_CL73_USERB0,
+                                     0x10,
+                                     reg_val | 0x2);
+
+               CL45_WR_OVER_CL22(bp, params->port,
+                       params->phy_addr,
+                       MDIO_REG_BANK_CL73_USERB0,
+                       MDIO_CL73_USERB0_CL73_BAM_CTRL1,
+                       MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
+                       MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
+                       MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
+
+               /* Merge CL73 and CL37 aneg resolution */
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_CL73_USERB0,
+                                     MDIO_CL73_USERB0_CL73_BAM_CTRL3,
+                                     &reg_val);
+
+
+               /* Set the CL73 AN speed */
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_CL73_IEEEB1,
+                                     MDIO_CL73_IEEEB1_AN_ADV2,
+                                     &reg_val);
+
+               CL45_WR_OVER_CL22(bp, params->port,
+                       params->phy_addr,
+                       MDIO_REG_BANK_CL73_IEEEB1,
+                       MDIO_CL73_IEEEB1_AN_ADV2,
+                       reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4);
+
+               /* CL73 Autoneg Enabled */
+               reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
+
+       } else /* CL73 Autoneg Disabled */
+               reg_val = 0;
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_CL73_IEEEB0,
+                             MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
+}
+
+/* program SerDes, forced speed */
+static void bnx2x_program_serdes(struct link_params *params,
+                              struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u16 reg_val;
+
+       /* program duplex, disable autoneg */
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
+       reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
+                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
+       if (params->req_duplex == DUPLEX_FULL)
+               reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
+
+       /* program speed
+          - needed only if the speed is greater than 1G (2.5G or 10G) */
+       CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_SERDES_DIGITAL,
+                                     MDIO_SERDES_DIGITAL_MISC1, &reg_val);
+       /* clearing the speed value before setting the right speed */
+       DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
+
+       reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
+                    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
+
+       if (!((vars->line_speed == SPEED_1000) ||
+             (vars->line_speed == SPEED_100) ||
+             (vars->line_speed == SPEED_10))) {
+
+               reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
+                           MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
+               if (vars->line_speed == SPEED_10000)
+                       reg_val |=
+                               MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
+               if (vars->line_speed == SPEED_13000)
+                       reg_val |=
+                               MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
+       }
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_SERDES_DIGITAL,
+                                     MDIO_SERDES_DIGITAL_MISC1, reg_val);
+
+}
+
+static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u16 val = 0;
+
+       /* configure the 48 bits for BAM AN */
+
+       /* set extended capabilities */
+       if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
+               val |= MDIO_OVER_1G_UP1_2_5G;
+       if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+               val |= MDIO_OVER_1G_UP1_10G;
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_OVER_1G,
+                             MDIO_OVER_1G_UP1, val);
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_OVER_1G,
+                             MDIO_OVER_1G_UP3, 0);
+}
+
+static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
+{
+       *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
+       /* resolve pause mode and advertisement
+        * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
+
+       switch (params->req_flow_ctrl) {
+       case BNX2X_FLOW_CTRL_AUTO:
+               if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
+                       *ieee_fc |=
+                            MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+               } else {
+                       *ieee_fc |=
+                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+               }
+               break;
+       case BNX2X_FLOW_CTRL_TX:
+               *ieee_fc |=
+                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+               break;
+
+       case BNX2X_FLOW_CTRL_RX:
+       case BNX2X_FLOW_CTRL_BOTH:
+               *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+               break;
+
+       case BNX2X_FLOW_CTRL_NONE:
+       default:
+               *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
+               break;
+       }
+}
+
+static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
+                                          u16 ieee_fc)
+{
+       struct bnx2x *bp = params->bp;
+       /* for AN, we are always publishing full duplex */
+
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_COMBO_IEEE0,
+                             MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
+}
+
+static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
+{
+       struct bnx2x *bp = params->bp;
+       u16 mii_control;
+
+       DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
+       /* Enable and restart BAM/CL37 aneg */
+
+       if (enable_cl73) {
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_CL73_IEEEB0,
+                                     MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+                                     &mii_control);
+
+               CL45_WR_OVER_CL22(bp, params->port,
+                               params->phy_addr,
+                               MDIO_REG_BANK_CL73_IEEEB0,
+                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+                               (mii_control |
+                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
+                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
+       } else {
+
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_MII_CONTROL,
+                                     &mii_control);
+               DP(NETIF_MSG_LINK,
+                        "bnx2x_restart_autoneg mii_control before = 0x%x\n",
+                        mii_control);
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_MII_CONTROL,
+                                     (mii_control |
+                                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+                                      MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
+       }
+}
+
+static void bnx2x_initialize_sgmii_process(struct link_params *params,
+                                        struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u16 control1;
+
+       /* in SGMII mode, the unicore is always slave */
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_SERDES_DIGITAL,
+                             MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+                     &control1);
+       control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
+       /* set sgmii mode (and not fiber) */
+       control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
+                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
+                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
+       CL45_WR_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_SERDES_DIGITAL,
+                             MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+                             control1);
+
+       /* if forced speed */
+       if (!(vars->line_speed == SPEED_AUTO_NEG)) {
+               /* set speed, disable autoneg */
+               u16 mii_control;
+
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_MII_CONTROL,
+                                     &mii_control);
+               mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+                                MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
+                                MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
+
+               switch (vars->line_speed) {
+               case SPEED_100:
+                       mii_control |=
+                               MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
+                       break;
+               case SPEED_1000:
+                       mii_control |=
+                               MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
+                       break;
+               case SPEED_10:
+                       /* there is nothing to set for 10M */
+                       break;
+               default:
+                       /* invalid speed for SGMII */
+                       DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
+                                 vars->line_speed);
+                       break;
+               }
+
+               /* setting the full duplex */
+               if (params->req_duplex == DUPLEX_FULL)
+                       mii_control |=
+                               MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+               CL45_WR_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_MII_CONTROL,
+                                     mii_control);
+
+       } else { /* AN mode */
+               /* enable and restart AN */
+               bnx2x_restart_autoneg(params, 0);
+       }
+}
+
+
+/*
+ * link management
+ */
+
+static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
+{                                              /*  LD      LP   */
+       switch (pause_result) {                 /* ASYM P ASYM P */
+       case 0xb:                               /*   1  0   1  1 */
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
+               break;
+
+       case 0xe:                               /*   1  1   1  0 */
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
+               break;
+
+       case 0x5:                               /*   0  1   0  1 */
+       case 0x7:                               /*   0  1   1  1 */
+       case 0xd:                               /*   1  1   0  1 */
+       case 0xf:                               /*   1  1   1  1 */
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
+               break;
+
+       default:
+               break;
+       }
+}
+
+static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
+                                 struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u8 ext_phy_addr;
+       u16 ld_pause;   /* local */
+       u16 lp_pause;   /* link partner */
+       u16 an_complete; /* AN complete */
+       u16 pause_result;
+       u8 ret = 0;
+       u32 ext_phy_type;
+       u8 port = params->port;
+       ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+       /* read twice */
+
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_AN_DEVAD,
+                     MDIO_AN_REG_STATUS, &an_complete);
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_AN_DEVAD,
+                     MDIO_AN_REG_STATUS, &an_complete);
+
+       if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
+               ret = 1;
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_AN_DEVAD,
+                             MDIO_AN_REG_ADV_PAUSE, &ld_pause);
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_AN_DEVAD,
+                             MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
+               pause_result = (ld_pause &
+                               MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
+               pause_result |= (lp_pause &
+                                MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
+               DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
+                  pause_result);
+               bnx2x_pause_resolve(vars, pause_result);
+               if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
+                    ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+                       bnx2x_cl45_read(bp, port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD,
+                                     MDIO_AN_REG_CL37_FC_LD, &ld_pause);
+
+                       bnx2x_cl45_read(bp, port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD,
+                                     MDIO_AN_REG_CL37_FC_LP, &lp_pause);
+                       pause_result = (ld_pause &
+                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
+                       pause_result |= (lp_pause &
+                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
+
+                       bnx2x_pause_resolve(vars, pause_result);
+                       DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
+                                pause_result);
+               }
+       }
+       return ret;
+}
+
+
+static void bnx2x_flow_ctrl_resolve(struct link_params *params,
+                                 struct link_vars *vars,
+                                 u32 gp_status)
+{
+       struct bnx2x *bp = params->bp;
+       u16 ld_pause;   /* local driver */
+       u16 lp_pause;   /* link partner */
+       u16 pause_result;
+
+       vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+
+       /* resolve from gp_status in case of AN complete and not sgmii */
+       if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
+           (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
+           (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
+           (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
+                                     &ld_pause);
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                       MDIO_REG_BANK_COMBO_IEEE0,
+                       MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
+                       &lp_pause);
+               pause_result = (ld_pause &
+                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
+               pause_result |= (lp_pause &
+                                MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
+               DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
+               bnx2x_pause_resolve(vars, pause_result);
+       } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
+                  (bnx2x_ext_phy_resove_fc(params, vars))) {
+               return;
+       } else {
+               if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
+                       vars->flow_ctrl = params->req_fc_auto_adv;
+               else
+                       vars->flow_ctrl = params->req_flow_ctrl;
+       }
+       DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
+}
+
+
+static u8 bnx2x_link_settings_status(struct link_params *params,
+                                  struct link_vars *vars,
+                                  u32 gp_status)
+{
+       struct bnx2x *bp = params->bp;
+       u16 new_line_speed;
+       u8 rc = 0;
+       vars->link_status = 0;
+
+       if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
+               DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
+                        gp_status);
+
+               vars->phy_link_up = 1;
+               vars->link_status |= LINK_STATUS_LINK_UP;
+
+               if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
+                       vars->duplex = DUPLEX_FULL;
+               else
+                       vars->duplex = DUPLEX_HALF;
+
+               bnx2x_flow_ctrl_resolve(params, vars, gp_status);
+
+               switch (gp_status & GP_STATUS_SPEED_MASK) {
+               case GP_STATUS_10M:
+                       new_line_speed = SPEED_10;
+                       if (vars->duplex == DUPLEX_FULL)
+                               vars->link_status |= LINK_10TFD;
+                       else
+                               vars->link_status |= LINK_10THD;
+                       break;
+
+               case GP_STATUS_100M:
+                       new_line_speed = SPEED_100;
+                       if (vars->duplex == DUPLEX_FULL)
+                               vars->link_status |= LINK_100TXFD;
+                       else
+                               vars->link_status |= LINK_100TXHD;
+                       break;
+
+               case GP_STATUS_1G:
+               case GP_STATUS_1G_KX:
+                       new_line_speed = SPEED_1000;
+                       if (vars->duplex == DUPLEX_FULL)
+                               vars->link_status |= LINK_1000TFD;
+                       else
+                               vars->link_status |= LINK_1000THD;
+                       break;
+
+               case GP_STATUS_2_5G:
+                       new_line_speed = SPEED_2500;
+                       if (vars->duplex == DUPLEX_FULL)
+                               vars->link_status |= LINK_2500TFD;
+                       else
+                               vars->link_status |= LINK_2500THD;
+                       break;
+
+               case GP_STATUS_5G:
+               case GP_STATUS_6G:
+                       DP(NETIF_MSG_LINK,
+                                "link speed unsupported  gp_status 0x%x\n",
+                                 gp_status);
+                       return -EINVAL;
+
+               case GP_STATUS_10G_KX4:
+               case GP_STATUS_10G_HIG:
+               case GP_STATUS_10G_CX4:
+                       new_line_speed = SPEED_10000;
+                       vars->link_status |= LINK_10GTFD;
+                       break;
+
+               case GP_STATUS_12G_HIG:
+                       new_line_speed = SPEED_12000;
+                       vars->link_status |= LINK_12GTFD;
+                       break;
+
+               case GP_STATUS_12_5G:
+                       new_line_speed = SPEED_12500;
+                       vars->link_status |= LINK_12_5GTFD;
+                       break;
+
+               case GP_STATUS_13G:
+                       new_line_speed = SPEED_13000;
+                       vars->link_status |= LINK_13GTFD;
+                       break;
+
+               case GP_STATUS_15G:
+                       new_line_speed = SPEED_15000;
+                       vars->link_status |= LINK_15GTFD;
+                       break;
+
+               case GP_STATUS_16G:
+                       new_line_speed = SPEED_16000;
+                       vars->link_status |= LINK_16GTFD;
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK,
+                                 "link speed unsupported gp_status 0x%x\n",
+                                 gp_status);
+                       return -EINVAL;
+               }
+
+               /* Upon link speed change set the NIG into drain mode.
+               Comes to deals with possible FIFO glitch due to clk change
+               when speed is decreased without link down indicator */
+               if (new_line_speed != vars->line_speed) {
+                       REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
+                                   + params->port*4, 0);
+                       msleep(1);
+               }
+               vars->line_speed = new_line_speed;
+               vars->link_status |= LINK_STATUS_SERDES_LINK;
+
+               if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+                   ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
+                   (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
+                   (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
+                       vars->autoneg = AUTO_NEG_ENABLED;
+
+                       if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+                               vars->autoneg |= AUTO_NEG_COMPLETE;
+                               vars->link_status |=
+                                       LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+                       }
+
+                       vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
+                       vars->link_status |=
+                               LINK_STATUS_PARALLEL_DETECTION_USED;
+
+               }
+               if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+                       vars->link_status |=
+                               LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
+
+               if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
+                       vars->link_status |=
+                               LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
+
+       } else { /* link_down */
+               DP(NETIF_MSG_LINK, "phy link down\n");
+
+               vars->phy_link_up = 0;
+
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+               vars->autoneg = AUTO_NEG_DISABLED;
+               vars->mac_type = MAC_TYPE_NONE;
+       }
+
+       DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x \n",
+                gp_status, vars->phy_link_up, vars->line_speed);
+       DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x"
+                " autoneg 0x%x\n",
+                vars->duplex,
+                vars->flow_ctrl, vars->autoneg);
+       DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
+
+       return rc;
+}
+
+static void bnx2x_set_gmii_tx_driver(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u16 lp_up2;
+       u16 tx_driver;
+       u16 bank;
+
+       /* read precomp */
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_OVER_1G,
+                             MDIO_OVER_1G_LP_UP2, &lp_up2);
+
+       /* bits [10:7] at lp_up2, positioned at [15:12] */
+       lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
+                  MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
+                 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
+
+       if (lp_up2 == 0)
+               return;
+
+       for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
+             bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
+               CL45_RD_OVER_CL22(bp, params->port,
+                                     params->phy_addr,
+                                     bank,
+                                     MDIO_TX0_TX_DRIVER, &tx_driver);
+
+               /* replace tx_driver bits [15:12] */
+               if (lp_up2 !=
+                   (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
+                       tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
+                       tx_driver |= lp_up2;
+                       CL45_WR_OVER_CL22(bp, params->port,
+                                             params->phy_addr,
+                                             bank,
+                                             MDIO_TX0_TX_DRIVER, tx_driver);
+               }
+       }
+}
+
+static u8 bnx2x_emac_program(struct link_params *params,
+                          u32 line_speed, u32 duplex)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u16 mode = 0;
+
+       DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
+       bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
+                    EMAC_REG_EMAC_MODE,
+                    (EMAC_MODE_25G_MODE |
+                    EMAC_MODE_PORT_MII_10M |
+                    EMAC_MODE_HALF_DUPLEX));
+       switch (line_speed) {
+       case SPEED_10:
+               mode |= EMAC_MODE_PORT_MII_10M;
+               break;
+
+       case SPEED_100:
+               mode |= EMAC_MODE_PORT_MII;
+               break;
+
+       case SPEED_1000:
+               mode |= EMAC_MODE_PORT_GMII;
+               break;
+
+       case SPEED_2500:
+               mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
+               break;
+
+       default:
+               /* 10G not valid for EMAC */
+               DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
+               return -EINVAL;
+       }
+
+       if (duplex == DUPLEX_HALF)
+               mode |= EMAC_MODE_HALF_DUPLEX;
+       bnx2x_bits_en(bp,
+                   GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
+                   mode);
+
+       bnx2x_set_led(bp, params->port, LED_MODE_OPER,
+                   line_speed, params->hw_led_mode, params->chip_id);
+       return 0;
+}
+
+/*****************************************************************************/
+/*                          External Phy section                            */
+/*****************************************************************************/
+void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
+{
+       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                         MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+       msleep(1);
+       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                         MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+}
+
+static void bnx2x_ext_phy_reset(struct link_params *params,
+                             struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u32 ext_phy_type;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+       DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
+       ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+       /* The PHY reset is controled by GPIO 1
+        * Give it 1ms of reset pulse
+        */
+       if (vars->phy_flags & PHY_XGXS_FLAG) {
+
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+                       DP(NETIF_MSG_LINK, "XGXS Direct\n");
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+                       DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
+
+                       /* Restore normal power mode*/
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       /* HW reset */
+                       bnx2x_ext_phy_hw_reset(bp, params->port);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_CTRL, 0xa040);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+
+                       /* Restore normal power mode*/
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_CTRL,
+                                      1<<15);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+                       DP(NETIF_MSG_LINK, "XGXS 8072\n");
+
+                       /* Unset Low Power Mode and SW reset */
+                       /* Restore normal power mode*/
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_CTRL,
+                                      1<<15);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+                       DP(NETIF_MSG_LINK, "XGXS 8073\n");
+
+                       /* Restore normal power mode*/
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+                       DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
+
+                       /* Restore normal power mode*/
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       /* HW reset */
+                       bnx2x_ext_phy_hw_reset(bp, params->port);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+                       /* Restore normal power mode*/
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
+
+                       /* HW reset */
+                       bnx2x_ext_phy_hw_reset(bp, params->port);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_CTRL,
+                                      1<<15);
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+                       DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+                                params->ext_phy_config);
+                       break;
+               }
+
+       } else { /* SerDes */
+               ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+                       DP(NETIF_MSG_LINK, "SerDes Direct\n");
+                       break;
+
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+                       DP(NETIF_MSG_LINK, "SerDes 5482\n");
+                       bnx2x_ext_phy_hw_reset(bp, params->port);
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
+                                params->ext_phy_config);
+                       break;
+               }
+       }
+}
+
+static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
+                                   u32 shmem_base, u32 spirom_ver)
+{
+       DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
+                (u16)(spirom_ver>>16), (u16)spirom_ver);
+       REG_WR(bp, shmem_base +
+                  offsetof(struct shmem_region,
+                           port_mb[port].ext_phy_fw_version),
+                       spirom_ver);
+}
+
+static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
+                                   u32 ext_phy_type, u8 ext_phy_addr,
+                                   u32 shmem_base)
+{
+       u16 fw_ver1, fw_ver2;
+
+       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER1, &fw_ver1);
+       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER2, &fw_ver2);
+       bnx2x_save_spirom_version(bp, port, shmem_base,
+                               (u32)(fw_ver1<<16 | fw_ver2));
+}
+
+
+static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
+                                        u8 ext_phy_addr, u32 shmem_base)
+{
+       u16 val, fw_ver1, fw_ver2, cnt;
+       /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
+       /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr, MDIO_PMA_DEVAD,
+                      0xA819, 0x0014);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      0xA81A,
+                      0xc200);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      0xA81B,
+                      0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      0xA81C,
+                      0x0300);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      0xA817,
+                      0x0009);
+
+       for (cnt = 0; cnt < 100; cnt++) {
+               bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             0xA818,
+                             &val);
+               if (val & 1)
+                       break;
+               udelay(5);
+       }
+       if (cnt == 100) {
+               DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
+               bnx2x_save_spirom_version(bp, port,
+                                       shmem_base, 0);
+               return;
+       }
+
+
+       /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr, MDIO_PMA_DEVAD,
+                      0xA819, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr, MDIO_PMA_DEVAD,
+                      0xA81A, 0xc200);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr, MDIO_PMA_DEVAD,
+                      0xA817, 0x000A);
+       for (cnt = 0; cnt < 100; cnt++) {
+               bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             0xA818,
+                             &val);
+               if (val & 1)
+                       break;
+               udelay(5);
+       }
+       if (cnt == 100) {
+               DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
+               bnx2x_save_spirom_version(bp, port,
+                                       shmem_base, 0);
+               return;
+       }
+
+       /* lower 16 bits of the register SPI_FW_STATUS */
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     0xA81B,
+                     &fw_ver1);
+       /* upper 16 bits of register SPI_FW_STATUS */
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     0xA81C,
+                     &fw_ver2);
+
+       bnx2x_save_spirom_version(bp, port,
+                               shmem_base, (fw_ver2<<16) | fw_ver1);
+}
+
+static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       /* Need to wait 200ms after reset */
+       msleep(200);
+       /* Boot port from external ROM
+        * Set ser_boot_ctl bit in the MISC_CTRL1 register
+        */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
+       /* Reset internal microprocessor */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+       /* set micro reset = 0 */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+       /* Reset internal microprocessor */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+       /* wait for 100ms for code download via SPI port */
+       msleep(100);
+
+       /* Clear ser_boot_ctl bit */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+       /* Wait 100ms */
+       msleep(100);
+
+       bnx2x_save_bcm_spirom_ver(bp, port,
+                               ext_phy_type,
+                               ext_phy_addr,
+                               params->shmem_base);
+}
+
+static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
+{
+       /* This is only required for 8073A1, version 102 only */
+
+       struct bnx2x *bp = params->bp;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u16 val;
+
+       /* Read 8073 HW revision*/
+       bnx2x_cl45_read(bp, params->port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_8073_CHIP_REV, &val);
+
+       if (val != 1) {
+               /* No need to workaround in 8073 A1 */
+               return 0;
+       }
+
+       bnx2x_cl45_read(bp, params->port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER2, &val);
+
+       /* SNR should be applied only for version 0x102 */
+       if (val != 0x102)
+               return 0;
+
+       return 1;
+}
+
+static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u16 val, cnt, cnt1 ;
+
+       bnx2x_cl45_read(bp, params->port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_8073_CHIP_REV, &val);
+
+       if (val > 0) {
+               /* No need to workaround in 8073 A1 */
+               return 0;
+       }
+       /* XAUI workaround in 8073 A0: */
+
+       /* After loading the boot ROM and restarting Autoneg,
+       poll Dev1, Reg $C820: */
+
+       for (cnt = 0; cnt < 1000; cnt++) {
+               bnx2x_cl45_read(bp, params->port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
+                             &val);
+                 /* If bit [14] = 0 or bit [13] = 0, continue on with
+                  system initialization (XAUI work-around not required,
+                   as these bits indicate 2.5G or 1G link up). */
+               if (!(val & (1<<14)) || !(val & (1<<13))) {
+                       DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
+                       return 0;
+               } else if (!(val & (1<<15))) {
+                       DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
+                        /* If bit 15 is 0, then poll Dev1, Reg $C841 until
+                         it's MSB (bit 15) goes to 1 (indicating that the
+                         XAUI workaround has completed),
+                         then continue on with system initialization.*/
+                       for (cnt1 = 0; cnt1 < 1000; cnt1++) {
+                               bnx2x_cl45_read(bp, params->port,
+                                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                                       ext_phy_addr,
+                                       MDIO_PMA_DEVAD,
+                                       MDIO_PMA_REG_8073_XAUI_WA, &val);
+                               if (val & (1<<15)) {
+                                       DP(NETIF_MSG_LINK,
+                                         "XAUI workaround has completed\n");
+                                       return 0;
+                                }
+                                msleep(3);
+                       }
+                       break;
+               }
+               msleep(3);
+       }
+       DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
+       return -EINVAL;
+}
+
+static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
+                                                 u8 ext_phy_addr,
+                                                 u32 ext_phy_type,
+                                                 u32 shmem_base)
+{
+       /* Boot port from external ROM  */
+       /* EDC grst */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      0x0001);
+
+       /* ucode reboot and rst */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      0x008c);
+
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
+       /* Reset internal microprocessor */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+
+       /* Release srst bit */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+
+       /* wait for 100ms for code download via SPI port */
+       msleep(100);
+
+       /* Clear ser_boot_ctl bit */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+
+       bnx2x_save_bcm_spirom_ver(bp, port,
+                               ext_phy_type,
+                               ext_phy_addr,
+                               shmem_base);
+}
+
+static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
+                                         u8 ext_phy_addr,
+                                         u32 shmem_base)
+{
+       bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
+                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                                        shmem_base);
+}
+
+static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
+                                         u8 ext_phy_addr,
+                                         u32 shmem_base)
+{
+       bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
+                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                                        shmem_base);
+
+}
+
+static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       /* Need to wait 100ms after reset */
+       msleep(100);
+
+       /* Set serial boot control for external load */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
+       /* Micro controller re-boot */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+
+       /* Set soft reset */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+
+       /* Set PLL register value to be same like in P13 ver */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_PLL_CTRL,
+                      0x73A0);
+
+       /* Clear soft reset.
+       Will automatically reset micro-controller re-boot */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL,
+                      MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+
+       /* wait for 150ms for microcode load */
+       msleep(150);
+
+       /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+
+       msleep(200);
+       bnx2x_save_bcm_spirom_ver(bp, port,
+                               ext_phy_type,
+                               ext_phy_addr,
+                               params->shmem_base);
+}
+
+static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
+                                   u32 ext_phy_type, u8 ext_phy_addr,
+                                   u8 tx_en)
+{
+       u16 val;
+
+       DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
+                tx_en, port);
+       /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_PHY_IDENTIFIER,
+                     &val);
+
+       if (tx_en)
+               val &= ~(1<<15);
+       else
+               val |= (1<<15);
+
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_PHY_IDENTIFIER,
+                      val);
+}
+
+static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
+                                         u16 addr, u8 byte_cnt, u8 *o_buf)
+{
+       struct bnx2x *bp = params->bp;
+       u16 val = 0;
+       u16 i;
+       u8 port = params->port;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       if (byte_cnt > 16) {
+               DP(NETIF_MSG_LINK, "Reading from eeprom is"
+                           " is limited to 0xf\n");
+               return -EINVAL;
+       }
+       /* Set the read command byte count */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
+                      (byte_cnt | 0xa000));
+
+       /* Set the read command address */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
+                      addr);
+
+       /* Activate read command */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+                      0x2c0f);
+
+       /* Wait up to 500us for command complete status */
+       for (i = 0; i < 100; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+               if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+                   MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
+                       break;
+               udelay(5);
+       }
+
+       if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
+                   MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+               DP(NETIF_MSG_LINK,
+                        "Got bad status 0x%x when reading from SFP+ EEPROM\n",
+                        (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+               return -EINVAL;
+       }
+
+       /* Read the buffer */
+       for (i = 0; i < byte_cnt; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
+               o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
+       }
+
+       for (i = 0; i < 100; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+               if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+                   MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
+                       return 0;;
+               msleep(1);
+       }
+       return -EINVAL;
+}
+
+static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
+                                         u16 addr, u8 byte_cnt, u8 *o_buf)
+{
+       struct bnx2x *bp = params->bp;
+       u16 val, i;
+       u8 port = params->port;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       if (byte_cnt > 16) {
+               DP(NETIF_MSG_LINK, "Reading from eeprom is"
+                           " is limited to 0xf\n");
+               return -EINVAL;
+       }
+
+       /* Need to read from 1.8000 to clear it */
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+                     &val);
+
+       /* Set the read command byte count */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
+                      ((byte_cnt < 2) ? 2 : byte_cnt));
+
+       /* Set the read command address */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
+                      addr);
+       /* Set the destination address */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      0x8004,
+                      MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
+
+       /* Activate read command */
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+                      0x8002);
+       /* Wait appropriate time for two-wire command to finish before
+       polling the status register */
+       msleep(1);
+
+       /* Wait up to 500us for command complete status */
+       for (i = 0; i < 100; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+               if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+                   MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
+                       break;
+               udelay(5);
+       }
+
+       if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
+                   MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+               DP(NETIF_MSG_LINK,
+                        "Got bad status 0x%x when reading from SFP+ EEPROM\n",
+                        (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+               return -EINVAL;
+       }
+
+       /* Read the buffer */
+       for (i = 0; i < byte_cnt; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
+               o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
+       }
+
+       for (i = 0; i < 100; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+               if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+                   MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
+                       return 0;;
+               msleep(1);
+       }
+
+       return -EINVAL;
+}
+
+u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
+                                    u8 byte_cnt, u8 *o_buf)
+{
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
+               return bnx2x_8726_read_sfp_module_eeprom(params, addr,
+                                                      byte_cnt, o_buf);
+       else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
+               return bnx2x_8727_read_sfp_module_eeprom(params, addr,
+                                                      byte_cnt, o_buf);
+       return -EINVAL;
+}
+
+static u8 bnx2x_get_edc_mode(struct link_params *params,
+                                 u16 *edc_mode)
+{
+       struct bnx2x *bp = params->bp;
+       u8 val, check_limiting_mode = 0;
+       *edc_mode = EDC_MODE_LIMITING;
+
+       /* First check for copper cable */
+       if (bnx2x_read_sfp_module_eeprom(params,
+                                      SFP_EEPROM_CON_TYPE_ADDR,
+                                      1,
+                                      &val) != 0) {
+               DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
+               return -EINVAL;
+       }
+
+       switch (val) {
+       case SFP_EEPROM_CON_TYPE_VAL_COPPER:
+       {
+               u8 copper_module_type;
+
+               /* Check if its active cable( includes SFP+ module)
+               of passive cable*/
+               if (bnx2x_read_sfp_module_eeprom(params,
+                                              SFP_EEPROM_FC_TX_TECH_ADDR,
+                                              1,
+                                              &copper_module_type) !=
+                   0) {
+                       DP(NETIF_MSG_LINK,
+                               "Failed to read copper-cable-type"
+                               " from SFP+ EEPROM\n");
+                       return -EINVAL;
+               }
+
+               if (copper_module_type &
+                   SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
+                       DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
+                       check_limiting_mode = 1;
+               } else if (copper_module_type &
+                       SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
+                               DP(NETIF_MSG_LINK, "Passive Copper"
+                                           " cable detected\n");
+                               *edc_mode =
+                                     EDC_MODE_PASSIVE_DAC;
+               } else {
+                       DP(NETIF_MSG_LINK, "Unknown copper-cable-"
+                                    "type 0x%x !!!\n", copper_module_type);
+                       return -EINVAL;
+               }
+               break;
+       }
+       case SFP_EEPROM_CON_TYPE_VAL_LC:
+               DP(NETIF_MSG_LINK, "Optic module detected\n");
+               check_limiting_mode = 1;
+               break;
+       default:
+               DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
+                        val);
+               return -EINVAL;
+       }
+
+       if (check_limiting_mode) {
+               u8 options[SFP_EEPROM_OPTIONS_SIZE];
+               if (bnx2x_read_sfp_module_eeprom(params,
+                                              SFP_EEPROM_OPTIONS_ADDR,
+                                              SFP_EEPROM_OPTIONS_SIZE,
+                                              options) != 0) {
+                       DP(NETIF_MSG_LINK, "Failed to read Option"
+                               " field from module EEPROM\n");
+                       return -EINVAL;
+               }
+               if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
+                       *edc_mode = EDC_MODE_LINEAR;
+               else
+                       *edc_mode = EDC_MODE_LIMITING;
+       }
+       DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
+       return 0;
+}
+
+/* This function read the relevant field from the module ( SFP+ ),
+       and verify it is compliant with this board */
+static u8 bnx2x_verify_sfp_module(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u32 val;
+       u32 fw_resp;
+       char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
+       char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
+
+       val = REG_RD(bp, params->shmem_base +
+                        offsetof(struct shmem_region, dev_info.
+                                 port_feature_config[params->port].config));
+       if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+           PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
+               DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
+               return 0;
+       }
+
+       /* Ask the FW to validate the module */
+       if (!(params->feature_config_flags &
+             FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
+               DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
+                           "verification\n");
+               return -EINVAL;
+       }
+
+       fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
+       if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
+               DP(NETIF_MSG_LINK, "Approved module\n");
+               return 0;
+       }
+
+       /* format the warning message */
+       if (bnx2x_read_sfp_module_eeprom(params,
+                                      SFP_EEPROM_VENDOR_NAME_ADDR,
+                                      SFP_EEPROM_VENDOR_NAME_SIZE,
+                                      (u8 *)vendor_name))
+               vendor_name[0] = '\0';
+       else
+               vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
+       if (bnx2x_read_sfp_module_eeprom(params,
+                                      SFP_EEPROM_PART_NO_ADDR,
+                                      SFP_EEPROM_PART_NO_SIZE,
+                                      (u8 *)vendor_pn))
+               vendor_pn[0] = '\0';
+       else
+               vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
+
+       printk(KERN_INFO PFX  "Warning: "
+                        "Unqualified SFP+ module "
+                        "detected on %s, Port %d from %s part number %s\n"
+                       , bp->dev->name, params->port,
+                       vendor_name, vendor_pn);
+       return -EINVAL;
+}
+
+static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
+                                       u16 edc_mode)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u16 cur_limiting_mode;
+
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER2,
+                     &cur_limiting_mode);
+       DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
+                cur_limiting_mode);
+
+       if (edc_mode == EDC_MODE_LIMITING) {
+               DP(NETIF_MSG_LINK,
+                        "Setting LIMITING MODE\n");
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_ROM_VER2,
+                              EDC_MODE_LIMITING);
+       } else { /* LRM mode ( default )*/
+
+               DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
+
+               /* Changing to LRM mode takes quite few seconds.
+               So do it only if current mode is limiting
+               ( default is LRM )*/
+               if (cur_limiting_mode != EDC_MODE_LIMITING)
+                       return 0;
+
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_LRM_MODE,
+                              0);
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_ROM_VER2,
+                              0x128);
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_MISC_CTRL0,
+                              0x4008);
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_LRM_MODE,
+                              0xaaaa);
+       }
+       return 0;
+}
+
+static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
+                                       u16 edc_mode)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u16 phy_identifier;
+       u16 rom_ver2_val;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+       bnx2x_cl45_read(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_PHY_IDENTIFIER,
+                      &phy_identifier);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_PHY_IDENTIFIER,
+                      (phy_identifier & ~(1<<9)));
+
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER2,
+                     &rom_ver2_val);
+       /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_ROM_VER2,
+                      (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_PHY_IDENTIFIER,
+                      (phy_identifier | (1<<9)));
+
+       return 0;
+}
+
+
+static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
+{
+       u8 val;
+       struct bnx2x *bp = params->bp;
+       u16 timeout;
+       /* Initialization time after hot-plug may take up to 300ms for some
+       phys type ( e.g. JDSU ) */
+       for (timeout = 0; timeout < 60; timeout++) {
+               if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
+                   == 0) {
+                       DP(NETIF_MSG_LINK, "SFP+ module initialization "
+                                    "took %d ms\n", timeout * 5);
+                       return 0;
+               }
+               msleep(5);
+       }
+       return -EINVAL;
+}
+
+static void bnx2x_8727_power_module(struct bnx2x *bp,
+                                 struct link_params *params,
+                                 u8 ext_phy_addr, u8 is_power_up) {
+       /* Make sure GPIOs are not using for LED mode */
+       u16 val;
+       u8 port = params->port;
+       /*
+        * In the GPIO register, bit 4 is use to detemine if the GPIOs are
+        * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
+        * output
+        * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
+        * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
+        * where the 1st bit is the over-current(only input), and 2nd bit is
+        * for power( only output )
+       */
+
+       /*
+        * In case of NOC feature is disabled and power is up, set GPIO control
+        *  as input to enable listening of over-current indication
+        */
+
+       if (!(params->feature_config_flags &
+             FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
+               val = (1<<4);
+       else
+               /*
+                * Set GPIO control to OUTPUT, and set the power bit
+                * to according to the is_power_up
+                */
+               val = ((!(is_power_up)) << 1);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_8727_GPIO_CTRL,
+                      val);
+}
+
+static u8 bnx2x_sfp_module_detection(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u16 edc_mode;
+       u8 rc = 0;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+       u32 val = REG_RD(bp, params->shmem_base +
+                            offsetof(struct shmem_region, dev_info.
+                                    port_feature_config[params->port].config));
+
+       DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
+                params->port);
+
+       if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
+               DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
+               return -EINVAL;
+       } else if (bnx2x_verify_sfp_module(params) !=
+                  0) {
+               /* check SFP+ module compatibility */
+               DP(NETIF_MSG_LINK, "Module verification failed!!\n");
+               rc = -EINVAL;
+               /* Turn on fault module-detected led */
+               bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                                 MISC_REGISTERS_GPIO_HIGH,
+                                 params->port);
+               if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
+                   ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+                    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
+                       /* Shutdown SFP+ module */
+                       DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
+                       bnx2x_8727_power_module(bp, params,
+                                             ext_phy_addr, 0);
+                       return rc;
+               }
+       } else {
+               /* Turn off fault module-detected led */
+               DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
+               bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                                         MISC_REGISTERS_GPIO_LOW,
+                                         params->port);
+       }
+
+       /* power up the SFP module */
+       if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
+               bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
+
+       /* Check and set limiting mode / LRM mode on 8726.
+       On 8727 it is done automatically */
+       if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
+               bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
+       else
+               bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
+       /*
+        * Enable transmit for this module if the module is approved, or
+        * if unapproved modules should also enable the Tx laser
+        */
+       if (rc == 0 ||
+           (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
+           PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+               bnx2x_sfp_set_transmitter(bp, params->port,
+                                       ext_phy_type, ext_phy_addr, 1);
+       else
+               bnx2x_sfp_set_transmitter(bp, params->port,
+                                       ext_phy_type, ext_phy_addr, 0);
+
+       return rc;
+}
+
+void bnx2x_handle_module_detect_int(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u32 gpio_val;
+       u8 port = params->port;
+
+       /* Set valid module led off */
+       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                         MISC_REGISTERS_GPIO_HIGH,
+                         params->port);
+
+       /* Get current gpio val refelecting module plugged in / out*/
+       gpio_val = bnx2x_get_gpio(bp,  MISC_REGISTERS_GPIO_3, port);
+
+       /* Call the handling function in case module is detected */
+       if (gpio_val == 0) {
+
+               bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
+                                     MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
+                                     port);
+
+               if (bnx2x_wait_for_sfp_module_initialized(params) ==
+                   0)
+                       bnx2x_sfp_module_detection(params);
+               else
+                       DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
+       } else {
+               u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+               u32 ext_phy_type =
+                       XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+               u32 val = REG_RD(bp, params->shmem_base +
+                                    offsetof(struct shmem_region, dev_info.
+                                             port_feature_config[params->port].
+                                             config));
+
+               bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
+                                     MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
+                                     port);
+               /* Module was plugged out. */
+               /* Disable transmit for this module */
+               if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+                   PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+                       bnx2x_sfp_set_transmitter(bp, params->port,
+                                               ext_phy_type, ext_phy_addr, 0);
+       }
+}
+
+static void bnx2x_bcm807x_force_10G(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       /* Force KR or KX */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_CTRL,
+                      0x2040);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_10G_CTRL2,
+                      0x000b);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_BCM_CTRL,
+                      0x0000);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_AN_DEVAD,
+                      MDIO_AN_REG_CTRL,
+                      0x0000);
+}
+
+static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u16 val;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       bnx2x_cl45_read(bp, params->port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_8073_CHIP_REV, &val);
+
+       if (val == 0) {
+               /* Mustn't set low power mode in 8073 A0 */
+               return;
+       }
+
+       /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
+       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD,
+                      MDIO_XS_PLL_SEQUENCER, &val);
+       val &= ~(1<<13);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
+
+       /* PLL controls */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x805E, 0x1077);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x805D, 0x0000);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x805C, 0x030B);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x805B, 0x1240);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x805A, 0x2490);
+
+       /* Tx Controls */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x80A7, 0x0C74);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x80A6, 0x9041);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x80A5, 0x4640);
+
+       /* Rx Controls */
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x80FE, 0x01C4);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x80FD, 0x9249);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, 0x80FC, 0x2015);
+
+       /* Enable PLL sequencer  (use read-modify-write to set bit 13) */
+       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
+                     MDIO_XS_DEVAD,
+                     MDIO_XS_PLL_SEQUENCER, &val);
+       val |= (1<<13);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
+}
+
+static void bnx2x_8073_set_pause_cl37(struct link_params *params,
+                                   struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u16 cl37_val;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       bnx2x_cl45_read(bp, params->port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_AN_DEVAD,
+                     MDIO_AN_REG_CL37_FC_LD, &cl37_val);
+
+       cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+       /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
+
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
+               cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
+       }
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
+               cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+       }
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
+               cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+       }
+       DP(NETIF_MSG_LINK,
+                "Ext phy AN advertize cl37 0x%x\n", cl37_val);
+
+       bnx2x_cl45_write(bp, params->port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_AN_DEVAD,
+                      MDIO_AN_REG_CL37_FC_LD, cl37_val);
+       msleep(500);
+}
+
+static void bnx2x_ext_phy_set_pause(struct link_params *params,
+                                 struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u16 val;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       /* read modify write pause advertizing */
+       bnx2x_cl45_read(bp, params->port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_AN_DEVAD,
+                     MDIO_AN_REG_ADV_PAUSE, &val);
+
+       val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
+
+       /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
+
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
+               val |=  MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
+       }
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
+               val |=
+                MDIO_AN_REG_ADV_PAUSE_PAUSE;
+       }
+       DP(NETIF_MSG_LINK,
+                "Ext phy AN advertize 0x%x\n", val);
+       bnx2x_cl45_write(bp, params->port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_AN_DEVAD,
+                      MDIO_AN_REG_ADV_PAUSE, val);
+}
+static void bnx2x_set_preemphasis(struct link_params *params)
+{
+       u16 bank, i = 0;
+       struct bnx2x *bp = params->bp;
+
+       for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
+               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
+                       CL45_WR_OVER_CL22(bp, params->port,
+                                             params->phy_addr,
+                                             bank,
+                                             MDIO_RX0_RX_EQ_BOOST,
+                                             params->xgxs_config_rx[i]);
+       }
+
+       for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
+               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
+                       CL45_WR_OVER_CL22(bp, params->port,
+                                             params->phy_addr,
+                                             bank,
+                                             MDIO_TX0_TX_DRIVER,
+                                             params->xgxs_config_tx[i]);
+       }
+}
+
+static void bnx2x_init_internal_phy(struct link_params *params,
+                                 struct link_vars *vars,
+                                 u8 enable_cl73)
+{
+       struct bnx2x *bp = params->bp;
+
+       if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
+               if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+                   (params->feature_config_flags &
+                    FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
+                       bnx2x_set_preemphasis(params);
+
+               /* forced speed requested? */
+               if (vars->line_speed != SPEED_AUTO_NEG) {
+                       DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
+
+                       /* disable autoneg */
+                       bnx2x_set_autoneg(params, vars, 0);
+
+                       /* program speed and duplex */
+                       bnx2x_program_serdes(params, vars);
+
+               } else { /* AN_mode */
+                       DP(NETIF_MSG_LINK, "not SGMII, AN\n");
+
+                       /* AN enabled */
+                       bnx2x_set_brcm_cl37_advertisment(params);
+
+                       /* program duplex & pause advertisement (for aneg) */
+                       bnx2x_set_ieee_aneg_advertisment(params,
+                                                      vars->ieee_fc);
+
+                       /* enable autoneg */
+                       bnx2x_set_autoneg(params, vars, enable_cl73);
+
+                       /* enable and restart AN */
+                       bnx2x_restart_autoneg(params, enable_cl73);
+               }
+
+       } else { /* SGMII mode */
+               DP(NETIF_MSG_LINK, "SGMII\n");
+
+               bnx2x_initialize_sgmii_process(params, vars);
+       }
+}
+
+static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u32 ext_phy_type;
+       u8 ext_phy_addr;
+       u16 cnt;
+       u16 ctrl = 0;
+       u16 val = 0;
+       u8 rc = 0;
+
+       if (vars->phy_flags & PHY_XGXS_FLAG) {
+               ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+               ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+               /* Make sure that the soft reset is off (expect for the 8072:
+                * due to the lock, it will be done inside the specific
+                * handling)
+                */
+               if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+                   (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
+                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
+                   (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
+                   (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
+                       /* Wait for soft reset to get cleared upto 1 sec */
+                       for (cnt = 0; cnt < 1000; cnt++) {
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PMA_DEVAD,
+                                             MDIO_PMA_REG_CTRL, &ctrl);
+                               if (!(ctrl & (1<<15)))
+                                       break;
+                               msleep(1);
+                       }
+                       DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
+                                ctrl, cnt);
+               }
+
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+                       DP(NETIF_MSG_LINK, "XGXS 8705\n");
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_MISC_CTRL,
+                                      0x8288);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_PHY_IDENTIFIER,
+                                      0x7fbf);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_CMU_PLL_BYPASS,
+                                      0x0100);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_WIS_DEVAD,
+                                      MDIO_WIS_REG_LASI_CNTL, 0x1);
+
+                       /* BCM8705 doesn't have microcode, hence the 0 */
+                       bnx2x_save_spirom_version(bp, params->port,
+                                               params->shmem_base, 0);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+                       /* Wait until fw is loaded */
+                       for (cnt = 0; cnt < 100; cnt++) {
+                               bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                             ext_phy_addr, MDIO_PMA_DEVAD,
+                                             MDIO_PMA_REG_ROM_VER1, &val);
+                               if (val)
+                                       break;
+                               msleep(10);
+                       }
+                       DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
+                               "after %d ms\n", cnt);
+                       if ((params->feature_config_flags &
+                            FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
+                               u8 i;
+                               u16 reg;
+                               for (i = 0; i < 4; i++) {
+                                       reg = MDIO_XS_8706_REG_BANK_RX0 +
+                                               i*(MDIO_XS_8706_REG_BANK_RX1 -
+                                                  MDIO_XS_8706_REG_BANK_RX0);
+                                       bnx2x_cl45_read(bp, params->port,
+                                                     ext_phy_type,
+                                                     ext_phy_addr,
+                                                     MDIO_XS_DEVAD,
+                                                     reg, &val);
+                                       /* Clear first 3 bits of the control */
+                                       val &= ~0x7;
+                                       /* Set control bits according to
+                                       configuation */
+                                       val |= (params->xgxs_config_rx[i] &
+                                               0x7);
+                                       DP(NETIF_MSG_LINK, "Setting RX"
+                                                "Equalizer to BCM8706 reg 0x%x"
+                                                " <-- val 0x%x\n", reg, val);
+                                       bnx2x_cl45_write(bp, params->port,
+                                                      ext_phy_type,
+                                                      ext_phy_addr,
+                                                      MDIO_XS_DEVAD,
+                                                      reg, val);
+                               }
+                       }
+                       /* Force speed */
+                       /* First enable LASI */
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_RX_ALARM_CTRL,
+                                      0x0400);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_LASI_CTRL, 0x0004);
+
+                       if (params->req_line_speed == SPEED_10000) {
+                               DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_DIGITAL_CTRL,
+                                               0x400);
+                       } else {
+                               /* Force 1Gbps using autoneg with 1G
+                               advertisment */
+
+                               /* Allow CL37 through CL73 */
+                               DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_CL73,
+                                              0x040c);
+
+                               /* Enable Full-Duplex advertisment on CL37 */
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_FC_LP,
+                                              0x0020);
+                               /* Enable CL37 AN */
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_AN,
+                                              0x1000);
+                               /* 1G support */
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_ADV, (1<<5));
+
+                               /* Enable clause 73 AN */
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CTRL,
+                                              0x1200);
+
+                       }
+                       bnx2x_save_bcm_spirom_ver(bp, params->port,
+                                               ext_phy_type,
+                                               ext_phy_addr,
+                                               params->shmem_base);
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+                       DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
+                       bnx2x_bcm8726_external_rom_boot(params);
+
+                       /* Need to call module detected on initialization since
+                       the module detection triggered by actual module
+                       insertion might occur before driver is loaded, and when
+                       driver is loaded, it reset all registers, including the
+                       transmitter */
+                       bnx2x_sfp_module_detection(params);
+
+                       /* Set Flow control */
+                       bnx2x_ext_phy_set_pause(params, vars);
+                       if (params->req_line_speed == SPEED_1000) {
+                               DP(NETIF_MSG_LINK, "Setting 1G force\n");
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_CTRL, 0x40);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_10G_CTRL2, 0xD);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_LASI_CTRL, 0x5);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_RX_ALARM_CTRL,
+                                              0x400);
+                       } else if ((params->req_line_speed ==
+                                   SPEED_AUTO_NEG) &&
+                                  ((params->speed_cap_mask &
+                                    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
+                               DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_ADV, 0x20);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_CL73, 0x040c);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_FC_LD, 0x0020);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_AN, 0x1000);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CTRL, 0x1200);
+
+                               /* Enable RX-ALARM control to receive
+                               interrupt for 1G speed change */
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_LASI_CTRL, 0x4);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_RX_ALARM_CTRL,
+                                              0x400);
+
+                       } else { /* Default 10G. Set only LASI control */
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_LASI_CTRL, 1);
+                       }
+
+                       /* Set TX PreEmphasis if needed */
+                       if ((params->feature_config_flags &
+                            FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
+                               DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
+                                        "TX_CTRL2 0x%x\n",
+                                        params->xgxs_config_tx[0],
+                                        params->xgxs_config_tx[1]);
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_8726_TX_CTRL1,
+                                              params->xgxs_config_tx[0]);
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_8726_TX_CTRL2,
+                                              params->xgxs_config_tx[1]);
+                       }
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+               {
+                       u16 tmp1;
+                       u16 rx_alarm_ctrl_val;
+                       u16 lasi_ctrl_val;
+                       if (ext_phy_type ==
+                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
+                               rx_alarm_ctrl_val = 0x400;
+                               lasi_ctrl_val = 0x0004;
+                       } else {
+                               rx_alarm_ctrl_val = (1<<2);
+                               lasi_ctrl_val = 0x0004;
+                       }
+
+                       /* enable LASI */
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_RX_ALARM_CTRL,
+                                      rx_alarm_ctrl_val);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_LASI_CTRL,
+                                      lasi_ctrl_val);
+
+                       bnx2x_8073_set_pause_cl37(params, vars);
+
+                       if (ext_phy_type ==
+                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
+                               bnx2x_bcm8072_external_rom_boot(params);
+                       else
+                               /* In case of 8073 with long xaui lines,
+                               don't set the 8073 xaui low power*/
+                               bnx2x_bcm8073_set_xaui_low_power_mode(params);
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_M8051_MSGOUT_REG,
+                                     &tmp1);
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_RX_ALARM, &tmp1);
+
+                       DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
+                                            "0x%x\n", tmp1);
+
+                       /* If this is forced speed, set to KR or KX
+                        * (all other are not supported)
+                        */
+                       if (params->loopback_mode == LOOPBACK_EXT) {
+                               bnx2x_bcm807x_force_10G(params);
+                               DP(NETIF_MSG_LINK,
+                                       "Forced speed 10G on 807X\n");
+                               break;
+                       } else {
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type, ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_BCM_CTRL,
+                                              0x0002);
+                       }
+                       if (params->req_line_speed != SPEED_AUTO_NEG) {
+                               if (params->req_line_speed == SPEED_10000) {
+                                       val = (1<<7);
+                               } else if (params->req_line_speed ==
+                                          SPEED_2500) {
+                                       val = (1<<5);
+                                       /* Note that 2.5G works only
+                                       when used with 1G advertisment */
+                               } else
+                                       val = (1<<5);
+                       } else {
+
+                               val = 0;
+                               if (params->speed_cap_mask &
+                                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+                                       val |= (1<<7);
+
+                               /* Note that 2.5G works only when
+                               used with 1G advertisment */
+                               if (params->speed_cap_mask &
+                                       (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
+                                       val |= (1<<5);
+                               DP(NETIF_MSG_LINK,
+                                        "807x autoneg val = 0x%x\n", val);
+                       }
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_ADV, val);
+                       if (ext_phy_type ==
+                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_8073_2_5G, &tmp1);
+
+                               if (((params->speed_cap_mask &
+                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
+                                    (params->req_line_speed ==
+                                     SPEED_AUTO_NEG)) ||
+                                   (params->req_line_speed ==
+                                    SPEED_2500)) {
+                                       u16 phy_ver;
+                                       /* Allow 2.5G for A1 and above */
+                                       bnx2x_cl45_read(bp, params->port,
+                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                                        ext_phy_addr,
+                                        MDIO_PMA_DEVAD,
+                                        MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
+                                       DP(NETIF_MSG_LINK, "Add 2.5G\n");
+                                       if (phy_ver > 0)
+                                               tmp1 |= 1;
+                                       else
+                                               tmp1 &= 0xfffe;
+                               } else {
+                                       DP(NETIF_MSG_LINK, "Disable 2.5G\n");
+                                       tmp1 &= 0xfffe;
+                               }
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_8073_2_5G, tmp1);
+                       }
+
+                       /* Add support for CL37 (passive mode) II */
+
+                       bnx2x_cl45_read(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_CL37_FC_LD,
+                                      &tmp1);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_CL37_FC_LD, (tmp1 |
+                                      ((params->req_duplex == DUPLEX_FULL) ?
+                                      0x20 : 0x40)));
+
+                       /* Add support for CL37 (passive mode) III */
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_CL37_AN, 0x1000);
+
+                       if (ext_phy_type ==
+                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+                               /* The SNR will improve about 2db by changing
+                               BW and FEE main tap. Rest commands are executed
+                               after link is up*/
+                               /*Change FFE main cursor to 5 in EDC register*/
+                               if (bnx2x_8073_is_snr_needed(params))
+                                       bnx2x_cl45_write(bp, params->port,
+                                                   ext_phy_type,
+                                                   ext_phy_addr,
+                                                   MDIO_PMA_DEVAD,
+                                                   MDIO_PMA_REG_EDC_FFE_MAIN,
+                                                   0xFB0C);
+
+                               /* Enable FEC (Forware Error Correction)
+                               Request in the AN */
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_ADV2, &tmp1);
+
+                               tmp1 |= (1<<15);
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_ADV2, tmp1);
+
+                       }
+
+                       bnx2x_ext_phy_set_pause(params, vars);
+
+                       /* Restart autoneg */
+                       msleep(500);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_CTRL, 0x1200);
+                       DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
+                          "Advertise 1G=%x, 10G=%x\n",
+                          ((val & (1<<5)) > 0),
+                          ((val & (1<<7)) > 0));
+                       break;
+               }
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               {
+                       u16 tmp1;
+                       u16 rx_alarm_ctrl_val;
+                       u16 lasi_ctrl_val;
+
+                       /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
+
+                       u16 mod_abs;
+                       rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
+                       lasi_ctrl_val = 0x0004;
+
+                       DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
+                       /* enable LASI */
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_RX_ALARM_CTRL,
+                                      rx_alarm_ctrl_val);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_LASI_CTRL,
+                                      lasi_ctrl_val);
+
+                       /* Initially configure  MOD_ABS to interrupt when
+                       module is presence( bit 8) */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
+                       /* Set EDC off by setting OPTXLOS signal input to low
+                       (bit 9).
+                       When the EDC is off it locks onto a reference clock and
+                       avoids becoming 'lost'.*/
+                       mod_abs &= ~((1<<8) | (1<<9));
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
+
+                       /* Make MOD_ABS give interrupt on change */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+                                     &val);
+                       val |= (1<<12);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+                                      val);
+
+                       /* Set 8727 GPIOs to input to allow reading from the
+                       8727 GPIO0 status which reflect SFP+ module
+                       over-current */
+
+                       bnx2x_cl45_read(bp, params->port,
+                                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+                                      &val);
+                       val &= 0xff8f; /* Reset bits 4-6 */
+                       bnx2x_cl45_write(bp, params->port,
+                                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+                                      val);
+
+                       bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
+                       bnx2x_bcm8073_set_xaui_low_power_mode(params);
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_M8051_MSGOUT_REG,
+                                     &tmp1);
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_RX_ALARM, &tmp1);
+
+                       /* Set option 1G speed */
+                       if (params->req_line_speed == SPEED_1000) {
+
+                               DP(NETIF_MSG_LINK, "Setting 1G force\n");
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_CTRL, 0x40);
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_10G_CTRL2, 0xD);
+                               bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_10G_CTRL2, &tmp1);
+                               DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1);
+
+                       } else if ((params->req_line_speed ==
+                                   SPEED_AUTO_NEG) &&
+                                  ((params->speed_cap_mask &
+                                    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
+
+                               DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_PMA_REG_8727_MISC_CTRL, 0);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CL37_AN, 0x1300);
+                       } else {
+                               /* Since the 8727 has only single reset pin,
+                               need to set the 10G registers although it is
+                               default */
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_CTRL, 0x0020);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_AN_DEVAD,
+                                              0x7, 0x0100);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_CTRL, 0x2040);
+                               bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                              ext_phy_addr, MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_10G_CTRL2, 0x0008);
+                       }
+
+                       /* Set 2-wire transfer rate to 400Khz since 100Khz
+                       is not operational */
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
+                                      0xa101);
+
+                       /* Set TX PreEmphasis if needed */
+                       if ((params->feature_config_flags &
+                            FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
+                               DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
+                                        "TX_CTRL2 0x%x\n",
+                                        params->xgxs_config_tx[0],
+                                        params->xgxs_config_tx[1]);
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_8727_TX_CTRL1,
+                                              params->xgxs_config_tx[0]);
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_8727_TX_CTRL2,
+                                              params->xgxs_config_tx[1]);
+                       }
+
+                       break;
+               }
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+               {
+                       u16 fw_ver1, fw_ver2;
+                       DP(NETIF_MSG_LINK,
+                               "Setting the SFX7101 LASI indication\n");
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_LASI_CTRL, 0x1);
+                       DP(NETIF_MSG_LINK,
+                         "Setting the SFX7101 LED to blink on traffic\n");
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
+
+                       bnx2x_ext_phy_set_pause(params, vars);
+                       /* Restart autoneg */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD,
+                                     MDIO_AN_REG_CTRL, &val);
+                       val |= 0x200;
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_CTRL, val);
+
+                       /* Save spirom version */
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr, MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_7101_VER1, &fw_ver1);
+
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr, MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_7101_VER2, &fw_ver2);
+
+                       bnx2x_save_spirom_version(params->bp, params->port,
+                                               params->shmem_base,
+                                               (u32)(fw_ver1<<16 | fw_ver2));
+                       break;
+               }
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+                       DP(NETIF_MSG_LINK,
+                               "Setting the BCM8481 LASI control\n");
+                       /* This phy uses the NIG latch mechanism since link
+                               indication arrives through its LED4 and not via
+                               its LASI signal, so we get steady signal
+                               instead of clear on read */
+                       bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
+                                   1 << NIG_LATCH_BC_ENABLE_MI_INT);
+
+                       /* Enable LED4 when link speed is 10/100/1000 */
+                       /* Bit 15 enables write to the shadow reg */
+                       /* Bits 10..14 sets the shadow reg to LED selector 2 */
+                       /* Bits 4..7 Set the LED2 selector itself to LED4 */
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_8481_LEGACY_SHADOW,
+                                      (1<<15) | (0xe << 10) | (0xc << 4));
+                       /* Enable continous signal to go active  on link */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
+                       val &= ~(1<<11);
+                       val |= (2<<9);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_8481_LINK_SIGNAL, val);
+                       /* Unmask LED4 for 10G link */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_8481_SIGNAL_MASK, &val);
+                       val |= (1<<7);
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_8481_SIGNAL_MASK, val);
+
+                       if (params->req_line_speed == SPEED_AUTO_NEG) {
+
+                               u16 autoneg_val, an_1000_val, an_10_100_val;
+                               /* set 1000 speed advertisement */
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_8481_1000T_CTRL,
+                                             &an_1000_val);
+
+                               if (params->speed_cap_mask &
+                                   PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
+                                       an_1000_val |= (1<<8);
+                                       if (params->req_duplex == DUPLEX_FULL)
+                                               an_1000_val |= (1<<9);
+                                       DP(NETIF_MSG_LINK, "Advertising 1G\n");
+                               } else
+                                       an_1000_val &= ~((1<<8) | (1<<9));
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_8481_1000T_CTRL,
+                                              an_1000_val);
+
+                               /* set 100 speed advertisement */
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_8481_LEGACY_AN_ADV,
+                                             &an_10_100_val);
+
+                               if (params->speed_cap_mask &
+                                (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
+                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
+                                       an_10_100_val |= (1<<7);
+                                       if (params->req_duplex == DUPLEX_FULL)
+                                               an_10_100_val |= (1<<8);
+                                       DP(NETIF_MSG_LINK,
+                                               "Advertising 100M\n");
+                               } else
+                                       an_10_100_val &= ~((1<<7) | (1<<8));
+
+                               /* set 10 speed advertisement */
+                               if (params->speed_cap_mask &
+                                 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
+                                  PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
+                                       an_10_100_val |= (1<<5);
+                                       if (params->req_duplex == DUPLEX_FULL)
+                                               an_10_100_val |= (1<<6);
+                                       DP(NETIF_MSG_LINK, "Advertising 10M\n");
+                                    }
+                               else
+                                       an_10_100_val &= ~((1<<5) | (1<<6));
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_8481_LEGACY_AN_ADV,
+                                              an_10_100_val);
+
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+                                             &autoneg_val);
+
+                               /* Disable forced speed */
+                               autoneg_val &= ~(1<<6|1<<13);
+
+                               /* Enable autoneg and restart autoneg
+                               for legacy speeds */
+                               autoneg_val |= (1<<9|1<<12);
+
+                               if (params->req_duplex == DUPLEX_FULL)
+                                       autoneg_val |= (1<<8);
+                               else
+                                       autoneg_val &= ~(1<<8);
+
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+                                              autoneg_val);
+
+                               if (params->speed_cap_mask &
+                                   PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
+                                       DP(NETIF_MSG_LINK, "Advertising 10G\n");
+                                       /* Restart autoneg for 10G*/
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD,
+                                     MDIO_AN_REG_CTRL, &val);
+                       val |= 0x200;
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_AN_DEVAD,
+                                      MDIO_AN_REG_CTRL, val);
+                               }
+                       } else {
+                               /* Force speed */
+                               u16 autoneg_ctrl, pma_ctrl;
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+                                             &autoneg_ctrl);
+
+                               /* Disable autoneg */
+                               autoneg_ctrl &= ~(1<<12);
+
+                               /* Set 1000 force */
+                               switch (params->req_line_speed) {
+                               case SPEED_10000:
+                                       DP(NETIF_MSG_LINK,
+                                               "Unable to set 10G force !\n");
+                                       break;
+                               case SPEED_1000:
+                                       bnx2x_cl45_read(bp, params->port,
+                                                     ext_phy_type,
+                                                     ext_phy_addr,
+                                                     MDIO_PMA_DEVAD,
+                                                     MDIO_PMA_REG_CTRL,
+                                                     &pma_ctrl);
+                                       autoneg_ctrl &= ~(1<<13);
+                                       autoneg_ctrl |= (1<<6);
+                                       pma_ctrl &= ~(1<<13);
+                                       pma_ctrl |= (1<<6);
+                                       DP(NETIF_MSG_LINK,
+                                               "Setting 1000M force\n");
+                                       bnx2x_cl45_write(bp, params->port,
+                                                      ext_phy_type,
+                                                      ext_phy_addr,
+                                                      MDIO_PMA_DEVAD,
+                                                      MDIO_PMA_REG_CTRL,
+                                                      pma_ctrl);
+                                       break;
+                               case SPEED_100:
+                                       autoneg_ctrl |= (1<<13);
+                                       autoneg_ctrl &= ~(1<<6);
+                                       DP(NETIF_MSG_LINK,
+                                               "Setting 100M force\n");
+                                       break;
+                               case SPEED_10:
+                                       autoneg_ctrl &= ~(1<<13);
+                                       autoneg_ctrl &= ~(1<<6);
+                                       DP(NETIF_MSG_LINK,
+                                               "Setting 10M force\n");
+                                       break;
+                               }
+
+                               /* Duplex mode */
+                               if (params->req_duplex == DUPLEX_FULL) {
+                                       autoneg_ctrl |= (1<<8);
+                                       DP(NETIF_MSG_LINK,
+                                               "Setting full duplex\n");
+                               } else
+                                       autoneg_ctrl &= ~(1<<8);
+
+                               /* Update autoneg ctrl and pma ctrl */
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_AN_DEVAD,
+                                              MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+                                              autoneg_ctrl);
+                       }
+
+                       /* Save spirom version */
+                       bnx2x_save_8481_spirom_version(bp, params->port,
+                                                    ext_phy_addr,
+                                                    params->shmem_base);
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+                       DP(NETIF_MSG_LINK,
+                                "XGXS PHY Failure detected 0x%x\n",
+                                params->ext_phy_config);
+                       rc = -EINVAL;
+                       break;
+               default:
+                       DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+                                 params->ext_phy_config);
+                       rc = -EINVAL;
+                       break;
+               }
+
+       } else { /* SerDes */
+
+               ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+                       DP(NETIF_MSG_LINK, "SerDes Direct\n");
+                       break;
+
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+                       DP(NETIF_MSG_LINK, "SerDes 5482\n");
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
+                          params->ext_phy_config);
+                       break;
+               }
+       }
+       return rc;
+}
+
+static void bnx2x_8727_handle_mod_abs(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u16 mod_abs, rx_alarm_status;
+       u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+       u32 val = REG_RD(bp, params->shmem_base +
+                            offsetof(struct shmem_region, dev_info.
+                                     port_feature_config[params->port].
+                                     config));
+       bnx2x_cl45_read(bp, params->port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
+       if (mod_abs & (1<<8)) {
+
+               /* Module is absent */
+               DP(NETIF_MSG_LINK, "MOD_ABS indication "
+                           "show module is absent\n");
+
+               /* 1. Set mod_abs to detect next module
+               presence event
+                  2. Set EDC off by setting OPTXLOS signal input to low
+                       (bit 9).
+                       When the EDC is off it locks onto a reference clock and
+                       avoids becoming 'lost'.*/
+               mod_abs &= ~((1<<8)|(1<<9));
+               bnx2x_cl45_write(bp, params->port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
+
+               /* Clear RX alarm since it stays up as long as
+               the mod_abs wasn't changed */
+               bnx2x_cl45_read(bp, params->port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
+
+       } else {
+               /* Module is present */
+               DP(NETIF_MSG_LINK, "MOD_ABS indication "
+                           "show module is present\n");
+               /* First thing, disable transmitter,
+               and if the module is ok, the
+               module_detection will enable it*/
+
+               /* 1. Set mod_abs to detect next module
+               absent event ( bit 8)
+                  2. Restore the default polarity of the OPRXLOS signal and
+               this signal will then correctly indicate the presence or
+               absence of the Rx signal. (bit 9) */
+               mod_abs |= ((1<<8)|(1<<9));
+               bnx2x_cl45_write(bp, params->port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
+
+               /* Clear RX alarm since it stays up as long as
+               the mod_abs wasn't changed. This is need to be done
+               before calling the module detection, otherwise it will clear
+               the link update alarm */
+               bnx2x_cl45_read(bp, params->port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
+
+
+               if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+                   PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+                       bnx2x_sfp_set_transmitter(bp, params->port,
+                                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                                       ext_phy_addr, 0);
+
+               if (bnx2x_wait_for_sfp_module_initialized(params)
+                   == 0)
+                       bnx2x_sfp_module_detection(params);
+               else
+                       DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
+       }
+
+       DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
+                rx_alarm_status);
+       /* No need to check link status in case of
+       module plugged in/out */
+}
+
+
+static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
+                                struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u32 ext_phy_type;
+       u8 ext_phy_addr;
+       u16 val1 = 0, val2;
+       u16 rx_sd, pcs_status;
+       u8 ext_phy_link_up = 0;
+       u8 port = params->port;
+
+       if (vars->phy_flags & PHY_XGXS_FLAG) {
+               ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+               ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+                       DP(NETIF_MSG_LINK, "XGXS Direct\n");
+                       ext_phy_link_up = 1;
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+                       DP(NETIF_MSG_LINK, "XGXS 8705\n");
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_WIS_DEVAD,
+                                     MDIO_WIS_REG_LASI_STATUS, &val1);
+                       DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
+
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_WIS_DEVAD,
+                                     MDIO_WIS_REG_LASI_STATUS, &val1);
+                       DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
+
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_RX_SD, &rx_sd);
+
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     1,
+                                     0xc809, &val1);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     1,
+                                     0xc809, &val1);
+
+                       DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
+                       ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9))
+                                          && ((val1 & (1<<8)) == 0));
+                       if (ext_phy_link_up)
+                               vars->line_speed = SPEED_10000;
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+                       DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
+                       /* Clear RX Alarm*/
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
+                                     &val2);
+                       /* clear LASI indication*/
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
+                                     &val1);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
+                                     &val2);
+                       DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
+                                    "0x%x\n", val1, val2);
+
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
+                                     &rx_sd);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
+                                     &pcs_status);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
+                                     &val2);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
+                                     &val2);
+
+                       DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
+                          "  pcs_status 0x%x 1Gbps link_status 0x%x\n",
+                          rx_sd, pcs_status, val2);
+                       /* link is up if both bit 0 of pmd_rx_sd and
+                        * bit 0 of pcs_status are set, or if the autoneg bit
+                          1 is set
+                        */
+                       ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
+                                          (val2 & (1<<1)));
+                       if (ext_phy_link_up) {
+                               if (ext_phy_type ==
+                                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
+                                       /* If transmitter is disabled,
+                                       ignore false link up indication */
+                                       bnx2x_cl45_read(bp, params->port,
+                                                  ext_phy_type,
+                                                  ext_phy_addr,
+                                                  MDIO_PMA_DEVAD,
+                                                  MDIO_PMA_REG_PHY_IDENTIFIER,
+                                                  &val1);
+                                       if (val1 & (1<<15)) {
+                                               DP(NETIF_MSG_LINK, "Tx is "
+                                                           "disabled\n");
+                                               ext_phy_link_up = 0;
+                                               break;
+                                       }
+                               }
+                               if (val2 & (1<<1))
+                                       vars->line_speed = SPEED_1000;
+                               else
+                                       vars->line_speed = SPEED_10000;
+                       }
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               {
+                       u16 link_status = 0;
+                       u16 rx_alarm_status;
+                       /* Check the LASI */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
+
+                       DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
+                                rx_alarm_status);
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_LASI_STATUS, &val1);
+
+                       DP(NETIF_MSG_LINK,
+                                "8727 LASI status 0x%x\n",
+                                val1);
+
+                       /* Clear MSG-OUT */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_M8051_MSGOUT_REG,
+                                     &val1);
+
+                       /*
+                        * If a module is present and there is need to check
+                        * for over current
+                        */
+                       if (!(params->feature_config_flags &
+                             FEATURE_CONFIG_BCM8727_NOC) &&
+                           !(rx_alarm_status & (1<<5))) {
+                               /* Check over-current using 8727 GPIO0 input*/
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PMA_DEVAD,
+                                             MDIO_PMA_REG_8727_GPIO_CTRL,
+                                             &val1);
+
+                               if ((val1 & (1<<8)) == 0) {
+                                       DP(NETIF_MSG_LINK, "8727 Power fault has"
+                                                " been detected on port %d\n",
+                                                params->port);
+                                       printk(KERN_ERR PFX  "Error:  Power"
+                                                " fault on %s Port %d has"
+                                                " been detected and the"
+                                                " power to that SFP+ module"
+                                                " has been removed to prevent"
+                                                " failure of the card. Please"
+                                                " remove the SFP+ module and"
+                                                " restart the system to clear"
+                                                " this error.\n"
+                       , bp->dev->name, params->port);
+                                       /*
+                                        * Disable all RX_ALARMs except for
+                                        * mod_abs
+                                        */
+                                       bnx2x_cl45_write(bp, params->port,
+                                                    ext_phy_type,
+                                                    ext_phy_addr,
+                                                    MDIO_PMA_DEVAD,
+                                                    MDIO_PMA_REG_RX_ALARM_CTRL,
+                                                    (1<<5));
+
+                                       bnx2x_cl45_read(bp, params->port,
+                                                   ext_phy_type,
+                                                   ext_phy_addr,
+                                                   MDIO_PMA_DEVAD,
+                                                   MDIO_PMA_REG_PHY_IDENTIFIER,
+                                                   &val1);
+                                       /* Wait for module_absent_event */
+                                       val1 |= (1<<8);
+                                       bnx2x_cl45_write(bp, params->port,
+                                                   ext_phy_type,
+                                                   ext_phy_addr,
+                                                   MDIO_PMA_DEVAD,
+                                                   MDIO_PMA_REG_PHY_IDENTIFIER,
+                                                   val1);
+                                       /* Clear RX alarm */
+                                       bnx2x_cl45_read(bp, params->port,
+                                                     ext_phy_type,
+                                                     ext_phy_addr,
+                                                     MDIO_PMA_DEVAD,
+                                                     MDIO_PMA_REG_RX_ALARM,
+                                                     &rx_alarm_status);
+                                       break;
+                               }
+                       } /* Over current check */
+
+                       /* When module absent bit is set, check module */
+                       if (rx_alarm_status & (1<<5)) {
+                               bnx2x_8727_handle_mod_abs(params);
+                               /* Enable all mod_abs and link detection bits */
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type,
+                                              ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_RX_ALARM_CTRL,
+                                              ((1<<5) | (1<<2)));
+                       }
+
+                       /* If transmitter is disabled,
+                       ignore false link up indication */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_PHY_IDENTIFIER,
+                                     &val1);
+                       if (val1 & (1<<15)) {
+                               DP(NETIF_MSG_LINK, "Tx is disabled\n");
+                               ext_phy_link_up = 0;
+                               break;
+                       }
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
+                                     &link_status);
+
+                       /* Bits 0..2 --> speed detected,
+                          bits 13..15--> link is down */
+                       if ((link_status & (1<<2)) &&
+                           (!(link_status & (1<<15)))) {
+                               ext_phy_link_up = 1;
+                               vars->line_speed = SPEED_10000;
+                       } else if ((link_status & (1<<0)) &&
+                                  (!(link_status & (1<<13)))) {
+                               ext_phy_link_up = 1;
+                               vars->line_speed = SPEED_1000;
+                               DP(NETIF_MSG_LINK,
+                                        "port %x: External link"
+                                        " up in 1G\n", params->port);
+                       } else {
+                               ext_phy_link_up = 0;
+                               DP(NETIF_MSG_LINK,
+                                        "port %x: External link"
+                                        " is down\n", params->port);
+                       }
+                       break;
+               }
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+               {
+                       u16 link_status = 0;
+                       u16 an1000_status = 0;
+
+                       if (ext_phy_type ==
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PCS_DEVAD,
+                                             MDIO_PCS_REG_LASI_STATUS, &val1);
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PCS_DEVAD,
+                                             MDIO_PCS_REG_LASI_STATUS, &val2);
+                               DP(NETIF_MSG_LINK,
+                                        "870x LASI status 0x%x->0x%x\n",
+                                        val1, val2);
+                       } else {
+                               /* In 8073, port1 is directed through emac0 and
+                                * port0 is directed through emac1
+                                */
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PMA_DEVAD,
+                                             MDIO_PMA_REG_LASI_STATUS, &val1);
+
+                               DP(NETIF_MSG_LINK,
+                                        "8703 LASI status 0x%x\n",
+                                         val1);
+                       }
+
+                       /* clear the interrupt LASI status register */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PCS_DEVAD,
+                                     MDIO_PCS_REG_STATUS, &val2);
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PCS_DEVAD,
+                                     MDIO_PCS_REG_STATUS, &val1);
+                       DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
+                                val2, val1);
+                       /* Clear MSG-OUT */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_M8051_MSGOUT_REG,
+                                     &val1);
+
+                       /* Check the LASI */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_RX_ALARM, &val2);
+
+                       DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
+
+                       /* Check the link status */
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PCS_DEVAD,
+                                     MDIO_PCS_REG_STATUS, &val2);
+                       DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
+
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_STATUS, &val2);
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_STATUS, &val1);
+                       ext_phy_link_up = ((val1 & 4) == 4);
+                       DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
+                       if (ext_phy_type ==
+                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+
+                               if (ext_phy_link_up &&
+                                   ((params->req_line_speed !=
+                                       SPEED_10000))) {
+                                       if (bnx2x_bcm8073_xaui_wa(params)
+                                            != 0) {
+                                               ext_phy_link_up = 0;
+                                               break;
+                                       }
+                               }
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_LINK_STATUS,
+                                             &an1000_status);
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_LINK_STATUS,
+                                             &an1000_status);
+
+                               /* Check the link status on 1.1.2 */
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PMA_DEVAD,
+                                             MDIO_PMA_REG_STATUS, &val2);
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_PMA_DEVAD,
+                                             MDIO_PMA_REG_STATUS, &val1);
+                               DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
+                                            "an_link_status=0x%x\n",
+                                         val2, val1, an1000_status);
+
+                               ext_phy_link_up = (((val1 & 4) == 4) ||
+                                               (an1000_status & (1<<1)));
+                               if (ext_phy_link_up &&
+                                   bnx2x_8073_is_snr_needed(params)) {
+                                       /* The SNR will improve about 2dbby
+                                       changing the BW and FEE main tap.*/
+
+                                       /* The 1st write to change FFE main
+                                       tap is set before restart AN */
+                                       /* Change PLL Bandwidth in EDC
+                                       register */
+                                       bnx2x_cl45_write(bp, port, ext_phy_type,
+                                                   ext_phy_addr,
+                                                   MDIO_PMA_DEVAD,
+                                                   MDIO_PMA_REG_PLL_BANDWIDTH,
+                                                   0x26BC);
+
+                                       /* Change CDR Bandwidth in EDC
+                                       register */
+                                       bnx2x_cl45_write(bp, port, ext_phy_type,
+                                               ext_phy_addr,
+                                               MDIO_PMA_DEVAD,
+                                               MDIO_PMA_REG_CDR_BANDWIDTH,
+                                               0x0333);
+                               }
+                               bnx2x_cl45_read(bp, params->port,
+                                          ext_phy_type,
+                                          ext_phy_addr,
+                                          MDIO_PMA_DEVAD,
+                                          MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
+                                          &link_status);
+
+                               /* Bits 0..2 --> speed detected,
+                                  bits 13..15--> link is down */
+                               if ((link_status & (1<<2)) &&
+                                   (!(link_status & (1<<15)))) {
+                                       ext_phy_link_up = 1;
+                                       vars->line_speed = SPEED_10000;
+                                       DP(NETIF_MSG_LINK,
+                                                "port %x: External link"
+                                                " up in 10G\n", params->port);
+                               } else if ((link_status & (1<<1)) &&
+                                          (!(link_status & (1<<14)))) {
+                                       ext_phy_link_up = 1;
+                                       vars->line_speed = SPEED_2500;
+                                       DP(NETIF_MSG_LINK,
+                                                "port %x: External link"
+                                                " up in 2.5G\n", params->port);
+                               } else if ((link_status & (1<<0)) &&
+                                          (!(link_status & (1<<13)))) {
+                                       ext_phy_link_up = 1;
+                                       vars->line_speed = SPEED_1000;
+                                       DP(NETIF_MSG_LINK,
+                                                "port %x: External link"
+                                                " up in 1G\n", params->port);
+                               } else {
+                                       ext_phy_link_up = 0;
+                                       DP(NETIF_MSG_LINK,
+                                                "port %x: External link"
+                                                " is down\n", params->port);
+                               }
+                       } else {
+                               /* See if 1G link is up for the 8072 */
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_LINK_STATUS,
+                                             &an1000_status);
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_LINK_STATUS,
+                                             &an1000_status);
+                               if (an1000_status & (1<<1)) {
+                                       ext_phy_link_up = 1;
+                                       vars->line_speed = SPEED_1000;
+                                       DP(NETIF_MSG_LINK,
+                                                "port %x: External link"
+                                                " up in 1G\n", params->port);
+                               } else if (ext_phy_link_up) {
+                                       ext_phy_link_up = 1;
+                                       vars->line_speed = SPEED_10000;
+                                       DP(NETIF_MSG_LINK,
+                                                "port %x: External link"
+                                                " up in 10G\n", params->port);
+                               }
+                       }
+
+
+                       break;
+               }
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_LASI_STATUS, &val2);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_LASI_STATUS, &val1);
+                       DP(NETIF_MSG_LINK,
+                                "10G-base-T LASI status 0x%x->0x%x\n",
+                                 val2, val1);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_STATUS, &val2);
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_STATUS, &val1);
+                       DP(NETIF_MSG_LINK,
+                                "10G-base-T PMA status 0x%x->0x%x\n",
+                                val2, val1);
+                       ext_phy_link_up = ((val1 & 4) == 4);
+                       /* if link is up
+                        * print the AN outcome of the SFX7101 PHY
+                        */
+                       if (ext_phy_link_up) {
+                               bnx2x_cl45_read(bp, params->port,
+                                             ext_phy_type,
+                                             ext_phy_addr,
+                                             MDIO_AN_DEVAD,
+                                             MDIO_AN_REG_MASTER_STATUS,
+                                             &val2);
+                               vars->line_speed = SPEED_10000;
+                               DP(NETIF_MSG_LINK,
+                                        "SFX7101 AN status 0x%x->Master=%x\n",
+                                         val2,
+                                        (val2 & (1<<14)));
+                       }
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+                       /* Clear LASI interrupt. (Obsolete) */
+
+                       DP(NETIF_MSG_LINK, "8481 LASI status reg = 0x%x\n",
+                                val1);
+
+                       /* Check 10G-BaseT link status */
+                       /* Check PMD signal ok */
+                       bnx2x_cl45_read(bp, params->port, ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_8481_PMD_SIGNAL,
+                                     &val2);
+
+                       /* Check link 10G */
+                       if (val2 & (1<<11)) {
+                               vars->line_speed = SPEED_10000;
+                               ext_phy_link_up = 1;
+                       } else { /* Check Legacy speed link */
+                               u16 legacy_status, legacy_speed;
+
+                               /* Enable expansion register 0x42
+                               (Operation mode status) */
+                               bnx2x_cl45_write(bp, params->port,
+                                        ext_phy_type,
+                                        ext_phy_addr,
+                                        MDIO_AN_DEVAD,
+                                        MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
+                                        0xf42);
+
+                               /* Get legacy speed operation status */
+                               bnx2x_cl45_read(bp, params->port,
+                                         ext_phy_type,
+                                         ext_phy_addr,
+                                         MDIO_AN_DEVAD,
+                                         MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
+                                         &legacy_status);
+
+                               DP(NETIF_MSG_LINK, "Legacy speed status"
+                                            " = 0x%x\n", legacy_status);
+                               ext_phy_link_up = ((legacy_status & (1<<11))
+                                                  == (1<<11));
+                               if (ext_phy_link_up) {
+                                       legacy_speed = (legacy_status & (3<<9));
+                                       if (legacy_speed == (0<<9))
+                                               vars->line_speed = SPEED_10;
+                                       else if (legacy_speed == (1<<9))
+                                               vars->line_speed =
+                                                       SPEED_100;
+                                       else if (legacy_speed == (2<<9))
+                                               vars->line_speed =
+                                                       SPEED_1000;
+                                       else /* Should not happen */
+                                               vars->line_speed = 0;
+
+                                       if (legacy_status & (1<<8))
+                                               vars->duplex = DUPLEX_FULL;
+                                       else
+                                               vars->duplex = DUPLEX_HALF;
+
+                                       DP(NETIF_MSG_LINK, "Link is up "
+                                                    "in %dMbps, is_duplex_full"
+                                                    "= %d\n",
+                                               vars->line_speed,
+                                               (vars->duplex == DUPLEX_FULL));
+                               }
+                       }
+                       break;
+               default:
+                       DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+                          params->ext_phy_config);
+                       ext_phy_link_up = 0;
+                       break;
+               }
+
+       } else { /* SerDes */
+               ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+                       DP(NETIF_MSG_LINK, "SerDes Direct\n");
+                       ext_phy_link_up = 1;
+                       break;
+
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+                       DP(NETIF_MSG_LINK, "SerDes 5482\n");
+                       ext_phy_link_up = 1;
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK,
+                                "BAD SerDes ext_phy_config 0x%x\n",
+                                params->ext_phy_config);
+                       ext_phy_link_up = 0;
+                       break;
+               }
+       }
+
+       return ext_phy_link_up;
+}
+
+static void bnx2x_link_int_enable(struct link_params *params)
+{
+       u8 port = params->port;
+       u32 ext_phy_type;
+       u32 mask;
+       struct bnx2x *bp = params->bp;
+
+       /* setting the status to report on link up
+          for either XGXS or SerDes */
+
+       if (params->switch_cfg == SWITCH_CFG_10G) {
+               mask = (NIG_MASK_XGXS0_LINK10G |
+                       NIG_MASK_XGXS0_LINK_STATUS);
+               DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
+               ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+               if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+                   (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
+                   (ext_phy_type !=
+                               PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
+                       mask |= NIG_MASK_MI_INT;
+                       DP(NETIF_MSG_LINK, "enabled external phy int\n");
+               }
+
+       } else { /* SerDes */
+               mask = NIG_MASK_SERDES0_LINK_STATUS;
+               DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
+               ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+               if ((ext_phy_type !=
+                               PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
+                   (ext_phy_type !=
+                               PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
+                       mask |= NIG_MASK_MI_INT;
+                       DP(NETIF_MSG_LINK, "enabled external phy int\n");
+               }
+       }
+       bnx2x_bits_en(bp,
+                   NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
+                   mask);
+
+       DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
+                (params->switch_cfg == SWITCH_CFG_10G),
+                REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
+       DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
+                REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
+                REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
+                REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
+       DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
+                REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
+                REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
+}
+
+static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
+                                       u8 is_mi_int)
+{
+       u32 latch_status = 0, is_mi_int_status;
+       /* Disable the MI INT ( external phy int )
+        * by writing 1 to the status register. Link down indication
+        * is high-active-signal, so in this case we need to write the
+        * status to clear the XOR
+        */
+       /* Read Latched signals */
+       latch_status = REG_RD(bp,
+                                 NIG_REG_LATCH_STATUS_0 + port*8);
+       is_mi_int_status = REG_RD(bp,
+                                 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
+       DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
+                    "latch_status = 0x%x\n",
+                is_mi_int, is_mi_int_status, latch_status);
+       /* Handle only those with latched-signal=up.*/
+       if (latch_status & 1) {
+               /* For all latched-signal=up,Write original_signal to status */
+               if (is_mi_int)
+                       bnx2x_bits_en(bp,
+                                   NIG_REG_STATUS_INTERRUPT_PORT0
+                                   + port*4,
+                                   NIG_STATUS_EMAC0_MI_INT);
+               else
+                       bnx2x_bits_dis(bp,
+                                    NIG_REG_STATUS_INTERRUPT_PORT0
+                                    + port*4,
+                                    NIG_STATUS_EMAC0_MI_INT);
+               /* For all latched-signal=up : Re-Arm Latch signals */
+               REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
+                          (latch_status & 0xfffe) | (latch_status & 1));
+       }
+}
+/*
+ * link management
+ */
+static void bnx2x_link_int_ack(struct link_params *params,
+                            struct link_vars *vars, u8 is_10g,
+                            u8 is_mi_int)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+
+       /* first reset all status
+        * we assume only one line will be change at a time */
+       bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
+                    (NIG_STATUS_XGXS0_LINK10G |
+                     NIG_STATUS_XGXS0_LINK_STATUS |
+                     NIG_STATUS_SERDES0_LINK_STATUS));
+       if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
+           == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
+               bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
+       }
+       if (vars->phy_link_up) {
+               if (is_10g) {
+                       /* Disable the 10G link interrupt
+                        * by writing 1 to the status register
+                        */
+                       DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
+                       bnx2x_bits_en(bp,
+                                   NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
+                                   NIG_STATUS_XGXS0_LINK10G);
+
+               } else if (params->switch_cfg == SWITCH_CFG_10G) {
+                       /* Disable the link interrupt
+                        * by writing 1 to the relevant lane
+                        * in the status register
+                        */
+                       u32 ser_lane = ((params->lane_config &
+                                   PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+                                   PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+                       DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
+                                vars->line_speed);
+                       bnx2x_bits_en(bp,
+                                   NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
+                                   ((1 << ser_lane) <<
+                                    NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
+
+               } else { /* SerDes */
+                       DP(NETIF_MSG_LINK, "SerDes phy link up\n");
+                       /* Disable the link interrupt
+                        * by writing 1 to the status register
+                        */
+                       bnx2x_bits_en(bp,
+                                   NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
+                                   NIG_STATUS_SERDES0_LINK_STATUS);
+               }
+
+       } else { /* link_down */
+       }
+}
+
+static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
+{
+       u8 *str_ptr = str;
+       u32 mask = 0xf0000000;
+       u8 shift = 8*4;
+       u8 digit;
+       if (len < 10) {
+               /* Need more then 10chars for this format */
+               *str_ptr = '\0';
+               return -EINVAL;
+       }
+       while (shift > 0) {
+
+               shift -= 4;
+               digit = ((num & mask) >> shift);
+               if (digit < 0xa)
+                       *str_ptr = digit + '0';
+               else
+                       *str_ptr = digit - 0xa + 'a';
+               str_ptr++;
+               mask = mask >> 4;
+               if (shift == 4*4) {
+                       *str_ptr = ':';
+                       str_ptr++;
+               }
+       }
+       *str_ptr = '\0';
+       return 0;
+}
+
+static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
+                          u32 ext_phy_type)
+{
+       u32 cnt = 0;
+       u16 ctrl = 0;
+
+       /* Enable EMAC0 in to enable MDIO */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+              (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+       msleep(5);
+
+       /* take ext phy out of reset */
+       bnx2x_set_gpio(bp,
+                         MISC_REGISTERS_GPIO_2,
+                         MISC_REGISTERS_GPIO_HIGH,
+                         port);
+
+       bnx2x_set_gpio(bp,
+                         MISC_REGISTERS_GPIO_1,
+                         MISC_REGISTERS_GPIO_HIGH,
+                         port);
+
+       /* wait for 5ms */
+       msleep(5);
+
+       for (cnt = 0; cnt < 1000; cnt++) {
+               msleep(1);
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_CTRL,
+                             &ctrl);
+               if (!(ctrl & (1<<15))) {
+                       DP(NETIF_MSG_LINK, "Reset completed\n\n");
+                               break;
+               }
+       }
+}
+
+static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
+{
+       /* put sf to reset */
+       bnx2x_set_gpio(bp,
+                         MISC_REGISTERS_GPIO_1,
+                         MISC_REGISTERS_GPIO_LOW,
+                         port);
+       bnx2x_set_gpio(bp,
+                         MISC_REGISTERS_GPIO_2,
+                         MISC_REGISTERS_GPIO_LOW,
+                         port);
+}
+
+u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
+                             u8 *version, u16 len)
+{
+       struct bnx2x *bp = params->bp;
+       u32 ext_phy_type = 0;
+       u32 spirom_ver = 0;
+       u8 status = 0;
+
+       if (version == NULL || params == NULL)
+               return -EINVAL;
+
+       spirom_ver = REG_RD(bp, params->shmem_base +
+                  offsetof(struct shmem_region,
+                           port_mb[params->port].ext_phy_fw_version));
+
+       /* reset the returned value to zero */
+       ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+       switch (ext_phy_type) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+
+               if (len < 5)
+                       return -EINVAL;
+
+               version[0] = (spirom_ver & 0xFF);
+               version[1] = (spirom_ver & 0xFF00) >> 8;
+               version[2] = (spirom_ver & 0xFF0000) >> 16;
+               version[3] = (spirom_ver & 0xFF000000) >> 24;
+               version[4] = '\0';
+
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               status = bnx2x_format_ver(spirom_ver, version, len);
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+               spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
+                       (spirom_ver & 0x7F);
+               status = bnx2x_format_ver(spirom_ver, version, len);
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+               break;
+
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+               DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
+                                   " type is FAILURE!\n");
+               status = -EINVAL;
+               break;
+
+       default:
+               break;
+       }
+       return status;
+}
+
+static void bnx2x_set_xgxs_loopback(struct link_params *params,
+                                 struct link_vars *vars,
+                                 u8 is_10g)
+{
+       u8 port = params->port;
+       struct bnx2x *bp = params->bp;
+
+       if (is_10g) {
+               u32 md_devad;
+
+               DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
+
+               /* change the uni_phy_addr in the nig */
+               md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
+                                         port*0x18));
+
+               REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
+
+               bnx2x_cl45_write(bp, port, 0,
+                              params->phy_addr,
+                              5,
+                              (MDIO_REG_BANK_AER_BLOCK +
+                               (MDIO_AER_BLOCK_AER_REG & 0xf)),
+                              0x2800);
+
+               bnx2x_cl45_write(bp, port, 0,
+                              params->phy_addr,
+                              5,
+                              (MDIO_REG_BANK_CL73_IEEEB0 +
+                               (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
+                              0x6041);
+               msleep(200);
+               /* set aer mmd back */
+               bnx2x_set_aer_mmd(params, vars);
+
+               /* and md_devad */
+               REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
+                           md_devad);
+
+       } else {
+               u16 mii_control;
+
+               DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
+
+               CL45_RD_OVER_CL22(bp, port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_MII_CONTROL,
+                                     &mii_control);
+
+               CL45_WR_OVER_CL22(bp, port,
+                                     params->phy_addr,
+                                     MDIO_REG_BANK_COMBO_IEEE0,
+                                     MDIO_COMBO_IEEE0_MII_CONTROL,
+                                     (mii_control |
+                                      MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
+       }
+}
+
+
+static void bnx2x_ext_phy_loopback(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 ext_phy_addr;
+       u32 ext_phy_type;
+
+       if (params->switch_cfg == SWITCH_CFG_10G) {
+               ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+               ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+               /* CL37 Autoneg Enabled */
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
+                       DP(NETIF_MSG_LINK,
+                               "ext_phy_loopback: We should not get here\n");
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+                       DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+                       DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+                       DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
+                       bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_CTRL,
+                                      0x0001);
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+                       /* SFX7101_XGXS_TEST1 */
+                       bnx2x_cl45_write(bp, params->port, ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_XS_DEVAD,
+                                      MDIO_XS_SFX7101_XGXS_TEST1,
+                                      0x100);
+                       DP(NETIF_MSG_LINK,
+                               "ext_phy_loopback: set ext phy loopback\n");
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+
+                       break;
+               } /* switch external PHY type */
+       } else {
+               /* serdes */
+               ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+               ext_phy_addr = (params->ext_phy_config  &
+               PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
+               >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
+       }
+}
+
+
+/*
+ *------------------------------------------------------------------------
+ * bnx2x_override_led_value -
+ *
+ * Override the led value of the requsted led
+ *
+ *------------------------------------------------------------------------
+ */
+u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
+                         u32 led_idx, u32 value)
+{
+       u32 reg_val;
+
+       /* If port 0 then use EMAC0, else use EMAC1*/
+       u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+       DP(NETIF_MSG_LINK,
+                "bnx2x_override_led_value() port %x led_idx %d value %d\n",
+                port, led_idx, value);
+
+       switch (led_idx) {
+       case 0: /* 10MB led */
+               /* Read the current value of the LED register in
+               the EMAC block */
+               reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
+               /* Set the OVERRIDE bit to 1 */
+               reg_val |= EMAC_LED_OVERRIDE;
+               /* If value is 1, set the 10M_OVERRIDE bit,
+               otherwise reset it.*/
+               reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
+                       (reg_val & ~EMAC_LED_10MB_OVERRIDE);
+               REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
+               break;
+       case 1: /*100MB led    */
+               /*Read the current value of the LED register in
+               the EMAC block */
+               reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
+               /*  Set the OVERRIDE bit to 1 */
+               reg_val |= EMAC_LED_OVERRIDE;
+               /*  If value is 1, set the 100M_OVERRIDE bit,
+               otherwise reset it.*/
+               reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
+                       (reg_val & ~EMAC_LED_100MB_OVERRIDE);
+               REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
+               break;
+       case 2: /* 1000MB led */
+               /* Read the current value of the LED register in the
+               EMAC block */
+               reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
+               /* Set the OVERRIDE bit to 1 */
+               reg_val |= EMAC_LED_OVERRIDE;
+               /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
+               reset it. */
+               reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
+                       (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
+               REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
+               break;
+       case 3: /* 2500MB led */
+               /*  Read the current value of the LED register in the
+               EMAC block*/
+               reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
+               /* Set the OVERRIDE bit to 1 */
+               reg_val |= EMAC_LED_OVERRIDE;
+               /*  If value is 1, set the 2500M_OVERRIDE bit, otherwise
+               reset it.*/
+               reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
+                       (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
+               REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
+               break;
+       case 4: /*10G led */
+               if (port == 0) {
+                       REG_WR(bp, NIG_REG_LED_10G_P0,
+                                   value);
+               } else {
+                       REG_WR(bp, NIG_REG_LED_10G_P1,
+                                   value);
+               }
+               break;
+       case 5: /* TRAFFIC led */
+               /* Find if the traffic control is via BMAC or EMAC */
+               if (port == 0)
+                       reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
+               else
+                       reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
+
+               /*  Override the traffic led in the EMAC:*/
+               if (reg_val == 1) {
+                       /* Read the current value of the LED register in
+                       the EMAC block */
+                       reg_val = REG_RD(bp, emac_base +
+                                            EMAC_REG_EMAC_LED);
+                       /* Set the TRAFFIC_OVERRIDE bit to 1 */
+                       reg_val |= EMAC_LED_OVERRIDE;
+                       /* If value is 1, set the TRAFFIC bit, otherwise
+                       reset it.*/
+                       reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
+                               (reg_val & ~EMAC_LED_TRAFFIC);
+                       REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
+               } else { /* Override the traffic led in the BMAC: */
+                       REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+                                  + port*4, 1);
+                       REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
+                                   value);
+               }
+               break;
+       default:
+               DP(NETIF_MSG_LINK,
+                        "bnx2x_override_led_value() unknown led index %d "
+                        "(should be 0-5)\n", led_idx);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+
+u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
+              u16 hw_led_mode, u32 chip_id)
+{
+       u8 rc = 0;
+       u32 tmp;
+       u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+       DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
+       DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
+                speed, hw_led_mode);
+       switch (mode) {
+       case LED_MODE_OFF:
+               REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
+               REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
+                          SHARED_HW_CFG_LED_MAC1);
+
+               tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
+               EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
+               break;
+
+       case LED_MODE_OPER:
+               REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
+               REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
+                          port*4, 0);
+               /* Set blinking rate to ~15.9Hz */
+               REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
+                          LED_BLINK_RATE_VAL);
+               REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
+                          port*4, 1);
+               tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
+               EMAC_WR(bp, EMAC_REG_EMAC_LED,
+                           (tmp & (~EMAC_LED_OVERRIDE)));
+
+               if (CHIP_IS_E1(bp) &&
+                   ((speed == SPEED_2500) ||
+                    (speed == SPEED_1000) ||
+                    (speed == SPEED_100) ||
+                    (speed == SPEED_10))) {
+                       /* On Everest 1 Ax chip versions for speeds less than
+                       10G LED scheme is different */
+                       REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+                                  + port*4, 1);
+                       REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
+                                  port*4, 0);
+                       REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
+                                  port*4, 1);
+               }
+               break;
+
+       default:
+               rc = -EINVAL;
+               DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
+                        mode);
+               break;
+       }
+       return rc;
+
+}
+
+u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u16 gp_status = 0;
+
+       CL45_RD_OVER_CL22(bp, params->port,
+                             params->phy_addr,
+                             MDIO_REG_BANK_GP_STATUS,
+                             MDIO_GP_STATUS_TOP_AN_STATUS1,
+                             &gp_status);
+       /* link is up only if both local phy and external phy are up */
+       if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
+           bnx2x_ext_phy_is_link_up(params, vars))
+               return 0;
+
+       return -ESRCH;
+}
+
+static u8 bnx2x_link_initialize(struct link_params *params,
+                             struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 rc = 0;
+       u8 non_ext_phy;
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       /* Activate the external PHY */
+       bnx2x_ext_phy_reset(params, vars);
+
+       bnx2x_set_aer_mmd(params, vars);
+
+       if (vars->phy_flags & PHY_XGXS_FLAG)
+               bnx2x_set_master_ln(params);
+
+       rc = bnx2x_reset_unicore(params);
+       /* reset the SerDes and wait for reset bit return low */
+       if (rc != 0)
+               return rc;
+
+       bnx2x_set_aer_mmd(params, vars);
+
+       /* setting the masterLn_def again after the reset */
+       if (vars->phy_flags & PHY_XGXS_FLAG) {
+               bnx2x_set_master_ln(params);
+               bnx2x_set_swap_lanes(params);
+       }
+
+       if (vars->phy_flags & PHY_XGXS_FLAG) {
+               if ((params->req_line_speed &&
+                   ((params->req_line_speed == SPEED_100) ||
+                    (params->req_line_speed == SPEED_10))) ||
+                   (!params->req_line_speed &&
+                    (params->speed_cap_mask >=
+                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
+                    (params->speed_cap_mask <
+                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
+                    ))  {
+                       vars->phy_flags |= PHY_SGMII_FLAG;
+               } else {
+                       vars->phy_flags &= ~PHY_SGMII_FLAG;
+               }
+       }
+       /* In case of external phy existance, the line speed would be the
+        line speed linked up by the external phy. In case it is direct only,
+         then the line_speed during initialization will be equal to the
+          req_line_speed*/
+       vars->line_speed = params->req_line_speed;
+
+       bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
+
+       /* init ext phy and enable link state int */
+       non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
+                      (params->loopback_mode == LOOPBACK_XGXS_10));
+
+       if (non_ext_phy ||
+           (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
+           (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
+           (params->loopback_mode == LOOPBACK_EXT_PHY)) {
+               if (params->req_line_speed == SPEED_AUTO_NEG)
+                       bnx2x_set_parallel_detection(params, vars->phy_flags);
+               bnx2x_init_internal_phy(params, vars, 0);
+       }
+
+       if (!non_ext_phy)
+               rc |= bnx2x_ext_phy_init(params, vars);
+
+       bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
+                    (NIG_STATUS_XGXS0_LINK10G |
+                     NIG_STATUS_XGXS0_LINK_STATUS |
+                     NIG_STATUS_SERDES0_LINK_STATUS));
+
+       return rc;
+
+}
+
+
+u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u32 val;
+
+       DP(NETIF_MSG_LINK, "Phy Initialization started\n");
+       DP(NETIF_MSG_LINK, "req_speed %d, req_flowctrl %d\n",
+                params->req_line_speed, params->req_flow_ctrl);
+       vars->link_status = 0;
+       vars->phy_link_up = 0;
+       vars->link_up = 0;
+       vars->line_speed = 0;
+       vars->duplex = DUPLEX_FULL;
+       vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+       vars->mac_type = MAC_TYPE_NONE;
+
+       if (params->switch_cfg ==  SWITCH_CFG_1G)
+               vars->phy_flags = PHY_SERDES_FLAG;
+       else
+               vars->phy_flags = PHY_XGXS_FLAG;
+
+       /* disable attentions */
+       bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
+                      (NIG_MASK_XGXS0_LINK_STATUS |
+                       NIG_MASK_XGXS0_LINK10G |
+                       NIG_MASK_SERDES0_LINK_STATUS |
+                       NIG_MASK_MI_INT));
+
+       bnx2x_emac_init(params, vars);
+
+       if (CHIP_REV_IS_FPGA(bp)) {
+
+               vars->link_up = 1;
+               vars->line_speed = SPEED_10000;
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+               vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
+               /* enable on E1.5 FPGA */
+               if (!CHIP_IS_E1(bp)) {
+                       vars->flow_ctrl |=
+                                       (BNX2X_FLOW_CTRL_TX |
+                                        BNX2X_FLOW_CTRL_RX);
+                       vars->link_status |=
+                                       (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
+                                        LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
+               }
+
+               bnx2x_emac_enable(params, vars, 0);
+               if (!(CHIP_IS_E2_NOT_PHASE0(params->chip_id)))
+                       bnx2x_pbf_update(params, vars->flow_ctrl,
+                                      vars->line_speed);
+               /* disable drain */
+               REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
+
+               /* update shared memory */
+               bnx2x_update_mng(params, vars->link_status);
+
+               return 0;
+
+       } else
+       if (CHIP_REV_IS_EMUL(bp)) {
+
+               vars->link_up = 1;
+               vars->line_speed = SPEED_10000;
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+               vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
+
+               bnx2x_bmac_enable(params, vars, 0);
+
+               if (!(CHIP_IS_E2_NOT_PHASE0(params->chip_id)))
+                       bnx2x_pbf_update(params, vars->flow_ctrl,
+                                      vars->line_speed);
+               /* Disable drain */
+               REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
+                                   + params->port*4, 0);
+
+               /* update shared memory */
+               bnx2x_update_mng(params, vars->link_status);
+
+               return 0;
+
+       } else
+       if (params->loopback_mode == LOOPBACK_BMAC) {
+
+               vars->link_up = 1;
+               vars->line_speed = SPEED_10000;
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+               vars->mac_type = MAC_TYPE_BMAC;
+
+               vars->phy_flags = PHY_XGXS_FLAG;
+
+               bnx2x_phy_deassert(params, vars->phy_flags);
+               /* set bmac loopback */
+               bnx2x_bmac_enable(params, vars, 1);
+
+               REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
+                          params->port*4, 0);
+
+       } else if (params->loopback_mode == LOOPBACK_EMAC) {
+
+               vars->link_up = 1;
+               vars->line_speed = SPEED_1000;
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+               vars->mac_type = MAC_TYPE_EMAC;
+
+               vars->phy_flags = PHY_XGXS_FLAG;
+
+               bnx2x_phy_deassert(params, vars->phy_flags);
+               /* set bmac loopback */
+               bnx2x_emac_enable(params, vars, 1);
+               bnx2x_emac_program(params, vars->line_speed,
+                                             vars->duplex);
+               REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
+                          params->port*4, 0);
+
+       } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
+                  (params->loopback_mode == LOOPBACK_EXT_PHY)) {
+
+               vars->link_up = 1;
+               vars->line_speed = SPEED_10000;
+               vars->duplex = DUPLEX_FULL;
+               vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+
+               vars->phy_flags = PHY_XGXS_FLAG;
+
+               val = REG_RD(bp,
+                                NIG_REG_XGXS0_CTRL_PHY_ADDR+
+                                params->port*0x18);
+               params->phy_addr = (u8)val;
+
+               bnx2x_phy_deassert(params, vars->phy_flags);
+               bnx2x_link_initialize(params, vars);
+
+               vars->mac_type = MAC_TYPE_BMAC;
+
+               bnx2x_bmac_enable(params, vars, 0);
+
+               if (params->loopback_mode == LOOPBACK_XGXS_10) {
+                       /* set 10G XGXS loopback */
+                       bnx2x_set_xgxs_loopback(params, vars, 1);
+               } else {
+                       /* set external phy loopback */
+                       bnx2x_ext_phy_loopback(params);
+               }
+               REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
+                           params->port*4, 0);
+
+               bnx2x_set_led(bp, params->port, LED_MODE_OPER,
+                           vars->line_speed, params->hw_led_mode,
+                           params->chip_id);
+
+       } else
+       /* No loopback */
+       {
+               bnx2x_phy_deassert(params, vars->phy_flags);
+               switch (params->switch_cfg) {
+               case SWITCH_CFG_1G:
+                       vars->phy_flags |= PHY_SERDES_FLAG;
+                       if ((params->ext_phy_config &
+                            PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
+                            PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
+                               vars->phy_flags |= PHY_SGMII_FLAG;
+                       }
+
+                       val = REG_RD(bp,
+                                        NIG_REG_SERDES0_CTRL_PHY_ADDR+
+                                        params->port*0x10);
+
+                       params->phy_addr = (u8)val;
+
+                       break;
+               case SWITCH_CFG_10G:
+                       vars->phy_flags |= PHY_XGXS_FLAG;
+                       val = REG_RD(bp,
+                                NIG_REG_XGXS0_CTRL_PHY_ADDR+
+                                params->port*0x18);
+                       params->phy_addr = (u8)val;
+
+                       break;
+               default:
+                       DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
+                       return -EINVAL;
+               }
+               DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
+
+               bnx2x_link_initialize(params, vars);
+               msleep(30);
+               bnx2x_link_int_enable(params);
+       }
+       return 0;
+}
+
+static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
+{
+       DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
+
+       /* Set serial boot control for external load */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_GEN_CTRL, 0x0001);
+}
+
+u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
+                 u8 reset_ext_phy)
+{
+       struct bnx2x *bp = params->bp;
+       u32 ext_phy_config = params->ext_phy_config;
+       u16 hw_led_mode = params->hw_led_mode;
+       u32 chip_id = params->chip_id;
+       u8 port = params->port;
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
+       u32 val = REG_RD(bp, params->shmem_base +
+                            offsetof(struct shmem_region, dev_info.
+                                     port_feature_config[params->port].
+                                     config));
+
+       /* disable attentions */
+       vars->link_status = 0;
+       bnx2x_update_mng(params, vars->link_status);
+       bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
+                    (NIG_MASK_XGXS0_LINK_STATUS |
+                     NIG_MASK_XGXS0_LINK10G |
+                     NIG_MASK_SERDES0_LINK_STATUS |
+                     NIG_MASK_MI_INT));
+
+       /* activate nig drain */
+       REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
+
+       /* disable nig egress interface */
+       REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
+       REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
+
+       /* Stop BigMac rx */
+       bnx2x_bmac_rx_disable(bp, params->chip_id, port);
+
+       /* disable emac */
+       REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
+
+       msleep(10);
+       /* The PHY reset is controled by GPIO 1
+        * Hold it as vars low
+        */
+        /* clear link led */
+       bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
+       if (reset_ext_phy) {
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               {
+
+                       /* Disable Transmitter */
+                       u8 ext_phy_addr =
+                               XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+                       if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+                           PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+                               bnx2x_sfp_set_transmitter(bp, port,
+                                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                                       ext_phy_addr, 0);
+                       break;
+               }
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+                       DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
+                                "low power mode\n",
+                                port);
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_LOW,
+                                         port);
+                       break;
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               {
+                       u8 ext_phy_addr =
+                               XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+                       /* Set soft reset */
+                       bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
+                       break;
+               }
+               default:
+                       /* HW reset */
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                                         MISC_REGISTERS_GPIO_OUTPUT_LOW,
+                                         port);
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                         MISC_REGISTERS_GPIO_OUTPUT_LOW,
+                                         port);
+                       DP(NETIF_MSG_LINK, "reset external PHY\n");
+               }
+       }
+       /* reset the SerDes/XGXS */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
+              (0x1ff << (port*16)));
+
+       /* reset BigMac */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+              (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+       /* disable nig ingress interface */
+       REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
+       REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
+       REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
+       REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
+       vars->link_up = 0;
+       return 0;
+}
+
+static u8 bnx2x_update_link_down(struct link_params *params,
+                              struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+
+       DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
+       bnx2x_set_led(bp, port, LED_MODE_OFF,
+                   0, params->hw_led_mode,
+                   params->chip_id);
+
+       /* indicate no mac active */
+       vars->mac_type = MAC_TYPE_NONE;
+
+       /* update shared memory */
+       vars->link_status = 0;
+       vars->line_speed = 0;
+       bnx2x_update_mng(params, vars->link_status);
+
+       /* activate nig drain */
+       REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
+
+       /* disable emac */
+       REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
+
+       msleep(10);
+
+       /* reset BigMac */
+       bnx2x_bmac_rx_disable(bp, params->chip_id, params->port);
+       REG_WR(bp, GRCBASE_MISC +
+                  MISC_REGISTERS_RESET_REG_2_CLEAR,
+                  (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+       return 0;
+}
+
+static u8 bnx2x_update_link_up(struct link_params *params,
+                            struct link_vars *vars,
+                            u8 link_10g, u32 gp_status)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 rc = 0;
+
+       vars->link_status |= LINK_STATUS_LINK_UP;
+       if (link_10g) {
+               bnx2x_bmac_enable(params, vars, 0);
+               bnx2x_set_led(bp, port, LED_MODE_OPER,
+                           SPEED_10000, params->hw_led_mode,
+                           params->chip_id);
+
+       } else {
+               bnx2x_emac_enable(params, vars, 0);
+               rc = bnx2x_emac_program(params, vars->line_speed,
+                                     vars->duplex);
+
+               /* AN complete? */
+               if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+                       if (!(vars->phy_flags &
+                             PHY_SGMII_FLAG))
+                               bnx2x_set_gmii_tx_driver(params);
+               }
+       }
+
+       /* PBF - link up */
+       if (!(CHIP_IS_E2_NOT_PHASE0(params->chip_id)))
+               rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
+                                    vars->line_speed);
+
+       /* disable drain */
+       REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
+
+       /* update shared memory */
+       bnx2x_update_mng(params, vars->link_status);
+       msleep(20);
+       return rc;
+}
+/* This function should called upon link interrupt */
+/* In case vars->link_up, driver needs to
+       1. Update the pbf
+       2. Disable drain
+       3. Update the shared memory
+       4. Indicate link up
+       5. Set LEDs
+   Otherwise,
+       1. Update shared memory
+       2. Reset BigMac
+       3. Report link down
+       4. Unset LEDs
+*/
+u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u16 gp_status;
+       u8 link_10g;
+       u8 ext_phy_link_up, rc = 0;
+       u32 ext_phy_type;
+       u8 is_mi_int = 0;
+
+       DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
+                port, (vars->phy_flags & PHY_XGXS_FLAG),
+                REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
+
+       is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
+                                   port*0x18) > 0);
+       DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
+                REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
+                is_mi_int,
+                REG_RD(bp,
+                           NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
+
+       DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
+                REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
+                REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
+
+       /* disable emac */
+       REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
+
+       ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+       /* Check external link change only for non-direct */
+       ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars);
+
+       /* Read gp_status */
+       CL45_RD_OVER_CL22(bp, port, params->phy_addr,
+                             MDIO_REG_BANK_GP_STATUS,
+                             MDIO_GP_STATUS_TOP_AN_STATUS1,
+                             &gp_status);
+
+       rc = bnx2x_link_settings_status(params, vars, gp_status);
+       if (rc != 0)
+               return rc;
+
+       /* anything 10 and over uses the bmac */
+       link_10g = ((vars->line_speed == SPEED_10000) ||
+                   (vars->line_speed == SPEED_12000) ||
+                   (vars->line_speed == SPEED_12500) ||
+                   (vars->line_speed == SPEED_13000) ||
+                   (vars->line_speed == SPEED_15000) ||
+                   (vars->line_speed == SPEED_16000));
+
+       bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
+
+       /* In case external phy link is up, and internal link is down
+       ( not initialized yet probably after link initialization, it needs
+       to be initialized.
+       Note that after link down-up as result of cable plug,
+       the xgxs link would probably become up again without the need to
+       initialize it*/
+
+       if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
+           (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
+           (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
+           (ext_phy_link_up && !vars->phy_link_up)) {
+               if (vars->line_speed < SPEED_1000)
+                       vars->phy_flags |= PHY_SGMII_FLAG;
+               else
+                       vars->phy_flags &= ~PHY_SGMII_FLAG;
+               bnx2x_init_internal_phy(params, vars, 0);
+       }
+
+       /* link is up only if both local phy and external phy are up */
+       vars->link_up = (ext_phy_link_up && vars->phy_link_up);
+
+       if (vars->link_up)
+               rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
+       else
+               rc = bnx2x_update_link_down(params, vars);
+
+       return rc;
+}
+
+static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
+{
+       u8 ext_phy_addr[PORT_MAX];
+       u16 val;
+       s8 port;
+
+       /* PART1 - Reset both phys */
+       for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+               /* Extract the ext phy address for the port */
+               u32 ext_phy_config = REG_RD(bp, shmem_base +
+                                       offsetof(struct shmem_region,
+                  dev_info.port_hw_config[port].external_phy_config));
+
+               /* disable attentions */
+               bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
+                            (NIG_MASK_XGXS0_LINK_STATUS |
+                             NIG_MASK_XGXS0_LINK10G |
+                             NIG_MASK_SERDES0_LINK_STATUS |
+                             NIG_MASK_MI_INT));
+
+               ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
+
+               /* Need to take the phy out of low power mode in order
+                       to write to access its registers */
+               bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+
+               /* Reset the phy */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                              ext_phy_addr[port],
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_CTRL,
+                              1<<15);
+       }
+
+       /* Add delay of 150ms after reset */
+       msleep(150);
+
+       /* PART2 - Download firmware to both phys */
+       for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+               u16 fw_ver1;
+
+               bnx2x_bcm8073_external_rom_boot(bp, port,
+                                             ext_phy_addr[port], shmem_base);
+
+               bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                             ext_phy_addr[port],
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_ROM_VER1, &fw_ver1);
+               if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
+                       DP(NETIF_MSG_LINK,
+                                "bnx2x_8073_common_init_phy port %x:"
+                                "Download failed. fw version = 0x%x\n",
+                                port, fw_ver1);
+                       return -EINVAL;
+               }
+
+               /* Only set bit 10 = 1 (Tx power down) */
+               bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                             ext_phy_addr[port],
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_TX_POWER_DOWN, &val);
+
+               /* Phase1 of TX_POWER_DOWN reset */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                              ext_phy_addr[port],
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_TX_POWER_DOWN,
+                              (val | 1<<10));
+       }
+
+       /* Toggle Transmitter: Power down and then up with 600ms
+          delay between */
+       msleep(600);
+
+       /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
+       for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+               /* Phase2 of POWER_DOWN_RESET */
+               /* Release bit 10 (Release Tx power down) */
+               bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                             ext_phy_addr[port],
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_TX_POWER_DOWN, &val);
+
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                              ext_phy_addr[port],
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
+               msleep(15);
+
+               /* Read modify write the SPI-ROM version select register */
+               bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                             ext_phy_addr[port],
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_EDC_FFE_MAIN, &val);
+               bnx2x_cl45_write(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                              ext_phy_addr[port],
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
+
+               /* set GPIO2 back to LOW */
+               bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+       }
+       return 0;
+
+}
+
+static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
+{
+       u8 ext_phy_addr[PORT_MAX];
+       s8 port;
+       u32 swap_val, swap_override;
+       DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
+       swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
+       swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
+
+       bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
+       msleep(5);
+
+       /* PART1 - Reset both phys */
+       for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+               /* Extract the ext phy address for the port */
+               u32 ext_phy_config = REG_RD(bp, shmem_base +
+                                       offsetof(struct shmem_region,
+                  dev_info.port_hw_config[port].external_phy_config));
+
+               /* disable attentions */
+               bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
+                            (NIG_MASK_XGXS0_LINK_STATUS |
+                             NIG_MASK_XGXS0_LINK10G |
+                             NIG_MASK_SERDES0_LINK_STATUS |
+                             NIG_MASK_MI_INT));
+
+               ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
+
+               /* Reset the phy */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                              ext_phy_addr[port],
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_CTRL,
+                              1<<15);
+       }
+
+       /* Add delay of 150ms after reset */
+       msleep(150);
+
+       /* PART2 - Download firmware to both phys */
+       for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+               u16 fw_ver1;
+
+               bnx2x_bcm8727_external_rom_boot(bp, port,
+                                             ext_phy_addr[port], shmem_base);
+
+               bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+                             ext_phy_addr[port],
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_ROM_VER1, &fw_ver1);
+               if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
+                       DP(NETIF_MSG_LINK,
+                                "bnx2x_8073_common_init_phy port %x:"
+                                "Download failed. fw version = 0x%x\n",
+                                port, fw_ver1);
+                       return -EINVAL;
+               }
+
+       }
+
+
+
+       return 0;
+}
+
+
+static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
+{
+       u8 ext_phy_addr;
+       u32 val;
+       s8 port;
+
+       /* Use port1 because of the static port-swap */
+       /* Enable the module detection interrupt */
+       val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
+       val |= ((1<<MISC_REGISTERS_GPIO_3)|
+               (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
+       REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
+
+       bnx2x_ext_phy_hw_reset(bp, 1);
+       msleep(5);
+       for (port = 0; port < PORT_MAX; port++) {
+               /* Extract the ext phy address for the port */
+               u32 ext_phy_config = REG_RD(bp, shmem_base +
+                                       offsetof(struct shmem_region,
+                       dev_info.port_hw_config[port].external_phy_config));
+
+               ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
+               DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
+                        ext_phy_addr);
+
+               bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
+
+               /* Set fault module detected LED on */
+               bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                                 MISC_REGISTERS_GPIO_HIGH,
+                                 port);
+       }
+
+       return 0;
+}
+
+u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
+{
+       u8 rc = 0;
+       u32 ext_phy_type;
+
+       DP(NETIF_MSG_LINK, "Begin common phy init\n");
+
+       /* Read the ext_phy_type for arbitrary port(0) */
+       ext_phy_type = XGXS_EXT_PHY_TYPE(
+                       REG_RD(bp, shmem_base +
+                          offsetof(struct shmem_region,
+                            dev_info.port_hw_config[0].external_phy_config)));
+
+       switch (ext_phy_type) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+       {
+               rc = bnx2x_8073_common_init_phy(bp, shmem_base);
+               break;
+       }
+
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
+               rc = bnx2x_8727_common_init_phy(bp, shmem_base);
+               break;
+
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               /* GPIO1 affects both ports, so there's need to pull
+               it for single port alone */
+               rc = bnx2x_8726_common_init_phy(bp, shmem_base);
+
+               break;
+       default:
+               DP(NETIF_MSG_LINK,
+                        "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
+                        ext_phy_type);
+               break;
+       }
+
+       return rc;
+}
+
+static u8 bnx2x_verify_image_header(struct bnx2x *bp,
+                                 struct bnx2x_image_header *header,
+                                 u32 ext_phy_type) {
+       u32 image_hdr_type;
+
+       switch (ext_phy_type) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               image_hdr_type = IMAGE_HDR_TYPE_BCM8726; break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               image_hdr_type = IMAGE_HDR_TYPE_BCM8727; break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+               image_hdr_type = IMAGE_HDR_TYPE_BCM8073; break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+               image_hdr_type = IMAGE_HDR_TYPE_BCM8481; break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+               image_hdr_type = IMAGE_HDR_TYPE_SFX7101; break;
+       default:
+               DP(NETIF_MSG_LINK, "Invalid phy type 0x%x for header"
+                            " verification\n", ext_phy_type);
+               return -EINVAL;
+       }
+
+       DP(NETIF_MSG_LINK, "Image Header: type = 0x%x, image_info = 0x%x,"
+                " byte_cnt = 0x%x\n", header->type, header->image_info,
+                header->byte_cnt);
+
+       if ((header->magic != FILE_MAGIC) ||
+           (header->version != FORMAT_VERSION_2) ||
+           (header->type != image_hdr_type)) {
+               DP(NETIF_MSG_LINK, "Invalid image header: Magic = 0x%x,"
+                        " version = 0x%x, phy_type = 0x%x\n",
+                        header->magic, header->version, header->type);
+               return -EINVAL;
+       }
+       return 0;
+}
+
+void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
+{
+       u16 val, cnt;
+
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                     phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_7101_RESET, &val);
+
+       for (cnt = 0; cnt < 10; cnt++) {
+               msleep(50);
+               /* Writes a self-clearing reset */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              phy_addr,
+                              MDIO_PMA_DEVAD,
+                              MDIO_PMA_REG_7101_RESET,
+                              (val | (1<<15)));
+               /* Wait for clear */
+               bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                             phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_7101_RESET, &val);
+
+               if ((val & (1<<15)) == 0)
+                       break;
+       }
+}
+
+#define RESERVED_SIZE 256
+/* max application is 160K bytes - data at end of RAM */
+#define MAX_APP_SIZE (160*1024 - RESERVED_SIZE)
+
+/* Header is 14 bytes */
+#define HEADER_SIZE 14
+#define DATA_OFFSET HEADER_SIZE
+
+#define SPI_START_TRANSFER(bp, port, ext_phy_addr) \
+       bnx2x_cl45_write(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, \
+                       ext_phy_addr, \
+                       MDIO_PCS_DEVAD, \
+                       MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1)
+
+/************************************************************************/
+/*   Function: bnx2x_bcm_flash_download                                */
+/*   Description   : Load SPI EEPROM through BCM8073.                  */
+/*                                                                     */
+/************************************************************************/
+
+#define WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wrdata, rddata) \
+       {if (write_message_bcm(bp, port, ext_phy_addr, \
+               ext_phy_type, wrdata, rddata) != 0) \
+               return -EINVAL; }
+
+static u8 write_message_bcm(struct bnx2x *bp, u8 port,
+                       u8 ext_phy_addr, u32 ext_phy_type,
+                       u16 wrdata, u16 *rddata)
+{
+       u16 tmp_data = 0;
+       u16 i = 0;
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp_data);
+
+       /* Write SPI Control Register Write Command.*/
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_M8051_MSGIN_REG, wrdata);
+
+       /* Wait For LASI To be asserted when M8051 writes Next Parameter To
+       MSG_OUT Register TBD  wait (xlasi_ch1 === 1'b0);
+       Above wait can also be done by polling 9005, bit 2 As bellow. */
+
+       for (i = 0; i < UPGRADE_TIMEOUT_BCM; i++) {
+               bnx2x_cl45_read(bp, port,
+                             ext_phy_type,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD,
+                             MDIO_PMA_REG_LASI_STATUS, &tmp_data);
+               if ((tmp_data & (1<<2)) != 0) {/* bit 2 is Rx Alarm for LASI.*/
+                       break;
+               }
+               msleep(6);
+       }
+
+       if (i == UPGRADE_TIMEOUT_BCM) {
+               DP(NETIF_MSG_LINK, "Failed to get LASI indication. Aborting\n");
+               return -EINVAL;
+       }
+
+       /* Read Message out register. 1.CA13 */
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp_data);
+       *rddata = tmp_data;
+
+       /* Clear LASI Message Out Status. 1.9003*/
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_RX_ALARM, &tmp_data);
+       return 0;
+}
+
+
+static u8 bnx2x_phy_bcm_rom_wait(struct bnx2x *bp, u8 port,
+                              u8 ext_phy_addr, u32 ext_phy_type)
+{
+       /* Wait For WRSR Command To be written.*/
+       u8 spi_ready = 0, count;
+
+       u16 rd_data = 0, wr_data = 0 ;
+       u16 retry_count = 0;
+       while ((rd_data & 0x0100) == 0 && (++retry_count < 1000)) {
+               /* Write SPI Control Register Read Command.*/
+               count = 1;
+               wr_data = ((RD_CPU_CTRL_REGS * 0x0100) | count);
+               count = 2;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Address.*/
+               wr_data = SPI_CTRL_1_L;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+       }
+       if (retry_count == 1000) {
+               DP(NETIF_MSG_LINK,
+                       "Failed writing SPI Write SPI Control Register\n");
+               return -EINVAL;
+       }
+       DP(NETIF_MSG_LINK, "SPI Controller Wrote WRSR Command.\n"
+                   " Checking SPI Status Now ");
+       spi_ready = 1;
+       retry_count = 0;
+       while (spi_ready == 1 && (++retry_count < 1000)) {
+               /* Set-up SPI Controller To Receive SPI EEPROM Status.*/
+               /* Write SPI Control Register Write Command.*/
+               count   = 1;
+               wr_data = ((WR_CPU_CTRL_REGS * 0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -2 Register Address.*/
+               wr_data = SPI_CTRL_2_H;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -2 Register Word-2.*/
+               wr_data = 0x0100;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Fill-up SPI Transmit Fifo To check SPI Status.*/
+               /* Write SPI Control Register Write Command.*/
+               count = 2;
+               wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write Tx Fifo Register Address.*/
+               wr_data = SPI_TXFIFO;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Tx Fifo Control Word-1.*/
+               wr_data = ((1 * 0x0100) | MSGTYPE_HRD);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Tx Fifo Control Word-2.*/
+               wr_data = RDSR_OPCODE;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control Register Write Command.*/
+               count = 2;
+               wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Address.*/
+               wr_data = SPI_CTRL_1_L;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Word-1.*/
+               wr_data = 0x0101;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Word-2.*/
+               wr_data = 0x0100;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control Register Write Command.*/
+               count = 1;
+               wr_data = ((WR_CPU_CTRL_REGS * 0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Address.*/
+               wr_data = SPI_CTRL_1_H;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Word-2.*/
+               wr_data = 0x0103;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               DP(NETIF_MSG_LINK, "**Wait for Status Register to be written ");
+
+               /* Wait For 64 bytes To be written.*/
+               rd_data = 0x0000;
+               while ((rd_data & 0x0100) == 0) {
+                       /* Write SPI Control Register Read Command.*/
+                       count = 1;
+                       wr_data = ((RD_CPU_CTRL_REGS * 0x0100) | count);
+                       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr,
+                                          wr_data, &rd_data);
+
+                       /* Write SPI Control -1 Register Address.*/
+                       wr_data = SPI_CTRL_1_L;
+                       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr,
+                                          wr_data, &rd_data);
+               }
+               DP(NETIF_MSG_LINK, "**Write SPI CTRl Read command ");
+
+               /* Write SPI Control Register Read Command.*/
+               count = 1;      /* Read from SPI Controller register C000.*/
+               wr_data = ((RD_CPU_CTRL_REGS * 0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Address.*/
+               wr_data = SPI_RXFIFO;
+               if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 ||
+                   ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) {
+                       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr,
+                                         wr_data, &rd_data);
+               } else {
+                       bnx2x_cl45_write(bp, port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_M8051_MSGIN_REG, wr_data);
+
+                       bnx2x_cl45_read(bp, port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_M8051_MSGOUT_REG, &rd_data);
+
+                       bnx2x_cl45_read(bp, port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     MDIO_PMA_REG_RX_ALARM, &wr_data);
+               }
+
+       if ((rd_data & 0x1) == 0)
+               spi_ready = 0;
+       } /* spi_ready  */
+       if (retry_count == 1000)
+               return -EINVAL;
+
+       return 0;
+}
+
+
+static u8 bnx2x_phy_bcm_rom_write_enable(struct bnx2x *bp, u8 port,
+                                      u8 ext_phy_addr, u32 ext_phy_type,
+                                      u8 enable)
+{
+       u8 count = 0, wrsr_data;
+       u16 rd_data = 0, wr_data = 0;
+
+       /* De-assert SPI EEPROM Block Protection.*/
+       DP(NETIF_MSG_LINK, "*** De-assert SPI Block Protect\n");
+
+       /* Write SPI Control Register Write Command.*/
+       count = 2;
+       wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+       DP(NETIF_MSG_LINK, "First write succeeded\n");
+       /* Write SPI Control -2 Register Address.*/
+       wr_data = SPI_CTRL_2_L;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -2 Register Word-1.*/
+       wr_data = 0x8200;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -2 Register Word-2.*/
+       wr_data = 0x0100;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Fill-up SPI Transmit Fifo With SPI EEPROM Messages.*/
+       /* Write SPI Control Register Write Command.*/
+       count = 4;
+       wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write Tx Fifo Register Address.*/
+       wr_data = SPI_TXFIFO;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Tx Fifo Control Word-1.*/
+       wr_data = ((1 * 0x0100) | MSGTYPE_HWR);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Tx Fifo Control Word-2.*/
+       wr_data = ((MSGTYPE_HWR * 0x0100) | WREN_OPCODE);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Tx Fifo Control Word-3.*/
+       wr_data = ((WRSR_OPCODE * 0x0100) | 0x02);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Tx Fifo Control Word-4.*/
+
+       wrsr_data = enable ? 0x2 : 0xc;
+       wr_data = ((wrsr_data * 0x0100) | wrsr_data);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control Register Write Command.*/
+       wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -1 Register Address.*/
+       wr_data = SPI_CTRL_1_L;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -1 Register Word-1.*/
+       wr_data = 0x0101;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -1 Register Word-2.*/
+       wr_data = 0x0003;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       return bnx2x_phy_bcm_rom_wait(bp, port, ext_phy_addr, ext_phy_type);
+
+}
+
+/* Programs an image to DSP's flash via the SPI port*/
+static u8 bnx2x_bcm_flash_download(struct bnx2x *bp, u8 port,
+                                 u8 ext_phy_addr, u32 ext_phy_type,
+                                 char *code_ptr, u32 size) {
+       u16 tmp, rd_data, wr_data = 4;
+       u8 count, rc = 0;
+       u32 i, data_index;
+       u16 misc_ctrl;
+
+       DP(NETIF_MSG_LINK, "bnx2x_bcm_flash_download: size=0x%x\n", size);
+
+       bnx2x_cl45_write(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_AN_DEVAD,
+                     MDIO_AN_REG_CTRL, 0);
+
+       /* Enable the LASI For Message out */
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_MISC_CTRL1, &misc_ctrl);
+
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, (misc_ctrl | (1<<0)));
+
+       /* Read LASI Status registers To clear initial Failure status. */
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_RX_ALARM, &tmp);
+
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_TX_ALARM, &tmp);
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_LASI_STATUS, &tmp);
+
+       /* Enable the LASI For Message out */
+
+       switch (ext_phy_type) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               wr_data = 0x0004;
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               wr_data = 0x0400;
+               break;
+       }
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_RX_ALARM_CTRL, wr_data);
+
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_LASI_CTRL, 0x4);
+
+
+       /*  Read Any Residual Message out register.1.CA13*/
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_M8051_MSGOUT_REG, &rd_data);
+
+       /*  Clear LASI Message Out Status. 1.9003 */
+       bnx2x_cl45_read(bp, port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_RX_ALARM, &rd_data);
+
+       if (bnx2x_phy_bcm_rom_write_enable(bp, port, ext_phy_addr,
+                                        ext_phy_type, 1) != 0)
+               return -EINVAL;
+
+       for (data_index = 0; data_index < BUF_SIZE_BCM;
+             data_index += WR_BLOCK_SIZE) {
+               /* Setup SPI Controller
+               Write SPI Control Register Write Command. */
+
+               count = 2;/* Write to C400, C401, C402, C403 Registers.*/
+               wr_data = ((WR_CPU_CTRL_FIFO * 0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -2 Register Address.*/
+               wr_data = SPI_CTRL_2_L;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -2 Register Word-1 */
+               /* C400 = 0 for 0 Fill Byte. C401 = 02 for SPI Clcok to
+               be divide by 2 and little endian fifo.*/
+               wr_data = 0x8200;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -2 Register Word-2.*/
+               /* C402 = 0, clear all status. C403 = 1,
+               to enable Done Status.*/
+               wr_data = 0x0100;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Fill-up SPI Transmit Fifo.*/
+               /* Write SPI Control Register Write Command. */
+               /* Write To Transmit Fifo D000-onwards.*/
+               count = 4 + (WR_BLOCK_SIZE/2);
+               wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write Tx Fifo Register Address.*/
+               wr_data = SPI_TXFIFO;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Tx Fifo Control Word-1.*/
+               /* {8'h1, MSGTYPE_HWR};
+               ( 1byte to transmit for WREN opcode).*/
+               wr_data = ((1*0x0100) | MSGTYPE_HWR);
+               /* D001 = Write Message And  Higher byte of Transfer Size */
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+               /* Write SPI Tx Fifo Control Word-2.*/
+               /* D002 = WREN Opcode For transmit.*/
+               wr_data = ((MSGTYPE_HWR * 0x0100) | WREN_OPCODE);
+               /* D003 = Total byte To be transmited
+               (64 + 3 For command, And address).*/
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Tx Fifo Control Word-3.*/
+               /* D004 = Second Message is also WRITE Message.*/
+               wr_data = ((WR_OPCODE * 0x0100) |
+                          (0x3 + WR_BLOCK_SIZE));
+               /* D005 = Write Opcode.*/
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Tx Fifo Control Word-4. */
+               /* D006 = SPI EEPROM Dest Addr (higher byte sent out first).*/
+               /* D007 = SPI EEPROM Dest Addr (lower byte sent out later).*/
+               wr_data = (((data_index & 0x00FF)*0x0100) |
+                          ((data_index & 0xFF00)/0x0100));
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               for (i = 0; i < WR_BLOCK_SIZE; i += 2) {
+                       /* Write SPI Tx Fifo Data Word-4.*/
+                       /* D008 = Low Byte. D009 = High Byte.*/
+                       wr_data = (u16)((code_ptr[i+data_index+1]*0x0100) |
+                                       (code_ptr[i+data_index] & 0x00FF));
+                       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data,
+                                          &rd_data);
+               }
+
+               DP(NETIF_MSG_LINK, " 64bytes filled in SPIfifo 0x%x\n",
+                        data_index);
+
+               /* Let the user know something's going on every 1024 bytes.*/
+               if ((data_index % 1024) == 0)
+                       DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
+
+               /* Set-up SPI Controller To Transmit.*/
+               /* Write SPI Control Register Write Command.*/
+               /* Write to SPI Control Register C000 onwards.*/
+               count = 2;
+               /* {CLC_WR_CPU_CTRL_FIFO, count};*/
+               wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count);
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Address.*/
+               wr_data = SPI_CTRL_1_L;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Word-1.*/
+               /* C000 = 1 to clear CMD Done Status. C001 = 1 to clear CMD Done
+               INT Status.*/
+               wr_data = 0x0501;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               /* Write SPI Control -1 Register Word-2.*/
+               /* C002 = 3, Start Immidiate Command. C003 = 0, No Prepend byte
+               for Write.*/
+               wr_data = 0x0003;
+               WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+               if (bnx2x_phy_bcm_rom_wait(bp, port, ext_phy_addr, ext_phy_type)
+                       != 0)
+                       return -EINVAL;
+       }
+       DP(NETIF_MSG_LINK, "*** SPI_READ and WRITE COMPLETE 0x%x\n",
+                data_index);
+
+       if (bnx2x_phy_bcm_rom_write_enable(bp, port, ext_phy_addr,
+                                        ext_phy_type, 0) != 0)
+               return -EINVAL;
+
+       /* Disable SPI EEPROM.*/
+       /* Write SPI Control Register Write Command.*/
+       count = 2; /* Write to C400, C401, C402, C403 Registers.*/
+       wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -2 Register Address.*/
+       wr_data = SPI_CTRL_2_L;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -2 Register Word-1.*/
+       wr_data = 0x8200; /* C400 = 0 for 0 Fill Byte. C401 = 02 for
+       SPI Clcok to be divide by 2 and little endian fifo.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -2 Register Word-2.*/
+       wr_data = 0x0100; /* C402 = 0, clear all status. C403 = 1, to
+       enable Done Status.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Fill-up SPI Transmit Fifo With SPI EEPROM Messages.*/
+       /* Write SPI Control Register Write Command.*/
+       count   = 2;  /* Write to Transmit Fifo D000-onwards.*/
+               wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /*Write Tx Fifo Register Address.*/
+       wr_data = SPI_TXFIFO;       /* D000.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Tx Fifo Control Word-1.*/
+       wr_data = ((0x1*0x0100) | MSGTYPE_HWR); /* D000 = Only 1
+       byte Message ( 1byte to transmit for WRDI opcode).*/
+
+       /* D001 = Write Message And  Higher byte of Transfer Size.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Tx Fifo Control Word-2.*/
+       wr_data = WRDI_OPCODE; /* D002 = WRDI Opcode for transmit.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /*Write SPI Control Register Write Command.*/
+       count   = 2;       /* Write to SPI Control Register C000 onwards.*/
+       wr_data = ((WR_CPU_CTRL_FIFO*0x0100) | count);
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+       /* Write SPI Control -1 Register Address.*/
+       wr_data = SPI_CTRL_1_L;
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -1 Register Word-1.*/
+       wr_data = 0x0101;  /* C000 = 1 to clear CMD Done Status.
+       C001 = 1 to clear CMD Done INT Status.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+
+       /* Write SPI Control -1 Register Word-2.*/
+       wr_data = 0x0003; /* C002 = 3, Start Immidiate Command.
+       C003 = 0, No Prepend byte for Write.*/
+       WRITE_MESSAGE_BCM(bp, port, ext_phy_addr, wr_data, &rd_data);
+       bnx2x_cl45_write(bp, port,
+                      ext_phy_type,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_MISC_CTRL1, (misc_ctrl & ~(1<<0)));
+       DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
+       return rc;
+}
+
+/* Programs an image to DSP's flash via the SPI port*/
+static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
+                                    u8 ext_phy_addr,
+                                    char data[], u32 size)
+{
+       const u16 num_trans = size/4; /* 4 bytes can be sent at a time */
+       /* Doesn't include last trans!*/
+       const u16 last_trans_size = size%4; /* Num bytes on last trans */
+       u16 trans_cnt, byte_cnt;
+       u32 data_index;
+       u16 tmp;
+       u16 code_started = 0;
+       u16 image_revision1, image_revision2;
+       u16 cnt;
+
+       DP(NETIF_MSG_LINK, "bnx2x_sfx7101_flash_download file_size=%d\n", size);
+       /* Going to flash*/
+       if ((size-HEADER_SIZE) > MAX_APP_SIZE) {
+               /* This very often will be the case, because the image is built
+               with 160Kbytes size whereas the total image size must actually
+               be 160Kbytes-RESERVED_SIZE */
+               DP(NETIF_MSG_LINK, "Warning, file size was %d bytes "
+                        "truncated to %d bytes\n", size, MAX_APP_SIZE);
+               size = MAX_APP_SIZE+HEADER_SIZE;
+       }
+       DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
+       DP(NETIF_MSG_LINK, "          %c%c\n", data[0x150], data[0x151]);
+       /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
+          and issuing a reset.*/
+
+       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                         MISC_REGISTERS_GPIO_HIGH, port);
+
+       bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
+
+       /* wait 0.5 sec */
+       for (cnt = 0; cnt < 100; cnt++)
+               msleep(5);
+
+       /* Make sure we can access the DSP
+          And it's in the correct mode (waiting for download) */
+
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                     ext_phy_addr,
+                     MDIO_PCS_DEVAD,
+                     MDIO_PCS_REG_7101_DSP_ACCESS, &tmp);
+
+       if (tmp != 0x000A) {
+               DP(NETIF_MSG_LINK, "DSP is not in waiting on download mode. "
+                        "Expected 0x000A, read 0x%04X\n", tmp);
+               DP(NETIF_MSG_LINK, "Download failed\n");
+               return -EINVAL;
+       }
+
+       /* Mux the SPI interface away from the internal processor */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_MUX, 1);
+
+       /* Reset the SPI port */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_CTRL_ADDR,
+                      (1<<MDIO_PCS_REG_7101_SPI_RESET_BIT));
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
+
+       /* Erase the flash */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                       MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
+                      1);
+
+       SPI_START_TRANSFER(bp, port, ext_phy_addr);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                       MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                      ext_phy_addr,
+                      MDIO_PCS_DEVAD,
+                      MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
+                      1);
+       SPI_START_TRANSFER(bp, port, ext_phy_addr);
+
+       /* Wait 10 seconds, the maximum time for the erase to complete */
+       DP(NETIF_MSG_LINK, "Erasing flash, this takes 10 seconds...\n");
+       for (cnt = 0; cnt < 1000; cnt++)
+               msleep(10);
+
+       DP(NETIF_MSG_LINK, "Downloading flash, please wait...\n");
+       data_index = 0;
+       for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) {
+               bnx2x_cl45_write(bp, port,
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                            ext_phy_addr,
+                            MDIO_PCS_DEVAD,
+                            MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                            MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
+
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
+                              1);
+               SPI_START_TRANSFER(bp, port, ext_phy_addr);
+
+               bnx2x_cl45_write(bp, port,
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                            ext_phy_addr,
+                            MDIO_PCS_DEVAD,
+                            MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                            MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
+
+               /* Bits 23-16 of address */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                              (data_index>>16));
+               /* Bits 15-8 of address */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                              (data_index>>8));
+
+               /* Bits 7-0 of address */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                              ((u16)data_index));
+
+               byte_cnt = 0;
+               while (byte_cnt < 4 && data_index < size) {
+                       bnx2x_cl45_write(bp, port,
+                                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                                      ext_phy_addr,
+                                      MDIO_PCS_DEVAD,
+                                      MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                                      data[data_index++]);
+                       byte_cnt++;
+               }
+
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
+                              byte_cnt+4);
+
+               SPI_START_TRANSFER(bp, port, ext_phy_addr);
+               msleep(5); /* Wait 5 ms minimum between transs */
+
+               /* Let the user know something's going on.*/
+               /* a pacifier ever 4K */
+               if ((data_index % 1023) == 0)
+                       DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
+       }
+
+       DP(NETIF_MSG_LINK, "\n");
+       /* Transfer the last block if there is data remaining */
+       if (last_trans_size) {
+               bnx2x_cl45_write(bp, port,
+                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                       ext_phy_addr,
+                       MDIO_PCS_DEVAD,
+                       MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                       MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
+
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
+                              1);
+
+               SPI_START_TRANSFER(bp, port, ext_phy_addr);
+
+               bnx2x_cl45_write(bp, port,
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                            ext_phy_addr,
+                            MDIO_PCS_DEVAD,
+                            MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                            MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
+
+               /* Bits 23-16 of address */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                              (data_index>>16));
+               /* Bits 15-8 of address */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                              (data_index>>8));
+
+               /* Bits 7-0 of address */
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                              ((u16)data_index));
+
+               byte_cnt = 0;
+               while (byte_cnt < last_trans_size && data_index < size) {
+                       /* Bits 7-0 of address */
+                       bnx2x_cl45_write(bp, port,
+                                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                                      ext_phy_addr,
+                                      MDIO_PCS_DEVAD,
+                                      MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
+                                      data[data_index++]);
+                       byte_cnt++;
+               }
+
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                              ext_phy_addr,
+                              MDIO_PCS_DEVAD,
+                              MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
+                              byte_cnt+4);
+
+               SPI_START_TRANSFER(bp, port, ext_phy_addr);
+       }
+
+       /* DSP Remove Download Mode */
+       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                         MISC_REGISTERS_GPIO_LOW, port);
+
+       bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
+
+       /* wait 0.5 sec to allow it to run */
+       for (cnt = 0; cnt < 100; cnt++)
+               msleep(5);
+
+       bnx2x_ext_phy_hw_reset(bp, port);
+
+       for (cnt = 0; cnt < 100; cnt++)
+               msleep(5);
+
+       /* Check that the code is started. In case the download
+       checksum failed, the code won't be started. */
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                     ext_phy_addr,
+                     MDIO_PCS_DEVAD,
+                     MDIO_PCS_REG_7101_DSP_ACCESS,
+                     &tmp);
+
+       code_started = (tmp & (1<<4));
+       if (!code_started) {
+               DP(NETIF_MSG_LINK, "Download failed. Please check file.\n");
+               return -EINVAL;
+       }
+
+       /* Verify that the file revision is now equal to the image
+       revision within the DSP */
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_7101_VER1,
+                     &image_revision1);
+
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_7101_VER2,
+                     &image_revision2);
+
+       if (data[0x14e] != (image_revision2&0xFF) ||
+           data[0x14f] != ((image_revision2&0xFF00)>>8) ||
+           data[0x150] != (image_revision1&0xFF) ||
+           data[0x151] != ((image_revision1&0xFF00)>>8)) {
+               DP(NETIF_MSG_LINK, "Download failed.\n");
+               return -EINVAL;
+       }
+       DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
+       return 0;
+}
+
+
+
+u8 bnx2x_bcm8481_flash_download(struct bnx2x *bp, u8 port,
+                             u8 ext_phy_addr,
+                             char data[], u32 size)
+{
+       u32 data_index;
+       u16 val, cnt;
+
+       /* Disable interrupts */
+       bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
+                    (NIG_MASK_XGXS0_LINK_STATUS |
+                     NIG_MASK_XGXS0_LINK10G |
+                     NIG_MASK_SERDES0_LINK_STATUS |
+                     NIG_MASK_MI_INT));
+
+       /* Step 1: Halt system */
+       DP(NETIF_MSG_LINK, "Step 1: Halt system\n");
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4186, 0x8000);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x017c);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x0040);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA819, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81A, 0xc300);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81B, 0x001e);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81C, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA817, 0x0009);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA819, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81A, 0xffff);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81B, 0xfffe);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81C, 0xeaff);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA817, 0x0009);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x0000);
+
+       /* Step 2: Download code into memory*/
+       DP(NETIF_MSG_LINK, "Step 2: Download code into memory\n");
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA817, 0x0039);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81A, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA819, 0x0000);
+
+       for (data_index = 0; data_index < size; data_index += 4) {
+               /* File is in Little Endian */
+               /* Write upper 16-bits(x)*/
+               val = data[data_index+2] | (data[data_index+3] << 8);
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD, 0xA81C, val);
+               /* Write lower 16-bits(x)*/
+               val = data[data_index+0] | (data[data_index+1] << 8);
+               bnx2x_cl45_write(bp, port,
+                              PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                              ext_phy_addr,
+                              MDIO_PMA_DEVAD, 0xA81B, val);
+               /* Wait for complete status for upto 5 ms*/
+               for (cnt = 0; cnt < 1000; cnt++) {
+                       bnx2x_cl45_read(bp, port,
+                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                             ext_phy_addr,
+                             MDIO_PMA_DEVAD, 0xA818, &val);
+                       if (val & 0x1)
+                               break;
+                       /* Wait 50 microSec*/
+                       udelay(50);
+               }
+               if (cnt == 1000) {
+                       DP(NETIF_MSG_LINK, "Failed to download image\n");
+                       return -EINVAL;
+               }
+               if ((data_index % 1024) == 0)
+                       DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
+       }
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA817, 0x0000);
+
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA819, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81A, 0xc300);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81B, 0x000c);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA81C, 0x0000);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      MDIO_PMA_DEVAD, 0xA817, 0x0009);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x0040);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x0000);
+       DP(NETIF_MSG_LINK, "Step 3: Waiting for the Programming"
+               "phase to be completed (5 seconds).\n");
+       for (cnt = 0; cnt < 1000; cnt++)
+               msleep(5);
+       /* Step 3: Restart system */
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x017c);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x0040);
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+                      ext_phy_addr,
+                      0x1e, 0x4181, 0x0000);
+       DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
+       return 0;
+}
+u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
+                     u8 driver_loaded, char data[], u32 size)
+{
+       u8 rc = 0;
+       u32 ext_phy_type;
+       u8 ext_phy_addr;
+       ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
+       ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
+
+       /* Verify image header */
+       if (bnx2x_verify_image_header(bp,
+                                   (struct bnx2x_image_header *)data,
+                                   ext_phy_type) != 0)
+               return -EINVAL;
+       data += sizeof(struct bnx2x_image_header);
+       size -= sizeof(struct bnx2x_image_header);
+
+       switch (ext_phy_type) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+               DP(NETIF_MSG_LINK,
+                       "Flash download not supported for this ext phy\n");
+               rc = -EINVAL;
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+               if (!driver_loaded)
+                       bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
+
+               rc = bnx2x_bcm_flash_download(bp, port, ext_phy_addr,
+                                        ext_phy_type,
+                                        data, size);
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+               /* Take ext phy out of reset */
+               if (!driver_loaded)
+                       bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
+               rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
+                                               data, size);
+               if (!driver_loaded)
+                       bnx2x_turn_off_sf(bp, port);
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+               rc = bnx2x_bcm8481_flash_download(bp, port, ext_phy_addr,
+                                               data, size);
+               break;
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
+       default:
+               DP(NETIF_MSG_LINK, "Invalid ext phy type\n");
+               rc = -EINVAL;
+               break;
+       }
+       return rc;
+}
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_link.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_link.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_link.h        1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_link.h     2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,210 @@
+/* Copyright 2008-2009 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
+ *
+ * Written by Yaniv Rosner
+ *
+ */
+
+#ifndef BNX2X_LINK_H
+#define BNX2X_LINK_H
+
+
+
+/***********************************************************/
+/*                         Defines                         */
+/***********************************************************/
+#define DEFAULT_PHY_DEV_ADDR   3
+
+
+
+#define BNX2X_FLOW_CTRL_AUTO           PORT_FEATURE_FLOW_CONTROL_AUTO
+#define BNX2X_FLOW_CTRL_TX             PORT_FEATURE_FLOW_CONTROL_TX
+#define BNX2X_FLOW_CTRL_RX             PORT_FEATURE_FLOW_CONTROL_RX
+#define BNX2X_FLOW_CTRL_BOTH           PORT_FEATURE_FLOW_CONTROL_BOTH
+#define BNX2X_FLOW_CTRL_NONE           PORT_FEATURE_FLOW_CONTROL_NONE
+
+#define SPEED_AUTO_NEG             0
+#define SPEED_12000                    12000
+#define SPEED_12500                    12500
+#define SPEED_13000                    13000
+#define SPEED_15000                    15000
+#define SPEED_16000                    16000
+
+#define SFP_EEPROM_VENDOR_NAME_ADDR            0x14
+#define SFP_EEPROM_VENDOR_NAME_SIZE            16
+#define SFP_EEPROM_VENDOR_OUI_ADDR             0x25
+#define SFP_EEPROM_VENDOR_OUI_SIZE             3
+#define SFP_EEPROM_PART_NO_ADDR                0x28
+#define SFP_EEPROM_PART_NO_SIZE                16
+#define PWR_FLT_ERR_MSG_LEN                    250
+/***********************************************************/
+/*                         Structs                         */
+/***********************************************************/
+/* Inputs parameters to the CLC */
+struct link_params {
+
+       u8 port;
+
+       /* Default / User Configuration */
+       u8 loopback_mode;
+#define LOOPBACK_NONE          0
+#define LOOPBACK_EMAC          1
+#define LOOPBACK_BMAC          2
+#define LOOPBACK_XGXS_10               3
+#define LOOPBACK_EXT_PHY               4
+#define LOOPBACK_EXT           5
+
+       u16 req_duplex;
+       u16 req_flow_ctrl;
+       u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
+       req_flow_ctrl is set to AUTO */
+       u16 req_line_speed; /* Also determine AutoNeg */
+
+       /* Device parameters */
+       u8 mac_addr[6];
+
+       /* shmem parameters */
+       u32 shmem_base;
+       u32 speed_cap_mask;
+       u32 switch_cfg;
+#define SWITCH_CFG_1G          PORT_FEATURE_CON_SWITCH_1G_SWITCH
+#define SWITCH_CFG_10G         PORT_FEATURE_CON_SWITCH_10G_SWITCH
+#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
+
+       u16 hw_led_mode; /* part of the hw_config read from the shmem */
+
+       /* phy_addr populated by the CLC */
+       u8 phy_addr;
+       /*u8 reserved1;*/
+
+       u32 lane_config;
+       u32 ext_phy_config;
+#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
+               ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
+#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
+               (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
+                PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
+#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
+               ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
+
+       /* Phy register parameter */
+       u32 chip_id;
+
+       u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
+       u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
+
+       u32 feature_config_flags;
+#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED    (1<<0)
+#define FEATURE_CONFIG_PFC_ENABLED                     (1<<1)
+#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY                (1<<2)
+#define FEATURE_CONFIG_BCM8727_NOC                     (1<<3)
+
+       /* Device pointer passed to all callback functions */
+       struct bnx2x *bp;
+};
+
+/* Output parameters */
+struct link_vars {
+       u8 phy_flags;
+
+       u8 mac_type;
+#define MAC_TYPE_NONE          0
+#define MAC_TYPE_EMAC          1
+#define MAC_TYPE_BMAC          2
+
+       u8 phy_link_up; /* internal phy link indication */
+       u8 link_up;
+
+       u16 line_speed;
+       u16 duplex;
+
+       u16 flow_ctrl;
+       u16 ieee_fc;
+
+       u32 autoneg;
+#define AUTO_NEG_DISABLED                      0x0
+#define AUTO_NEG_ENABLED                       0x1
+#define AUTO_NEG_COMPLETE                      0x2
+#define AUTO_NEG_PARALLEL_DETECTION_USED       0x3
+
+       /* The same definitions as the shmem parameter */
+       u32 link_status;
+};
+
+/***********************************************************/
+/*                         Functions                       */
+/***********************************************************/
+
+/* Initialize the phy */
+u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
+
+/* Reset the link. Should be called when driver or interface goes down
+   Before calling phy firmware upgrade, the reset_ext_phy should be set
+   to 0 */
+u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
+                 u8 reset_ext_phy);
+
+/* bnx2x_link_update should be called upon link interrupt */
+u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
+
+/* use the following cl45 functions to read/write from external_phy
+  In order to use it to read/write internal phy registers, use
+  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
+  Use ext_phy_type of 0 in case of cl22 over cl45
+  the register */
+u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
+                u8 phy_addr, u8 devad, u16 reg, u16 *ret_val);
+
+u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
+                 u8 phy_addr, u8 devad, u16 reg, u16 val);
+
+/* Reads the link_status from the shmem,
+   and update the link vars accordingly */
+void bnx2x_link_status_update(struct link_params *input,
+                           struct link_vars *output);
+/* returns string representing the fw_version of the external phy */
+u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
+                             u8 *version, u16 len);
+
+/* Set/Unset the led
+   Basically, the CLC takes care of the led for the link, but in case one needs
+   to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
+   blink the led, and LED_MODE_OFF to set the led off.*/
+u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
+              u16 hw_led_mode, u32 chip_id);
+#define LED_MODE_OFF   0
+#define LED_MODE_OPER  2
+
+u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value);
+
+u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
+                     u8 driver_loaded, char data[], u32 size);
+/* bnx2x_handle_module_detect_int should be called upon module detection
+   interrupt */
+void bnx2x_handle_module_detect_int(struct link_params *params);
+
+/* Get the actual link status. In case it returns 0, link is up,
+       otherwise link is down*/
+u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
+
+/* One-time initialization for external phy after power up */
+u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
+
+/* Reset the external PHY using GPIO */
+void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
+
+void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr);
+
+u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
+                             u8 byte_cnt, u8 *o_buf);
+
+#endif /* BNX2X_LINK_H */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_main.c linux-2.6.22-800/drivers/net/bnx2x/bnx2x_main.c
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_main.c        1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_main.c     2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,14191 @@
+/* bnx2x_main.c: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Eliezer Tamir
+ * Based on code from Michael Chan's bnx2 driver
+ * UDP CSUM errata workaround by Arik Gendelman
+ * Slowpath and fastpath rework by Vladislav Zolotarov
+ * Statistics and Link management by Yitchak Gertner
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+#include <linux/moduleparam.h>
+#endif
+#include <linux/kernel.h>
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+#include <linux/device.h>  /* for dev_info() */
+#endif
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+#include <linux/dma-mapping.h>
+#endif
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+#include <linux/time.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/if_vlan.h>
+#include <net/ip.h>
+#if (LINUX_VERSION_CODE < 0x020600) /* ! BNX2X_UPSTREAM */
+#include <net/ipv6.h>
+#endif
+#include <net/tcp.h>
+#include <net/checksum.h>
+#if (LINUX_VERSION_CODE > 0x020607) /* BNX2X_UPSTREAM */
+#include <net/ip6_checksum.h>
+#endif
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+#include <linux/workqueue.h>
+#endif
+#include <linux/crc32.h>
+#if (LINUX_VERSION_CODE >= 0x02061b) && !defined(BNX2X_DRIVER_DISK) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */
+#include <linux/crc32c.h>
+#endif
+#include <linux/prefetch.h>
+#include <linux/zlib.h>
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+#include <linux/io.h>
+#else
+#include <asm/io.h>
+#endif
+
+#if (LINUX_VERSION_CODE < 0x020600) /* ! BNX2X_UPSTREAM */
+#define __NO_TPA__             1
+#endif
+
+#include "bnx2x.h"
+#include "bnx2x_init.h"
+#include "bnx2x_init_ops.h"
+#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
+#include "bnx2x_self_test.h"
+#endif
+#include "bnx2x_dump.h"
+
+#define DRV_MODULE_VERSION     "1.50.13"
+#define DRV_MODULE_RELDATE     "$DateTime: 2009/07/22 07:22:59 $"
+#define BNX2X_BC_VER           0x040200
+
+#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */
+#include <linux/firmware.h>
+#include "bnx2x_fw_file_hdr.h"
+/* FW files */
+#define FW_FILE_PREFIX_E1      "bnx2x-e1-"
+#define FW_FILE_PREFIX_E1H     "bnx2x-e1h-"
+#else
+void bnx2x_init_e1_firmware(struct bnx2x *bp);
+void bnx2x_init_e1h_firmware(struct bnx2x *bp);
+#endif
+
+/* Time in jiffies before concluding the transmitter is hung */
+#define TX_TIMEOUT             (5*HZ)
+
+static char version[] __devinitdata =
+       "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
+       DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
+
+MODULE_AUTHOR("Eliezer Tamir");
+MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_MODULE_VERSION);
+#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
+#if (LINUX_VERSION_CODE >= 0x020600) /* ! BNX2X_UPSTREAM */
+MODULE_INFO(cvs_version, "$Revision: #18 $");
+#endif
+#endif
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+static int multi_mode = 1;
+module_param(multi_mode, int, 0);
+#ifdef BNX2X_SAFC
+MODULE_PARM_DESC(multi_mode, " Multi queue mode "
+                            "(0 Disable; 1 Enable (default);"
+                            " 2 VLAN PRI; 3 E1HOV PRI; 4 IP DSCP)");
+
+static int pri_map;
+module_param(pri_map, int, 0);
+MODULE_PARM_DESC(pri_map, " Priority to HW queue mapping");
+
+static int qs_per_cos;
+module_param(qs_per_cos, int, 0);
+MODULE_PARM_DESC(qs_per_cos, " Number of queues per HW queue");
+
+static int cos_min_rate;
+module_param(cos_min_rate, int, 0);
+MODULE_PARM_DESC(cos_min_rate, " Weight for RR between HW queues");
+#else /* BNX2X_UPSTREAM */
+MODULE_PARM_DESC(multi_mode, " Multi queue mode "
+                            "(0 Disable; 1 Enable (default))");
+#endif /* not BNX2X_SAFC */
+#else /* not BNX2X_NEW_NAPI */
+static int multi_mode;
+#endif
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+static int num_rx_queues;
+module_param(num_rx_queues, int, 0);
+MODULE_PARM_DESC(num_rx_queues, " Number of Rx queues for multi_mode=1"
+                               " (default is half number of CPUs)");
+#endif
+
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+static int num_tx_queues;
+module_param(num_tx_queues, int, 0);
+MODULE_PARM_DESC(num_tx_queues, " Number of Tx queues for multi_mode=1"
+                               " (default is half number of CPUs)");
+#endif
+
+#if defined(__NO_TPA__)
+static int disable_tpa = 1;
+#else /* BNX2X_UPSTREAM */
+static int disable_tpa;
+module_param(disable_tpa, int, 0);
+MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
+#endif
+
+static int int_mode;
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+module_param(int_mode, int, 0);
+MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
+#endif
+
+static int dropless_fc;
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+module_param(dropless_fc, int, 0);
+MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
+#endif
+
+static int poll;
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+module_param(poll, int, 0);
+MODULE_PARM_DESC(poll, " Use polling (for debug)");
+#endif
+
+static int mrrs = -1;
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+module_param(mrrs, int, 0);
+MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
+#endif
+
+static int debug;
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+module_param(debug, int, 0);
+MODULE_PARM_DESC(debug, " Default debug msglevel");
+#endif
+
+static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
+
+static struct workqueue_struct *bnx2x_wq;
+
+enum bnx2x_board_type {
+       BCM57710 = 0,
+       BCM57711 = 1,
+       BCM57711E = 2,
+};
+
+/* indexed by board_type, above */
+static struct {
+       char *name;
+} board_info[] __devinitdata = {
+       { "Broadcom NetXtreme II BCM57710 XGb" },
+       { "Broadcom NetXtreme II BCM57711 XGb" },
+       { "Broadcom NetXtreme II BCM57711E XGb" }
+};
+
+#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
+#ifndef PCI_DEVICE_ID_NX2_57710
+#define PCI_DEVICE_ID_NX2_57710                0x164e
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57711
+#define PCI_DEVICE_ID_NX2_57711                0x164f
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57711E
+#define PCI_DEVICE_ID_NX2_57711E       0x1650
+#endif
+#endif
+
+static const struct pci_device_id bnx2x_pci_tbl[] = {
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
+       { 0 }
+};
+
+MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+static int bnx2x_netqueue_ops(vmknetddi_queueops_op_t op, void *args);
+#endif
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+/* used only at init
+ * locking is done by mcp
+ */
+void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
+{
+       pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
+       pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
+       pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
+                              PCICFG_VENDOR_ID_OFFSET);
+}
+
+static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
+{
+       u32 val;
+
+       pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
+       pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
+       pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
+                              PCICFG_VENDOR_ID_OFFSET);
+
+       return val;
+}
+
+static const u32 dmae_reg_go_c[] = {
+       DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
+       DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
+       DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
+       DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
+};
+
+/* copy command into DMAE command memory and set DMAE command go */
+static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
+                           int idx)
+{
+       u32 cmd_offset;
+       int i;
+
+       cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
+       for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
+               REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
+
+               DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
+                  idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
+       }
+       REG_WR(bp, dmae_reg_go_c[idx], 1);
+}
+
+void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
+                     u32 len32)
+{
+       struct dmae_command dmae;
+       u32 *wb_comp = bnx2x_sp(bp, wb_comp);
+       int cnt = 200;
+
+       if (!bp->dmae_ready) {
+               u32 *data = bnx2x_sp(bp, wb_data[0]);
+
+               DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
+                  "  using indirect\n", dst_addr, len32);
+               bnx2x_init_ind_wr(bp, dst_addr, data, len32);
+               return;
+       }
+
+       memset(&dmae, 0, sizeof(struct dmae_command));
+
+       dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+                      DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+                      DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                      DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                      DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                      (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                      (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+       dmae.src_addr_lo = U64_LO(dma_addr);
+       dmae.src_addr_hi = U64_HI(dma_addr);
+       dmae.dst_addr_lo = dst_addr >> 2;
+       dmae.dst_addr_hi = 0;
+       dmae.len = len32;
+       dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+       dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+       dmae.comp_val = DMAE_COMP_VAL;
+
+       DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
+          DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
+                   "dst_addr [%x:%08x (%08x)]\n"
+          DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
+          dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
+          dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, dst_addr,
+          dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
+       DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
+          bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
+          bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
+
+       mutex_lock(&bp->dmae_mutex);
+
+       *wb_comp = 0;
+
+       bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
+
+       udelay(5);
+
+       while (*wb_comp != DMAE_COMP_VAL) {
+               DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
+
+               if (!cnt) {
+                       BNX2X_ERR("DMAE timeout!\n");
+                       break;
+               }
+               cnt--;
+               /* adjust delay for emulation/FPGA */
+               if (CHIP_REV_IS_SLOW(bp))
+                       msleep(100);
+               else
+                       udelay(5);
+       }
+
+       mutex_unlock(&bp->dmae_mutex);
+}
+
+void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
+{
+       struct dmae_command dmae;
+       u32 *wb_comp = bnx2x_sp(bp, wb_comp);
+       int cnt = 200;
+
+       if (!bp->dmae_ready) {
+               u32 *data = bnx2x_sp(bp, wb_data[0]);
+               int i;
+
+               DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
+                  "  using indirect\n", src_addr, len32);
+               for (i = 0; i < len32; i++)
+                       data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
+               return;
+       }
+
+       memset(&dmae, 0, sizeof(struct dmae_command));
+
+       dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+                      DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+                      DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                      DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                      DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                      (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                      (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+       dmae.src_addr_lo = src_addr >> 2;
+       dmae.src_addr_hi = 0;
+       dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
+       dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
+       dmae.len = len32;
+       dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+       dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+       dmae.comp_val = DMAE_COMP_VAL;
+
+       DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
+          DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
+                   "dst_addr [%x:%08x (%08x)]\n"
+          DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
+          dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
+          dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, src_addr,
+          dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
+
+       mutex_lock(&bp->dmae_mutex);
+
+       memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
+       *wb_comp = 0;
+
+       bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
+
+       udelay(5);
+
+       while (*wb_comp != DMAE_COMP_VAL) {
+
+               if (!cnt) {
+                       BNX2X_ERR("DMAE timeout!\n");
+                       break;
+               }
+               cnt--;
+               /* adjust delay for emulation/FPGA */
+               if (CHIP_REV_IS_SLOW(bp))
+                       msleep(100);
+               else
+                       udelay(5);
+       }
+       DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
+          bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
+          bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
+
+       mutex_unlock(&bp->dmae_mutex);
+}
+
+void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
+                              u32 addr, u32 len)
+{
+       int offset = 0;
+
+       while (len > DMAE_LEN32_WR_MAX) {
+               bnx2x_write_dmae(bp, phys_addr + offset,
+                                addr + offset, DMAE_LEN32_WR_MAX);
+               offset += DMAE_LEN32_WR_MAX * 4;
+               len -= DMAE_LEN32_WR_MAX;
+       }
+
+       bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
+}
+
+/* used only for slowpath so not inlined */
+static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
+{
+       u32 wb_write[2];
+
+       wb_write[0] = val_hi;
+       wb_write[1] = val_lo;
+       REG_WR_DMAE(bp, reg, wb_write, 2);
+}
+
+#ifdef USE_WB_RD
+static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
+{
+       u32 wb_data[2];
+
+       REG_RD_DMAE(bp, reg, wb_data, 2);
+
+       return HILO_U64(wb_data[0], wb_data[1]);
+}
+#endif
+
+static int bnx2x_mc_assert(struct bnx2x *bp)
+{
+       char last_idx;
+       int i, rc = 0;
+       u32 row0, row1, row2, row3;
+
+       /* XSTORM */
+       last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
+                          XSTORM_ASSERT_LIST_INDEX_OFFSET);
+       if (last_idx)
+               BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
+
+       /* print the asserts */
+       for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
+
+               row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
+                             XSTORM_ASSERT_LIST_OFFSET(i));
+               row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
+                             XSTORM_ASSERT_LIST_OFFSET(i) + 4);
+               row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
+                             XSTORM_ASSERT_LIST_OFFSET(i) + 8);
+               row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
+                             XSTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+               if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+                       BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
+                                 " 0x%08x 0x%08x 0x%08x\n",
+                                 i, row3, row2, row1, row0);
+                       rc++;
+               } else {
+                       break;
+               }
+       }
+
+       /* TSTORM */
+       last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
+                          TSTORM_ASSERT_LIST_INDEX_OFFSET);
+       if (last_idx)
+               BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
+
+       /* print the asserts */
+       for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
+
+               row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
+                             TSTORM_ASSERT_LIST_OFFSET(i));
+               row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
+                             TSTORM_ASSERT_LIST_OFFSET(i) + 4);
+               row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
+                             TSTORM_ASSERT_LIST_OFFSET(i) + 8);
+               row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
+                             TSTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+               if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+                       BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
+                                 " 0x%08x 0x%08x 0x%08x\n",
+                                 i, row3, row2, row1, row0);
+                       rc++;
+               } else {
+                       break;
+               }
+       }
+
+       /* CSTORM */
+       last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
+                          CSTORM_ASSERT_LIST_INDEX_OFFSET);
+       if (last_idx)
+               BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
+
+       /* print the asserts */
+       for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
+
+               row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
+                             CSTORM_ASSERT_LIST_OFFSET(i));
+               row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
+                             CSTORM_ASSERT_LIST_OFFSET(i) + 4);
+               row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
+                             CSTORM_ASSERT_LIST_OFFSET(i) + 8);
+               row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
+                             CSTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+               if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+                       BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
+                                 " 0x%08x 0x%08x 0x%08x\n",
+                                 i, row3, row2, row1, row0);
+                       rc++;
+               } else {
+                       break;
+               }
+       }
+
+       /* USTORM */
+       last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
+                          USTORM_ASSERT_LIST_INDEX_OFFSET);
+       if (last_idx)
+               BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
+
+       /* print the asserts */
+       for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
+
+               row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
+                             USTORM_ASSERT_LIST_OFFSET(i));
+               row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
+                             USTORM_ASSERT_LIST_OFFSET(i) + 4);
+               row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
+                             USTORM_ASSERT_LIST_OFFSET(i) + 8);
+               row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
+                             USTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+               if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+                       BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
+                                 " 0x%08x 0x%08x 0x%08x\n",
+                                 i, row3, row2, row1, row0);
+                       rc++;
+               } else {
+                       break;
+               }
+       }
+
+       return rc;
+}
+
+static void bnx2x_fw_dump(struct bnx2x *bp)
+{
+       u32 mark, offset;
+       __be32 data[9];
+       int word;
+
+       mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
+       mark = ((mark + 0x3) & ~0x3);
+       printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
+
+       for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
+               for (word = 0; word < 8; word++)
+                       data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
+                                                 offset + 4*word));
+               data[8] = 0x0;
+               printk(KERN_CONT "%s", (char *)data);
+       }
+       for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
+               for (word = 0; word < 8; word++)
+                       data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
+                                                 offset + 4*word));
+               data[8] = 0x0;
+               printk(KERN_CONT "%s", (char *)data);
+       }
+       printk("\n" KERN_ERR PFX "end of fw dump\n");
+}
+
+static void bnx2x_panic_dump(struct bnx2x *bp)
+{
+       int i;
+       u16 j, start, end;
+
+       bp->stats_state = STATS_STATE_DISABLED;
+       DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
+
+       BNX2X_ERR("begin crash dump -----------------\n");
+
+       /* Indices */
+       /* Common */
+       BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
+                 "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
+                 "  spq_prod_idx(%u)\n",
+                 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
+                 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
+
+       /* Rx */
+       for_each_rx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               BNX2X_ERR("fp%d: rx_bd_prod(%x)  rx_bd_cons(%x)"
+                         "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
+                         "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
+                         i, fp->rx_bd_prod, fp->rx_bd_cons,
+                         le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
+                         fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
+               BNX2X_ERR("      rx_sge_prod(%x)  last_max_sge(%x)"
+                         "  fp_u_idx(%x) *sb_u_idx(%x)\n",
+                         fp->rx_sge_prod, fp->last_max_sge,
+                         le16_to_cpu(fp->fp_u_idx),
+                         fp->status_blk->u_status_block.status_block_index);
+       }
+
+       /* Tx */
+       for_each_tx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               BNX2X_ERR("fp%d: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
+                         "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
+                         i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
+                         fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
+               BNX2X_ERR("      fp_c_idx(%x)  *sb_c_idx(%x)"
+                         "  tx_db_prod(%x)\n", le16_to_cpu(fp->fp_c_idx),
+                         fp->status_blk->c_status_block.status_block_index,
+                         fp->tx_db.data.prod);
+       }
+
+       /* Rings */
+       /* Rx */
+       for_each_rx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
+               end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
+               for (j = start; j != end; j = RX_BD(j + 1)) {
+                       u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
+                       struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
+
+                       BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
+                                 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
+               }
+
+               start = RX_SGE(fp->rx_sge_prod);
+               end = RX_SGE(fp->last_max_sge);
+               for (j = start; j != end; j = RX_SGE(j + 1)) {
+                       u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
+                       struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
+
+                       BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
+                                 i, j, rx_sge[1], rx_sge[0], sw_page->page);
+               }
+
+               start = RCQ_BD(fp->rx_comp_cons - 10);
+               end = RCQ_BD(fp->rx_comp_cons + 503);
+               for (j = start; j != end; j = RCQ_BD(j + 1)) {
+                       u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
+
+                       BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
+                                 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
+               }
+       }
+
+       /* Tx */
+       for_each_tx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
+               end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
+               for (j = start; j != end; j = TX_BD(j + 1)) {
+                       struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
+
+                       BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
+                                 i, j, sw_bd->skb, sw_bd->first_bd);
+               }
+
+               start = TX_BD(fp->tx_bd_cons - 10);
+               end = TX_BD(fp->tx_bd_cons + 254);
+               for (j = start; j != end; j = TX_BD(j + 1)) {
+                       u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
+
+                       BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
+                                 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
+               }
+       }
+
+       bnx2x_fw_dump(bp);
+#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
+       bp->msglevel |= NETIF_MSG_PROBE;
+       BNX2X_ERR("Idle check (1st round) ----------\n");
+       bnx2x_idle_chk(bp);
+       BNX2X_ERR("Idle check (2nd round) ----------\n");
+       bnx2x_idle_chk(bp);
+#endif
+       bnx2x_mc_assert(bp);
+       BNX2X_ERR("end crash dump -----------------\n");
+}
+
+static void bnx2x_int_enable(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
+       u32 val = REG_RD(bp, addr);
+       int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
+       int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
+
+       if (msix) {
+               val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+                        HC_CONFIG_0_REG_INT_LINE_EN_0);
+               val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+                       HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+       } else if (msi) {
+               val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
+               val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+                       HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+                       HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+       } else {
+               val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+                       HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+                       HC_CONFIG_0_REG_INT_LINE_EN_0 |
+                       HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+
+               DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
+                  val, port, addr);
+
+               REG_WR(bp, addr, val);
+
+               val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
+       }
+
+       DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
+          val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
+
+       REG_WR(bp, addr, val);
+       barrier();
+
+       if (CHIP_IS_E1H(bp)) {
+               /* init leading/trailing edge */
+               if (IS_E1HMF(bp)) {
+                       val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
+                       if (bp->port.pmf)
+                               /* enable nig and gpio3 attention */
+                               val |= 0x1100;
+               } else
+                       val = 0xffff;
+
+               REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
+               REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
+       }
+
+       /* Make sure that interrupts are indeed enabled from here on */
+       mmiowb();
+}
+
+static void bnx2x_int_disable(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
+       u32 val = REG_RD(bp, addr);
+
+       val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+                HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+                HC_CONFIG_0_REG_INT_LINE_EN_0 |
+                HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+
+       DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
+          val, port, addr);
+
+       /* flush all outstanding writes */
+       mmiowb();
+
+       REG_WR(bp, addr, val);
+       if (REG_RD(bp, addr) != val)
+               BNX2X_ERR("BUG! proper val not read from IGU!\n");
+}
+
+static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
+{
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+       int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
+       int i, offset;
+#endif
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       int j;
+#endif
+
+       /* disable interrupt handling */
+       atomic_inc(&bp->intr_sem);
+       smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
+
+       if (disable_hw)
+               /* prevent the HW from sending interrupts */
+               bnx2x_int_disable(bp);
+
+       /* make sure all ISRs are done */
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+       if (msix) {
+               synchronize_irq(bp->msix_table[0].vector);
+               offset = 1;
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+               offset++;
+#endif
+               for_each_queue(bp, i)
+                       synchronize_irq(bp->msix_table[i + offset].vector);
+       } else
+#endif
+               synchronize_irq(bp->pdev->irq);
+
+       /* make sure sp_task is not running */
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+       cancel_delayed_work(&bp->sp_task);
+       flush_workqueue(bnx2x_wq);
+#else
+       j = 0;
+       smp_mb(); /* sp_running is set by sp_task */
+       while (bp->sp_running) {
+               if (!(++j % 1000))
+                       BNX2X_ERR("sp_running (j %d)\n", j);
+               msleep(1);
+               smp_mb();
+       }
+#endif
+}
+
+/* fast path */
+
+/*
+ * General service functions
+ */
+
+static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
+                               u8 storm, u16 index, u8 op, u8 update)
+{
+       u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
+                      COMMAND_REG_INT_ACK);
+       struct igu_ack_register igu_ack;
+
+       igu_ack.status_block_index = index;
+       igu_ack.sb_id_and_flags =
+                       ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
+                        (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
+                        (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
+                        (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
+
+#if (LINUX_VERSION_CODE < 0x020600) /* ! BNX2X_UPSTREAM */
+       /* x86's writel() in 2.4.x does not have barrier(). */
+       barrier();
+#endif
+       DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
+          (*(u32 *)&igu_ack), hc_addr);
+       REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
+
+       /* Make sure that ACK is written */
+       mmiowb();
+       barrier();
+}
+
+static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
+{
+       struct host_status_block *fpsb = fp->status_blk;
+       u16 rc = 0;
+
+       barrier(); /* status block is written to by the chip */
+       if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
+               fp->fp_c_idx = fpsb->c_status_block.status_block_index;
+               rc |= 1;
+       }
+       if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
+               fp->fp_u_idx = fpsb->u_status_block.status_block_index;
+               rc |= 2;
+       }
+       return rc;
+}
+
+static u16 bnx2x_ack_int(struct bnx2x *bp)
+{
+       u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
+                      COMMAND_REG_SIMD_MASK);
+       u32 result = REG_RD(bp, hc_addr);
+
+       DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
+          result, hc_addr);
+
+       return result;
+}
+
+
+/*
+ * fast path service functions
+ */
+
+static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
+{
+       /* Tell compiler that consumer and producer can change */
+       barrier();
+       return (fp->tx_pkt_prod != fp->tx_pkt_cons);
+}
+
+/* free skb in the packet ring at pos idx
+ * return idx of last bd freed
+ */
+static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+                            u16 idx)
+{
+       struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
+       struct eth_tx_start_bd *tx_start_bd;
+       struct eth_tx_bd *tx_data_bd;
+       struct sk_buff *skb = tx_buf->skb;
+       u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
+       int nbd;
+
+       /* prefetch skb end pointer to speedup dev_kfree_skb() */
+       prefetch(&skb->end);
+
+       DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
+          idx, tx_buf, skb);
+
+       /* unmap first bd */
+       DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
+       tx_start_bd = &fp->tx_desc_ring[bd_idx].start_bd;
+       pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_start_bd),
+                        BD_UNMAP_LEN(tx_start_bd), PCI_DMA_TODEVICE);
+
+       nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
+#ifdef BNX2X_STOP_ON_ERROR
+       if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
+               BNX2X_ERR("BAD nbd!\n");
+               bnx2x_panic();
+       }
+#endif
+       new_cons = nbd + tx_buf->first_bd;
+
+       /* Get the next bd */
+       bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+
+       /* Skip a parse bd... */
+       --nbd;
+       bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+
+       /* ...and the TSO split header bd since they have no mapping */
+       if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
+               --nbd;
+               bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+       }
+
+       /* now free frags */
+       while (nbd > 0) {
+
+               DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
+               tx_data_bd = &fp->tx_desc_ring[bd_idx].reg_bd;
+               pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_data_bd),
+                              BD_UNMAP_LEN(tx_data_bd), PCI_DMA_TODEVICE);
+               if (--nbd)
+                       bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+       }
+
+       /* release skb */
+       WARN_ON(!skb);
+       dev_kfree_skb_any(skb);
+       tx_buf->first_bd = 0;
+       tx_buf->skb = NULL;
+
+       return new_cons;
+}
+
+static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
+{
+       s16 used;
+       u16 prod;
+       u16 cons;
+
+       barrier(); /* Tell compiler that prod and cons can change */
+       prod = fp->tx_bd_prod;
+       cons = fp->tx_bd_cons;
+
+       /* NUM_TX_RINGS = number of "next-page" entries
+          It will be used as a threshold */
+       used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
+
+#ifdef BNX2X_STOP_ON_ERROR
+       WARN_ON(used < 0);
+       WARN_ON(used > fp->bp->tx_ring_size);
+       WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
+#endif
+
+       return (s16)(fp->bp->tx_ring_size) - used;
+}
+
+static void bnx2x_tx_int(struct bnx2x_fastpath *fp)
+{
+       struct bnx2x *bp = fp->bp;
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       struct netdev_queue *txq;
+#endif
+       u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
+       int done = 0;
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return;
+#endif
+
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       txq = netdev_get_tx_queue(bp->dev, fp->index - bp->num_rx_queues);
+#endif
+       hw_cons = le16_to_cpu(*fp->tx_cons_sb);
+       sw_cons = fp->tx_pkt_cons;
+
+       while (sw_cons != hw_cons) {
+               u16 pkt_cons;
+
+               pkt_cons = TX_BD(sw_cons);
+
+               /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
+
+               DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
+                  hw_cons, sw_cons, pkt_cons);
+
+/*             if (NEXT_TX_IDX(sw_cons) != hw_cons) {
+                       rmb();
+                       prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
+               }
+*/
+               bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
+               sw_cons++;
+               done++;
+       }
+
+       fp->tx_pkt_cons = sw_cons;
+       fp->tx_bd_cons = bd_cons;
+
+       /* TBD need a thresh? */
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       if (unlikely(netif_tx_queue_stopped(txq))) {
+
+               /* Need to make the tx_bd_cons update visible to start_xmit()
+                * before checking for netif_tx_queue_stopped().  Without the
+                * memory barrier, there is a small possibility that
+                * start_xmit() will miss it and cause the queue to be stopped
+                * forever.
+                */
+               smp_mb();
+
+               if ((netif_tx_queue_stopped(txq)) &&
+                   (bp->state == BNX2X_STATE_OPEN) &&
+                   (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
+                       netif_tx_wake_queue(txq);
+       }
+#else
+       if (unlikely(netif_queue_stopped(bp->dev))) {
+
+               /* See above */
+               smp_mb();
+
+               if (netif_queue_stopped(bp->dev) &&
+                   (bp->state == BNX2X_STATE_OPEN) &&
+                   (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
+                       netif_wake_queue(bp->dev);
+       }
+#endif
+}
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
+#endif
+
+static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
+                          union eth_rx_cqe *rr_cqe)
+{
+       struct bnx2x *bp = fp->bp;
+       int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+       int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+
+       DP(BNX2X_MSG_SP,
+          "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
+          fp->index, cid, command, bp->state,
+          rr_cqe->ramrod_cqe.ramrod_type);
+
+       bp->spq_left++;
+
+       if (fp->index) {
+               switch (command | fp->state) {
+               case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
+                                               BNX2X_FP_STATE_OPENING):
+                       DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
+                          cid);
+                       fp->state = BNX2X_FP_STATE_OPEN;
+                       break;
+
+               case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
+                       DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
+                          cid);
+                       fp->state = BNX2X_FP_STATE_HALTED;
+                       break;
+
+               default:
+                       BNX2X_ERR("unexpected MC reply (%d)  "
+                                 "fp->state is %x\n", command, fp->state);
+                       break;
+               }
+               mb(); /* force bnx2x_wait_ramrod() to see the change */
+               return;
+       }
+
+       switch (command | bp->state) {
+       case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
+               DP(NETIF_MSG_IFUP, "got setup ramrod\n");
+               bp->state = BNX2X_STATE_OPEN;
+               break;
+
+       case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
+               DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
+               bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
+               fp->state = BNX2X_FP_STATE_HALTED;
+               break;
+
+       case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
+               DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
+               bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
+               break;
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_OPEN):
+               DP(NETIF_MSG_IFDOWN, "got delete ramrod for CID %d\n", cid);
+               bnx2x_cnic_cfc_comp(bp, cid);
+               break;
+#endif
+
+       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
+       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
+               DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
+               bp->set_mac_pending = 0;
+               break;
+
+       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
+       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DISABLED):
+               DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
+               break;
+
+       default:
+               BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
+                         command, bp->state);
+               break;
+       }
+       mb(); /* force bnx2x_wait_ramrod() to see the change */
+}
+
+static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
+                                    struct bnx2x_fastpath *fp, u16 index)
+{
+       struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
+       struct page *page = sw_buf->page;
+       struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
+
+       /* Skip "next page" elements */
+       if (!page)
+               return;
+
+       pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
+                      SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
+       __free_pages(page, PAGES_PER_SGE_SHIFT);
+
+       sw_buf->page = NULL;
+       sge->addr_hi = 0;
+       sge->addr_lo = 0;
+}
+
+static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
+                                          struct bnx2x_fastpath *fp, int last)
+{
+       int i;
+
+       for (i = 0; i < last; i++)
+               bnx2x_free_rx_sge(bp, fp, i);
+}
+
+static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
+                                    struct bnx2x_fastpath *fp, u16 index)
+{
+       struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
+       struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
+       struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
+       dma_addr_t mapping;
+
+       if (unlikely(page == NULL))
+               return -ENOMEM;
+
+       mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
+                              PCI_DMA_FROMDEVICE);
+#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+       if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
+#else
+       if (unlikely(dma_mapping_error(mapping))) {
+#endif
+               __free_pages(page, PAGES_PER_SGE_SHIFT);
+               return -ENOMEM;
+       }
+
+       sw_buf->page = page;
+       pci_unmap_addr_set(sw_buf, mapping, mapping);
+
+       sge->addr_hi = cpu_to_le32(U64_HI(mapping));
+       sge->addr_lo = cpu_to_le32(U64_LO(mapping));
+
+       return 0;
+}
+
+static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
+                                    struct bnx2x_fastpath *fp, u16 index)
+{
+       struct sk_buff *skb;
+       struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
+       struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
+       dma_addr_t mapping;
+
+       skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
+       if (unlikely(skb == NULL))
+               return -ENOMEM;
+
+       mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
+                                PCI_DMA_FROMDEVICE);
+#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+       if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
+#else
+       if (unlikely(dma_mapping_error(mapping))) {
+#endif
+               dev_kfree_skb(skb);
+               return -ENOMEM;
+       }
+
+       rx_buf->skb = skb;
+       pci_unmap_addr_set(rx_buf, mapping, mapping);
+
+       rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+       rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+
+       return 0;
+}
+
+/* note that we are not allocating a new skb,
+ * we are just moving one from cons to prod
+ * we are not creating a new mapping,
+ * so there is no need to check for dma_mapping_error().
+ */
+static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
+                              struct sk_buff *skb, u16 cons, u16 prod)
+{
+       struct bnx2x *bp = fp->bp;
+       struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
+       struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
+       struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
+       struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
+
+       pci_dma_sync_single_for_device(bp->pdev,
+                                      pci_unmap_addr(cons_rx_buf, mapping),
+                                      RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
+
+       prod_rx_buf->skb = cons_rx_buf->skb;
+       pci_unmap_addr_set(prod_rx_buf, mapping,
+                          pci_unmap_addr(cons_rx_buf, mapping));
+       *prod_bd = *cons_bd;
+}
+
+#if !defined(__NO_TPA__) /* BNX2X_UPSTREAM */
+static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
+                                            u16 idx)
+{
+       u16 last_max = fp->last_max_sge;
+
+       if (SUB_S16(idx, last_max) > 0)
+               fp->last_max_sge = idx;
+}
+
+static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
+{
+       int i, j;
+
+       for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
+               int idx = RX_SGE_CNT * i - 1;
+
+               for (j = 0; j < 2; j++) {
+                       SGE_MASK_CLEAR_BIT(fp, idx);
+                       idx--;
+               }
+       }
+}
+
+static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
+                                 struct eth_fast_path_rx_cqe *fp_cqe)
+{
+       struct bnx2x *bp = fp->bp;
+       u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
+                                    le16_to_cpu(fp_cqe->len_on_bd)) >>
+                     SGE_PAGE_SHIFT;
+       u16 last_max, last_elem, first_elem;
+       u16 delta = 0;
+       u16 i;
+
+       if (!sge_len)
+               return;
+
+       /* First mark all used pages */
+       for (i = 0; i < sge_len; i++)
+               SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
+
+       DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
+          sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
+
+       /* Here we assume that the last SGE index is the biggest */
+       prefetch((void *)(fp->sge_mask));
+       bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
+
+       last_max = RX_SGE(fp->last_max_sge);
+       last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
+       first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
+
+       /* If ring is not full */
+       if (last_elem + 1 != first_elem)
+               last_elem++;
+
+       /* Now update the prod */
+       for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
+               if (likely(fp->sge_mask[i]))
+                       break;
+
+               fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
+               delta += RX_SGE_MASK_ELEM_SZ;
+       }
+
+       if (delta > 0) {
+               fp->rx_sge_prod += delta;
+               /* clear page-end entries */
+               bnx2x_clear_sge_mask_next_elems(fp);
+       }
+
+       DP(NETIF_MSG_RX_STATUS,
+          "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
+          fp->last_max_sge, fp->rx_sge_prod);
+}
+
+static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
+{
+       /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
+       memset(fp->sge_mask, 0xff,
+              (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
+
+       /* Clear the two last indices in the page to 1:
+          these are the indices that correspond to the "next" element,
+          hence will never be indicated and should be removed from
+          the calculations. */
+       bnx2x_clear_sge_mask_next_elems(fp);
+}
+
+static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
+                           struct sk_buff *skb, u16 cons, u16 prod)
+{
+       struct bnx2x *bp = fp->bp;
+       struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
+       struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
+       struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
+       dma_addr_t mapping;
+
+       /* move empty skb from pool to prod and map it */
+       prod_rx_buf->skb = fp->tpa_pool[queue].skb;
+       mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
+                                bp->rx_buf_size, PCI_DMA_FROMDEVICE);
+       pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
+
+       /* move partial skb from cons to pool (don't unmap yet) */
+       fp->tpa_pool[queue] = *cons_rx_buf;
+
+       /* mark bin state as start - print error if current state != stop */
+       if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
+               BNX2X_ERR("start of bin not in stop [%d]\n", queue);
+
+       fp->tpa_state[queue] = BNX2X_TPA_START;
+
+       /* point prod_bd to new skb */
+       prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+       prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+
+#ifdef BNX2X_STOP_ON_ERROR
+       fp->tpa_queue_used |= (1 << queue);
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+#ifdef _ASM_GENERIC_INT_L64_H
+       DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
+#else
+       DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
+#endif
+#else
+#if defined(__powerpc64__) || defined(_ASM_IA64_TYPES_H)
+       DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
+#else
+       DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
+#endif
+#endif
+          fp->tpa_queue_used);
+#endif
+}
+
+static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+                              struct sk_buff *skb,
+                              struct eth_fast_path_rx_cqe *fp_cqe,
+                              u16 cqe_idx)
+{
+       struct sw_rx_page *rx_pg, old_rx_pg;
+       u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
+       u32 i, frag_len, frag_size, pages;
+       int err;
+       int j;
+
+       frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
+       pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
+
+       /* This is needed in order to enable forwarding support */
+       if (frag_size)
+               skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
+                                              max(frag_size, (u32)len_on_bd));
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (pages >
+           min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
+               BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
+                         pages, cqe_idx);
+               BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
+                         fp_cqe->pkt_len, len_on_bd);
+               bnx2x_panic();
+               return -EINVAL;
+       }
+#endif
+
+       /* Run through the SGL and compose the fragmented skb */
+       for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
+               u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
+
+               /* FW gives the indices of the SGE as if the ring is an array
+                  (meaning that "next" element will consume 2 indices) */
+               frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
+               rx_pg = &fp->rx_page_ring[sge_idx];
+               old_rx_pg = *rx_pg;
+
+               /* If we fail to allocate a substitute page, we simply stop
+                  where we are and drop the whole packet */
+               err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
+               if (unlikely(err)) {
+                       fp->eth_q_stats.rx_skb_alloc_failed++;
+                       return err;
+               }
+
+               /* Unmap the page as we r going to pass it to the stack */
+               pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
+                             SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
+
+               /* Add one frag and update the appropriate fields in the skb */
+               skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
+
+               skb->data_len += frag_len;
+               skb->truesize += frag_len;
+               skb->len += frag_len;
+
+               frag_size -= frag_len;
+       }
+
+       return 0;
+}
+
+static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+                          u16 queue, int pad, int len, union eth_rx_cqe *cqe,
+                          u16 cqe_idx)
+{
+       struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
+       struct sk_buff *skb = rx_buf->skb;
+       /* alloc new skb */
+       struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
+
+       /* Unmap skb in the pool anyway, as we are going to change
+          pool entry status to BNX2X_TPA_STOP even if new skb allocation
+          fails. */
+       pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
+                        bp->rx_buf_size, PCI_DMA_FROMDEVICE);
+
+       if (likely(new_skb)) {
+               /* fix ip xsum and give it to the stack */
+               /* (no need to map the new skb) */
+#ifdef BCM_VLAN
+               int is_vlan_cqe =
+                       (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
+                        PARSING_FLAGS_VLAN);
+               int is_not_hwaccel_vlan_cqe =
+                       (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
+#endif
+
+               prefetch(skb);
+               prefetch(((char *)(skb)) + 128);
+
+#ifdef BNX2X_STOP_ON_ERROR
+               if (pad + len > bp->rx_buf_size) {
+                       BNX2X_ERR("skb_put is about to fail...  "
+                                 "pad %d  len %d  rx_buf_size %d\n",
+                                 pad, len, bp->rx_buf_size);
+                       bnx2x_panic();
+                       return;
+               }
+#endif
+
+               skb_reserve(skb, pad);
+               skb_put(skb, len);
+
+               skb->protocol = eth_type_trans(skb, bp->dev);
+               skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+               {
+                       struct iphdr *iph;
+
+                       iph = (struct iphdr *)skb->data;
+#ifdef BCM_VLAN
+                       /* If there is no Rx VLAN offloading -
+                          take VLAN tag into an account */
+                       if (unlikely(is_not_hwaccel_vlan_cqe))
+                               iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
+#endif
+                       iph->check = 0;
+                       iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
+               }
+
+               if (!bnx2x_fill_frag_skb(bp, fp, skb,
+                                        &cqe->fast_path_cqe, cqe_idx)) {
+#ifdef BCM_VLAN
+                       if ((bp->vlgrp != NULL) && is_vlan_cqe &&
+                           (!is_not_hwaccel_vlan_cqe))
+                               vlan_hwaccel_receive_skb(skb, bp->vlgrp,
+                                               le16_to_cpu(cqe->fast_path_cqe.
+                                                           vlan_tag));
+                       else
+#endif
+                               netif_receive_skb(skb);
+               } else {
+                       DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
+                          " - dropping packet!\n");
+                       dev_kfree_skb(skb);
+               }
+
+#if (LINUX_VERSION_CODE < 0x02061b) /* ! BNX2X_UPSTREAM */
+               bp->dev->last_rx = jiffies;
+#endif
+
+               /* put new skb in bin */
+               fp->tpa_pool[queue].skb = new_skb;
+
+       } else {
+               /* else drop the packet and keep the buffer in the bin */
+               DP(NETIF_MSG_RX_STATUS,
+                  "Failed to allocate new skb - dropping packet!\n");
+               fp->eth_q_stats.rx_skb_alloc_failed++;
+       }
+
+       fp->tpa_state[queue] = BNX2X_TPA_STOP;
+}
+#endif
+
+static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
+                                       struct bnx2x_fastpath *fp,
+                                       u16 bd_prod, u16 rx_comp_prod,
+                                       u16 rx_sge_prod)
+{
+       struct ustorm_eth_rx_producers rx_prods = {0};
+       int i;
+
+       /* Update producers */
+       rx_prods.bd_prod = bd_prod;
+       rx_prods.cqe_prod = rx_comp_prod;
+       rx_prods.sge_prod = rx_sge_prod;
+
+       /*
+        * Make sure that the BD and SGE data is updated before updating the
+        * producers since FW might read the BD/SGE right after the producer
+        * is updated.
+        * This is only applicable for weak-ordered memory model archs such
+        * as IA-64. The following barrier is also mandatory since FW will
+        * assumes BDs must have buffers.
+        */
+       wmb();
+
+       for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
+                      ((u32 *)&rx_prods)[i]);
+
+       mmiowb(); /* keep prod updates ordered */
+
+       DP(NETIF_MSG_RX_STATUS,
+          "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
+          fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
+}
+
+static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
+{
+       struct bnx2x *bp = fp->bp;
+       u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
+       u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
+       int rx_pkt = 0;
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return 0;
+#endif
+
+       /* CQ "next element" is of the size of the regular element,
+          that's why it's ok here */
+       hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
+       if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
+               hw_comp_cons++;
+
+       bd_cons = fp->rx_bd_cons;
+       bd_prod = fp->rx_bd_prod;
+       bd_prod_fw = bd_prod;
+       sw_comp_cons = fp->rx_comp_cons;
+       sw_comp_prod = fp->rx_comp_prod;
+
+       /* Memory barrier necessary as speculative reads of the rx
+        * buffer can be ahead of the index in the status block
+        */
+       rmb();
+
+       DP(NETIF_MSG_RX_STATUS,
+          "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
+          fp->index, hw_comp_cons, sw_comp_cons);
+
+       while (sw_comp_cons != hw_comp_cons) {
+               struct sw_rx_bd *rx_buf = NULL;
+               struct sk_buff *skb;
+               union eth_rx_cqe *cqe;
+               u8 cqe_fp_flags;
+               u16 len, pad;
+
+               comp_ring_cons = RCQ_BD(sw_comp_cons);
+               bd_prod = RX_BD(bd_prod);
+               bd_cons = RX_BD(bd_cons);
+
+               /* Prefetch the page containing the BD descriptor
+                  at producer's index. It will be needed when new skb is
+                  allocated */
+               prefetch((void *)(PAGE_ALIGN((unsigned long)
+                                            (&fp->rx_desc_ring[bd_prod])) -
+                                 PAGE_SIZE + 1));
+
+               cqe = &fp->rx_comp_ring[comp_ring_cons];
+               cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
+
+               DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
+                  "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
+                  cqe_fp_flags, cqe->fast_path_cqe.status_flags,
+                  le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
+                  le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
+                  le16_to_cpu(cqe->fast_path_cqe.pkt_len));
+
+               /* is this a slowpath msg? */
+               if (unlikely(CQE_TYPE(cqe_fp_flags))) {
+                       bnx2x_sp_event(fp, cqe);
+                       goto next_cqe;
+
+               /* this is an rx packet */
+               } else {
+                       rx_buf = &fp->rx_buf_ring[bd_cons];
+                       skb = rx_buf->skb;
+                       len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
+                       pad = cqe->fast_path_cqe.placement_offset;
+
+#if !defined(__NO_TPA__) /* BNX2X_UPSTREAM */
+                       /* If CQE is marked both TPA_START and TPA_END
+                          it is a non-TPA CQE */
+                       if ((!fp->disable_tpa) &&
+                           (TPA_TYPE(cqe_fp_flags) !=
+                                       (TPA_TYPE_START | TPA_TYPE_END))) {
+                               u16 queue = cqe->fast_path_cqe.queue_index;
+
+                               if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
+                                       DP(NETIF_MSG_RX_STATUS,
+                                          "calling tpa_start on queue %d\n",
+                                          queue);
+
+                                       bnx2x_tpa_start(fp, queue, skb,
+                                                       bd_cons, bd_prod);
+                                       goto next_rx;
+                               }
+
+                               if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
+                                       DP(NETIF_MSG_RX_STATUS,
+                                          "calling tpa_stop on queue %d\n",
+                                          queue);
+
+                                       if (!BNX2X_RX_SUM_FIX(cqe))
+                                               BNX2X_ERR("STOP on none TCP "
+                                                         "data\n");
+
+                                       /* This is a size of the linear data
+                                          on this skb */
+                                       len = le16_to_cpu(cqe->fast_path_cqe.
+                                                               len_on_bd);
+                                       bnx2x_tpa_stop(bp, fp, queue, pad,
+                                                   len, cqe, comp_ring_cons);
+#ifdef BNX2X_STOP_ON_ERROR
+                                       if (bp->panic)
+                                               return 0;
+#endif
+
+                                       bnx2x_update_sge_prod(fp,
+                                                       &cqe->fast_path_cqe);
+                                       goto next_cqe;
+                               }
+                       }
+#endif
+
+                       pci_dma_sync_single_for_device(bp->pdev,
+                                       pci_unmap_addr(rx_buf, mapping),
+                                                      pad + RX_COPY_THRESH,
+                                                      PCI_DMA_FROMDEVICE);
+                       prefetch(skb);
+                       prefetch(((char *)(skb)) + 128);
+
+                       /* is this an error packet? */
+                       if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
+                               DP(NETIF_MSG_RX_ERR,
+                                  "ERROR  flags %x  rx packet %u\n",
+                                  cqe_fp_flags, sw_comp_cons);
+                               fp->eth_q_stats.rx_err_discard_pkt++;
+                               goto reuse_rx;
+                       }
+
+                       /* Since we don't have a jumbo ring
+                        * copy small packets if mtu > 1500
+                        */
+                       if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
+                           (len <= RX_COPY_THRESH)) {
+                               struct sk_buff *new_skb;
+
+                               new_skb = netdev_alloc_skb(bp->dev,
+                                                          len + pad);
+                               if (new_skb == NULL) {
+                                       DP(NETIF_MSG_RX_ERR,
+                                          "ERROR  packet dropped "
+                                          "because of alloc failure\n");
+                                       fp->eth_q_stats.rx_skb_alloc_failed++;
+                                       goto reuse_rx;
+                               }
+
+                               /* aligned copy */
+                               skb_copy_from_linear_data_offset(skb, pad,
+                                                   new_skb->data + pad, len);
+                               skb_reserve(new_skb, pad);
+                               skb_put(new_skb, len);
+
+                               bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
+
+                               skb = new_skb;
+
+                       } else
+                       if (likely(bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0)) {
+                               pci_unmap_single(bp->pdev,
+                                       pci_unmap_addr(rx_buf, mapping),
+                                                bp->rx_buf_size,
+                                                PCI_DMA_FROMDEVICE);
+                               skb_reserve(skb, pad);
+                               skb_put(skb, len);
+
+                       } else {
+                               DP(NETIF_MSG_RX_ERR,
+                                  "ERROR  packet dropped because "
+                                  "of alloc failure\n");
+                               fp->eth_q_stats.rx_skb_alloc_failed++;
+reuse_rx:
+                               bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
+                               goto next_rx;
+                       }
+
+                       skb->protocol = eth_type_trans(skb, bp->dev);
+
+                       skb->ip_summed = CHECKSUM_NONE;
+                       if (bp->rx_csum) {
+                               if (likely(BNX2X_RX_CSUM_OK(cqe)))
+                                       skb->ip_summed = CHECKSUM_UNNECESSARY;
+                               else
+                                       fp->eth_q_stats.hw_csum_err++;
+                       }
+               }
+
+               skb_record_rx_queue(skb, fp->index);
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+               vmknetddi_queueops_set_skb_queueid(skb,
+                               VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(fp->index));
+#endif
+
+#ifdef BCM_VLAN
+               if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
+                   (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
+                    PARSING_FLAGS_VLAN))
+                       vlan_hwaccel_receive_skb(skb, bp->vlgrp,
+                               le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
+               else
+#endif
+                       netif_receive_skb(skb);
+
+#if (LINUX_VERSION_CODE < 0x02061b) /* ! BNX2X_UPSTREAM */
+               bp->dev->last_rx = jiffies;
+#endif
+
+next_rx:
+               rx_buf->skb = NULL;
+
+               bd_cons = NEXT_RX_IDX(bd_cons);
+               bd_prod = NEXT_RX_IDX(bd_prod);
+               bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
+               rx_pkt++;
+next_cqe:
+               sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
+               sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
+
+               if (rx_pkt == budget)
+                       break;
+       } /* while */
+
+       fp->rx_bd_cons = bd_cons;
+       fp->rx_bd_prod = bd_prod_fw;
+       fp->rx_comp_cons = sw_comp_cons;
+       fp->rx_comp_prod = sw_comp_prod;
+
+       /* Update producers */
+       bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
+                            fp->rx_sge_prod);
+
+       fp->rx_pkt += rx_pkt;
+       fp->rx_calls++;
+
+       return rx_pkt;
+}
+
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 4000)
+static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie,
+                                    struct pt_regs *regs)
+#else /* BNX2X_UPSTREAM */
+static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
+#endif
+{
+       struct bnx2x_fastpath *fp = fp_cookie;
+       struct bnx2x *bp = fp->bp;
+
+       /* Return here if interrupt is disabled */
+       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+               return IRQ_HANDLED;
+       }
+
+       DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
+          fp->index, fp->sb_id);
+       bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return IRQ_HANDLED;
+#endif
+       /* Handle Rx or Tx according to MSI-X vector */
+       if (fp->is_rx_queue) {
+               prefetch(fp->rx_cons_sb);
+               prefetch(&fp->status_blk->u_status_block.status_block_index);
+
+               napi_schedule(&bnx2x_fp(bp, fp->index, napi));
+
+       } else {
+               prefetch(fp->tx_cons_sb);
+               prefetch(&fp->status_blk->c_status_block.status_block_index);
+
+               bnx2x_update_fpsb_idx(fp);
+               rmb();
+               bnx2x_tx_int(fp);
+
+               /* Re-enable interrupts */
+               bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
+                            le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
+               bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
+                            le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
+       }
+
+       return IRQ_HANDLED;
+}
+#endif
+
+#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 40000)
+static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance,
+                                  struct pt_regs *regs)
+#else /* BNX2X_UPSTREAM */
+static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
+#endif
+{
+       struct bnx2x *bp = netdev_priv(dev_instance);
+       u16 status = bnx2x_ack_int(bp);
+       u16 mask;
+       int i;
+
+       /* Return here if interrupt is shared and it's not for us */
+       if (unlikely(status == 0)) {
+               DP(NETIF_MSG_INTR, "not our interrupt!\n");
+               return IRQ_NONE;
+       }
+       DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
+
+       /* Return here if interrupt is disabled */
+       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+               return IRQ_HANDLED;
+       }
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return IRQ_HANDLED;
+#endif
+
+       for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               mask = 0x2 << fp->sb_id;
+               if (status & mask) {
+                       /* Handle Rx or Tx according to SB id */
+                       if (fp->is_rx_queue) {
+                               prefetch(fp->rx_cons_sb);
+                               prefetch(&fp->status_blk->u_status_block.
+                                                       status_block_index);
+
+                               napi_schedule(&bnx2x_fp(bp, fp->index, napi));
+
+                       } else {
+                               prefetch(fp->tx_cons_sb);
+                               prefetch(&fp->status_blk->c_status_block.
+                                                       status_block_index);
+
+                               bnx2x_update_fpsb_idx(fp);
+                               rmb();
+                               bnx2x_tx_int(fp);
+
+                               /* Re-enable interrupts */
+                               bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
+                                            le16_to_cpu(fp->fp_u_idx),
+                                            IGU_INT_NOP, 1);
+                               bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
+                                            le16_to_cpu(fp->fp_c_idx),
+                                            IGU_INT_ENABLE, 1);
+                       }
+                       status &= ~mask;
+               }
+       }
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       mask = 0x2 << CNIC_SB_ID(bp);
+       if (status & mask) {
+               struct cnic_ops *c_ops = NULL;
+
+               rcu_read_lock();
+               c_ops = rcu_dereference(bp->cnic_ops);
+               if (c_ops)
+                       c_ops->cnic_handler(bp->cnic_data, NULL);
+               rcu_read_unlock();
+
+               status &= ~mask;
+       }
+#endif
+
+       if (unlikely(status & 0x1)) {
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+               queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
+#else
+               queue_work(bnx2x_wq, &bp->sp_task);
+#endif
+
+               status &= ~0x1;
+               if (!status)
+                       return IRQ_HANDLED;
+       }
+
+       if (status)
+               DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
+                  status);
+
+       return IRQ_HANDLED;
+}
+
+/* end of fast path */
+
+static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
+
+/* Link */
+
+/*
+ * General service functions
+ */
+
+static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
+{
+       u32 lock_status;
+       u32 resource_bit = (1 << resource);
+       int func = BP_FUNC(bp);
+       u32 hw_lock_control_reg;
+       int cnt;
+
+       /* Validating that the resource is within range */
+       if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+               DP(NETIF_MSG_HW,
+                  "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
+                  resource, HW_LOCK_MAX_RESOURCE_VALUE);
+               return -EINVAL;
+       }
+
+       if (func <= 5) {
+               hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
+       } else {
+               hw_lock_control_reg =
+                               (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
+       }
+
+       /* Validating that the resource is not already taken */
+       lock_status = REG_RD(bp, hw_lock_control_reg);
+       if (lock_status & resource_bit) {
+               DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
+                  lock_status, resource_bit);
+               return -EEXIST;
+       }
+
+       /* Try for 5 second every 5ms */
+       for (cnt = 0; cnt < 1000; cnt++) {
+               /* Try to acquire the lock */
+               REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
+               lock_status = REG_RD(bp, hw_lock_control_reg);
+               if (lock_status & resource_bit)
+                       return 0;
+
+               msleep(5);
+       }
+       DP(NETIF_MSG_HW, "Timeout\n");
+       return -EAGAIN;
+}
+
+static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
+{
+       u32 lock_status;
+       u32 resource_bit = (1 << resource);
+       int func = BP_FUNC(bp);
+       u32 hw_lock_control_reg;
+
+       /* Validating that the resource is within range */
+       if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+               DP(NETIF_MSG_HW,
+                  "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
+                  resource, HW_LOCK_MAX_RESOURCE_VALUE);
+               return -EINVAL;
+       }
+
+       if (func <= 5) {
+               hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
+       } else {
+               hw_lock_control_reg =
+                               (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
+       }
+
+       /* Validating that the resource is currently taken */
+       lock_status = REG_RD(bp, hw_lock_control_reg);
+       if (!(lock_status & resource_bit)) {
+               DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
+                  lock_status, resource_bit);
+               return -EFAULT;
+       }
+
+       REG_WR(bp, hw_lock_control_reg, resource_bit);
+       return 0;
+}
+
+/* HW Lock for shared dual port PHYs */
+static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
+{
+       mutex_lock(&bp->port.phy_mutex);
+
+       if (bp->port.need_hw_lock)
+               bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
+}
+
+static void bnx2x_release_phy_lock(struct bnx2x *bp)
+{
+       if (bp->port.need_hw_lock)
+               bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
+
+       mutex_unlock(&bp->port.phy_mutex);
+}
+
+int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
+{
+       /* The GPIO should be swapped if swap register is set and active */
+       int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
+                        REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
+       int gpio_shift = gpio_num +
+                       (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
+       u32 gpio_mask = (1 << gpio_shift);
+       u32 gpio_reg;
+       int value;
+
+       if (gpio_num > MISC_REGISTERS_GPIO_3) {
+               BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
+               return -EINVAL;
+       }
+
+       /* read GPIO value */
+       gpio_reg = REG_RD(bp, MISC_REG_GPIO);
+
+       /* get the requested pin value */
+       if ((gpio_reg & gpio_mask) == gpio_mask)
+               value = 1;
+       else
+               value = 0;
+
+       DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
+
+       return value;
+}
+
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
+{
+       /* The GPIO should be swapped if swap register is set and active */
+       int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
+                        REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
+       int gpio_shift = gpio_num +
+                       (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
+       u32 gpio_mask = (1 << gpio_shift);
+       u32 gpio_reg;
+
+       if (gpio_num > MISC_REGISTERS_GPIO_3) {
+               BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
+               return -EINVAL;
+       }
+
+       bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+       /* read GPIO and mask except the float bits */
+       gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
+
+       switch (mode) {
+       case MISC_REGISTERS_GPIO_OUTPUT_LOW:
+               DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
+                  gpio_num, gpio_shift);
+               /* clear FLOAT and set CLR */
+               gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+               gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
+               break;
+
+       case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
+               DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
+                  gpio_num, gpio_shift);
+               /* clear FLOAT and set SET */
+               gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+               gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
+               break;
+
+       case MISC_REGISTERS_GPIO_INPUT_HI_Z:
+               DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
+                  gpio_num, gpio_shift);
+               /* set FLOAT */
+               gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+               break;
+
+       default:
+               break;
+       }
+
+       REG_WR(bp, MISC_REG_GPIO, gpio_reg);
+       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+
+       return 0;
+}
+
+int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
+{
+       /* The GPIO should be swapped if swap register is set and active */
+       int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
+                        REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
+       int gpio_shift = gpio_num +
+                       (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
+       u32 gpio_mask = (1 << gpio_shift);
+       u32 gpio_reg;
+
+       if (gpio_num > MISC_REGISTERS_GPIO_3) {
+               BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
+               return -EINVAL;
+       }
+
+       bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+       /* read GPIO int */
+       gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
+
+       switch (mode) {
+       case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
+               DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
+                                  "output low\n", gpio_num, gpio_shift);
+               /* clear SET and set CLR */
+               gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
+               gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
+               break;
+
+       case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
+               DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
+                                  "output high\n", gpio_num, gpio_shift);
+               /* clear CLR and set SET */
+               gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
+               gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
+               break;
+
+       default:
+               break;
+       }
+
+       REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
+       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+
+       return 0;
+}
+
+static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
+{
+       u32 spio_mask = (1 << spio_num);
+       u32 spio_reg;
+
+       if ((spio_num < MISC_REGISTERS_SPIO_4) ||
+           (spio_num > MISC_REGISTERS_SPIO_7)) {
+               BNX2X_ERR("Invalid SPIO %d\n", spio_num);
+               return -EINVAL;
+       }
+
+       bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
+       /* read SPIO and mask except the float bits */
+       spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
+
+       switch (mode) {
+       case MISC_REGISTERS_SPIO_OUTPUT_LOW:
+               DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
+               /* clear FLOAT and set CLR */
+               spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
+               spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
+               break;
+
+       case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
+               DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
+               /* clear FLOAT and set SET */
+               spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
+               spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
+               break;
+
+       case MISC_REGISTERS_SPIO_INPUT_HI_Z:
+               DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
+               /* set FLOAT */
+               spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
+               break;
+
+       default:
+               break;
+       }
+
+       REG_WR(bp, MISC_REG_SPIO, spio_reg);
+       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
+
+       return 0;
+}
+
+static void bnx2x_calc_fc_adv(struct bnx2x *bp)
+{
+       switch (bp->link_vars.ieee_fc &
+               MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
+       case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
+               bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
+                                         ADVERTISED_Pause);
+               break;
+
+       case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
+               bp->port.advertising |= (ADVERTISED_Asym_Pause |
+                                        ADVERTISED_Pause);
+               break;
+
+       case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
+               bp->port.advertising |= ADVERTISED_Asym_Pause;
+               break;
+
+       default:
+               bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
+                                         ADVERTISED_Pause);
+               break;
+       }
+}
+
+static void bnx2x_link_report(struct bnx2x *bp)
+{
+       if (bp->state == BNX2X_STATE_DISABLED) {
+               netif_carrier_off(bp->dev);
+               printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
+               return;
+       }
+
+       if (bp->link_vars.link_up) {
+               if (bp->state == BNX2X_STATE_OPEN)
+                       netif_carrier_on(bp->dev);
+               printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
+
+               printk("%d Mbps ", bp->link_vars.line_speed);
+
+               if (bp->link_vars.duplex == DUPLEX_FULL)
+                       printk("full duplex");
+               else
+                       printk("half duplex");
+
+               if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
+                       if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
+                               printk(", receive ");
+                               if (bp->link_vars.flow_ctrl &
+                                   BNX2X_FLOW_CTRL_TX)
+                                       printk("& transmit ");
+                       } else {
+                               printk(", transmit ");
+                       }
+                       printk("flow control ON");
+               }
+               printk("\n");
+
+       } else { /* link_down */
+               netif_carrier_off(bp->dev);
+               printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
+       }
+}
+
+static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
+{
+       if (!BP_NOMCP(bp)) {
+               u8 rc;
+
+               /* Initialize link parameters structure variables */
+               /* It is recommended to turn off RX FC for jumbo frames
+                  for better performance */
+               if (bp->dev->mtu > 5000)
+                       bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
+               else
+                       bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
+
+               bnx2x_acquire_phy_lock(bp);
+
+               if (load_mode == LOAD_DIAG)
+                       bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
+
+               rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
+
+               bnx2x_release_phy_lock(bp);
+
+               bnx2x_calc_fc_adv(bp);
+
+               if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
+                       bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
+                       bnx2x_link_report(bp);
+               }
+
+               return rc;
+       }
+       BNX2X_ERR("Bootcode is missing - can not initialize link\n");
+       return -EINVAL;
+}
+
+static void bnx2x_link_set(struct bnx2x *bp)
+{
+       if (!BP_NOMCP(bp)) {
+               bnx2x_acquire_phy_lock(bp);
+               bnx2x_phy_init(&bp->link_params, &bp->link_vars);
+               bnx2x_release_phy_lock(bp);
+
+               bnx2x_calc_fc_adv(bp);
+       } else
+               BNX2X_ERR("Bootcode is missing - can not set link\n");
+}
+
+static void bnx2x__link_reset(struct bnx2x *bp)
+{
+       if (!BP_NOMCP(bp)) {
+               bnx2x_acquire_phy_lock(bp);
+               bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
+               bnx2x_release_phy_lock(bp);
+       } else
+               BNX2X_ERR("Bootcode is missing - can not reset link\n");
+}
+
+static u8 bnx2x_link_test(struct bnx2x *bp)
+{
+       u8 rc;
+
+       bnx2x_acquire_phy_lock(bp);
+       rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
+       bnx2x_release_phy_lock(bp);
+
+       return rc;
+}
+
+static void bnx2x_init_port_minmax(struct bnx2x *bp)
+{
+       u32 r_param = bp->link_vars.line_speed / 8;
+       u32 fair_periodic_timeout_usec;
+       u32 t_fair;
+
+       memset(&(bp->cmng.rs_vars), 0,
+              sizeof(struct rate_shaping_vars_per_port));
+       memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
+
+       /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
+       bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
+
+       /* this is the threshold below which no timer arming will occur
+          1.25 coefficient is for the threshold to be a little bigger
+          than the real time, to compensate for timer in-accuracy */
+       bp->cmng.rs_vars.rs_threshold =
+                               (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
+
+       /* resolution of fairness timer */
+       fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
+       /* for 10G it is 1000usec. for 1G it is 10000usec. */
+       t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
+
+       /* this is the threshold below which we won't arm the timer anymore */
+       bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
+
+       /* we multiply by 1e3/8 to get bytes/msec.
+          We don't want the credits to pass a credit
+          of the t_fair*FAIR_MEM (algorithm resolution) */
+       bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
+       /* since each tick is 4 usec */
+       bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
+}
+
+/* Calculates the sum of vn_min_rates.
+   It's needed for further normalizing of the min_rates.
+   Returns:
+     sum of vn_min_rates.
+       or
+     0 - if all the min_rates are 0.
+     In the later case fainess algorithm should be deactivated.
+     If not all min_rates are zero then those that are zeroes will be set to 1.
+ */
+static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
+{
+       int all_zero = 1;
+       int port = BP_PORT(bp);
+       int vn;
+
+       bp->vn_weight_sum = 0;
+       for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+               int func = 2*vn + port;
+               u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+               u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+                                  FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
+
+               /* Skip hidden vns */
+               if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
+                       continue;
+
+               /* If min rate is zero - set it to 1 */
+               if (!vn_min_rate)
+                       vn_min_rate = DEF_MIN_RATE;
+               else
+                       all_zero = 0;
+
+               bp->vn_weight_sum += vn_min_rate;
+       }
+
+       /* ... only if all min rates are zeros - disable fairness */
+       if (all_zero)
+               bp->vn_weight_sum = 0;
+}
+
+static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
+{
+       struct rate_shaping_vars_per_vn m_rs_vn;
+       struct fairness_vars_per_vn m_fair_vn;
+       u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+       u16 vn_min_rate, vn_max_rate;
+       int i;
+
+       /* If function is hidden - set min and max to zeroes */
+       if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
+               vn_min_rate = 0;
+               vn_max_rate = 0;
+
+       } else {
+               vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+                               FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
+               /* If fairness is enabled (not all min rates are zeroes) and
+                  if current min rate is zero - set it to 1.
+                  This is a requirement of the algorithm. */
+               if (bp->vn_weight_sum && (vn_min_rate == 0))
+                       vn_min_rate = DEF_MIN_RATE;
+               vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
+                               FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+       }
+
+       DP(NETIF_MSG_IFUP,
+          "func %d: vn_min_rate=%d  vn_max_rate=%d  vn_weight_sum=%d\n",
+          func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
+
+       memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
+       memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
+
+       /* global vn counter - maximal Mbps for this vn */
+       m_rs_vn.vn_counter.rate = vn_max_rate;
+
+       /* quota - number of bytes transmitted in this period */
+       m_rs_vn.vn_counter.quota =
+                               (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
+
+       if (bp->vn_weight_sum) {
+               /* credit for each period of the fairness algorithm:
+                  number of bytes in T_FAIR (the vn share the port rate).
+                  vn_weight_sum should not be larger than 10000, thus
+                  T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
+                  than zero */
+               m_fair_vn.vn_credit_delta =
+                       max((u32)(vn_min_rate * (T_FAIR_COEF /
+                                                (8 * bp->vn_weight_sum))),
+                           (u32)(bp->cmng.fair_vars.fair_threshold * 2));
+               DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
+                  m_fair_vn.vn_credit_delta);
+       }
+
+       /* Store it to internal memory */
+       for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
+               REG_WR(bp, BAR_XSTRORM_INTMEM +
+                      XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
+                      ((u32 *)(&m_rs_vn))[i]);
+
+       for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
+               REG_WR(bp, BAR_XSTRORM_INTMEM +
+                      XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
+                      ((u32 *)(&m_fair_vn))[i]);
+}
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+static void bnx2x_init_cos_credit(struct bnx2x *bp)
+{
+       struct fairness_vars_per_vn m_fair_vn;
+       int func = BP_FUNC(bp);
+       int i, cos;
+
+       memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
+
+       for (cos = 0; cos < BNX2X_MAX_COS; cos++) {
+               if (bp->cos_min_rate[cos]) {
+                       m_fair_vn.cos_credit_delta[cos] =
+                       max((u32)(bp->cos_min_rate[cos] *
+                                 (T_FAIR_COEF / (8 * bp->cos_weight_sum))),
+                           (u32)(bp->cmng.fair_vars.fair_threshold * 2));
+               }
+               DP(NETIF_MSG_IFUP, "cos_credit_delta[%d] = %d\n",
+                  cos, m_fair_vn.cos_credit_delta[cos]);
+       }
+
+       for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
+               REG_WR(bp, BAR_XSTRORM_INTMEM +
+                      XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
+                      ((u32 *)(&m_fair_vn))[i]);
+}
+#endif
+
+/* This function is called upon link interrupt */
+static void bnx2x_link_attn(struct bnx2x *bp)
+{
+       /* Make sure that we are synced with the current statistics */
+       bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+
+       bnx2x_link_update(&bp->link_params, &bp->link_vars);
+
+       if (bp->link_vars.link_up) {
+
+               /* dropless flow control */
+               if (CHIP_IS_E1H(bp) && bp->dropless_fc) {
+                       int port = BP_PORT(bp);
+                       u32 pause_enabled = 0;
+
+#ifdef BNX2X_SAFC
+                       if ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ||
+                           (bp->flags & SAFC_TX_FLAG))
+#else /* BNX2X_UPSTREAM */
+                       if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
+#endif
+                               pause_enabled = 1;
+
+                       REG_WR(bp, BAR_USTRORM_INTMEM +
+                              USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
+                              pause_enabled);
+               }
+
+               if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
+                       struct host_port_stats *pstats;
+
+                       pstats = bnx2x_sp(bp, port_stats);
+                       /* reset old bmac stats */
+                       memset(&(pstats->mac_stx[0]), 0,
+                              sizeof(struct mac_stx));
+               }
+               if ((bp->state == BNX2X_STATE_OPEN) ||
+                   (bp->state == BNX2X_STATE_DISABLED))
+                       bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
+       }
+
+       /* indicate link status */
+       bnx2x_link_report(bp);
+
+       if (IS_E1HMF(bp)) {
+               int port = BP_PORT(bp);
+               int func;
+               int vn;
+
+               /* Set the attention towards other drivers on the same port */
+               for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+                       if (vn == BP_E1HVN(bp))
+                               continue;
+
+                       func = ((vn << 1) | port);
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
+                              (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
+               }
+
+               if (bp->link_vars.link_up) {
+                       int i;
+
+                       /* Init rate shaping and fairness contexts */
+                       bnx2x_init_port_minmax(bp);
+
+                       for (vn = VN_0; vn < E1HVN_MAX; vn++)
+                               bnx2x_init_vn_minmax(bp, 2*vn + port);
+
+                       /* Store it to internal memory */
+                       for (i = 0;
+                            i < sizeof(struct cmng_struct_per_port) / 4; i++)
+                               REG_WR(bp, BAR_XSTRORM_INTMEM +
+                                 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
+                                      ((u32 *)(&bp->cmng))[i]);
+               }
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       } else {
+               if (bp->link_vars.link_up && bp->cos_weight_sum) {
+                       int port = BP_PORT(bp);
+                       int i;
+
+                       /* Init fairness context */
+                       bnx2x_init_port_minmax(bp);
+
+                       bnx2x_init_cos_credit(bp);
+
+                       /* Store it to internal memory */
+                       for (i = 0;
+                            i < sizeof(struct cmng_struct_per_port) / 4; i++)
+                               REG_WR(bp, BAR_XSTRORM_INTMEM +
+                                 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
+                                      ((u32 *)(&bp->cmng))[i]);
+               }
+#endif
+       }
+}
+
+static void bnx2x__link_status_update(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+
+       if (bp->state != BNX2X_STATE_OPEN)
+               return;
+
+       bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
+
+       if (bp->link_vars.link_up)
+               bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
+       else
+               bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+
+       bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+       bnx2x_calc_vn_weight_sum(bp);
+
+       /* indicate link status */
+       bnx2x_link_report(bp);
+}
+
+static void bnx2x_pmf_update(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       u32 val;
+
+       bp->port.pmf = 1;
+       DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
+
+       /* enable nig attention */
+       val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
+       REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
+       REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
+
+       bnx2x_stats_handle(bp, STATS_EVENT_PMF);
+}
+
+/* end of Link */
+
+/* slow path */
+
+/*
+ * General service functions
+ */
+
+/* send the MCP a request, block until there is a reply */
+u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
+{
+       int func = BP_FUNC(bp);
+       u32 seq = ++bp->fw_seq;
+       u32 rc = 0;
+       u32 cnt = 1;
+       u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
+
+       SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
+       DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
+
+       do {
+               /* let the FW do it's magic ... */
+               msleep(delay);
+
+               rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
+
+               /* Give the FW up to 2 second (200*10ms) */
+       } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
+
+       DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
+          cnt*delay, rc, seq);
+
+       /* is this a reply to our command? */
+       if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
+               rc &= FW_MSG_CODE_MASK;
+       else {
+               /* FW BUG! */
+               BNX2X_ERR("FW failed to respond!\n");
+               bnx2x_fw_dump(bp);
+               rc = 0;
+       }
+
+       return rc;
+}
+
+static void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
+static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set);
+static void bnx2x_set_rx_mode(struct net_device *dev);
+
+static void bnx2x_e1h_disable(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int i;
+
+       bp->rx_mode = BNX2X_RX_MODE_NONE;
+       bnx2x_set_storm_rx_mode(bp);
+
+       netif_tx_disable(bp->dev);
+       bp->dev->trans_start = jiffies; /* prevent tx timeout */
+
+       REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
+
+       bnx2x_set_mac_addr_e1h(bp, 0);
+
+       for (i = 0; i < MC_HASH_SIZE; i++)
+               REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
+
+       netif_carrier_off(bp->dev);
+}
+
+static void bnx2x_e1h_enable(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+
+       REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
+
+       bnx2x_set_mac_addr_e1h(bp, 1);
+
+       /* Tx queue should be only reenabled */
+       netif_tx_wake_all_queues(bp->dev);
+
+       /* Initialize the receive filter. */
+       bnx2x_set_rx_mode(bp->dev);
+}
+
+static void bnx2x_update_min_max(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int vn, i;
+
+       /* Init rate shaping and fairness contexts */
+       bnx2x_init_port_minmax(bp);
+
+       bnx2x_calc_vn_weight_sum(bp);
+
+       for (vn = VN_0; vn < E1HVN_MAX; vn++)
+               bnx2x_init_vn_minmax(bp, 2*vn + port);
+
+       if (bp->port.pmf) {
+               int func;
+
+               /* Set the attention towards other drivers on the same port */
+               for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+                       if (vn == BP_E1HVN(bp))
+                               continue;
+
+                       func = ((vn << 1) | port);
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
+                              (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
+               }
+
+               /* Store it to internal memory */
+               for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
+                       REG_WR(bp, BAR_XSTRORM_INTMEM +
+                              XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
+                              ((u32 *)(&bp->cmng))[i]);
+       }
+}
+
+static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
+{
+       int func = BP_FUNC(bp);
+
+       DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
+       bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+
+       if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
+
+               if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
+                       DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
+                       bp->state = BNX2X_STATE_DISABLED;
+
+                       bnx2x_e1h_disable(bp);
+               } else {
+                       DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
+                       bp->state = BNX2X_STATE_OPEN;
+
+                       bnx2x_e1h_enable(bp);
+               }
+               dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
+       }
+       if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
+
+               bnx2x_update_min_max(bp);
+               dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
+       }
+
+       /* Report results to MCP */
+       if (dcc_event)
+               bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE);
+       else
+               bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK);
+}
+
+/* the slow path queue is odd since completions arrive on the fastpath ring */
+static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
+                        u32 data_hi, u32 data_lo, int common)
+{
+       int func = BP_FUNC(bp);
+
+       DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
+          "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
+          (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
+          (void *)bp->spq_prod_bd - (void *)bp->spq), command,
+          HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return -EIO;
+#endif
+
+       spin_lock_bh(&bp->spq_lock);
+
+       if (!bp->spq_left) {
+               BNX2X_ERR("BUG! SPQ ring full!\n");
+               spin_unlock_bh(&bp->spq_lock);
+               bnx2x_panic();
+               return -EBUSY;
+       }
+
+       /* CID needs port number to be encoded int it */
+       bp->spq_prod_bd->hdr.conn_and_cmd_data =
+                       cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
+                                    HW_CID(bp, cid)));
+       bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
+       if (common)
+               bp->spq_prod_bd->hdr.type |=
+                       cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
+
+       bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
+       bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
+
+       bp->spq_left--;
+
+       if (bp->spq_prod_bd == bp->spq_last_bd) {
+               bp->spq_prod_bd = bp->spq;
+               bp->spq_prod_idx = 0;
+               DP(NETIF_MSG_TIMER, "end of spq\n");
+
+       } else {
+               bp->spq_prod_bd++;
+               bp->spq_prod_idx++;
+       }
+
+       /* Make sure that BD data is updated before writing the producer */
+       wmb();
+
+       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
+              bp->spq_prod_idx);
+
+       mmiowb();
+
+       spin_unlock_bh(&bp->spq_lock);
+       return 0;
+}
+
+/* acquire split MCP access lock register */
+static int bnx2x_acquire_alr(struct bnx2x *bp)
+{
+       u32 i, j, val;
+       int rc = 0;
+
+       might_sleep();
+       i = 100;
+       for (j = 0; j < i*10; j++) {
+               val = (1UL << 31);
+               REG_WR(bp, GRCBASE_MCP + 0x9c, val);
+               val = REG_RD(bp, GRCBASE_MCP + 0x9c);
+               if (val & (1L << 31))
+                       break;
+
+               msleep(5);
+       }
+       if (!(val & (1L << 31))) {
+               BNX2X_ERR("Cannot acquire MCP access lock register\n");
+               rc = -EBUSY;
+       }
+
+       return rc;
+}
+
+/* release split MCP access lock register */
+static void bnx2x_release_alr(struct bnx2x *bp)
+{
+       u32 val = 0;
+
+       REG_WR(bp, GRCBASE_MCP + 0x9c, val);
+}
+
+static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
+{
+       struct host_def_status_block *def_sb = bp->def_status_blk;
+       u16 rc = 0;
+
+       barrier(); /* status block is written to by the chip */
+       if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
+               bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
+               rc |= 1;
+       }
+       if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
+               bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
+               rc |= 2;
+       }
+       if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
+               bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
+               rc |= 4;
+       }
+       if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
+               bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
+               rc |= 8;
+       }
+       if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
+               bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
+               rc |= 16;
+       }
+       return rc;
+}
+
+/*
+ * slow path service functions
+ */
+
+static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
+{
+       int port = BP_PORT(bp);
+       u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
+                      COMMAND_REG_ATTN_BITS_SET);
+       u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+                             MISC_REG_AEU_MASK_ATTN_FUNC_0;
+       u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
+                                      NIG_REG_MASK_INTERRUPT_PORT0;
+       u32 aeu_mask;
+       u32 nig_mask = 0;
+
+       if (bp->attn_state & asserted)
+               BNX2X_ERR("IGU ERROR\n");
+
+       bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+       aeu_mask = REG_RD(bp, aeu_addr);
+
+       DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
+          aeu_mask, asserted);
+       aeu_mask &= ~(asserted & 0xff);
+       DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
+
+       REG_WR(bp, aeu_addr, aeu_mask);
+       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+       DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
+       bp->attn_state |= asserted;
+       DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
+
+       if (asserted & ATTN_HARD_WIRED_MASK) {
+               if (asserted & ATTN_NIG_FOR_FUNC) {
+
+                       bnx2x_acquire_phy_lock(bp);
+
+                       /* save nig interrupt mask */
+                       nig_mask = REG_RD(bp, nig_int_mask_addr);
+                       REG_WR(bp, nig_int_mask_addr, 0);
+
+                       bnx2x_link_attn(bp);
+
+                       /* handle unicore attn? */
+               }
+               if (asserted & ATTN_SW_TIMER_4_FUNC)
+                       DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
+
+               if (asserted & GPIO_2_FUNC)
+                       DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
+
+               if (asserted & GPIO_3_FUNC)
+                       DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
+
+               if (asserted & GPIO_4_FUNC)
+                       DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
+
+               if (port == 0) {
+                       if (asserted & ATTN_GENERAL_ATTN_1) {
+                               DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
+                               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
+                       }
+                       if (asserted & ATTN_GENERAL_ATTN_2) {
+                               DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
+                               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
+                       }
+                       if (asserted & ATTN_GENERAL_ATTN_3) {
+                               DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
+                               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
+                       }
+               } else {
+                       if (asserted & ATTN_GENERAL_ATTN_4) {
+                               DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
+                               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
+                       }
+                       if (asserted & ATTN_GENERAL_ATTN_5) {
+                               DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
+                               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
+                       }
+                       if (asserted & ATTN_GENERAL_ATTN_6) {
+                               DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
+                               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
+                       }
+               }
+
+       } /* if hardwired */
+
+       DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
+          asserted, hc_addr);
+       REG_WR(bp, hc_addr, asserted);
+
+       /* now set back the mask */
+       if (asserted & ATTN_NIG_FOR_FUNC) {
+               REG_WR(bp, nig_int_mask_addr, nig_mask);
+               bnx2x_release_phy_lock(bp);
+       }
+}
+
+static inline void bnx2x_fan_failure(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+
+       /* mark the failure */
+       bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+       bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
+       SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
+                bp->link_params.ext_phy_config);
+
+       /* log the failure */
+       printk(KERN_ERR PFX "Fan Failure on Network Controller %s has caused"
+              " the driver to shutdown the card to prevent permanent"
+              " damage.  Please contact Dell Support for assistance\n",
+              bp->dev->name);
+}
+
+static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
+{
+       int port = BP_PORT(bp);
+       int reg_offset;
+       u32 val, swap_val, swap_override;
+
+       reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+                            MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
+
+       if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
+
+               val = REG_RD(bp, reg_offset);
+               val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
+               REG_WR(bp, reg_offset, val);
+
+               BNX2X_ERR("SPIO5 hw attention\n");
+
+               /* Fan failure attention */
+               switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+                       /* Low power mode is controlled by GPIO 2 */
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
+                                      MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+                       /* The PHY reset is controlled by GPIO 1 */
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                                      MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+                       /* The PHY reset is controlled by GPIO 1 */
+                       /* fake the port number to cancel the swap done in
+                          set_gpio() */
+                       swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
+                       swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
+                       port = (swap_val && swap_override) ^ 1;
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
+                                      MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+                       break;
+
+               default:
+                       break;
+               }
+               bnx2x_fan_failure(bp);
+       }
+
+       if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
+                   AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
+               bnx2x_acquire_phy_lock(bp);
+               bnx2x_handle_module_detect_int(&bp->link_params);
+               bnx2x_release_phy_lock(bp);
+       }
+
+       if (attn & HW_INTERRUT_ASSERT_SET_0) {
+
+               val = REG_RD(bp, reg_offset);
+               val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
+               REG_WR(bp, reg_offset, val);
+
+               BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
+                         (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
+               bnx2x_panic();
+       }
+}
+
+static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
+{
+       u32 val;
+
+       if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
+
+               val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
+               BNX2X_ERR("DB hw attention 0x%x\n", val);
+               /* DORQ discard attention */
+               if (val & 0x2)
+                       BNX2X_ERR("FATAL error from DORQ\n");
+       }
+
+       if (attn & HW_INTERRUT_ASSERT_SET_1) {
+
+               int port = BP_PORT(bp);
+               int reg_offset;
+
+               reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
+                                    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
+
+               val = REG_RD(bp, reg_offset);
+               val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
+               REG_WR(bp, reg_offset, val);
+
+               BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
+                         (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
+               bnx2x_panic();
+       }
+}
+
+static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
+{
+       u32 val;
+
+       if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
+
+               val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
+               BNX2X_ERR("CFC hw attention 0x%x\n", val);
+               /* CFC error attention */
+               if (val & 0x2)
+                       BNX2X_ERR("FATAL error from CFC\n");
+       }
+
+       if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
+
+               val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
+               BNX2X_ERR("PXP hw attention 0x%x\n", val);
+               /* RQ_USDMDP_FIFO_OVERFLOW */
+               if (val & 0x18000)
+                       BNX2X_ERR("FATAL error from PXP\n");
+       }
+
+       if (attn & HW_INTERRUT_ASSERT_SET_2) {
+
+               int port = BP_PORT(bp);
+               int reg_offset;
+
+               reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
+                                    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
+
+               val = REG_RD(bp, reg_offset);
+               val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
+               REG_WR(bp, reg_offset, val);
+
+               BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
+                         (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
+               bnx2x_panic();
+       }
+}
+
+static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
+{
+       u32 val;
+
+       if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
+
+               if (attn & BNX2X_PMF_LINK_ASSERT) {
+                       int func = BP_FUNC(bp);
+
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
+                       val = SHMEM_RD(bp, func_mb[func].drv_status);
+                       if (val & DRV_STATUS_DCC_EVENT_MASK)
+                               bnx2x_dcc_event(bp,
+                                           (val & DRV_STATUS_DCC_EVENT_MASK));
+                       bnx2x__link_status_update(bp);
+                       if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
+                               bnx2x_pmf_update(bp);
+
+               } else if (attn & BNX2X_MC_ASSERT_BITS) {
+
+                       BNX2X_ERR("MC assert!\n");
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
+                       bnx2x_panic();
+
+               } else if (attn & BNX2X_MCP_ASSERT) {
+
+                       BNX2X_ERR("MCP assert!\n");
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
+                       bnx2x_fw_dump(bp);
+
+               } else
+                       BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
+       }
+
+       if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
+               BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
+               if (attn & BNX2X_GRC_TIMEOUT) {
+                       val = CHIP_IS_E1H(bp) ?
+                               REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
+                       BNX2X_ERR("GRC time-out 0x%08x\n", val);
+               }
+               if (attn & BNX2X_GRC_RSV) {
+                       val = CHIP_IS_E1H(bp) ?
+                               REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
+                       BNX2X_ERR("GRC reserved 0x%08x\n", val);
+               }
+               REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
+       }
+}
+
+static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
+{
+       struct attn_route attn;
+       struct attn_route group_mask;
+       int port = BP_PORT(bp);
+       int index;
+       u32 reg_addr;
+       u32 val;
+       u32 aeu_mask;
+
+       /* need to take HW lock because MCP or other port might also
+          try to handle this event */
+       bnx2x_acquire_alr(bp);
+
+       attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
+       attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
+       attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
+       attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
+       DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
+          attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
+
+       for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+               if (deasserted & (1 << index)) {
+                       group_mask = bp->attn_group[index];
+
+                       DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
+                          index, group_mask.sig[0], group_mask.sig[1],
+                          group_mask.sig[2], group_mask.sig[3]);
+
+                       bnx2x_attn_int_deasserted3(bp,
+                                       attn.sig[3] & group_mask.sig[3]);
+                       bnx2x_attn_int_deasserted1(bp,
+                                       attn.sig[1] & group_mask.sig[1]);
+                       bnx2x_attn_int_deasserted2(bp,
+                                       attn.sig[2] & group_mask.sig[2]);
+                       bnx2x_attn_int_deasserted0(bp,
+                                       attn.sig[0] & group_mask.sig[0]);
+
+                       if ((attn.sig[0] & group_mask.sig[0] &
+                                               HW_PRTY_ASSERT_SET_0) ||
+                           (attn.sig[1] & group_mask.sig[1] &
+                                               HW_PRTY_ASSERT_SET_1) ||
+                           (attn.sig[2] & group_mask.sig[2] &
+                                               HW_PRTY_ASSERT_SET_2))
+                               BNX2X_ERR("FATAL HW block parity attention\n");
+               }
+       }
+
+       bnx2x_release_alr(bp);
+
+       reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
+
+       val = ~deasserted;
+       DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
+          val, reg_addr);
+       REG_WR(bp, reg_addr, val);
+
+       if (~bp->attn_state & deasserted)
+               BNX2X_ERR("IGU ERROR\n");
+
+       reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
+
+       bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+       aeu_mask = REG_RD(bp, reg_addr);
+
+       DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
+          aeu_mask, deasserted);
+       aeu_mask |= (deasserted & 0xff);
+       DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
+
+       REG_WR(bp, reg_addr, aeu_mask);
+       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+       DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
+       bp->attn_state &= ~deasserted;
+       DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
+}
+
+static void bnx2x_attn_int(struct bnx2x *bp)
+{
+       /* read local copy of bits */
+       u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
+                                                               attn_bits);
+       u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
+                                                               attn_bits_ack);
+       u32 attn_state = bp->attn_state;
+
+       /* look for changed bits */
+       u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
+       u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
+
+       DP(NETIF_MSG_HW,
+          "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
+          attn_bits, attn_ack, asserted, deasserted);
+
+       if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
+               BNX2X_ERR("BAD attention state\n");
+
+       /* handle bits that were raised */
+       if (asserted)
+               bnx2x_attn_int_asserted(bp, asserted);
+
+       if (deasserted)
+               bnx2x_attn_int_deasserted(bp, deasserted);
+}
+
+#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) || (VMWARE_ESX_DDK_VERSION >= 40000) /* BNX2X_UPSTREAM */
+static void bnx2x_sp_task(struct work_struct *work)
+{
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
+#else
+       struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
+#endif
+#else
+static void bnx2x_sp_task(void *data)
+{
+       struct bnx2x *bp = (struct bnx2x *)data;
+#endif
+       u16 status;
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       bp->sp_running = 1;
+       smp_mb(); /* make sure close can see this */
+#endif
+
+       /* Return here if interrupt is disabled */
+       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+               return;
+#else
+               goto sp_task_exit;
+#endif
+       }
+
+       status = bnx2x_update_dsb_idx(bp);
+/*     if (status == 0)                                     */
+/*             BNX2X_ERR("spurious slowpath interrupt!\n"); */
+
+       DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
+
+       /* HW attentions */
+       if (status & 0x1)
+               bnx2x_attn_int(bp);
+
+       bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
+                    IGU_INT_NOP, 1);
+       bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
+                    IGU_INT_NOP, 1);
+       bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
+                    IGU_INT_NOP, 1);
+       bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
+                    IGU_INT_NOP, 1);
+       bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
+                    IGU_INT_ENABLE, 1);
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+sp_task_exit:
+       bp->sp_running = 0;
+       smp_mb(); /* make sure close can see this */
+#endif
+}
+
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 40000)
+static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance,
+                                    struct pt_regs *regs)
+#else /* BNX2X_UPSTREAM */
+static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
+#endif
+{
+       struct net_device *dev = dev_instance;
+       struct bnx2x *bp = netdev_priv(dev);
+
+       /* Return here if interrupt is disabled */
+       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+               return IRQ_HANDLED;
+       }
+
+       bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return IRQ_HANDLED;
+#endif
+
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
+#else
+       queue_work(bnx2x_wq, &bp->sp_task);
+#endif
+
+       return IRQ_HANDLED;
+}
+#endif
+
+/* end of slow path */
+
+/* Statistics */
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/* sum[hi:lo] += add[hi:lo] */
+#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
+       do { \
+               s_lo += a_lo; \
+               s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
+       } while (0)
+
+/* difference = minuend - subtrahend */
+#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
+       do { \
+               if (m_lo < s_lo) { \
+                       /* underflow */ \
+                       d_hi = m_hi - s_hi; \
+                       if (d_hi > 0) { \
+                               /* we can 'loan' 1 */ \
+                               d_hi--; \
+                               d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
+                       } else { \
+                               /* m_hi <= s_hi */ \
+                               d_hi = 0; \
+                               d_lo = 0; \
+                       } \
+               } else { \
+                       /* m_lo >= s_lo */ \
+                       if (m_hi < s_hi) { \
+                               d_hi = 0; \
+                               d_lo = 0; \
+                       } else { \
+                               /* m_hi >= s_hi */ \
+                               d_hi = m_hi - s_hi; \
+                               d_lo = m_lo - s_lo; \
+                       } \
+               } \
+       } while (0)
+
+#define UPDATE_STAT64(s, t) \
+       do { \
+               DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
+                       diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
+               pstats->mac_stx[0].t##_hi = new->s##_hi; \
+               pstats->mac_stx[0].t##_lo = new->s##_lo; \
+               ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
+                      pstats->mac_stx[1].t##_lo, diff.lo); \
+       } while (0)
+
+#define UPDATE_STAT64_NIG(s, t) \
+       do { \
+               DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
+                       diff.lo, new->s##_lo, old->s##_lo); \
+               ADD_64(estats->t##_hi, diff.hi, \
+                      estats->t##_lo, diff.lo); \
+       } while (0)
+
+/* sum[hi:lo] += add */
+#define ADD_EXTEND_64(s_hi, s_lo, a) \
+       do { \
+               s_lo += a; \
+               s_hi += (s_lo < a) ? 1 : 0; \
+       } while (0)
+
+#define UPDATE_EXTEND_STAT(s) \
+       do { \
+               ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
+                             pstats->mac_stx[1].s##_lo, \
+                             new->s); \
+       } while (0)
+
+#define UPDATE_EXTEND_TSTAT(s, t) \
+       do { \
+               diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \
+               old_tclient->s = tclient->s; \
+               ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
+       } while (0)
+
+#define UPDATE_EXTEND_USTAT(s, t) \
+       do { \
+               diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
+               old_uclient->s = uclient->s; \
+               ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
+       } while (0)
+
+#define UPDATE_EXTEND_XSTAT(s, t) \
+       do { \
+               diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
+               old_xclient->s = xclient->s; \
+               ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
+       } while (0)
+
+/* minuend -= subtrahend */
+#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
+       do { \
+               DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
+       } while (0)
+
+/* minuend[hi:lo] -= subtrahend */
+#define SUB_EXTEND_64(m_hi, m_lo, s) \
+       do { \
+               SUB_64(m_hi, 0, m_lo, s); \
+       } while (0)
+
+#define SUB_EXTEND_USTAT(s, t) \
+       do { \
+               diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
+               SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
+       } while (0)
+
+/*
+ * General service functions
+ */
+
+static inline long bnx2x_hilo(u32 *hiref)
+{
+       u32 lo = *(hiref + 1);
+#if (BITS_PER_LONG == 64)
+       u32 hi = *hiref;
+
+       return HILO_U64(hi, lo);
+#else
+       return lo;
+#endif
+}
+
+/*
+ * Init service functions
+ */
+
+static void bnx2x_storm_stats_post(struct bnx2x *bp)
+{
+       if (!bp->stats_pending) {
+               struct eth_query_ramrod_data ramrod_data = {0};
+               int i, rc;
+
+               ramrod_data.drv_counter = bp->stats_counter++;
+               ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
+               for_each_queue(bp, i)
+                       ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
+
+               rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
+                                  ((u32 *)&ramrod_data)[1],
+                                  ((u32 *)&ramrod_data)[0], 0);
+               if (rc == 0) {
+                       /* stats ramrod has it's own slot on the spq */
+                       bp->spq_left++;
+                       bp->stats_pending = 1;
+               }
+       }
+}
+
+static void bnx2x_hw_stats_post(struct bnx2x *bp)
+{
+       struct dmae_command *dmae = &bp->stats_dmae;
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       *stats_comp = DMAE_COMP_VAL;
+       if (CHIP_REV_IS_SLOW(bp))
+               return;
+
+       /* loader */
+       if (bp->executer_idx) {
+               int loader_idx = PMF_DMAE_C(bp);
+
+               memset(dmae, 0, sizeof(struct dmae_command));
+
+               dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+                               DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+                               DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                               DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                               DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                               (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
+                                              DMAE_CMD_PORT_0) |
+                               (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+               dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
+               dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
+               dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
+                                    sizeof(struct dmae_command) *
+                                    (loader_idx + 1)) >> 2;
+               dmae->dst_addr_hi = 0;
+               dmae->len = sizeof(struct dmae_command) >> 2;
+               if (CHIP_IS_E1(bp))
+                       dmae->len--;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+
+               *stats_comp = 0;
+               bnx2x_post_dmae(bp, dmae, loader_idx);
+
+       } else if (bp->func_stx) {
+               *stats_comp = 0;
+               bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
+       }
+}
+
+static int bnx2x_stats_comp(struct bnx2x *bp)
+{
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+       int cnt = 10;
+
+       might_sleep();
+       while (*stats_comp != DMAE_COMP_VAL) {
+               if (!cnt) {
+                       BNX2X_ERR("timeout waiting for stats finished\n");
+                       break;
+               }
+               cnt--;
+               msleep(1);
+       }
+       return 1;
+}
+
+/*
+ * Statistics service functions
+ */
+
+static void bnx2x_stats_pmf_update(struct bnx2x *bp)
+{
+       struct dmae_command *dmae;
+       u32 opcode;
+       int loader_idx = PMF_DMAE_C(bp);
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       /* sanity */
+       if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
+               BNX2X_ERR("BUG!\n");
+               return;
+       }
+
+       bp->executer_idx = 0;
+
+       opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+                 DMAE_CMD_C_ENABLE |
+                 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                 DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+
+       dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+       dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
+       dmae->src_addr_lo = bp->port.port_stx >> 2;
+       dmae->src_addr_hi = 0;
+       dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
+       dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
+       dmae->len = DMAE_LEN32_RD_MAX;
+       dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+       dmae->comp_addr_hi = 0;
+       dmae->comp_val = 1;
+
+       dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+       dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
+       dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
+       dmae->src_addr_hi = 0;
+       dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
+                                  DMAE_LEN32_RD_MAX * 4);
+       dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
+                                  DMAE_LEN32_RD_MAX * 4);
+       dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
+       dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_val = DMAE_COMP_VAL;
+
+       *stats_comp = 0;
+       bnx2x_hw_stats_post(bp);
+       bnx2x_stats_comp(bp);
+}
+
+static void bnx2x_port_stats_init(struct bnx2x *bp)
+{
+       struct dmae_command *dmae;
+       int port = BP_PORT(bp);
+       int vn = BP_E1HVN(bp);
+       u32 opcode;
+       int loader_idx = PMF_DMAE_C(bp);
+       u32 mac_addr;
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       /* sanity */
+       if (!bp->link_vars.link_up || !bp->port.pmf) {
+               BNX2X_ERR("BUG!\n");
+               return;
+       }
+
+       bp->executer_idx = 0;
+
+       /* MCP */
+       opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+                 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                 DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                 (vn << DMAE_CMD_E1HVN_SHIFT));
+
+       if (bp->port.port_stx) {
+
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
+               dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
+               dmae->dst_addr_lo = bp->port.port_stx >> 2;
+               dmae->dst_addr_hi = 0;
+               dmae->len = sizeof(struct host_port_stats) >> 2;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+       }
+
+       if (bp->func_stx) {
+
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
+               dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
+               dmae->dst_addr_lo = bp->func_stx >> 2;
+               dmae->dst_addr_hi = 0;
+               dmae->len = sizeof(struct host_func_stats) >> 2;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+       }
+
+       /* MAC */
+       opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+                 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                 DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                 (vn << DMAE_CMD_E1HVN_SHIFT));
+
+       if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
+
+               mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
+                                  NIG_REG_INGRESS_BMAC0_MEM);
+
+               /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
+                  BIGMAC_REGISTER_TX_STAT_GTBYT */
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = (mac_addr +
+                                    BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
+               dmae->src_addr_hi = 0;
+               dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
+               dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
+               dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
+                            BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+
+               /* BIGMAC_REGISTER_RX_STAT_GR64 ..
+                  BIGMAC_REGISTER_RX_STAT_GRIPJ */
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = (mac_addr +
+                                    BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
+               dmae->src_addr_hi = 0;
+               dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
+                               offsetof(struct bmac_stats, rx_stat_gr64_lo));
+               dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
+                               offsetof(struct bmac_stats, rx_stat_gr64_lo));
+               dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
+                            BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+
+       } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
+
+               mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
+
+               /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = (mac_addr +
+                                    EMAC_REG_EMAC_RX_STAT_AC) >> 2;
+               dmae->src_addr_hi = 0;
+               dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
+               dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
+               dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+
+               /* EMAC_REG_EMAC_RX_STAT_AC_28 */
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = (mac_addr +
+                                    EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
+               dmae->src_addr_hi = 0;
+               dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
+                    offsetof(struct emac_stats, rx_stat_falsecarriererrors));
+               dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
+                    offsetof(struct emac_stats, rx_stat_falsecarriererrors));
+               dmae->len = 1;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+
+               /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = opcode;
+               dmae->src_addr_lo = (mac_addr +
+                                    EMAC_REG_EMAC_TX_STAT_AC) >> 2;
+               dmae->src_addr_hi = 0;
+               dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
+                       offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
+               dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
+                       offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
+               dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
+               dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+               dmae->comp_addr_hi = 0;
+               dmae->comp_val = 1;
+       }
+
+       /* NIG */
+       dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+       dmae->opcode = opcode;
+       dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
+                                   NIG_REG_STAT0_BRB_DISCARD) >> 2;
+       dmae->src_addr_hi = 0;
+       dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
+       dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
+       dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
+       dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+       dmae->comp_addr_hi = 0;
+       dmae->comp_val = 1;
+
+       dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+       dmae->opcode = opcode;
+       dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
+                                   NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
+       dmae->src_addr_hi = 0;
+       dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
+                       offsetof(struct nig_stats, egress_mac_pkt0_lo));
+       dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
+                       offsetof(struct nig_stats, egress_mac_pkt0_lo));
+       dmae->len = (2*sizeof(u32)) >> 2;
+       dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+       dmae->comp_addr_hi = 0;
+       dmae->comp_val = 1;
+
+       dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+       dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+                       DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+                       DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                       DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                       DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                       (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                       (vn << DMAE_CMD_E1HVN_SHIFT));
+       dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
+                                   NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
+       dmae->src_addr_hi = 0;
+       dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
+                       offsetof(struct nig_stats, egress_mac_pkt1_lo));
+       dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
+                       offsetof(struct nig_stats, egress_mac_pkt1_lo));
+       dmae->len = (2*sizeof(u32)) >> 2;
+       dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_val = DMAE_COMP_VAL;
+
+       *stats_comp = 0;
+}
+
+static void bnx2x_func_stats_init(struct bnx2x *bp)
+{
+       struct dmae_command *dmae = &bp->stats_dmae;
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       /* sanity */
+       if (!bp->func_stx) {
+               BNX2X_ERR("BUG!\n");
+               return;
+       }
+
+       bp->executer_idx = 0;
+       memset(dmae, 0, sizeof(struct dmae_command));
+
+       dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+                       DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+                       DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                       DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                       DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                       (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                       (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+       dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
+       dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
+       dmae->dst_addr_lo = bp->func_stx >> 2;
+       dmae->dst_addr_hi = 0;
+       dmae->len = sizeof(struct host_func_stats) >> 2;
+       dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_val = DMAE_COMP_VAL;
+
+       *stats_comp = 0;
+}
+
+static void bnx2x_stats_start(struct bnx2x *bp)
+{
+       if (bp->port.pmf)
+               bnx2x_port_stats_init(bp);
+
+       else if (bp->func_stx)
+               bnx2x_func_stats_init(bp);
+
+       bnx2x_hw_stats_post(bp);
+       bnx2x_storm_stats_post(bp);
+}
+
+static void bnx2x_stats_pmf_start(struct bnx2x *bp)
+{
+       bnx2x_stats_comp(bp);
+       bnx2x_stats_pmf_update(bp);
+       bnx2x_stats_start(bp);
+}
+
+static void bnx2x_stats_restart(struct bnx2x *bp)
+{
+       bnx2x_stats_comp(bp);
+       bnx2x_stats_start(bp);
+}
+
+static void bnx2x_bmac_stats_update(struct bnx2x *bp)
+{
+       struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
+       struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
+       struct bnx2x_eth_stats *estats = &bp->eth_stats;
+       struct {
+               u32 lo;
+               u32 hi;
+       } diff;
+
+       UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
+       UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
+       UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
+       UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
+       UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
+       UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
+       UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
+       UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
+       UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
+       UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
+       UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
+       UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
+       UPDATE_STAT64(tx_stat_gt127,
+                               tx_stat_etherstatspkts65octetsto127octets);
+       UPDATE_STAT64(tx_stat_gt255,
+                               tx_stat_etherstatspkts128octetsto255octets);
+       UPDATE_STAT64(tx_stat_gt511,
+                               tx_stat_etherstatspkts256octetsto511octets);
+       UPDATE_STAT64(tx_stat_gt1023,
+                               tx_stat_etherstatspkts512octetsto1023octets);
+       UPDATE_STAT64(tx_stat_gt1518,
+                               tx_stat_etherstatspkts1024octetsto1522octets);
+       UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
+       UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
+       UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
+       UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
+       UPDATE_STAT64(tx_stat_gterr,
+                               tx_stat_dot3statsinternalmactransmiterrors);
+       UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
+
+       estats->pause_frames_received_hi =
+                               pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
+       estats->pause_frames_received_lo =
+                               pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
+
+       estats->pause_frames_sent_hi =
+                               pstats->mac_stx[1].tx_stat_outxoffsent_hi;
+       estats->pause_frames_sent_lo =
+                               pstats->mac_stx[1].tx_stat_outxoffsent_lo;
+}
+
+static void bnx2x_emac_stats_update(struct bnx2x *bp)
+{
+       struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
+       struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
+       struct bnx2x_eth_stats *estats = &bp->eth_stats;
+
+       UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
+       UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
+       UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
+       UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
+       UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
+       UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
+       UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
+       UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
+       UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
+       UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
+       UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
+       UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
+       UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
+       UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
+       UPDATE_EXTEND_STAT(tx_stat_outxonsent);
+       UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
+       UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
+       UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
+       UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
+       UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
+       UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
+       UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
+       UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
+       UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
+
+       estats->pause_frames_received_hi =
+                       pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
+       estats->pause_frames_received_lo =
+                       pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
+       ADD_64(estats->pause_frames_received_hi,
+              pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
+              estats->pause_frames_received_lo,
+              pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
+
+       estats->pause_frames_sent_hi =
+                       pstats->mac_stx[1].tx_stat_outxonsent_hi;
+       estats->pause_frames_sent_lo =
+                       pstats->mac_stx[1].tx_stat_outxonsent_lo;
+       ADD_64(estats->pause_frames_sent_hi,
+              pstats->mac_stx[1].tx_stat_outxoffsent_hi,
+              estats->pause_frames_sent_lo,
+              pstats->mac_stx[1].tx_stat_outxoffsent_lo);
+}
+
+static int bnx2x_hw_stats_update(struct bnx2x *bp)
+{
+       struct nig_stats *new = bnx2x_sp(bp, nig_stats);
+       struct nig_stats *old = &(bp->port.old_nig_stats);
+       struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
+       struct bnx2x_eth_stats *estats = &bp->eth_stats;
+       struct {
+               u32 lo;
+               u32 hi;
+       } diff;
+       u32 nig_timer_max;
+
+       if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
+               bnx2x_bmac_stats_update(bp);
+
+       else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
+               bnx2x_emac_stats_update(bp);
+
+       else { /* unreached */
+               BNX2X_ERR("stats updated by DMAE but no MAC active\n");
+               return -1;
+       }
+
+       ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
+                     new->brb_discard - old->brb_discard);
+       ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
+                     new->brb_truncate - old->brb_truncate);
+
+       UPDATE_STAT64_NIG(egress_mac_pkt0,
+                                       etherstatspkts1024octetsto1522octets);
+       UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
+
+       memcpy(old, new, sizeof(struct nig_stats));
+
+       memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
+              sizeof(struct mac_stx));
+       estats->brb_drop_hi = pstats->brb_drop_hi;
+       estats->brb_drop_lo = pstats->brb_drop_lo;
+
+       pstats->host_port_stats_start = ++pstats->host_port_stats_end;
+
+       nig_timer_max = SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
+       if (nig_timer_max != estats->nig_timer_max) {
+               estats->nig_timer_max = nig_timer_max;
+               BNX2X_ERR("NIG timer max (%u)\n", estats->nig_timer_max);
+       }
+
+       return 0;
+}
+
+static int bnx2x_storm_stats_update(struct bnx2x *bp)
+{
+       struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
+       struct tstorm_per_port_stats *tport =
+                                       &stats->tstorm_common.port_statistics;
+       struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
+       struct bnx2x_eth_stats *estats = &bp->eth_stats;
+       int i;
+
+       memcpy(&(fstats->total_bytes_received_hi),
+              &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
+              sizeof(struct host_func_stats) - 2*sizeof(u32));
+       estats->error_bytes_received_hi = 0;
+       estats->error_bytes_received_lo = 0;
+       estats->etherstatsoverrsizepkts_hi = 0;
+       estats->etherstatsoverrsizepkts_lo = 0;
+       estats->no_buff_discard_hi = 0;
+       estats->no_buff_discard_lo = 0;
+
+       for_each_rx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+               int cl_id = fp->cl_id;
+               struct tstorm_per_client_stats *tclient =
+                               &stats->tstorm_common.client_statistics[cl_id];
+               struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
+               struct ustorm_per_client_stats *uclient =
+                               &stats->ustorm_common.client_statistics[cl_id];
+               struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
+               struct xstorm_per_client_stats *xclient =
+                               &stats->xstorm_common.client_statistics[cl_id];
+               struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
+               struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
+               u32 diff;
+
+               /* are storm stats valid? */
+               if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
+                                                       bp->stats_counter) {
+                       DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
+                          "  xstorm counter (%d) != stats_counter (%d)\n",
+                          i, xclient->stats_counter, bp->stats_counter);
+                       return -1;
+               }
+               if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
+                                                       bp->stats_counter) {
+                       DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
+                          "  tstorm counter (%d) != stats_counter (%d)\n",
+                          i, tclient->stats_counter, bp->stats_counter);
+                       return -2;
+               }
+               if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
+                                                       bp->stats_counter) {
+                       DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
+                          "  ustorm counter (%d) != stats_counter (%d)\n",
+                          i, uclient->stats_counter, bp->stats_counter);
+                       return -4;
+               }
+
+               qstats->total_bytes_received_hi =
+                       le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
+               qstats->total_bytes_received_lo =
+                       le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
+
+               ADD_64(qstats->total_bytes_received_hi,
+                      le32_to_cpu(tclient->rcv_multicast_bytes.hi),
+                      qstats->total_bytes_received_lo,
+                      le32_to_cpu(tclient->rcv_multicast_bytes.lo));
+
+               ADD_64(qstats->total_bytes_received_hi,
+                      le32_to_cpu(tclient->rcv_unicast_bytes.hi),
+                      qstats->total_bytes_received_lo,
+                      le32_to_cpu(tclient->rcv_unicast_bytes.lo));
+
+               qstats->valid_bytes_received_hi =
+                                       qstats->total_bytes_received_hi;
+               qstats->valid_bytes_received_lo =
+                                       qstats->total_bytes_received_lo;
+
+               qstats->error_bytes_received_hi =
+                               le32_to_cpu(tclient->rcv_error_bytes.hi);
+               qstats->error_bytes_received_lo =
+                               le32_to_cpu(tclient->rcv_error_bytes.lo);
+
+               ADD_64(qstats->total_bytes_received_hi,
+                      qstats->error_bytes_received_hi,
+                      qstats->total_bytes_received_lo,
+                      qstats->error_bytes_received_lo);
+
+               UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
+                                       total_unicast_packets_received);
+               UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
+                                       total_multicast_packets_received);
+               UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
+                                       total_broadcast_packets_received);
+               UPDATE_EXTEND_TSTAT(packets_too_big_discard,
+                                       etherstatsoverrsizepkts);
+               UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
+
+               SUB_EXTEND_USTAT(ucast_no_buff_pkts,
+                                       total_unicast_packets_received);
+               SUB_EXTEND_USTAT(mcast_no_buff_pkts,
+                                       total_multicast_packets_received);
+               SUB_EXTEND_USTAT(bcast_no_buff_pkts,
+                                       total_broadcast_packets_received);
+               UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
+               UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
+               UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
+
+               qstats->total_bytes_transmitted_hi =
+                               le32_to_cpu(xclient->unicast_bytes_sent.hi);
+               qstats->total_bytes_transmitted_lo =
+                               le32_to_cpu(xclient->unicast_bytes_sent.lo);
+
+               ADD_64(qstats->total_bytes_transmitted_hi,
+                      le32_to_cpu(xclient->multicast_bytes_sent.hi),
+                      qstats->total_bytes_transmitted_lo,
+                      le32_to_cpu(xclient->multicast_bytes_sent.lo));
+
+               ADD_64(qstats->total_bytes_transmitted_hi,
+                      le32_to_cpu(xclient->broadcast_bytes_sent.hi),
+                      qstats->total_bytes_transmitted_lo,
+                      le32_to_cpu(xclient->broadcast_bytes_sent.lo));
+
+               UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
+                                       total_unicast_packets_transmitted);
+               UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
+                                       total_multicast_packets_transmitted);
+               UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
+                                       total_broadcast_packets_transmitted);
+
+               old_tclient->checksum_discard = tclient->checksum_discard;
+               old_tclient->ttl0_discard = tclient->ttl0_discard;
+
+               ADD_64(fstats->total_bytes_received_hi,
+                      qstats->total_bytes_received_hi,
+                      fstats->total_bytes_received_lo,
+                      qstats->total_bytes_received_lo);
+               ADD_64(fstats->total_bytes_transmitted_hi,
+                      qstats->total_bytes_transmitted_hi,
+                      fstats->total_bytes_transmitted_lo,
+                      qstats->total_bytes_transmitted_lo);
+               ADD_64(fstats->total_unicast_packets_received_hi,
+                      qstats->total_unicast_packets_received_hi,
+                      fstats->total_unicast_packets_received_lo,
+                      qstats->total_unicast_packets_received_lo);
+               ADD_64(fstats->total_multicast_packets_received_hi,
+                      qstats->total_multicast_packets_received_hi,
+                      fstats->total_multicast_packets_received_lo,
+                      qstats->total_multicast_packets_received_lo);
+               ADD_64(fstats->total_broadcast_packets_received_hi,
+                      qstats->total_broadcast_packets_received_hi,
+                      fstats->total_broadcast_packets_received_lo,
+                      qstats->total_broadcast_packets_received_lo);
+               ADD_64(fstats->total_unicast_packets_transmitted_hi,
+                      qstats->total_unicast_packets_transmitted_hi,
+                      fstats->total_unicast_packets_transmitted_lo,
+                      qstats->total_unicast_packets_transmitted_lo);
+               ADD_64(fstats->total_multicast_packets_transmitted_hi,
+                      qstats->total_multicast_packets_transmitted_hi,
+                      fstats->total_multicast_packets_transmitted_lo,
+                      qstats->total_multicast_packets_transmitted_lo);
+               ADD_64(fstats->total_broadcast_packets_transmitted_hi,
+                      qstats->total_broadcast_packets_transmitted_hi,
+                      fstats->total_broadcast_packets_transmitted_lo,
+                      qstats->total_broadcast_packets_transmitted_lo);
+               ADD_64(fstats->valid_bytes_received_hi,
+                      qstats->valid_bytes_received_hi,
+                      fstats->valid_bytes_received_lo,
+                      qstats->valid_bytes_received_lo);
+
+               ADD_64(estats->error_bytes_received_hi,
+                      qstats->error_bytes_received_hi,
+                      estats->error_bytes_received_lo,
+                      qstats->error_bytes_received_lo);
+               ADD_64(estats->etherstatsoverrsizepkts_hi,
+                      qstats->etherstatsoverrsizepkts_hi,
+                      estats->etherstatsoverrsizepkts_lo,
+                      qstats->etherstatsoverrsizepkts_lo);
+               ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
+                      estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
+       }
+
+       ADD_64(fstats->total_bytes_received_hi,
+              estats->rx_stat_ifhcinbadoctets_hi,
+              fstats->total_bytes_received_lo,
+              estats->rx_stat_ifhcinbadoctets_lo);
+
+       memcpy(estats, &(fstats->total_bytes_received_hi),
+              sizeof(struct host_func_stats) - 2*sizeof(u32));
+
+       ADD_64(estats->etherstatsoverrsizepkts_hi,
+              estats->rx_stat_dot3statsframestoolong_hi,
+              estats->etherstatsoverrsizepkts_lo,
+              estats->rx_stat_dot3statsframestoolong_lo);
+       ADD_64(estats->error_bytes_received_hi,
+              estats->rx_stat_ifhcinbadoctets_hi,
+              estats->error_bytes_received_lo,
+              estats->rx_stat_ifhcinbadoctets_lo);
+
+       if (bp->port.pmf) {
+               estats->mac_filter_discard =
+                               le32_to_cpu(tport->mac_filter_discard);
+               estats->xxoverflow_discard =
+                               le32_to_cpu(tport->xxoverflow_discard);
+               estats->brb_truncate_discard =
+                               le32_to_cpu(tport->brb_truncate_discard);
+               estats->mac_discard = le32_to_cpu(tport->mac_discard);
+       }
+
+       fstats->host_func_stats_start = ++fstats->host_func_stats_end;
+
+       bp->stats_pending = 0;
+
+       return 0;
+}
+
+static void bnx2x_net_stats_update(struct bnx2x *bp)
+{
+       struct bnx2x_eth_stats *estats = &bp->eth_stats;
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+       struct net_device_stats *nstats = &bp->dev->stats;
+#else
+       struct net_device_stats *nstats = &bp->net_stats;
+#endif
+       int i;
+
+       nstats->rx_packets =
+               bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
+               bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
+               bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
+
+       nstats->tx_packets =
+               bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
+               bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
+               bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
+
+       nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
+
+       nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
+
+       nstats->rx_dropped = estats->mac_discard;
+       for_each_rx_queue(bp, i)
+               nstats->rx_dropped +=
+                       le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
+
+       nstats->tx_dropped = 0;
+
+       nstats->multicast =
+               bnx2x_hilo(&estats->total_multicast_packets_received_hi);
+
+       nstats->collisions =
+               bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
+
+       nstats->rx_length_errors =
+               bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
+               bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
+       nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
+                                bnx2x_hilo(&estats->brb_truncate_hi);
+       nstats->rx_crc_errors =
+               bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
+       nstats->rx_frame_errors =
+               bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
+       nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
+       nstats->rx_missed_errors = estats->xxoverflow_discard;
+
+       nstats->rx_errors = nstats->rx_length_errors +
+                           nstats->rx_over_errors +
+                           nstats->rx_crc_errors +
+                           nstats->rx_frame_errors +
+                           nstats->rx_fifo_errors +
+                           nstats->rx_missed_errors;
+
+       nstats->tx_aborted_errors =
+               bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
+               bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
+       nstats->tx_carrier_errors =
+               bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
+       nstats->tx_fifo_errors = 0;
+       nstats->tx_heartbeat_errors = 0;
+       nstats->tx_window_errors = 0;
+
+       nstats->tx_errors = nstats->tx_aborted_errors +
+                           nstats->tx_carrier_errors +
+           bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
+}
+
+static void bnx2x_drv_stats_update(struct bnx2x *bp)
+{
+       struct bnx2x_eth_stats *estats = &bp->eth_stats;
+       int i;
+
+       estats->driver_xoff = 0;
+       estats->rx_err_discard_pkt = 0;
+       estats->rx_skb_alloc_failed = 0;
+       estats->hw_csum_err = 0;
+       for_each_rx_queue(bp, i) {
+               struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
+
+               estats->driver_xoff += qstats->driver_xoff;
+               estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
+               estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
+               estats->hw_csum_err += qstats->hw_csum_err;
+       }
+}
+
+static void bnx2x_stats_update(struct bnx2x *bp)
+{
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       if (*stats_comp != DMAE_COMP_VAL)
+               return;
+
+       if (bp->port.pmf)
+               bnx2x_hw_stats_update(bp);
+
+       if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
+               BNX2X_ERR("storm stats were not updated for 3 times\n");
+               bnx2x_panic();
+               return;
+       }
+
+       bnx2x_net_stats_update(bp);
+       bnx2x_drv_stats_update(bp);
+
+       if (bp->msglevel & NETIF_MSG_TIMER) {
+               struct bnx2x_fastpath *fp0_rx = bp->fp;
+               struct bnx2x_fastpath *fp0_tx = &(bp->fp[bp->num_rx_queues]);
+               struct tstorm_per_client_stats *old_tclient =
+                                                       &bp->fp->old_tclient;
+               struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
+               struct bnx2x_eth_stats *estats = &bp->eth_stats;
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+               struct net_device_stats *nstats = &bp->dev->stats;
+#else
+               struct net_device_stats *nstats = &bp->net_stats;
+#endif
+               int i;
+
+               printk(KERN_DEBUG "%s:\n", bp->dev->name);
+               printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
+                                 "  tx pkt (%lx)\n",
+                      bnx2x_tx_avail(fp0_tx),
+                      le16_to_cpu(*fp0_tx->tx_cons_sb), nstats->tx_packets);
+               printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
+                                 "  rx pkt (%lx)\n",
+                      (u16)(le16_to_cpu(*fp0_rx->rx_cons_sb) -
+                            fp0_rx->rx_comp_cons),
+                      le16_to_cpu(*fp0_rx->rx_cons_sb), nstats->rx_packets);
+               printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u  "
+                                 "brb truncate %u\n",
+                      (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
+                      qstats->driver_xoff,
+                      estats->brb_drop_lo, estats->brb_truncate_lo);
+               printk(KERN_DEBUG "tstats: checksum_discard %u  "
+                       "packets_too_big_discard %lu  no_buff_discard %lu  "
+                       "mac_discard %u  mac_filter_discard %u  "
+                       "xxovrflow_discard %u  brb_truncate_discard %u  "
+                       "ttl0_discard %u\n",
+                      le32_to_cpu(old_tclient->checksum_discard),
+                      bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi),
+                      bnx2x_hilo(&qstats->no_buff_discard_hi),
+                      estats->mac_discard, estats->mac_filter_discard,
+                      estats->xxoverflow_discard, estats->brb_truncate_discard,
+                      le32_to_cpu(old_tclient->ttl0_discard));
+
+               for_each_queue(bp, i) {
+                       printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
+                              bnx2x_fp(bp, i, tx_pkt),
+                              bnx2x_fp(bp, i, rx_pkt),
+                              bnx2x_fp(bp, i, rx_calls));
+               }
+       }
+
+       bnx2x_hw_stats_post(bp);
+       bnx2x_storm_stats_post(bp);
+}
+
+static void bnx2x_port_stats_stop(struct bnx2x *bp)
+{
+       struct dmae_command *dmae;
+       u32 opcode;
+       int loader_idx = PMF_DMAE_C(bp);
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       bp->executer_idx = 0;
+
+       opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+                 DMAE_CMD_C_ENABLE |
+                 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                 DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+
+       if (bp->port.port_stx) {
+
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               if (bp->func_stx)
+                       dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
+               else
+                       dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
+               dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
+               dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
+               dmae->dst_addr_lo = bp->port.port_stx >> 2;
+               dmae->dst_addr_hi = 0;
+               dmae->len = sizeof(struct host_port_stats) >> 2;
+               if (bp->func_stx) {
+                       dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+                       dmae->comp_addr_hi = 0;
+                       dmae->comp_val = 1;
+               } else {
+                       dmae->comp_addr_lo =
+                               U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+                       dmae->comp_addr_hi =
+                               U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+                       dmae->comp_val = DMAE_COMP_VAL;
+
+                       *stats_comp = 0;
+               }
+       }
+
+       if (bp->func_stx) {
+
+               dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+               dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
+               dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
+               dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
+               dmae->dst_addr_lo = bp->func_stx >> 2;
+               dmae->dst_addr_hi = 0;
+               dmae->len = sizeof(struct host_func_stats) >> 2;
+               dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+               dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+               dmae->comp_val = DMAE_COMP_VAL;
+
+               *stats_comp = 0;
+       }
+}
+
+static void bnx2x_stats_stop(struct bnx2x *bp)
+{
+       int update = 0;
+
+       bnx2x_stats_comp(bp);
+
+       if (bp->port.pmf)
+               update = (bnx2x_hw_stats_update(bp) == 0);
+
+       update |= (bnx2x_storm_stats_update(bp) == 0);
+
+       if (update) {
+               bnx2x_net_stats_update(bp);
+
+               if (bp->port.pmf)
+                       bnx2x_port_stats_stop(bp);
+
+               bnx2x_hw_stats_post(bp);
+               bnx2x_stats_comp(bp);
+       }
+}
+
+static void bnx2x_stats_do_nothing(struct bnx2x *bp)
+{
+}
+
+static const struct {
+       void (*action)(struct bnx2x *bp);
+       enum bnx2x_stats_state next_state;
+} bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
+/* state       event   */
+{
+/* DISABLED    PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
+/*             LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
+/*             UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
+/*             STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
+},
+{
+/* ENABLED     PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
+/*             LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
+/*             UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
+/*             STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
+}
+};
+
+static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
+{
+       enum bnx2x_stats_state state = bp->stats_state;
+
+       bnx2x_stats_stm[state][event].action(bp);
+       bp->stats_state = bnx2x_stats_stm[state][event].next_state;
+
+       if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
+               DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
+                  state, event, bp->stats_state);
+}
+
+static void bnx2x_port_stats_base_init(struct bnx2x *bp)
+{
+       struct dmae_command *dmae;
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       /* sanity */
+       if (!bp->port.pmf || !bp->port.port_stx) {
+               BNX2X_ERR("BUG!\n");
+               return;
+       }
+
+       bp->executer_idx = 0;
+
+       dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
+       dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+                       DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+                       DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                       DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                       DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                       (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                       (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+       dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
+       dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
+       dmae->dst_addr_lo = bp->port.port_stx >> 2;
+       dmae->dst_addr_hi = 0;
+       dmae->len = sizeof(struct host_port_stats) >> 2;
+       dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_val = DMAE_COMP_VAL;
+
+       *stats_comp = 0;
+       bnx2x_hw_stats_post(bp);
+       bnx2x_stats_comp(bp);
+}
+
+static void bnx2x_func_stats_base_init(struct bnx2x *bp)
+{
+       int vn, vn_max = IS_E1HMF(bp) ? E1HVN_MAX : E1VN_MAX;
+       int port = BP_PORT(bp);
+       int func;
+       u32 func_stx;
+
+       /* sanity */
+       if (!bp->port.pmf || !bp->func_stx) {
+               BNX2X_ERR("BUG!\n");
+               return;
+       }
+
+       /* save our func_stx */
+       func_stx = bp->func_stx;
+
+       for (vn = VN_0; vn < vn_max; vn++) {
+               func = 2*vn + port;
+
+               bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
+               bnx2x_func_stats_init(bp);
+               bnx2x_hw_stats_post(bp);
+               bnx2x_stats_comp(bp);
+       }
+
+       /* restore our func_stx */
+       bp->func_stx = func_stx;
+}
+
+static void bnx2x_func_stats_base_update(struct bnx2x *bp)
+{
+       struct dmae_command *dmae = &bp->stats_dmae;
+       u32 *stats_comp = bnx2x_sp(bp, stats_comp);
+
+       /* sanity */
+       if (!bp->func_stx) {
+               BNX2X_ERR("BUG!\n");
+               return;
+       }
+
+       bp->executer_idx = 0;
+       memset(dmae, 0, sizeof(struct dmae_command));
+
+       dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+                       DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+                       DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+                       DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+                       DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+                       (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+                       (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+       dmae->src_addr_lo = bp->func_stx >> 2;
+       dmae->src_addr_hi = 0;
+       dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
+       dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
+       dmae->len = sizeof(struct host_func_stats) >> 2;
+       dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
+       dmae->comp_val = DMAE_COMP_VAL;
+
+       *stats_comp = 0;
+       bnx2x_hw_stats_post(bp);
+       bnx2x_stats_comp(bp);
+}
+
+static void bnx2x_stats_init(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int func = BP_FUNC(bp);
+       int i;
+
+       bp->stats_pending = 0;
+       bp->executer_idx = 0;
+       bp->stats_counter = 0;
+
+       /* port and func stats for management */
+       if (!BP_NOMCP(bp)) {
+               bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
+               bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
+
+       } else {
+               bp->port.port_stx = 0;
+               bp->func_stx = 0;
+       }
+       DP(BNX2X_MSG_STATS, "port_stx 0x%x  func_stx 0x%x\n",
+          bp->port.port_stx, bp->func_stx);
+
+       /* port stats */
+       memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
+       bp->port.old_nig_stats.brb_discard =
+                       REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
+       bp->port.old_nig_stats.brb_truncate =
+                       REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
+       REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
+                   &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
+       REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
+                   &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
+
+       /* function stats */
+       for_each_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               memset(&fp->old_tclient, 0,
+                      sizeof(struct tstorm_per_client_stats));
+               memset(&fp->old_uclient, 0,
+                      sizeof(struct ustorm_per_client_stats));
+               memset(&fp->old_xclient, 0,
+                      sizeof(struct xstorm_per_client_stats));
+               memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
+       }
+
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+       memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
+#else
+       memset(&bp->net_stats, 0, sizeof(struct net_device_stats));
+#endif
+       memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
+
+       bp->stats_state = STATS_STATE_DISABLED;
+
+       if (bp->port.pmf) {
+               if (bp->port.port_stx)
+                       bnx2x_port_stats_base_init(bp);
+
+               if (bp->func_stx)
+                       bnx2x_func_stats_base_init(bp);
+
+       } else if (bp->func_stx)
+               bnx2x_func_stats_base_update(bp);
+}
+
+static void bnx2x_timer(unsigned long data)
+{
+       struct bnx2x *bp = (struct bnx2x *) data;
+
+       if (!netif_running(bp->dev))
+               return;
+
+       if (atomic_read(&bp->intr_sem) != 0)
+               goto timer_restart;
+
+       if (poll) {
+               struct bnx2x_fastpath *fp = &bp->fp[0];
+               int rc;
+
+               bnx2x_tx_int(fp);
+               rc = bnx2x_rx_int(fp, 1000);
+       }
+
+       if (!BP_NOMCP(bp)) {
+               int func = BP_FUNC(bp);
+               u32 drv_pulse;
+               u32 mcp_pulse;
+
+               ++bp->fw_drv_pulse_wr_seq;
+               bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
+               /* TBD - add SYSTEM_TIME */
+               drv_pulse = bp->fw_drv_pulse_wr_seq;
+               SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
+
+               mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
+                            MCP_PULSE_SEQ_MASK);
+               /* The delta between driver pulse and mcp response
+                * should be 1 (before mcp response) or 0 (after mcp response)
+                */
+               if ((drv_pulse != mcp_pulse) &&
+                   (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
+                       /* someone lost a heartbeat... */
+                       BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
+                                 drv_pulse, mcp_pulse);
+               }
+       }
+
+       if ((bp->state == BNX2X_STATE_OPEN) ||
+           (bp->state == BNX2X_STATE_DISABLED))
+               bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
+
+timer_restart:
+       mod_timer(&bp->timer, jiffies + bp->current_interval);
+}
+
+/* end of Statistics */
+
+/* nic init */
+
+/*
+ * nic init service functions
+ */
+
+static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
+{
+       int port = BP_PORT(bp);
+
+       /* "CSTORM" */
+       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+                       CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
+                       CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
+       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+                       CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
+                       CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
+}
+
+static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
+                         dma_addr_t mapping, int sb_id)
+{
+       int port = BP_PORT(bp);
+       int func = BP_FUNC(bp);
+       int index;
+       u64 section;
+
+       /* USTORM */
+       section = ((u64)mapping) + offsetof(struct host_status_block,
+                                           u_status_block);
+       sb->u_status_block.status_block_id = sb_id;
+
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
+              U64_HI(section));
+       REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF +
+               CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
+
+       for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
+               REG_WR16(bp, BAR_CSTRORM_INTMEM +
+                        CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1);
+
+       /* CSTORM */
+       section = ((u64)mapping) + offsetof(struct host_status_block,
+                                           c_status_block);
+       sb->c_status_block.status_block_id = sb_id;
+
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
+              U64_HI(section));
+       REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
+               CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
+
+       for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
+               REG_WR16(bp, BAR_CSTRORM_INTMEM +
+                        CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1);
+
+       bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+}
+
+static void bnx2x_zero_def_sb(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+
+       bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY +
+                       TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+                       sizeof(struct tstorm_def_status_block)/4);
+       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+                       CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
+                       sizeof(struct cstorm_def_status_block_u)/4);
+       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
+                       CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
+                       sizeof(struct cstorm_def_status_block_c)/4);
+       bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY +
+                       XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+                       sizeof(struct xstorm_def_status_block)/4);
+}
+
+static void bnx2x_init_def_sb(struct bnx2x *bp,
+                             struct host_def_status_block *def_sb,
+                             dma_addr_t mapping, int sb_id)
+{
+       int port = BP_PORT(bp);
+       int func = BP_FUNC(bp);
+       int index, val, reg_offset;
+       u64 section;
+
+       /* ATTN */
+       section = ((u64)mapping) + offsetof(struct host_def_status_block,
+                                           atten_status_block);
+       def_sb->atten_status_block.status_block_id = sb_id;
+
+       bp->attn_state = 0;
+
+       reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+                            MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
+
+       for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+               bp->attn_group[index].sig[0] = REG_RD(bp,
+                                                    reg_offset + 0x10*index);
+               bp->attn_group[index].sig[1] = REG_RD(bp,
+                                              reg_offset + 0x4 + 0x10*index);
+               bp->attn_group[index].sig[2] = REG_RD(bp,
+                                              reg_offset + 0x8 + 0x10*index);
+               bp->attn_group[index].sig[3] = REG_RD(bp,
+                                              reg_offset + 0xc + 0x10*index);
+       }
+
+       reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
+                            HC_REG_ATTN_MSG0_ADDR_L);
+
+       REG_WR(bp, reg_offset, U64_LO(section));
+       REG_WR(bp, reg_offset + 4, U64_HI(section));
+
+       reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
+
+       val = REG_RD(bp, reg_offset);
+       val |= sb_id;
+       REG_WR(bp, reg_offset, val);
+
+       /* USTORM */
+       section = ((u64)mapping) + offsetof(struct host_def_status_block,
+                                           u_def_status_block);
+       def_sb->u_def_status_block.status_block_id = sb_id;
+
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4),
+              U64_HI(section));
+       REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF +
+               CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
+
+       for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
+               REG_WR16(bp, BAR_CSTRORM_INTMEM +
+                        CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
+
+       /* CSTORM */
+       section = ((u64)mapping) + offsetof(struct host_def_status_block,
+                                           c_def_status_block);
+       def_sb->c_def_status_block.status_block_id = sb_id;
+
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
+       REG_WR(bp, BAR_CSTRORM_INTMEM +
+              ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4),
+              U64_HI(section));
+       REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
+               CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
+
+       for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
+               REG_WR16(bp, BAR_CSTRORM_INTMEM +
+                        CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
+
+       /* TSTORM */
+       section = ((u64)mapping) + offsetof(struct host_def_status_block,
+                                           t_def_status_block);
+       def_sb->t_def_status_block.status_block_id = sb_id;
+
+       REG_WR(bp, BAR_TSTRORM_INTMEM +
+              TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
+       REG_WR(bp, BAR_TSTRORM_INTMEM +
+              ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
+              U64_HI(section));
+       REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
+               TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+
+       for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
+               REG_WR16(bp, BAR_TSTRORM_INTMEM +
+                        TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+
+       /* XSTORM */
+       section = ((u64)mapping) + offsetof(struct host_def_status_block,
+                                           x_def_status_block);
+       def_sb->x_def_status_block.status_block_id = sb_id;
+
+       REG_WR(bp, BAR_XSTRORM_INTMEM +
+              XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
+       REG_WR(bp, BAR_XSTRORM_INTMEM +
+              ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
+              U64_HI(section));
+       REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
+               XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+
+       for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
+               REG_WR16(bp, BAR_XSTRORM_INTMEM +
+                        XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+
+       bp->stats_pending = 0;
+       bp->set_mac_pending = 0;
+
+       bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+}
+
+static void bnx2x_update_coalesce(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int i;
+
+       for_each_queue(bp, i) {
+               int sb_id = bp->fp[i].sb_id;
+
+               /* HC_INDEX_U_ETH_RX_CQ_CONS */
+               REG_WR8(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
+                                                     U_SB_ETH_RX_CQ_INDEX),
+                       bp->rx_ticks/12);
+               REG_WR16(bp, BAR_CSTRORM_INTMEM +
+                        CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
+                                                      U_SB_ETH_RX_CQ_INDEX),
+                        (bp->rx_ticks/12) ? 0 : 1);
+
+               /* HC_INDEX_C_ETH_TX_CQ_CONS */
+               REG_WR8(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
+                                                     C_SB_ETH_TX_CQ_INDEX),
+                       bp->tx_ticks/12);
+               REG_WR16(bp, BAR_CSTRORM_INTMEM +
+                        CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
+                                                      C_SB_ETH_TX_CQ_INDEX),
+                        (bp->tx_ticks/12) ? 0 : 1);
+       }
+}
+
+static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
+                                      struct bnx2x_fastpath *fp, int last)
+{
+       int i;
+
+       for (i = 0; i < last; i++) {
+               struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
+               struct sk_buff *skb = rx_buf->skb;
+
+               if (skb == NULL) {
+                       DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
+                       continue;
+               }
+
+               if (fp->tpa_state[i] == BNX2X_TPA_START)
+                       pci_unmap_single(bp->pdev,
+                                        pci_unmap_addr(rx_buf, mapping),
+                                        bp->rx_buf_size, PCI_DMA_FROMDEVICE);
+
+               dev_kfree_skb(skb);
+               rx_buf->skb = NULL;
+       }
+}
+
+static void bnx2x_init_rx_rings(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+       int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
+                                             ETH_MAX_AGGREGATION_QUEUES_E1H;
+       u16 ring_prod, cqe_ring_prod;
+       int i, j;
+
+       bp->rx_buf_size = bp->dev->mtu + ETH_OVREHEAD + BNX2X_RX_ALIGN;
+       DP(NETIF_MSG_IFUP,
+          "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
+
+       if (bp->flags & TPA_ENABLE_FLAG) {
+
+               for_each_rx_queue(bp, j) {
+                       struct bnx2x_fastpath *fp = &bp->fp[j];
+
+                       for (i = 0; i < max_agg_queues; i++) {
+                               fp->tpa_pool[i].skb =
+                                  netdev_alloc_skb(bp->dev, bp->rx_buf_size);
+                               if (!fp->tpa_pool[i].skb) {
+                                       BNX2X_ERR("Failed to allocate TPA "
+                                                 "skb pool for queue[%d] - "
+                                                 "disabling TPA on this "
+                                                 "queue!\n", j);
+                                       bnx2x_free_tpa_pool(bp, fp, i);
+                                       fp->disable_tpa = 1;
+                                       break;
+                               }
+                               pci_unmap_addr_set((struct sw_rx_bd *)
+                                                       &bp->fp->tpa_pool[i],
+                                                  mapping, 0);
+                               fp->tpa_state[i] = BNX2X_TPA_STOP;
+                       }
+               }
+       }
+
+       for_each_rx_queue(bp, j) {
+               struct bnx2x_fastpath *fp = &bp->fp[j];
+
+               fp->rx_bd_cons = 0;
+               fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
+               fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
+
+               /* Mark queue as Rx */
+               fp->is_rx_queue = 1;
+
+#if defined(__NO_TPA__)
+               fp->disable_tpa = 1;
+#else /* BNX2X_UPSTREAM */
+               /* "next page" elements initialization */
+               /* SGE ring */
+               for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
+                       struct eth_rx_sge *sge;
+
+                       sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
+                       sge->addr_hi =
+                               cpu_to_le32(U64_HI(fp->rx_sge_mapping +
+                                       BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
+                       sge->addr_lo =
+                               cpu_to_le32(U64_LO(fp->rx_sge_mapping +
+                                       BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
+               }
+
+               bnx2x_init_sge_ring_bit_mask(fp);
+#endif
+
+               /* RX BD ring */
+               for (i = 1; i <= NUM_RX_RINGS; i++) {
+                       struct eth_rx_bd *rx_bd;
+
+                       rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
+                       rx_bd->addr_hi =
+                               cpu_to_le32(U64_HI(fp->rx_desc_mapping +
+                                           BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
+                       rx_bd->addr_lo =
+                               cpu_to_le32(U64_LO(fp->rx_desc_mapping +
+                                           BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
+               }
+
+               /* CQ ring */
+               for (i = 1; i <= NUM_RCQ_RINGS; i++) {
+                       struct eth_rx_cqe_next_page *nextpg;
+
+                       nextpg = (struct eth_rx_cqe_next_page *)
+                               &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
+                       nextpg->addr_hi =
+                               cpu_to_le32(U64_HI(fp->rx_comp_mapping +
+                                          BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
+                       nextpg->addr_lo =
+                               cpu_to_le32(U64_LO(fp->rx_comp_mapping +
+                                          BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
+               }
+
+#if !defined(__NO_TPA__) /* BNX2X_UPSTREAM */
+               /* Allocate SGEs and initialize the ring elements */
+               for (i = 0, ring_prod = 0;
+                    i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
+
+                       if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
+                               BNX2X_ERR("was only able to allocate "
+                                         "%d rx sges\n", i);
+                               BNX2X_ERR("disabling TPA for queue[%d]\n", j);
+                               /* Cleanup already allocated elements */
+                               bnx2x_free_rx_sge_range(bp, fp, ring_prod);
+                               bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
+                               fp->disable_tpa = 1;
+                               ring_prod = 0;
+                               break;
+                       }
+                       ring_prod = NEXT_SGE_IDX(ring_prod);
+               }
+               fp->rx_sge_prod = ring_prod;
+#endif
+
+               /* Allocate BDs and initialize BD ring */
+               fp->rx_comp_cons = 0;
+               cqe_ring_prod = ring_prod = 0;
+               for (i = 0; i < bp->rx_ring_size; i++) {
+                       if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
+                               BNX2X_ERR("was only able to allocate "
+                                         "%d rx skbs on queue[%d]\n", i, j);
+                               fp->eth_q_stats.rx_skb_alloc_failed++;
+                               break;
+                       }
+                       ring_prod = NEXT_RX_IDX(ring_prod);
+                       cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
+                       WARN_ON(ring_prod <= i);
+               }
+
+               fp->rx_bd_prod = ring_prod;
+               /* must not have more available CQEs than BDs */
+               fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
+                                      cqe_ring_prod);
+               fp->rx_pkt = fp->rx_calls = 0;
+
+               /* Warning!
+                * this will generate an interrupt (to the TSTORM)
+                * must only be done after chip is initialized
+                */
+               bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
+                                    fp->rx_sge_prod);
+               if (j != 0)
+                       continue;
+
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
+                      U64_LO(fp->rx_comp_mapping));
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
+                      U64_HI(fp->rx_comp_mapping));
+       }
+}
+
+static void bnx2x_init_tx_ring(struct bnx2x *bp)
+{
+       int i, j;
+
+       for_each_tx_queue(bp, j) {
+               struct bnx2x_fastpath *fp = &bp->fp[j];
+
+               for (i = 1; i <= NUM_TX_RINGS; i++) {
+                       struct eth_tx_next_bd *tx_next_bd =
+                               &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
+
+                       tx_next_bd->addr_hi =
+                               cpu_to_le32(U64_HI(fp->tx_desc_mapping +
+                                           BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
+                       tx_next_bd->addr_lo =
+                               cpu_to_le32(U64_LO(fp->tx_desc_mapping +
+                                           BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
+               }
+
+               fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
+               fp->tx_db.data.zero_fill1 = 0;
+               fp->tx_db.data.prod = 0;
+
+               fp->tx_pkt_prod = 0;
+               fp->tx_pkt_cons = 0;
+               fp->tx_bd_prod = 0;
+               fp->tx_bd_cons = 0;
+               fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
+               fp->tx_pkt = 0;
+       }
+
+       /* clean tx statistics */
+       for_each_rx_queue(bp, i)
+               bnx2x_fp(bp, i, tx_pkt) = 0;
+}
+
+static void bnx2x_init_sp_ring(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+
+       spin_lock_init(&bp->spq_lock);
+
+       bp->spq_left = MAX_SPQ_PENDING;
+       bp->spq_prod_idx = 0;
+       bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
+       bp->spq_prod_bd = bp->spq;
+       bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
+
+       REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
+              U64_LO(bp->spq_mapping));
+       REG_WR(bp,
+              XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
+              U64_HI(bp->spq_mapping));
+
+       REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
+              bp->spq_prod_idx);
+}
+
+static void bnx2x_init_context(struct bnx2x *bp)
+{
+       int i;
+
+       for_each_rx_queue(bp, i) {
+               struct eth_context *context = bnx2x_sp(bp, context[i].eth);
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+               u8 cl_id = fp->cl_id;
+
+               context->ustorm_st_context.common.sb_index_numbers =
+                                               BNX2X_RX_SB_INDEX_NUM;
+               context->ustorm_st_context.common.clientId = cl_id;
+               context->ustorm_st_context.common.status_block_id = fp->sb_id;
+               context->ustorm_st_context.common.flags =
+                       (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
+                        USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
+               context->ustorm_st_context.common.statistics_counter_id =
+                                               cl_id;
+               context->ustorm_st_context.common.mc_alignment_log_size =
+                                               BNX2X_RX_ALIGN_SHIFT;
+               context->ustorm_st_context.common.bd_buff_size =
+                                               bp->rx_buf_size;
+               context->ustorm_st_context.common.bd_page_base_hi =
+                                               U64_HI(fp->rx_desc_mapping);
+               context->ustorm_st_context.common.bd_page_base_lo =
+                                               U64_LO(fp->rx_desc_mapping);
+               if (!fp->disable_tpa) {
+                       context->ustorm_st_context.common.flags |=
+                               USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
+                       context->ustorm_st_context.common.sge_buff_size =
+                               (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
+                                        (u32)0xffff);
+                       context->ustorm_st_context.common.sge_page_base_hi =
+                                               U64_HI(fp->rx_sge_mapping);
+                       context->ustorm_st_context.common.sge_page_base_lo =
+                                               U64_LO(fp->rx_sge_mapping);
+
+                       context->ustorm_st_context.common.max_sges_for_packet =
+                               SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
+                       context->ustorm_st_context.common.max_sges_for_packet =
+                               ((context->ustorm_st_context.common.
+                                 max_sges_for_packet + PAGES_PER_SGE - 1) &
+                                (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
+               }
+
+               context->ustorm_ag_context.cdu_usage =
+                       CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
+                                              CDU_REGION_NUMBER_UCM_AG,
+                                              ETH_CONNECTION_TYPE);
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+               switch (bp->multi_mode) {
+               case ETH_RSS_MODE_DISABLED:
+               case ETH_RSS_MODE_REGULAR:
+                       break;
+
+               case ETH_RSS_MODE_VLAN_PRI:
+               case ETH_RSS_MODE_E1HOV_PRI:
+               case ETH_RSS_MODE_IP_DSCP:
+                       context->xstorm_st_context.safc_group_en = 1;
+                       context->xstorm_st_context.safc_group_num = fp->cos;
+                       break;
+
+               default:
+                       break;
+               }
+#endif
+               context->xstorm_ag_context.cdu_reserved =
+                       CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
+                                              CDU_REGION_NUMBER_XCM_AG,
+                                              ETH_CONNECTION_TYPE);
+       }
+
+       for_each_tx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+               struct eth_context *context =
+                       bnx2x_sp(bp, context[i - bp->num_rx_queues].eth);
+
+               context->cstorm_st_context.sb_index_number =
+                                               C_SB_ETH_TX_CQ_INDEX;
+               context->cstorm_st_context.status_block_id = fp->sb_id;
+
+               context->xstorm_st_context.tx_bd_page_base_hi =
+                                               U64_HI(fp->tx_desc_mapping);
+               context->xstorm_st_context.tx_bd_page_base_lo =
+                                               U64_LO(fp->tx_desc_mapping);
+               context->xstorm_st_context.statistics_data = (fp->cl_id |
+                               XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
+       }
+}
+
+static void bnx2x_init_ind_table(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+#ifdef BNX2X_SAFC
+       int i, cos;
+       u8 val;
+#else /* BNX2X_UPSTREAM */
+       int i;
+#endif
+
+       if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
+               return;
+
+       DP(NETIF_MSG_IFUP,
+          "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
+#ifdef BNX2X_SAFC
+       for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++) {
+               cos = bp->pri_map[i / BNX2X_MAX_ENTRIES_PER_PRI];
+               val = bp->fp->cl_id + bp->cos_map[cos] +
+                     (i % bp->qs_per_cos[cos]);
+               REG_WR8(bp, BAR_TSTRORM_INTMEM +
+                       TSTORM_INDIRECTION_TABLE_OFFSET(func) + i, val);
+       }
+#else /* BNX2X_UPSTREAM */
+       for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
+               REG_WR8(bp, BAR_TSTRORM_INTMEM +
+                       TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
+                       bp->fp->cl_id + (i % bp->num_rx_queues));
+#endif
+}
+
+static void bnx2x_set_client_config(struct bnx2x *bp)
+{
+       struct tstorm_eth_client_config tstorm_client = {0};
+       int port = BP_PORT(bp);
+       int i;
+
+       tstorm_client.mtu = bp->dev->mtu;
+       tstorm_client.config_flags =
+                               (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
+                                TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
+#ifdef BCM_VLAN
+       if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
+               tstorm_client.config_flags |=
+                               TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
+               DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
+       }
+#endif
+
+       for_each_queue(bp, i) {
+               tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
+
+               REG_WR(bp, BAR_TSTRORM_INTMEM +
+                      TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
+                      ((u32 *)&tstorm_client)[0]);
+               REG_WR(bp, BAR_TSTRORM_INTMEM +
+                      TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
+                      ((u32 *)&tstorm_client)[1]);
+       }
+
+       DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
+          ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
+}
+
+static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
+{
+       struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
+       int mode = bp->rx_mode;
+       int mask = (1 << BP_L_ID(bp));
+       int func = BP_FUNC(bp);
+       int i;
+
+       DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
+
+       switch (mode) {
+       case BNX2X_RX_MODE_NONE: /* no Rx */
+               tstorm_mac_filter.ucast_drop_all = mask;
+               tstorm_mac_filter.mcast_drop_all = mask;
+               tstorm_mac_filter.bcast_drop_all = mask;
+               break;
+
+       case BNX2X_RX_MODE_NORMAL:
+               tstorm_mac_filter.bcast_accept_all = mask;
+               break;
+
+       case BNX2X_RX_MODE_ALLMULTI:
+               tstorm_mac_filter.mcast_accept_all = mask;
+               tstorm_mac_filter.bcast_accept_all = mask;
+               break;
+
+       case BNX2X_RX_MODE_PROMISC:
+               tstorm_mac_filter.ucast_accept_all = mask;
+               tstorm_mac_filter.mcast_accept_all = mask;
+               tstorm_mac_filter.bcast_accept_all = mask;
+               break;
+
+       default:
+               BNX2X_ERR("BAD rx mode (%d)\n", mode);
+               break;
+       }
+
+       for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
+               REG_WR(bp, BAR_TSTRORM_INTMEM +
+                      TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
+                      ((u32 *)&tstorm_mac_filter)[i]);
+
+/*             DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
+                  ((u32 *)&tstorm_mac_filter)[i]); */
+       }
+
+       if (mode != BNX2X_RX_MODE_NONE)
+               bnx2x_set_client_config(bp);
+}
+
+static void bnx2x_init_internal_common(struct bnx2x *bp)
+{
+       int i;
+
+       /* Zero this manually as its initialization is
+          currently missing in the initTool */
+       for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_AGG_DATA_OFFSET + i * 4, 0);
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       if (bp->flags & SAFC_TX_FLAG) {
+               REG_WR(bp, BAR_TSTRORM_INTMEM +
+                      TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET, 1);
+               REG_WR(bp, BAR_TSTRORM_INTMEM +
+                      TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET, 10);
+               REG_WR(bp, MISC_REG_SW_TIMER_VAL + 0xc, 10);
+               REG_WR(bp, MISC_REG_SW_TIMER_RELOAD_VAL_4, 10);
+       }
+#endif
+}
+
+static void bnx2x_init_internal_port(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+
+       REG_WR(bp,
+              BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR);
+       REG_WR(bp,
+              BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR);
+       REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+}
+
+static void bnx2x_init_internal_func(struct bnx2x *bp)
+{
+       struct tstorm_eth_function_common_config tstorm_config = {0};
+       struct stats_indication_flags stats_flags = {0};
+       int port = BP_PORT(bp);
+       int func = BP_FUNC(bp);
+       int i, j;
+       u32 offset;
+       u16 max_agg_size;
+
+       if (is_multi(bp)) {
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__)
+               /* enable queue 0 as the default queue */
+               tstorm_config.config_flags =
+                       TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE;
+#else /* BNX2X_UPSTREAM */
+               tstorm_config.config_flags = MULTI_FLAGS(bp);
+               tstorm_config.rss_result_mask = MULTI_MASK;
+#endif
+       }
+
+       /* Enable TPA if needed */
+       if (bp->flags & TPA_ENABLE_FLAG)
+               tstorm_config.config_flags |=
+                       TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
+
+       if (IS_E1HMF(bp))
+               tstorm_config.config_flags |=
+                               TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
+
+       tstorm_config.leading_client_id = BP_L_ID(bp);
+
+       REG_WR(bp, BAR_TSTRORM_INTMEM +
+              TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
+              (*(u32 *)&tstorm_config));
+
+       bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
+       bnx2x_set_storm_rx_mode(bp);
+
+       for_each_queue(bp, i) {
+               u8 cl_id = bp->fp[i].cl_id;
+
+               /* reset xstorm per client statistics */
+               offset = BAR_XSTRORM_INTMEM +
+                        XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
+               for (j = 0;
+                    j < sizeof(struct xstorm_per_client_stats) / 4; j++)
+                       REG_WR(bp, offset + j*4, 0);
+
+               /* reset tstorm per client statistics */
+               offset = BAR_TSTRORM_INTMEM +
+                        TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
+               for (j = 0;
+                    j < sizeof(struct tstorm_per_client_stats) / 4; j++)
+                       REG_WR(bp, offset + j*4, 0);
+
+               /* reset ustorm per client statistics */
+               offset = BAR_USTRORM_INTMEM +
+                        USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
+               for (j = 0;
+                    j < sizeof(struct ustorm_per_client_stats) / 4; j++)
+                       REG_WR(bp, offset + j*4, 0);
+       }
+
+       /* Init statistics related context */
+       stats_flags.collect_eth = 1;
+
+       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
+              ((u32 *)&stats_flags)[0]);
+       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
+              ((u32 *)&stats_flags)[1]);
+
+       REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
+              ((u32 *)&stats_flags)[0]);
+       REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
+              ((u32 *)&stats_flags)[1]);
+
+       REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
+              ((u32 *)&stats_flags)[0]);
+       REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
+              ((u32 *)&stats_flags)[1]);
+
+       REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
+              ((u32 *)&stats_flags)[0]);
+       REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
+              ((u32 *)&stats_flags)[1]);
+
+       REG_WR(bp, BAR_XSTRORM_INTMEM +
+              XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
+              U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
+       REG_WR(bp, BAR_XSTRORM_INTMEM +
+              XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
+              U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
+
+       REG_WR(bp, BAR_TSTRORM_INTMEM +
+              TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
+              U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
+       REG_WR(bp, BAR_TSTRORM_INTMEM +
+              TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
+              U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
+
+       REG_WR(bp, BAR_USTRORM_INTMEM +
+              USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
+              U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
+       REG_WR(bp, BAR_USTRORM_INTMEM +
+              USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
+              U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
+
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
+                       IS_E1HMF(bp));
+               REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
+                       IS_E1HMF(bp));
+               REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
+                       IS_E1HMF(bp));
+               REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
+                       IS_E1HMF(bp));
+
+               REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
+                        bp->e1hov);
+       }
+
+       /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
+       max_agg_size =
+               min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
+                         SGE_PAGE_SIZE * PAGES_PER_SGE),
+                   (u32)0xffff);
+       for_each_rx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
+                      U64_LO(fp->rx_comp_mapping));
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
+                      U64_HI(fp->rx_comp_mapping));
+
+               /* Next page */
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id),
+                      U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE));
+               REG_WR(bp, BAR_USTRORM_INTMEM +
+                      USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4,
+                      U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE));
+
+               REG_WR16(bp, BAR_USTRORM_INTMEM +
+                        USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
+                        max_agg_size);
+       }
+
+       /* dropless flow control */
+       if (CHIP_IS_E1H(bp)) {
+               struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
+
+               rx_pause.bd_thr_low = 250;
+               rx_pause.cqe_thr_low = 250;
+               rx_pause.cos = 1;
+               rx_pause.sge_thr_low = 0;
+               rx_pause.bd_thr_high = 350;
+               rx_pause.cqe_thr_high = 350;
+               rx_pause.sge_thr_high = 0;
+
+               for_each_rx_queue(bp, i) {
+                       struct bnx2x_fastpath *fp = &bp->fp[i];
+
+                       if (!fp->disable_tpa) {
+                               rx_pause.sge_thr_low = 150;
+                               rx_pause.sge_thr_high = 250;
+                       }
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+                       if (bp->flags & SAFC_TX_FLAG) {
+                               rx_pause.cos = 0;
+                               for (j = 0; j < BNX2X_MAX_PRIORITY; j++)
+                                       if (bp->pri_map[j] == fp->cos)
+                                               rx_pause.cos |= (1 << j);
+                       }
+#endif
+
+                       offset = BAR_USTRORM_INTMEM +
+                                USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
+                                                                  fp->cl_id);
+                       for (j = 0;
+                            j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
+                            j++)
+                               REG_WR(bp, offset + j*4,
+                                      ((u32 *)&rx_pause)[j]);
+               }
+       }
+
+       memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
+
+       /* Init rate shaping and fairness contexts */
+       if (IS_E1HMF(bp)) {
+               int vn;
+
+               /* During init there is no active link
+                  Until link is up, set link rate to 10Gbps */
+               bp->link_vars.line_speed = SPEED_10000;
+               bnx2x_init_port_minmax(bp);
+
+               bnx2x_calc_vn_weight_sum(bp);
+
+               for (vn = VN_0; vn < E1HVN_MAX; vn++)
+                       bnx2x_init_vn_minmax(bp, 2*vn + port);
+
+               /* Enable rate shaping and fairness */
+               bp->cmng.flags.cmng_enables =
+                                       CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
+               if (bp->vn_weight_sum)
+                       bp->cmng.flags.cmng_enables |=
+                                       CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
+               else
+                       DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
+                          "  fairness will be disabled\n");
+       } else {
+#ifdef BNX2X_SAFC
+               if (bp->cos_weight_sum) {
+                       /* During init there is no active link
+                          Until link is up, set link rate to 10Gbps */
+                       bp->link_vars.line_speed = SPEED_10000;
+                       bnx2x_init_port_minmax(bp);
+
+                       bnx2x_init_cos_credit(bp);
+
+                       /* Enable fairness */
+                       bp->cmng.flags.cmng_enables =
+                                       CMNG_FLAGS_PER_PORT_FAIRNESS_COS;
+               } else
+                       DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
+                          "  fairness will be disabled\n");
+#else /* BNX2X_UPSTREAM */
+               /* rate shaping and fairness are disabled */
+               DP(NETIF_MSG_IFUP,
+                  "single function mode  minmax will be disabled\n");
+#endif
+       }
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       switch (bp->multi_mode) {
+       case ETH_RSS_MODE_DISABLED:
+       case ETH_RSS_MODE_REGULAR:
+               break;
+
+       case ETH_RSS_MODE_VLAN_PRI:
+       case ETH_RSS_MODE_E1HOV_PRI:
+       case ETH_RSS_MODE_IP_DSCP:
+               bp->cmng.safc_vars.safc_timeout_usec = 200;
+               for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
+                       bp->cmng.safc_vars.cos_to_pause_mask[i] =
+                                                       (1 << bp->pri_map[i]);
+               break;
+
+       default:
+               break;
+       }
+#endif
+
+       /* Store it to internal memory */
+       if (bp->port.pmf)
+               for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
+                       REG_WR(bp, BAR_XSTRORM_INTMEM +
+                              XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
+                              ((u32 *)(&bp->cmng))[i]);
+}
+
+static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
+{
+       switch (load_code) {
+       case FW_MSG_CODE_DRV_LOAD_COMMON:
+               bnx2x_init_internal_common(bp);
+               /* no break */
+
+       case FW_MSG_CODE_DRV_LOAD_PORT:
+               bnx2x_init_internal_port(bp);
+               /* no break */
+
+       case FW_MSG_CODE_DRV_LOAD_FUNCTION:
+               bnx2x_init_internal_func(bp);
+               break;
+
+       default:
+               BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
+               break;
+       }
+}
+
+static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
+{
+       int i;
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       int cos, num_queues;
+#endif
+
+       for_each_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               fp->bp = bp;
+               fp->state = BNX2X_FP_STATE_CLOSED;
+               fp->index = i;
+               fp->cl_id = BP_L_ID(bp) + i;
+#ifdef BCM_CNIC
+               fp->sb_id = fp->cl_id + 1;
+#else/* BNX2X_UPSTREAM */
+               fp->sb_id = fp->cl_id;
+#endif
+               /* Suitable Rx and Tx SBs are served by the same client */
+               if (i >= bp->num_rx_queues)
+                       fp->cl_id -= bp->num_rx_queues;
+#ifdef BNX2X_SAFC
+               num_queues = 0;
+               for (cos = 0; cos < BNX2X_MAX_COS; cos++) {
+                       if (i < (num_queues + bp->qs_per_cos[cos])) {
+                               fp->cos = cos;
+                               break;
+                       } else
+                               num_queues += bp->qs_per_cos[cos];
+               }
+               DP(NETIF_MSG_IFUP, "queue[%d]:  bnx2x_init_sb(%p,%p)  "
+                                  "cl_id %d  sb %d  cos %d\n",
+                  i, bp, fp->status_blk, fp->cl_id, fp->sb_id, fp->cos);
+#else /* BNX2X_UPSTREAM */
+               DP(NETIF_MSG_IFUP,
+                  "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  sb %d\n",
+                  i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
+#endif
+               bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
+                             fp->sb_id);
+               bnx2x_update_fpsb_idx(fp);
+       }
+
+       /* ensure status block indices were read */
+       rmb();
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       for (cos = 0; cos < BNX2X_MAX_COS; cos++) {
+               bp->cos_map[cos] = 0;
+               for_each_queue(bp, i) {
+                       /* take the 1st queue that belongs to this cos */
+                       if (bp->fp[i].cos == cos) {
+                               bp->cos_map[cos] = i;
+                               break;
+                       }
+               }
+       }
+#endif
+
+       bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
+                         DEF_SB_ID);
+       bnx2x_update_dsb_idx(bp);
+       bnx2x_update_coalesce(bp);
+       bnx2x_init_rx_rings(bp);
+       bnx2x_init_tx_ring(bp);
+       bnx2x_init_sp_ring(bp);
+       bnx2x_init_context(bp);
+       bnx2x_init_internal(bp, load_code);
+       bnx2x_init_ind_table(bp);
+       bnx2x_stats_init(bp);
+
+       /* At this point, we are ready for interrupts */
+       atomic_set(&bp->intr_sem, 0);
+
+       /* flush all before enabling interrupts */
+       mb();
+       mmiowb();
+
+       bnx2x_int_enable(bp);
+
+       /* Check for SPIO5 */
+       bnx2x_attn_int_deasserted0(bp,
+               REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
+                                  AEU_INPUTS_ATTN_BITS_SPIO5);
+}
+
+/* end of nic init */
+
+/*
+ * gzip service functions
+ */
+
+static int bnx2x_gunzip_init(struct bnx2x *bp)
+{
+       bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
+                                             &bp->gunzip_mapping);
+       if (bp->gunzip_buf  == NULL)
+               goto gunzip_nomem1;
+
+       bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
+       if (bp->strm  == NULL)
+               goto gunzip_nomem2;
+
+       bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
+                                     GFP_KERNEL);
+       if (bp->strm->workspace == NULL)
+               goto gunzip_nomem3;
+
+       return 0;
+
+gunzip_nomem3:
+       kfree(bp->strm);
+       bp->strm = NULL;
+
+gunzip_nomem2:
+       pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
+                           bp->gunzip_mapping);
+       bp->gunzip_buf = NULL;
+
+gunzip_nomem1:
+       printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
+              " un-compression\n", bp->dev->name);
+       return -ENOMEM;
+}
+
+static void bnx2x_gunzip_end(struct bnx2x *bp)
+{
+       kfree(bp->strm->workspace);
+
+       kfree(bp->strm);
+       bp->strm = NULL;
+
+       if (bp->gunzip_buf) {
+               pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
+                                   bp->gunzip_mapping);
+               bp->gunzip_buf = NULL;
+       }
+}
+
+static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
+{
+       int n, rc;
+
+       /* check gzip header */
+       if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
+               BNX2X_ERR("Bad gzip header\n");
+               return -EINVAL;
+       }
+
+       n = 10;
+
+#define FNAME                          0x8
+
+       if (zbuf[3] & FNAME)
+               while ((zbuf[n++] != 0) && (n < len));
+
+       bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
+       bp->strm->avail_in = len - n;
+       bp->strm->next_out = bp->gunzip_buf;
+       bp->strm->avail_out = FW_BUF_SIZE;
+
+       rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
+       if (rc != Z_OK)
+               return rc;
+
+       rc = zlib_inflate(bp->strm, Z_FINISH);
+       if ((rc != Z_OK) && (rc != Z_STREAM_END))
+               printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
+                      bp->dev->name, bp->strm->msg);
+
+       bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
+       if (bp->gunzip_outlen & 0x3)
+               printk(KERN_ERR PFX "%s: Firmware decompression error:"
+                                   " gunzip_outlen (%d) not aligned\n",
+                      bp->dev->name, bp->gunzip_outlen);
+       bp->gunzip_outlen >>= 2;
+
+       zlib_inflateEnd(bp->strm);
+
+       if (rc == Z_STREAM_END)
+               return 0;
+
+       return rc;
+}
+
+/* nic load/unload */
+
+/*
+ * General service functions
+ */
+
+/* send a NIG loopback debug packet */
+static void bnx2x_lb_pckt(struct bnx2x *bp)
+{
+       u32 wb_write[3];
+
+       /* Ethernet source and destination addresses */
+       wb_write[0] = 0x55555555;
+       wb_write[1] = 0x55555555;
+       wb_write[2] = 0x20;             /* SOP */
+       REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
+
+       /* NON-IP protocol */
+       wb_write[0] = 0x09000000;
+       wb_write[1] = 0x55555555;
+       wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
+       REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
+}
+
+/* some of the internal memories
+ * are not directly readable from the driver
+ * to test them we send debug packets
+ */
+static int bnx2x_int_mem_test(struct bnx2x *bp)
+{
+       int factor;
+       int count, i;
+       u32 val = 0;
+
+       if (CHIP_REV_IS_FPGA(bp))
+               factor = 120;
+       else if (CHIP_REV_IS_EMUL(bp))
+               factor = 200;
+       else
+               factor = 1;
+
+       DP(NETIF_MSG_HW, "start part1\n");
+
+       /* Disable inputs of parser neighbor blocks */
+       REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
+       REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
+       REG_WR(bp, CFC_REG_DEBUG0, 0x1);
+       REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
+
+       /*  Write 0 to parser credits for CFC search request */
+       REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
+
+       /* send Ethernet packet */
+       bnx2x_lb_pckt(bp);
+
+       /* TODO do i reset NIG statistic? */
+       /* Wait until NIG register shows 1 packet of size 0x10 */
+       count = 1000 * factor;
+       while (count) {
+
+               bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
+               val = *bnx2x_sp(bp, wb_data[0]);
+               if (val == 0x10)
+                       break;
+
+               msleep(10);
+               count--;
+       }
+       if (val != 0x10) {
+               BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
+               return -1;
+       }
+
+       /* Wait until PRS register shows 1 packet */
+       count = 1000 * factor;
+       while (count) {
+               val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
+               if (val == 1)
+                       break;
+
+               msleep(10);
+               count--;
+       }
+       if (val != 0x1) {
+               BNX2X_ERR("PRS timeout val = 0x%x\n", val);
+               return -2;
+       }
+
+       /* Reset and init BRB, PRS */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
+       msleep(50);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
+       msleep(50);
+       bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
+
+       DP(NETIF_MSG_HW, "part2\n");
+
+       /* Disable inputs of parser neighbor blocks */
+       REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
+       REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
+       REG_WR(bp, CFC_REG_DEBUG0, 0x1);
+       REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
+
+       /* Write 0 to parser credits for CFC search request */
+       REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
+
+       /* send 10 Ethernet packets */
+       for (i = 0; i < 10; i++)
+               bnx2x_lb_pckt(bp);
+
+       /* Wait until NIG register shows 10 + 1
+          packets of size 11*0x10 = 0xb0 */
+       count = 1000 * factor;
+       while (count) {
+
+               bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
+               val = *bnx2x_sp(bp, wb_data[0]);
+               if (val == 0xb0)
+                       break;
+
+               msleep(10);
+               count--;
+       }
+       if (val != 0xb0) {
+               BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
+               return -3;
+       }
+
+       /* Wait until PRS register shows 2 packets */
+       val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
+       if (val != 2)
+               BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
+
+       /* Write 1 to parser credits for CFC search request */
+       REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
+
+       /* Wait until PRS register shows 3 packets */
+       msleep(10 * factor);
+       /* Wait until NIG register shows 1 packet of size 0x10 */
+       val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
+       if (val != 3)
+               BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
+
+       /* clear NIG EOP FIFO */
+       for (i = 0; i < 11; i++)
+               REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
+       val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
+       if (val != 1) {
+               BNX2X_ERR("clear of NIG failed\n");
+               return -4;
+       }
+
+       /* Reset and init BRB, PRS, NIG */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
+       msleep(50);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
+       msleep(50);
+       bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
+#ifndef BCM_CNIC /* BNX2X_UPSTREAM */
+       /* set NIC mode */
+       REG_WR(bp, PRS_REG_NIC_MODE, 1);
+#endif
+
+       /* Enable inputs of parser neighbor blocks */
+       REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
+       REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
+       REG_WR(bp, CFC_REG_DEBUG0, 0x0);
+       REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
+
+       DP(NETIF_MSG_HW, "done\n");
+
+       return 0; /* OK */
+}
+
+static void enable_blocks_attention(struct bnx2x *bp)
+{
+       REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
+       REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
+       REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
+       REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
+       REG_WR(bp, QM_REG_QM_INT_MASK, 0);
+       REG_WR(bp, TM_REG_TM_INT_MASK, 0);
+       REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
+       REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
+       REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
+/*     REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
+/*     REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
+       REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
+       REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
+       REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
+/*     REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
+/*     REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
+       REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
+       REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
+       REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
+       REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
+/*     REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
+/*     REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
+       if (CHIP_REV_IS_FPGA(bp))
+               REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
+       else
+               REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
+       REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
+       REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
+       REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
+/*     REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
+/*     REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
+       REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
+       REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
+/*     REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
+       REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
+}
+
+#ifdef BNX2X_EXTRA_DEBUG /* ! BNX2X_UPSTREAM */
+static void enable_blocks_parity(struct bnx2x *bp)
+{
+       REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000);     /* bit 19 masked */
+       REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020);/* bit 5,18,20-31 */
+       REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);    /* bit 5 */
+       REG_WR(bp, QM_REG_QM_PRTY_MASK, 0x0);
+       REG_WR(bp, DORQ_REG_DORQ_PRTY_MASK, 0x0);
+       REG_WR(bp, GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0);
+       REG_WR(bp, GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0);
+       REG_WR(bp, SRC_REG_SRC_PRTY_MASK, 0x4);         /* bit 2 */
+       REG_WR(bp, CDU_REG_CDU_PRTY_MASK, 0x0);
+       REG_WR(bp, CFC_REG_CFC_PRTY_MASK, 0x0);
+       REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0);
+       REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0);
+       REG_WR(bp, DBG_REG_DBG_PRTY_MASK, 0x0);
+       REG_WR(bp, DMAE_REG_DMAE_PRTY_MASK, 0x0);
+       REG_WR(bp, BRB1_REG_BRB1_PRTY_MASK, 0x0);
+       REG_WR(bp, PRS_REG_PRS_PRTY_MASK, (1<<6));      /* bit 6 */
+       REG_WR(bp, TSDM_REG_TSDM_PRTY_MASK, 0x8);       /* bit 3 */
+       REG_WR(bp, CSDM_REG_CSDM_PRTY_MASK, 0x8);       /* bit 3 */
+       REG_WR(bp, USDM_REG_USDM_PRTY_MASK, 0x28);      /* bit 3,5 */
+       REG_WR(bp, XSDM_REG_XSDM_PRTY_MASK, 0x8);       /* bit 3 */
+       REG_WR(bp, TSEM_REG_TSEM_PRTY_MASK_0, 0x0);
+       REG_WR(bp, TSEM_REG_TSEM_PRTY_MASK_1, 0x0);
+       REG_WR(bp, USEM_REG_USEM_PRTY_MASK_0, 0x0);
+       REG_WR(bp, USEM_REG_USEM_PRTY_MASK_1, 0x0);
+       REG_WR(bp, CSEM_REG_CSEM_PRTY_MASK_0, 0x0);
+       REG_WR(bp, CSEM_REG_CSEM_PRTY_MASK_1, 0x0);
+       REG_WR(bp, XSEM_REG_XSEM_PRTY_MASK_0, 0x0);
+       REG_WR(bp, XSEM_REG_XSEM_PRTY_MASK_1, 0x0);
+}
+#endif
+
+static void bnx2x_reset_common(struct bnx2x *bp)
+{
+       /* reset_common */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
+              0xd3ffff7f);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
+}
+
+static void bnx2x_init_pxp(struct bnx2x *bp)
+{
+       u16 devctl;
+       int r_order, w_order;
+
+       pci_read_config_word(bp->pdev,
+                            bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
+       DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
+       w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+       if (bp->mrrs == -1)
+               r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+       else {
+               DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
+               r_order = bp->mrrs;
+       }
+
+       bnx2x_init_pxp_arb(bp, r_order, w_order);
+}
+
+static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
+{
+       u32 val;
+       u8 port;
+       u8 is_required = 0;
+
+       val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
+             SHARED_HW_CFG_FAN_FAILURE_MASK;
+
+       if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
+               is_required = 1;
+
+       /*
+        * The fan failure mechanism is usually related to the PHY type since
+        * the power consumption of the board is affected by the PHY. Currently,
+        * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
+        */
+       else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
+               for (port = PORT_0; port < PORT_MAX; port++) {
+                       u32 phy_type =
+                               SHMEM_RD(bp, dev_info.port_hw_config[port].
+                                        external_phy_config) &
+                               PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+                       is_required |=
+                               ((phy_type ==
+                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
+                                (phy_type ==
+                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
+                                (phy_type ==
+                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
+               }
+
+       DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
+
+       if (is_required == 0)
+               return;
+
+       /* Fan failure is indicated by SPIO 5 */
+       bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
+                      MISC_REGISTERS_SPIO_INPUT_HI_Z);
+
+       /* set to active low mode */
+       val = REG_RD(bp, MISC_REG_SPIO_INT);
+       val |= ((1 << MISC_REGISTERS_SPIO_5) <<
+                               MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
+       REG_WR(bp, MISC_REG_SPIO_INT, val);
+
+       /* enable interrupt to signal the IGU */
+       val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
+       val |= (1 << MISC_REGISTERS_SPIO_5);
+       REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
+}
+
+static int bnx2x_init_common(struct bnx2x *bp)
+{
+       u32 val, i;
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       u32 wb_write[2];
+#endif
+
+       DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
+
+       bnx2x_reset_common(bp);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
+
+       bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
+       if (CHIP_IS_E1H(bp))
+               REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
+
+       REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
+       msleep(30);
+       REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
+
+       bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
+       if (CHIP_IS_E1(bp)) {
+               /* enable HW interrupt from PXP on USDM overflow
+                  bit 16 on INT_MASK_0 */
+               REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
+       }
+
+       bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
+       bnx2x_init_pxp(bp);
+
+#ifdef __BIG_ENDIAN
+       REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
+       REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
+       REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
+       REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
+       REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
+       /* make sure this value is 0 */
+       REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
+
+/*     REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
+       REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
+       REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
+       REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
+       REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
+#endif
+
+       REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
+       REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
+       REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
+#endif
+
+       if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
+               REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
+
+       /* let the HW do it's magic ... */
+       msleep(100);
+       /* finish PXP init */
+       val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
+       if (val != 1) {
+               BNX2X_ERR("PXP2 CFG failed\n");
+               return -EBUSY;
+       }
+       val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
+       if (val != 1) {
+               BNX2X_ERR("PXP2 RD_INIT failed\n");
+               return -EBUSY;
+       }
+
+       REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
+       REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
+
+       bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
+
+       /* clean the DMAE memory */
+       bp->dmae_ready = 1;
+       bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
+
+       bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
+
+       bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
+       bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
+       bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
+       bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
+
+       bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       switch (bp->multi_mode) {
+       case ETH_RSS_MODE_DISABLED:
+       case ETH_RSS_MODE_REGULAR:
+               break;
+
+       case ETH_RSS_MODE_VLAN_PRI:
+       case ETH_RSS_MODE_E1HOV_PRI:
+       case ETH_RSS_MODE_IP_DSCP:
+               REG_WR(bp, QM_REG_BYTECRDINITVAL, 0x5dc0);
+               break;
+
+       default:
+               break;
+       }
+#endif
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       wb_write[0] = 0;
+       wb_write[1] = 0;
+       for (i = 0; i < 64; i++) {
+               REG_WR(bp, QM_REG_BASEADDR + i*4, 1024 * 4 * (i%16));
+               bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8, wb_write, 2);
+
+               if (CHIP_IS_E1H(bp)) {
+                       REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4, 1024*4*(i%16));
+                       bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8,
+                                         wb_write, 2);
+               }
+       }
+#endif
+       /* soft reset pulse */
+       REG_WR(bp, QM_REG_SOFT_RESET, 1);
+       REG_WR(bp, QM_REG_SOFT_RESET, 0);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
+#endif
+
+       bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
+       REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
+       if (!CHIP_REV_IS_SLOW(bp)) {
+               /* enable hw interrupt from doorbell Q */
+               REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
+       }
+
+       bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
+       REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
+#ifndef BCM_CNIC /* BNX2X_UPSTREAM */
+       /* set NIC mode */
+       REG_WR(bp, PRS_REG_NIC_MODE, 1);
+#endif
+#ifdef BNX2X_SAFC
+       if (CHIP_IS_E1H(bp)) {
+               val = (IS_E1HMF(bp) ||
+                      (bp->multi_mode == ETH_RSS_MODE_E1HOV_PRI)) ? 1 : 0;
+               REG_WR(bp, PRS_REG_E1HOV_MODE, val);
+       }
+#else /* BNX2X_UPSTREAM */
+       if (CHIP_IS_E1H(bp))
+               REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
+#endif
+
+       bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
+
+       bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+       bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+       bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+
+       bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
+
+       /* sync semi rtc */
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
+              0x80000000);
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
+              0x80000000);
+
+       bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
+
+       REG_WR(bp, SRC_REG_SOFT_RST, 1);
+       for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
+               REG_WR(bp, i, 0xc0cac01a);
+               /* TODO: replace with something meaningful */
+       }
+       bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
+       REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
+       REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
+       REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
+       REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
+       REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
+       REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
+       REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
+       REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
+       REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
+#endif
+       REG_WR(bp, SRC_REG_SOFT_RST, 0);
+
+       if (sizeof(union cdu_context) != 1024)
+               /* we currently assume that a context is 1024 bytes */
+               printk(KERN_ALERT PFX "please adjust the size of"
+                      " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
+
+       bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
+       val = (4 << 24) + (0 << 12) + 1024;
+       REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
+
+       bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
+       REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
+       /* enable context validation interrupt from CFC */
+       REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
+
+       /* set the thresholds to prevent CFC/CDU race */
+       REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
+
+       bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
+
+       bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
+       /* Reset PCIE errors for debug */
+       REG_WR(bp, 0x2814, 0xffffffff);
+       REG_WR(bp, 0x3820, 0xffffffff);
+
+       bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
+
+       bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
+               REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
+       }
+
+       if (CHIP_REV_IS_SLOW(bp))
+               msleep(200);
+
+       /* finish CFC init */
+       val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
+       if (val != 1) {
+               BNX2X_ERR("CFC LL_INIT failed\n");
+               return -EBUSY;
+       }
+       val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
+       if (val != 1) {
+               BNX2X_ERR("CFC AC_INIT failed\n");
+               return -EBUSY;
+       }
+       val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
+       if (val != 1) {
+               BNX2X_ERR("CFC CAM_INIT failed\n");
+               return -EBUSY;
+       }
+       REG_WR(bp, CFC_REG_DEBUG0, 0);
+
+       /* read NIG statistic
+          to see if this is our first up since powerup */
+       bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
+       val = *bnx2x_sp(bp, wb_data[0]);
+
+       /* do internal memory self test */
+       if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
+               BNX2X_ERR("internal mem self test failed\n");
+               return -EBUSY;
+       }
+
+       switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               bp->port.need_hw_lock = 1;
+               break;
+
+       default:
+               break;
+       }
+
+       bnx2x_setup_fan_failure_detection(bp);
+
+       /* clear PXP2 attentions */
+       REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
+
+       enable_blocks_attention(bp);
+#ifdef BNX2X_EXTRA_DEBUG /* ! BNX2X_UPSTREAM */
+       enable_blocks_parity(bp);
+#endif
+
+       if (!BP_NOMCP(bp)) {
+               bnx2x_acquire_phy_lock(bp);
+               bnx2x_common_init_phy(bp, bp->common.shmem_base);
+               bnx2x_release_phy_lock(bp);
+       } else
+               BNX2X_ERR("Bootcode is missing - can not initialize link\n");
+
+       return 0;
+}
+
+static int bnx2x_init_port(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
+       u32 low, high;
+       u32 val;
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       int i;
+#endif
+
+       DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
+
+       REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
+
+       bnx2x_init_block(bp, PXP_BLOCK, init_stage);
+       bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, TCM_BLOCK, init_stage);
+       bnx2x_init_block(bp, UCM_BLOCK, init_stage);
+       bnx2x_init_block(bp, CCM_BLOCK, init_stage);
+       bnx2x_init_block(bp, XCM_BLOCK, init_stage);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       REG_WR(bp, QM_REG_CONNNUM_0 + port*4, 1024/16 - 1);
+
+       bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
+       REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
+       REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
+#endif
+
+       bnx2x_init_block(bp, DQ_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
+       if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
+               /* no pause for emulation and FPGA */
+               low = 0;
+               high = 513;
+       } else {
+               if (IS_E1HMF(bp))
+                       low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
+               else if (bp->dev->mtu > 4096) {
+                       if (bp->flags & ONE_PORT_FLAG)
+                               low = 160;
+                       else {
+                               val = bp->dev->mtu;
+                               /* (24*1024 + val*4)/256 */
+                               low = 96 + (val/64) + ((val % 64) ? 1 : 0);
+                       }
+               } else
+                       low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
+               high = low + 56;        /* 14*1024/256 */
+       }
+       REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
+       REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       if (bp->flags & SAFC_TX_FLAG) {
+               REG_WR(bp, BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 + port*4, 0xa0);
+               REG_WR(bp, BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 + port*4, 0xd8);
+               REG_WR(bp, BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 + port*4, 0xa0);
+               REG_WR(bp, BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 + port*4, 0xd8);
+       }
+#endif
+
+       bnx2x_init_block(bp, PRS_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
+       bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
+       bnx2x_init_block(bp, USDM_BLOCK, init_stage);
+       bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
+       bnx2x_init_block(bp, USEM_BLOCK, init_stage);
+       bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
+       bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, UPB_BLOCK, init_stage);
+       bnx2x_init_block(bp, XPB_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, PBF_BLOCK, init_stage);
+
+       /* configure PBF to work without PAUSE mtu 9000 */
+       REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
+
+       /* update threshold */
+       REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
+       /* update init credit */
+       REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
+
+       /* probe changes */
+       REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
+       msleep(5);
+       REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
+#endif
+       bnx2x_init_block(bp, CDU_BLOCK, init_stage);
+       bnx2x_init_block(bp, CFC_BLOCK, init_stage);
+
+       if (CHIP_IS_E1(bp)) {
+               REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
+               REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
+       }
+       bnx2x_init_block(bp, HC_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
+       /* init aeu_mask_attn_func_0/1:
+        *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
+        *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
+        *             bits 4-7 are used for "per vn group attention" */
+       REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
+              (IS_E1HMF(bp) ? 0xF7 : 0x7));
+
+       bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
+       bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
+       bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
+       bnx2x_init_block(bp, DBU_BLOCK, init_stage);
+       bnx2x_init_block(bp, DBG_BLOCK, init_stage);
+
+       bnx2x_init_block(bp, NIG_BLOCK, init_stage);
+
+       REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
+
+       if (CHIP_IS_E1H(bp)) {
+               /* 0x2 disable e1hov, 0x1 enable */
+               REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
+                      (IS_E1HMF(bp) ? 0x1 : 0x2));
+
+#ifdef BNX2X_SAFC
+               if (bp->flags & SAFC_TX_FLAG) {
+                       high = 0;
+                       for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
+                               if (bp->pri_map[i] == 1)
+                                       high |= (1 << i);
+                       REG_WR(bp,
+                              NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 + port*4,
+                              high);
+                       low = 0;
+                       for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
+                               if (bp->pri_map[i] == 0)
+                                       low |= (1 << i);
+                       REG_WR(bp,
+                              NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 + port*4,
+                              low);
+
+                       REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 0);
+                       REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 1);
+                       REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 1);
+               } else {
+#else /* BNX2X_UPSTREAM */
+               {
+#endif
+                       REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
+                       REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
+                       REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
+               }
+       }
+
+       bnx2x_init_block(bp, MCP_BLOCK, init_stage);
+       bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
+
+       switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               {
+               u32 swap_val, swap_override, aeu_gpio_mask, offset;
+
+               bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
+                              MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
+
+               /* The GPIO should be swapped if the swap register is
+                  set and active */
+               swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
+               swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
+
+               /* Select function upon port-swap configuration */
+               if (port == 0) {
+                       offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+                       aeu_gpio_mask = (swap_val && swap_override) ?
+                               AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
+                               AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
+               } else {
+                       offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
+                       aeu_gpio_mask = (swap_val && swap_override) ?
+                               AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
+                               AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
+               }
+               val = REG_RD(bp, offset);
+               /* add GPIO3 to group */
+               val |= aeu_gpio_mask;
+               REG_WR(bp, offset, val);
+               }
+               break;
+
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+       case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+               /* add SPIO 5 to group 0 */
+               {
+               u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
+               val = REG_RD(bp, reg_addr);
+               val |= AEU_INPUTS_ATTN_BITS_SPIO5;
+               REG_WR(bp, reg_addr, val);
+               }
+               break;
+
+       default:
+               break;
+       }
+
+       bnx2x__link_reset(bp);
+
+       return 0;
+}
+
+#define ILT_PER_FUNC           (768/2)
+#define FUNC_ILT_BASE(func)    (func * ILT_PER_FUNC)
+/* the phys address is shifted right 12 bits and has an added
+   1=valid bit added to the 53rd bit
+   then since this is a wide register(TM)
+   we split it into two 32 bit writes
+ */
+#define ONCHIP_ADDR1(x)                ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
+#define ONCHIP_ADDR2(x)                ((u32)((1 << 20) | ((u64)x >> 44)))
+#define PXP_ONE_ILT(x)         (((x) << 10) | x)
+#define PXP_ILT_RANGE(f, l)    (((l) << 10) | f)
+
+#ifdef BCM_CNIC
+#define CNIC_ILT_LINES         127
+#define CNIC_CTX_PER_ILT       16
+#else /* BNX2X_UPSTREAM */
+#define CNIC_ILT_LINES         0
+#endif
+
+static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
+{
+       int reg;
+
+       if (CHIP_IS_E1H(bp))
+               reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
+       else /* E1 */
+               reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
+
+       bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
+}
+
+static int bnx2x_init_func(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int func = BP_FUNC(bp);
+       u32 addr, val;
+       int i;
+
+       DP(BNX2X_MSG_MCP, "starting func init  func %x\n", func);
+
+       /* set MSI reconfigure capability */
+       addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
+       val = REG_RD(bp, addr);
+       val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
+       REG_WR(bp, addr, val);
+
+       i = FUNC_ILT_BASE(func);
+
+       bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
+               REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
+       } else /* E1 */
+               REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
+                      PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       i += 1 + CNIC_ILT_LINES;
+       bnx2x_ilt_wr(bp, i, bp->timers_mapping);
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR(bp, PXP2_REG_RQ_TM_FIRST_ILT, i);
+               REG_WR(bp, PXP2_REG_RQ_TM_LAST_ILT, i);
+       } else /* E1 */
+               REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
+
+       i++;
+       bnx2x_ilt_wr(bp, i, bp->qm_mapping);
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR(bp, PXP2_REG_RQ_QM_FIRST_ILT, i);
+               REG_WR(bp, PXP2_REG_RQ_QM_LAST_ILT, i);
+       } else /* E1 */
+               REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
+
+       i++;
+       bnx2x_ilt_wr(bp, i, bp->t1_mapping);
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR(bp, PXP2_REG_RQ_SRC_FIRST_ILT, i);
+               REG_WR(bp, PXP2_REG_RQ_SRC_LAST_ILT, i);
+       } else /* E1 */
+               REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
+
+       /* tell the searcher where the T2 table is */
+       REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, 16*1024/64);
+
+       bnx2x_wb_wr(bp, SRC_REG_FIRSTFREE0 + port*16,
+                   U64_LO(bp->t2_mapping), U64_HI(bp->t2_mapping));
+
+       bnx2x_wb_wr(bp, SRC_REG_LASTFREE0 + port*16,
+                   U64_LO((u64)bp->t2_mapping + 16*1024 - 64),
+                   U64_HI((u64)bp->t2_mapping + 16*1024 - 64));
+
+       REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, 10);
+#endif
+
+       if (CHIP_IS_E1H(bp)) {
+               bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
+               bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
+
+               REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
+               REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
+       }
+
+       /* HC init per function */
+       if (CHIP_IS_E1H(bp)) {
+               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
+
+               REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
+               REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
+       }
+       bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
+
+       /* Reset PCIE errors for debug */
+       REG_WR(bp, 0x2114, 0xffffffff);
+       REG_WR(bp, 0x2120, 0xffffffff);
+
+       return 0;
+}
+
+static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
+{
+       int i, rc = 0;
+
+       DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
+          BP_FUNC(bp), load_code);
+
+       bp->dmae_ready = 0;
+       mutex_init(&bp->dmae_mutex);
+       rc = bnx2x_gunzip_init(bp);
+       if (rc)
+               return rc;
+
+       switch (load_code) {
+       case FW_MSG_CODE_DRV_LOAD_COMMON:
+               rc = bnx2x_init_common(bp);
+               if (rc)
+                       goto init_hw_err;
+               /* no break */
+
+       case FW_MSG_CODE_DRV_LOAD_PORT:
+               bp->dmae_ready = 1;
+               rc = bnx2x_init_port(bp);
+               if (rc)
+                       goto init_hw_err;
+               /* no break */
+
+       case FW_MSG_CODE_DRV_LOAD_FUNCTION:
+               bp->dmae_ready = 1;
+               rc = bnx2x_init_func(bp);
+               if (rc)
+                       goto init_hw_err;
+               break;
+
+       default:
+               BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
+               break;
+       }
+
+       if (!BP_NOMCP(bp)) {
+               int func = BP_FUNC(bp);
+
+               bp->fw_drv_pulse_wr_seq =
+                               (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
+                                DRV_PULSE_SEQ_MASK);
+               DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
+       }
+
+       /* this needs to be done before gunzip end */
+       bnx2x_zero_def_sb(bp);
+       for_each_queue(bp, i)
+               bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
+#endif
+
+init_hw_err:
+       bnx2x_gunzip_end(bp);
+
+       return rc;
+}
+
+static void bnx2x_free_mem(struct bnx2x *bp)
+{
+
+#define BNX2X_PCI_FREE(x, y, size) \
+       do { \
+               if (x) { \
+                       pci_free_consistent(bp->pdev, size, x, y); \
+                       x = NULL; \
+                       y = 0; \
+               } \
+       } while (0)
+
+#define BNX2X_FREE(x) \
+       do { \
+               if (x) { \
+                       vfree(x); \
+                       x = NULL; \
+               } \
+       } while (0)
+
+       int i;
+
+       /* fastpath */
+       /* Common */
+       for_each_queue(bp, i) {
+
+               /* status blocks */
+               BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
+                              bnx2x_fp(bp, i, status_blk_mapping),
+                              sizeof(struct host_status_block));
+       }
+       /* Rx */
+       for_each_rx_queue(bp, i) {
+
+               /* fastpath rx rings: rx_buf rx_desc rx_comp */
+               BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
+               BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
+                              bnx2x_fp(bp, i, rx_desc_mapping),
+                              sizeof(struct eth_rx_bd) * NUM_RX_BD);
+
+               BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
+                              bnx2x_fp(bp, i, rx_comp_mapping),
+                              sizeof(struct eth_fast_path_rx_cqe) *
+                              NUM_RCQ_BD);
+
+               /* SGE ring */
+               BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
+               BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
+                              bnx2x_fp(bp, i, rx_sge_mapping),
+                              BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
+       }
+       /* Tx */
+       for_each_tx_queue(bp, i) {
+
+               /* fastpath tx rings: tx_buf tx_desc */
+               BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
+               BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
+                              bnx2x_fp(bp, i, tx_desc_mapping),
+                              sizeof(union eth_tx_bd_types) * NUM_TX_BD);
+       }
+       /* end of fastpath */
+
+       BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
+                      sizeof(struct host_def_status_block));
+
+       BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
+                      sizeof(struct bnx2x_slowpath));
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
+       BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
+       BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
+       BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
+       BNX2X_PCI_FREE(bp->cnic_sb, bp->cnic_sb_mapping,
+                      sizeof(struct host_status_block));
+#endif
+       BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
+
+#undef BNX2X_PCI_FREE
+#undef BNX2X_KFREE
+}
+
+static int bnx2x_alloc_mem(struct bnx2x *bp)
+{
+
+#define BNX2X_PCI_ALLOC(x, y, size) \
+       do { \
+               x = pci_alloc_consistent(bp->pdev, size, y); \
+               if (x == NULL) \
+                       goto alloc_mem_err; \
+               memset(x, 0, size); \
+       } while (0)
+
+#define BNX2X_ALLOC(x, size) \
+       do { \
+               x = vmalloc(size); \
+               if (x == NULL) \
+                       goto alloc_mem_err; \
+               memset(x, 0, size); \
+       } while (0)
+
+       int i;
+
+       /* fastpath */
+       /* Common */
+       for_each_queue(bp, i) {
+               bnx2x_fp(bp, i, bp) = bp;
+
+               /* status blocks */
+               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
+                               &bnx2x_fp(bp, i, status_blk_mapping),
+                               sizeof(struct host_status_block));
+       }
+       /* Rx */
+       for_each_rx_queue(bp, i) {
+
+               /* fastpath rx rings: rx_buf rx_desc rx_comp */
+               BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
+                               sizeof(struct sw_rx_bd) * NUM_RX_BD);
+               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
+                               &bnx2x_fp(bp, i, rx_desc_mapping),
+                               sizeof(struct eth_rx_bd) * NUM_RX_BD);
+
+               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
+                               &bnx2x_fp(bp, i, rx_comp_mapping),
+                               sizeof(struct eth_fast_path_rx_cqe) *
+                               NUM_RCQ_BD);
+
+               /* SGE ring */
+               BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
+                               sizeof(struct sw_rx_page) * NUM_RX_SGE);
+               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
+                               &bnx2x_fp(bp, i, rx_sge_mapping),
+                               BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
+       }
+       /* Tx */
+       for_each_tx_queue(bp, i) {
+
+               /* fastpath tx rings: tx_buf tx_desc */
+               BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
+                               sizeof(struct sw_tx_bd) * NUM_TX_BD);
+               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
+                               &bnx2x_fp(bp, i, tx_desc_mapping),
+                               sizeof(union eth_tx_bd_types) * NUM_TX_BD);
+       }
+       /* end of fastpath */
+
+       BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
+                       sizeof(struct host_def_status_block));
+
+       BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
+                       sizeof(struct bnx2x_slowpath));
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
+
+       /* allocate searcher T2 table
+          we allocate 1/4 of alloc num for T2
+         (which is not entered into the ILT) */
+       BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
+
+       /* Initialize T2 (for 1024 connections) */
+       for (i = 0; i < 16*1024; i += 64)
+               *(u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
+
+       /* Timer block array (8*MAX_CONN) phys uncached for now 1024 conns */
+       BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
+
+       /* QM queues (128*MAX_CONN) */
+       BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
+
+       BNX2X_PCI_ALLOC(bp->cnic_sb, &bp->cnic_sb_mapping,
+                       sizeof(struct host_status_block));
+#endif
+
+       /* Slow path ring */
+       BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
+
+       return 0;
+
+alloc_mem_err:
+       bnx2x_free_mem(bp);
+       return -ENOMEM;
+
+#undef BNX2X_PCI_ALLOC
+#undef BNX2X_ALLOC
+}
+
+static void bnx2x_free_tx_skbs(struct bnx2x *bp)
+{
+       int i;
+
+       for_each_tx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               u16 bd_cons = fp->tx_bd_cons;
+               u16 sw_prod = fp->tx_pkt_prod;
+               u16 sw_cons = fp->tx_pkt_cons;
+
+               while (sw_cons != sw_prod) {
+                       bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
+                       sw_cons++;
+               }
+       }
+}
+
+static void bnx2x_free_rx_skbs(struct bnx2x *bp)
+{
+       int i, j;
+
+       for_each_rx_queue(bp, j) {
+               struct bnx2x_fastpath *fp = &bp->fp[j];
+
+               for (i = 0; i < NUM_RX_BD; i++) {
+                       struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
+                       struct sk_buff *skb = rx_buf->skb;
+
+                       if (skb == NULL)
+                               continue;
+
+                       pci_unmap_single(bp->pdev,
+                                        pci_unmap_addr(rx_buf, mapping),
+                                        bp->rx_buf_size, PCI_DMA_FROMDEVICE);
+
+                       rx_buf->skb = NULL;
+                       dev_kfree_skb(skb);
+               }
+               if (!fp->disable_tpa)
+                       bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
+                                           ETH_MAX_AGGREGATION_QUEUES_E1 :
+                                           ETH_MAX_AGGREGATION_QUEUES_E1H);
+       }
+}
+
+static void bnx2x_free_skbs(struct bnx2x *bp)
+{
+       bnx2x_free_tx_skbs(bp);
+       bnx2x_free_rx_skbs(bp);
+}
+
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+static void bnx2x_free_msix_irqs(struct bnx2x *bp)
+{
+       int i, offset = 1;
+
+       free_irq(bp->msix_table[0].vector, bp->dev);
+       DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
+          bp->msix_table[0].vector);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       offset++;
+#endif
+       for_each_queue(bp, i) {
+               DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq  "
+                  "state %x\n", i, bp->msix_table[i + offset].vector,
+                  bnx2x_fp(bp, i, state));
+
+               free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
+       }
+}
+#endif
+
+static void bnx2x_free_irq(struct bnx2x *bp)
+{
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+       if (bp->flags & USING_MSIX_FLAG) {
+               bnx2x_free_msix_irqs(bp);
+               pci_disable_msix(bp->pdev);
+               bp->flags &= ~USING_MSIX_FLAG;
+
+       } else if (bp->flags & USING_MSI_FLAG) {
+               free_irq(bp->pdev->irq, bp->dev);
+               pci_disable_msi(bp->pdev);
+               bp->flags &= ~USING_MSI_FLAG;
+
+       } else
+#endif
+               free_irq(bp->pdev->irq, bp->dev);
+}
+
+static int bnx2x_enable_msix(struct bnx2x *bp)
+{
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+       int i, rc, offset = 1;
+       int igu_vec = 0;
+
+       bp->msix_table[0].entry = igu_vec;
+       DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", igu_vec);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       igu_vec = BP_L_ID(bp) + offset;
+       bp->msix_table[1].entry = igu_vec;
+       DP(NETIF_MSG_IFUP, "msix_table[1].entry = %d (CNIC)\n", igu_vec);
+       offset++;
+#endif
+       for_each_queue(bp, i) {
+               igu_vec = BP_L_ID(bp) + offset + i;
+               bp->msix_table[i + offset].entry = igu_vec;
+               DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
+                  "(fastpath #%u)\n", i + offset, igu_vec, i);
+       }
+
+       rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
+                            BNX2X_NUM_QUEUES(bp) + offset);
+       if (rc) {
+               DP(NETIF_MSG_IFUP, "MSI-X is not attainable  rc %d\n", rc);
+               return rc;
+       }
+
+       bp->flags |= USING_MSIX_FLAG;
+
+       return 0;
+#else
+       return -1;
+#endif
+}
+
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+static int bnx2x_req_msix_irqs(struct bnx2x *bp)
+{
+       int i, rc, offset = 1;
+
+       rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
+                        bp->dev->name, bp->dev);
+       if (rc) {
+               BNX2X_ERR("request sp irq failed\n");
+               return -EBUSY;
+       }
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       offset++;
+#endif
+       for_each_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               if (i < bp->num_rx_queues)
+                       sprintf(fp->name, "%s-rx-%d", bp->dev->name, i);
+               else
+                       sprintf(fp->name, "%s-tx-%d",
+                               bp->dev->name, i - bp->num_rx_queues);
+
+               rc = request_irq(bp->msix_table[i + offset].vector,
+                                bnx2x_msix_fp_int, 0, fp->name, fp);
+               if (rc) {
+                       BNX2X_ERR("request fp #%d irq failed  rc %d\n", i, rc);
+                       bnx2x_free_msix_irqs(bp);
+                       return -EBUSY;
+               }
+
+               fp->state = BNX2X_FP_STATE_IRQ;
+       }
+
+       i = BNX2X_NUM_QUEUES(bp);
+       printk(KERN_INFO PFX "%s: using MSI-X  IRQs: sp %d  fp[%d] %d"
+              " ... fp[%d] %d\n",
+              bp->dev->name, bp->msix_table[0].vector,
+              0, bp->msix_table[offset].vector,
+              i - 1, bp->msix_table[offset + i - 1].vector);
+
+       return 0;
+}
+
+static int bnx2x_enable_msi(struct bnx2x *bp)
+{
+       int rc;
+
+       rc = pci_enable_msi(bp->pdev);
+       if (rc) {
+               DP(NETIF_MSG_IFUP, "MSI is not attainable\n");
+               return -1;
+       }
+       bp->flags |= USING_MSI_FLAG;
+
+       return 0;
+}
+#endif
+
+static int bnx2x_req_irq(struct bnx2x *bp)
+{
+       unsigned long flags;
+       int rc;
+
+       if (bp->flags & USING_MSI_FLAG)
+               flags = 0;
+       else
+               flags = IRQF_SHARED;
+
+       rc = request_irq(bp->pdev->irq, bnx2x_interrupt, flags,
+                        bp->dev->name, bp->dev);
+       if (!rc)
+               bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
+
+       return rc;
+}
+
+static void bnx2x_napi_enable(struct bnx2x *bp)
+{
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       int i;
+
+       for_each_rx_queue(bp, i)
+               napi_enable(&bnx2x_fp(bp, i, napi));
+#else
+       netif_poll_enable(bp->dev);
+#endif
+}
+
+static void bnx2x_napi_disable(struct bnx2x *bp)
+{
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       int i;
+
+       for_each_rx_queue(bp, i)
+               napi_disable(&bnx2x_fp(bp, i, napi));
+#else
+       netif_poll_disable(bp->dev);
+#endif
+}
+
+static void bnx2x_netif_start(struct bnx2x *bp)
+{
+       int intr_sem;
+
+       intr_sem = atomic_dec_and_test(&bp->intr_sem);
+       smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
+
+       if (intr_sem) {
+               if (netif_running(bp->dev)) {
+                       bnx2x_napi_enable(bp);
+                       bnx2x_int_enable(bp);
+                       if (bp->state == BNX2X_STATE_OPEN)
+                               netif_tx_wake_all_queues(bp->dev);
+               }
+       }
+}
+
+static void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
+{
+       bnx2x_int_disable_sync(bp, disable_hw);
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       bnx2x_napi_disable(bp);
+#else
+       if (netif_running(bp->dev))
+               bnx2x_napi_disable(bp);
+#endif
+       netif_tx_disable(bp->dev);
+       bp->dev->trans_start = jiffies; /* prevent tx timeout */
+}
+
+/*
+ * Init service functions
+ */
+
+static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
+{
+       struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
+       int port = BP_PORT(bp);
+
+       /* CAM allocation
+        * unicasts 0-31:port0 32-63:port1
+        * multicast 64-127:port0 128-191:port1
+        */
+       config->hdr.length = 2;
+       config->hdr.offset = port ? 32 : 0;
+       config->hdr.client_id = bp->fp->cl_id;
+       config->hdr.reserved1 = 0;
+
+       /* primary MAC */
+       config->config_table[0].cam_entry.msb_mac_addr =
+                                       swab16(*(u16 *)&bp->dev->dev_addr[0]);
+       config->config_table[0].cam_entry.middle_mac_addr =
+                                       swab16(*(u16 *)&bp->dev->dev_addr[2]);
+       config->config_table[0].cam_entry.lsb_mac_addr =
+                                       swab16(*(u16 *)&bp->dev->dev_addr[4]);
+       config->config_table[0].cam_entry.flags = cpu_to_le16(port);
+       if (set)
+               config->config_table[0].target_table_entry.flags = 0;
+       else
+               CAM_INVALIDATE(config->config_table[0]);
+       config->config_table[0].target_table_entry.clients_bit_vector =
+                                               cpu_to_le32(1 << BP_L_ID(bp));
+       config->config_table[0].target_table_entry.vlan_id = 0;
+
+       DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
+          (set ? "setting" : "clearing"),
+          config->config_table[0].cam_entry.msb_mac_addr,
+          config->config_table[0].cam_entry.middle_mac_addr,
+          config->config_table[0].cam_entry.lsb_mac_addr);
+
+       /* broadcast */
+       config->config_table[1].cam_entry.msb_mac_addr = cpu_to_le16(0xffff);
+       config->config_table[1].cam_entry.middle_mac_addr = cpu_to_le16(0xffff);
+       config->config_table[1].cam_entry.lsb_mac_addr = cpu_to_le16(0xffff);
+       config->config_table[1].cam_entry.flags = cpu_to_le16(port);
+       if (set)
+               config->config_table[1].target_table_entry.flags =
+                               TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
+       else
+               CAM_INVALIDATE(config->config_table[1]);
+       config->config_table[1].target_table_entry.clients_bit_vector =
+                                               cpu_to_le32(1 << BP_L_ID(bp));
+       config->config_table[1].target_table_entry.vlan_id = 0;
+
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+}
+
+static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
+{
+       struct mac_configuration_cmd_e1h *config =
+               (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
+
+       /* CAM allocation for E1H
+        * unicasts: by func number
+        * multicast: 20+FUNC*20, 20 each
+        */
+       config->hdr.length = 1;
+       config->hdr.offset = BP_FUNC(bp);
+       config->hdr.client_id = bp->fp->cl_id;
+       config->hdr.reserved1 = 0;
+
+       /* primary MAC */
+       config->config_table[0].msb_mac_addr =
+                                       swab16(*(u16 *)&bp->dev->dev_addr[0]);
+       config->config_table[0].middle_mac_addr =
+                                       swab16(*(u16 *)&bp->dev->dev_addr[2]);
+       config->config_table[0].lsb_mac_addr =
+                                       swab16(*(u16 *)&bp->dev->dev_addr[4]);
+       config->config_table[0].clients_bit_vector =
+                                       cpu_to_le32(1 << BP_L_ID(bp));
+       config->config_table[0].vlan_id = 0;
+       config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
+       if (set)
+               config->config_table[0].flags = BP_PORT(bp);
+       else
+               config->config_table[0].flags =
+                               MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
+
+       DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)  E1HOV %d  CLID %d\n",
+          (set ? "setting" : "clearing"),
+          config->config_table[0].msb_mac_addr,
+          config->config_table[0].middle_mac_addr,
+          config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
+
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+}
+
+static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
+                            int *state_p, int poll)
+{
+       /* can take a while if any port is running */
+       int cnt = 5000;
+
+       DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
+          poll ? "polling" : "waiting", state, idx);
+
+       might_sleep();
+       while (cnt--) {
+               if (poll) {
+                       bnx2x_rx_int(bp->fp, 10);
+                       /* if index is different from 0
+                        * the reply for some commands will
+                        * be on the non default queue
+                        */
+                       if (idx)
+                               bnx2x_rx_int(&bp->fp[idx], 10);
+               }
+
+               mb(); /* state is changed by bnx2x_sp_event() */
+               if (*state_p == state) {
+#ifdef BNX2X_STOP_ON_ERROR
+                       DP(NETIF_MSG_IFUP, "exit  (cnt %d)\n", 5000 - cnt);
+#endif
+                       return 0;
+               }
+
+               msleep(1);
+
+               if (bp->panic)
+                       return -EIO;
+       }
+
+       /* timeout! */
+       BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
+                 poll ? "polling" : "waiting", state, idx);
+#ifdef BNX2X_STOP_ON_ERROR
+       bnx2x_panic();
+#endif
+
+       return -EBUSY;
+}
+
+static int bnx2x_setup_leading(struct bnx2x *bp)
+{
+       int rc;
+
+       /* reset IGU state */
+       bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+       /* SETUP ramrod */
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
+
+       /* Wait for completion */
+       rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
+
+       return rc;
+}
+
+static int bnx2x_setup_multi(struct bnx2x *bp, int index)
+{
+       struct bnx2x_fastpath *fp = &bp->fp[index];
+
+       /* reset IGU state */
+       bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+       /* SETUP ramrod */
+       fp->state = BNX2X_FP_STATE_OPENING;
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0,
+                     fp->cl_id, 0);
+
+       /* Wait for completion */
+       return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
+                                &(fp->state), 0);
+}
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+static int bnx2x_poll(struct napi_struct *napi, int budget);
+#else
+static int bnx2x_poll(struct net_device *dev, int *budget);
+#endif
+
+static void bnx2x_set_int_mode_msix(struct bnx2x *bp, int *num_rx_queues_out,
+                                   int *num_tx_queues_out)
+{
+       int _num_rx_queues = 0, _num_tx_queues = 0;
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       int i;
+#endif
+
+       switch (bp->multi_mode) {
+       case ETH_RSS_MODE_DISABLED:
+               _num_rx_queues = 1;
+               _num_tx_queues = 1;
+               break;
+
+       case ETH_RSS_MODE_REGULAR:
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+               if (num_rx_queues)
+                       _num_rx_queues = min_t(u32, num_rx_queues,
+                                              BNX2X_MAX_QUEUES(bp));
+               else
+                       _num_rx_queues = min_t(u32, num_online_cpus(),
+                                              BNX2X_MAX_QUEUES(bp));
+#else
+               _num_rx_queues = 1;
+#endif
+
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+               if (num_tx_queues)
+                       _num_tx_queues = min_t(u32, num_tx_queues,
+                                              BNX2X_MAX_QUEUES(bp));
+               else
+                       _num_tx_queues = min_t(u32, num_online_cpus(),
+                                              BNX2X_MAX_QUEUES(bp));
+
+               /* There must be not more Tx queues than Rx queues */
+               if (_num_tx_queues > _num_rx_queues) {
+                       BNX2X_ERR("number of tx queues (%d) > "
+                                 "number of rx queues (%d)"
+                                 "  defaulting to %d\n",
+                                 _num_tx_queues, _num_rx_queues,
+                                 _num_rx_queues);
+                       _num_tx_queues = _num_rx_queues;
+               }
+#else
+               _num_tx_queues = 1;
+#endif
+               break;
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       case ETH_RSS_MODE_VLAN_PRI:
+       case ETH_RSS_MODE_E1HOV_PRI:
+       case ETH_RSS_MODE_IP_DSCP:
+               _num_rx_queues = 0;
+               for (i = 0; i < BNX2X_MAX_COS; i++)
+                       _num_rx_queues += bp->qs_per_cos[i];
+               _num_tx_queues = _num_rx_queues;
+               break;
+#endif
+
+       default:
+               _num_rx_queues = 1;
+               _num_tx_queues = 1;
+               break;
+       }
+
+       *num_rx_queues_out = _num_rx_queues;
+       *num_tx_queues_out = _num_tx_queues;
+}
+
+static int bnx2x_set_int_mode(struct bnx2x *bp)
+{
+       int rc = 0;
+
+       switch (int_mode) {
+       case INT_MODE_INTx:
+       case INT_MODE_MSI:
+               bp->num_rx_queues = 1;
+               bp->num_tx_queues = 1;
+               DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
+               break;
+
+       case INT_MODE_MSIX:
+       default:
+               /* Set interrupt mode according to bp->multi_mode value */
+               bnx2x_set_int_mode_msix(bp, &bp->num_rx_queues, &bp->num_tx_queues);
+
+               DP(NETIF_MSG_IFUP, "set number of queues to: rx %d tx %d\n",
+                  bp->num_rx_queues, bp->num_tx_queues);
+
+               /* if we can't use MSI-X we only need one fp,
+                * so try to enable MSI-X with the requested number of fp's
+                * and fallback to MSI or legacy INTx with one fp
+                */
+               rc = bnx2x_enable_msix(bp);
+               if (rc) {
+                       /* failed to enable MSI-X */
+                       if (bp->multi_mode)
+                               BNX2X_ERR("Multi requested but failed to "
+                                         "enable MSI-X (rx %d tx %d), "
+                                         "set number of queues to 1\n",
+                                         bp->num_rx_queues, bp->num_tx_queues);
+                       bp->num_rx_queues = 1;
+                       bp->num_tx_queues = 1;
+               }
+               break;
+       }
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       bp->dev->real_num_tx_queues = bp->num_tx_queues;
+#endif
+       return rc;
+}
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+static int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
+static void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
+#endif
+
+/* must be called with rtnl_lock */
+static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
+{
+       u32 load_code;
+       int i, rc;
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return -EPERM;
+#endif
+
+       bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
+
+       rc = bnx2x_set_int_mode(bp);
+
+       if (bnx2x_alloc_mem(bp))
+               return -ENOMEM;
+
+       for_each_rx_queue(bp, i)
+               bnx2x_fp(bp, i, disable_tpa) =
+                                       ((bp->flags & TPA_ENABLE_FLAG) == 0);
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       for_each_rx_queue(bp, i)
+               netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
+                              bnx2x_poll, 128);
+#endif
+
+       bnx2x_napi_enable(bp);
+
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+       if (bp->flags & USING_MSIX_FLAG) {
+               rc = bnx2x_req_msix_irqs(bp);
+               if (rc) {
+                       pci_disable_msix(bp->pdev);
+                       goto load_error1;
+               }
+       } else {
+               /* Fall to INTx if failed to enable MSI-X due to lack of
+                  memory (in bnx2x_set_int_mode()) */
+               if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx))
+                       bnx2x_enable_msi(bp);
+#else
+       {
+#endif
+               bnx2x_ack_int(bp);
+               rc = bnx2x_req_irq(bp);
+               if (rc) {
+                       BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+                       if (bp->flags & USING_MSI_FLAG)
+                               pci_disable_msi(bp->pdev);
+#endif
+                       goto load_error1;
+               }
+               if (bp->flags & USING_MSI_FLAG) {
+                       bp->dev->irq = bp->pdev->irq;
+                       printk(KERN_INFO PFX "%s: using MSI  IRQ %d\n",
+                              bp->dev->name, bp->pdev->irq);
+               }
+       }
+
+       /* Send LOAD_REQUEST command to MCP
+          Returns the type of LOAD command:
+          if it is the first port to be initialized
+          common blocks should be initialized, otherwise - not
+       */
+       if (!BP_NOMCP(bp)) {
+               load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
+               if (!load_code) {
+                       BNX2X_ERR("MCP response failure, aborting\n");
+                       rc = -EBUSY;
+                       goto load_error2;
+               }
+               if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) {
+                       rc = -EBUSY; /* other port in diagnostic mode */
+                       goto load_error2;
+               }
+
+       } else {
+               int port = BP_PORT(bp);
+
+               DP(NETIF_MSG_IFUP, "NO MCP - load counts      %d, %d, %d\n",
+                  load_count[0], load_count[1], load_count[2]);
+               load_count[0]++;
+               load_count[1 + port]++;
+               DP(NETIF_MSG_IFUP, "NO MCP - new load counts  %d, %d, %d\n",
+                  load_count[0], load_count[1], load_count[2]);
+               if (load_count[0] == 1)
+                       load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
+               else if (load_count[1 + port] == 1)
+                       load_code = FW_MSG_CODE_DRV_LOAD_PORT;
+               else
+                       load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
+       }
+
+       if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
+           (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
+               bp->port.pmf = 1;
+       else
+               bp->port.pmf = 0;
+       DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
+
+       /* Initialize HW */
+       rc = bnx2x_init_hw(bp, load_code);
+       if (rc) {
+               BNX2X_ERR("HW init failed, aborting\n");
+               goto load_error2;
+       }
+
+       /* Setup NIC internals and enable interrupts */
+       bnx2x_nic_init(bp, load_code);
+
+       if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
+           (bp->common.shmem2_base))
+               SHMEM2_WR(bp, dcc_support,
+                         (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
+                          SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
+
+       /* Send LOAD_DONE command to MCP */
+       if (!BP_NOMCP(bp)) {
+               load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
+               if (!load_code) {
+                       BNX2X_ERR("MCP response failure, aborting\n");
+                       rc = -EBUSY;
+                       goto load_error3;
+               }
+       }
+
+       bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
+
+       rc = bnx2x_setup_leading(bp);
+       if (rc) {
+               BNX2X_ERR("Setup leading failed!\n");
+#ifndef BNX2X_STOP_ON_ERROR
+               goto load_error3;
+#else
+               bp->panic = 1;
+               return -EBUSY;
+#endif
+       }
+
+       if (CHIP_IS_E1H(bp))
+               if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
+                       DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
+                       bp->state = BNX2X_STATE_DISABLED;
+               }
+
+       if (bp->state == BNX2X_STATE_OPEN) {
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+               /* Enable Timer scan */
+               REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + BP_PORT(bp)*4, 1);
+#endif
+               for_each_nondefault_queue(bp, i) {
+                       rc = bnx2x_setup_multi(bp, i);
+                       if (rc)
+#ifdef BCM_CNIC
+                               goto load_error4;
+#else /* BNX2X_UPSTREAM */
+                               goto load_error3;
+#endif
+               }
+
+               if (CHIP_IS_E1(bp))
+                       bnx2x_set_mac_addr_e1(bp, 1);
+               else
+                       bnx2x_set_mac_addr_e1h(bp, 1);
+       }
+
+       if (bp->port.pmf)
+               bnx2x_initial_phy_init(bp, load_mode);
+
+       /* Start fast path */
+       switch (load_mode) {
+       case LOAD_NORMAL:
+               if (bp->state == BNX2X_STATE_OPEN) {
+                       /* Tx queue should be only reenabled */
+                       netif_tx_wake_all_queues(bp->dev);
+               }
+               /* Initialize the receive filter. */
+               bnx2x_set_rx_mode(bp->dev);
+               break;
+
+       case LOAD_OPEN:
+               netif_tx_start_all_queues(bp->dev);
+               if (bp->state != BNX2X_STATE_OPEN)
+                       netif_tx_disable(bp->dev);
+               /* Initialize the receive filter. */
+               bnx2x_set_rx_mode(bp->dev);
+               break;
+
+       case LOAD_DIAG:
+               /* Initialize the receive filter. */
+               bnx2x_set_rx_mode(bp->dev);
+               bp->state = BNX2X_STATE_DIAG;
+               break;
+
+       default:
+               break;
+       }
+
+       if (!bp->port.pmf)
+               bnx2x__link_status_update(bp);
+
+       /* start the timer */
+       mod_timer(&bp->timer, jiffies + bp->current_interval);
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+       for_each_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               fp->netq_flags &= ~(BNX2X_NETQ_RX_QUEUE_ALLOCATED |
+                                   BNX2X_NETQ_TX_QUEUE_ALLOCATED);
+       }
+       bp->n_rx_queues_allocated = 0;
+       bp->n_tx_queues_allocated = 0;
+       if (bp->netq_enabled) {
+               /* workaround for packets duplicated issue when NetQ enabled */
+               bp->rx_mode = BNX2X_RX_MODE_NORMAL;
+               bnx2x_set_storm_rx_mode(bp);
+       }
+#endif
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       bnx2x_setup_cnic_irq_info(bp);
+       if (bp->state == BNX2X_STATE_OPEN)
+               bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
+#endif
+       return 0;
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+load_error4:
+       /* Disable Timer scan */
+       REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + BP_PORT(bp)*4, 0);
+#endif
+load_error3:
+       bnx2x_int_disable_sync(bp, 1);
+       if (!BP_NOMCP(bp)) {
+               bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
+               bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
+       }
+       bp->port.pmf = 0;
+       /* Free SKBs, SGEs, TPA pool and driver internals */
+       bnx2x_free_skbs(bp);
+       for_each_rx_queue(bp, i)
+               bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
+load_error2:
+       /* Release IRQs */
+       bnx2x_free_irq(bp);
+load_error1:
+       bnx2x_napi_disable(bp);
+#if defined(BNX2X_NEW_NAPI) && (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+       for_each_rx_queue(bp, i)
+               netif_napi_del(&bnx2x_fp(bp, i, napi));
+#endif
+       bnx2x_free_mem(bp);
+
+       return rc;
+}
+
+static int bnx2x_stop_multi(struct bnx2x *bp, int index)
+{
+       struct bnx2x_fastpath *fp = &bp->fp[index];
+       int rc;
+
+       /* halt the connection */
+       fp->state = BNX2X_FP_STATE_HALTING;
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0);
+
+       /* Wait for completion */
+       rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
+                              &(fp->state), 1);
+       if (rc) /* timeout */
+               return rc;
+
+       /* delete cfc entry */
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
+
+       /* Wait for completion */
+       rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
+                              &(fp->state), 1);
+       return rc;
+}
+
+static int bnx2x_stop_leading(struct bnx2x *bp)
+{
+       __le16 dsb_sp_prod_idx;
+       /* if the other port is handling traffic,
+          this can take a lot of time */
+       int cnt = 500;
+       int rc;
+
+       might_sleep();
+
+       /* Send HALT ramrod */
+       bp->fp[0].state = BNX2X_FP_STATE_HALTING;
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0);
+
+       /* Wait for completion */
+       rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
+                              &(bp->fp[0].state), 1);
+       if (rc) /* timeout */
+               return rc;
+
+       dsb_sp_prod_idx = *bp->dsb_sp_prod;
+
+       /* Send PORT_DELETE ramrod */
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
+
+       /* Wait for completion to arrive on default status block
+          we are going to reset the chip anyway
+          so there is not much to do if this times out
+        */
+       while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
+               if (!cnt) {
+                       DP(NETIF_MSG_IFDOWN, "timeout waiting for port del  "
+                          "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
+                          *bp->dsb_sp_prod, dsb_sp_prod_idx);
+#ifdef BNX2X_STOP_ON_ERROR
+                       bnx2x_panic();
+#endif
+                       rc = -EBUSY;
+                       break;
+               }
+               cnt--;
+               msleep(1);
+               rmb(); /* Refresh the dsb_sp_prod */
+       }
+       bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
+       bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
+
+       return rc;
+}
+
+static void bnx2x_reset_func(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int func = BP_FUNC(bp);
+       int base, i;
+
+       /* Configure IGU */
+       REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
+       REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       /* Disable Timer scan */
+       REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
+       /*
+        * Wait for at least 10ms and up to 2 second for the timers scan to
+        * complete
+        */
+       for (i = 0; i < 200; i++) {
+               msleep(10);
+               if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
+                       break;
+       }
+#endif
+       /* Clear ILT */
+       base = FUNC_ILT_BASE(func);
+       for (i = base; i < base + ILT_PER_FUNC; i++)
+               bnx2x_ilt_wr(bp, i, 0);
+}
+
+static void bnx2x_reset_port(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       u32 val;
+
+       REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
+
+       /* Do not rcv packets to BRB */
+       REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
+       /* Do not direct rcv packets that are not for MCP to the BRB */
+       REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
+                          NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
+
+       /* Configure AEU */
+       REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
+
+       msleep(100);
+       /* Check for BRB port occupancy */
+       val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
+       if (val)
+               DP(NETIF_MSG_IFDOWN,
+                  "BRB1 is not empty  %d blocks are occupied\n", val);
+
+       /* TODO: Close Doorbell port? */
+}
+
+static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
+{
+       DP(BNX2X_MSG_MCP, "function %d  reset_code %x\n",
+          BP_FUNC(bp), reset_code);
+
+       switch (reset_code) {
+       case FW_MSG_CODE_DRV_UNLOAD_COMMON:
+               bnx2x_reset_port(bp);
+               bnx2x_reset_func(bp);
+               bnx2x_reset_common(bp);
+               break;
+
+       case FW_MSG_CODE_DRV_UNLOAD_PORT:
+               bnx2x_reset_port(bp);
+               bnx2x_reset_func(bp);
+               break;
+
+       case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
+               bnx2x_reset_func(bp);
+               break;
+
+       default:
+               BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
+               break;
+       }
+}
+
+/* must be called with rtnl_lock */
+static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
+{
+       int port = BP_PORT(bp);
+       u32 reset_code = 0;
+       int i, cnt, rc;
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+       bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
+#endif
+       bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
+
+       /* Set "drop all" */
+       bp->rx_mode = BNX2X_RX_MODE_NONE;
+       bnx2x_set_storm_rx_mode(bp);
+
+       /* Disable HW interrupts, NAPI and Tx */
+       bnx2x_netif_stop(bp, 1);
+
+       del_timer_sync(&bp->timer);
+       SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
+                (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
+       bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+
+       /* Release IRQs */
+       bnx2x_free_irq(bp);
+
+       /* Wait until tx fastpath tasks complete */
+       for_each_tx_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               cnt = 1000;
+               while (bnx2x_has_tx_work_unload(fp)) {
+
+                       bnx2x_tx_int(fp);
+                       if (!cnt) {
+                               BNX2X_ERR("timeout waiting for queue[%d]\n",
+                                         i);
+#ifdef BNX2X_STOP_ON_ERROR
+                               bnx2x_panic();
+                               return -EBUSY;
+#else
+                               break;
+#endif
+                       }
+                       cnt--;
+                       msleep(1);
+               }
+       }
+       /* Give HW time to discard old tx messages */
+       msleep(1);
+
+       if (CHIP_IS_E1(bp)) {
+               struct mac_configuration_cmd *config =
+                                               bnx2x_sp(bp, mcast_config);
+
+               bnx2x_set_mac_addr_e1(bp, 0);
+
+               for (i = 0; i < config->hdr.length; i++)
+                       CAM_INVALIDATE(config->config_table[i]);
+
+               config->hdr.length = i;
+               if (CHIP_REV_IS_SLOW(bp))
+                       config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
+               else
+                       config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
+               config->hdr.client_id = bp->fp->cl_id;
+               config->hdr.reserved1 = 0;
+
+               bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                             U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
+                             U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
+
+       } else { /* E1H */
+               REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
+
+               bnx2x_set_mac_addr_e1h(bp, 0);
+
+               for (i = 0; i < MC_HASH_SIZE; i++)
+                       REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
+
+               REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
+       }
+
+       if (unload_mode == UNLOAD_NORMAL)
+               reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+
+       else if (bp->flags & NO_WOL_FLAG)
+               reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
+
+       else if (bp->wol) {
+               u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+               u8 *mac_addr = bp->dev->dev_addr;
+               u32 val;
+               /* The mac address is written to entries 1-4 to
+                  preserve entry 0 which is used by the PMF */
+               u8 entry = (BP_E1HVN(bp) + 1)*8;
+
+               val = (mac_addr[0] << 8) | mac_addr[1];
+               EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
+
+               val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
+                     (mac_addr[4] << 8) | mac_addr[5];
+               EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
+
+               reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
+
+       } else
+               reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+
+       /* Close multi and leading connections
+          Completions for ramrods are collected in a synchronous way */
+       for_each_nondefault_queue(bp, i)
+               if (bnx2x_stop_multi(bp, i))
+                       goto unload_error;
+
+       rc = bnx2x_stop_leading(bp);
+       if (rc) {
+               BNX2X_ERR("Stop leading failed!\n");
+#ifdef BNX2X_STOP_ON_ERROR
+               return -EBUSY;
+#else
+               goto unload_error;
+#endif
+       }
+
+unload_error:
+       if (!BP_NOMCP(bp))
+               reset_code = bnx2x_fw_command(bp, reset_code);
+       else {
+               DP(NETIF_MSG_IFDOWN, "NO MCP - load counts      %d, %d, %d\n",
+                  load_count[0], load_count[1], load_count[2]);
+               load_count[0]--;
+               load_count[1 + port]--;
+               DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts  %d, %d, %d\n",
+                  load_count[0], load_count[1], load_count[2]);
+               if (load_count[0] == 0)
+                       reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
+               else if (load_count[1 + port] == 0)
+                       reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
+               else
+                       reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
+       }
+
+       if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
+           (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
+               bnx2x__link_reset(bp);
+
+       /* Reset the chip */
+       bnx2x_reset_chip(bp, reset_code);
+
+       /* Report UNLOAD_DONE to MCP */
+       if (!BP_NOMCP(bp))
+               bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
+
+       bp->port.pmf = 0;
+
+       /* Free SKBs, SGEs, TPA pool and driver internals */
+       bnx2x_free_skbs(bp);
+       for_each_rx_queue(bp, i)
+               bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
+#if defined(BNX2X_NEW_NAPI) && (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+       for_each_rx_queue(bp, i)
+               netif_napi_del(&bnx2x_fp(bp, i, napi));
+#endif
+       bnx2x_free_mem(bp);
+
+       bp->state = BNX2X_STATE_CLOSED;
+
+       netif_carrier_off(bp->dev);
+
+       return 0;
+}
+
+#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) || (VMWARE_ESX_DDK_VERSION >= 40000) /* BNX2X_UPSTREAM */
+static void bnx2x_reset_task(struct work_struct *work)
+{
+       struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
+#else
+static void bnx2x_reset_task(void *data)
+{
+       struct bnx2x *bp = (struct bnx2x *)data;
+#endif
+
+#ifdef BNX2X_STOP_ON_ERROR
+       BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
+                 " so reset not done to allow debug dump,\n"
+        KERN_ERR " you will need to reboot when done\n");
+       return;
+#endif
+
+       rtnl_lock();
+
+       if (!netif_running(bp->dev))
+               goto reset_task_exit;
+
+       bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+       bnx2x_nic_load(bp, LOAD_NORMAL);
+
+reset_task_exit:
+       rtnl_unlock();
+}
+
+/* end of nic load/unload */
+
+/* ethtool_ops */
+
+/*
+ * Init service functions
+ */
+
+static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func)
+{
+       switch (func) {
+       case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0;
+       case 1: return PXP2_REG_PGL_PRETEND_FUNC_F1;
+       case 2: return PXP2_REG_PGL_PRETEND_FUNC_F2;
+       case 3: return PXP2_REG_PGL_PRETEND_FUNC_F3;
+       case 4: return PXP2_REG_PGL_PRETEND_FUNC_F4;
+       case 5: return PXP2_REG_PGL_PRETEND_FUNC_F5;
+       case 6: return PXP2_REG_PGL_PRETEND_FUNC_F6;
+       case 7: return PXP2_REG_PGL_PRETEND_FUNC_F7;
+       default:
+               BNX2X_ERR("Unsupported function index: %d\n", func);
+               return (u32)(-1);
+       }
+}
+
+static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func)
+{
+       u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val;
+
+       /* Flush all outstanding writes */
+       mmiowb();
+
+       /* Pretend to be function 0 */
+       REG_WR(bp, reg, 0);
+       /* Flush the GRC transaction (in the chip) */
+       new_val = REG_RD(bp, reg);
+       if (new_val != 0) {
+               BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n",
+                         new_val);
+               BUG();
+       }
+
+       /* From now we are in the "like-E1" mode */
+       bnx2x_int_disable(bp);
+
+       /* Flush all outstanding writes */
+       mmiowb();
+
+       /* Restore the original funtion settings */
+       REG_WR(bp, reg, orig_func);
+       new_val = REG_RD(bp, reg);
+       if (new_val != orig_func) {
+               BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n",
+                         orig_func, new_val);
+               BUG();
+       }
+}
+
+static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func)
+{
+       if (CHIP_IS_E1H(bp))
+               bnx2x_undi_int_disable_e1h(bp, func);
+       else
+               bnx2x_int_disable(bp);
+}
+
+static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
+{
+       u32 val;
+
+       /* Check if there is any driver already loaded */
+       val = REG_RD(bp, MISC_REG_UNPREPARED);
+       if (val == 0x1) {
+               /* Check if it is the UNDI driver
+                * UNDI driver initializes CID offset for normal bell to 0x7
+                */
+               bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
+               val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
+               if (val == 0x7) {
+                       u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+                       /* save our func */
+                       int func = BP_FUNC(bp);
+                       u32 swap_en;
+                       u32 swap_val;
+
+                       /* clear the UNDI indication */
+                       REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
+
+                       BNX2X_DEV_INFO("UNDI is active! reset device\n");
+
+                       /* try unload UNDI on port 0 */
+                       bp->func = 0;
+                       bp->fw_seq =
+                              (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
+                               DRV_MSG_SEQ_NUMBER_MASK);
+                       reset_code = bnx2x_fw_command(bp, reset_code);
+
+                       /* if UNDI is loaded on the other port */
+                       if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
+
+                               /* send "DONE" for previous unload */
+                               bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
+
+                               /* unload UNDI on port 1 */
+                               bp->func = 1;
+                               bp->fw_seq =
+                              (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
+                                       DRV_MSG_SEQ_NUMBER_MASK);
+                               reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+
+                               bnx2x_fw_command(bp, reset_code);
+                       }
+
+                       /* now it's safe to release the lock */
+                       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
+
+                       bnx2x_undi_int_disable(bp, func);
+
+                       /* close input traffic and wait for it */
+                       /* Do not rcv packets to BRB */
+                       REG_WR(bp,
+                             (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
+                                            NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
+                       /* Do not direct rcv packets that are not for MCP to
+                        * the BRB */
+                       REG_WR(bp,
+                              (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
+                                             NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
+                       /* clear AEU */
+                       REG_WR(bp,
+                            (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+                                           MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
+                       msleep(10);
+
+                       /* save NIG port swap info */
+                       swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
+                       swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
+                       /* reset device */
+                       REG_WR(bp,
+                              GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
+                              0xd3ffffff);
+                       REG_WR(bp,
+                              GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+                              0x1403);
+                       /* take the NIG out of reset and restore swap values */
+                       REG_WR(bp,
+                              GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
+                              MISC_REGISTERS_RESET_REG_1_RST_NIG);
+                       REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
+                       REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
+
+                       /* send unload done to the MCP */
+                       bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
+
+                       /* restore our func and fw_seq */
+                       bp->func = func;
+                       bp->fw_seq =
+                              (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
+                               DRV_MSG_SEQ_NUMBER_MASK);
+
+               } else
+                       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
+       }
+}
+
+static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
+{
+       u32 val, val2, val3, val4, id;
+       u16 pmc;
+
+       /* Get the chip revision id and number. */
+       /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+       val = REG_RD(bp, MISC_REG_CHIP_NUM);
+       id = ((val & 0xffff) << 16);
+       val = REG_RD(bp, MISC_REG_CHIP_REV);
+       id |= ((val & 0xf) << 12);
+       val = REG_RD(bp, MISC_REG_CHIP_METAL);
+       id |= ((val & 0xff) << 4);
+       val = REG_RD(bp, MISC_REG_BOND_ID);
+       id |= (val & 0xf);
+       bp->common.chip_id = id;
+       bp->link_params.chip_id = bp->common.chip_id;
+       BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
+
+       val = (REG_RD(bp, 0x2874) & 0x55);
+       if ((bp->common.chip_id & 0x1) ||
+           (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
+               bp->flags |= ONE_PORT_FLAG;
+               BNX2X_DEV_INFO("single port device\n");
+       }
+
+       val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
+       bp->common.flash_size = (NVRAM_1MB_SIZE <<
+                                (val & MCPR_NVM_CFG4_FLASH_SIZE));
+       BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
+                      bp->common.flash_size, bp->common.flash_size);
+
+       bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
+       bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0);
+       bp->link_params.shmem_base = bp->common.shmem_base;
+       BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
+                      bp->common.shmem_base, bp->common.shmem2_base);
+
+       if (!bp->common.shmem_base ||
+           (bp->common.shmem_base < 0xA0000) ||
+           (bp->common.shmem_base >= 0xC0000)) {
+               BNX2X_DEV_INFO("MCP not active\n");
+               bp->flags |= NO_MCP_FLAG;
+               return;
+       }
+
+       val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
+       if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
+               != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
+               BNX2X_ERR("BAD MCP validity signature\n");
+
+       bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
+       BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
+
+       bp->link_params.hw_led_mode = ((bp->common.hw_config &
+                                       SHARED_HW_CFG_LED_MODE_MASK) >>
+                                      SHARED_HW_CFG_LED_MODE_SHIFT);
+
+       bp->link_params.feature_config_flags = 0;
+       val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
+       if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
+               bp->link_params.feature_config_flags |=
+                               FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
+       else
+               bp->link_params.feature_config_flags &=
+                               ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
+
+       val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
+       bp->common.bc_ver = val;
+       BNX2X_DEV_INFO("bc_ver %X\n", val);
+       if (val < BNX2X_BC_VER) {
+               /* for now only warn
+                * later we might need to enforce this */
+               BNX2X_ERR("This driver needs bc_ver %X but found %X,"
+                         " please upgrade BC\n", BNX2X_BC_VER, val);
+       }
+       bp->link_params.feature_config_flags |=
+               (val >= REQ_BC_VER_4_VRFY_OPT_MDL) ?
+               FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
+
+       if (BP_E1HVN(bp) == 0) {
+               pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
+               bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
+       } else {
+               /* no WOL capability for E1HVN != 0 */
+               bp->flags |= NO_WOL_FLAG;
+       }
+       BNX2X_DEV_INFO("%sWoL capable\n",
+                      (bp->flags & NO_WOL_FLAG) ? "not " : "");
+
+       val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
+       val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
+       val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
+       val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
+
+       printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
+              val, val2, val3, val4);
+}
+
+static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
+                                                   u32 switch_cfg)
+{
+       int port = BP_PORT(bp);
+       u32 ext_phy_type;
+
+       switch (switch_cfg) {
+       case SWITCH_CFG_1G:
+               BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
+
+               ext_phy_type =
+                       SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10baseT_Half |
+                                              SUPPORTED_10baseT_Full |
+                                              SUPPORTED_100baseT_Half |
+                                              SUPPORTED_100baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_2500baseX_Full |
+                                              SUPPORTED_TP |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10baseT_Half |
+                                              SUPPORTED_10baseT_Full |
+                                              SUPPORTED_100baseT_Half |
+                                              SUPPORTED_100baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_TP |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               default:
+                       BNX2X_ERR("NVRAM config error. "
+                                 "BAD SerDes ext_phy_config 0x%x\n",
+                                 bp->link_params.ext_phy_config);
+                       return;
+               }
+
+               bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
+                                          port*0x10);
+               BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
+               break;
+
+       case SWITCH_CFG_10G:
+               BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
+
+               ext_phy_type =
+                       XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10baseT_Half |
+                                              SUPPORTED_10baseT_Full |
+                                              SUPPORTED_100baseT_Half |
+                                              SUPPORTED_100baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_2500baseX_Full |
+                                              SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_TP |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_2500baseX_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_FIBRE |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_TP |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+                       BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
+                                      ext_phy_type);
+
+                       bp->port.supported |= (SUPPORTED_10baseT_Half |
+                                              SUPPORTED_10baseT_Full |
+                                              SUPPORTED_100baseT_Half |
+                                              SUPPORTED_100baseT_Full |
+                                              SUPPORTED_1000baseT_Full |
+                                              SUPPORTED_10000baseT_Full |
+                                              SUPPORTED_TP |
+                                              SUPPORTED_Autoneg |
+                                              SUPPORTED_Pause |
+                                              SUPPORTED_Asym_Pause);
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+                       BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
+                                 bp->link_params.ext_phy_config);
+                       break;
+
+               default:
+                       BNX2X_ERR("NVRAM config error. "
+                                 "BAD XGXS ext_phy_config 0x%x\n",
+                                 bp->link_params.ext_phy_config);
+                       return;
+               }
+
+               bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
+                                          port*0x18);
+               BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
+
+               break;
+
+       default:
+               BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
+                         bp->port.link_config);
+               return;
+       }
+       bp->link_params.phy_addr = bp->port.phy_addr;
+
+       /* mask what we support according to speed_cap_mask */
+       if (!(bp->link_params.speed_cap_mask &
+                               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
+               bp->port.supported &= ~SUPPORTED_10baseT_Half;
+
+       if (!(bp->link_params.speed_cap_mask &
+                               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
+               bp->port.supported &= ~SUPPORTED_10baseT_Full;
+
+       if (!(bp->link_params.speed_cap_mask &
+                               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
+               bp->port.supported &= ~SUPPORTED_100baseT_Half;
+
+       if (!(bp->link_params.speed_cap_mask &
+                               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
+               bp->port.supported &= ~SUPPORTED_100baseT_Full;
+
+       if (!(bp->link_params.speed_cap_mask &
+                                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
+               bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
+                                       SUPPORTED_1000baseT_Full);
+
+       if (!(bp->link_params.speed_cap_mask &
+                                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
+               bp->port.supported &= ~SUPPORTED_2500baseX_Full;
+
+       if (!(bp->link_params.speed_cap_mask &
+                                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
+               bp->port.supported &= ~SUPPORTED_10000baseT_Full;
+
+       BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
+}
+
+static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
+{
+       bp->link_params.req_duplex = DUPLEX_FULL;
+
+       switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
+       case PORT_FEATURE_LINK_SPEED_AUTO:
+               if (bp->port.supported & SUPPORTED_Autoneg) {
+                       bp->link_params.req_line_speed = SPEED_AUTO_NEG;
+                       bp->port.advertising = bp->port.supported;
+               } else {
+                       u32 ext_phy_type =
+                           XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+
+                       if ((ext_phy_type ==
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
+                           (ext_phy_type ==
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
+                               /* force 10G, no AN */
+                               bp->link_params.req_line_speed = SPEED_10000;
+                               bp->port.advertising =
+                                               (ADVERTISED_10000baseT_Full |
+                                                ADVERTISED_FIBRE);
+                               break;
+                       }
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  Autoneg not supported\n",
+                                 bp->port.link_config);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_10M_FULL:
+               if (bp->port.supported & SUPPORTED_10baseT_Full) {
+                       bp->link_params.req_line_speed = SPEED_10;
+                       bp->port.advertising = (ADVERTISED_10baseT_Full |
+                                               ADVERTISED_TP);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_10M_HALF:
+               if (bp->port.supported & SUPPORTED_10baseT_Half) {
+                       bp->link_params.req_line_speed = SPEED_10;
+                       bp->link_params.req_duplex = DUPLEX_HALF;
+                       bp->port.advertising = (ADVERTISED_10baseT_Half |
+                                               ADVERTISED_TP);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_100M_FULL:
+               if (bp->port.supported & SUPPORTED_100baseT_Full) {
+                       bp->link_params.req_line_speed = SPEED_100;
+                       bp->port.advertising = (ADVERTISED_100baseT_Full |
+                                               ADVERTISED_TP);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_100M_HALF:
+               if (bp->port.supported & SUPPORTED_100baseT_Half) {
+                       bp->link_params.req_line_speed = SPEED_100;
+                       bp->link_params.req_duplex = DUPLEX_HALF;
+                       bp->port.advertising = (ADVERTISED_100baseT_Half |
+                                               ADVERTISED_TP);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_1G:
+               if (bp->port.supported & SUPPORTED_1000baseT_Full) {
+                       bp->link_params.req_line_speed = SPEED_1000;
+                       bp->port.advertising = (ADVERTISED_1000baseT_Full |
+                                               ADVERTISED_TP);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_2_5G:
+               if (bp->port.supported & SUPPORTED_2500baseX_Full) {
+                       bp->link_params.req_line_speed = SPEED_2500;
+                       bp->port.advertising = (ADVERTISED_2500baseX_Full |
+                                               ADVERTISED_TP);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       case PORT_FEATURE_LINK_SPEED_10G_CX4:
+       case PORT_FEATURE_LINK_SPEED_10G_KX4:
+       case PORT_FEATURE_LINK_SPEED_10G_KR:
+               if (bp->port.supported & SUPPORTED_10000baseT_Full) {
+                       bp->link_params.req_line_speed = SPEED_10000;
+                       bp->port.advertising = (ADVERTISED_10000baseT_Full |
+                                               ADVERTISED_FIBRE);
+               } else {
+                       BNX2X_ERR("NVRAM config error. "
+                                 "Invalid link_config 0x%x"
+                                 "  speed_cap_mask 0x%x\n",
+                                 bp->port.link_config,
+                                 bp->link_params.speed_cap_mask);
+                       return;
+               }
+               break;
+
+       default:
+               BNX2X_ERR("NVRAM config error. "
+                         "BAD link speed link_config 0x%x\n",
+                         bp->port.link_config);
+               bp->link_params.req_line_speed = SPEED_AUTO_NEG;
+               bp->port.advertising = bp->port.supported;
+               break;
+       }
+
+       bp->link_params.req_flow_ctrl = (bp->port.link_config &
+                                        PORT_FEATURE_FLOW_CONTROL_MASK);
+       if ((bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
+           !(bp->port.supported & SUPPORTED_Autoneg))
+               bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+
+       BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d  req_flow_ctrl 0x%x"
+                      "  advertising 0x%x\n",
+                      bp->link_params.req_line_speed,
+                      bp->link_params.req_duplex,
+                      bp->link_params.req_flow_ctrl, bp->port.advertising);
+}
+
+static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       u32 val, val2;
+       u32 config;
+       u16 i;
+       u32 ext_phy_type;
+
+       bp->link_params.bp = bp;
+       bp->link_params.port = port;
+
+       bp->link_params.lane_config =
+               SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
+       bp->link_params.ext_phy_config =
+               SHMEM_RD(bp,
+                        dev_info.port_hw_config[port].external_phy_config);
+       /* BCM8727_NOC => BCM8727 no over current */
+       if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
+           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
+               bp->link_params.ext_phy_config &=
+                       ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+               bp->link_params.ext_phy_config |=
+                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
+               bp->link_params.feature_config_flags |=
+                       FEATURE_CONFIG_BCM8727_NOC;
+       }
+
+       bp->link_params.speed_cap_mask =
+               SHMEM_RD(bp,
+                        dev_info.port_hw_config[port].speed_capability_mask);
+
+       bp->port.link_config =
+               SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
+
+       /* Get the 4 lanes xgxs config rx and tx */
+       for (i = 0; i < 2; i++) {
+               val = SHMEM_RD(bp,
+                          dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
+               bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
+               bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
+
+               val = SHMEM_RD(bp,
+                          dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
+               bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
+               bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
+       }
+
+       /* If the device is capable of WoL, set the default state according
+        * to the HW
+        */
+       config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
+       bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
+                  (config & PORT_FEATURE_WOL_ENABLED));
+
+       BNX2X_DEV_INFO("lane_config 0x%08x  ext_phy_config 0x%08x"
+                      "  speed_cap_mask 0x%08x  link_config 0x%08x\n",
+                      bp->link_params.lane_config,
+                      bp->link_params.ext_phy_config,
+                      bp->link_params.speed_cap_mask, bp->port.link_config);
+
+       bp->link_params.switch_cfg |= (bp->port.link_config &
+                                      PORT_FEATURE_CONNECTED_SWITCH_MASK);
+       bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
+
+       bnx2x_link_settings_requested(bp);
+
+       /*
+        * If connected directly, work with the internal PHY, otherwise, work
+        * with the external PHY
+        */
+       ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+       if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
+               bp->mdio.prtad = bp->link_params.phy_addr;
+
+       else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
+                (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
+               bp->mdio.prtad =
+                       XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
+       }
+
+       val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
+       val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
+       bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
+       bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
+       bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
+       bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
+       bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
+       bp->dev->dev_addr[5] = (u8)(val & 0xff);
+       memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
+#ifdef ETHTOOL_GPERMADDR /* BNX2X_UPSTREAM */
+       memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
+#endif
+}
+
+static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+       u32 val, val2;
+       int rc = 0;
+
+       bnx2x_get_common_hwinfo(bp);
+
+       bp->e1hov = 0;
+       bp->e1hmf = 0;
+       if (CHIP_IS_E1H(bp)) {
+               bp->mf_config =
+                       SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+
+               val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) &
+                      FUNC_MF_CFG_E1HOV_TAG_MASK);
+               if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
+                       bp->e1hmf = 1;
+               BNX2X_DEV_INFO("%s function mode\n",
+                              IS_E1HMF(bp) ? "multi" : "single");
+
+               if (IS_E1HMF(bp)) {
+                       val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].
+                                                               e1hov_tag) &
+                              FUNC_MF_CFG_E1HOV_TAG_MASK);
+                       if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
+                               bp->e1hov = val;
+                               BNX2X_DEV_INFO("E1HOV for func %d is %d "
+                                              "(0x%04x)\n",
+                                              func, bp->e1hov, bp->e1hov);
+                       } else {
+                               BNX2X_ERR("!!!  No valid E1HOV for func %d,"
+                                         "  aborting\n", func);
+                               rc = -EPERM;
+                       }
+               } else {
+                       if (BP_E1HVN(bp)) {
+                               BNX2X_ERR("!!!  VN %d in single function mode,"
+                                         "  aborting\n", BP_E1HVN(bp));
+                               rc = -EPERM;
+                       }
+               }
+       }
+
+       if (!BP_NOMCP(bp)) {
+               bnx2x_get_port_hwinfo(bp);
+
+               bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
+                             DRV_MSG_SEQ_NUMBER_MASK);
+               BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
+       }
+
+       if (IS_E1HMF(bp)) {
+               val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
+               val = SHMEM_RD(bp,  mf_cfg.func_mf_config[func].mac_lower);
+               if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
+                   (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
+                       bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
+                       bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
+                       bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
+                       bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
+                       bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
+                       bp->dev->dev_addr[5] = (u8)(val & 0xff);
+                       memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
+                              ETH_ALEN);
+#ifdef ETHTOOL_GPERMADDR /* BNX2X_UPSTREAM */
+                       memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
+                              ETH_ALEN);
+#endif
+               }
+
+               return rc;
+       }
+
+       if (BP_NOMCP(bp)) {
+               /* only supposed to happen on emulation/FPGA */
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+               BNX2X_ERR("warning random MAC workaround active\n");
+               random_ether_addr(bp->dev->dev_addr);
+#else
+               BNX2X_ERR("warning constant MAC workaround active\n");
+               bp->dev->dev_addr[0] = 0;
+               bp->dev->dev_addr[1] = 0x50;
+               bp->dev->dev_addr[2] = 0xc2;
+               bp->dev->dev_addr[3] = 0x2c;
+               bp->dev->dev_addr[4] = (func + 1) * 0x10;
+               bp->dev->dev_addr[5] = 0x00;
+               memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
+#endif
+#ifdef ETHTOOL_GPERMADDR /* BNX2X_UPSTREAM */
+               memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
+#endif
+       }
+
+       return rc;
+}
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+static u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
+
+static void __devinit bnx2x_init_safc(struct bnx2x *bp)
+{
+       int i, cos, max_cos, max_queues;
+
+       bp->flags &= ~SAFC_TX_FLAG;
+
+       for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
+               bp->pri_map[i] = 0;
+
+       max_cos = BNX2X_MAX_COS;
+       bp->cos_weight_sum = 0;
+       for (cos = 0; cos < BNX2X_MAX_COS; cos++) {
+               bp->qs_per_cos[cos] = 0;
+               bp->cos_min_rate[cos] = 0;
+       }
+
+       switch (bp->multi_mode) {
+       case ETH_RSS_MODE_DISABLED:
+               bp->qs_per_cos[0] = 1;
+               break;
+
+       case ETH_RSS_MODE_REGULAR:
+               bp->qs_per_cos[0] = min_t(u32, num_online_cpus(),
+                                         BNX2X_MAX_QUEUES(bp));
+               break;
+
+       case ETH_RSS_MODE_VLAN_PRI:
+       case ETH_RSS_MODE_E1HOV_PRI:
+               if (CHIP_IS_E1H(bp)) {
+                       bp->flags |= SAFC_TX_FLAG;
+                       max_cos = BNX2X_MAX_TX_COS;
+               }
+
+               /* fallthrough */
+
+       case ETH_RSS_MODE_IP_DSCP:
+               /* COS 0 must have at least 1 queue */
+               if (BNX2X_COS_QUEUES(0) == 0) {
+                       printk(KERN_ERR PFX
+                              "Illegal number of queues per COS 0  "
+                              "defaulting to 1\n");
+                       qs_per_cos |= 0x1;
+               }
+
+               for (i = 0; i < BNX2X_MAX_PRIORITY; i++) {
+                       cos = ((pri_map & (0xf << i*4)) >> i*4);
+                       if (cos < max_cos) {
+                               bp->pri_map[i] = cos;
+                               if (BNX2X_COS_QUEUES(cos) == 0) {
+                                       printk(KERN_ERR PFX
+                                              "Illegal number of queues per "
+                                              "COS %d  defaulting to 1\n",
+                                              cos);
+                                       qs_per_cos |= (0x1 << cos*8);
+                               }
+                       } else {
+                               printk(KERN_ERR PFX
+                                      "Illegal COS (%d) for priority %d  "
+                                      "defaulting to 0\n", cos, i);
+                               pri_map &= ~(0xf << i*4);
+                               bp->pri_map[i] = 0;
+                       }
+               }
+
+               max_queues = BNX2X_MAX_QUEUES(bp);
+               for (cos = 0; cos < BNX2X_MAX_COS; cos++) {
+                       i = BNX2X_COS_QUEUES(cos);
+                       if (i <= max_queues) {
+                               bp->qs_per_cos[cos] = i;
+                               max_queues -= i;
+                       } else {
+                               bp->qs_per_cos[cos] = max_queues;
+                               max_queues = 0;
+                       }
+                       if (bp->qs_per_cos[cos] == 0)
+                               for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
+                                       if (bp->pri_map[i] == cos) {
+                                               printk(KERN_ERR PFX
+                                                      "Illegal COS (%d) for "
+                                                      "priority %d  "
+                                                      "defaulting to 0\n",
+                                                      cos, i);
+                                               pri_map &= ~(0xf << i*4);
+                                               bp->pri_map[i] = 0;
+                                       }
+               }
+
+               bp->dev->select_queue = bnx2x_select_queue;
+
+               if (cos_min_rate == 0)
+                       break;
+
+               for (cos = 0; cos < BNX2X_MAX_COS; cos++) {
+                       i = BNX2X_COS_RATE(cos);
+                       if (i > 100) {
+                               printk(KERN_ERR PFX
+                                      "Illegal rate (%d) for COS %d  "
+                                      "defaulting to 100\n", i, cos);
+                               i = 100;
+                               cos_min_rate |= (i << cos*8);
+                       }
+                       i *= 100;
+                       if (bp->qs_per_cos[cos]) {
+                               if (i == 0) {
+                                       printk(KERN_ERR PFX
+                                              "Illegal rate for COS %d  "
+                                              "defaulting to 1\n", cos);
+                                       i = DEF_MIN_RATE;
+                                       cos_min_rate |= (i << cos*8);
+                               }
+                       } else {
+                               if (i) {
+                                       printk(KERN_ERR PFX
+                                              "Illegal rate (%d) for COS %d "
+                                              "with no queues  "
+                                              "defaulting to 0\n", i, cos);
+                                       i = 0;
+                                       cos_min_rate &= ~(0xff << cos*8);
+                               }
+                       }
+                       bp->cos_min_rate[cos] = i;
+                       bp->cos_weight_sum += i;
+               }
+               break;
+
+       default:
+               bp->multi_mode = ETH_RSS_MODE_DISABLED;
+               bp->qs_per_cos[0] = 1;
+               break;
+       }
+}
+#endif
+
+static int __devinit bnx2x_init_bp(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+       int timer_interval;
+       int rc;
+
+       /* Disable interrupt handling until HW is initialized */
+       atomic_set(&bp->intr_sem, 1);
+       smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
+
+       mutex_init(&bp->port.phy_mutex);
+
+#if defined(INIT_DELAYED_WORK_DEFERRABLE) || defined(INIT_WORK_NAR) || (VMWARE_ESX_DDK_VERSION >= 40000) /* BNX2X_UPSTREAM */
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
+#else
+       INIT_WORK(&bp->sp_task, bnx2x_sp_task);
+#endif
+       INIT_WORK(&bp->reset_task, bnx2x_reset_task);
+#else
+       INIT_WORK(&bp->sp_task, bnx2x_sp_task, bp);
+       INIT_WORK(&bp->reset_task, bnx2x_reset_task, bp);
+#endif
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       bp->sp_running = 0;
+#endif
+
+       rc = bnx2x_get_hwinfo(bp);
+
+       /* need to reset chip if undi was active */
+       if (!BP_NOMCP(bp))
+               bnx2x_undi_unload(bp);
+
+       if (CHIP_REV_IS_FPGA(bp))
+               printk(KERN_ERR PFX "FPGA detected\n");
+
+       if (BP_NOMCP(bp) && (func == 0))
+               printk(KERN_ERR PFX
+                      "MCP disabled, must load devices in order!\n");
+
+       /* Set multi queue mode and priority mapping */
+       if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
+           ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
+               printk(KERN_ERR PFX
+                     "Multi disabled since int_mode requested is not MSI-X\n");
+               multi_mode = ETH_RSS_MODE_DISABLED;
+       }
+       bp->multi_mode = multi_mode;
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+       bnx2x_init_safc(bp);
+#endif
+
+       /* Set TPA flags */
+       if (disable_tpa) {
+               bp->flags &= ~TPA_ENABLE_FLAG;
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+               bp->dev->features &= ~NETIF_F_LRO;
+#endif
+       } else {
+               bp->flags |= TPA_ENABLE_FLAG;
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+               bp->dev->features |= NETIF_F_LRO;
+#endif
+       }
+
+       if (CHIP_IS_E1(bp))
+               bp->dropless_fc = 0;
+       else
+               bp->dropless_fc = dropless_fc;
+
+       bp->mrrs = mrrs;
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       /* MCP workaround */
+       if (BP_NOMCP(bp)) {
+               /* [0x24c0]table size:
+                  PCI_REG_GRC_PTR(func)->pci_msix_control = 0x10; */
+               REG_WR(bp, 0x24c0, 0x10);
+               /* [0x24c4]table pointer:
+                  PCI_REG_GRC_PTR(func)->pci_msix_tbl_off_bir =
+                                               0x440000 + 0x2000*func; */
+               REG_WR(bp, 0x24c4, 0x440000 + 0x2000*func);
+               /* [0x24c8]PBA pointer:
+                  PCI_REG_GRC_PTR(func)->pci_msix_pba_off_bir =
+                                               0x441800 + 0x2000*func; */
+               REG_WR(bp, 0x24c8, 0x441800 + 0x2000*func);
+       }
+#endif
+       bp->tx_ring_size = MAX_TX_AVAIL;
+       bp->rx_ring_size = MAX_RX_AVAIL;
+
+       bp->rx_csum = 1;
+
+       bp->tx_ticks = 50;
+       bp->rx_ticks = 25;
+
+       timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
+       bp->current_interval = (poll ? poll : timer_interval);
+
+       init_timer(&bp->timer);
+       bp->timer.expires = jiffies + bp->current_interval;
+       bp->timer.data = (unsigned long) bp;
+       bp->timer.function = bnx2x_timer;
+
+       return rc;
+}
+
+/*
+ * ethtool service functions
+ */
+
+/* All ethtool functions called with rtnl_lock */
+
+static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       cmd->supported = bp->port.supported;
+       cmd->advertising = bp->port.advertising;
+
+       if (netif_carrier_ok(dev)) {
+               cmd->speed = bp->link_vars.line_speed;
+               cmd->duplex = bp->link_vars.duplex;
+       } else {
+               cmd->speed = bp->link_params.req_line_speed;
+               cmd->duplex = bp->link_params.req_duplex;
+       }
+       if (IS_E1HMF(bp)) {
+               u16 vn_max_rate;
+
+               vn_max_rate = ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
+                               FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+               if (vn_max_rate < cmd->speed)
+                       cmd->speed = vn_max_rate;
+       }
+
+       if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
+               u32 ext_phy_type =
+                       XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+
+               switch (ext_phy_type) {
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+                       cmd->port = PORT_FIBRE;
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+                       cmd->port = PORT_TP;
+                       break;
+
+               case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+                       BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
+                                 bp->link_params.ext_phy_config);
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+                          bp->link_params.ext_phy_config);
+                       break;
+               }
+       } else
+               cmd->port = PORT_TP;
+
+       cmd->phy_address = bp->mdio.prtad;
+       cmd->transceiver = XCVR_INTERNAL;
+
+       if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
+               cmd->autoneg = AUTONEG_ENABLE;
+       else
+               cmd->autoneg = AUTONEG_DISABLE;
+
+       cmd->maxtxpkt = 0;
+       cmd->maxrxpkt = 0;
+
+       DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
+          DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
+          DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
+          DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
+          cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
+          cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
+          cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
+
+       return 0;
+}
+
+static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       u32 advertising;
+
+       if (IS_E1HMF(bp))
+               return 0;
+
+       DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
+          DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
+          DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
+          DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
+          cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
+          cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
+          cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
+
+       if (cmd->autoneg == AUTONEG_ENABLE) {
+               if (!(bp->port.supported & SUPPORTED_Autoneg)) {
+                       DP(NETIF_MSG_LINK, "Autoneg not supported\n");
+                       return -EINVAL;
+               }
+
+               /* advertise the requested speed and duplex if supported */
+               cmd->advertising &= bp->port.supported;
+
+               bp->link_params.req_line_speed = SPEED_AUTO_NEG;
+               bp->link_params.req_duplex = DUPLEX_FULL;
+               bp->port.advertising |= (ADVERTISED_Autoneg |
+                                        cmd->advertising);
+
+       } else { /* forced speed */
+               /* advertise the requested speed and duplex if supported */
+               switch (cmd->speed) {
+               case SPEED_10:
+                       if (cmd->duplex == DUPLEX_FULL) {
+                               if (!(bp->port.supported &
+                                     SUPPORTED_10baseT_Full)) {
+                                       DP(NETIF_MSG_LINK,
+                                          "10M full not supported\n");
+                                       return -EINVAL;
+                               }
+
+                               advertising = (ADVERTISED_10baseT_Full |
+                                              ADVERTISED_TP);
+                       } else {
+                               if (!(bp->port.supported &
+                                     SUPPORTED_10baseT_Half)) {
+                                       DP(NETIF_MSG_LINK,
+                                          "10M half not supported\n");
+                                       return -EINVAL;
+                               }
+
+                               advertising = (ADVERTISED_10baseT_Half |
+                                              ADVERTISED_TP);
+                       }
+                       break;
+
+               case SPEED_100:
+                       if (cmd->duplex == DUPLEX_FULL) {
+                               if (!(bp->port.supported &
+                                               SUPPORTED_100baseT_Full)) {
+                                       DP(NETIF_MSG_LINK,
+                                          "100M full not supported\n");
+                                       return -EINVAL;
+                               }
+
+                               advertising = (ADVERTISED_100baseT_Full |
+                                              ADVERTISED_TP);
+                       } else {
+                               if (!(bp->port.supported &
+                                               SUPPORTED_100baseT_Half)) {
+                                       DP(NETIF_MSG_LINK,
+                                          "100M half not supported\n");
+                                       return -EINVAL;
+                               }
+
+                               advertising = (ADVERTISED_100baseT_Half |
+                                              ADVERTISED_TP);
+                       }
+                       break;
+
+               case SPEED_1000:
+                       if (cmd->duplex != DUPLEX_FULL) {
+                               DP(NETIF_MSG_LINK, "1G half not supported\n");
+                               return -EINVAL;
+                       }
+
+                       if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
+                               DP(NETIF_MSG_LINK, "1G full not supported\n");
+                               return -EINVAL;
+                       }
+
+                       advertising = (ADVERTISED_1000baseT_Full |
+                                      ADVERTISED_TP);
+                       break;
+
+               case SPEED_2500:
+                       if (cmd->duplex != DUPLEX_FULL) {
+                               DP(NETIF_MSG_LINK,
+                                  "2.5G half not supported\n");
+                               return -EINVAL;
+                       }
+
+                       if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
+                               DP(NETIF_MSG_LINK,
+                                  "2.5G full not supported\n");
+                               return -EINVAL;
+                       }
+
+                       advertising = (ADVERTISED_2500baseX_Full |
+                                      ADVERTISED_TP);
+                       break;
+
+               case SPEED_10000:
+                       if (cmd->duplex != DUPLEX_FULL) {
+                               DP(NETIF_MSG_LINK, "10G half not supported\n");
+                               return -EINVAL;
+                       }
+
+                       if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
+                               DP(NETIF_MSG_LINK, "10G full not supported\n");
+                               return -EINVAL;
+                       }
+
+                       advertising = (ADVERTISED_10000baseT_Full |
+                                      ADVERTISED_FIBRE);
+                       break;
+
+               default:
+                       DP(NETIF_MSG_LINK, "Unsupported speed\n");
+                       return -EINVAL;
+               }
+
+               bp->link_params.req_line_speed = cmd->speed;
+               bp->link_params.req_duplex = cmd->duplex;
+               bp->port.advertising = advertising;
+       }
+
+       DP(NETIF_MSG_LINK, "req_line_speed %d\n"
+          DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
+          bp->link_params.req_line_speed, bp->link_params.req_duplex,
+          bp->port.advertising);
+
+       if (netif_running(dev)) {
+               bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+               bnx2x_link_set(bp);
+       }
+
+       return 0;
+}
+
+#define IS_E1_ONLINE(info)     (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
+#define IS_E1H_ONLINE(info)    (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
+
+static int bnx2x_get_regs_len(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int regdump_len = 0;
+       int i;
+
+       if (CHIP_IS_E1(bp)) {
+               for (i = 0; i < REGS_COUNT; i++)
+                       if (IS_E1_ONLINE(reg_addrs[i].info))
+                               regdump_len += reg_addrs[i].size;
+
+               for (i = 0; i < WREGS_COUNT_E1; i++)
+                       if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
+                               regdump_len += wreg_addrs_e1[i].size *
+                                       (1 + wreg_addrs_e1[i].read_regs_count);
+
+       } else { /* E1H */
+               for (i = 0; i < REGS_COUNT; i++)
+                       if (IS_E1H_ONLINE(reg_addrs[i].info))
+                               regdump_len += reg_addrs[i].size;
+
+               for (i = 0; i < WREGS_COUNT_E1H; i++)
+                       if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
+                               regdump_len += wreg_addrs_e1h[i].size *
+                                       (1 + wreg_addrs_e1h[i].read_regs_count);
+       }
+       regdump_len *= 4;
+       regdump_len += sizeof(struct dump_hdr);
+
+       return regdump_len;
+}
+
+static void bnx2x_get_regs(struct net_device *dev,
+                          struct ethtool_regs *regs, void *_p)
+{
+       u32 *p = _p, i, j;
+       struct bnx2x *bp = netdev_priv(dev);
+       struct dump_hdr dump_hdr = {0};
+
+       regs->version = 0;
+       memset(p, 0, regs->len);
+
+       if (!netif_running(bp->dev))
+               return;
+
+       dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
+       dump_hdr.dump_sign = dump_sign_all;
+       dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
+       dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
+       dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
+       dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
+       dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;
+
+       memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
+       p += dump_hdr.hdr_size + 1;
+
+       if (CHIP_IS_E1(bp)) {
+               for (i = 0; i < REGS_COUNT; i++)
+                       if (IS_E1_ONLINE(reg_addrs[i].info))
+                               for (j = 0; j < reg_addrs[i].size; j++)
+                                       *p++ = REG_RD(bp,
+                                                     reg_addrs[i].addr + j*4);
+
+       } else { /* E1H */
+               for (i = 0; i < REGS_COUNT; i++)
+                       if (IS_E1H_ONLINE(reg_addrs[i].info))
+                               for (j = 0; j < reg_addrs[i].size; j++)
+                                       *p++ = REG_RD(bp,
+                                                     reg_addrs[i].addr + j*4);
+       }
+}
+
+#define PHY_FW_VER_LEN                 10
+
+static void bnx2x_get_drvinfo(struct net_device *dev,
+                             struct ethtool_drvinfo *info)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       u8 phy_fw_ver[PHY_FW_VER_LEN];
+
+       strcpy(info->driver, DRV_MODULE_NAME);
+       strcpy(info->version, DRV_MODULE_VERSION);
+
+       phy_fw_ver[0] = '\0';
+       if (bp->port.pmf) {
+               bnx2x_acquire_phy_lock(bp);
+               bnx2x_get_ext_phy_fw_version(&bp->link_params,
+                                            (bp->state != BNX2X_STATE_CLOSED),
+                                            phy_fw_ver, PHY_FW_VER_LEN);
+               bnx2x_release_phy_lock(bp);
+       }
+
+       snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s",
+                (bp->common.bc_ver & 0xff0000) >> 16,
+                (bp->common.bc_ver & 0xff00) >> 8,
+                (bp->common.bc_ver & 0xff),
+                ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver);
+       strcpy(info->bus_info, pci_name(bp->pdev));
+       info->n_stats = BNX2X_NUM_STATS;
+       info->testinfo_len = BNX2X_NUM_TESTS;
+       info->eedump_len = bp->common.flash_size;
+       info->regdump_len = bnx2x_get_regs_len(dev);
+}
+
+static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (bp->flags & NO_WOL_FLAG) {
+               wol->supported = 0;
+               wol->wolopts = 0;
+       } else {
+               wol->supported = WAKE_MAGIC;
+               if (bp->wol)
+                       wol->wolopts = WAKE_MAGIC;
+               else
+                       wol->wolopts = 0;
+       }
+       memset(&wol->sopass, 0, sizeof(wol->sopass));
+}
+
+static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (wol->wolopts & ~WAKE_MAGIC)
+               return -EINVAL;
+
+       if (wol->wolopts & WAKE_MAGIC) {
+               if (bp->flags & NO_WOL_FLAG)
+                       return -EINVAL;
+
+               bp->wol = 1;
+       } else
+               bp->wol = 0;
+
+       return 0;
+}
+
+static u32 bnx2x_get_msglevel(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       return bp->msglevel;
+}
+
+static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (capable(CAP_NET_ADMIN))
+               bp->msglevel = level;
+}
+
+static int bnx2x_nway_reset(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (!bp->port.pmf)
+               return 0;
+
+       if (netif_running(dev)) {
+               bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+               bnx2x_link_set(bp);
+       }
+
+       return 0;
+}
+
+static u32 bnx2x_get_link(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       return bp->link_vars.link_up;
+}
+
+#if (LINUX_VERSION_CODE >= 0x020418) /* BNX2X_UPSTREAM */
+static int bnx2x_get_eeprom_len(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       return bp->common.flash_size;
+}
+#endif
+
+static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int count, i;
+       u32 val = 0;
+
+       /* adjust timeout for emulation/FPGA */
+       count = NVRAM_TIMEOUT_COUNT;
+       if (CHIP_REV_IS_SLOW(bp))
+               count *= 100;
+
+       /* request access to nvram interface */
+       REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
+              (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
+
+       for (i = 0; i < count*10; i++) {
+               val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
+               if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
+                       break;
+
+               udelay(5);
+       }
+
+       if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
+               DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
+               return -EBUSY;
+       }
+
+       return 0;
+}
+
+static int bnx2x_release_nvram_lock(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int count, i;
+       u32 val = 0;
+
+       /* adjust timeout for emulation/FPGA */
+       count = NVRAM_TIMEOUT_COUNT;
+       if (CHIP_REV_IS_SLOW(bp))
+               count *= 100;
+
+       /* relinquish nvram interface */
+       REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
+              (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
+
+       for (i = 0; i < count*10; i++) {
+               val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
+               if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
+                       break;
+
+               udelay(5);
+       }
+
+       if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
+               DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
+               return -EBUSY;
+       }
+
+       return 0;
+}
+
+static void bnx2x_enable_nvram_access(struct bnx2x *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
+
+       /* enable both bits, even on read */
+       REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
+              (val | MCPR_NVM_ACCESS_ENABLE_EN |
+                     MCPR_NVM_ACCESS_ENABLE_WR_EN));
+}
+
+static void bnx2x_disable_nvram_access(struct bnx2x *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
+
+       /* disable both bits, even after read */
+       REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
+              (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
+                       MCPR_NVM_ACCESS_ENABLE_WR_EN)));
+}
+
+static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
+                                 u32 cmd_flags)
+{
+       int count, i, rc;
+       u32 val;
+
+       /* build the command word */
+       cmd_flags |= MCPR_NVM_COMMAND_DOIT;
+
+       /* need to clear DONE bit separately */
+       REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
+
+       /* address of the NVRAM to read from */
+       REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
+              (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
+
+       /* issue a read command */
+       REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
+
+       /* adjust timeout for emulation/FPGA */
+       count = NVRAM_TIMEOUT_COUNT;
+       if (CHIP_REV_IS_SLOW(bp))
+               count *= 100;
+
+       /* wait for completion */
+       *ret_val = 0;
+       rc = -EBUSY;
+       for (i = 0; i < count; i++) {
+               udelay(5);
+               val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
+
+               if (val & MCPR_NVM_COMMAND_DONE) {
+                       val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
+                       /* we read nvram data in cpu order
+                        * but ethtool sees it as an array of bytes
+                        * converting to big-endian will do the work */
+                       *ret_val = cpu_to_be32(val);
+                       rc = 0;
+                       break;
+               }
+       }
+
+       return rc;
+}
+
+static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
+                           int buf_size)
+{
+       int rc;
+       u32 cmd_flags;
+       __be32 val;
+
+       if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+               DP(BNX2X_MSG_NVM,
+                  "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
+                  offset, buf_size);
+               return -EINVAL;
+       }
+
+       if (offset + buf_size > bp->common.flash_size) {
+               DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
+                                 " buf_size (0x%x) > flash_size (0x%x)\n",
+                  offset, buf_size, bp->common.flash_size);
+               return -EINVAL;
+       }
+
+       /* request access to nvram interface */
+       rc = bnx2x_acquire_nvram_lock(bp);
+       if (rc)
+               return rc;
+
+       /* enable access to nvram interface */
+       bnx2x_enable_nvram_access(bp);
+
+       /* read the first word(s) */
+       cmd_flags = MCPR_NVM_COMMAND_FIRST;
+       while ((buf_size > sizeof(u32)) && (rc == 0)) {
+               rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
+               memcpy(ret_buf, &val, 4);
+
+               /* advance to the next dword */
+               offset += sizeof(u32);
+               ret_buf += sizeof(u32);
+               buf_size -= sizeof(u32);
+               cmd_flags = 0;
+       }
+
+       if (rc == 0) {
+               cmd_flags |= MCPR_NVM_COMMAND_LAST;
+               rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
+               memcpy(ret_buf, &val, 4);
+       }
+
+       /* disable access to nvram interface */
+       bnx2x_disable_nvram_access(bp);
+       bnx2x_release_nvram_lock(bp);
+
+       return rc;
+}
+
+static int bnx2x_get_eeprom(struct net_device *dev,
+                           struct ethtool_eeprom *eeprom, u8 *eebuf)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int rc;
+
+       if (!netif_running(dev))
+               return -EAGAIN;
+
+       DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
+          DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
+          eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
+          eeprom->len, eeprom->len);
+
+       /* parameters already validated in ethtool_get_eeprom */
+
+       rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
+
+       return rc;
+}
+
+static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
+                                  u32 cmd_flags)
+{
+       int count, i, rc;
+
+       /* build the command word */
+       cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
+
+       /* need to clear DONE bit separately */
+       REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
+
+       /* write the data */
+       REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
+
+       /* address of the NVRAM to write to */
+       REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
+              (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
+
+       /* issue the write command */
+       REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
+
+       /* adjust timeout for emulation/FPGA */
+       count = NVRAM_TIMEOUT_COUNT;
+       if (CHIP_REV_IS_SLOW(bp))
+               count *= 100;
+
+       /* wait for completion */
+       rc = -EBUSY;
+       for (i = 0; i < count; i++) {
+               udelay(5);
+               val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
+               if (val & MCPR_NVM_COMMAND_DONE) {
+                       rc = 0;
+                       break;
+               }
+       }
+
+       return rc;
+}
+
+#define BYTE_OFFSET(offset)            (8 * (offset & 0x03))
+
+static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
+                             int buf_size)
+{
+       int rc;
+       u32 cmd_flags;
+       u32 align_offset;
+       __be32 val;
+
+       if (offset + buf_size > bp->common.flash_size) {
+               DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
+                                 " buf_size (0x%x) > flash_size (0x%x)\n",
+                  offset, buf_size, bp->common.flash_size);
+               return -EINVAL;
+       }
+
+       /* request access to nvram interface */
+       rc = bnx2x_acquire_nvram_lock(bp);
+       if (rc)
+               return rc;
+
+       /* enable access to nvram interface */
+       bnx2x_enable_nvram_access(bp);
+
+       cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
+       align_offset = (offset & ~0x03);
+       rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
+
+       if (rc == 0) {
+               val &= ~(0xff << BYTE_OFFSET(offset));
+               val |= (*data_buf << BYTE_OFFSET(offset));
+
+               /* nvram data is returned as an array of bytes
+                * convert it back to cpu order */
+               val = be32_to_cpu(val);
+
+               rc = bnx2x_nvram_write_dword(bp, align_offset, val,
+                                            cmd_flags);
+       }
+
+       /* disable access to nvram interface */
+       bnx2x_disable_nvram_access(bp);
+       bnx2x_release_nvram_lock(bp);
+
+       return rc;
+}
+
+static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
+                            int buf_size)
+{
+       int rc;
+       u32 cmd_flags;
+       u32 val;
+       u32 written_so_far;
+
+       if (buf_size == 1)      /* ethtool */
+               return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
+
+       if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+               DP(BNX2X_MSG_NVM,
+                  "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
+                  offset, buf_size);
+               return -EINVAL;
+       }
+
+       if (offset + buf_size > bp->common.flash_size) {
+               DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
+                                 " buf_size (0x%x) > flash_size (0x%x)\n",
+                  offset, buf_size, bp->common.flash_size);
+               return -EINVAL;
+       }
+
+       /* request access to nvram interface */
+       rc = bnx2x_acquire_nvram_lock(bp);
+       if (rc)
+               return rc;
+
+       /* enable access to nvram interface */
+       bnx2x_enable_nvram_access(bp);
+
+       written_so_far = 0;
+       cmd_flags = MCPR_NVM_COMMAND_FIRST;
+       while ((written_so_far < buf_size) && (rc == 0)) {
+               if (written_so_far == (buf_size - sizeof(u32)))
+                       cmd_flags |= MCPR_NVM_COMMAND_LAST;
+               else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
+                       cmd_flags |= MCPR_NVM_COMMAND_LAST;
+               else if ((offset % NVRAM_PAGE_SIZE) == 0)
+                       cmd_flags |= MCPR_NVM_COMMAND_FIRST;
+
+               memcpy(&val, data_buf, 4);
+
+               rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
+
+               /* advance to the next dword */
+               offset += sizeof(u32);
+               data_buf += sizeof(u32);
+               written_so_far += sizeof(u32);
+               cmd_flags = 0;
+       }
+
+       /* disable access to nvram interface */
+       bnx2x_disable_nvram_access(bp);
+       bnx2x_release_nvram_lock(bp);
+
+       return rc;
+}
+
+static int bnx2x_set_eeprom(struct net_device *dev,
+                           struct ethtool_eeprom *eeprom, u8 *eebuf)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int port = BP_PORT(bp);
+       int rc = 0;
+
+       if (!netif_running(dev))
+               return -EAGAIN;
+
+       DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
+          DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
+          eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
+          eeprom->len, eeprom->len);
+
+       /* parameters already validated in ethtool_set_eeprom */
+
+       /* PHY eeprom can be accessed only by the PMF */
+       if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
+           !bp->port.pmf)
+               return -EINVAL;
+
+       if (eeprom->magic == 0x50485950) {
+               /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
+               bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+
+               bnx2x_acquire_phy_lock(bp);
+               rc |= bnx2x_link_reset(&bp->link_params,
+                                      &bp->link_vars, 0);
+               if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
+                                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                                      MISC_REGISTERS_GPIO_HIGH, port);
+               bnx2x_release_phy_lock(bp);
+               bnx2x_link_report(bp);
+
+       } else if (eeprom->magic == 0x50485952) {
+               /* 'PHYR' (0x50485952): re-init link after FW upgrade */
+               if ((bp->state == BNX2X_STATE_OPEN) ||
+                   (bp->state == BNX2X_STATE_DISABLED)) {
+                       bnx2x_acquire_phy_lock(bp);
+                       rc |= bnx2x_link_reset(&bp->link_params,
+                                              &bp->link_vars, 1);
+
+                       rc |= bnx2x_phy_init(&bp->link_params,
+                                            &bp->link_vars);
+                       bnx2x_release_phy_lock(bp);
+                       bnx2x_calc_fc_adv(bp);
+               }
+       } else if (eeprom->magic == 0x53985943) {
+               /* 'PHYC' (0x53985943): PHY FW upgrade completed */
+               if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
+                                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
+                       u8 ext_phy_addr =
+                            XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
+
+                       /* DSP Remove Download Mode */
+                       bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
+                                      MISC_REGISTERS_GPIO_LOW, port);
+
+                       bnx2x_acquire_phy_lock(bp);
+
+                       bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
+
+                       /* wait 0.5 sec to allow it to run */
+                       msleep(500);
+                       bnx2x_ext_phy_hw_reset(bp, port);
+                       msleep(500);
+                       bnx2x_release_phy_lock(bp);
+               }
+       } else
+               rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
+
+       return rc;
+}
+
+static int bnx2x_get_coalesce(struct net_device *dev,
+                             struct ethtool_coalesce *coal)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       memset(coal, 0, sizeof(struct ethtool_coalesce));
+
+       coal->rx_coalesce_usecs = bp->rx_ticks;
+       coal->tx_coalesce_usecs = bp->tx_ticks;
+
+       return 0;
+}
+
+#define BNX2X_MAX_COALES_TOUT  (0xf0*12) /* Maximal coalescing timeout in us */
+static int bnx2x_set_coalesce(struct net_device *dev,
+                             struct ethtool_coalesce *coal)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
+       if (bp->rx_ticks > BNX2X_MAX_COALES_TOUT)
+               bp->rx_ticks = BNX2X_MAX_COALES_TOUT;
+
+       bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
+       if (bp->tx_ticks > BNX2X_MAX_COALES_TOUT)
+               bp->tx_ticks = BNX2X_MAX_COALES_TOUT;
+
+       if (netif_running(dev))
+               bnx2x_update_coalesce(bp);
+
+       return 0;
+}
+
+static void bnx2x_get_ringparam(struct net_device *dev,
+                               struct ethtool_ringparam *ering)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       ering->rx_max_pending = MAX_RX_AVAIL;
+       ering->rx_mini_max_pending = 0;
+       ering->rx_jumbo_max_pending = 0;
+
+       ering->rx_pending = bp->rx_ring_size;
+       ering->rx_mini_pending = 0;
+       ering->rx_jumbo_pending = 0;
+
+       ering->tx_max_pending = MAX_TX_AVAIL;
+       ering->tx_pending = bp->tx_ring_size;
+}
+
+static int bnx2x_set_ringparam(struct net_device *dev,
+                              struct ethtool_ringparam *ering)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int rc = 0;
+
+       if ((ering->rx_pending > MAX_RX_AVAIL) ||
+           (ering->tx_pending > MAX_TX_AVAIL) ||
+           (ering->tx_pending <= MAX_SKB_FRAGS + 4))
+               return -EINVAL;
+
+       bp->rx_ring_size = ering->rx_pending;
+       bp->tx_ring_size = ering->tx_pending;
+
+       if (netif_running(dev)) {
+               bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+               rc = bnx2x_nic_load(bp, LOAD_NORMAL);
+       }
+
+       return rc;
+}
+
+static void bnx2x_get_pauseparam(struct net_device *dev,
+                                struct ethtool_pauseparam *epause)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       epause->autoneg = (bp->link_params.req_flow_ctrl ==
+                          BNX2X_FLOW_CTRL_AUTO) &&
+                         (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
+
+       epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
+                           BNX2X_FLOW_CTRL_RX);
+       epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
+                           BNX2X_FLOW_CTRL_TX);
+
+       DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
+          DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
+          epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
+}
+
+static int bnx2x_set_pauseparam(struct net_device *dev,
+                               struct ethtool_pauseparam *epause)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (IS_E1HMF(bp))
+               return 0;
+
+       DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
+          DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
+          epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
+
+       bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
+
+       if (epause->rx_pause)
+               bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX;
+
+       if (epause->tx_pause)
+               bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX;
+
+       if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
+               bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
+
+       if (epause->autoneg) {
+               if (!(bp->port.supported & SUPPORTED_Autoneg)) {
+                       DP(NETIF_MSG_LINK, "autoneg not supported\n");
+                       return -EINVAL;
+               }
+
+               if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
+                       bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
+       }
+
+       DP(NETIF_MSG_LINK,
+          "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
+
+       if (netif_running(dev)) {
+               bnx2x_stats_handle(bp, STATS_EVENT_STOP);
+               bnx2x_link_set(bp);
+       }
+
+       return 0;
+}
+
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+static int bnx2x_set_flags(struct net_device *dev, u32 data)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int changed = 0;
+       int rc = 0;
+
+       /* TPA requires Rx CSUM offloading */
+       if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
+               if (!(dev->features & NETIF_F_LRO)) {
+                       dev->features |= NETIF_F_LRO;
+                       bp->flags |= TPA_ENABLE_FLAG;
+                       changed = 1;
+               }
+
+       } else if (dev->features & NETIF_F_LRO) {
+               dev->features &= ~NETIF_F_LRO;
+               bp->flags &= ~TPA_ENABLE_FLAG;
+               changed = 1;
+       }
+
+       if (changed && netif_running(dev)) {
+               bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+               rc = bnx2x_nic_load(bp, LOAD_NORMAL);
+       }
+
+       return rc;
+}
+#endif
+
+static u32 bnx2x_get_rx_csum(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       return bp->rx_csum;
+}
+
+static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int rc = 0;
+
+       bp->rx_csum = data;
+
+       /* Disable TPA, when Rx CSUM is disabled. Otherwise all
+          TPA'ed packets will be discarded due to wrong TCP CSUM */
+       if (!data) {
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+               u32 flags = ethtool_op_get_flags(dev);
+
+               rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
+#else
+               bp->flags &= ~TPA_ENABLE_FLAG;
+               if (netif_running(dev)) {
+                       bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+                       rc = bnx2x_nic_load(bp, LOAD_NORMAL);
+               }
+#endif
+       }
+
+       return rc;
+}
+
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+static int bnx2x_set_tso(struct net_device *dev, u32 data)
+{
+       if (data) {
+               dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
+#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */
+               dev->features |= NETIF_F_TSO6;
+#endif
+#ifdef BCM_VLAN
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+               dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
+               dev->vlan_features |= NETIF_F_TSO6;
+#endif
+#endif
+       } else {
+               dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
+#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */
+               dev->features &= ~NETIF_F_TSO6;
+#endif
+#ifdef BCM_VLAN
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+               dev->vlan_features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
+               dev->vlan_features &= ~NETIF_F_TSO6;
+#endif
+#endif
+       }
+
+       return 0;
+}
+#endif
+
+static const struct {
+       char string[ETH_GSTRING_LEN];
+} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
+       { "register_test (offline)" },
+       { "memory_test (offline)" },
+       { "loopback_test (offline)" },
+       { "nvram_test (online)" },
+       { "interrupt_test (online)" },
+       { "link_test (online)" },
+       { "idle check (online)" }
+};
+
+static int bnx2x_self_test_count(struct net_device *dev)
+{
+       return BNX2X_NUM_TESTS;
+}
+
+static int bnx2x_test_registers(struct bnx2x *bp)
+{
+       int idx, i, rc = -ENODEV;
+       u32 wr_val = 0;
+       int port = BP_PORT(bp);
+       static const struct {
+               u32  offset0;
+               u32  offset1;
+               u32  mask;
+       } reg_tbl[] = {
+/* 0 */                { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
+               { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
+               { HC_REG_AGG_INT_0,                    4, 0x000003ff },
+               { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
+               { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
+               { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
+               { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
+               { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
+               { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
+               { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
+/* 10 */       { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
+               { QM_REG_CONNNUM_0,                    4, 0x000fffff },
+               { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
+               { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
+               { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
+               { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
+               { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
+               { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
+               { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
+               { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
+/* 20 */       { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
+               { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
+               { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
+               { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
+               { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
+               { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
+               { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
+               { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
+               { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
+               { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
+/* 30 */       { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
+               { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
+               { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
+               { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
+               { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
+               { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
+               { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
+
+               { 0xffffffff, 0, 0x00000000 }
+       };
+
+       if (!netif_running(bp->dev))
+               return rc;
+
+       /* Repeat the test twice:
+          First by writing 0x00000000, second by writing 0xffffffff */
+       for (idx = 0; idx < 2; idx++) {
+
+               switch (idx) {
+               case 0:
+                       wr_val = 0;
+                       break;
+               case 1:
+                       wr_val = 0xffffffff;
+                       break;
+               }
+
+               for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
+                       u32 offset, mask, save_val, val;
+
+                       offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
+                       mask = reg_tbl[i].mask;
+
+                       save_val = REG_RD(bp, offset);
+
+                       REG_WR(bp, offset, wr_val);
+                       val = REG_RD(bp, offset);
+
+                       /* Restore the original register's value */
+                       REG_WR(bp, offset, save_val);
+
+                       /* verify that value is as expected value */
+                       if ((val & mask) != (wr_val & mask))
+                               goto test_reg_exit;
+               }
+       }
+
+       rc = 0;
+
+test_reg_exit:
+       return rc;
+}
+
+static int bnx2x_test_memory(struct bnx2x *bp)
+{
+       int i, j, rc = -ENODEV;
+       u32 val;
+       static const struct {
+               u32 offset;
+               int size;
+       } mem_tbl[] = {
+               { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
+               { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
+               { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
+               { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
+               { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
+               { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
+               { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
+
+               { 0xffffffff, 0 }
+       };
+       static const struct {
+               char *name;
+               u32 offset;
+               u32 e1_mask;
+               u32 e1h_mask;
+       } prty_tbl[] = {
+               { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0 },
+               { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2 },
+               { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0 },
+               { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0 },
+               { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0 },
+               { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0 },
+
+               { NULL, 0xffffffff, 0, 0 }
+       };
+
+       if (!netif_running(bp->dev))
+               return rc;
+
+       /* Go through all the memories */
+       for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
+               for (j = 0; j < mem_tbl[i].size; j++)
+                       REG_RD(bp, mem_tbl[i].offset + j*4);
+
+       /* Check the parity status */
+       for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
+               val = REG_RD(bp, prty_tbl[i].offset);
+               if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
+                   (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
+                       DP(NETIF_MSG_HW,
+                          "%s is 0x%x\n", prty_tbl[i].name, val);
+                       goto test_mem_exit;
+               }
+       }
+
+       rc = 0;
+
+test_mem_exit:
+       return rc;
+}
+
+static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
+{
+       int cnt = 1000;
+
+       if (link_up)
+               while (bnx2x_link_test(bp) && cnt--)
+                       msleep(10);
+}
+
+static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
+{
+       unsigned int pkt_size, num_pkts, i;
+       struct sk_buff *skb;
+       unsigned char *packet;
+       struct bnx2x_fastpath *fp_rx = &bp->fp[0];
+       struct bnx2x_fastpath *fp_tx = &bp->fp[bp->num_rx_queues];
+       u16 tx_start_idx, tx_idx;
+       u16 rx_start_idx, rx_idx;
+       u16 pkt_prod, bd_prod;
+       struct sw_tx_bd *tx_buf;
+       struct eth_tx_start_bd *tx_start_bd;
+       struct eth_tx_parse_bd *pbd = NULL;
+       dma_addr_t mapping;
+       union eth_rx_cqe *cqe;
+       u8 cqe_fp_flags;
+       struct sw_rx_bd *rx_buf;
+       u16 len;
+       int rc = -ENODEV;
+
+       /* check the loopback mode */
+       switch (loopback_mode) {
+       case BNX2X_PHY_LOOPBACK:
+               if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
+                       return -EINVAL;
+               break;
+       case BNX2X_MAC_LOOPBACK:
+               bp->link_params.loopback_mode = LOOPBACK_BMAC;
+               bnx2x_phy_init(&bp->link_params, &bp->link_vars);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       /* prepare the loopback packet */
+       pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
+                    bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
+       skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
+       if (!skb) {
+               rc = -ENOMEM;
+               goto test_loopback_exit;
+       }
+       packet = skb_put(skb, pkt_size);
+       memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
+       memset(packet + ETH_ALEN, 0, ETH_ALEN);
+       memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
+       for (i = ETH_HLEN; i < pkt_size; i++)
+               packet[i] = (unsigned char) (i & 0xff);
+
+       /* send the loopback packet */
+       num_pkts = 0;
+       tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
+       rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
+
+       pkt_prod = fp_tx->tx_pkt_prod++;
+       tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
+       tx_buf->first_bd = fp_tx->tx_bd_prod;
+       tx_buf->skb = skb;
+       tx_buf->flags = 0;
+
+       bd_prod = TX_BD(fp_tx->tx_bd_prod);
+       tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
+       mapping = pci_map_single(bp->pdev, skb->data,
+                                skb_headlen(skb), PCI_DMA_TODEVICE);
+       tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+       tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+       tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
+       tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
+       tx_start_bd->vlan = cpu_to_le16(pkt_prod);
+       tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+       tx_start_bd->general_data = ((UNICAST_ADDRESS <<
+                               ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1);
+
+       /* turn on parsing and get a BD */
+       bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+       pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd;
+
+       memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
+
+       wmb();
+
+       fp_tx->tx_db.data.prod += 2;
+       barrier();
+       DOORBELL(bp, fp_tx->index - bp->num_rx_queues, fp_tx->tx_db.raw);
+
+       mmiowb();
+
+       num_pkts++;
+       fp_tx->tx_bd_prod += 2; /* start + pbd */
+       bp->dev->trans_start = jiffies;
+
+       udelay(100);
+
+       tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
+       if (tx_idx != tx_start_idx + num_pkts)
+               goto test_loopback_exit;
+
+       rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
+       if (rx_idx != rx_start_idx + num_pkts)
+               goto test_loopback_exit;
+
+       cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
+       cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
+       if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
+               goto test_loopback_rx_exit;
+
+       len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
+       if (len != pkt_size)
+               goto test_loopback_rx_exit;
+
+       rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
+       skb = rx_buf->skb;
+       skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
+       for (i = ETH_HLEN; i < pkt_size; i++)
+               if (*(skb->data + i) != (unsigned char) (i & 0xff))
+                       goto test_loopback_rx_exit;
+
+       rc = 0;
+
+test_loopback_rx_exit:
+#if (LINUX_VERSION_CODE < 0x02061b) /* ! BNX2X_UPSTREAM */
+       bp->dev->last_rx = jiffies;
+#endif
+
+       fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
+       fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
+       fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
+       fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
+
+       /* Update producers */
+       bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
+                            fp_rx->rx_sge_prod);
+
+test_loopback_exit:
+       bp->link_params.loopback_mode = LOOPBACK_NONE;
+
+       return rc;
+}
+
+static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
+{
+       int rc = 0, res;
+
+       if (!netif_running(bp->dev))
+               return BNX2X_LOOPBACK_FAILED;
+
+       bnx2x_netif_stop(bp, 1);
+       bnx2x_acquire_phy_lock(bp);
+
+       res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
+       if (res) {
+               DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
+               rc |= BNX2X_PHY_LOOPBACK_FAILED;
+       }
+
+       res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
+       if (res) {
+               DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
+               rc |= BNX2X_MAC_LOOPBACK_FAILED;
+       }
+
+       bnx2x_release_phy_lock(bp);
+       bnx2x_netif_start(bp);
+
+       return rc;
+}
+
+#define CRC32_RESIDUAL                 0xdebb20e3
+
+static int bnx2x_test_nvram(struct bnx2x *bp)
+{
+       static const struct {
+               int offset;
+               int size;
+       } nvram_tbl[] = {
+               {     0,  0x14 }, /* bootstrap */
+               {  0x14,  0xec }, /* dir */
+               { 0x100, 0x350 }, /* manuf_info */
+               { 0x450,  0xf0 }, /* feature_info */
+               { 0x640,  0x64 }, /* upgrade_key_info */
+               { 0x6a4,  0x64 },
+               { 0x708,  0x70 }, /* manuf_key_info */
+               { 0x778,  0x70 },
+               {     0,     0 }
+       };
+       __be32 buf[0x350 / 4];
+       u8 *data = (u8 *)buf;
+       int i, rc;
+       u32 magic, crc;
+
+       rc = bnx2x_nvram_read(bp, 0, data, 4);
+       if (rc) {
+               DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
+               goto test_nvram_exit;
+       }
+
+       magic = be32_to_cpu(buf[0]);
+       if (magic != 0x669955aa) {
+               DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
+               rc = -ENODEV;
+               goto test_nvram_exit;
+       }
+
+       for (i = 0; nvram_tbl[i].size; i++) {
+
+               rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
+                                     nvram_tbl[i].size);
+               if (rc) {
+                       DP(NETIF_MSG_PROBE,
+                          "nvram_tbl[%d] read data (rc %d)\n", i, rc);
+                       goto test_nvram_exit;
+               }
+
+               crc = ether_crc_le(nvram_tbl[i].size, data);
+               if (crc != CRC32_RESIDUAL) {
+                       DP(NETIF_MSG_PROBE,
+                          "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
+                       rc = -ENODEV;
+                       goto test_nvram_exit;
+               }
+       }
+
+test_nvram_exit:
+       return rc;
+}
+
+static int bnx2x_test_intr(struct bnx2x *bp)
+{
+       struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
+       int i, rc;
+
+       if (!netif_running(bp->dev))
+               return -ENODEV;
+
+       config->hdr.length = 0;
+       if (CHIP_IS_E1(bp))
+               config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
+       else
+               config->hdr.offset = BP_FUNC(bp);
+       config->hdr.client_id = bp->fp->cl_id;
+       config->hdr.reserved1 = 0;
+
+       rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                          U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                          U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+       if (rc == 0) {
+               bp->set_mac_pending++;
+               for (i = 0; i < 10; i++) {
+                       if (!bp->set_mac_pending)
+                               break;
+                       msleep_interruptible(10);
+               }
+               if (i == 10)
+                       rc = -ENODEV;
+       }
+
+       return rc;
+}
+
+static void bnx2x_self_test(struct net_device *dev,
+                           struct ethtool_test *etest, u64 *buf)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
+
+       if (!netif_running(dev))
+               return;
+
+       /* offline tests are not supported in MF mode */
+       if (IS_E1HMF(bp))
+               etest->flags &= ~ETH_TEST_FL_OFFLINE;
+
+       if (etest->flags & ETH_TEST_FL_OFFLINE) {
+               int port = BP_PORT(bp);
+               u32 val;
+               u8 link_up;
+
+               /* save current value of input enable for TX port IF */
+               val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
+               /* disable input for TX port IF */
+               REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
+
+               link_up = bp->link_vars.link_up;
+               bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+               bnx2x_nic_load(bp, LOAD_DIAG);
+               /* wait until link state is restored */
+               bnx2x_wait_for_link(bp, link_up);
+
+               if (bnx2x_test_registers(bp) != 0) {
+                       buf[0] = 1;
+                       etest->flags |= ETH_TEST_FL_FAILED;
+               }
+               if (bnx2x_test_memory(bp) != 0) {
+                       buf[1] = 1;
+                       etest->flags |= ETH_TEST_FL_FAILED;
+               }
+               buf[2] = bnx2x_test_loopback(bp, link_up);
+               if (buf[2] != 0)
+                       etest->flags |= ETH_TEST_FL_FAILED;
+
+               bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+
+               /* restore input for TX port IF */
+               REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
+
+               bnx2x_nic_load(bp, LOAD_NORMAL);
+               /* wait until link state is restored */
+               bnx2x_wait_for_link(bp, link_up);
+       }
+       if (bnx2x_test_nvram(bp) != 0) {
+               buf[3] = 1;
+               etest->flags |= ETH_TEST_FL_FAILED;
+       }
+       if (bnx2x_test_intr(bp) != 0) {
+               buf[4] = 1;
+               etest->flags |= ETH_TEST_FL_FAILED;
+       }
+       if (bp->port.pmf)
+               if (bnx2x_link_test(bp) != 0) {
+                       buf[5] = 1;
+                       etest->flags |= ETH_TEST_FL_FAILED;
+               }
+#ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
+       /* run the idle check twice */
+       bnx2x_idle_chk(bp);
+       buf[6] = bnx2x_idle_chk(bp);
+       if (buf[6] != 0)
+               etest->flags |= ETH_TEST_FL_FAILED;
+#endif
+
+#ifdef BNX2X_EXTRA_DEBUG
+       bnx2x_panic_dump(bp);
+#endif
+}
+
+static const struct {
+       long offset;
+       int size;
+       u8 string[ETH_GSTRING_LEN];
+} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
+/* 1 */        { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
+       { Q_STATS_OFFSET32(error_bytes_received_hi),
+                                               8, "[%d]: rx_error_bytes" },
+       { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
+                                               8, "[%d]: rx_ucast_packets" },
+       { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
+                                               8, "[%d]: rx_mcast_packets" },
+       { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
+                                               8, "[%d]: rx_bcast_packets" },
+       { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
+       { Q_STATS_OFFSET32(rx_err_discard_pkt),
+                                        4, "[%d]: rx_phy_ip_err_discards"},
+       { Q_STATS_OFFSET32(rx_skb_alloc_failed),
+                                        4, "[%d]: rx_skb_alloc_discard" },
+       { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
+
+/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi),        8, "[%d]: tx_bytes" },
+       { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
+                                                       8, "[%d]: tx_packets" }
+};
+
+static const struct {
+       long offset;
+       int size;
+       u32 flags;
+#define STATS_FLAGS_PORT               1
+#define STATS_FLAGS_FUNC               2
+#define STATS_FLAGS_BOTH               (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
+       u8 string[ETH_GSTRING_LEN];
+} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
+/* 1 */        { STATS_OFFSET32(total_bytes_received_hi),
+                               8, STATS_FLAGS_BOTH, "rx_bytes" },
+       { STATS_OFFSET32(error_bytes_received_hi),
+                               8, STATS_FLAGS_BOTH, "rx_error_bytes" },
+       { STATS_OFFSET32(total_unicast_packets_received_hi),
+                               8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
+       { STATS_OFFSET32(total_multicast_packets_received_hi),
+                               8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
+       { STATS_OFFSET32(total_broadcast_packets_received_hi),
+                               8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
+       { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
+                               8, STATS_FLAGS_PORT, "rx_crc_errors" },
+       { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
+                               8, STATS_FLAGS_PORT, "rx_align_errors" },
+       { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
+                               8, STATS_FLAGS_PORT, "rx_undersize_packets" },
+       { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
+                               8, STATS_FLAGS_PORT, "rx_oversize_packets" },
+/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
+                               8, STATS_FLAGS_PORT, "rx_fragments" },
+       { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
+                               8, STATS_FLAGS_PORT, "rx_jabbers" },
+       { STATS_OFFSET32(no_buff_discard_hi),
+                               8, STATS_FLAGS_BOTH, "rx_discards" },
+       { STATS_OFFSET32(mac_filter_discard),
+                               4, STATS_FLAGS_PORT, "rx_filtered_packets" },
+       { STATS_OFFSET32(xxoverflow_discard),
+                               4, STATS_FLAGS_PORT, "rx_fw_discards" },
+       { STATS_OFFSET32(brb_drop_hi),
+                               8, STATS_FLAGS_PORT, "rx_brb_discard" },
+       { STATS_OFFSET32(brb_truncate_hi),
+                               8, STATS_FLAGS_PORT, "rx_brb_truncate" },
+       { STATS_OFFSET32(pause_frames_received_hi),
+                               8, STATS_FLAGS_PORT, "rx_pause_frames" },
+       { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
+                               8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
+       { STATS_OFFSET32(nig_timer_max),
+                       4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
+/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
+                               4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
+       { STATS_OFFSET32(rx_skb_alloc_failed),
+                               4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
+       { STATS_OFFSET32(hw_csum_err),
+                               4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
+
+       { STATS_OFFSET32(total_bytes_transmitted_hi),
+                               8, STATS_FLAGS_BOTH, "tx_bytes" },
+       { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
+                               8, STATS_FLAGS_PORT, "tx_error_bytes" },
+       { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
+                               8, STATS_FLAGS_BOTH, "tx_packets" },
+       { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
+                               8, STATS_FLAGS_PORT, "tx_mac_errors" },
+       { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
+                               8, STATS_FLAGS_PORT, "tx_carrier_errors" },
+       { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
+                               8, STATS_FLAGS_PORT, "tx_single_collisions" },
+       { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
+                               8, STATS_FLAGS_PORT, "tx_multi_collisions" },
+/* 30 */{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
+                               8, STATS_FLAGS_PORT, "tx_deferred" },
+       { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
+                               8, STATS_FLAGS_PORT, "tx_excess_collisions" },
+       { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
+                               8, STATS_FLAGS_PORT, "tx_late_collisions" },
+       { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
+                               8, STATS_FLAGS_PORT, "tx_total_collisions" },
+       { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
+                               8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
+       { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
+                       8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
+       { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
+                       8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
+       { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
+                       8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
+       { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
+                       8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
+       { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
+                       8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
+/* 40 */{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
+                       8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
+       { STATS_OFFSET32(pause_frames_sent_hi),
+                               8, STATS_FLAGS_PORT, "tx_pause_frames" }
+};
+
+#define IS_PORT_STAT(i) \
+       ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
+#define IS_FUNC_STAT(i)                (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
+#define IS_E1HMF_MODE_STAT(bp) \
+                       (IS_E1HMF(bp) && !(bp->msglevel & BNX2X_MSG_STATS))
+
+static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int i, j, k;
+
+       switch (stringset) {
+       case ETH_SS_STATS:
+               if (is_multi(bp)) {
+                       k = 0;
+                       for_each_rx_queue(bp, i) {
+                               for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
+                                       sprintf(buf + (k + j)*ETH_GSTRING_LEN,
+                                               bnx2x_q_stats_arr[j].string, i);
+                               k += BNX2X_NUM_Q_STATS;
+                       }
+                       if (IS_E1HMF_MODE_STAT(bp))
+                               break;
+                       for (j = 0; j < BNX2X_NUM_STATS; j++)
+                               strcpy(buf + (k + j)*ETH_GSTRING_LEN,
+                                      bnx2x_stats_arr[j].string);
+               } else {
+                       for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
+                               if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
+                                       continue;
+                               strcpy(buf + j*ETH_GSTRING_LEN,
+                                      bnx2x_stats_arr[i].string);
+                               j++;
+                       }
+               }
+               break;
+
+       case ETH_SS_TEST:
+               memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
+               break;
+       }
+}
+
+static int bnx2x_get_stats_count(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int i, num_stats;
+
+       if (is_multi(bp)) {
+               num_stats = BNX2X_NUM_Q_STATS * bp->num_rx_queues;
+               if (!IS_E1HMF_MODE_STAT(bp))
+                       num_stats += BNX2X_NUM_STATS;
+       } else {
+               if (IS_E1HMF_MODE_STAT(bp)) {
+                       num_stats = 0;
+                       for (i = 0; i < BNX2X_NUM_STATS; i++)
+                               if (IS_FUNC_STAT(i))
+                                       num_stats++;
+               } else
+                       num_stats = BNX2X_NUM_STATS;
+       }
+
+       return num_stats;
+}
+
+static void bnx2x_get_ethtool_stats(struct net_device *dev,
+                                   struct ethtool_stats *stats, u64 *buf)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       u32 *hw_stats, *offset;
+       int i, j, k;
+
+       if (is_multi(bp)) {
+               k = 0;
+               for_each_rx_queue(bp, i) {
+                       hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
+                       for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
+                               if (bnx2x_q_stats_arr[j].size == 0) {
+                                       /* skip this counter */
+                                       buf[k + j] = 0;
+                                       continue;
+                               }
+                               offset = (hw_stats +
+                                         bnx2x_q_stats_arr[j].offset);
+                               if (bnx2x_q_stats_arr[j].size == 4) {
+                                       /* 4-byte counter */
+                                       buf[k + j] = (u64) *offset;
+                                       continue;
+                               }
+                               /* 8-byte counter */
+                               buf[k + j] = HILO_U64(*offset, *(offset + 1));
+                       }
+                       k += BNX2X_NUM_Q_STATS;
+               }
+               if (IS_E1HMF_MODE_STAT(bp))
+                       return;
+               hw_stats = (u32 *)&bp->eth_stats;
+               for (j = 0; j < BNX2X_NUM_STATS; j++) {
+                       if (bnx2x_stats_arr[j].size == 0) {
+                               /* skip this counter */
+                               buf[k + j] = 0;
+                               continue;
+                       }
+                       offset = (hw_stats + bnx2x_stats_arr[j].offset);
+                       if (bnx2x_stats_arr[j].size == 4) {
+                               /* 4-byte counter */
+                               buf[k + j] = (u64) *offset;
+                               continue;
+                       }
+                       /* 8-byte counter */
+                       buf[k + j] = HILO_U64(*offset, *(offset + 1));
+               }
+       } else {
+               hw_stats = (u32 *)&bp->eth_stats;
+               for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
+                       if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
+                               continue;
+                       if (bnx2x_stats_arr[i].size == 0) {
+                               /* skip this counter */
+                               buf[j] = 0;
+                               j++;
+                               continue;
+                       }
+                       offset = (hw_stats + bnx2x_stats_arr[i].offset);
+                       if (bnx2x_stats_arr[i].size == 4) {
+                               /* 4-byte counter */
+                               buf[j] = (u64) *offset;
+                               j++;
+                               continue;
+                       }
+                       /* 8-byte counter */
+                       buf[j] = HILO_U64(*offset, *(offset + 1));
+                       j++;
+               }
+       }
+}
+
+static int bnx2x_phys_id(struct net_device *dev, u32 data)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int port = BP_PORT(bp);
+       int i;
+
+       if (!netif_running(dev))
+               return 0;
+
+       if (!bp->port.pmf)
+               return 0;
+
+       if (data == 0)
+               data = 2;
+
+       for (i = 0; i < (data * 2); i++) {
+               if ((i % 2) == 0)
+                       bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
+                                     bp->link_params.hw_led_mode,
+                                     bp->link_params.chip_id);
+               else
+                       bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
+                                     bp->link_params.hw_led_mode,
+                                     bp->link_params.chip_id);
+
+               msleep_interruptible(500);
+               if (signal_pending(current))
+                       break;
+       }
+
+       if (bp->link_vars.link_up)
+               bnx2x_set_led(bp, port, LED_MODE_OPER,
+                             bp->link_vars.line_speed,
+                             bp->link_params.hw_led_mode,
+                             bp->link_params.chip_id);
+
+       return 0;
+}
+
+static struct ethtool_ops bnx2x_ethtool_ops = {
+       .get_settings           = bnx2x_get_settings,
+       .set_settings           = bnx2x_set_settings,
+       .get_drvinfo            = bnx2x_get_drvinfo,
+       .get_regs_len           = bnx2x_get_regs_len,
+       .get_regs               = bnx2x_get_regs,
+       .get_wol                = bnx2x_get_wol,
+       .set_wol                = bnx2x_set_wol,
+       .get_msglevel           = bnx2x_get_msglevel,
+       .set_msglevel           = bnx2x_set_msglevel,
+       .nway_reset             = bnx2x_nway_reset,
+       .get_link               = bnx2x_get_link,
+#if (LINUX_VERSION_CODE >= 0x020418) /* BNX2X_UPSTREAM */
+       .get_eeprom_len         = bnx2x_get_eeprom_len,
+#endif
+       .get_eeprom             = bnx2x_get_eeprom,
+       .set_eeprom             = bnx2x_set_eeprom,
+       .get_coalesce           = bnx2x_get_coalesce,
+       .set_coalesce           = bnx2x_set_coalesce,
+       .get_ringparam          = bnx2x_get_ringparam,
+       .set_ringparam          = bnx2x_set_ringparam,
+       .get_pauseparam         = bnx2x_get_pauseparam,
+       .set_pauseparam         = bnx2x_set_pauseparam,
+       .get_rx_csum            = bnx2x_get_rx_csum,
+       .set_rx_csum            = bnx2x_set_rx_csum,
+       .get_tx_csum            = ethtool_op_get_tx_csum,
+#if (LINUX_VERSION_CODE >= 0x020618) /* BNX2X_UPSTREAM */
+       .set_tx_csum            = ethtool_op_set_tx_hw_csum,
+#else
+       .set_tx_csum            = bnx2x_set_tx_hw_csum,
+#endif
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+       .set_flags              = bnx2x_set_flags,
+       .get_flags              = ethtool_op_get_flags,
+#endif
+       .get_sg                 = ethtool_op_get_sg,
+       .set_sg                 = ethtool_op_set_sg,
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+       .get_tso                = ethtool_op_get_tso,
+       .set_tso                = bnx2x_set_tso,
+#endif
+       .self_test_count        = bnx2x_self_test_count,
+       .self_test              = bnx2x_self_test,
+       .get_strings            = bnx2x_get_strings,
+       .phys_id                = bnx2x_phys_id,
+       .get_stats_count        = bnx2x_get_stats_count,
+       .get_ethtool_stats      = bnx2x_get_ethtool_stats,
+#ifdef ETHTOOL_GPERMADDR /* ! BNX2X_UPSTREAM */
+#if (LINUX_VERSION_CODE < 0x020617)
+       .get_perm_addr          = ethtool_op_get_perm_addr
+#endif
+#endif
+};
+
+/* end of ethtool_ops */
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
+{
+       u16 pmcsr;
+
+       pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
+
+       switch (state) {
+       case PCI_D0:
+               pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+                                     ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
+                                      PCI_PM_CTRL_PME_STATUS));
+
+               if (pmcsr & PCI_PM_CTRL_STATE_MASK)
+                       /* delay required during transition out of D3hot */
+                       msleep(20);
+               break;
+
+       case PCI_D3hot:
+               pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
+               pmcsr |= 3;
+
+               if (bp->wol)
+                       pmcsr |= PCI_PM_CTRL_PME_ENABLE;
+
+               pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+                                     pmcsr);
+
+               /* No more memory access after this point until
+               * device is brought back to D0.
+               */
+               break;
+
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
+{
+       u16 rx_cons_sb;
+
+       /* Tell compiler that status block fields can change */
+       barrier();
+       rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
+       if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
+               rx_cons_sb++;
+       return (fp->rx_comp_cons != rx_cons_sb);
+}
+
+/*
+ * net_device service functions
+ */
+
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+static int bnx2x_poll(struct napi_struct *napi, int budget)
+#else
+static int bnx2x_poll(struct net_device *dev, int *budget)
+#endif
+{
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
+                                                napi);
+       struct bnx2x *bp = fp->bp;
+       int work_done = 0;
+#else
+       struct bnx2x *bp = netdev_priv(dev);
+       struct bnx2x_fastpath *fp = &bp->fp[0];
+       int orig_budget = min(*budget, dev->quota);
+       int work_done;
+#endif
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               goto poll_panic;
+#endif
+
+       prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
+       prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
+
+       bnx2x_update_fpsb_idx(fp);
+
+       if (bnx2x_has_rx_work(fp)) {
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+               work_done = bnx2x_rx_int(fp, budget);
+
+               /* must not complete if we consumed full budget */
+               if (work_done >= budget)
+                       goto poll_again;
+#else
+               work_done = bnx2x_rx_int(fp, orig_budget);
+
+               *budget -= work_done;
+               dev->quota -= work_done;
+               if (dev->quota <= 0)
+                       goto poll_again;
+#endif
+       }
+
+       /* bnx2x_has_rx_work() reads the status block, thus we need to
+        * ensure that status block indices have been actually read
+        * (bnx2x_update_fpsb_idx) prior to this check (bnx2x_has_rx_work)
+        * so that we won't write the "newer" value of the status block to IGU
+        * (if there was a DMA right after bnx2x_has_rx_work and
+        * if there is no rmb, the memory reading (bnx2x_update_fpsb_idx)
+        * may be postponed to right before bnx2x_ack_sb). In this case
+        * there will never be another interrupt until there is another update
+        * of the status block, while there is still unhandled work.
+        */
+       rmb();
+
+       if (!bnx2x_has_rx_work(fp)) {
+#ifdef BNX2X_STOP_ON_ERROR
+poll_panic:
+#endif
+               napi_complete(napi);
+
+               bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
+                            le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
+               bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
+                            le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
+#ifndef BNX2X_NEW_NAPI /* ! BNX2X_UPSTREAM */
+               return 0;
+#endif
+       }
+
+poll_again:
+#ifdef BNX2X_NEW_NAPI /* BNX2X_UPSTREAM */
+       return work_done;
+#else
+       return 1;
+#endif
+}
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+static struct net_device_stats *bnx2x_get_stats(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       return &bp->net_stats;
+}
+#endif
+
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+/* we split the first BD into headers and data BDs
+ * to ease the pain of our fellow microcode engineers
+ * we use one mapping for both BDs
+ * So far this has only been observed to happen
+ * in Other Operating Systems(TM)
+ */
+static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
+                                  struct bnx2x_fastpath *fp,
+                                  struct sw_tx_bd *tx_buf,
+                                  struct eth_tx_start_bd **tx_bd, u16 hlen,
+                                  u16 bd_prod, int nbd)
+{
+       struct eth_tx_start_bd *h_tx_bd = *tx_bd;
+       struct eth_tx_bd *d_tx_bd;
+       dma_addr_t mapping;
+       int old_len = le16_to_cpu(h_tx_bd->nbytes);
+
+       /* first fix first BD */
+       h_tx_bd->nbd = cpu_to_le16(nbd);
+       h_tx_bd->nbytes = cpu_to_le16(hlen);
+
+       DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d "
+          "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
+          h_tx_bd->addr_lo, h_tx_bd->nbd);
+
+       /* now get a new data BD
+        * (after the pbd) and fill it */
+       bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+       d_tx_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
+
+       mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
+                          le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
+
+       d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+       d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+       d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
+
+       /* this marks the BD as one that has no individual mapping */
+       tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
+
+       DP(NETIF_MSG_TX_QUEUED,
+          "TSO split data size is %d (%x:%x)\n",
+          d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
+
+       /* update tx_bd */
+       *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
+
+       return bd_prod;
+}
+#endif
+
+static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
+{
+       if (fix > 0)
+               csum = (u16) ~csum_fold(csum_sub(csum,
+                               csum_partial(t_header - fix, fix, 0)));
+
+       else if (fix < 0)
+               csum = (u16) ~csum_fold(csum_add(csum,
+                               csum_partial(t_header, -fix, 0)));
+
+       return swab16(csum);
+}
+
+static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
+{
+       u32 rc;
+
+       if (skb->ip_summed != CHECKSUM_PARTIAL)
+               rc = XMIT_PLAIN;
+
+       else {
+               if (skb->protocol == htons(ETH_P_IPV6)) {
+                       rc = XMIT_CSUM_V6;
+                       if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
+                               rc |= XMIT_CSUM_TCP;
+
+               } else {
+                       rc = XMIT_CSUM_V4;
+                       if (ip_hdr(skb)->protocol == IPPROTO_TCP)
+                               rc |= XMIT_CSUM_TCP;
+               }
+       }
+
+#ifdef NETIF_F_GSO /* BNX2X_UPSTREAM */
+       if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
+               rc |= XMIT_GSO_V4;
+
+#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */
+       else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
+               rc |= XMIT_GSO_V6;
+#endif
+#elif defined(NETIF_F_TSO) /* ! BNX2X_UPSTREAM */
+       if ((skb_shinfo(skb)->gso_size) &&
+           (skb->len > (bp->dev->mtu + ETH_HLEN)))
+               rc |= XMIT_GSO_V4;
+#endif
+
+       return rc;
+}
+
+#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
+/* check if packet requires linearization (packet is too fragmented)
+   no need to check fragmentation if page size > 8K (there will be no
+   violation to FW restrictions) */
+static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
+                            u32 xmit_type)
+{
+       int to_copy = 0;
+       int hlen = 0;
+       int first_bd_sz = 0;
+
+       /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
+       if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
+
+               if (xmit_type & XMIT_GSO) {
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+                       unsigned short lso_mss = skb_shinfo(skb)->gso_size;
+                       /* Check if LSO packet needs to be copied:
+                          3 = 1 (for headers BD) + 2 (for PBD and last BD) */
+                       int wnd_size = MAX_FETCH_BD - 3;
+                       /* Number of windows to check */
+                       int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
+                       int wnd_idx = 0;
+                       int frag_idx = 0;
+                       u32 wnd_sum = 0;
+
+                       /* Headers length */
+                       hlen = (int)(skb_transport_header(skb) - skb->data) +
+                               tcp_hdrlen(skb);
+
+                       /* Amount of data (w/o headers) on linear part of SKB*/
+                       first_bd_sz = skb_headlen(skb) - hlen;
+
+                       wnd_sum  = first_bd_sz;
+
+                       /* Calculate the first sum - it's special */
+                       for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
+                               wnd_sum +=
+                                       skb_shinfo(skb)->frags[frag_idx].size;
+
+                       /* If there was data on linear skb data - check it */
+                       if (first_bd_sz > 0) {
+                               if (unlikely(wnd_sum < lso_mss)) {
+                                       to_copy = 1;
+                                       goto exit_lbl;
+                               }
+
+                               wnd_sum -= first_bd_sz;
+                       }
+
+                       /* Others are easier: run through the frag list and
+                          check all windows */
+                       for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
+                               wnd_sum +=
+                         skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;
+
+                               if (unlikely(wnd_sum < lso_mss)) {
+                                       to_copy = 1;
+                                       break;
+                               }
+                               wnd_sum -=
+                                       skb_shinfo(skb)->frags[wnd_idx].size;
+                       }
+#endif
+               } else {
+                       /* in non-LSO too fragmented packet should always
+                          be linearized */
+                       to_copy = 1;
+               }
+       }
+
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+exit_lbl:
+#endif
+       if (unlikely(to_copy))
+               DP(NETIF_MSG_TX_QUEUED,
+                  "Linearization IS REQUIRED for %s packet. "
+                  "num_frags %d  hlen %d  first_bd_sz %d\n",
+                  (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
+                  skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
+
+       return to_copy;
+}
+#endif
+
+#ifdef BNX2X_SAFC /* ! BNX2X_UPSTREAM */
+static u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int i, fp_index = 0;
+
+       /* Determine which tx ring we will be placed on */
+       switch (bp->multi_mode) {
+       case ETH_RSS_MODE_VLAN_PRI:
+       case ETH_RSS_MODE_E1HOV_PRI:
+#ifdef BCM_VLAN
+               if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) {
+                       i = ((vlan_tx_tag_get(skb) >> 13) & 0x7);
+                       fp_index = bp->cos_map[bp->pri_map[i]];
+               }
+#endif
+               break;
+
+       case ETH_RSS_MODE_IP_DSCP:
+               if (skb->protocol == htons(ETH_P_IP)) {
+                       i = ((ip_hdr(skb)->tos >> 2) & 0x7);
+                       fp_index = bp->cos_map[bp->pri_map[i]];
+               }
+               break;
+       }
+
+       return fp_index;
+}
+#endif
+
+/* called with netif_tx_lock
+ * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
+ * netif_wake_queue()
+ */
+static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       struct bnx2x_fastpath *fp, *fp_stat;
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       struct netdev_queue *txq;
+#endif
+       struct sw_tx_bd *tx_buf;
+       struct eth_tx_start_bd *tx_start_bd;
+       struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
+       struct eth_tx_parse_bd *pbd = NULL;
+       u16 pkt_prod, bd_prod;
+       int nbd, fp_index;
+       dma_addr_t mapping;
+       u32 xmit_type = bnx2x_xmit_type(bp, skb);
+       int i;
+       u8 hlen = 0;
+       __le16 pkt_size = 0;
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return NETDEV_TX_BUSY;
+#endif
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__)
+       VMK_ASSERT(skb->queue_mapping < BNX2X_NUM_QUEUES(bp));
+       fp_index = skb->queue_mapping;
+       txq = netdev_get_tx_queue(dev, fp_index);
+#else /* BNX2X_UPSTREAM */
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       fp_index = skb_get_queue_mapping(skb);
+       txq = netdev_get_tx_queue(dev, fp_index);
+#else
+       fp_index = 0;
+#endif
+#endif
+
+       fp = &bp->fp[fp_index + bp->num_rx_queues];
+       fp_stat = &bp->fp[fp_index];
+
+       if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) {
+               fp_stat->eth_q_stats.driver_xoff++;
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+               netif_tx_stop_queue(txq);
+#else
+               netif_stop_queue(dev);
+#endif
+               BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
+               return NETDEV_TX_BUSY;
+       }
+
+#ifdef NETIF_F_GSO /* BNX2X_UPSTREAM */
+       DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x  protocol %x  protocol(%x,%x)"
+          "  gso type %x  xmit_type %x\n",
+          skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
+          ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
+#endif
+
+#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
+       /* First, check if we need to linearize the skb (due to FW
+          restrictions). No need to check fragmentation if page size > 8K
+          (there will be no violation to FW restrictions) */
+       if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
+               /* Statistics of linearization */
+               bp->lin_cnt++;
+#if (LINUX_VERSION_CODE > 0x020611) || defined(SLE_VERSION_CODE) /* BNX2X_UPSTREAM */
+               if (skb_linearize(skb) != 0) {
+#else
+               if (skb_linearize(skb, GFP_ATOMIC) != 0) {
+#endif
+                       DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
+                          "silently dropping this SKB\n");
+                       dev_kfree_skb_any(skb);
+                       return NETDEV_TX_OK;
+               }
+       }
+#endif
+
+       /*
+       Please read carefully. First we use one BD which we mark as start,
+       then we have a parsing info BD (used for TSO or xsum),
+       and only then we have the rest of the TSO BDs.
+       (don't forget to mark the last one as last,
+       and to unmap only AFTER you write to the BD ...)
+       And above all, all pdb sizes are in words - NOT DWORDS!
+       */
+
+       pkt_prod = fp->tx_pkt_prod++;
+       bd_prod = TX_BD(fp->tx_bd_prod);
+
+       /* get a tx_buf and first BD */
+       tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
+       tx_start_bd = &fp->tx_desc_ring[bd_prod].start_bd;
+
+       tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+       tx_start_bd->general_data = (UNICAST_ADDRESS <<
+                                    ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
+       /* header nbd */
+       tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
+
+       /* remember the first BD of the packet */
+       tx_buf->first_bd = fp->tx_bd_prod;
+       tx_buf->skb = skb;
+       tx_buf->flags = 0;
+
+       DP(NETIF_MSG_TX_QUEUED,
+          "sending pkt %u @%p  next_idx %u  bd %u @%p\n",
+          pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
+
+#ifdef BCM_VLAN
+       if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb) &&
+           (bp->flags & HW_VLAN_TX_FLAG)) {
+               tx_start_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
+               tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
+       } else
+#endif
+               tx_start_bd->vlan = cpu_to_le16(pkt_prod);
+
+       /* turn on parsing and get a BD */
+       bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+       pbd = &fp->tx_desc_ring[bd_prod].parse_bd;
+
+       memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
+
+       if (xmit_type & XMIT_CSUM) {
+               hlen = (skb_network_header(skb) - skb->data) / 2;
+
+               /* for now NS flag is not used in Linux */
+               pbd->global_data =
+                       (hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
+                                ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
+
+               pbd->ip_hlen = (skb_transport_header(skb) -
+                               skb_network_header(skb)) / 2;
+
+               hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
+
+               pbd->total_hlen = cpu_to_le16(hlen);
+               hlen = hlen*2;
+
+               tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
+
+               if (xmit_type & XMIT_CSUM_V4)
+                       tx_start_bd->bd_flags.as_bitfield |=
+                                               ETH_TX_BD_FLAGS_IP_CSUM;
+               else
+                       tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
+
+               if (xmit_type & XMIT_CSUM_TCP) {
+                       pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
+
+               } else {
+                       s8 fix = SKB_CS_OFF(skb); /* signed! */
+
+                       pbd->global_data |= ETH_TX_PARSE_BD_UDP_CS_FLG;
+
+                       DP(NETIF_MSG_TX_QUEUED,
+                          "hlen %d  fix %d  csum before fix %x\n",
+                          le16_to_cpu(pbd->total_hlen), fix, SKB_CS(skb));
+
+                       /* HW bug: fixup the CSUM */
+                       pbd->tcp_pseudo_csum =
+                               bnx2x_csum_fix(skb_transport_header(skb),
+                                              SKB_CS(skb), fix);
+
+                       DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
+                          pbd->tcp_pseudo_csum);
+               }
+       }
+
+       mapping = pci_map_single(bp->pdev, skb->data,
+                                skb_headlen(skb), PCI_DMA_TODEVICE);
+
+       tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+       tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+       nbd = skb_shinfo(skb)->nr_frags + 2; /* start_bd + pbd + frags */
+       tx_start_bd->nbd = cpu_to_le16(nbd);
+       tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
+       pkt_size = tx_start_bd->nbytes;
+
+       DP(NETIF_MSG_TX_QUEUED, "first bd @%p  addr (%x:%x)  nbd %d"
+          "  nbytes %d  flags %x  vlan %x\n",
+          tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
+          le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
+          tx_start_bd->bd_flags.as_bitfield, le16_to_cpu(tx_start_bd->vlan));
+
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+       if (xmit_type & XMIT_GSO) {
+
+               DP(NETIF_MSG_TX_QUEUED,
+                  "TSO packet len %d  hlen %d  total len %d  tso size %d\n",
+                  skb->len, hlen, skb_headlen(skb),
+                  skb_shinfo(skb)->gso_size);
+
+               tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
+
+               if (unlikely(skb_headlen(skb) > hlen))
+                       bd_prod = bnx2x_tx_split(bp, fp, tx_buf, &tx_start_bd,
+                                                hlen, bd_prod, ++nbd);
+
+               pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
+               pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
+               pbd->tcp_flags = pbd_tcp_flags(skb);
+
+               if (xmit_type & XMIT_GSO_V4) {
+                       pbd->ip_id = swab16(ip_hdr(skb)->id);
+                       pbd->tcp_pseudo_csum =
+                               swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
+                                                         ip_hdr(skb)->daddr,
+                                                         0, IPPROTO_TCP, 0));
+
+               } else
+                       pbd->tcp_pseudo_csum =
+                               swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
+                                                       &ipv6_hdr(skb)->daddr,
+                                                       0, IPPROTO_TCP, 0));
+
+               pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
+       }
+#endif
+       tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
+
+       for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+               bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+               tx_data_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
+               if (total_pkt_bd == NULL)
+                       total_pkt_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
+
+               mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
+                                      frag->size, PCI_DMA_TODEVICE);
+
+               tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+               tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+               tx_data_bd->nbytes = cpu_to_le16(frag->size);
+               le16_add_cpu(&pkt_size, frag->size);
+
+               DP(NETIF_MSG_TX_QUEUED,
+                  "frag %d  bd @%p  addr (%x:%x)  nbytes %d\n",
+                  i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
+                  le16_to_cpu(tx_data_bd->nbytes));
+       }
+
+       DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
+
+       bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+
+       /* now send a tx doorbell, counting the next BD
+        * if the packet contains or ends with it
+        */
+       if (TX_BD_POFF(bd_prod) < nbd)
+               nbd++;
+
+       if (total_pkt_bd != NULL)
+               total_pkt_bd->total_pkt_bytes = pkt_size;
+
+       if (pbd)
+               DP(NETIF_MSG_TX_QUEUED,
+                  "PBD @%p  ip_data %x  ip_hlen %u  ip_id %u  lso_mss %u"
+                  "  tcp_flags %x  xsum %x  seq %u  hlen %u\n",
+                  pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
+                  pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
+                  pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
+
+       DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d  bd %u\n", nbd, bd_prod);
+
+       /*
+        * Make sure that the BD data is updated before updating the producer
+        * since FW might read the BD right after the producer is updated.
+        * This is only applicable for weak-ordered memory model archs such
+        * as IA-64. The following barrier is also mandatory since FW will
+        * assumes packets must have BDs.
+        */
+       wmb();
+
+       fp->tx_db.data.prod += nbd;
+       barrier();
+       DOORBELL(bp, fp->index - bp->num_rx_queues, fp->tx_db.raw);
+
+       mmiowb();
+
+       fp->tx_bd_prod += nbd;
+#if (LINUX_VERSION_CODE < 0x02061f) /* ! BNX2X_UPSTREAM */
+       /* In kernels starting from 2.6.31 netdev layer does this */
+       dev->trans_start = jiffies;
+#endif
+
+       if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+               netif_tx_stop_queue(txq);
+#else
+               netif_stop_queue(dev);
+#endif
+               /* We want bnx2x_tx_int to "see" the updated tx_bd_prod
+                  if we put Tx into XOFF state. */
+               smp_mb();
+               fp_stat->eth_q_stats.driver_xoff++;
+               if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+                       netif_tx_wake_queue(txq);
+#else
+                       netif_wake_queue(dev);
+#endif
+       }
+       fp_stat->tx_pkt++;
+
+       return NETDEV_TX_OK;
+}
+
+/* called with rtnl_lock */
+static int bnx2x_open(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       netif_carrier_off(dev);
+
+       bnx2x_set_power_state(bp, PCI_D0);
+
+       return bnx2x_nic_load(bp, LOAD_OPEN);
+}
+
+/* called with rtnl_lock */
+static int bnx2x_close(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       /* Unload the driver, release IRQs */
+       bnx2x_nic_unload(bp, UNLOAD_CLOSE);
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       if (atomic_read(&bp->pdev->enable_cnt) == 1)
+#endif
+               if (!CHIP_REV_IS_SLOW(bp))
+                       bnx2x_set_power_state(bp, PCI_D3hot);
+
+       return 0;
+}
+
+/* called with netif_tx_lock from dev_mcast.c */
+static void bnx2x_set_rx_mode(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       u32 rx_mode = BNX2X_RX_MODE_NORMAL;
+       int port = BP_PORT(bp);
+
+       if (bp->state != BNX2X_STATE_OPEN) {
+               DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
+               return;
+       }
+
+       DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
+
+       if (dev->flags & IFF_PROMISC)
+               rx_mode = BNX2X_RX_MODE_PROMISC;
+
+       else if ((dev->flags & IFF_ALLMULTI) ||
+                ((dev->mc_count > BNX2X_MAX_MULTICAST) && CHIP_IS_E1(bp)))
+               rx_mode = BNX2X_RX_MODE_ALLMULTI;
+
+       else { /* some multicasts */
+               if (CHIP_IS_E1(bp)) {
+                       int i, old, offset;
+                       struct dev_mc_list *mclist;
+                       struct mac_configuration_cmd *config =
+                                               bnx2x_sp(bp, mcast_config);
+
+                       for (i = 0, mclist = dev->mc_list;
+                            mclist && (i < dev->mc_count);
+                            i++, mclist = mclist->next) {
+
+                               config->config_table[i].
+                                       cam_entry.msb_mac_addr =
+                                       swab16(*(u16 *)&mclist->dmi_addr[0]);
+                               config->config_table[i].
+                                       cam_entry.middle_mac_addr =
+                                       swab16(*(u16 *)&mclist->dmi_addr[2]);
+                               config->config_table[i].
+                                       cam_entry.lsb_mac_addr =
+                                       swab16(*(u16 *)&mclist->dmi_addr[4]);
+                               config->config_table[i].cam_entry.flags =
+                                                       cpu_to_le16(port);
+                               config->config_table[i].
+                                       target_table_entry.flags = 0;
+                               config->config_table[i].target_table_entry.
+                                       clients_bit_vector =
+                                               cpu_to_le32(1 << BP_L_ID(bp));
+                               config->config_table[i].
+                                       target_table_entry.vlan_id = 0;
+
+                               DP(NETIF_MSG_IFUP,
+                                  "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
+                                  config->config_table[i].
+                                               cam_entry.msb_mac_addr,
+                                  config->config_table[i].
+                                               cam_entry.middle_mac_addr,
+                                  config->config_table[i].
+                                               cam_entry.lsb_mac_addr);
+                       }
+                       old = config->hdr.length;
+                       if (old > i) {
+                               for (; i < old; i++) {
+                                       if (CAM_IS_INVALID(config->
+                                                          config_table[i])) {
+                                               /* already invalidated */
+                                               break;
+                                       }
+                                       /* invalidate */
+                                       CAM_INVALIDATE(config->
+                                                      config_table[i]);
+                               }
+                       }
+
+                       if (CHIP_REV_IS_SLOW(bp))
+                               offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
+                       else
+                               offset = BNX2X_MAX_MULTICAST*(1 + port);
+
+                       config->hdr.length = i;
+                       config->hdr.offset = offset;
+                       config->hdr.client_id = bp->fp->cl_id;
+                       config->hdr.reserved1 = 0;
+
+                       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                                  U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
+                                  U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
+                                     0);
+               } else { /* E1H */
+                       /* Accept one or more multicasts */
+                       struct dev_mc_list *mclist;
+                       u32 mc_filter[MC_HASH_SIZE];
+                       u32 crc, bit, regidx;
+                       int i;
+
+                       memset(mc_filter, 0, 4 * MC_HASH_SIZE);
+
+                       for (i = 0, mclist = dev->mc_list;
+                            mclist && (i < dev->mc_count);
+                            i++, mclist = mclist->next) {
+
+#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+                               DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
+                                  mclist->dmi_addr);
+#else
+                               DP(NETIF_MSG_IFUP, "Adding mcast MAC: "
+                                  "%02x:%02x:%02x:%02x:%02x:%02x\n",
+                                  mclist->dmi_addr[0], mclist->dmi_addr[1],
+                                  mclist->dmi_addr[2], mclist->dmi_addr[3],
+                                  mclist->dmi_addr[4], mclist->dmi_addr[5]);
+#endif
+
+                               crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
+                               bit = (crc >> 24) & 0xff;
+                               regidx = bit >> 5;
+                               bit &= 0x1f;
+                               mc_filter[regidx] |= (1 << bit);
+                       }
+
+                       for (i = 0; i < MC_HASH_SIZE; i++)
+                               REG_WR(bp, MC_HASH_OFFSET(bp, i),
+                                      mc_filter[i]);
+               }
+       }
+
+       bp->rx_mode = rx_mode;
+       bnx2x_set_storm_rx_mode(bp);
+}
+
+/* called with rtnl_lock */
+static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
+{
+       struct sockaddr *addr = p;
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
+               return -EINVAL;
+
+       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+       if (netif_running(dev)) {
+               if (CHIP_IS_E1(bp))
+                       bnx2x_set_mac_addr_e1(bp, 1);
+               else
+                       bnx2x_set_mac_addr_e1h(bp, 1);
+       }
+
+       return 0;
+}
+
+/* called with rtnl_lock */
+static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
+                          int devad, u16 addr)
+{
+       struct bnx2x *bp = netdev_priv(netdev);
+       u16 value;
+       int rc;
+       u32 phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+
+       DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
+          prtad, devad, addr);
+
+       if (prtad != bp->mdio.prtad) {
+               DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
+                  prtad, bp->mdio.prtad);
+               return -EINVAL;
+       }
+
+       /* The HW expects different devad if CL22 is used */
+       devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
+
+       bnx2x_acquire_phy_lock(bp);
+       rc = bnx2x_cl45_read(bp, BP_PORT(bp), phy_type, prtad,
+                            devad, addr, &value);
+       bnx2x_release_phy_lock(bp);
+       DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
+
+       if (!rc)
+               rc = value;
+       return rc;
+}
+
+/* called with rtnl_lock */
+static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
+                           u16 addr, u16 value)
+{
+       struct bnx2x *bp = netdev_priv(netdev);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
+       int rc;
+
+       DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
+                          " value 0x%x\n", prtad, devad, addr, value);
+
+       if (prtad != bp->mdio.prtad) {
+               DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
+                  prtad, bp->mdio.prtad);
+               return -EINVAL;
+       }
+
+       /* The HW expects different devad if CL22 is used */
+       devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
+
+       bnx2x_acquire_phy_lock(bp);
+       rc = bnx2x_cl45_write(bp, BP_PORT(bp), ext_phy_type, prtad,
+                             devad, addr, value);
+       bnx2x_release_phy_lock(bp);
+       return rc;
+}
+
+/* called with rtnl_lock */
+static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       struct mii_ioctl_data *mdio = if_mii(ifr);
+
+       DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
+          mdio->phy_id, mdio->reg_num, mdio->val_in);
+
+       if (!netif_running(dev))
+               return -EAGAIN;
+
+       return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
+}
+
+/* called with rtnl_lock */
+static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int rc = 0;
+
+       if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
+           ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
+               return -EINVAL;
+
+       /* This does not race with packet allocation
+        * because the actual alloc size is
+        * only updated as part of load
+        */
+       dev->mtu = new_mtu;
+
+       if (netif_running(dev)) {
+               bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+               rc = bnx2x_nic_load(bp, LOAD_NORMAL);
+       }
+
+       return rc;
+}
+
+static void bnx2x_tx_timeout(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (!bp->panic)
+               bnx2x_panic();
+#endif
+       /* This allows the netif to be shutdown gracefully before resetting */
+       schedule_work(&bp->reset_task);
+}
+
+#ifdef BCM_VLAN
+/* called with rtnl_lock */
+static void bnx2x_vlan_rx_register(struct net_device *dev,
+                                  struct vlan_group *vlgrp)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       bp->vlgrp = vlgrp;
+
+       /* Set flags according to the required capabilities */
+       bp->flags &= ~(HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
+
+       if (dev->features & NETIF_F_HW_VLAN_TX)
+               bp->flags |= HW_VLAN_TX_FLAG;
+
+       if (dev->features & NETIF_F_HW_VLAN_RX)
+               bp->flags |= HW_VLAN_RX_FLAG;
+
+       if (netif_running(dev))
+               bnx2x_set_client_config(bp);
+}
+
+#if (LINUX_VERSION_CODE < 0x020616) /* ! BNX2X_UPSTREAM */
+static void bnx2x_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       if (bp->vlgrp)
+               vlan_group_set_device(bp->vlgrp, vid, NULL);
+}
+#endif
+#endif
+
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+static void poll_bnx2x(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       disable_irq(bp->pdev->irq);
+#if (LINUX_VERSION_CODE < 0x020613) && (VMWARE_ESX_DDK_VERSION < 40000)
+       bnx2x_interrupt(bp->pdev->irq, dev, NULL);
+#else /* BNX2X_UPSTREAM */
+       bnx2x_interrupt(bp->pdev->irq, dev);
+#endif
+       enable_irq(bp->pdev->irq);
+}
+#endif
+
+#if (LINUX_VERSION_CODE >= 0x02061e) /* BNX2X_UPSTREAM */
+static const struct net_device_ops bnx2x_netdev_ops = {
+       .ndo_open               = bnx2x_open,
+       .ndo_stop               = bnx2x_close,
+       .ndo_start_xmit         = bnx2x_start_xmit,
+       .ndo_set_multicast_list = bnx2x_set_rx_mode,
+       .ndo_set_mac_address    = bnx2x_change_mac_addr,
+       .ndo_validate_addr      = eth_validate_addr,
+       .ndo_do_ioctl           = bnx2x_ioctl,
+       .ndo_change_mtu         = bnx2x_change_mtu,
+       .ndo_tx_timeout         = bnx2x_tx_timeout,
+#ifdef BCM_VLAN
+       .ndo_vlan_rx_register   = bnx2x_vlan_rx_register,
+#endif
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+       .ndo_poll_controller    = poll_bnx2x,
+#endif
+};
+#endif
+
+static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
+                                   struct net_device *dev)
+{
+       struct bnx2x *bp;
+       int rc;
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       SET_MODULE_OWNER(dev);
+#endif
+#if (LINUX_VERSION_CODE >= 0x020419) /* BNX2X_UPSTREAM */
+       SET_NETDEV_DEV(dev, &pdev->dev);
+#endif
+       bp = netdev_priv(dev);
+
+       bp->dev = dev;
+       bp->pdev = pdev;
+       bp->flags = 0;
+       bp->func = PCI_FUNC(pdev->devfn);
+
+       rc = pci_enable_device(pdev);
+       if (rc) {
+               printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
+               goto err_out;
+       }
+
+       if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+               printk(KERN_ERR PFX "Cannot find PCI device base address,"
+                      " aborting\n");
+               rc = -ENODEV;
+               goto err_out_disable;
+       }
+
+       if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
+               printk(KERN_ERR PFX "Cannot find second PCI device"
+                      " base address, aborting\n");
+               rc = -ENODEV;
+               goto err_out_disable;
+       }
+
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       if (atomic_read(&pdev->enable_cnt) == 1) {
+#endif
+               rc = pci_request_regions(pdev, DRV_MODULE_NAME);
+               if (rc) {
+                       printk(KERN_ERR PFX "Cannot obtain PCI resources,"
+                              " aborting\n");
+                       goto err_out_disable;
+               }
+
+               pci_set_master(pdev);
+#if (LINUX_VERSION_CODE >= 0x02060b) /* BNX2X_UPSTREAM */
+               pci_save_state(pdev);
+#else
+               pci_save_state(pdev, bp->pci_state);
+#endif
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       }
+#endif
+
+       bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+       if (bp->pm_cap == 0) {
+               printk(KERN_ERR PFX "Cannot find power management"
+                      " capability, aborting\n");
+               rc = -EIO;
+               goto err_out_release;
+       }
+
+       bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+       if (bp->pcie_cap == 0) {
+               printk(KERN_ERR PFX "Cannot find PCI Express capability,"
+                      " aborting\n");
+               rc = -EIO;
+               goto err_out_release;
+       }
+
+       if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
+               bp->flags |= USING_DAC_FLAG;
+               if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
+                       printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
+                              " failed, aborting\n");
+                       rc = -EIO;
+                       goto err_out_release;
+               }
+
+       } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
+               printk(KERN_ERR PFX "System does not support DMA,"
+                      " aborting\n");
+               rc = -EIO;
+               goto err_out_release;
+       }
+
+       dev->mem_start = pci_resource_start(pdev, 0);
+       dev->base_addr = dev->mem_start;
+       dev->mem_end = pci_resource_end(pdev, 0);
+
+       dev->irq = pdev->irq;
+
+#if (LINUX_VERSION_CODE >= 0x02061c) /* BNX2X_UPSTREAM */
+       bp->regview = pci_ioremap_bar(pdev, 0);
+#else
+       bp->regview = ioremap_nocache(dev->base_addr,
+                                     pci_resource_len(pdev, 0));
+#endif
+       if (!bp->regview) {
+               printk(KERN_ERR PFX "Cannot map register space, aborting\n");
+               rc = -ENOMEM;
+               goto err_out_release;
+       }
+
+       bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
+                                       min_t(u64, BNX2X_DB_SIZE,
+                                             pci_resource_len(pdev, 2)));
+       if (!bp->doorbells) {
+               printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
+               rc = -ENOMEM;
+               goto err_out_unmap;
+       }
+
+       bnx2x_set_power_state(bp, PCI_D0);
+
+       /* clean indirect addresses */
+       pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
+                              PCICFG_VENDOR_ID_OFFSET);
+       REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
+       REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
+       REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
+       REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
+
+#if (LINUX_VERSION_CODE < 0x02061e) /* ! BNX2X_UPSTREAM */
+#ifndef BNX2X_NEW_NAPI /* ! BNX2X_UPSTREAM */
+       dev->poll = bnx2x_poll;
+       dev->weight = 128*4;
+#endif
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       dev->get_stats = bnx2x_get_stats;
+#endif
+       dev->hard_start_xmit = bnx2x_start_xmit;
+#endif
+       dev->watchdog_timeo = TX_TIMEOUT;
+
+#if (LINUX_VERSION_CODE >= 0x02061e) /* BNX2X_UPSTREAM */
+       dev->netdev_ops = &bnx2x_netdev_ops;
+#endif
+       dev->ethtool_ops = &bnx2x_ethtool_ops;
+#if (LINUX_VERSION_CODE < 0x02061e) /* ! BNX2X_UPSTREAM */
+       dev->open = bnx2x_open;
+       dev->stop = bnx2x_close;
+       dev->set_multicast_list = bnx2x_set_rx_mode;
+       dev->set_mac_address = bnx2x_change_mac_addr;
+       dev->do_ioctl = bnx2x_ioctl;
+       dev->change_mtu = bnx2x_change_mtu;
+       dev->tx_timeout = bnx2x_tx_timeout;
+#ifdef BCM_VLAN
+       dev->vlan_rx_register = bnx2x_vlan_rx_register;
+#if (LINUX_VERSION_CODE < 0x020616) /* ! BNX2X_UPSTREAM */
+       dev->vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid;
+#endif
+#endif
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+       dev->poll_controller = poll_bnx2x;
+#endif
+#endif
+       dev->features |= NETIF_F_SG;
+       dev->features |= NETIF_F_HW_CSUM;
+       if (bp->flags & USING_DAC_FLAG)
+               dev->features |= NETIF_F_HIGHDMA;
+#ifdef NETIF_F_TSO /* BNX2X_UPSTREAM */
+       dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
+#endif
+#ifdef NETIF_F_TSO6 /* BNX2X_UPSTREAM */
+       dev->features |= NETIF_F_TSO6;
+#endif
+#ifdef BCM_VLAN
+       dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
+       bp->flags |= (HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
+
+#if (LINUX_VERSION_CODE >= 0x02061a) /* BNX2X_UPSTREAM */
+       dev->vlan_features |= NETIF_F_SG;
+       dev->vlan_features |= NETIF_F_HW_CSUM;
+       if (bp->flags & USING_DAC_FLAG)
+               dev->vlan_features |= NETIF_F_HIGHDMA;
+       dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
+       dev->vlan_features |= NETIF_F_TSO6;
+#endif
+#endif
+
+       /* get_port_hwinfo() will set prtad and mmds properly */
+       bp->mdio.prtad = MDIO_PRTAD_NONE;
+       bp->mdio.mmds = 0;
+       bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
+       bp->mdio.dev = dev;
+       bp->mdio.mdio_read = bnx2x_mdio_read;
+       bp->mdio.mdio_write = bnx2x_mdio_write;
+
+       return 0;
+
+err_out_unmap:
+       if (bp->regview) {
+               iounmap(bp->regview);
+               bp->regview = NULL;
+       }
+       if (bp->doorbells) {
+               iounmap(bp->doorbells);
+               bp->doorbells = NULL;
+       }
+
+err_out_release:
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       if (atomic_read(&pdev->enable_cnt) == 1)
+#endif
+               pci_release_regions(pdev);
+
+err_out_disable:
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+
+err_out:
+       return rc;
+}
+
+static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
+                                                int *width, int *speed)
+{
+       u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
+
+       *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
+
+       /* return value of 1=2.5GHz 2=5GHz */
+       *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
+}
+
+#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */
+static int __devinit bnx2x_check_firmware(struct bnx2x *bp)
+{
+       const struct firmware *firmware = bp->firmware;
+       struct bnx2x_fw_file_hdr *fw_hdr;
+       struct bnx2x_fw_file_section *sections;
+       u32 offset, len, num_ops;
+       u16 *ops_offsets;
+       int i;
+       const u8 *fw_ver;
+
+       if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
+               return -EINVAL;
+
+       fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
+       sections = (struct bnx2x_fw_file_section *)fw_hdr;
+
+       /* Make sure none of the offsets and sizes make us read beyond
+        * the end of the firmware data */
+       for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
+               offset = be32_to_cpu(sections[i].offset);
+               len = be32_to_cpu(sections[i].len);
+               if (offset + len > firmware->size) {
+                       printk(KERN_ERR PFX "Section %d length is out of "
+                                           "bounds\n", i);
+                       return -EINVAL;
+               }
+       }
+
+       /* Likewise for the init_ops offsets */
+       offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
+       ops_offsets = (u16 *)(firmware->data + offset);
+       num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
+
+       for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
+               if (be16_to_cpu(ops_offsets[i]) > num_ops) {
+                       printk(KERN_ERR PFX "Section offset %d is out of "
+                                           "bounds\n", i);
+                       return -EINVAL;
+               }
+       }
+
+       /* Check FW version */
+       offset = be32_to_cpu(fw_hdr->fw_version.offset);
+       fw_ver = firmware->data + offset;
+       if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
+           (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
+           (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
+           (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
+               printk(KERN_ERR PFX "Bad FW version:%d.%d.%d.%d."
+                                   " Should be %d.%d.%d.%d\n",
+                      fw_ver[0], fw_ver[1], fw_ver[2],
+                      fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
+                      BCM_5710_FW_MINOR_VERSION,
+                      BCM_5710_FW_REVISION_VERSION,
+                      BCM_5710_FW_ENGINEERING_VERSION);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
+{
+       const __be32 *source = (const __be32 *)_source;
+       u32 *target = (u32 *)_target;
+       u32 i;
+
+       for (i = 0; i < n/4; i++)
+               target[i] = be32_to_cpu(source[i]);
+}
+
+/*
+   Ops array is stored in the following format:
+   {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
+ */
+static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
+{
+       const __be32 *source = (const __be32 *)_source;
+       struct raw_op *target = (struct raw_op *)_target;
+       u32 i, j, tmp;
+
+       for (i = 0, j = 0; i < n/8; i++, j += 2) {
+               tmp = be32_to_cpu(source[j]);
+               target[i].op = (tmp >> 24) & 0xff;
+               target[i].offset =  tmp & 0xffffff;
+               target[i].raw_data = be32_to_cpu(source[j+1]);
+       }
+}
+
+static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
+{
+       const __be16 *source = (const __be16 *)_source;
+       u16 *target = (u16 *)_target;
+       u32 i;
+
+       for (i = 0; i < n/2; i++)
+               target[i] = be16_to_cpu(source[i]);
+}
+
+#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
+       do { \
+               u32 len = be32_to_cpu(fw_hdr->arr.len); \
+               bp->arr = kmalloc(len, GFP_KERNEL); \
+               if (!bp->arr) { \
+                       printk(KERN_ERR PFX "Failed to allocate %d bytes " \
+                                           "for "#arr"\n", len); \
+                       goto lbl; \
+               } \
+               func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
+                    (u8 *)bp->arr, len); \
+       } while (0)
+
+static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
+{
+       char fw_file_name[40] = {0};
+       struct bnx2x_fw_file_hdr *fw_hdr;
+       int rc, offset;
+
+       /* Create a FW file name */
+       if (CHIP_IS_E1(bp))
+               offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1);
+       else
+               offset = sprintf(fw_file_name, FW_FILE_PREFIX_E1H);
+
+       sprintf(fw_file_name + offset, "%d.%d.%d.%d.fw",
+               BCM_5710_FW_MAJOR_VERSION,
+               BCM_5710_FW_MINOR_VERSION,
+               BCM_5710_FW_REVISION_VERSION,
+               BCM_5710_FW_ENGINEERING_VERSION);
+
+       printk(KERN_INFO PFX "Loading %s\n", fw_file_name);
+
+       rc = request_firmware(&bp->firmware, fw_file_name, dev);
+       if (rc) {
+               printk(KERN_ERR PFX "Can't load firmware file %s\n",
+                      fw_file_name);
+               goto request_firmware_exit;
+       }
+
+       rc = bnx2x_check_firmware(bp);
+       if (rc) {
+               printk(KERN_ERR PFX "Corrupt firmware file %s\n", fw_file_name);
+               goto request_firmware_exit;
+       }
+
+       fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
+
+       /* Initialize the pointers to the init arrays */
+       /* Blob */
+       BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
+
+       /* Opcodes */
+       BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
+
+       /* Offsets */
+       BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
+                           be16_to_cpu_n);
+
+       /* STORMs firmware */
+       INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
+       INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->tsem_pram_data.offset);
+       INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->usem_int_table_data.offset);
+       INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->usem_pram_data.offset);
+       INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
+       INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->xsem_pram_data.offset);
+       INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->csem_int_table_data.offset);
+       INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
+                       be32_to_cpu(fw_hdr->csem_pram_data.offset);
+
+       return 0;
+
+init_offsets_alloc_err:
+       kfree(bp->init_ops);
+init_ops_alloc_err:
+       kfree(bp->init_data);
+request_firmware_exit:
+       release_firmware(bp->firmware);
+
+       return rc;
+}
+
+#else
+
+static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
+{
+       if (CHIP_IS_E1(bp))
+               bnx2x_init_e1_firmware(bp);
+
+       else if (CHIP_IS_E1H(bp))
+               bnx2x_init_e1h_firmware(bp);
+
+       else {
+               printk(KERN_ERR PFX "Unsupported chip revision\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+#endif
+
+static int __devinit bnx2x_init_one(struct pci_dev *pdev,
+                                   const struct pci_device_id *ent)
+{
+       struct net_device *dev = NULL;
+       struct bnx2x *bp;
+       int pcie_width, pcie_speed;
+       int rc;
+
+       /* dev zeroed in init_etherdev */
+#ifdef BNX2X_MULTI_QUEUE /* BNX2X_UPSTREAM */
+       dev = alloc_etherdev_mq(sizeof(*bp), MAX_CONTEXT);
+#else
+       dev = alloc_etherdev(sizeof(*bp));
+#endif
+       if (!dev) {
+               printk(KERN_ERR PFX "Cannot allocate net device\n");
+               return -ENOMEM;
+       }
+
+       bp = netdev_priv(dev);
+       bp->msglevel = debug;
+
+       pci_set_drvdata(pdev, dev);
+
+       rc = bnx2x_init_dev(pdev, dev);
+       if (rc < 0) {
+               free_netdev(dev);
+               return rc;
+       }
+
+       rc = bnx2x_init_bp(bp);
+       if (rc)
+               goto init_one_exit;
+
+       /* Set init arrays */
+       rc = bnx2x_init_firmware(bp, &pdev->dev);
+       if (rc) {
+               printk(KERN_ERR PFX "Error loading firmware\n");
+               goto init_one_exit;
+       }
+
+       rc = register_netdev(dev);
+       if (rc) {
+               dev_err(&pdev->dev, "Cannot register net device\n");
+               goto init_one_exit;
+       }
+
+       bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
+       printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
+              " IRQ %d, ", dev->name, board_info[ent->driver_data].name,
+              (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
+              pcie_width, (pcie_speed == 2) ? "5GHz (Gen2)" : "2.5GHz",
+              dev->base_addr, bp->pdev->irq);
+#if (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+       printk(KERN_CONT "node addr %pM\n", dev->dev_addr);
+#else
+       printk(KERN_CONT "node addr ");
+       {
+               int i;
+
+               for (i = 0; i < ETH_ALEN; i++)
+                       printk(KERN_CONT "%2.2x", dev->dev_addr[i]);
+       }
+       printk(KERN_CONT "\n");
+#endif
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+       VMKNETDDI_REGISTER_QUEUEOPS(dev, bnx2x_netqueue_ops);
+       printk(KERN_INFO "VMware NetQueue Ops is registered for bnx2x\n");
+#endif
+
+       return 0;
+
+init_one_exit:
+       if (bp->regview)
+               iounmap(bp->regview);
+
+       if (bp->doorbells)
+               iounmap(bp->doorbells);
+
+       free_netdev(dev);
+
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       if (atomic_read(&pdev->enable_cnt) == 1)
+#endif
+               pci_release_regions(pdev);
+
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+
+       return rc;
+}
+
+static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2x *bp;
+
+       if (!dev) {
+               printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
+               return;
+       }
+       bp = netdev_priv(dev);
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       flush_scheduled_work();
+#endif
+       unregister_netdev(dev);
+
+#if defined(BNX2X_UPSTREAM) && !defined(BNX2X_USE_INIT_VALUES) /* BNX2X_UPSTREAM */
+       kfree(bp->init_ops_offsets);
+       kfree(bp->init_ops);
+       kfree(bp->init_data);
+       release_firmware(bp->firmware);
+#endif
+
+       if (bp->regview)
+               iounmap(bp->regview);
+
+       if (bp->doorbells)
+               iounmap(bp->doorbells);
+
+       free_netdev(dev);
+
+#if (LINUX_VERSION_CODE >= 0x020614) /* BNX2X_UPSTREAM */
+       if (atomic_read(&pdev->enable_cnt) == 1)
+#endif
+               pci_release_regions(pdev);
+
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+}
+
+static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2x *bp;
+
+       if (!dev) {
+               printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
+               return -ENODEV;
+       }
+       bp = netdev_priv(dev);
+
+       rtnl_lock();
+
+#if (LINUX_VERSION_CODE >= 0x02060b) /* BNX2X_UPSTREAM */
+       pci_save_state(pdev);
+#else
+       pci_save_state(pdev, bp->pci_state);
+#endif
+
+       if (!netif_running(dev)) {
+               rtnl_unlock();
+               return 0;
+       }
+
+#if (LINUX_VERSION_CODE < 0x020618) /* ! BNX2X_UPSTREAM */
+       flush_scheduled_work();
+#endif
+       netif_device_detach(dev);
+
+       bnx2x_nic_unload(bp, UNLOAD_CLOSE);
+
+       bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
+
+       rtnl_unlock();
+
+       return 0;
+}
+
+static int bnx2x_resume(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2x *bp;
+       int rc;
+
+       if (!dev) {
+               printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
+               return -ENODEV;
+       }
+       bp = netdev_priv(dev);
+
+       rtnl_lock();
+
+#if (LINUX_VERSION_CODE >= 0x02060b) /* BNX2X_UPSTREAM */
+       pci_restore_state(pdev);
+#else
+       pci_restore_state(pdev, bp->pci_state);
+#endif
+
+       if (!netif_running(dev)) {
+               rtnl_unlock();
+               return 0;
+       }
+
+       bnx2x_set_power_state(bp, PCI_D0);
+       netif_device_attach(dev);
+
+       rc = bnx2x_nic_load(bp, LOAD_OPEN);
+
+       rtnl_unlock();
+
+       return rc;
+}
+
+#if (LINUX_VERSION_CODE >= 0x02060b) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */
+static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
+{
+       int i;
+
+       bp->state = BNX2X_STATE_ERROR;
+
+       bp->rx_mode = BNX2X_RX_MODE_NONE;
+
+       bnx2x_netif_stop(bp, 0);
+
+       del_timer_sync(&bp->timer);
+       bp->stats_state = STATS_STATE_DISABLED;
+       DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
+
+       /* Release IRQs */
+       bnx2x_free_irq(bp);
+
+       if (CHIP_IS_E1(bp)) {
+               struct mac_configuration_cmd *config =
+                                               bnx2x_sp(bp, mcast_config);
+
+               for (i = 0; i < config->hdr.length; i++)
+                       CAM_INVALIDATE(config->config_table[i]);
+       }
+
+       /* Free SKBs, SGEs, TPA pool and driver internals */
+       bnx2x_free_skbs(bp);
+       for_each_rx_queue(bp, i)
+               bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
+#if defined(BNX2X_NEW_NAPI) && (LINUX_VERSION_CODE >= 0x02061b) /* BNX2X_UPSTREAM */
+       for_each_rx_queue(bp, i)
+               netif_napi_del(&bnx2x_fp(bp, i, napi));
+#endif
+       bnx2x_free_mem(bp);
+
+       bp->state = BNX2X_STATE_CLOSED;
+
+       netif_carrier_off(bp->dev);
+
+       return 0;
+}
+
+static void bnx2x_eeh_recover(struct bnx2x *bp)
+{
+       u32 val;
+
+       mutex_init(&bp->port.phy_mutex);
+
+       bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
+       bp->link_params.shmem_base = bp->common.shmem_base;
+       BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
+
+       if (!bp->common.shmem_base ||
+           (bp->common.shmem_base < 0xA0000) ||
+           (bp->common.shmem_base >= 0xC0000)) {
+               BNX2X_DEV_INFO("MCP not active\n");
+               bp->flags |= NO_MCP_FLAG;
+               return;
+       }
+
+       val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
+       if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
+               != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
+               BNX2X_ERR("BAD MCP validity signature\n");
+
+       if (!BP_NOMCP(bp)) {
+               bp->fw_seq = (SHMEM_RD(bp, func_mb[BP_FUNC(bp)].drv_mb_header)
+                             & DRV_MSG_SEQ_NUMBER_MASK);
+               BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
+       }
+}
+
+/**
+ * bnx2x_io_error_detected - called when PCI error is detected
+ * @pdev: Pointer to PCI device
+ * @state: The current pci connection state
+ *
+ * This function is called after a PCI bus error affecting
+ * this device has been detected.
+ */
+static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
+                                               pci_channel_state_t state)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2x *bp = netdev_priv(dev);
+
+       rtnl_lock();
+
+       netif_device_detach(dev);
+
+       if (netif_running(dev))
+               bnx2x_eeh_nic_unload(bp);
+
+       pci_disable_device(pdev);
+
+       rtnl_unlock();
+
+       /* Request a slot reset */
+       return PCI_ERS_RESULT_NEED_RESET;
+}
+
+/**
+ * bnx2x_io_slot_reset - called after the PCI bus has been reset
+ * @pdev: Pointer to PCI device
+ *
+ * Restart the card from scratch, as if from a cold-boot.
+ */
+static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2x *bp = netdev_priv(dev);
+
+       rtnl_lock();
+
+       if (pci_enable_device(pdev)) {
+               dev_err(&pdev->dev,
+                       "Cannot re-enable PCI device after reset\n");
+               rtnl_unlock();
+               return PCI_ERS_RESULT_DISCONNECT;
+       }
+
+       pci_set_master(pdev);
+       pci_restore_state(pdev);
+
+       if (netif_running(dev))
+               bnx2x_set_power_state(bp, PCI_D0);
+
+       rtnl_unlock();
+
+       return PCI_ERS_RESULT_RECOVERED;
+}
+
+/**
+ * bnx2x_io_resume - called when traffic can start flowing again
+ * @pdev: Pointer to PCI device
+ *
+ * This callback is called when the error recovery driver tells us that
+ * its OK to resume normal operation.
+ */
+static void bnx2x_io_resume(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2x *bp = netdev_priv(dev);
+
+       rtnl_lock();
+
+       bnx2x_eeh_recover(bp);
+
+       if (netif_running(dev))
+               bnx2x_nic_load(bp, LOAD_NORMAL);
+
+       netif_device_attach(dev);
+
+       rtnl_unlock();
+}
+
+static struct pci_error_handlers bnx2x_err_handler = {
+       .error_detected = bnx2x_io_error_detected,
+       .slot_reset     = bnx2x_io_slot_reset,
+       .resume         = bnx2x_io_resume,
+};
+#endif
+
+static struct pci_driver bnx2x_pci_driver = {
+       .name        = DRV_MODULE_NAME,
+       .id_table    = bnx2x_pci_tbl,
+       .probe       = bnx2x_init_one,
+       .remove      = __devexit_p(bnx2x_remove_one),
+       .suspend     = bnx2x_suspend,
+       .resume      = bnx2x_resume,
+#if (LINUX_VERSION_CODE >= 0x02060b) && !defined(__VMKLNX__) /* BNX2X_UPSTREAM */
+       .err_handler = &bnx2x_err_handler,
+#endif
+};
+
+static int __init bnx2x_init(void)
+{
+       int rc;
+
+       printk(KERN_INFO "%s", version);
+
+       bnx2x_wq = create_singlethread_workqueue("bnx2x");
+       if (bnx2x_wq == NULL) {
+               printk(KERN_ERR PFX "Cannot create workqueue\n");
+               return -ENOMEM;
+       }
+
+#if (LINUX_VERSION_CODE >= 0x020600) /* BNX2X_UPSTREAM */
+       rc = pci_register_driver(&bnx2x_pci_driver);
+#else
+       rc = pci_module_init(&bnx2x_pci_driver);
+#endif
+#if (LINUX_VERSION_CODE >= 0x02060a) /* BNX2X_UPSTREAM */
+       if (rc) {
+               printk(KERN_ERR PFX "Cannot register driver\n");
+               destroy_workqueue(bnx2x_wq);
+       }
+#endif
+       return rc;
+}
+
+static void __exit bnx2x_cleanup(void)
+{
+       pci_unregister_driver(&bnx2x_pci_driver);
+
+       destroy_workqueue(bnx2x_wq);
+}
+
+module_init(bnx2x_init);
+module_exit(bnx2x_cleanup);
+
+#ifdef BCM_CNIC /* ! BNX2X_UPSTREAM */
+
+/* count denotes the number of new completions we have seen */
+static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
+{
+       int func = BP_FUNC(bp);
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return;
+#endif
+
+       spin_lock_bh(&bp->spq_lock);
+       bp->cnic_spq_pending -= count;
+
+       for (; bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending;
+            bp->cnic_spq_pending++) {
+
+               if (!bp->cnic_kwq_pending)
+                       break;
+
+               *bp->spq_prod_bd = *bp->cnic_kwq_cons;
+
+               bp->cnic_kwq_pending--;
+
+               DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
+                  bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
+
+               if (bp->spq_prod_bd == bp->spq_last_bd) {
+                       bp->spq_prod_bd = bp->spq;
+                       bp->spq_prod_idx = 0;
+                       DP(NETIF_MSG_TIMER, "end of spq\n");
+
+               } else {
+                       bp->spq_prod_bd++;
+                       bp->spq_prod_idx++;
+               }
+
+               if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
+                       bp->cnic_kwq_cons = bp->cnic_kwq;
+               else
+                       bp->cnic_kwq_cons++;
+       }
+
+       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
+              bp->spq_prod_idx);
+
+       spin_unlock_bh(&bp->spq_lock);
+}
+
+static int bnx2x_cnic_sp_queue(struct net_device *dev,
+                              struct kwqe_16 *kwqes[], u32 count)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       int i;
+
+#ifdef BNX2X_STOP_ON_ERROR
+       if (unlikely(bp->panic))
+               return -EIO;
+#endif
+
+       spin_lock_bh(&bp->spq_lock);
+
+       for (i = 0; i < count; i++) {
+               struct eth_spe *spe = (struct eth_spe *)kwqes[i];
+
+               if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
+                       break;
+
+               *bp->cnic_kwq_prod = *spe;
+
+               bp->cnic_kwq_pending++;
+
+               DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
+                  spe->hdr.conn_and_cmd_data, spe->hdr.type,
+                  spe->data.mac_config_addr.hi,
+                  spe->data.mac_config_addr.lo,
+                  bp->cnic_kwq_pending);
+
+               if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
+                       bp->cnic_kwq_prod = bp->cnic_kwq;
+               else
+                       bp->cnic_kwq_prod++;
+       }
+
+       spin_unlock_bh(&bp->spq_lock);
+
+       if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
+               bnx2x_cnic_sp_post(bp, 0);
+
+       return i;
+}
+
+static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
+{
+       struct cnic_ops *c_ops;
+       int rc = 0;
+
+       rcu_read_lock();
+       c_ops = rcu_dereference(bp->cnic_ops);
+       if (c_ops)
+               rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
+       rcu_read_unlock();
+
+       /* since for now we don't handle send failure just tell the user */
+       if (rc)
+               BNX2X_ERR("sending cmd %x returned %d\n", ctl->cmd, rc);
+
+       return rc;
+}
+
+/*
+ * for commands that have no data
+ */
+static int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
+{
+       struct cnic_ctl_info ctl = {0};
+
+       ctl.cmd = cmd;
+
+       return bnx2x_cnic_ctl_send(bp, &ctl);
+}
+
+static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
+{
+       struct cnic_ctl_info ctl;
+
+       /* first we tell CNIC and only then we count this as a completion */
+       ctl.cmd = CNIC_CTL_COMPLETION_CMD;
+       ctl.data.comp.cid = cid;
+
+       bnx2x_cnic_ctl_send(bp, &ctl);
+       bnx2x_cnic_sp_post(bp, 1);
+}
+
+static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+
+       switch (ctl->cmd) {
+       case DRV_CTL_CTXTBL_WR_CMD:
+               {
+                       u32 index = ctl->data.io.offset;
+                       dma_addr_t addr = ctl->data.io.dma_addr;
+
+                       bnx2x_ilt_wr(bp, index, addr);
+                       return 0;
+               }
+               break;
+
+       case DRV_CTL_COMPLETION_CMD:
+               {
+                       int count = ctl->data.comp.comp_count;
+
+                       bnx2x_cnic_sp_post(bp, count);
+                       return 0;
+               }
+               break;
+
+       default:
+               BNX2X_ERR("unknown command %x\n", ctl->cmd);
+               return -EINVAL;
+       }
+}
+
+static void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
+{
+       struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
+
+#ifdef CONFIG_PCI_MSI /* BNX2X_UPSTREAM */
+       if (bp->flags & USING_MSIX_FLAG) {
+               cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
+               cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
+               cp->irq_arr[0].vector = bp->msix_table[1].vector;
+       } else {
+#else
+       {
+#endif
+               cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
+               cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
+       }
+       cp->irq_arr[0].status_blk = bp->cnic_sb;
+       cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
+
+       cp->num_irq = 1;
+}
+
+static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
+                              void *data)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
+
+       if (ops == NULL)
+               return -EINVAL;
+
+#if !defined(__VMKLNX__)
+       if (!try_module_get(ops->cnic_owner))
+               return -EBUSY;
+#endif
+
+       if (atomic_read(&bp->intr_sem) != 0)
+               return -EBUSY;
+
+       bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
+       if (!bp->cnic_kwq)
+               return -ENOMEM;
+
+       bp->cnic_kwq_cons = bp->cnic_kwq;
+       bp->cnic_kwq_prod = bp->cnic_kwq;
+       bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
+
+       bp->cnic_spq_pending = 0;
+       bp->cnic_kwq_pending = 0;
+
+       bp->cnic_data = data;
+       rcu_assign_pointer(bp->cnic_ops, ops);
+
+       cp->num_irq = 0;
+       cp->drv_state = CNIC_DRV_STATE_REGD;
+
+       bnx2x_init_sb(bp, bp->cnic_sb, bp->cnic_sb_mapping, CNIC_SB_ID(bp));
+
+       bnx2x_setup_cnic_irq_info(bp);
+
+       return 0;
+}
+
+static int bnx2x_unregister_cnic(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
+
+       cp->drv_state = 0;
+#if !defined(__VMKLNX__)
+       module_put(bp->cnic_ops->cnic_owner);
+#endif
+       rcu_assign_pointer(bp->cnic_ops, NULL);
+#if !defined(__VMKLNX__)
+       synchronize_rcu();
+#endif
+       kfree(bp->cnic_kwq);
+
+       return 0;
+}
+
+struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
+{
+       struct bnx2x *bp = netdev_priv(dev);
+       struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
+
+       cp->drv_owner = THIS_MODULE;
+       cp->chip_id = CHIP_ID(bp);
+       cp->pdev = bp->pdev;
+       cp->io_base = bp->regview;
+       cp->max_kwqe_pending = 8;
+       cp->ctx_blk_size = CNIC_CTX_PER_ILT * sizeof(union cdu_context);
+       cp->ctx_tbl_offset = FUNC_ILT_BASE(bp->func) + 1;
+       cp->ctx_tbl_len = CNIC_ILT_LINES;
+       cp->starting_cid = 16;
+       cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
+       cp->drv_ctl = bnx2x_drv_ctl;
+       cp->drv_register_cnic = bnx2x_register_cnic;
+       cp->drv_unregister_cnic = bnx2x_unregister_cnic;
+
+       return cp;
+}
+EXPORT_SYMBOL(bnx2x_cnic_probe);
+
+#endif /* BCM_CNIC */
+
+#if defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) /* ! BNX2X_UPSTREAM */
+
+static int bnx2x_get_netqueue_features(vmknetddi_queueop_get_features_args_t *args)
+{
+       args->features = VMKNETDDI_QUEUEOPS_FEATURE_NONE;
+       args->features |= VMKNETDDI_QUEUEOPS_FEATURE_RXQUEUES;
+       args->features |= VMKNETDDI_QUEUEOPS_FEATURE_TXQUEUES;
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static int bnx2x_get_queue_count(vmknetddi_queueop_get_queue_count_args_t *args)
+{
+       struct bnx2x *bp = netdev_priv(args->netdev);
+
+       /* workaround for packets duplicated */
+       if (is_multi(bp)) {
+               bp->rx_mode = BNX2X_RX_MODE_NORMAL;
+               bnx2x_set_storm_rx_mode(bp);
+               bp->netq_enabled = 1;
+       }
+       if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) {
+               args->count = max_t(u16, BNX2X_NUM_QUEUES(bp) - 1, 0);
+               return VMKNETDDI_QUEUEOPS_OK;
+
+       } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) {
+               args->count = max_t(u16, BNX2X_NUM_QUEUES(bp) - 1, 0);
+               return VMKNETDDI_QUEUEOPS_OK;
+
+       } else {
+               printk("bnx2x_get_queue_count: invalid queue type\n");
+               return VMKNETDDI_QUEUEOPS_ERR;
+       }
+}
+
+static int bnx2x_get_filter_count(vmknetddi_queueop_get_filter_count_args_t *args)
+{
+       /* Only support 1 Mac filter per queue */
+       args->count = 1;
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static int bnx2x_alloc_rx_queue(struct net_device *netdev,
+                               vmknetddi_queueops_queueid_t *p_qid,
+                               struct napi_struct **napi_p)
+{
+       struct bnx2x *bp = netdev_priv(netdev);
+       int i;
+
+       if (bp->n_rx_queues_allocated >= BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       for_each_nondefault_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               if (!BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp)) {
+                       fp->netq_flags |= BNX2X_NETQ_RX_QUEUE_ALLOCATED;
+                       bp->n_rx_queues_allocated++;
+                       *p_qid = VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(fp->index);
+                       *napi_p = &fp->napi;
+                       return VMKNETDDI_QUEUEOPS_OK;
+               }
+       }
+       BNX2X_ERR("bnx2x_alloc_rx_queue: no free rx queues found!\n");
+       return VMKNETDDI_QUEUEOPS_ERR;
+}
+
+static int bnx2x_alloc_tx_queue(struct net_device *netdev,
+                               vmknetddi_queueops_queueid_t *p_qid,
+                               u16 *queue_mapping)
+{
+       struct bnx2x *bp = netdev_priv(netdev);
+       int i;
+
+       if (bp->n_tx_queues_allocated >= BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       for_each_nondefault_queue(bp, i) {
+               struct bnx2x_fastpath *fp = &bp->fp[i];
+
+               if (!BNX2X_IS_NETQ_TX_QUEUE_ALLOCATED(fp)) {
+                       fp->netq_flags |= BNX2X_NETQ_TX_QUEUE_ALLOCATED;
+                       bp->n_tx_queues_allocated++;
+                       *p_qid = VMKNETDDI_QUEUEOPS_MK_TX_QUEUEID(fp->index);
+                       *queue_mapping = fp->index;
+                       return VMKNETDDI_QUEUEOPS_OK;
+               }
+       }
+       BNX2X_ERR("bnx2x_alloc_tx_queue: no free tx queues found!\n");
+       return VMKNETDDI_QUEUEOPS_ERR;
+}
+
+static int bnx2x_alloc_queue(vmknetddi_queueop_alloc_queue_args_t *args)
+{
+       if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX)
+               return bnx2x_alloc_tx_queue(args->netdev, &args->queueid,
+                                           &args->queue_mapping);
+
+       else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX)
+               return bnx2x_alloc_rx_queue(args->netdev, &args->queueid,
+                                           &args->napi);
+       else {
+               printk("bnx2x_alloc_queue: invalid queue type\n");
+               return VMKNETDDI_QUEUEOPS_ERR;
+       }
+}
+
+static int bnx2x_free_tx_queue(struct net_device *netdev,
+                              vmknetddi_queueops_queueid_t qid)
+{
+       struct bnx2x *bp = netdev_priv(netdev);
+       u16 index = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(qid);
+
+       if (index > BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       struct bnx2x_fastpath *fp = &bp->fp[index];
+
+       if (!BNX2X_IS_NETQ_TX_QUEUE_ALLOCATED(fp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       fp->netq_flags &= ~BNX2X_NETQ_TX_QUEUE_ALLOCATED;
+       bp->n_tx_queues_allocated--;
+
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static int bnx2x_free_rx_queue(struct net_device *netdev,
+                              vmknetddi_queueops_queueid_t qid)
+{
+       struct bnx2x *bp = netdev_priv(netdev);
+       u16 index = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(qid);
+
+       if (index > BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       struct bnx2x_fastpath *fp = &bp->fp[index];
+
+       if (!BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       fp->netq_flags &= ~BNX2X_NETQ_RX_QUEUE_ALLOCATED;
+       bp->n_rx_queues_allocated--;
+
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static int bnx2x_free_queue(vmknetddi_queueop_free_queue_args_t *args)
+{
+       if (VMKNETDDI_QUEUEOPS_IS_TX_QUEUEID(args->queueid))
+               return bnx2x_free_tx_queue(args->netdev, args->queueid);
+
+       else if (VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid))
+               return bnx2x_free_rx_queue(args->netdev, args->queueid);
+
+       else {
+               printk("bnx2x_free_queue: invalid queue type\n");
+               return VMKNETDDI_QUEUEOPS_ERR;
+       }
+}
+
+static int bnx2x_get_queue_vector(vmknetddi_queueop_get_queue_vector_args_t *args)
+{
+       struct net_device *netdev = args->netdev;
+       struct bnx2x *bp = netdev_priv(netdev);
+       int qid;
+
+       qid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid);
+       if (qid > BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+#ifdef CONFIG_PCI_MSI
+       args->vector = bp->msix_table[qid].vector;
+#endif
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static int bnx2x_get_default_queue(vmknetddi_queueop_get_default_queue_args_t *args)
+{
+       struct net_device *netdev = args->netdev;
+       struct bnx2x *bp = netdev_priv(netdev);
+
+       if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_RX) {
+               args->queueid = VMKNETDDI_QUEUEOPS_MK_RX_QUEUEID(0);
+               args->napi = &bp->fp[0].napi;
+               return VMKNETDDI_QUEUEOPS_OK;
+
+       } else if (args->type == VMKNETDDI_QUEUEOPS_QUEUE_TYPE_TX) {
+               args->queueid = VMKNETDDI_QUEUEOPS_MK_TX_QUEUEID(0);
+               args->queue_mapping = 0;
+               return VMKNETDDI_QUEUEOPS_OK;
+
+       } else
+               return VMKNETDDI_QUEUEOPS_ERR;
+}
+
+static void bnx2x_remove_rx_filter_e1h(struct bnx2x *bp, u16 qid)
+{
+       struct bnx2x_fastpath *fp = &bp->fp[qid];
+       struct mac_configuration_cmd_e1h *config =
+               (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
+
+       /* CAM allocation for E1H
+        * unicasts: by func number
+        * multicast: 20+FUNC*20, 20 each
+        */
+       config->hdr.length = 1;
+       config->hdr.offset = BP_FUNC(bp) + (qid << (IS_E1HMF(bp) ? 3 : 1));
+       config->hdr.client_id = bp->fp[0].cl_id;
+       config->hdr.reserved1 = 0;
+
+       /* primary MAC */
+       config->config_table[0].msb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[0]);
+       config->config_table[0].middle_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[2]);
+       config->config_table[0].lsb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[4]);
+       config->config_table[0].client_id = BP_L_ID(bp) + qid;
+       config->config_table[0].vlan_id = 0;
+       config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
+       config->config_table[0].flags = MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
+
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+
+       memset(fp->mac_filter_addr, 0, 6);
+       fp->netq_flags &= ~BNX2X_NETQ_RX_QUEUE_ACTIVE;
+}
+
+static void bnx2x_remove_rx_filter_e1(struct bnx2x *bp, u16 qid)
+{
+       struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
+       struct bnx2x_fastpath *fp = &bp->fp[qid];
+
+       config->hdr.length = 1;
+       config->hdr.offset = (BP_PORT(bp) ? 32 : 0) + qid;
+       config->hdr.client_id = bp->fp[0].cl_id;
+       config->hdr.reserved1 = 0;
+
+       config->config_table[0].cam_entry.msb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[0]);
+       config->config_table[0].cam_entry.middle_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[2]);
+       config->config_table[0].cam_entry.lsb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[4]);
+       config->config_table[0].cam_entry.flags = cpu_to_le16(BP_PORT(bp));
+       config->config_table[0].target_table_entry.flags =
+                                       TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE;
+       config->config_table[0].target_table_entry.client_id = qid;
+       config->config_table[0].target_table_entry.vlan_id = 0;
+
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+
+       memset(fp->mac_filter_addr, 0, 6);
+       fp->netq_flags &= ~BNX2X_NETQ_RX_QUEUE_ACTIVE;
+}
+
+static int bnx2x_remove_rx_filter(vmknetddi_queueop_remove_rx_filter_args_t *args)
+{
+       struct bnx2x *bp = netdev_priv(args->netdev);
+       u16 qid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid);
+       u16 fid = VMKNETDDI_QUEUEOPS_FILTERID_VAL(args->filterid);
+       struct bnx2x_fastpath *fp = &bp->fp[qid];
+
+       if (!VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       if (qid > BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       /* Only support one Mac filter per queue */
+       if ((fid != 0) || !BNX2X_IS_NETQ_RX_QUEUE_ACTIVE(fp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       if (CHIP_IS_E1H(bp))
+               bnx2x_remove_rx_filter_e1h(bp, qid);
+       else
+               bnx2x_remove_rx_filter_e1(bp, qid);
+
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static void bnx2x_apply_rx_filter_e1h(struct bnx2x *bp, u16 queueid)
+{
+       struct mac_configuration_cmd_e1h *config =
+               (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
+       struct bnx2x_fastpath *fp = &bp->fp[queueid];
+
+       config->hdr.length = 1;
+       config->hdr.offset = BP_FUNC(bp) + (queueid << (IS_E1HMF(bp) ? 3 : 1));
+       config->hdr.client_id = bp->fp[0].cl_id;
+       config->hdr.reserved1 = 0;
+
+       config->config_table[0].msb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[0]);
+       config->config_table[0].middle_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[2]);
+       config->config_table[0].lsb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[4]);
+       config->config_table[0].client_id = BP_L_ID(bp) + queueid;
+       config->config_table[0].vlan_id = 0;
+       config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
+       config->config_table[0].flags = BP_PORT(bp);
+
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+
+       fp->netq_flags |= BNX2X_NETQ_RX_QUEUE_ACTIVE;
+}
+
+static void bnx2x_apply_rx_filter_e1(struct bnx2x *bp, u16 queueid)
+{
+       struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
+       struct bnx2x_fastpath *fp = &bp->fp[queueid];
+
+       config->hdr.length = 1;
+       config->hdr.offset = (BP_PORT(bp) ? 32 : 0) + queueid;
+       config->hdr.client_id = bp->fp[0].cl_id;
+       config->hdr.reserved1 = 0;
+
+       config->config_table[0].cam_entry.msb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[0]);
+       config->config_table[0].cam_entry.middle_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[2]);
+       config->config_table[0].cam_entry.lsb_mac_addr =
+                                       swab16(*(u16 *)&fp->mac_filter_addr[4]);
+       config->config_table[0].cam_entry.flags = cpu_to_le16(BP_PORT(bp));
+       config->config_table[0].target_table_entry.flags = 0;
+       config->config_table[0].target_table_entry.client_id = queueid;
+       config->config_table[0].target_table_entry.vlan_id = 0;
+
+       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+
+       fp->netq_flags |= BNX2X_NETQ_RX_QUEUE_ACTIVE;
+}
+
+static int bnx2x_apply_rx_filter(vmknetddi_queueop_apply_rx_filter_args_t *args)
+{
+       struct bnx2x *bp = netdev_priv(args->netdev);
+       struct bnx2x_fastpath *fp;
+       u16 queueid = VMKNETDDI_QUEUEOPS_QUEUEID_VAL(args->queueid);
+       u8 *macaddr;
+
+       if (!VMKNETDDI_QUEUEOPS_IS_RX_QUEUEID(args->queueid))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       if (vmknetddi_queueops_get_filter_class(&args->filter)
+                                       != VMKNETDDI_QUEUEOPS_FILTER_MACADDR)
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       if (queueid > BNX2X_NUM_QUEUES(bp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       fp = &bp->fp[queueid];
+
+       if (BNX2X_IS_NETQ_RX_QUEUE_ACTIVE(fp) ||
+           !BNX2X_IS_NETQ_RX_QUEUE_ALLOCATED(fp))
+               return VMKNETDDI_QUEUEOPS_ERR;
+
+       macaddr = (void *)vmknetddi_queueops_get_filter_macaddr(&args->filter);
+       memcpy(fp->mac_filter_addr, macaddr, 6);
+       if (CHIP_IS_E1H(bp))
+               bnx2x_apply_rx_filter_e1h(bp, queueid);
+       else
+               bnx2x_apply_rx_filter_e1(bp, queueid);
+       args->filterid = VMKNETDDI_QUEUEOPS_MK_FILTERID(0);
+
+       return VMKNETDDI_QUEUEOPS_OK;
+}
+
+static int bnx2x_get_queue_stats(vmknetddi_queueop_get_stats_args_t *args)
+{
+       return VMKNETDDI_QUEUEOPS_ERR;
+}
+
+static int bnx2x_get_netqueue_version(vmknetddi_queueop_get_version_args_t *args)
+{
+       return vmknetddi_queueops_version(args);
+}
+
+static int bnx2x_netqueue_ops(vmknetddi_queueops_op_t op, void *args)
+{
+       switch (op) {
+       case VMKNETDDI_QUEUEOPS_OP_GET_VERSION:
+               return bnx2x_get_netqueue_version(
+                       (vmknetddi_queueop_get_version_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_GET_FEATURES:
+               return bnx2x_get_netqueue_features(
+                       (vmknetddi_queueop_get_features_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_GET_QUEUE_COUNT:
+               return bnx2x_get_queue_count(
+                       (vmknetddi_queueop_get_queue_count_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_GET_FILTER_COUNT:
+               return bnx2x_get_filter_count(
+                       (vmknetddi_queueop_get_filter_count_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_ALLOC_QUEUE:
+               return bnx2x_alloc_queue(
+                       (vmknetddi_queueop_alloc_queue_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_FREE_QUEUE:
+               return bnx2x_free_queue(
+                       (vmknetddi_queueop_free_queue_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_GET_QUEUE_VECTOR:
+               return bnx2x_get_queue_vector(
+                       (vmknetddi_queueop_get_queue_vector_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_GET_DEFAULT_QUEUE:
+               return bnx2x_get_default_queue(
+                       (vmknetddi_queueop_get_default_queue_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_APPLY_RX_FILTER:
+               return bnx2x_apply_rx_filter(
+                       (vmknetddi_queueop_apply_rx_filter_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_REMOVE_RX_FILTER:
+               return bnx2x_remove_rx_filter(
+                       (vmknetddi_queueop_remove_rx_filter_args_t *)args);
+               break;
+
+       case VMKNETDDI_QUEUEOPS_OP_GET_STATS:
+               return bnx2x_get_queue_stats(
+                       (vmknetddi_queueop_get_stats_args_t *)args);
+               break;
+
+       default:
+               printk("Unhandled NETQUEUE OP %d\n", op);
+               return VMKNETDDI_QUEUEOPS_ERR;
+       }
+
+       return VMKNETDDI_QUEUEOPS_ERR;
+}
+
+#endif /* defined(__VMKLNX__) && defined(__VMKNETDDI_QUEUEOPS__) */
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_reg.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_reg.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_reg.h 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_reg.h      2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,5350 @@
+/* bnx2x_reg.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * The registers description starts with the register Access type followed
+ * by size in bits. For example [RW 32]. The access types are:
+ * R  - Read only
+ * RC - Clear on read
+ * RW - Read/Write
+ * ST - Statistics register (clear on read)
+ * W  - Write only
+ * WB - Wide bus register - the size is over 32 bits and it should be
+ *      read/write in consecutive 32 bits accesses
+ * WR - Write Clear (write 1 to clear the bit)
+ *
+ */
+
+
+/* [R 19] Interrupt register #0 read */
+#define BRB1_REG_BRB1_INT_STS                                   0x6011c
+/* [RW 4] Parity mask register #0 read/write */
+#define BRB1_REG_BRB1_PRTY_MASK                                 0x60138
+/* [R 4] Parity register #0 read */
+#define BRB1_REG_BRB1_PRTY_STS                                  0x6012c
+/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
+   address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
+   BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
+#define BRB1_REG_FREE_LIST_PRS_CRDT                             0x60200
+/* [RW 10] The number of free blocks above which the High_llfc signal to
+   interface #n is de-asserted. */
+#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0                     0x6014c
+/* [RW 10] The number of free blocks below which the High_llfc signal to
+   interface #n is asserted. */
+#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0                      0x6013c
+/* [RW 23] LL RAM data. */
+#define BRB1_REG_LL_RAM                                         0x61000
+/* [RW 10] The number of free blocks above which the Low_llfc signal to
+   interface #n is de-asserted. */
+#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0                      0x6016c
+/* [RW 10] The number of free blocks below which the Low_llfc signal to
+   interface #n is asserted. */
+#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0                       0x6015c
+/* [R 24] The number of full blocks. */
+#define BRB1_REG_NUM_OF_FULL_BLOCKS                             0x60090
+/* [ST 32] The number of cycles that the write_full signal towards MAC #0
+   was asserted. */
+#define BRB1_REG_NUM_OF_FULL_CYCLES_0                           0x600c8
+#define BRB1_REG_NUM_OF_FULL_CYCLES_1                           0x600cc
+#define BRB1_REG_NUM_OF_FULL_CYCLES_4                           0x600d8
+/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
+   asserted. */
+#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0                          0x600b8
+#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1                          0x600bc
+/* [RW 10] Write client 0: De-assert pause threshold. */
+#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0                         0x60078
+#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1                         0x6007c
+/* [RW 10] Write client 0: Assert pause threshold. */
+#define BRB1_REG_PAUSE_LOW_THRESHOLD_0                          0x60068
+#define BRB1_REG_PAUSE_LOW_THRESHOLD_1                          0x6006c
+/* [R 24] The number of full blocks occupied by port. */
+#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0                          0x60094
+/* [RW 1] Reset the design by software. */
+#define BRB1_REG_SOFT_RESET                                     0x600dc
+/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
+#define CCM_REG_CAM_OCCUP                                       0xd0188
+/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_CCM_CFC_IFEN                                    0xd003c
+/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_CCM_CQM_IFEN                                    0xd000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
+   Otherwise 0 is inserted. */
+#define CCM_REG_CCM_CQM_USE_Q                                   0xd00c0
+/* [RW 11] Interrupt mask register #0 read/write */
+#define CCM_REG_CCM_INT_MASK                                    0xd01e4
+/* [R 11] Interrupt register #0 read */
+#define CCM_REG_CCM_INT_STS                                     0xd01d8
+/* [R 27] Parity register #0 read */
+#define CCM_REG_CCM_PRTY_STS                                    0xd01e8
+/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
+   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+   Is used to determine the number of the AG context REG-pairs written back;
+   when the input message Reg1WbFlg isn't set. */
+#define CCM_REG_CCM_REG0_SZ                                     0xd00c4
+/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_CCM_STORM0_IFEN                                 0xd0004
+/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_CCM_STORM1_IFEN                                 0xd0008
+/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define CCM_REG_CDU_AG_RD_IFEN                                  0xd0030
+/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
+   are disregarded; all other signals are treated as usual; if 1 - normal
+   activity. */
+#define CCM_REG_CDU_AG_WR_IFEN                                  0xd002c
+/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define CCM_REG_CDU_SM_RD_IFEN                                  0xd0038
+/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
+   input is disregarded; all other signals are treated as usual; if 1 -
+   normal activity. */
+#define CCM_REG_CDU_SM_WR_IFEN                                  0xd0034
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 1 at start-up. */
+#define CCM_REG_CFC_INIT_CRD                                    0xd0204
+/* [RW 2] Auxillary counter flag Q number 1. */
+#define CCM_REG_CNT_AUX1_Q                                      0xd00c8
+/* [RW 2] Auxillary counter flag Q number 2. */
+#define CCM_REG_CNT_AUX2_Q                                      0xd00cc
+/* [RW 28] The CM header value for QM request (primary). */
+#define CCM_REG_CQM_CCM_HDR_P                                   0xd008c
+/* [RW 28] The CM header value for QM request (secondary). */
+#define CCM_REG_CQM_CCM_HDR_S                                   0xd0090
+/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_CQM_CCM_IFEN                                    0xd0014
+/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 32 at start-up. */
+#define CCM_REG_CQM_INIT_CRD                                    0xd020c
+/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_CQM_P_WEIGHT                                    0xd00b8
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_CQM_S_WEIGHT                                    0xd00bc
+/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_CSDM_IFEN                                       0xd0018
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the SDM interface is detected. */
+#define CCM_REG_CSDM_LENGTH_MIS                                 0xd0170
+/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_CSDM_WEIGHT                                     0xd00b4
+/* [RW 28] The CM header for QM formatting in case of an error in the QM
+   inputs. */
+#define CCM_REG_ERR_CCM_HDR                                     0xd0094
+/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
+#define CCM_REG_ERR_EVNT_ID                                     0xd0098
+/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define CCM_REG_FIC0_INIT_CRD                                   0xd0210
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define CCM_REG_FIC1_INIT_CRD                                   0xd0214
+/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
+   - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
+   ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
+   ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
+   outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
+#define CCM_REG_GR_ARB_TYPE                                     0xd015c
+/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed; that the Store channel priority is
+   the compliment to 4 of the rest priorities - Aggregation channel; Load
+   (FIC0) channel and Load (FIC1). */
+#define CCM_REG_GR_LD0_PR                                       0xd0164
+/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed; that the Store channel priority is
+   the compliment to 4 of the rest priorities - Aggregation channel; Load
+   (FIC0) channel and Load (FIC1). */
+#define CCM_REG_GR_LD1_PR                                       0xd0168
+/* [RW 2] General flags index. */
+#define CCM_REG_INV_DONE_Q                                      0xd0108
+/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
+   context and sent to STORM; for a specific connection type. The double
+   REG-pairs are used in order to align to STORM context row size of 128
+   bits. The offset of these data in the STORM context is always 0. Index
+   _(0..15) stands for the connection type (one of 16). */
+#define CCM_REG_N_SM_CTX_LD_0                                   0xd004c
+#define CCM_REG_N_SM_CTX_LD_1                                   0xd0050
+#define CCM_REG_N_SM_CTX_LD_2                                   0xd0054
+#define CCM_REG_N_SM_CTX_LD_3                                   0xd0058
+#define CCM_REG_N_SM_CTX_LD_4                                   0xd005c
+/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define CCM_REG_PBF_IFEN                                        0xd0028
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the pbf interface is detected. */
+#define CCM_REG_PBF_LENGTH_MIS                                  0xd0180
+/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_PBF_WEIGHT                                      0xd00ac
+#define CCM_REG_PHYS_QNUM1_0                                    0xd0134
+#define CCM_REG_PHYS_QNUM1_1                                    0xd0138
+#define CCM_REG_PHYS_QNUM2_0                                    0xd013c
+#define CCM_REG_PHYS_QNUM2_1                                    0xd0140
+#define CCM_REG_PHYS_QNUM3_0                                    0xd0144
+#define CCM_REG_PHYS_QNUM3_1                                    0xd0148
+#define CCM_REG_QOS_PHYS_QNUM0_0                                0xd0114
+#define CCM_REG_QOS_PHYS_QNUM0_1                                0xd0118
+#define CCM_REG_QOS_PHYS_QNUM1_0                                0xd011c
+#define CCM_REG_QOS_PHYS_QNUM1_1                                0xd0120
+#define CCM_REG_QOS_PHYS_QNUM2_0                                0xd0124
+#define CCM_REG_QOS_PHYS_QNUM2_1                                0xd0128
+#define CCM_REG_QOS_PHYS_QNUM3_0                                0xd012c
+#define CCM_REG_QOS_PHYS_QNUM3_1                                0xd0130
+/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define CCM_REG_STORM_CCM_IFEN                                  0xd0010
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the STORM interface is detected. */
+#define CCM_REG_STORM_LENGTH_MIS                                0xd016c
+/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
+   mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
+   weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
+   tc. */
+#define CCM_REG_STORM_WEIGHT                                    0xd009c
+/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define CCM_REG_TSEM_IFEN                                       0xd001c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the tsem interface is detected. */
+#define CCM_REG_TSEM_LENGTH_MIS                                 0xd0174
+/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_TSEM_WEIGHT                                     0xd00a0
+/* [RW 1] Input usem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define CCM_REG_USEM_IFEN                                       0xd0024
+/* [RC 1] Set when message length mismatch (relative to last indication) at
+   the usem interface is detected. */
+#define CCM_REG_USEM_LENGTH_MIS                                 0xd017c
+/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_USEM_WEIGHT                                     0xd00a8
+/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define CCM_REG_XSEM_IFEN                                       0xd0020
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the xsem interface is detected. */
+#define CCM_REG_XSEM_LENGTH_MIS                                 0xd0178
+/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define CCM_REG_XSEM_WEIGHT                                     0xd00a4
+/* [RW 19] Indirect access to the descriptor table of the XX protection
+   mechanism. The fields are: [5:0] - message length; [12:6] - message
+   pointer; 18:13] - next pointer. */
+#define CCM_REG_XX_DESCR_TABLE                                  0xd0300
+#define CCM_REG_XX_DESCR_TABLE_SIZE                             36
+/* [R 7] Used to read the value of XX protection Free counter. */
+#define CCM_REG_XX_FREE                                         0xd0184
+/* [RW 6] Initial value for the credit counter; responsible for fulfilling
+   of the Input Stage XX protection buffer by the XX protection pending
+   messages. Max credit available - 127. Write writes the initial credit
+   value; read returns the current value of the credit counter. Must be
+   initialized to maximum XX protected message size - 2 at start-up. */
+#define CCM_REG_XX_INIT_CRD                                     0xd0220
+/* [RW 7] The maximum number of pending messages; which may be stored in XX
+   protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
+   At write comprises the start value of the ~ccm_registers_xx_free.xx_free
+   counter. */
+#define CCM_REG_XX_MSG_NUM                                      0xd0224
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define CCM_REG_XX_OVFL_EVNT_ID                                 0xd0044
+/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
+   The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
+   header pointer. */
+#define CCM_REG_XX_TABLE                                        0xd0280
+#define CDU_REG_CDU_CHK_MASK0                                   0x101000
+#define CDU_REG_CDU_CHK_MASK1                                   0x101004
+#define CDU_REG_CDU_CONTROL0                                    0x101008
+#define CDU_REG_CDU_DEBUG                                       0x101010
+#define CDU_REG_CDU_GLOBAL_PARAMS                               0x101020
+/* [RW 7] Interrupt mask register #0 read/write */
+#define CDU_REG_CDU_INT_MASK                                    0x10103c
+/* [R 7] Interrupt register #0 read */
+#define CDU_REG_CDU_INT_STS                                     0x101030
+/* [RW 5] Parity mask register #0 read/write */
+#define CDU_REG_CDU_PRTY_MASK                                   0x10104c
+/* [R 5] Parity register #0 read */
+#define CDU_REG_CDU_PRTY_STS                                    0x101040
+/* [RC 32] logging of error data in case of a CDU load error:
+   {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
+   ype_error; ctual_active; ctual_compressed_context}; */
+#define CDU_REG_ERROR_DATA                                      0x101014
+/* [WB 216] L1TT ram access. each entry has the following format :
+   {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
+   ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
+#define CDU_REG_L1TT                                            0x101800
+/* [WB 24] MATT ram access. each entry has the following
+   format:{RegionLength[11:0]; egionOffset[11:0]} */
+#define CDU_REG_MATT                                            0x101100
+/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
+#define CDU_REG_MF_MODE                                         0x101050
+/* [R 1] indication the initializing the activity counter by the hardware
+   was done. */
+#define CFC_REG_AC_INIT_DONE                                    0x104078
+/* [RW 13] activity counter ram access */
+#define CFC_REG_ACTIVITY_COUNTER                                0x104400
+#define CFC_REG_ACTIVITY_COUNTER_SIZE                           256
+/* [R 1] indication the initializing the cams by the hardware was done. */
+#define CFC_REG_CAM_INIT_DONE                                   0x10407c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define CFC_REG_CFC_INT_MASK                                    0x104108
+/* [R 2] Interrupt register #0 read */
+#define CFC_REG_CFC_INT_STS                                     0x1040fc
+/* [RC 2] Interrupt register #0 read clear */
+#define CFC_REG_CFC_INT_STS_CLR                                 0x104100
+/* [RW 4] Parity mask register #0 read/write */
+#define CFC_REG_CFC_PRTY_MASK                                   0x104118
+/* [R 4] Parity register #0 read */
+#define CFC_REG_CFC_PRTY_STS                                    0x10410c
+/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
+#define CFC_REG_CID_CAM                                         0x104800
+#define CFC_REG_CONTROL0                                        0x104028
+#define CFC_REG_DEBUG0                                          0x104050
+/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
+   vector) whether the cfc should be disabled upon it */
+#define CFC_REG_DISABLE_ON_ERROR                                0x104044
+/* [RC 14] CFC error vector. when the CFC detects an internal error it will
+   set one of these bits. the bit description can be found in CFC
+   specifications */
+#define CFC_REG_ERROR_VECTOR                                    0x10403c
+/* [WB 93] LCID info ram access */
+#define CFC_REG_INFO_RAM                                        0x105000
+#define CFC_REG_INFO_RAM_SIZE                                   1024
+#define CFC_REG_INIT_REG                                        0x10404c
+#define CFC_REG_INTERFACES                                      0x104058
+/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
+   field allows changing the priorities of the weighted-round-robin arbiter
+   which selects which CFC load client should be served next */
+#define CFC_REG_LCREQ_WEIGHTS                                   0x104084
+/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
+#define CFC_REG_LINK_LIST                                       0x104c00
+#define CFC_REG_LINK_LIST_SIZE                                  256
+/* [R 1] indication the initializing the link list by the hardware was done. */
+#define CFC_REG_LL_INIT_DONE                                    0x104074
+/* [R 9] Number of allocated LCIDs which are at empty state */
+#define CFC_REG_NUM_LCIDS_ALLOC                                 0x104020
+/* [R 9] Number of Arriving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_ARRIVING                              0x104004
+/* [R 9] Number of Leaving LCIDs in Link List Block */
+#define CFC_REG_NUM_LCIDS_LEAVING                               0x104018
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define CSDM_REG_AGG_INT_EVENT_0                                0xc2038
+#define CSDM_REG_AGG_INT_EVENT_10                               0xc2060
+#define CSDM_REG_AGG_INT_EVENT_11                               0xc2064
+#define CSDM_REG_AGG_INT_EVENT_12                               0xc2068
+#define CSDM_REG_AGG_INT_EVENT_13                               0xc206c
+#define CSDM_REG_AGG_INT_EVENT_14                               0xc2070
+#define CSDM_REG_AGG_INT_EVENT_15                               0xc2074
+#define CSDM_REG_AGG_INT_EVENT_16                               0xc2078
+#define CSDM_REG_AGG_INT_EVENT_2                                0xc2040
+#define CSDM_REG_AGG_INT_EVENT_3                                0xc2044
+#define CSDM_REG_AGG_INT_EVENT_4                                0xc2048
+#define CSDM_REG_AGG_INT_EVENT_5                                0xc204c
+#define CSDM_REG_AGG_INT_EVENT_6                                0xc2050
+#define CSDM_REG_AGG_INT_EVENT_7                                0xc2054
+#define CSDM_REG_AGG_INT_EVENT_8                                0xc2058
+#define CSDM_REG_AGG_INT_EVENT_9                                0xc205c
+/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
+   or auto-mask-mode (1) */
+#define CSDM_REG_AGG_INT_MODE_10                                0xc21e0
+#define CSDM_REG_AGG_INT_MODE_11                                0xc21e4
+#define CSDM_REG_AGG_INT_MODE_12                                0xc21e8
+#define CSDM_REG_AGG_INT_MODE_13                                0xc21ec
+#define CSDM_REG_AGG_INT_MODE_14                                0xc21f0
+#define CSDM_REG_AGG_INT_MODE_15                                0xc21f4
+#define CSDM_REG_AGG_INT_MODE_16                                0xc21f8
+#define CSDM_REG_AGG_INT_MODE_6                                 0xc21d0
+#define CSDM_REG_AGG_INT_MODE_7                                 0xc21d4
+#define CSDM_REG_AGG_INT_MODE_8                                 0xc21d8
+#define CSDM_REG_AGG_INT_MODE_9                                 0xc21dc
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define CSDM_REG_CFC_RSP_START_ADDR                             0xc2008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define CSDM_REG_CMP_COUNTER_MAX0                               0xc201c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define CSDM_REG_CMP_COUNTER_MAX1                               0xc2020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define CSDM_REG_CMP_COUNTER_MAX2                               0xc2024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define CSDM_REG_CMP_COUNTER_MAX3                               0xc2028
+/* [RW 13] The start address in the internal RAM for the completion
+   counters. */
+#define CSDM_REG_CMP_COUNTER_START_ADDR                         0xc200c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSDM_REG_CSDM_INT_MASK_0                                0xc229c
+#define CSDM_REG_CSDM_INT_MASK_1                                0xc22ac
+/* [R 32] Interrupt register #0 read */
+#define CSDM_REG_CSDM_INT_STS_0                                 0xc2290
+#define CSDM_REG_CSDM_INT_STS_1                                 0xc22a0
+/* [RW 11] Parity mask register #0 read/write */
+#define CSDM_REG_CSDM_PRTY_MASK                                 0xc22bc
+/* [R 11] Parity register #0 read */
+#define CSDM_REG_CSDM_PRTY_STS                                  0xc22b0
+#define CSDM_REG_ENABLE_IN1                                     0xc2238
+#define CSDM_REG_ENABLE_IN2                                     0xc223c
+#define CSDM_REG_ENABLE_OUT1                                    0xc2240
+#define CSDM_REG_ENABLE_OUT2                                    0xc2244
+/* [RW 4] The initial number of messages that can be sent to the pxp control
+   interface without receiving any ACK. */
+#define CSDM_REG_INIT_CREDIT_PXP_CTRL                           0xc24bc
+/* [ST 32] The number of ACK after placement messages received */
+#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE                         0xc227c
+/* [ST 32] The number of packet end messages received from the parser */
+#define CSDM_REG_NUM_OF_PKT_END_MSG                             0xc2274
+/* [ST 32] The number of requests received from the pxp async if */
+#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ                           0xc2278
+/* [ST 32] The number of commands received in queue 0 */
+#define CSDM_REG_NUM_OF_Q0_CMD                                  0xc2248
+/* [ST 32] The number of commands received in queue 10 */
+#define CSDM_REG_NUM_OF_Q10_CMD                                 0xc226c
+/* [ST 32] The number of commands received in queue 11 */
+#define CSDM_REG_NUM_OF_Q11_CMD                                 0xc2270
+/* [ST 32] The number of commands received in queue 1 */
+#define CSDM_REG_NUM_OF_Q1_CMD                                  0xc224c
+/* [ST 32] The number of commands received in queue 3 */
+#define CSDM_REG_NUM_OF_Q3_CMD                                  0xc2250
+/* [ST 32] The number of commands received in queue 4 */
+#define CSDM_REG_NUM_OF_Q4_CMD                                  0xc2254
+/* [ST 32] The number of commands received in queue 5 */
+#define CSDM_REG_NUM_OF_Q5_CMD                                  0xc2258
+/* [ST 32] The number of commands received in queue 6 */
+#define CSDM_REG_NUM_OF_Q6_CMD                                  0xc225c
+/* [ST 32] The number of commands received in queue 7 */
+#define CSDM_REG_NUM_OF_Q7_CMD                                  0xc2260
+/* [ST 32] The number of commands received in queue 8 */
+#define CSDM_REG_NUM_OF_Q8_CMD                                  0xc2264
+/* [ST 32] The number of commands received in queue 9 */
+#define CSDM_REG_NUM_OF_Q9_CMD                                  0xc2268
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define CSDM_REG_Q_COUNTER_START_ADDR                           0xc2010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                       0xc2548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_PARSER_EMPTY                              0xc2550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define CSDM_REG_SYNC_SYNC_EMPTY                                0xc2558
+/* [RW 32] Tick for timer counter. Applicable only when
+   ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
+#define CSDM_REG_TIMER_TICK                                     0xc2000
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define CSEM_REG_ARB_CYCLE_SIZE                                 0x200034
+/* [RW 3] The source that is associated with arbitration element 0. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2 */
+#define CSEM_REG_ARB_ELEMENT0                                   0x200020
+/* [RW 3] The source that is associated with arbitration element 1. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
+#define CSEM_REG_ARB_ELEMENT1                                   0x200024
+/* [RW 3] The source that is associated with arbitration element 2. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~csem_registers_arb_element0.arb_element0
+   and ~csem_registers_arb_element1.arb_element1 */
+#define CSEM_REG_ARB_ELEMENT2                                   0x200028
+/* [RW 3] The source that is associated with arbitration element 3. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+   not be equal to register ~csem_registers_arb_element0.arb_element0 and
+   ~csem_registers_arb_element1.arb_element1 and
+   ~csem_registers_arb_element2.arb_element2 */
+#define CSEM_REG_ARB_ELEMENT3                                   0x20002c
+/* [RW 3] The source that is associated with arbitration element 4. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~csem_registers_arb_element0.arb_element0
+   and ~csem_registers_arb_element1.arb_element1 and
+   ~csem_registers_arb_element2.arb_element2 and
+   ~csem_registers_arb_element3.arb_element3 */
+#define CSEM_REG_ARB_ELEMENT4                                   0x200030
+/* [RW 32] Interrupt mask register #0 read/write */
+#define CSEM_REG_CSEM_INT_MASK_0                                0x200110
+#define CSEM_REG_CSEM_INT_MASK_1                                0x200120
+/* [R 32] Interrupt register #0 read */
+#define CSEM_REG_CSEM_INT_STS_0                                 0x200104
+#define CSEM_REG_CSEM_INT_STS_1                                 0x200114
+/* [RW 32] Parity mask register #0 read/write */
+#define CSEM_REG_CSEM_PRTY_MASK_0                               0x200130
+#define CSEM_REG_CSEM_PRTY_MASK_1                               0x200140
+/* [R 32] Parity register #0 read */
+#define CSEM_REG_CSEM_PRTY_STS_0                                0x200124
+#define CSEM_REG_CSEM_PRTY_STS_1                                0x200134
+#define CSEM_REG_ENABLE_IN                                      0x2000a4
+#define CSEM_REG_ENABLE_OUT                                     0x2000a8
+/* [RW 32] This address space contains all registers and memories that are
+   placed in SEM_FAST block. The SEM_FAST registers are described in
+   appendix B. In order to access the sem_fast registers the base address
+   ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
+#define CSEM_REG_FAST_MEMORY                                    0x220000
+/* [RW 1] Disables input messages from FIC0 May be updated during run_time
+   by the microcode */
+#define CSEM_REG_FIC0_DISABLE                                   0x200224
+/* [RW 1] Disables input messages from FIC1 May be updated during run_time
+   by the microcode */
+#define CSEM_REG_FIC1_DISABLE                                   0x200234
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+   the middle of the work */
+#define CSEM_REG_INT_TABLE                                      0x200400
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC0 */
+#define CSEM_REG_MSG_NUM_FIC0                                   0x200000
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC1 */
+#define CSEM_REG_MSG_NUM_FIC1                                   0x200004
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC0 */
+#define CSEM_REG_MSG_NUM_FOC0                                   0x200008
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC1 */
+#define CSEM_REG_MSG_NUM_FOC1                                   0x20000c
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC2 */
+#define CSEM_REG_MSG_NUM_FOC2                                   0x200010
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC3 */
+#define CSEM_REG_MSG_NUM_FOC3                                   0x200014
+/* [RW 1] Disables input messages from the passive buffer May be updated
+   during run_time by the microcode */
+#define CSEM_REG_PAS_DISABLE                                    0x20024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define CSEM_REG_PASSIVE_BUFFER                                 0x202000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define CSEM_REG_PRAM                                           0x240000
+/* [R 16] Valid sleeping threads indication have bit per thread */
+#define CSEM_REG_SLEEP_THREADS_VALID                            0x20026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define CSEM_REG_SLOW_EXT_STORE_EMPTY                           0x2002a0
+/* [RW 16] List of free threads . There is a bit per thread. */
+#define CSEM_REG_THREADS_LIST                                   0x2002e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define CSEM_REG_TS_0_AS                                        0x200038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define CSEM_REG_TS_10_AS                                       0x200060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define CSEM_REG_TS_11_AS                                       0x200064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define CSEM_REG_TS_12_AS                                       0x200068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define CSEM_REG_TS_13_AS                                       0x20006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define CSEM_REG_TS_14_AS                                       0x200070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define CSEM_REG_TS_15_AS                                       0x200074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define CSEM_REG_TS_16_AS                                       0x200078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define CSEM_REG_TS_17_AS                                       0x20007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define CSEM_REG_TS_18_AS                                       0x200080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define CSEM_REG_TS_1_AS                                        0x20003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define CSEM_REG_TS_2_AS                                        0x200040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define CSEM_REG_TS_3_AS                                        0x200044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define CSEM_REG_TS_4_AS                                        0x200048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define CSEM_REG_TS_5_AS                                        0x20004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define CSEM_REG_TS_6_AS                                        0x200050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define CSEM_REG_TS_7_AS                                        0x200054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define CSEM_REG_TS_8_AS                                        0x200058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define CSEM_REG_TS_9_AS                                        0x20005c
+/* [RW 1] Parity mask register #0 read/write */
+#define DBG_REG_DBG_PRTY_MASK                                   0xc0a8
+/* [R 1] Parity register #0 read */
+#define DBG_REG_DBG_PRTY_STS                                    0xc09c
+/* [RW 32] Commands memory. The address to command X; row Y is to calculated
+   as 14*X+Y. */
+#define DMAE_REG_CMD_MEM                                        0x102400
+#define DMAE_REG_CMD_MEM_SIZE                                   224
+/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
+   initial value is all ones. */
+#define DMAE_REG_CRC16C_INIT                                    0x10201c
+/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
+   CRC-16 T10 initial value is all ones. */
+#define DMAE_REG_CRC16T10_INIT                                  0x102020
+/* [RW 2] Interrupt mask register #0 read/write */
+#define DMAE_REG_DMAE_INT_MASK                                  0x102054
+/* [RW 4] Parity mask register #0 read/write */
+#define DMAE_REG_DMAE_PRTY_MASK                                 0x102064
+/* [R 4] Parity register #0 read */
+#define DMAE_REG_DMAE_PRTY_STS                                  0x102058
+/* [RW 1] Command 0 go. */
+#define DMAE_REG_GO_C0                                          0x102080
+/* [RW 1] Command 1 go. */
+#define DMAE_REG_GO_C1                                          0x102084
+/* [RW 1] Command 10 go. */
+#define DMAE_REG_GO_C10                                         0x102088
+/* [RW 1] Command 11 go. */
+#define DMAE_REG_GO_C11                                         0x10208c
+/* [RW 1] Command 12 go. */
+#define DMAE_REG_GO_C12                                         0x102090
+/* [RW 1] Command 13 go. */
+#define DMAE_REG_GO_C13                                         0x102094
+/* [RW 1] Command 14 go. */
+#define DMAE_REG_GO_C14                                         0x102098
+/* [RW 1] Command 15 go. */
+#define DMAE_REG_GO_C15                                         0x10209c
+/* [RW 1] Command 2 go. */
+#define DMAE_REG_GO_C2                                          0x1020a0
+/* [RW 1] Command 3 go. */
+#define DMAE_REG_GO_C3                                          0x1020a4
+/* [RW 1] Command 4 go. */
+#define DMAE_REG_GO_C4                                          0x1020a8
+/* [RW 1] Command 5 go. */
+#define DMAE_REG_GO_C5                                          0x1020ac
+/* [RW 1] Command 6 go. */
+#define DMAE_REG_GO_C6                                          0x1020b0
+/* [RW 1] Command 7 go. */
+#define DMAE_REG_GO_C7                                          0x1020b4
+/* [RW 1] Command 8 go. */
+#define DMAE_REG_GO_C8                                          0x1020b8
+/* [RW 1] Command 9 go. */
+#define DMAE_REG_GO_C9                                          0x1020bc
+/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
+   input is disregarded; valid is deasserted; all other signals are treated
+   as usual; if 1 - normal activity. */
+#define DMAE_REG_GRC_IFEN                                       0x102008
+/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
+   acknowledge input is disregarded; valid is deasserted; full is asserted;
+   all other signals are treated as usual; if 1 - normal activity. */
+#define DMAE_REG_PCI_IFEN                                       0x102004
+/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
+   initial value to the credit counter; related to the address. Read returns
+   the current value of the counter. */
+#define DMAE_REG_PXP_REQ_INIT_CRD                               0x1020c0
+/* [RW 8] Aggregation command. */
+#define DORQ_REG_AGG_CMD0                                       0x170060
+/* [RW 8] Aggregation command. */
+#define DORQ_REG_AGG_CMD1                                       0x170064
+/* [RW 8] Aggregation command. */
+#define DORQ_REG_AGG_CMD2                                       0x170068
+/* [RW 8] Aggregation command. */
+#define DORQ_REG_AGG_CMD3                                       0x17006c
+/* [RW 28] UCM Header. */
+#define DORQ_REG_CMHEAD_RX                                      0x170050
+/* [RW 32] Doorbell address for RBC doorbells (function 0). */
+#define DORQ_REG_DB_ADDR0                                       0x17008c
+/* [RW 5] Interrupt mask register #0 read/write */
+#define DORQ_REG_DORQ_INT_MASK                                  0x170180
+/* [R 5] Interrupt register #0 read */
+#define DORQ_REG_DORQ_INT_STS                                   0x170174
+/* [RC 5] Interrupt register #0 read clear */
+#define DORQ_REG_DORQ_INT_STS_CLR                               0x170178
+/* [RW 2] Parity mask register #0 read/write */
+#define DORQ_REG_DORQ_PRTY_MASK                                 0x170190
+/* [R 2] Parity register #0 read */
+#define DORQ_REG_DORQ_PRTY_STS                                  0x170184
+/* [RW 8] The address to write the DPM CID to STORM. */
+#define DORQ_REG_DPM_CID_ADDR                                   0x170044
+/* [RW 5] The DPM mode CID extraction offset. */
+#define DORQ_REG_DPM_CID_OFST                                   0x170030
+/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
+#define DORQ_REG_DQ_FIFO_AFULL_TH                               0x17007c
+/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
+#define DORQ_REG_DQ_FIFO_FULL_TH                                0x170078
+/* [R 13] Current value of the DQ FIFO fill level according to following
+   pointer. The range is 0 - 256 FIFO rows; where each row stands for the
+   doorbell. */
+#define DORQ_REG_DQ_FILL_LVLF                                   0x1700a4
+/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
+   equal to full threshold; reset on full clear. */
+#define DORQ_REG_DQ_FULL_ST                                     0x1700c0
+/* [RW 28] The value sent to CM header in the case of CFC load error. */
+#define DORQ_REG_ERR_CMHEAD                                     0x170058
+#define DORQ_REG_IF_EN                                          0x170004
+#define DORQ_REG_MODE_ACT                                       0x170008
+/* [RW 5] The normal mode CID extraction offset. */
+#define DORQ_REG_NORM_CID_OFST                                  0x17002c
+/* [RW 28] TCM Header when only TCP context is loaded. */
+#define DORQ_REG_NORM_CMHEAD_TX                                 0x17004c
+/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
+   Interface. */
+#define DORQ_REG_OUTST_REQ                                      0x17003c
+#define DORQ_REG_REGN                                           0x170038
+/* [R 4] Current value of response A counter credit. Initial credit is
+   configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+   register. */
+#define DORQ_REG_RSPA_CRD_CNT                                   0x1700ac
+/* [R 4] Current value of response B counter credit. Initial credit is
+   configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+   register. */
+#define DORQ_REG_RSPB_CRD_CNT                                   0x1700b0
+/* [RW 4] The initial credit at the Doorbell Response Interface. The write
+   writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
+   read reads this written value. */
+#define DORQ_REG_RSP_INIT_CRD                                   0x170048
+/* [RW 4] Initial activity counter value on the load request; when the
+   shortcut is done. */
+#define DORQ_REG_SHRT_ACT_CNT                                   0x170070
+/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
+#define DORQ_REG_SHRT_CMHEAD                                    0x170054
+#define HC_CONFIG_0_REG_ATTN_BIT_EN_0                           (0x1<<4)
+#define HC_CONFIG_0_REG_INT_LINE_EN_0                           (0x1<<3)
+#define HC_CONFIG_0_REG_MSI_ATTN_EN_0                           (0x1<<7)
+#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0                       (0x1<<2)
+#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0                         (0x1<<1)
+#define HC_REG_AGG_INT_0                                        0x108050
+#define HC_REG_AGG_INT_1                                        0x108054
+#define HC_REG_ATTN_BIT                                         0x108120
+#define HC_REG_ATTN_IDX                                         0x108100
+#define HC_REG_ATTN_MSG0_ADDR_L                                 0x108018
+#define HC_REG_ATTN_MSG1_ADDR_L                                 0x108020
+#define HC_REG_ATTN_NUM_P0                                      0x108038
+#define HC_REG_ATTN_NUM_P1                                      0x10803c
+#define HC_REG_COMMAND_REG                                      0x108180
+#define HC_REG_CONFIG_0                                         0x108000
+#define HC_REG_CONFIG_1                                         0x108004
+#define HC_REG_FUNC_NUM_P0                                      0x1080ac
+#define HC_REG_FUNC_NUM_P1                                      0x1080b0
+/* [RW 3] Parity mask register #0 read/write */
+#define HC_REG_HC_PRTY_MASK                                     0x1080a0
+/* [R 3] Parity register #0 read */
+#define HC_REG_HC_PRTY_STS                                      0x108094
+#define HC_REG_INT_MASK                                         0x108108
+#define HC_REG_LEADING_EDGE_0                                   0x108040
+#define HC_REG_LEADING_EDGE_1                                   0x108048
+#define HC_REG_P0_PROD_CONS                                     0x108200
+#define HC_REG_P1_PROD_CONS                                     0x108400
+#define HC_REG_PBA_COMMAND                                      0x108140
+#define HC_REG_PCI_CONFIG_0                                     0x108010
+#define HC_REG_PCI_CONFIG_1                                     0x108014
+#define HC_REG_STATISTIC_COUNTERS                               0x109000
+#define HC_REG_TRAILING_EDGE_0                                  0x108044
+#define HC_REG_TRAILING_EDGE_1                                  0x10804c
+#define HC_REG_UC_RAM_ADDR_0                                    0x108028
+#define HC_REG_UC_RAM_ADDR_1                                    0x108030
+#define HC_REG_USTORM_ADDR_FOR_COALESCE                         0x108068
+#define HC_REG_VQID_0                                           0x108008
+#define HC_REG_VQID_1                                           0x10800c
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE                          0x86424
+#define MCP_REG_MCPR_NVM_ADDR                                   0x8640c
+#define MCP_REG_MCPR_NVM_CFG4                                   0x8642c
+#define MCP_REG_MCPR_NVM_COMMAND                                0x86400
+#define MCP_REG_MCPR_NVM_READ                                   0x86410
+#define MCP_REG_MCPR_NVM_SW_ARB                                 0x86420
+#define MCP_REG_MCPR_NVM_WRITE                                  0x86408
+#define MCP_REG_MCPR_SCRATCH                                    0xa0000
+/* [R 32] read first 32 bit after inversion of function 0. mapped as
+   follows: [0] NIG attention for function0; [1] NIG attention for
+   function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
+   [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
+   GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
+   glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
+   [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
+   MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
+   Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
+   interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
+   error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
+   interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
+   Parity error; [31] PBF Hw interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0                      0xa42c
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1                      0xa430
+/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
+   NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+   mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+   [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+   PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+   function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+   Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+   mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+   BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+   Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+   interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+   Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
+   interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_1_MCP                         0xa434
+/* [R 32] read second 32 bit after inversion of function 0. mapped as
+   follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+   interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0                      0xa438
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1                      0xa43c
+/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
+   PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
+   [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
+   [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
+   XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+   DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+   error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+   PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+   [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+   [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+   [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+   [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
+#define MISC_REG_AEU_AFTER_INVERT_2_MCP                         0xa440
+/* [R 32] read third 32 bit after inversion of function 0. mapped as
+   follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
+   error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
+   PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+   attn1; */
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0                      0xa444
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1                      0xa448
+/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
+   CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
+   Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
+   Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
+   error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
+   interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
+   MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
+   Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
+   timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
+   func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
+   func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
+   timers attn_4 func1; [30] General attn0; [31] General attn1; */
+#define MISC_REG_AEU_AFTER_INVERT_3_MCP                         0xa44c
+/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
+   follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+   [14] General attn16; [15] General attn17; [16] General attn18; [17]
+   General attn19; [18] General attn20; [19] General attn21; [20] Main power
+   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+   Latched timeout attention; [27] GRC Latched reserved access attention;
+   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0                      0xa450
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1                      0xa454
+/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
+   General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
+   [4] General attn6; [5] General attn7; [6] General attn8; [7] General
+   attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
+   General attn13; [12] General attn14; [13] General attn15; [14] General
+   attn16; [15] General attn17; [16] General attn18; [17] General attn19;
+   [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
+   RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
+   RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
+   attention; [27] GRC Latched reserved access attention; [28] MCP Latched
+   rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
+   ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_AFTER_INVERT_4_MCP                         0xa458
+/* [W 14] write to this register results with the clear of the latched
+   signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
+   d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
+   latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
+   GRC Latched reserved access attention; one in d7 clears Latched
+   rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
+   Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
+   ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
+   pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
+   from this register return zero */
+#define MISC_REG_AEU_CLR_LATCH_SIGNAL                           0xa45c
+/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
+   as follows: [0] NIG attention for function0; [1] NIG attention for
+   function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+   0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+   SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0                       0xa06c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1                       0xa07c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2                       0xa08c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3                       0xa09c
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5                       0xa0bc
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6                       0xa0cc
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7                       0xa0dc
+/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
+   as follows: [0] NIG attention for function0; [1] NIG attention for
+   function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
+   1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+   SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
+   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0                       0xa10c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1                       0xa11c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2                       0xa12c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3                       0xa13c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5                       0xa15c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6                       0xa16c
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7                       0xa17c
+/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
+   as follows: [0] NIG attention for function0; [1] NIG attention for
+   function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+   0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+   SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
+#define MISC_REG_AEU_ENABLE1_NIG_0                              0xa0ec
+#define MISC_REG_AEU_ENABLE1_NIG_1                              0xa18c
+/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
+   as follows: [0] NIG attention for function0; [1] NIG attention for
+   function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+   0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+   SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
+#define MISC_REG_AEU_ENABLE1_PXP_0                              0xa0fc
+#define MISC_REG_AEU_ENABLE1_PXP_1                              0xa19c
+/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
+   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+   interrupt; */
+#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0                       0xa070
+#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1                       0xa080
+/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
+   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+   interrupt; */
+#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0                       0xa110
+#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1                       0xa120
+/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
+   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+   interrupt; */
+#define MISC_REG_AEU_ENABLE2_NIG_0                              0xa0f0
+#define MISC_REG_AEU_ENABLE2_NIG_1                              0xa190
+/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
+   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+   interrupt; */
+#define MISC_REG_AEU_ENABLE2_PXP_0                              0xa100
+#define MISC_REG_AEU_ENABLE2_PXP_1                              0xa1a0
+/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
+   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+   attn1; */
+#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0                       0xa074
+#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1                       0xa084
+/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
+   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+   attn1; */
+#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0                       0xa114
+#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1                       0xa124
+/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
+   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+   attn1; */
+#define MISC_REG_AEU_ENABLE3_NIG_0                              0xa0f4
+#define MISC_REG_AEU_ENABLE3_NIG_1                              0xa194
+/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
+   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+   attn1; */
+#define MISC_REG_AEU_ENABLE3_PXP_0                              0xa104
+#define MISC_REG_AEU_ENABLE3_PXP_1                              0xa1a4
+/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
+   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+   [14] General attn16; [15] General attn17; [16] General attn18; [17]
+   General attn19; [18] General attn20; [19] General attn21; [20] Main power
+   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+   Latched timeout attention; [27] GRC Latched reserved access attention;
+   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0                       0xa078
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2                       0xa098
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4                       0xa0b8
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5                       0xa0c8
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6                       0xa0d8
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7                       0xa0e8
+/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
+   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+   [14] General attn16; [15] General attn17; [16] General attn18; [17]
+   General attn19; [18] General attn20; [19] General attn21; [20] Main power
+   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+   Latched timeout attention; [27] GRC Latched reserved access attention;
+   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0                       0xa118
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2                       0xa138
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4                       0xa158
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5                       0xa168
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6                       0xa178
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7                       0xa188
+/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
+   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+   [14] General attn16; [15] General attn17; [16] General attn18; [17]
+   General attn19; [18] General attn20; [19] General attn21; [20] Main power
+   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+   Latched timeout attention; [27] GRC Latched reserved access attention;
+   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_NIG_0                              0xa0f8
+#define MISC_REG_AEU_ENABLE4_NIG_1                              0xa198
+/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
+   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+   [14] General attn16; [15] General attn17; [16] General attn18; [17]
+   General attn19; [18] General attn20; [19] General attn21; [20] Main power
+   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+   Latched timeout attention; [27] GRC Latched reserved access attention;
+   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
+#define MISC_REG_AEU_ENABLE4_PXP_0                              0xa108
+#define MISC_REG_AEU_ENABLE4_PXP_1                              0xa1a8
+/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
+   128 bit vector */
+#define MISC_REG_AEU_GENERAL_ATTN_0                             0xa000
+#define MISC_REG_AEU_GENERAL_ATTN_1                             0xa004
+#define MISC_REG_AEU_GENERAL_ATTN_10                            0xa028
+#define MISC_REG_AEU_GENERAL_ATTN_11                            0xa02c
+#define MISC_REG_AEU_GENERAL_ATTN_12                            0xa030
+#define MISC_REG_AEU_GENERAL_ATTN_2                             0xa008
+#define MISC_REG_AEU_GENERAL_ATTN_3                             0xa00c
+#define MISC_REG_AEU_GENERAL_ATTN_4                             0xa010
+#define MISC_REG_AEU_GENERAL_ATTN_5                             0xa014
+#define MISC_REG_AEU_GENERAL_ATTN_6                             0xa018
+#define MISC_REG_AEU_GENERAL_ATTN_7                             0xa01c
+#define MISC_REG_AEU_GENERAL_ATTN_8                             0xa020
+#define MISC_REG_AEU_GENERAL_ATTN_9                             0xa024
+#define MISC_REG_AEU_GENERAL_MASK                               0xa61c
+/* [RW 32] first 32b for inverting the input for function 0; for each bit:
+   0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
+   function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
+   [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
+   [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+   SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
+   for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
+   Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
+   interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
+   Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
+   Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
+#define MISC_REG_AEU_INVERTER_1_FUNC_0                          0xa22c
+#define MISC_REG_AEU_INVERTER_1_FUNC_1                          0xa23c
+/* [RW 32] second 32b for inverting the input for function 0; for each bit:
+   0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
+   error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
+   interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
+   Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
+   interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+   DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+   error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+   PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+   [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+   [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+   [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+   [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
+#define MISC_REG_AEU_INVERTER_2_FUNC_0                          0xa230
+#define MISC_REG_AEU_INVERTER_2_FUNC_1                          0xa240
+/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
+   [9:8] = raserved. Zero = mask; one = unmask */
+#define MISC_REG_AEU_MASK_ATTN_FUNC_0                           0xa060
+#define MISC_REG_AEU_MASK_ATTN_FUNC_1                           0xa064
+/* [RW 1] If set a system kill occurred */
+#define MISC_REG_AEU_SYS_KILL_OCCURRED                          0xa610
+/* [RW 32] Represent the status of the input vector to the AEU when a system
+   kill occurred. The register is reset in por reset. Mapped as follows: [0]
+   NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+   mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+   [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+   PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+   function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+   Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+   mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+   BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+   Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+   interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+   Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
+   interrupt; */
+#define MISC_REG_AEU_SYS_KILL_STATUS_0                          0xa600
+#define MISC_REG_AEU_SYS_KILL_STATUS_1                          0xa604
+#define MISC_REG_AEU_SYS_KILL_STATUS_2                          0xa608
+#define MISC_REG_AEU_SYS_KILL_STATUS_3                          0xa60c
+/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
+   Port. */
+#define MISC_REG_BOND_ID                                        0xa400
+/* [R 8] These bits indicate the metal revision of the chip. This value
+   starts at 0x00 for each all-layer tape-out and increments by one for each
+   tape-out. */
+#define MISC_REG_CHIP_METAL                                     0xa404
+/* [R 16] These bits indicate the part number for the chip. */
+#define MISC_REG_CHIP_NUM                                       0xa408
+/* [R 4] These bits indicate the base revision of the chip. This value
+   starts at 0x0 for the A0 tape-out and increments by one for each
+   all-layer tape-out. */
+#define MISC_REG_CHIP_REV                                       0xa40c
+/* [RW 32] The following driver registers(1...16) represent 16 drivers and
+   32 clients. Each client can be controlled by one driver only. One in each
+   bit represent that this driver control the appropriate client (Ex: bit 5
+   is set means this driver control client number 5). addr1 = set; addr0 =
+   clear; read from both addresses will give the same result = status. write
+   to address 1 will set a request to control all the clients that their
+   appropriate bit (in the write command) is set. if the client is free (the
+   appropriate bit in all the other drivers is clear) one will be written to
+   that driver register; if the client isn't free the bit will remain zero.
+   if the appropriate bit is set (the driver request to gain control on a
+   client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
+   interrupt will be asserted). write to address 0 will set a request to
+   free all the clients that their appropriate bit (in the write command) is
+   set. if the appropriate bit is clear (the driver request to free a client
+   it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
+   be asserted). */
+#define MISC_REG_DRIVER_CONTROL_1                               0xa510
+#define MISC_REG_DRIVER_CONTROL_7                               0xa3c8
+/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
+   only. */
+#define MISC_REG_E1HMF_MODE                                     0xa5f8
+/* [RW 32] Debug only: spare RW register reset by core reset */
+#define MISC_REG_GENERIC_CR_0                                   0xa460
+/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
+   these bits is written as a '1'; the corresponding SPIO bit will turn off
+   it's drivers and become an input. This is the reset state of all GPIO
+   pins. The read value of these bits will be a '1' if that last command
+   (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
+   [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
+   as a '1'; the corresponding GPIO bit will drive low. The read value of
+   these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
+   this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
+   SET When any of these bits is written as a '1'; the corresponding GPIO
+   bit will drive high (if it has that capability). The read value of these
+   bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
+   bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
+   RO; These bits indicate the read value of each of the eight GPIO pins.
+   This is the result value of the pin; not the drive value. Writing these
+   bits will have not effect. */
+#define MISC_REG_GPIO                                           0xa490
+/* [RW 8] These bits enable the GPIO_INTs to signals event to the
+   IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
+   p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
+   [7] p1_gpio_3; */
+#define MISC_REG_GPIO_EVENT_EN                                  0xa2bc
+/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
+   '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
+   This will acknowledge an interrupt on the falling edge of corresponding
+   GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
+   Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
+   register. This will acknowledge an interrupt on the rising edge of
+   corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
+   OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
+   value. When the ~INT_STATE bit is set; this bit indicates the OLD value
+   of the pin such that if ~INT_STATE is set and this bit is '0'; then the
+   interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
+   is '1'; then the interrupt is due to a high to low edge (reset value 0).
+   [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
+   current GPIO interrupt state for each GPIO pin. This bit is cleared when
+   the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
+   set when the GPIO input does not match the current value in #OLD_VALUE
+   (reset value 0). */
+#define MISC_REG_GPIO_INT                                       0xa494
+/* [R 28] this field hold the last information that caused reserved
+   attention. bits [19:0] - address; [22:20] function; [23] reserved;
+   [27:24] the master that caused the attention - according to the following
+   encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+   dbu; 8 = dmae */
+#define MISC_REG_GRC_RSV_ATTN                                   0xa3c0
+/* [R 28] this field hold the last information that caused timeout
+   attention. bits [19:0] - address; [22:20] function; [23] reserved;
+   [27:24] the master that caused the attention - according to the following
+   encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+   dbu; 8 = dmae */
+#define MISC_REG_GRC_TIMEOUT_ATTN                               0xa3c4
+/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
+   access that does not finish within
+   ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
+   cleared; this timeout is disabled. If this timeout occurs; the GRC shall
+   assert it attention output. */
+#define MISC_REG_GRC_TIMEOUT_EN                                 0xa280
+/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
+   the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
+   111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
+   (reset value 001) Charge pump current control; 111 for 720u; 011 for
+   600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
+   Global bias control; When bit 7 is high bias current will be 10 0gh; When
+   bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
+   Pll_observe (reset value 010) Bits to control observability. bit 10 is
+   for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
+   (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
+   and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
+   sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
+   internally). [14] reserved (reset value 0) Reset for VCO sequencer is
+   connected to RESET input directly. [15] capRetry_en (reset value 0)
+   enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
+   value 0) bit to continuously monitor vco freq (inverted). [17]
+   freqDetRestart_en (reset value 0) bit to enable restart when not freq
+   locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
+   retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
+   0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
+   pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
+   (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
+   0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
+   bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
+   enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
+   capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
+   restart. [27] capSelectM_en (reset value 0) bit to enable cap select
+   register bits. */
+#define MISC_REG_LCPLL_CTRL_1                                   0xa2a4
+#define MISC_REG_LCPLL_CTRL_REG_2                               0xa2a8
+/* [RW 4] Interrupt mask register #0 read/write */
+#define MISC_REG_MISC_INT_MASK                                  0xa388
+/* [RW 1] Parity mask register #0 read/write */
+#define MISC_REG_MISC_PRTY_MASK                                 0xa398
+/* [R 1] Parity register #0 read */
+#define MISC_REG_MISC_PRTY_STS                                  0xa38c
+#define MISC_REG_NIG_WOL_P0                                     0xa270
+#define MISC_REG_NIG_WOL_P1                                     0xa274
+/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
+   assertion */
+#define MISC_REG_PCIE_HOT_RESET                                 0xa618
+/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
+   inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
+   divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
+   divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
+   divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
+   divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
+   freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
+   (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
+   1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
+   Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
+   value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
+   1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
+   [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
+   Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
+   testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
+   testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
+   testa_en (reset value 0); */
+#define MISC_REG_PLL_STORM_CTRL_1                               0xa294
+#define MISC_REG_PLL_STORM_CTRL_2                               0xa298
+#define MISC_REG_PLL_STORM_CTRL_3                               0xa29c
+#define MISC_REG_PLL_STORM_CTRL_4                               0xa2a0
+/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
+   write/read zero = the specific block is in reset; addr 0-wr- the write
+   value will be written to the register; addr 1-set - one will be written
+   to all the bits that have the value of one in the data written (bits that
+   have the value of zero will not be change) ; addr 2-clear - zero will be
+   written to all the bits that have the value of one in the data written
+   (bits that have the value of zero will not be change); addr 3-ignore;
+   read ignore from all addr except addr 00; inside order of the bits is:
+   [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
+   [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
+   rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
+   [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
+   Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
+   rst_pxp_rq_rd_wr; 31:17] reserved */
+#define MISC_REG_RESET_REG_2                                    0xa590
+/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
+   shared with the driver resides */
+#define MISC_REG_SHARED_MEM_ADDR                                0xa2b4
+/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
+   the corresponding SPIO bit will turn off it's drivers and become an
+   input. This is the reset state of all SPIO pins. The read value of these
+   bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
+   bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
+   is written as a '1'; the corresponding SPIO bit will drive low. The read
+   value of these bits will be a '1' if that last command (#SET; #CLR; or
+#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
+   these bits is written as a '1'; the corresponding SPIO bit will drive
+   high (if it has that capability). The read value of these bits will be a
+   '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
+   (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
+   each of the eight SPIO pins. This is the result value of the pin; not the
+   drive value. Writing these bits will have not effect. Each 8 bits field
+   is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
+   from VAUX. (This is an output pin only; the FLOAT field is not applicable
+   for this pin); [1] VAUX Disable; when pulsed low; disables supply form
+   VAUX. (This is an output pin only; FLOAT field is not applicable for this
+   pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
+   select VAUX supply. (This is an output pin only; it is not controlled by
+   the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
+   field is not applicable for this pin; only the VALUE fields is relevant -
+   it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
+   Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
+   device ID select; read by UMP firmware. */
+#define MISC_REG_SPIO                                           0xa4fc
+/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
+   according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
+   [7:0] reserved */
+#define MISC_REG_SPIO_EVENT_EN                                  0xa2b8
+/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
+   corresponding bit in the #OLD_VALUE register. This will acknowledge an
+   interrupt on the falling edge of corresponding SPIO input (reset value
+   0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
+   in the #OLD_VALUE register. This will acknowledge an interrupt on the
+   rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
+   RO; These bits indicate the old value of the SPIO input value. When the
+   ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
+   that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
+   to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
+   interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
+   RO; These bits indicate the current SPIO interrupt state for each SPIO
+   pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
+   command bit is written. This bit is set when the SPIO input does not
+   match the current value in #OLD_VALUE (reset value 0). */
+#define MISC_REG_SPIO_INT                                       0xa500
+/* [RW 32] reload value for counter 4 if reload; the value will be reload if
+   the counter reached zero and the reload bit
+   (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
+#define MISC_REG_SW_TIMER_RELOAD_VAL_4                          0xa2fc
+/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
+   in this register. addres 0 - timer 1; address - timer 2�address 7 -
+   timer 8 */
+#define MISC_REG_SW_TIMER_VAL                                   0xa5c0
+/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
+   loaded; 0-prepare; -unprepare */
+#define MISC_REG_UNPREPARED                                     0xa424
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT     (0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS   (0x1<<9)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G         (0x1<<15)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS     (0xf<<18)
+/* [RW 1] Input enable for RX_BMAC0 IF */
+#define NIG_REG_BMAC0_IN_EN                                     0x100ac
+/* [RW 1] output enable for TX_BMAC0 IF */
+#define NIG_REG_BMAC0_OUT_EN                                    0x100e0
+/* [RW 1] output enable for TX BMAC pause port 0 IF */
+#define NIG_REG_BMAC0_PAUSE_OUT_EN                              0x10110
+/* [RW 1] output enable for RX_BMAC0_REGS IF */
+#define NIG_REG_BMAC0_REGS_OUT_EN                               0x100e8
+/* [RW 1] output enable for RX BRB1 port0 IF */
+#define NIG_REG_BRB0_OUT_EN                                     0x100f8
+/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
+#define NIG_REG_BRB0_PAUSE_IN_EN                                0x100c4
+/* [RW 1] output enable for RX BRB1 port1 IF */
+#define NIG_REG_BRB1_OUT_EN                                     0x100fc
+/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
+#define NIG_REG_BRB1_PAUSE_IN_EN                                0x100c8
+/* [RW 1] output enable for RX BRB1 LP IF */
+#define NIG_REG_BRB_LB_OUT_EN                                   0x10100
+/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
+   error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
+   72:73]-vnic_num; 81:74]-sideband_info */
+#define NIG_REG_DEBUG_PACKET_LB                                 0x10800
+/* [RW 1] Input enable for TX Debug packet */
+#define NIG_REG_EGRESS_DEBUG_IN_EN                              0x100dc
+/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
+   packets from PBFare not forwarded to the MAC and just deleted from FIFO.
+   First packet may be deleted from the middle. And last packet will be
+   always deleted till the end. */
+#define NIG_REG_EGRESS_DRAIN0_MODE                              0x10060
+/* [RW 1] Output enable to EMAC0 */
+#define NIG_REG_EGRESS_EMAC0_OUT_EN                             0x10120
+/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
+   to emac for port0; other way to bmac for port0 */
+#define NIG_REG_EGRESS_EMAC0_PORT                               0x10058
+/* [RW 1] Input enable for TX PBF user packet port0 IF */
+#define NIG_REG_EGRESS_PBF0_IN_EN                               0x100cc
+/* [RW 1] Input enable for TX PBF user packet port1 IF */
+#define NIG_REG_EGRESS_PBF1_IN_EN                               0x100d0
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN                               0x100d4
+/* [RW 1] Input enable for RX_EMAC0 IF */
+#define NIG_REG_EMAC0_IN_EN                                     0x100a4
+/* [RW 1] output enable for TX EMAC pause port 0 IF */
+#define NIG_REG_EMAC0_PAUSE_OUT_EN                              0x10118
+/* [R 1] status from emac0. This bit is set when MDINT from either the
+   EXT_MDINT pin or from the Copper PHY is driven low. This condition must
+   be cleared in the attached PHY device that is driving the MINT pin. */
+#define NIG_REG_EMAC0_STATUS_MISC_MI_INT                        0x10494
+/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
+   are described in appendix A. In order to access the BMAC0 registers; the
+   base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
+   added to each BMAC register offset */
+#define NIG_REG_INGRESS_BMAC0_MEM                               0x10c00
+/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
+   are described in appendix A. In order to access the BMAC0 registers; the
+   base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
+   added to each BMAC register offset */
+#define NIG_REG_INGRESS_BMAC1_MEM                               0x11000
+/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
+#define NIG_REG_INGRESS_EOP_LB_EMPTY                            0x104e0
+/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
+   packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
+#define NIG_REG_INGRESS_EOP_LB_FIFO                             0x104e4
+/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
+   logic for interrupts must be used. Enable per bit of interrupt of
+   ~latch_status.latch_status */
+#define NIG_REG_LATCH_BC_0                                      0x16210
+/* [RW 27] Latch for each interrupt from Unicore.b[0]
+   status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+   b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+   b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+   b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+   b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+   b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+   b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+   b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+   b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+   b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+   b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+   b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
+#define NIG_REG_LATCH_STATUS_0                                  0x18000
+/* [RW 1] led 10g for port 0 */
+#define NIG_REG_LED_10G_P0                                      0x10320
+/* [RW 1] led 10g for port 1 */
+#define NIG_REG_LED_10G_P1                                      0x10324
+/* [RW 1] Port0: This bit is set to enable the use of the
+   ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
+   defined below. If this bit is cleared; then the blink rate will be about
+   8Hz. */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0                   0x10318
+/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
+   Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
+   is reset to 0x080; giving a default blink period of approximately 8Hz. */
+#define NIG_REG_LED_CONTROL_BLINK_RATE_P0                       0x10310
+/* [RW 1] Port0: If set along with the
+ ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
+   bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
+   bit; the Traffic LED will blink with the blink rate specified in
+   ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+   ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+   fields. */
+#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0                    0x10308
+/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
+   Traffic LED will then be controlled via bit ~nig_registers_
+   led_control_traffic_p0.led_control_traffic_p0 and bit
+   ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
+#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0                 0x102f8
+/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
+   turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
+   set; the LED will blink with blink rate specified in
+   ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+   ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+   fields. */
+#define NIG_REG_LED_CONTROL_TRAFFIC_P0                          0x10300
+/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
+   9-11PHY7; 12 MAC4; 13-15 PHY10; */
+#define NIG_REG_LED_MODE_P0                                     0x102f0
+/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
+   tsdm enable; b2- usdm enable */
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0                        0x16070
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1                        0x16074
+/* [RW 1] SAFC enable for port0. This register may get 1 only when
+   ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
+   port */
+#define NIG_REG_LLFC_ENABLE_0                                   0x16208
+/* [RW 16] classes are high-priority for port0 */
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0                    0x16058
+/* [RW 16] classes are low-priority for port0 */
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0                     0x16060
+/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
+#define NIG_REG_LLFC_OUT_EN_0                                   0x160c8
+#define NIG_REG_LLH0_ACPI_PAT_0_CRC                             0x1015c
+#define NIG_REG_LLH0_ACPI_PAT_6_LEN                             0x10154
+#define NIG_REG_LLH0_BRB1_DRV_MASK                              0x10244
+#define NIG_REG_LLH0_BRB1_DRV_MASK_MF                           0x16048
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH0_BRB1_NOT_MCP                               0x1025c
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+   classification upon VLAN id. 2: classification upon MAC address. 3:
+   classification upon both VLAN id & MAC addr. */
+#define NIG_REG_LLH0_CLS_TYPE                                   0x16080
+/* [RW 32] cm header for llh0 */
+#define NIG_REG_LLH0_CM_HEADER                                  0x1007c
+#define NIG_REG_LLH0_DEST_IP_0_1                                0x101dc
+#define NIG_REG_LLH0_DEST_MAC_0_0                               0x101c0
+/* [RW 16] destination TCP address 1. The LLH will look for this address in
+   all incoming packets. */
+#define NIG_REG_LLH0_DEST_TCP_0                                 0x10220
+/* [RW 16] destination UDP address 1 The LLH will look for this address in
+   all incoming packets. */
+#define NIG_REG_LLH0_DEST_UDP_0                                 0x10214
+#define NIG_REG_LLH0_ERROR_MASK                                 0x1008c
+/* [RW 8] event id for llh0 */
+#define NIG_REG_LLH0_EVENT_ID                                   0x10084
+#define NIG_REG_LLH0_FUNC_EN                                    0x160fc
+#define NIG_REG_LLH0_FUNC_VLAN_ID                               0x16100
+/* [RW 1] Determine the IP version to look for in
+   ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
+#define NIG_REG_LLH0_IPV4_IPV6_0                                0x10208
+/* [RW 1] t bit for llh0 */
+#define NIG_REG_LLH0_T_BIT                                      0x10074
+/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
+#define NIG_REG_LLH0_VLAN_ID_0                                  0x1022c
+/* [RW 8] init credit counter for port0 in LLH */
+#define NIG_REG_LLH0_XCM_INIT_CREDIT                            0x10554
+#define NIG_REG_LLH0_XCM_MASK                                   0x10130
+#define NIG_REG_LLH1_BRB1_DRV_MASK                              0x10248
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define NIG_REG_LLH1_BRB1_NOT_MCP                               0x102dc
+/* [RW 2] Determine the classification participants. 0: no classification.1:
+   classification upon VLAN id. 2: classification upon MAC address. 3:
+   classification upon both VLAN id & MAC addr. */
+#define NIG_REG_LLH1_CLS_TYPE                                   0x16084
+/* [RW 32] cm header for llh1 */
+#define NIG_REG_LLH1_CM_HEADER                                  0x10080
+#define NIG_REG_LLH1_ERROR_MASK                                 0x10090
+/* [RW 8] event id for llh1 */
+#define NIG_REG_LLH1_EVENT_ID                                   0x10088
+/* [RW 8] init credit counter for port1 in LLH */
+#define NIG_REG_LLH1_XCM_INIT_CREDIT                            0x10564
+#define NIG_REG_LLH1_XCM_MASK                                   0x10134
+/* [RW 1] When this bit is set; the LLH will expect all packets to be with
+   e1hov */
+#define NIG_REG_LLH_E1HOV_MODE                                  0x160d8
+/* [RW 1] When this bit is set; the LLH will classify the packet before
+   sending it to the BRB or calculating WoL on it. */
+#define NIG_REG_LLH_MF_MODE                                     0x16024
+#define NIG_REG_MASK_INTERRUPT_PORT0                            0x10330
+#define NIG_REG_MASK_INTERRUPT_PORT1                            0x10334
+/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
+#define NIG_REG_NIG_EMAC0_EN                                    0x1003c
+/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
+#define NIG_REG_NIG_EMAC1_EN                                    0x10040
+/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
+   EMAC0 to strip the CRC from the ingress packets. */
+#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC                        0x10044
+/* [R 32] Interrupt register #0 read */
+#define NIG_REG_NIG_INT_STS_0                                   0x103b0
+#define NIG_REG_NIG_INT_STS_1                                   0x103c0
+/* [R 32] Parity register #0 read */
+#define NIG_REG_NIG_PRTY_STS                                    0x103d0
+/* [RW 1] Pause enable for port0. This register may get 1 only when
+   ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
+   port */
+#define NIG_REG_PAUSE_ENABLE_0                                  0x160c0
+/* [RW 1] Input enable for RX PBF LP IF */
+#define NIG_REG_PBF_LB_IN_EN                                    0x100b4
+/* [RW 1] Value of this register will be transmitted to port swap when
+   ~nig_registers_strap_override.strap_override =1 */
+#define NIG_REG_PORT_SWAP                                       0x10394
+/* [RW 1] output enable for RX parser descriptor IF */
+#define NIG_REG_PRS_EOP_OUT_EN                                  0x10104
+/* [RW 1] Input enable for RX parser request IF */
+#define NIG_REG_PRS_REQ_IN_EN                                   0x100b8
+/* [RW 5] control to serdes - CL45 DEVAD */
+#define NIG_REG_SERDES0_CTRL_MD_DEVAD                           0x10370
+/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_SERDES0_CTRL_MD_ST                              0x1036c
+/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_SERDES0_CTRL_PHY_ADDR                           0x10374
+/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
+#define NIG_REG_SERDES0_STATUS_LINK_STATUS                      0x10578
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+   for port0 */
+#define NIG_REG_STAT0_BRB_DISCARD                               0x105f0
+/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
+   for port0 */
+#define NIG_REG_STAT0_BRB_TRUNCATE                              0x105f8
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+   between 1024 and 1522 bytes for port0 */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT0                           0x10750
+/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
+   between 1523 bytes and above for port0 */
+#define NIG_REG_STAT0_EGRESS_MAC_PKT1                           0x10760
+/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
+   for port1 */
+#define NIG_REG_STAT1_BRB_DISCARD                               0x10628
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+   between 1024 and 1522 bytes for port1 */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT0                           0x107a0
+/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
+   between 1523 bytes and above for port1 */
+#define NIG_REG_STAT1_EGRESS_MAC_PKT1                           0x107b0
+/* [WB_R 64] Rx statistics : User octets received for LP */
+#define NIG_REG_STAT2_BRB_OCTET                                 0x107e0
+#define NIG_REG_STATUS_INTERRUPT_PORT0                          0x10328
+#define NIG_REG_STATUS_INTERRUPT_PORT1                          0x1032c
+/* [RW 1] port swap mux selection. If this register equal to 0 then port
+   swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
+   ort swap is equal to ~nig_registers_port_swap.port_swap */
+#define NIG_REG_STRAP_OVERRIDE                                  0x10398
+/* [RW 1] output enable for RX_XCM0 IF */
+#define NIG_REG_XCM0_OUT_EN                                     0x100f0
+/* [RW 1] output enable for RX_XCM1 IF */
+#define NIG_REG_XCM1_OUT_EN                                     0x100f4
+/* [RW 1] control to xgxs - remote PHY in-band MDIO */
+#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST                      0x10348
+/* [RW 5] control to xgxs - CL45 DEVAD */
+#define NIG_REG_XGXS0_CTRL_MD_DEVAD                             0x1033c
+/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
+#define NIG_REG_XGXS0_CTRL_MD_ST                                0x10338
+/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
+#define NIG_REG_XGXS0_CTRL_PHY_ADDR                             0x10340
+/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
+#define NIG_REG_XGXS0_STATUS_LINK10G                            0x10680
+/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
+#define NIG_REG_XGXS0_STATUS_LINK_STATUS                        0x10684
+/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
+#define NIG_REG_XGXS_LANE_SEL_P0                                0x102e8
+/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
+#define NIG_REG_XGXS_SERDES0_MODE_SEL                           0x102e0
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT  (0x1<<0)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G     (0x1<<15)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS  (0xf<<18)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
+/* [RW 1] Disable processing further tasks from port 0 (after ending the
+   current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P0                        0x14005c
+/* [RW 1] Disable processing further tasks from port 1 (after ending the
+   current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P1                        0x140060
+/* [RW 1] Disable processing further tasks from port 4 (after ending the
+   current task in process). */
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P4                        0x14006c
+#define PBF_REG_IF_ENABLE_REG                                   0x140044
+/* [RW 1] Init bit. When set the initial credits are copied to the credit
+   registers (except the port credits). Should be set and then reset after
+   the configuration of the block has ended. */
+#define PBF_REG_INIT                                            0x140000
+/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
+   copied to the credit register. Should be set and then reset after the
+   configuration of the port has ended. */
+#define PBF_REG_INIT_P0                                         0x140004
+/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
+   copied to the credit register. Should be set and then reset after the
+   configuration of the port has ended. */
+#define PBF_REG_INIT_P1                                         0x140008
+/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
+   copied to the credit register. Should be set and then reset after the
+   configuration of the port has ended. */
+#define PBF_REG_INIT_P4                                         0x14000c
+/* [RW 1] Enable for mac interface 0. */
+#define PBF_REG_MAC_IF0_ENABLE                                  0x140030
+/* [RW 1] Enable for mac interface 1. */
+#define PBF_REG_MAC_IF1_ENABLE                                  0x140034
+/* [RW 1] Enable for the loopback interface. */
+#define PBF_REG_MAC_LB_ENABLE                                   0x140040
+/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
+   not suppoterd. */
+#define PBF_REG_P0_ARB_THRSH                                    0x1400e4
+/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
+#define PBF_REG_P0_CREDIT                                       0x140200
+/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
+   lines. */
+#define PBF_REG_P0_INIT_CRD                                     0x1400d0
+/* [RW 1] Indication that pause is enabled for port 0. */
+#define PBF_REG_P0_PAUSE_ENABLE                                 0x140014
+/* [R 8] Number of tasks in port 0 task queue. */
+#define PBF_REG_P0_TASK_CNT                                     0x140204
+/* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
+#define PBF_REG_P1_CREDIT                                       0x140208
+/* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
+   lines. */
+#define PBF_REG_P1_INIT_CRD                                     0x1400d4
+/* [R 8] Number of tasks in port 1 task queue. */
+#define PBF_REG_P1_TASK_CNT                                     0x14020c
+/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
+#define PBF_REG_P4_CREDIT                                       0x140210
+/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
+   lines. */
+#define PBF_REG_P4_INIT_CRD                                     0x1400e0
+/* [R 8] Number of tasks in port 4 task queue. */
+#define PBF_REG_P4_TASK_CNT                                     0x140214
+/* [RW 5] Interrupt mask register #0 read/write */
+#define PBF_REG_PBF_INT_MASK                                    0x1401d4
+/* [R 5] Interrupt register #0 read */
+#define PBF_REG_PBF_INT_STS                                     0x1401c8
+#define PB_REG_CONTROL                                          0
+/* [RW 2] Interrupt mask register #0 read/write */
+#define PB_REG_PB_INT_MASK                                      0x28
+/* [R 2] Interrupt register #0 read */
+#define PB_REG_PB_INT_STS                                       0x1c
+/* [RW 4] Parity mask register #0 read/write */
+#define PB_REG_PB_PRTY_MASK                                     0x38
+/* [R 4] Parity register #0 read */
+#define PB_REG_PB_PRTY_STS                                      0x2c
+#define PRS_REG_A_PRSU_20                                       0x40134
+/* [R 8] debug only: CFC load request current credit. Transaction based. */
+#define PRS_REG_CFC_LD_CURRENT_CREDIT                           0x40164
+/* [R 8] debug only: CFC search request current credit. Transaction based. */
+#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT                       0x40168
+/* [RW 6] The initial credit for the search message to the CFC interface.
+   Credit is transaction based. */
+#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT                       0x4011c
+/* [RW 24] CID for port 0 if no match */
+#define PRS_REG_CID_PORT_0                                      0x400fc
+/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
+   load response is reset and packet type is 0. Used in packet start message
+   to TCM. */
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0                        0x400dc
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1                        0x400e0
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2                        0x400e4
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3                        0x400e8
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4                        0x400ec
+#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5                        0x400f0
+/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
+   load response is set and packet type is 0. Used in packet start message
+   to TCM. */
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0                     0x400bc
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1                     0x400c0
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2                     0x400c4
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3                     0x400c8
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4                     0x400cc
+#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5                     0x400d0
+/* [RW 32] The CM header for a match and packet type 1 for loopback port.
+   Used in packet start message to TCM. */
+#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1                          0x4009c
+#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2                          0x400a0
+#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3                          0x400a4
+#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4                          0x400a8
+/* [RW 32] The CM header for a match and packet type 0. Used in packet start
+   message to TCM. */
+#define PRS_REG_CM_HDR_TYPE_0                                   0x40078
+#define PRS_REG_CM_HDR_TYPE_1                                   0x4007c
+#define PRS_REG_CM_HDR_TYPE_2                                   0x40080
+#define PRS_REG_CM_HDR_TYPE_3                                   0x40084
+#define PRS_REG_CM_HDR_TYPE_4                                   0x40088
+/* [RW 32] The CM header in case there was not a match on the connection */
+#define PRS_REG_CM_NO_MATCH_HDR                                 0x400b8
+/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
+#define PRS_REG_E1HOV_MODE                                      0x401c8
+/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
+   start message to TCM. */
+#define PRS_REG_EVENT_ID_1                                      0x40054
+#define PRS_REG_EVENT_ID_2                                      0x40058
+#define PRS_REG_EVENT_ID_3                                      0x4005c
+/* [RW 16] The Ethernet type value for FCoE */
+#define PRS_REG_FCOE_TYPE                                       0x401d0
+/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
+   load request message. */
+#define PRS_REG_FLUSH_REGIONS_TYPE_0                            0x40004
+#define PRS_REG_FLUSH_REGIONS_TYPE_1                            0x40008
+#define PRS_REG_FLUSH_REGIONS_TYPE_2                            0x4000c
+#define PRS_REG_FLUSH_REGIONS_TYPE_3                            0x40010
+#define PRS_REG_FLUSH_REGIONS_TYPE_4                            0x40014
+#define PRS_REG_FLUSH_REGIONS_TYPE_5                            0x40018
+#define PRS_REG_FLUSH_REGIONS_TYPE_6                            0x4001c
+#define PRS_REG_FLUSH_REGIONS_TYPE_7                            0x40020
+/* [RW 4] The increment value to send in the CFC load request message */
+#define PRS_REG_INC_VALUE                                       0x40048
+/* [RW 1] If set indicates not to send messages to CFC on received packets */
+#define PRS_REG_NIC_MODE                                        0x40138
+/* [RW 8] The 8-bit event ID for cases where there is no match on the
+   connection. Used in packet start message to TCM. */
+#define PRS_REG_NO_MATCH_EVENT_ID                               0x40070
+/* [ST 24] The number of input CFC flush packets */
+#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES                       0x40128
+/* [ST 32] The number of cycles the Parser halted its operation since it
+   could not allocate the next serial number */
+#define PRS_REG_NUM_OF_DEAD_CYCLES                              0x40130
+/* [ST 24] The number of input packets */
+#define PRS_REG_NUM_OF_PACKETS                                  0x40124
+/* [ST 24] The number of input transparent flush packets */
+#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES               0x4012c
+/* [RW 8] Context region for received Ethernet packet with a match and
+   packet type 0. Used in CFC load request message */
+#define PRS_REG_PACKET_REGIONS_TYPE_0                           0x40028
+#define PRS_REG_PACKET_REGIONS_TYPE_1                           0x4002c
+#define PRS_REG_PACKET_REGIONS_TYPE_2                           0x40030
+#define PRS_REG_PACKET_REGIONS_TYPE_3                           0x40034
+#define PRS_REG_PACKET_REGIONS_TYPE_4                           0x40038
+#define PRS_REG_PACKET_REGIONS_TYPE_5                           0x4003c
+#define PRS_REG_PACKET_REGIONS_TYPE_6                           0x40040
+#define PRS_REG_PACKET_REGIONS_TYPE_7                           0x40044
+/* [R 2] debug only: Number of pending requests for CAC on port 0. */
+#define PRS_REG_PENDING_BRB_CAC0_RQ                             0x40174
+/* [R 2] debug only: Number of pending requests for header parsing. */
+#define PRS_REG_PENDING_BRB_PRS_RQ                              0x40170
+/* [R 1] Interrupt register #0 read */
+#define PRS_REG_PRS_INT_STS                                     0x40188
+/* [RW 8] Parity mask register #0 read/write */
+#define PRS_REG_PRS_PRTY_MASK                                   0x401a4
+/* [R 8] Parity register #0 read */
+#define PRS_REG_PRS_PRTY_STS                                    0x40198
+/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
+   request message */
+#define PRS_REG_PURE_REGIONS                                    0x40024
+/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
+   serail number was released by SDM but cannot be used because a previous
+   serial number was not released. */
+#define PRS_REG_SERIAL_NUM_STATUS_LSB                           0x40154
+/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
+   serail number was released by SDM but cannot be used because a previous
+   serial number was not released. */
+#define PRS_REG_SERIAL_NUM_STATUS_MSB                           0x40158
+/* [R 4] debug only: SRC current credit. Transaction based. */
+#define PRS_REG_SRC_CURRENT_CREDIT                              0x4016c
+/* [R 8] debug only: TCM current credit. Cycle based. */
+#define PRS_REG_TCM_CURRENT_CREDIT                              0x40160
+/* [R 8] debug only: TSDM current credit. Transaction based. */
+#define PRS_REG_TSDM_CURRENT_CREDIT                             0x4015c
+/* [R 6] Debug only: Number of used entries in the data FIFO */
+#define PXP2_REG_HST_DATA_FIFO_STATUS                           0x12047c
+/* [R 7] Debug only: Number of used entries in the header FIFO */
+#define PXP2_REG_HST_HEADER_FIFO_STATUS                         0x120478
+#define PXP2_REG_PGL_ADDR_88_F0                                 0x120534
+#define PXP2_REG_PGL_ADDR_8C_F0                                 0x120538
+#define PXP2_REG_PGL_ADDR_90_F0                                 0x12053c
+#define PXP2_REG_PGL_ADDR_94_F0                                 0x120540
+#define PXP2_REG_PGL_CONTROL0                                   0x120490
+#define PXP2_REG_PGL_CONTROL1                                   0x120514
+#define PXP2_REG_PGL_DEBUG                                      0x120520
+/* [RW 32] third dword data of expansion rom request. this register is
+   special. reading from it provides a vector outstanding read requests. if
+   a bit is zero it means that a read request on the corresponding tag did
+   not finish yet (not all completions have arrived for it) */
+#define PXP2_REG_PGL_EXP_ROM2                                   0x120808
+/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
+   its[15:0]-address */
+#define PXP2_REG_PGL_INT_CSDM_0                                 0x1204f4
+#define PXP2_REG_PGL_INT_CSDM_1                                 0x1204f8
+#define PXP2_REG_PGL_INT_CSDM_2                                 0x1204fc
+#define PXP2_REG_PGL_INT_CSDM_3                                 0x120500
+#define PXP2_REG_PGL_INT_CSDM_4                                 0x120504
+#define PXP2_REG_PGL_INT_CSDM_5                                 0x120508
+#define PXP2_REG_PGL_INT_CSDM_6                                 0x12050c
+#define PXP2_REG_PGL_INT_CSDM_7                                 0x120510
+/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
+   its[15:0]-address */
+#define PXP2_REG_PGL_INT_TSDM_0                                 0x120494
+#define PXP2_REG_PGL_INT_TSDM_1                                 0x120498
+#define PXP2_REG_PGL_INT_TSDM_2                                 0x12049c
+#define PXP2_REG_PGL_INT_TSDM_3                                 0x1204a0
+#define PXP2_REG_PGL_INT_TSDM_4                                 0x1204a4
+#define PXP2_REG_PGL_INT_TSDM_5                                 0x1204a8
+#define PXP2_REG_PGL_INT_TSDM_6                                 0x1204ac
+#define PXP2_REG_PGL_INT_TSDM_7                                 0x1204b0
+/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
+   its[15:0]-address */
+#define PXP2_REG_PGL_INT_USDM_0                                 0x1204b4
+#define PXP2_REG_PGL_INT_USDM_1                                 0x1204b8
+#define PXP2_REG_PGL_INT_USDM_2                                 0x1204bc
+#define PXP2_REG_PGL_INT_USDM_3                                 0x1204c0
+#define PXP2_REG_PGL_INT_USDM_4                                 0x1204c4
+#define PXP2_REG_PGL_INT_USDM_5                                 0x1204c8
+#define PXP2_REG_PGL_INT_USDM_6                                 0x1204cc
+#define PXP2_REG_PGL_INT_USDM_7                                 0x1204d0
+/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
+   its[15:0]-address */
+#define PXP2_REG_PGL_INT_XSDM_0                                 0x1204d4
+#define PXP2_REG_PGL_INT_XSDM_1                                 0x1204d8
+#define PXP2_REG_PGL_INT_XSDM_2                                 0x1204dc
+#define PXP2_REG_PGL_INT_XSDM_3                                 0x1204e0
+#define PXP2_REG_PGL_INT_XSDM_4                                 0x1204e4
+#define PXP2_REG_PGL_INT_XSDM_5                                 0x1204e8
+#define PXP2_REG_PGL_INT_XSDM_6                                 0x1204ec
+#define PXP2_REG_PGL_INT_XSDM_7                                 0x1204f0
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F0                            0x120674
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F1                            0x120678
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F2                            0x12067c
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F3                            0x120680
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F4                            0x120684
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F5                            0x120688
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F6                            0x12068c
+/* [RW 3] this field allows one function to pretend being another function
+   when accessing any BAR mapped resource within the device. the value of
+   the field is the number of the function that will be accessed
+   effectively. after software write to this bit it must read it in order to
+   know that the new value is updated */
+#define PXP2_REG_PGL_PRETEND_FUNC_F7                            0x120690
+/* [R 1] this bit indicates that a read request was blocked because of
+   bus_master_en was deasserted */
+#define PXP2_REG_PGL_READ_BLOCKED                               0x120568
+#define PXP2_REG_PGL_TAGS_LIMIT                                 0x1205a8
+/* [R 18] debug only */
+#define PXP2_REG_PGL_TXW_CDTS                                   0x12052c
+/* [R 1] this bit indicates that a write request was blocked because of
+   bus_master_en was deasserted */
+#define PXP2_REG_PGL_WRITE_BLOCKED                              0x120564
+#define PXP2_REG_PSWRQ_BW_ADD1                                  0x1201c0
+#define PXP2_REG_PSWRQ_BW_ADD10                                 0x1201e4
+#define PXP2_REG_PSWRQ_BW_ADD11                                 0x1201e8
+#define PXP2_REG_PSWRQ_BW_ADD2                                  0x1201c4
+#define PXP2_REG_PSWRQ_BW_ADD28                                 0x120228
+#define PXP2_REG_PSWRQ_BW_ADD3                                  0x1201c8
+#define PXP2_REG_PSWRQ_BW_ADD6                                  0x1201d4
+#define PXP2_REG_PSWRQ_BW_ADD7                                  0x1201d8
+#define PXP2_REG_PSWRQ_BW_ADD8                                  0x1201dc
+#define PXP2_REG_PSWRQ_BW_ADD9                                  0x1201e0
+#define PXP2_REG_PSWRQ_BW_CREDIT                                0x12032c
+#define PXP2_REG_PSWRQ_BW_L1                                    0x1202b0
+#define PXP2_REG_PSWRQ_BW_L10                                   0x1202d4
+#define PXP2_REG_PSWRQ_BW_L11                                   0x1202d8
+#define PXP2_REG_PSWRQ_BW_L2                                    0x1202b4
+#define PXP2_REG_PSWRQ_BW_L28                                   0x120318
+#define PXP2_REG_PSWRQ_BW_L3                                    0x1202b8
+#define PXP2_REG_PSWRQ_BW_L6                                    0x1202c4
+#define PXP2_REG_PSWRQ_BW_L7                                    0x1202c8
+#define PXP2_REG_PSWRQ_BW_L8                                    0x1202cc
+#define PXP2_REG_PSWRQ_BW_L9                                    0x1202d0
+#define PXP2_REG_PSWRQ_BW_RD                                    0x120324
+#define PXP2_REG_PSWRQ_BW_UB1                                   0x120238
+#define PXP2_REG_PSWRQ_BW_UB10                                  0x12025c
+#define PXP2_REG_PSWRQ_BW_UB11                                  0x120260
+#define PXP2_REG_PSWRQ_BW_UB2                                   0x12023c
+#define PXP2_REG_PSWRQ_BW_UB28                                  0x1202a0
+#define PXP2_REG_PSWRQ_BW_UB3                                   0x120240
+#define PXP2_REG_PSWRQ_BW_UB6                                   0x12024c
+#define PXP2_REG_PSWRQ_BW_UB7                                   0x120250
+#define PXP2_REG_PSWRQ_BW_UB8                                   0x120254
+#define PXP2_REG_PSWRQ_BW_UB9                                   0x120258
+#define PXP2_REG_PSWRQ_BW_WR                                    0x120328
+#define PXP2_REG_PSWRQ_CDU0_L2P                                 0x120000
+#define PXP2_REG_PSWRQ_QM0_L2P                                  0x120038
+#define PXP2_REG_PSWRQ_SRC0_L2P                                 0x120054
+#define PXP2_REG_PSWRQ_TM0_L2P                                  0x12001c
+#define PXP2_REG_PSWRQ_TSDM0_L2P                                0x1200e0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP2_REG_PXP2_INT_MASK_0                                0x120578
+/* [R 32] Interrupt register #0 read */
+#define PXP2_REG_PXP2_INT_STS_0                                 0x12056c
+#define PXP2_REG_PXP2_INT_STS_1                                 0x120608
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP2_REG_PXP2_INT_STS_CLR_0                             0x120570
+/* [RW 32] Parity mask register #0 read/write */
+#define PXP2_REG_PXP2_PRTY_MASK_0                               0x120588
+#define PXP2_REG_PXP2_PRTY_MASK_1                               0x120598
+/* [R 32] Parity register #0 read */
+#define PXP2_REG_PXP2_PRTY_STS_0                                0x12057c
+#define PXP2_REG_PXP2_PRTY_STS_1                                0x12058c
+/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
+   indication about backpressure) */
+#define PXP2_REG_RD_ALMOST_FULL_0                               0x120424
+/* [R 8] Debug only: The blocks counter - number of unused block ids */
+#define PXP2_REG_RD_BLK_CNT                                     0x120418
+/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
+   Must be bigger than 6. Normally should not be changed. */
+#define PXP2_REG_RD_BLK_NUM_CFG                                 0x12040c
+/* [RW 2] CDU byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_CDURD_SWAP_MODE                             0x120404
+/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
+#define PXP2_REG_RD_DISABLE_INPUTS                              0x120374
+/* [R 1] PSWRD internal memories initialization is done */
+#define PXP2_REG_RD_INIT_DONE                                   0x120370
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq10 */
+#define PXP2_REG_RD_MAX_BLKS_VQ10                               0x1203a0
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq11 */
+#define PXP2_REG_RD_MAX_BLKS_VQ11                               0x1203a4
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq17 */
+#define PXP2_REG_RD_MAX_BLKS_VQ17                               0x1203bc
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq18 */
+#define PXP2_REG_RD_MAX_BLKS_VQ18                               0x1203c0
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq19 */
+#define PXP2_REG_RD_MAX_BLKS_VQ19                               0x1203c4
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq22 */
+#define PXP2_REG_RD_MAX_BLKS_VQ22                               0x1203d0
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq25 */
+#define PXP2_REG_RD_MAX_BLKS_VQ25                               0x1203dc
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq6 */
+#define PXP2_REG_RD_MAX_BLKS_VQ6                                0x120390
+/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
+   allocated for vq9 */
+#define PXP2_REG_RD_MAX_BLKS_VQ9                                0x12039c
+/* [RW 2] PBF byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_PBF_SWAP_MODE                               0x1203f4
+/* [R 1] Debug only: Indication if delivery ports are idle */
+#define PXP2_REG_RD_PORT_IS_IDLE_0                              0x12041c
+#define PXP2_REG_RD_PORT_IS_IDLE_1                              0x120420
+/* [RW 2] QM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_QM_SWAP_MODE                                0x1203f8
+/* [R 7] Debug only: The SR counter - number of unused sub request ids */
+#define PXP2_REG_RD_SR_CNT                                      0x120414
+/* [RW 2] SRC byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_SRC_SWAP_MODE                               0x120400
+/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
+   be bigger than 1. Normally should not be changed. */
+#define PXP2_REG_RD_SR_NUM_CFG                                  0x120408
+/* [RW 1] Signals the PSWRD block to start initializing internal memories */
+#define PXP2_REG_RD_START_INIT                                  0x12036c
+/* [RW 2] TM byte swapping mode configuration for master read requests */
+#define PXP2_REG_RD_TM_SWAP_MODE                                0x1203fc
+/* [RW 10] Bandwidth addition to VQ0 write requests */
+#define PXP2_REG_RQ_BW_RD_ADD0                                  0x1201bc
+/* [RW 10] Bandwidth addition to VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD12                                 0x1201ec
+/* [RW 10] Bandwidth addition to VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD13                                 0x1201f0
+/* [RW 10] Bandwidth addition to VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD14                                 0x1201f4
+/* [RW 10] Bandwidth addition to VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD15                                 0x1201f8
+/* [RW 10] Bandwidth addition to VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD16                                 0x1201fc
+/* [RW 10] Bandwidth addition to VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD17                                 0x120200
+/* [RW 10] Bandwidth addition to VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD18                                 0x120204
+/* [RW 10] Bandwidth addition to VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD19                                 0x120208
+/* [RW 10] Bandwidth addition to VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD20                                 0x12020c
+/* [RW 10] Bandwidth addition to VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD22                                 0x120210
+/* [RW 10] Bandwidth addition to VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD23                                 0x120214
+/* [RW 10] Bandwidth addition to VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD24                                 0x120218
+/* [RW 10] Bandwidth addition to VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD25                                 0x12021c
+/* [RW 10] Bandwidth addition to VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD26                                 0x120220
+/* [RW 10] Bandwidth addition to VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD27                                 0x120224
+/* [RW 10] Bandwidth addition to VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD4                                  0x1201cc
+/* [RW 10] Bandwidth addition to VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_ADD5                                  0x1201d0
+/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
+#define PXP2_REG_RQ_BW_RD_L0                                    0x1202ac
+/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
+#define PXP2_REG_RQ_BW_RD_L12                                   0x1202dc
+/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
+#define PXP2_REG_RQ_BW_RD_L13                                   0x1202e0
+/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
+#define PXP2_REG_RQ_BW_RD_L14                                   0x1202e4
+/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
+#define PXP2_REG_RQ_BW_RD_L15                                   0x1202e8
+/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
+#define PXP2_REG_RQ_BW_RD_L16                                   0x1202ec
+/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
+#define PXP2_REG_RQ_BW_RD_L17                                   0x1202f0
+/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
+#define PXP2_REG_RQ_BW_RD_L18                                   0x1202f4
+/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
+#define PXP2_REG_RQ_BW_RD_L19                                   0x1202f8
+/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
+#define PXP2_REG_RQ_BW_RD_L20                                   0x1202fc
+/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
+#define PXP2_REG_RQ_BW_RD_L22                                   0x120300
+/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
+#define PXP2_REG_RQ_BW_RD_L23                                   0x120304
+/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
+#define PXP2_REG_RQ_BW_RD_L24                                   0x120308
+/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
+#define PXP2_REG_RQ_BW_RD_L25                                   0x12030c
+/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
+#define PXP2_REG_RQ_BW_RD_L26                                   0x120310
+/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
+#define PXP2_REG_RQ_BW_RD_L27                                   0x120314
+/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
+#define PXP2_REG_RQ_BW_RD_L4                                    0x1202bc
+/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
+#define PXP2_REG_RQ_BW_RD_L5                                    0x1202c0
+/* [RW 7] Bandwidth upper bound for VQ0 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND0                               0x120234
+/* [RW 7] Bandwidth upper bound for VQ12 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND12                              0x120264
+/* [RW 7] Bandwidth upper bound for VQ13 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND13                              0x120268
+/* [RW 7] Bandwidth upper bound for VQ14 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND14                              0x12026c
+/* [RW 7] Bandwidth upper bound for VQ15 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND15                              0x120270
+/* [RW 7] Bandwidth upper bound for VQ16 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND16                              0x120274
+/* [RW 7] Bandwidth upper bound for VQ17 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND17                              0x120278
+/* [RW 7] Bandwidth upper bound for VQ18 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND18                              0x12027c
+/* [RW 7] Bandwidth upper bound for VQ19 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND19                              0x120280
+/* [RW 7] Bandwidth upper bound for VQ20 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND20                              0x120284
+/* [RW 7] Bandwidth upper bound for VQ22 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND22                              0x120288
+/* [RW 7] Bandwidth upper bound for VQ23 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND23                              0x12028c
+/* [RW 7] Bandwidth upper bound for VQ24 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND24                              0x120290
+/* [RW 7] Bandwidth upper bound for VQ25 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND25                              0x120294
+/* [RW 7] Bandwidth upper bound for VQ26 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND26                              0x120298
+/* [RW 7] Bandwidth upper bound for VQ27 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND27                              0x12029c
+/* [RW 7] Bandwidth upper bound for VQ4 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND4                               0x120244
+/* [RW 7] Bandwidth upper bound for VQ5 read requests */
+#define PXP2_REG_RQ_BW_RD_UBOUND5                               0x120248
+/* [RW 10] Bandwidth addition to VQ29 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD29                                 0x12022c
+/* [RW 10] Bandwidth addition to VQ30 write requests */
+#define PXP2_REG_RQ_BW_WR_ADD30                                 0x120230
+/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
+#define PXP2_REG_RQ_BW_WR_L29                                   0x12031c
+/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
+#define PXP2_REG_RQ_BW_WR_L30                                   0x120320
+/* [RW 7] Bandwidth upper bound for VQ29 */
+#define PXP2_REG_RQ_BW_WR_UBOUND29                              0x1202a4
+/* [RW 7] Bandwidth upper bound for VQ30 */
+#define PXP2_REG_RQ_BW_WR_UBOUND30                              0x1202a8
+/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
+#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR                        0x120008
+/* [RW 2] Endian mode for cdu */
+#define PXP2_REG_RQ_CDU_ENDIAN_M                                0x1201a0
+#define PXP2_REG_RQ_CDU_FIRST_ILT                               0x12061c
+#define PXP2_REG_RQ_CDU_LAST_ILT                                0x120620
+/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
+   -128k */
+#define PXP2_REG_RQ_CDU_P_SIZE                                  0x120018
+/* [R 1] 1' indicates that the requester has finished its internal
+   configuration */
+#define PXP2_REG_RQ_CFG_DONE                                    0x1201b4
+/* [RW 2] Endian mode for debug */
+#define PXP2_REG_RQ_DBG_ENDIAN_M                                0x1201a4
+/* [RW 1] When '1'; requests will enter input buffers but wont get out
+   towards the glue */
+#define PXP2_REG_RQ_DISABLE_INPUTS                              0x120330
+/* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
+#define PXP2_REG_RQ_DRAM_ALIGN                                  0x1205b0
+/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
+   be asserted */
+#define PXP2_REG_RQ_ELT_DISABLE                                 0x12066c
+/* [RW 2] Endian mode for hc */
+#define PXP2_REG_RQ_HC_ENDIAN_M                                 0x1201a8
+/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
+   compatibility needs; Note that different registers are used per mode */
+#define PXP2_REG_RQ_ILT_MODE                                    0x1205b4
+/* [WB 53] Onchip address table */
+#define PXP2_REG_RQ_ONCHIP_AT                                   0x122000
+/* [WB 53] Onchip address table - B0 */
+#define PXP2_REG_RQ_ONCHIP_AT_B0                                0x128000
+/* [RW 13] Pending read limiter threshold; in Dwords */
+#define PXP2_REG_RQ_PDR_LIMIT                                   0x12033c
+/* [RW 2] Endian mode for qm */
+#define PXP2_REG_RQ_QM_ENDIAN_M                                 0x120194
+#define PXP2_REG_RQ_QM_FIRST_ILT                                0x120634
+#define PXP2_REG_RQ_QM_LAST_ILT                                 0x120638
+/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
+   -128k */
+#define PXP2_REG_RQ_QM_P_SIZE                                   0x120050
+/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
+#define PXP2_REG_RQ_RBC_DONE                                    0x1201b0
+/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
+   001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
+#define PXP2_REG_RQ_RD_MBS0                                     0x120160
+/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
+   001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
+#define PXP2_REG_RQ_RD_MBS1                                     0x120168
+/* [RW 2] Endian mode for src */
+#define PXP2_REG_RQ_SRC_ENDIAN_M                                0x12019c
+#define PXP2_REG_RQ_SRC_FIRST_ILT                               0x12063c
+#define PXP2_REG_RQ_SRC_LAST_ILT                                0x120640
+/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
+   -128k */
+#define PXP2_REG_RQ_SRC_P_SIZE                                  0x12006c
+/* [RW 2] Endian mode for tm */
+#define PXP2_REG_RQ_TM_ENDIAN_M                                 0x120198
+#define PXP2_REG_RQ_TM_FIRST_ILT                                0x120644
+#define PXP2_REG_RQ_TM_LAST_ILT                                 0x120648
+/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
+   -128k */
+#define PXP2_REG_RQ_TM_P_SIZE                                   0x120034
+/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
+#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY                          0x12080c
+/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
+#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR                       0x120094
+/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
+#define PXP2_REG_RQ_VQ0_ENTRY_CNT                               0x120810
+/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
+#define PXP2_REG_RQ_VQ10_ENTRY_CNT                              0x120818
+/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
+#define PXP2_REG_RQ_VQ11_ENTRY_CNT                              0x120820
+/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
+#define PXP2_REG_RQ_VQ12_ENTRY_CNT                              0x120828
+/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
+#define PXP2_REG_RQ_VQ13_ENTRY_CNT                              0x120830
+/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
+#define PXP2_REG_RQ_VQ14_ENTRY_CNT                              0x120838
+/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
+#define PXP2_REG_RQ_VQ15_ENTRY_CNT                              0x120840
+/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
+#define PXP2_REG_RQ_VQ16_ENTRY_CNT                              0x120848
+/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
+#define PXP2_REG_RQ_VQ17_ENTRY_CNT                              0x120850
+/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
+#define PXP2_REG_RQ_VQ18_ENTRY_CNT                              0x120858
+/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
+#define PXP2_REG_RQ_VQ19_ENTRY_CNT                              0x120860
+/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
+#define PXP2_REG_RQ_VQ1_ENTRY_CNT                               0x120868
+/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
+#define PXP2_REG_RQ_VQ20_ENTRY_CNT                              0x120870
+/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
+#define PXP2_REG_RQ_VQ21_ENTRY_CNT                              0x120878
+/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
+#define PXP2_REG_RQ_VQ22_ENTRY_CNT                              0x120880
+/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
+#define PXP2_REG_RQ_VQ23_ENTRY_CNT                              0x120888
+/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
+#define PXP2_REG_RQ_VQ24_ENTRY_CNT                              0x120890
+/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
+#define PXP2_REG_RQ_VQ25_ENTRY_CNT                              0x120898
+/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
+#define PXP2_REG_RQ_VQ26_ENTRY_CNT                              0x1208a0
+/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
+#define PXP2_REG_RQ_VQ27_ENTRY_CNT                              0x1208a8
+/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
+#define PXP2_REG_RQ_VQ28_ENTRY_CNT                              0x1208b0
+/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
+#define PXP2_REG_RQ_VQ29_ENTRY_CNT                              0x1208b8
+/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
+#define PXP2_REG_RQ_VQ2_ENTRY_CNT                               0x1208c0
+/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
+#define PXP2_REG_RQ_VQ30_ENTRY_CNT                              0x1208c8
+/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
+#define PXP2_REG_RQ_VQ31_ENTRY_CNT                              0x1208d0
+/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
+#define PXP2_REG_RQ_VQ3_ENTRY_CNT                               0x1208d8
+/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
+#define PXP2_REG_RQ_VQ4_ENTRY_CNT                               0x1208e0
+/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
+#define PXP2_REG_RQ_VQ5_ENTRY_CNT                               0x1208e8
+/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
+#define PXP2_REG_RQ_VQ6_ENTRY_CNT                               0x1208f0
+/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
+#define PXP2_REG_RQ_VQ7_ENTRY_CNT                               0x1208f8
+/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
+#define PXP2_REG_RQ_VQ8_ENTRY_CNT                               0x120900
+/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
+#define PXP2_REG_RQ_VQ9_ENTRY_CNT                               0x120908
+/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
+   001:256B; 010: 512B; */
+#define PXP2_REG_RQ_WR_MBS0                                     0x12015c
+/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
+   001:256B; 010: 512B; */
+#define PXP2_REG_RQ_WR_MBS1                                     0x120164
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_CDU_MPS                                     0x1205f0
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_CSDM_MPS                                    0x1205d0
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_DBG_MPS                                     0x1205e8
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_DMAE_MPS                                    0x1205ec
+/* [RW 10] if Number of entries in dmae fifo will be higher than this
+   threshold then has_payload indication will be asserted; the default value
+   should be equal to &gt;  write MBS size! */
+#define PXP2_REG_WR_DMAE_TH                                     0x120368
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_HC_MPS                                      0x1205c8
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_QM_MPS                                      0x1205dc
+/* [RW 1] 0 - working in A0 mode;  - working in B0 mode */
+#define PXP2_REG_WR_REV_MODE                                    0x120670
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_SRC_MPS                                     0x1205e4
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_TM_MPS                                      0x1205e0
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_TSDM_MPS                                    0x1205d4
+/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
+   threshold then has_payload indication will be asserted; the default value
+   should be equal to &gt;  write MBS size! */
+#define PXP2_REG_WR_USDMDP_TH                                   0x120348
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_USDM_MPS                                    0x1205cc
+/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
+   buffer reaches this number has_payload will be asserted */
+#define PXP2_REG_WR_XSDM_MPS                                    0x1205d8
+/* [R 1] debug only: Indication if PSWHST arbiter is idle */
+#define PXP_REG_HST_ARB_IS_IDLE                                 0x103004
+/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
+   this client is waiting for the arbiter. */
+#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB                      0x103008
+/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
+   should update accoring to 'hst_discard_doorbells' register when the state
+   machine is idle */
+#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS                    0x1030a0
+/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
+   means this PSWHST is discarding inputs from this client. Each bit should
+   update accoring to 'hst_discard_internal_writes' register when the state
+   machine is idle. */
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS              0x10309c
+/* [WB 160] Used for initialization of the inbound interrupts memory */
+#define PXP_REG_HST_INBOUND_INT                                 0x103800
+/* [RW 32] Interrupt mask register #0 read/write */
+#define PXP_REG_PXP_INT_MASK_0                                  0x103074
+#define PXP_REG_PXP_INT_MASK_1                                  0x103084
+/* [R 32] Interrupt register #0 read */
+#define PXP_REG_PXP_INT_STS_0                                   0x103068
+#define PXP_REG_PXP_INT_STS_1                                   0x103078
+/* [RC 32] Interrupt register #0 read clear */
+#define PXP_REG_PXP_INT_STS_CLR_0                               0x10306c
+/* [RW 26] Parity mask register #0 read/write */
+#define PXP_REG_PXP_PRTY_MASK                                   0x103094
+/* [R 26] Parity register #0 read */
+#define PXP_REG_PXP_PRTY_STS                                    0x103088
+/* [RW 4] The activity counter initial increment value sent in the load
+   request */
+#define QM_REG_ACTCTRINITVAL_0                                  0x168040
+#define QM_REG_ACTCTRINITVAL_1                                  0x168044
+#define QM_REG_ACTCTRINITVAL_2                                  0x168048
+#define QM_REG_ACTCTRINITVAL_3                                  0x16804c
+/* [RW 32] The base logical address (in bytes) of each physical queue. The
+   index I represents the physical queue number. The 12 lsbs are ignore and
+   considered zero so practically there are only 20 bits in this register;
+   queues 63-0 */
+#define QM_REG_BASEADDR                                         0x168900
+/* [RW 32] The base logical address (in bytes) of each physical queue. The
+   index I represents the physical queue number. The 12 lsbs are ignore and
+   considered zero so practically there are only 20 bits in this register;
+   queues 127-64 */
+#define QM_REG_BASEADDR_EXT_A                                   0x16e100
+/* [RW 16] The byte credit cost for each task. This value is for both ports */
+#define QM_REG_BYTECRDCOST                                      0x168234
+/* [RW 16] The initial byte credit value for both ports. */
+#define QM_REG_BYTECRDINITVAL                                   0x168238
+/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
+   queue uses port 0 else it uses port 1; queues 31-0 */
+#define QM_REG_BYTECRDPORT_LSB                                  0x168228
+/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
+   queue uses port 0 else it uses port 1; queues 95-64 */
+#define QM_REG_BYTECRDPORT_LSB_EXT_A                            0x16e520
+/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
+   queue uses port 0 else it uses port 1; queues 63-32 */
+#define QM_REG_BYTECRDPORT_MSB                                  0x168224
+/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
+   queue uses port 0 else it uses port 1; queues 127-96 */
+#define QM_REG_BYTECRDPORT_MSB_EXT_A                            0x16e51c
+/* [RW 16] The byte credit value that if above the QM is considered almost
+   full */
+#define QM_REG_BYTECREDITAFULLTHR                               0x168094
+/* [RW 4] The initial credit for interface */
+#define QM_REG_CMINITCRD_0                                      0x1680cc
+#define QM_REG_CMINITCRD_1                                      0x1680d0
+#define QM_REG_CMINITCRD_2                                      0x1680d4
+#define QM_REG_CMINITCRD_3                                      0x1680d8
+#define QM_REG_CMINITCRD_4                                      0x1680dc
+#define QM_REG_CMINITCRD_5                                      0x1680e0
+#define QM_REG_CMINITCRD_6                                      0x1680e4
+#define QM_REG_CMINITCRD_7                                      0x1680e8
+/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
+   is masked */
+#define QM_REG_CMINTEN                                          0x1680ec
+/* [RW 12] A bit vector which indicates which one of the queues are tied to
+   interface 0 */
+#define QM_REG_CMINTVOQMASK_0                                   0x1681f4
+#define QM_REG_CMINTVOQMASK_1                                   0x1681f8
+#define QM_REG_CMINTVOQMASK_2                                   0x1681fc
+#define QM_REG_CMINTVOQMASK_3                                   0x168200
+#define QM_REG_CMINTVOQMASK_4                                   0x168204
+#define QM_REG_CMINTVOQMASK_5                                   0x168208
+#define QM_REG_CMINTVOQMASK_6                                   0x16820c
+#define QM_REG_CMINTVOQMASK_7                                   0x168210
+/* [RW 20] The number of connections divided by 16 which dictates the size
+   of each queue which belongs to even function number. */
+#define QM_REG_CONNNUM_0                                        0x168020
+/* [R 6] Keep the fill level of the fifo from write client 4 */
+#define QM_REG_CQM_WRC_FIFOLVL                                  0x168018
+/* [RW 8] The context regions sent in the CFC load request */
+#define QM_REG_CTXREG_0                                         0x168030
+#define QM_REG_CTXREG_1                                         0x168034
+#define QM_REG_CTXREG_2                                         0x168038
+#define QM_REG_CTXREG_3                                         0x16803c
+/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
+   bypass enable */
+#define QM_REG_ENBYPVOQMASK                                     0x16823c
+/* [RW 32] A bit mask per each physical queue. If a bit is set then the
+   physical queue uses the byte credit; queues 31-0 */
+#define QM_REG_ENBYTECRD_LSB                                    0x168220
+/* [RW 32] A bit mask per each physical queue. If a bit is set then the
+   physical queue uses the byte credit; queues 95-64 */
+#define QM_REG_ENBYTECRD_LSB_EXT_A                              0x16e518
+/* [RW 32] A bit mask per each physical queue. If a bit is set then the
+   physical queue uses the byte credit; queues 63-32 */
+#define QM_REG_ENBYTECRD_MSB                                    0x16821c
+/* [RW 32] A bit mask per each physical queue. If a bit is set then the
+   physical queue uses the byte credit; queues 127-96 */
+#define QM_REG_ENBYTECRD_MSB_EXT_A                              0x16e514
+/* [RW 4] If cleared then the secondary interface will not be served by the
+   RR arbiter */
+#define QM_REG_ENSEC                                            0x1680f0
+/* [RW 32] NA */
+#define QM_REG_FUNCNUMSEL_LSB                                   0x168230
+/* [RW 32] NA */
+#define QM_REG_FUNCNUMSEL_MSB                                   0x16822c
+/* [RW 32] A mask register to mask the Almost empty signals which will not
+   be use for the almost empty indication to the HW block; queues 31:0 */
+#define QM_REG_HWAEMPTYMASK_LSB                                 0x168218
+/* [RW 32] A mask register to mask the Almost empty signals which will not
+   be use for the almost empty indication to the HW block; queues 95-64 */
+#define QM_REG_HWAEMPTYMASK_LSB_EXT_A                           0x16e510
+/* [RW 32] A mask register to mask the Almost empty signals which will not
+   be use for the almost empty indication to the HW block; queues 63:32 */
+#define QM_REG_HWAEMPTYMASK_MSB                                 0x168214
+/* [RW 32] A mask register to mask the Almost empty signals which will not
+   be use for the almost empty indication to the HW block; queues 127-96 */
+#define QM_REG_HWAEMPTYMASK_MSB_EXT_A                           0x16e50c
+/* [RW 4] The number of outstanding request to CFC */
+#define QM_REG_OUTLDREQ                                         0x168804
+/* [RC 1] A flag to indicate that overflow error occurred in one of the
+   queues. */
+#define QM_REG_OVFERROR                                         0x16805c
+/* [RC 7] the Q were the qverflow occurs */
+#define QM_REG_OVFQNUM                                          0x168058
+/* [R 16] Pause state for physical queues 15-0 */
+#define QM_REG_PAUSESTATE0                                      0x168410
+/* [R 16] Pause state for physical queues 31-16 */
+#define QM_REG_PAUSESTATE1                                      0x168414
+/* [R 16] Pause state for physical queues 47-32 */
+#define QM_REG_PAUSESTATE2                                      0x16e684
+/* [R 16] Pause state for physical queues 63-48 */
+#define QM_REG_PAUSESTATE3                                      0x16e688
+/* [R 16] Pause state for physical queues 79-64 */
+#define QM_REG_PAUSESTATE4                                      0x16e68c
+/* [R 16] Pause state for physical queues 95-80 */
+#define QM_REG_PAUSESTATE5                                      0x16e690
+/* [R 16] Pause state for physical queues 111-96 */
+#define QM_REG_PAUSESTATE6                                      0x16e694
+/* [R 16] Pause state for physical queues 127-112 */
+#define QM_REG_PAUSESTATE7                                      0x16e698
+/* [RW 2] The PCI attributes field used in the PCI request. */
+#define QM_REG_PCIREQAT                                         0x168054
+/* [R 16] The byte credit of port 0 */
+#define QM_REG_PORT0BYTECRD                                     0x168300
+/* [R 16] The byte credit of port 1 */
+#define QM_REG_PORT1BYTECRD                                     0x168304
+/* [RW 3] pci function number of queues 15-0 */
+#define QM_REG_PQ2PCIFUNC_0                                     0x16e6bc
+#define QM_REG_PQ2PCIFUNC_1                                     0x16e6c0
+#define QM_REG_PQ2PCIFUNC_2                                     0x16e6c4
+#define QM_REG_PQ2PCIFUNC_3                                     0x16e6c8
+#define QM_REG_PQ2PCIFUNC_4                                     0x16e6cc
+#define QM_REG_PQ2PCIFUNC_5                                     0x16e6d0
+#define QM_REG_PQ2PCIFUNC_6                                     0x16e6d4
+#define QM_REG_PQ2PCIFUNC_7                                     0x16e6d8
+/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
+   ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+   bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
+#define QM_REG_PTRTBL                                           0x168a00
+/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
+   ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+   bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
+#define QM_REG_PTRTBL_EXT_A                                     0x16e200
+/* [RW 2] Interrupt mask register #0 read/write */
+#define QM_REG_QM_INT_MASK                                      0x168444
+/* [R 2] Interrupt register #0 read */
+#define QM_REG_QM_INT_STS                                       0x168438
+/* [RW 12] Parity mask register #0 read/write */
+#define QM_REG_QM_PRTY_MASK                                     0x168454
+/* [R 12] Parity register #0 read */
+#define QM_REG_QM_PRTY_STS                                      0x168448
+/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
+#define QM_REG_QSTATUS_HIGH                                     0x16802c
+/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
+#define QM_REG_QSTATUS_HIGH_EXT_A                               0x16e408
+/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
+#define QM_REG_QSTATUS_LOW                                      0x168028
+/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
+#define QM_REG_QSTATUS_LOW_EXT_A                                0x16e404
+/* [R 24] The number of tasks queued for each queue; queues 63-0 */
+#define QM_REG_QTASKCTR_0                                       0x168308
+/* [R 24] The number of tasks queued for each queue; queues 127-64 */
+#define QM_REG_QTASKCTR_EXT_A_0                                 0x16e584
+/* [RW 4] Queue tied to VOQ */
+#define QM_REG_QVOQIDX_0                                        0x1680f4
+#define QM_REG_QVOQIDX_10                                       0x16811c
+#define QM_REG_QVOQIDX_100                                      0x16e49c
+#define QM_REG_QVOQIDX_101                                      0x16e4a0
+#define QM_REG_QVOQIDX_102                                      0x16e4a4
+#define QM_REG_QVOQIDX_103                                      0x16e4a8
+#define QM_REG_QVOQIDX_104                                      0x16e4ac
+#define QM_REG_QVOQIDX_105                                      0x16e4b0
+#define QM_REG_QVOQIDX_106                                      0x16e4b4
+#define QM_REG_QVOQIDX_107                                      0x16e4b8
+#define QM_REG_QVOQIDX_108                                      0x16e4bc
+#define QM_REG_QVOQIDX_109                                      0x16e4c0
+#define QM_REG_QVOQIDX_11                                       0x168120
+#define QM_REG_QVOQIDX_110                                      0x16e4c4
+#define QM_REG_QVOQIDX_111                                      0x16e4c8
+#define QM_REG_QVOQIDX_112                                      0x16e4cc
+#define QM_REG_QVOQIDX_113                                      0x16e4d0
+#define QM_REG_QVOQIDX_114                                      0x16e4d4
+#define QM_REG_QVOQIDX_115                                      0x16e4d8
+#define QM_REG_QVOQIDX_116                                      0x16e4dc
+#define QM_REG_QVOQIDX_117                                      0x16e4e0
+#define QM_REG_QVOQIDX_118                                      0x16e4e4
+#define QM_REG_QVOQIDX_119                                      0x16e4e8
+#define QM_REG_QVOQIDX_12                                       0x168124
+#define QM_REG_QVOQIDX_120                                      0x16e4ec
+#define QM_REG_QVOQIDX_121                                      0x16e4f0
+#define QM_REG_QVOQIDX_122                                      0x16e4f4
+#define QM_REG_QVOQIDX_123                                      0x16e4f8
+#define QM_REG_QVOQIDX_124                                      0x16e4fc
+#define QM_REG_QVOQIDX_125                                      0x16e500
+#define QM_REG_QVOQIDX_126                                      0x16e504
+#define QM_REG_QVOQIDX_127                                      0x16e508
+#define QM_REG_QVOQIDX_13                                       0x168128
+#define QM_REG_QVOQIDX_14                                       0x16812c
+#define QM_REG_QVOQIDX_15                                       0x168130
+#define QM_REG_QVOQIDX_16                                       0x168134
+#define QM_REG_QVOQIDX_17                                       0x168138
+#define QM_REG_QVOQIDX_21                                       0x168148
+#define QM_REG_QVOQIDX_22                                       0x16814c
+#define QM_REG_QVOQIDX_23                                       0x168150
+#define QM_REG_QVOQIDX_24                                       0x168154
+#define QM_REG_QVOQIDX_25                                       0x168158
+#define QM_REG_QVOQIDX_26                                       0x16815c
+#define QM_REG_QVOQIDX_27                                       0x168160
+#define QM_REG_QVOQIDX_28                                       0x168164
+#define QM_REG_QVOQIDX_29                                       0x168168
+#define QM_REG_QVOQIDX_30                                       0x16816c
+#define QM_REG_QVOQIDX_31                                       0x168170
+#define QM_REG_QVOQIDX_32                                       0x168174
+#define QM_REG_QVOQIDX_33                                       0x168178
+#define QM_REG_QVOQIDX_34                                       0x16817c
+#define QM_REG_QVOQIDX_35                                       0x168180
+#define QM_REG_QVOQIDX_36                                       0x168184
+#define QM_REG_QVOQIDX_37                                       0x168188
+#define QM_REG_QVOQIDX_38                                       0x16818c
+#define QM_REG_QVOQIDX_39                                       0x168190
+#define QM_REG_QVOQIDX_40                                       0x168194
+#define QM_REG_QVOQIDX_41                                       0x168198
+#define QM_REG_QVOQIDX_42                                       0x16819c
+#define QM_REG_QVOQIDX_43                                       0x1681a0
+#define QM_REG_QVOQIDX_44                                       0x1681a4
+#define QM_REG_QVOQIDX_45                                       0x1681a8
+#define QM_REG_QVOQIDX_46                                       0x1681ac
+#define QM_REG_QVOQIDX_47                                       0x1681b0
+#define QM_REG_QVOQIDX_48                                       0x1681b4
+#define QM_REG_QVOQIDX_49                                       0x1681b8
+#define QM_REG_QVOQIDX_5                                        0x168108
+#define QM_REG_QVOQIDX_50                                       0x1681bc
+#define QM_REG_QVOQIDX_51                                       0x1681c0
+#define QM_REG_QVOQIDX_52                                       0x1681c4
+#define QM_REG_QVOQIDX_53                                       0x1681c8
+#define QM_REG_QVOQIDX_54                                       0x1681cc
+#define QM_REG_QVOQIDX_55                                       0x1681d0
+#define QM_REG_QVOQIDX_56                                       0x1681d4
+#define QM_REG_QVOQIDX_57                                       0x1681d8
+#define QM_REG_QVOQIDX_58                                       0x1681dc
+#define QM_REG_QVOQIDX_59                                       0x1681e0
+#define QM_REG_QVOQIDX_6                                        0x16810c
+#define QM_REG_QVOQIDX_60                                       0x1681e4
+#define QM_REG_QVOQIDX_61                                       0x1681e8
+#define QM_REG_QVOQIDX_62                                       0x1681ec
+#define QM_REG_QVOQIDX_63                                       0x1681f0
+#define QM_REG_QVOQIDX_64                                       0x16e40c
+#define QM_REG_QVOQIDX_65                                       0x16e410
+#define QM_REG_QVOQIDX_69                                       0x16e420
+#define QM_REG_QVOQIDX_7                                        0x168110
+#define QM_REG_QVOQIDX_70                                       0x16e424
+#define QM_REG_QVOQIDX_71                                       0x16e428
+#define QM_REG_QVOQIDX_72                                       0x16e42c
+#define QM_REG_QVOQIDX_73                                       0x16e430
+#define QM_REG_QVOQIDX_74                                       0x16e434
+#define QM_REG_QVOQIDX_75                                       0x16e438
+#define QM_REG_QVOQIDX_76                                       0x16e43c
+#define QM_REG_QVOQIDX_77                                       0x16e440
+#define QM_REG_QVOQIDX_78                                       0x16e444
+#define QM_REG_QVOQIDX_79                                       0x16e448
+#define QM_REG_QVOQIDX_8                                        0x168114
+#define QM_REG_QVOQIDX_80                                       0x16e44c
+#define QM_REG_QVOQIDX_81                                       0x16e450
+#define QM_REG_QVOQIDX_85                                       0x16e460
+#define QM_REG_QVOQIDX_86                                       0x16e464
+#define QM_REG_QVOQIDX_87                                       0x16e468
+#define QM_REG_QVOQIDX_88                                       0x16e46c
+#define QM_REG_QVOQIDX_89                                       0x16e470
+#define QM_REG_QVOQIDX_9                                        0x168118
+#define QM_REG_QVOQIDX_90                                       0x16e474
+#define QM_REG_QVOQIDX_91                                       0x16e478
+#define QM_REG_QVOQIDX_92                                       0x16e47c
+#define QM_REG_QVOQIDX_93                                       0x16e480
+#define QM_REG_QVOQIDX_94                                       0x16e484
+#define QM_REG_QVOQIDX_95                                       0x16e488
+#define QM_REG_QVOQIDX_96                                       0x16e48c
+#define QM_REG_QVOQIDX_97                                       0x16e490
+#define QM_REG_QVOQIDX_98                                       0x16e494
+#define QM_REG_QVOQIDX_99                                       0x16e498
+/* [RW 1] Initialization bit command */
+#define QM_REG_SOFT_RESET                                       0x168428
+/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
+#define QM_REG_TASKCRDCOST_0                                    0x16809c
+#define QM_REG_TASKCRDCOST_1                                    0x1680a0
+#define QM_REG_TASKCRDCOST_2                                    0x1680a4
+#define QM_REG_TASKCRDCOST_4                                    0x1680ac
+#define QM_REG_TASKCRDCOST_5                                    0x1680b0
+/* [R 6] Keep the fill level of the fifo from write client 3 */
+#define QM_REG_TQM_WRC_FIFOLVL                                  0x168010
+/* [R 6] Keep the fill level of the fifo from write client 2 */
+#define QM_REG_UQM_WRC_FIFOLVL                                  0x168008
+/* [RC 32] Credit update error register */
+#define QM_REG_VOQCRDERRREG                                     0x168408
+/* [R 16] The credit value for each VOQ */
+#define QM_REG_VOQCREDIT_0                                      0x1682d0
+#define QM_REG_VOQCREDIT_1                                      0x1682d4
+#define QM_REG_VOQCREDIT_4                                      0x1682e0
+/* [RW 16] The credit value that if above the QM is considered almost full */
+#define QM_REG_VOQCREDITAFULLTHR                                0x168090
+/* [RW 16] The init and maximum credit for each VoQ */
+#define QM_REG_VOQINITCREDIT_0                                  0x168060
+#define QM_REG_VOQINITCREDIT_1                                  0x168064
+#define QM_REG_VOQINITCREDIT_2                                  0x168068
+#define QM_REG_VOQINITCREDIT_4                                  0x168070
+#define QM_REG_VOQINITCREDIT_5                                  0x168074
+/* [RW 1] The port of which VOQ belongs */
+#define QM_REG_VOQPORT_0                                        0x1682a0
+#define QM_REG_VOQPORT_1                                        0x1682a4
+#define QM_REG_VOQPORT_2                                        0x1682a8
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_0_LSB                                   0x168240
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_0_LSB_EXT_A                             0x16e524
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_0_MSB                                   0x168244
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_0_MSB_EXT_A                             0x16e528
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_10_LSB                                  0x168290
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_10_LSB_EXT_A                            0x16e574
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_10_MSB                                  0x168294
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_10_MSB_EXT_A                            0x16e578
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_11_LSB                                  0x168298
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_11_LSB_EXT_A                            0x16e57c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_11_MSB                                  0x16829c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_11_MSB_EXT_A                            0x16e580
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_1_LSB                                   0x168248
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_1_LSB_EXT_A                             0x16e52c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_1_MSB                                   0x16824c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_1_MSB_EXT_A                             0x16e530
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_2_LSB                                   0x168250
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_2_LSB_EXT_A                             0x16e534
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_2_MSB                                   0x168254
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_2_MSB_EXT_A                             0x16e538
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_3_LSB                                   0x168258
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_3_LSB_EXT_A                             0x16e53c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_3_MSB_EXT_A                             0x16e540
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_4_LSB                                   0x168260
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_4_LSB_EXT_A                             0x16e544
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_4_MSB                                   0x168264
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_4_MSB_EXT_A                             0x16e548
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_5_LSB                                   0x168268
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_5_LSB_EXT_A                             0x16e54c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_5_MSB                                   0x16826c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_5_MSB_EXT_A                             0x16e550
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_6_LSB                                   0x168270
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_6_LSB_EXT_A                             0x16e554
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_6_MSB                                   0x168274
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_6_MSB_EXT_A                             0x16e558
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_7_LSB                                   0x168278
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_7_LSB_EXT_A                             0x16e55c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_7_MSB                                   0x16827c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_7_MSB_EXT_A                             0x16e560
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_8_LSB                                   0x168280
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_8_LSB_EXT_A                             0x16e564
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define QM_REG_VOQQMASK_8_MSB                                   0x168284
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_8_MSB_EXT_A                             0x16e568
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define QM_REG_VOQQMASK_9_LSB                                   0x168288
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define QM_REG_VOQQMASK_9_LSB_EXT_A                             0x16e56c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define QM_REG_VOQQMASK_9_MSB_EXT_A                             0x16e570
+/* [RW 32] Wrr weights */
+#define QM_REG_WRRWEIGHTS_0                                     0x16880c
+#define QM_REG_WRRWEIGHTS_1                                     0x168810
+#define QM_REG_WRRWEIGHTS_10                                    0x168814
+#define QM_REG_WRRWEIGHTS_11                                    0x168818
+#define QM_REG_WRRWEIGHTS_12                                    0x16881c
+#define QM_REG_WRRWEIGHTS_13                                    0x168820
+#define QM_REG_WRRWEIGHTS_14                                    0x168824
+#define QM_REG_WRRWEIGHTS_15                                    0x168828
+#define QM_REG_WRRWEIGHTS_16                                    0x16e000
+#define QM_REG_WRRWEIGHTS_17                                    0x16e004
+#define QM_REG_WRRWEIGHTS_18                                    0x16e008
+#define QM_REG_WRRWEIGHTS_19                                    0x16e00c
+#define QM_REG_WRRWEIGHTS_2                                     0x16882c
+#define QM_REG_WRRWEIGHTS_20                                    0x16e010
+#define QM_REG_WRRWEIGHTS_21                                    0x16e014
+#define QM_REG_WRRWEIGHTS_22                                    0x16e018
+#define QM_REG_WRRWEIGHTS_23                                    0x16e01c
+#define QM_REG_WRRWEIGHTS_24                                    0x16e020
+#define QM_REG_WRRWEIGHTS_25                                    0x16e024
+#define QM_REG_WRRWEIGHTS_26                                    0x16e028
+#define QM_REG_WRRWEIGHTS_27                                    0x16e02c
+#define QM_REG_WRRWEIGHTS_28                                    0x16e030
+#define QM_REG_WRRWEIGHTS_29                                    0x16e034
+#define QM_REG_WRRWEIGHTS_3                                     0x168830
+#define QM_REG_WRRWEIGHTS_30                                    0x16e038
+#define QM_REG_WRRWEIGHTS_31                                    0x16e03c
+#define QM_REG_WRRWEIGHTS_4                                     0x168834
+#define QM_REG_WRRWEIGHTS_5                                     0x168838
+#define QM_REG_WRRWEIGHTS_6                                     0x16883c
+#define QM_REG_WRRWEIGHTS_7                                     0x168840
+#define QM_REG_WRRWEIGHTS_8                                     0x168844
+#define QM_REG_WRRWEIGHTS_9                                     0x168848
+/* [R 6] Keep the fill level of the fifo from write client 1 */
+#define QM_REG_XQM_WRC_FIFOLVL                                  0x168000
+#define SRC_REG_COUNTFREE0                                      0x40500
+/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
+   ports. If set the searcher support 8 functions. */
+#define SRC_REG_E1HMF_ENABLE                                    0x404cc
+#define SRC_REG_FIRSTFREE0                                      0x40510
+#define SRC_REG_KEYRSS0_0                                       0x40408
+#define SRC_REG_KEYRSS0_7                                       0x40424
+#define SRC_REG_KEYRSS1_9                                       0x40454
+#define SRC_REG_KEYSEARCH_0                                     0x40458
+#define SRC_REG_KEYSEARCH_1                                     0x4045c
+#define SRC_REG_KEYSEARCH_2                                     0x40460
+#define SRC_REG_KEYSEARCH_3                                     0x40464
+#define SRC_REG_KEYSEARCH_4                                     0x40468
+#define SRC_REG_KEYSEARCH_5                                     0x4046c
+#define SRC_REG_KEYSEARCH_6                                     0x40470
+#define SRC_REG_KEYSEARCH_7                                     0x40474
+#define SRC_REG_KEYSEARCH_8                                     0x40478
+#define SRC_REG_KEYSEARCH_9                                     0x4047c
+#define SRC_REG_LASTFREE0                                       0x40530
+#define SRC_REG_NUMBER_HASH_BITS0                               0x40400
+/* [RW 1] Reset internal state machines. */
+#define SRC_REG_SOFT_RST                                        0x4049c
+/* [R 3] Interrupt register #0 read */
+#define SRC_REG_SRC_INT_STS                                     0x404ac
+/* [RW 3] Parity mask register #0 read/write */
+#define SRC_REG_SRC_PRTY_MASK                                   0x404c8
+/* [R 3] Parity register #0 read */
+#define SRC_REG_SRC_PRTY_STS                                    0x404bc
+/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
+#define TCM_REG_CAM_OCCUP                                       0x5017c
+/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define TCM_REG_CDU_AG_RD_IFEN                                  0x50034
+/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
+   are disregarded; all other signals are treated as usual; if 1 - normal
+   activity. */
+#define TCM_REG_CDU_AG_WR_IFEN                                  0x50030
+/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define TCM_REG_CDU_SM_RD_IFEN                                  0x5003c
+/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
+   input is disregarded; all other signals are treated as usual; if 1 -
+   normal activity. */
+#define TCM_REG_CDU_SM_WR_IFEN                                  0x50038
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 1 at start-up. */
+#define TCM_REG_CFC_INIT_CRD                                    0x50204
+/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_CP_WEIGHT                                       0x500c0
+/* [RW 1] Input csem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define TCM_REG_CSEM_IFEN                                       0x5002c
+/* [RC 1] Message length mismatch (relative to last indication) at the In#9
+   interface. */
+#define TCM_REG_CSEM_LENGTH_MIS                                 0x50174
+/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_CSEM_WEIGHT                                     0x500bc
+/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
+#define TCM_REG_ERR_EVNT_ID                                     0x500a0
+/* [RW 28] The CM erroneous header for QM and Timers formatting. */
+#define TCM_REG_ERR_TCM_HDR                                     0x5009c
+/* [RW 8] The Event ID for Timers expiration. */
+#define TCM_REG_EXPR_EVNT_ID                                    0x500a4
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define TCM_REG_FIC0_INIT_CRD                                   0x5020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define TCM_REG_FIC1_INIT_CRD                                   0x50210
+/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
+   - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
+   ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
+   ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
+#define TCM_REG_GR_ARB_TYPE                                     0x50114
+/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed that the Store channel is the
+   compliment of the other 3 groups. */
+#define TCM_REG_GR_LD0_PR                                       0x5011c
+/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed that the Store channel is the
+   compliment of the other 3 groups. */
+#define TCM_REG_GR_LD1_PR                                       0x50120
+/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
+   sent to STORM; for a specific connection type. The double REG-pairs are
+   used to align to STORM context row size of 128 bits. The offset of these
+   data in the STORM context is always 0. Index _i stands for the connection
+   type (one of 16). */
+#define TCM_REG_N_SM_CTX_LD_0                                   0x50050
+#define TCM_REG_N_SM_CTX_LD_1                                   0x50054
+#define TCM_REG_N_SM_CTX_LD_2                                   0x50058
+#define TCM_REG_N_SM_CTX_LD_3                                   0x5005c
+#define TCM_REG_N_SM_CTX_LD_4                                   0x50060
+#define TCM_REG_N_SM_CTX_LD_5                                   0x50064
+/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_PBF_IFEN                                        0x50024
+/* [RC 1] Message length mismatch (relative to last indication) at the In#7
+   interface. */
+#define TCM_REG_PBF_LENGTH_MIS                                  0x5016c
+/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_PBF_WEIGHT                                      0x500b4
+#define TCM_REG_PHYS_QNUM0_0                                    0x500e0
+#define TCM_REG_PHYS_QNUM0_1                                    0x500e4
+#define TCM_REG_PHYS_QNUM1_0                                    0x500e8
+#define TCM_REG_PHYS_QNUM1_1                                    0x500ec
+#define TCM_REG_PHYS_QNUM2_0                                    0x500f0
+#define TCM_REG_PHYS_QNUM2_1                                    0x500f4
+#define TCM_REG_PHYS_QNUM3_0                                    0x500f8
+#define TCM_REG_PHYS_QNUM3_1                                    0x500fc
+/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_PRS_IFEN                                        0x50020
+/* [RC 1] Message length mismatch (relative to last indication) at the In#6
+   interface. */
+#define TCM_REG_PRS_LENGTH_MIS                                  0x50168
+/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_PRS_WEIGHT                                      0x500b0
+/* [RW 8] The Event ID for Timers formatting in case of stop done. */
+#define TCM_REG_STOP_EVNT_ID                                    0x500a8
+/* [RC 1] Message length mismatch (relative to last indication) at the STORM
+   interface. */
+#define TCM_REG_STORM_LENGTH_MIS                                0x50160
+/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define TCM_REG_STORM_TCM_IFEN                                  0x50010
+/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_STORM_WEIGHT                                    0x500ac
+/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_TCM_CFC_IFEN                                    0x50040
+/* [RW 11] Interrupt mask register #0 read/write */
+#define TCM_REG_TCM_INT_MASK                                    0x501dc
+/* [R 11] Interrupt register #0 read */
+#define TCM_REG_TCM_INT_STS                                     0x501d0
+/* [R 27] Parity register #0 read */
+#define TCM_REG_TCM_PRTY_STS                                    0x501e0
+/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
+   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+   Is used to determine the number of the AG context REG-pairs written back;
+   when the input message Reg1WbFlg isn't set. */
+#define TCM_REG_TCM_REG0_SZ                                     0x500d8
+/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_TCM_STORM0_IFEN                                 0x50004
+/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_TCM_STORM1_IFEN                                 0x50008
+/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_TCM_TQM_IFEN                                    0x5000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
+#define TCM_REG_TCM_TQM_USE_Q                                   0x500d4
+/* [RW 28] The CM header for Timers expiration command. */
+#define TCM_REG_TM_TCM_HDR                                      0x50098
+/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define TCM_REG_TM_TCM_IFEN                                     0x5001c
+/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TM_WEIGHT                                       0x500d0
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 32 at start-up. */
+#define TCM_REG_TQM_INIT_CRD                                    0x5021c
+/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TQM_P_WEIGHT                                    0x500c8
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TQM_S_WEIGHT                                    0x500cc
+/* [RW 28] The CM header value for QM request (primary). */
+#define TCM_REG_TQM_TCM_HDR_P                                   0x50090
+/* [RW 28] The CM header value for QM request (secondary). */
+#define TCM_REG_TQM_TCM_HDR_S                                   0x50094
+/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_TQM_TCM_IFEN                                    0x50014
+/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define TCM_REG_TSDM_IFEN                                       0x50018
+/* [RC 1] Message length mismatch (relative to last indication) at the SDM
+   interface. */
+#define TCM_REG_TSDM_LENGTH_MIS                                 0x50164
+/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_TSDM_WEIGHT                                     0x500c4
+/* [RW 1] Input usem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define TCM_REG_USEM_IFEN                                       0x50028
+/* [RC 1] Message length mismatch (relative to last indication) at the In#8
+   interface. */
+#define TCM_REG_USEM_LENGTH_MIS                                 0x50170
+/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define TCM_REG_USEM_WEIGHT                                     0x500b8
+/* [RW 21] Indirect access to the descriptor table of the XX protection
+   mechanism. The fields are: [5:0] - length of the message; 15:6] - message
+   pointer; 20:16] - next pointer. */
+#define TCM_REG_XX_DESCR_TABLE                                  0x50280
+#define TCM_REG_XX_DESCR_TABLE_SIZE                             32
+/* [R 6] Use to read the value of XX protection Free counter. */
+#define TCM_REG_XX_FREE                                         0x50178
+/* [RW 6] Initial value for the credit counter; responsible for fulfilling
+   of the Input Stage XX protection buffer by the XX protection pending
+   messages. Max credit available - 127.Write writes the initial credit
+   value; read returns the current value of the credit counter. Must be
+   initialized to 19 at start-up. */
+#define TCM_REG_XX_INIT_CRD                                     0x50220
+/* [RW 6] Maximum link list size (messages locked) per connection in the XX
+   protection. */
+#define TCM_REG_XX_MAX_LL_SZ                                    0x50044
+/* [RW 6] The maximum number of pending messages; which may be stored in XX
+   protection. ~tcm_registers_xx_free.xx_free is read on read. */
+#define TCM_REG_XX_MSG_NUM                                      0x50224
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define TCM_REG_XX_OVFL_EVNT_ID                                 0x50048
+/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
+   The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
+   header pointer. */
+#define TCM_REG_XX_TABLE                                        0x50240
+/* [RW 4] Load value for for cfc ac credit cnt. */
+#define TM_REG_CFC_AC_CRDCNT_VAL                                0x164208
+/* [RW 4] Load value for cfc cld credit cnt. */
+#define TM_REG_CFC_CLD_CRDCNT_VAL                               0x164210
+/* [RW 8] Client0 context region. */
+#define TM_REG_CL0_CONT_REGION                                  0x164030
+/* [RW 8] Client1 context region. */
+#define TM_REG_CL1_CONT_REGION                                  0x164034
+/* [RW 8] Client2 context region. */
+#define TM_REG_CL2_CONT_REGION                                  0x164038
+/* [RW 2] Client in High priority client number. */
+#define TM_REG_CLIN_PRIOR0_CLIENT                               0x164024
+/* [RW 4] Load value for clout0 cred cnt. */
+#define TM_REG_CLOUT_CRDCNT0_VAL                                0x164220
+/* [RW 4] Load value for clout1 cred cnt. */
+#define TM_REG_CLOUT_CRDCNT1_VAL                                0x164228
+/* [RW 4] Load value for clout2 cred cnt. */
+#define TM_REG_CLOUT_CRDCNT2_VAL                                0x164230
+/* [RW 1] Enable client0 input. */
+#define TM_REG_EN_CL0_INPUT                                     0x164008
+/* [RW 1] Enable client1 input. */
+#define TM_REG_EN_CL1_INPUT                                     0x16400c
+/* [RW 1] Enable client2 input. */
+#define TM_REG_EN_CL2_INPUT                                     0x164010
+#define TM_REG_EN_LINEAR0_TIMER                                 0x164014
+/* [RW 1] Enable real time counter. */
+#define TM_REG_EN_REAL_TIME_CNT                                 0x1640d8
+/* [RW 1] Enable for Timers state machines. */
+#define TM_REG_EN_TIMERS                                        0x164000
+/* [RW 4] Load value for expiration credit cnt. CFC max number of
+   outstanding load requests for timers (expiration) context loading. */
+#define TM_REG_EXP_CRDCNT_VAL                                   0x164238
+/* [RW 32] Linear0 logic address. */
+#define TM_REG_LIN0_LOGIC_ADDR                                  0x164240
+/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
+#define TM_REG_LIN0_MAX_ACTIVE_CID                              0x164048
+/* [WB 64] Linear0 phy address. */
+#define TM_REG_LIN0_PHY_ADDR                                    0x164270
+/* [RW 1] Linear0 physical address valid. */
+#define TM_REG_LIN0_PHY_ADDR_VALID                              0x164248
+#define TM_REG_LIN0_SCAN_ON                                     0x1640d0
+/* [RW 24] Linear0 array scan timeout. */
+#define TM_REG_LIN0_SCAN_TIME                                   0x16403c
+/* [RW 32] Linear1 logic address. */
+#define TM_REG_LIN1_LOGIC_ADDR                                  0x164250
+/* [WB 64] Linear1 phy address. */
+#define TM_REG_LIN1_PHY_ADDR                                    0x164280
+/* [RW 1] Linear1 physical address valid. */
+#define TM_REG_LIN1_PHY_ADDR_VALID                              0x164258
+/* [RW 6] Linear timer set_clear fifo threshold. */
+#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR                       0x164070
+/* [RW 2] Load value for pci arbiter credit cnt. */
+#define TM_REG_PCIARB_CRDCNT_VAL                                0x164260
+/* [RW 20] The amount of hardware cycles for each timer tick. */
+#define TM_REG_TIMER_TICK_SIZE                                  0x16401c
+/* [RW 8] Timers Context region. */
+#define TM_REG_TM_CONTEXT_REGION                                0x164044
+/* [RW 1] Interrupt mask register #0 read/write */
+#define TM_REG_TM_INT_MASK                                      0x1640fc
+/* [R 1] Interrupt register #0 read */
+#define TM_REG_TM_INT_STS                                       0x1640f0
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define TSDM_REG_AGG_INT_EVENT_0                                0x42038
+#define TSDM_REG_AGG_INT_EVENT_1                                0x4203c
+#define TSDM_REG_AGG_INT_EVENT_2                                0x42040
+#define TSDM_REG_AGG_INT_EVENT_3                                0x42044
+#define TSDM_REG_AGG_INT_EVENT_4                                0x42048
+/* [RW 1] The T bit for aggregated interrupt 0 */
+#define TSDM_REG_AGG_INT_T_0                                    0x420b8
+#define TSDM_REG_AGG_INT_T_1                                    0x420bc
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define TSDM_REG_CFC_RSP_START_ADDR                             0x42008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define TSDM_REG_CMP_COUNTER_MAX0                               0x4201c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define TSDM_REG_CMP_COUNTER_MAX1                               0x42020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define TSDM_REG_CMP_COUNTER_MAX2                               0x42024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define TSDM_REG_CMP_COUNTER_MAX3                               0x42028
+/* [RW 13] The start address in the internal RAM for the completion
+   counters. */
+#define TSDM_REG_CMP_COUNTER_START_ADDR                         0x4200c
+#define TSDM_REG_ENABLE_IN1                                     0x42238
+#define TSDM_REG_ENABLE_IN2                                     0x4223c
+#define TSDM_REG_ENABLE_OUT1                                    0x42240
+#define TSDM_REG_ENABLE_OUT2                                    0x42244
+/* [RW 4] The initial number of messages that can be sent to the pxp control
+   interface without receiving any ACK. */
+#define TSDM_REG_INIT_CREDIT_PXP_CTRL                           0x424bc
+/* [ST 32] The number of ACK after placement messages received */
+#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE                         0x4227c
+/* [ST 32] The number of packet end messages received from the parser */
+#define TSDM_REG_NUM_OF_PKT_END_MSG                             0x42274
+/* [ST 32] The number of requests received from the pxp async if */
+#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ                           0x42278
+/* [ST 32] The number of commands received in queue 0 */
+#define TSDM_REG_NUM_OF_Q0_CMD                                  0x42248
+/* [ST 32] The number of commands received in queue 10 */
+#define TSDM_REG_NUM_OF_Q10_CMD                                 0x4226c
+/* [ST 32] The number of commands received in queue 11 */
+#define TSDM_REG_NUM_OF_Q11_CMD                                 0x42270
+/* [ST 32] The number of commands received in queue 1 */
+#define TSDM_REG_NUM_OF_Q1_CMD                                  0x4224c
+/* [ST 32] The number of commands received in queue 3 */
+#define TSDM_REG_NUM_OF_Q3_CMD                                  0x42250
+/* [ST 32] The number of commands received in queue 4 */
+#define TSDM_REG_NUM_OF_Q4_CMD                                  0x42254
+/* [ST 32] The number of commands received in queue 5 */
+#define TSDM_REG_NUM_OF_Q5_CMD                                  0x42258
+/* [ST 32] The number of commands received in queue 6 */
+#define TSDM_REG_NUM_OF_Q6_CMD                                  0x4225c
+/* [ST 32] The number of commands received in queue 7 */
+#define TSDM_REG_NUM_OF_Q7_CMD                                  0x42260
+/* [ST 32] The number of commands received in queue 8 */
+#define TSDM_REG_NUM_OF_Q8_CMD                                  0x42264
+/* [ST 32] The number of commands received in queue 9 */
+#define TSDM_REG_NUM_OF_Q9_CMD                                  0x42268
+/* [RW 13] The start address in the internal RAM for the packet end message */
+#define TSDM_REG_PCK_END_MSG_START_ADDR                         0x42014
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define TSDM_REG_Q_COUNTER_START_ADDR                           0x42010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                       0x42548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_PARSER_EMPTY                              0x42550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define TSDM_REG_SYNC_SYNC_EMPTY                                0x42558
+/* [RW 32] Tick for timer counter. Applicable only when
+   ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
+#define TSDM_REG_TIMER_TICK                                     0x42000
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSDM_REG_TSDM_INT_MASK_0                                0x4229c
+#define TSDM_REG_TSDM_INT_MASK_1                                0x422ac
+/* [R 32] Interrupt register #0 read */
+#define TSDM_REG_TSDM_INT_STS_0                                 0x42290
+#define TSDM_REG_TSDM_INT_STS_1                                 0x422a0
+/* [RW 11] Parity mask register #0 read/write */
+#define TSDM_REG_TSDM_PRTY_MASK                                 0x422bc
+/* [R 11] Parity register #0 read */
+#define TSDM_REG_TSDM_PRTY_STS                                  0x422b0
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define TSEM_REG_ARB_CYCLE_SIZE                                 0x180034
+/* [RW 3] The source that is associated with arbitration element 0. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2 */
+#define TSEM_REG_ARB_ELEMENT0                                   0x180020
+/* [RW 3] The source that is associated with arbitration element 1. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
+#define TSEM_REG_ARB_ELEMENT1                                   0x180024
+/* [RW 3] The source that is associated with arbitration element 2. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~tsem_registers_arb_element0.arb_element0
+   and ~tsem_registers_arb_element1.arb_element1 */
+#define TSEM_REG_ARB_ELEMENT2                                   0x180028
+/* [RW 3] The source that is associated with arbitration element 3. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+   not be equal to register ~tsem_registers_arb_element0.arb_element0 and
+   ~tsem_registers_arb_element1.arb_element1 and
+   ~tsem_registers_arb_element2.arb_element2 */
+#define TSEM_REG_ARB_ELEMENT3                                   0x18002c
+/* [RW 3] The source that is associated with arbitration element 4. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~tsem_registers_arb_element0.arb_element0
+   and ~tsem_registers_arb_element1.arb_element1 and
+   ~tsem_registers_arb_element2.arb_element2 and
+   ~tsem_registers_arb_element3.arb_element3 */
+#define TSEM_REG_ARB_ELEMENT4                                   0x180030
+#define TSEM_REG_ENABLE_IN                                      0x1800a4
+#define TSEM_REG_ENABLE_OUT                                     0x1800a8
+/* [RW 32] This address space contains all registers and memories that are
+   placed in SEM_FAST block. The SEM_FAST registers are described in
+   appendix B. In order to access the sem_fast registers the base address
+   ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
+#define TSEM_REG_FAST_MEMORY                                    0x1a0000
+/* [RW 1] Disables input messages from FIC0 May be updated during run_time
+   by the microcode */
+#define TSEM_REG_FIC0_DISABLE                                   0x180224
+/* [RW 1] Disables input messages from FIC1 May be updated during run_time
+   by the microcode */
+#define TSEM_REG_FIC1_DISABLE                                   0x180234
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+   the middle of the work */
+#define TSEM_REG_INT_TABLE                                      0x180400
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC0 */
+#define TSEM_REG_MSG_NUM_FIC0                                   0x180000
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC1 */
+#define TSEM_REG_MSG_NUM_FIC1                                   0x180004
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC0 */
+#define TSEM_REG_MSG_NUM_FOC0                                   0x180008
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC1 */
+#define TSEM_REG_MSG_NUM_FOC1                                   0x18000c
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC2 */
+#define TSEM_REG_MSG_NUM_FOC2                                   0x180010
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC3 */
+#define TSEM_REG_MSG_NUM_FOC3                                   0x180014
+/* [RW 1] Disables input messages from the passive buffer May be updated
+   during run_time by the microcode */
+#define TSEM_REG_PAS_DISABLE                                    0x18024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define TSEM_REG_PASSIVE_BUFFER                                 0x181000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define TSEM_REG_PRAM                                           0x1c0000
+/* [R 8] Valid sleeping threads indication have bit per thread */
+#define TSEM_REG_SLEEP_THREADS_VALID                            0x18026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define TSEM_REG_SLOW_EXT_STORE_EMPTY                           0x1802a0
+/* [RW 8] List of free threads . There is a bit per thread. */
+#define TSEM_REG_THREADS_LIST                                   0x1802e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define TSEM_REG_TS_0_AS                                        0x180038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define TSEM_REG_TS_10_AS                                       0x180060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define TSEM_REG_TS_11_AS                                       0x180064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define TSEM_REG_TS_12_AS                                       0x180068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define TSEM_REG_TS_13_AS                                       0x18006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define TSEM_REG_TS_14_AS                                       0x180070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define TSEM_REG_TS_15_AS                                       0x180074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define TSEM_REG_TS_16_AS                                       0x180078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define TSEM_REG_TS_17_AS                                       0x18007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define TSEM_REG_TS_18_AS                                       0x180080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define TSEM_REG_TS_1_AS                                        0x18003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define TSEM_REG_TS_2_AS                                        0x180040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define TSEM_REG_TS_3_AS                                        0x180044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define TSEM_REG_TS_4_AS                                        0x180048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define TSEM_REG_TS_5_AS                                        0x18004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define TSEM_REG_TS_6_AS                                        0x180050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define TSEM_REG_TS_7_AS                                        0x180054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define TSEM_REG_TS_8_AS                                        0x180058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define TSEM_REG_TS_9_AS                                        0x18005c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define TSEM_REG_TSEM_INT_MASK_0                                0x180100
+#define TSEM_REG_TSEM_INT_MASK_1                                0x180110
+/* [R 32] Interrupt register #0 read */
+#define TSEM_REG_TSEM_INT_STS_0                                 0x1800f4
+#define TSEM_REG_TSEM_INT_STS_1                                 0x180104
+/* [RW 32] Parity mask register #0 read/write */
+#define TSEM_REG_TSEM_PRTY_MASK_0                               0x180120
+#define TSEM_REG_TSEM_PRTY_MASK_1                               0x180130
+/* [R 32] Parity register #0 read */
+#define TSEM_REG_TSEM_PRTY_STS_0                                0x180114
+#define TSEM_REG_TSEM_PRTY_STS_1                                0x180124
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define UCM_REG_CAM_OCCUP                                       0xe0170
+/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define UCM_REG_CDU_AG_RD_IFEN                                  0xe0038
+/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
+   are disregarded; all other signals are treated as usual; if 1 - normal
+   activity. */
+#define UCM_REG_CDU_AG_WR_IFEN                                  0xe0034
+/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define UCM_REG_CDU_SM_RD_IFEN                                  0xe0040
+/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
+   input is disregarded; all other signals are treated as usual; if 1 -
+   normal activity. */
+#define UCM_REG_CDU_SM_WR_IFEN                                  0xe003c
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 1 at start-up. */
+#define UCM_REG_CFC_INIT_CRD                                    0xe0204
+/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_CP_WEIGHT                                       0xe00c4
+/* [RW 1] Input csem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_CSEM_IFEN                                       0xe0028
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the csem interface is detected. */
+#define UCM_REG_CSEM_LENGTH_MIS                                 0xe0160
+/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_CSEM_WEIGHT                                     0xe00b8
+/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_DORQ_IFEN                                       0xe0030
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the dorq interface is detected. */
+#define UCM_REG_DORQ_LENGTH_MIS                                 0xe0168
+/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_DORQ_WEIGHT                                     0xe00c0
+/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
+#define UCM_REG_ERR_EVNT_ID                                     0xe00a4
+/* [RW 28] The CM erroneous header for QM and Timers formatting. */
+#define UCM_REG_ERR_UCM_HDR                                     0xe00a0
+/* [RW 8] The Event ID for Timers expiration. */
+#define UCM_REG_EXPR_EVNT_ID                                    0xe00a8
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define UCM_REG_FIC0_INIT_CRD                                   0xe020c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define UCM_REG_FIC1_INIT_CRD                                   0xe0210
+/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
+   - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
+   ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
+   ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
+#define UCM_REG_GR_ARB_TYPE                                     0xe0144
+/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed that the Store channel group is
+   compliment to the others. */
+#define UCM_REG_GR_LD0_PR                                       0xe014c
+/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed that the Store channel group is
+   compliment to the others. */
+#define UCM_REG_GR_LD1_PR                                       0xe0150
+/* [RW 2] The queue index for invalidate counter flag decision. */
+#define UCM_REG_INV_CFLG_Q                                      0xe00e4
+/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
+   sent to STORM; for a specific connection type. the double REG-pairs are
+   used in order to align to STORM context row size of 128 bits. The offset
+   of these data in the STORM context is always 0. Index _i stands for the
+   connection type (one of 16). */
+#define UCM_REG_N_SM_CTX_LD_0                                   0xe0054
+#define UCM_REG_N_SM_CTX_LD_1                                   0xe0058
+#define UCM_REG_N_SM_CTX_LD_2                                   0xe005c
+#define UCM_REG_N_SM_CTX_LD_3                                   0xe0060
+#define UCM_REG_N_SM_CTX_LD_4                                   0xe0064
+#define UCM_REG_N_SM_CTX_LD_5                                   0xe0068
+#define UCM_REG_PHYS_QNUM0_0                                    0xe0110
+#define UCM_REG_PHYS_QNUM0_1                                    0xe0114
+#define UCM_REG_PHYS_QNUM1_0                                    0xe0118
+#define UCM_REG_PHYS_QNUM1_1                                    0xe011c
+#define UCM_REG_PHYS_QNUM2_0                                    0xe0120
+#define UCM_REG_PHYS_QNUM2_1                                    0xe0124
+#define UCM_REG_PHYS_QNUM3_0                                    0xe0128
+#define UCM_REG_PHYS_QNUM3_1                                    0xe012c
+/* [RW 8] The Event ID for Timers formatting in case of stop done. */
+#define UCM_REG_STOP_EVNT_ID                                    0xe00ac
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the STORM interface is detected. */
+#define UCM_REG_STORM_LENGTH_MIS                                0xe0154
+/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_STORM_UCM_IFEN                                  0xe0010
+/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_STORM_WEIGHT                                    0xe00b0
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 4 at start-up. */
+#define UCM_REG_TM_INIT_CRD                                     0xe021c
+/* [RW 28] The CM header for Timers expiration command. */
+#define UCM_REG_TM_UCM_HDR                                      0xe009c
+/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_TM_UCM_IFEN                                     0xe001c
+/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_TM_WEIGHT                                       0xe00d4
+/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_TSEM_IFEN                                       0xe0024
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the tsem interface is detected. */
+#define UCM_REG_TSEM_LENGTH_MIS                                 0xe015c
+/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_TSEM_WEIGHT                                     0xe00b4
+/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define UCM_REG_UCM_CFC_IFEN                                    0xe0044
+/* [RW 11] Interrupt mask register #0 read/write */
+#define UCM_REG_UCM_INT_MASK                                    0xe01d4
+/* [R 11] Interrupt register #0 read */
+#define UCM_REG_UCM_INT_STS                                     0xe01c8
+/* [R 27] Parity register #0 read */
+#define UCM_REG_UCM_PRTY_STS                                    0xe01d8
+/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
+   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+   Is used to determine the number of the AG context REG-pairs written back;
+   when the Reg1WbFlg isn't set. */
+#define UCM_REG_UCM_REG0_SZ                                     0xe00dc
+/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define UCM_REG_UCM_STORM0_IFEN                                 0xe0004
+/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define UCM_REG_UCM_STORM1_IFEN                                 0xe0008
+/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_UCM_TM_IFEN                                     0xe0020
+/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define UCM_REG_UCM_UQM_IFEN                                    0xe000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
+#define UCM_REG_UCM_UQM_USE_Q                                   0xe00d8
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 32 at start-up. */
+#define UCM_REG_UQM_INIT_CRD                                    0xe0220
+/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_UQM_P_WEIGHT                                    0xe00cc
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_UQM_S_WEIGHT                                    0xe00d0
+/* [RW 28] The CM header value for QM request (primary). */
+#define UCM_REG_UQM_UCM_HDR_P                                   0xe0094
+/* [RW 28] The CM header value for QM request (secondary). */
+#define UCM_REG_UQM_UCM_HDR_S                                   0xe0098
+/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define UCM_REG_UQM_UCM_IFEN                                    0xe0014
+/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define UCM_REG_USDM_IFEN                                       0xe0018
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the SDM interface is detected. */
+#define UCM_REG_USDM_LENGTH_MIS                                 0xe0158
+/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_USDM_WEIGHT                                     0xe00c8
+/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define UCM_REG_XSEM_IFEN                                       0xe002c
+/* [RC 1] Set when the message length mismatch (relative to last indication)
+   at the xsem interface isdetected. */
+#define UCM_REG_XSEM_LENGTH_MIS                                 0xe0164
+/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define UCM_REG_XSEM_WEIGHT                                     0xe00bc
+/* [RW 20] Indirect access to the descriptor table of the XX protection
+   mechanism. The fields are:[5:0] - message length; 14:6] - message
+   pointer; 19:15] - next pointer. */
+#define UCM_REG_XX_DESCR_TABLE                                  0xe0280
+#define UCM_REG_XX_DESCR_TABLE_SIZE                             32
+/* [R 6] Use to read the XX protection Free counter. */
+#define UCM_REG_XX_FREE                                         0xe016c
+/* [RW 6] Initial value for the credit counter; responsible for fulfilling
+   of the Input Stage XX protection buffer by the XX protection pending
+   messages. Write writes the initial credit value; read returns the current
+   value of the credit counter. Must be initialized to 12 at start-up. */
+#define UCM_REG_XX_INIT_CRD                                     0xe0224
+/* [RW 6] The maximum number of pending messages; which may be stored in XX
+   protection. ~ucm_registers_xx_free.xx_free read on read. */
+#define UCM_REG_XX_MSG_NUM                                      0xe0228
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define UCM_REG_XX_OVFL_EVNT_ID                                 0xe004c
+/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
+   The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
+   header pointer. */
+#define UCM_REG_XX_TABLE                                        0xe0300
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define USDM_REG_AGG_INT_EVENT_0                                0xc4038
+#define USDM_REG_AGG_INT_EVENT_1                                0xc403c
+#define USDM_REG_AGG_INT_EVENT_2                                0xc4040
+#define USDM_REG_AGG_INT_EVENT_4                                0xc4048
+#define USDM_REG_AGG_INT_EVENT_5                                0xc404c
+#define USDM_REG_AGG_INT_EVENT_6                                0xc4050
+/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
+   or auto-mask-mode (1) */
+#define USDM_REG_AGG_INT_MODE_0                                 0xc41b8
+#define USDM_REG_AGG_INT_MODE_1                                 0xc41bc
+#define USDM_REG_AGG_INT_MODE_4                                 0xc41c8
+#define USDM_REG_AGG_INT_MODE_5                                 0xc41cc
+#define USDM_REG_AGG_INT_MODE_6                                 0xc41d0
+/* [RW 1] The T bit for aggregated interrupt 5 */
+#define USDM_REG_AGG_INT_T_5                                    0xc40cc
+#define USDM_REG_AGG_INT_T_6                                    0xc40d0
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define USDM_REG_CFC_RSP_START_ADDR                             0xc4008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define USDM_REG_CMP_COUNTER_MAX0                               0xc401c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define USDM_REG_CMP_COUNTER_MAX1                               0xc4020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define USDM_REG_CMP_COUNTER_MAX2                               0xc4024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define USDM_REG_CMP_COUNTER_MAX3                               0xc4028
+/* [RW 13] The start address in the internal RAM for the completion
+   counters. */
+#define USDM_REG_CMP_COUNTER_START_ADDR                         0xc400c
+#define USDM_REG_ENABLE_IN1                                     0xc4238
+#define USDM_REG_ENABLE_IN2                                     0xc423c
+#define USDM_REG_ENABLE_OUT1                                    0xc4240
+#define USDM_REG_ENABLE_OUT2                                    0xc4244
+/* [RW 4] The initial number of messages that can be sent to the pxp control
+   interface without receiving any ACK. */
+#define USDM_REG_INIT_CREDIT_PXP_CTRL                           0xc44c0
+/* [ST 32] The number of ACK after placement messages received */
+#define USDM_REG_NUM_OF_ACK_AFTER_PLACE                         0xc4280
+/* [ST 32] The number of packet end messages received from the parser */
+#define USDM_REG_NUM_OF_PKT_END_MSG                             0xc4278
+/* [ST 32] The number of requests received from the pxp async if */
+#define USDM_REG_NUM_OF_PXP_ASYNC_REQ                           0xc427c
+/* [ST 32] The number of commands received in queue 0 */
+#define USDM_REG_NUM_OF_Q0_CMD                                  0xc4248
+/* [ST 32] The number of commands received in queue 10 */
+#define USDM_REG_NUM_OF_Q10_CMD                                 0xc4270
+/* [ST 32] The number of commands received in queue 11 */
+#define USDM_REG_NUM_OF_Q11_CMD                                 0xc4274
+/* [ST 32] The number of commands received in queue 1 */
+#define USDM_REG_NUM_OF_Q1_CMD                                  0xc424c
+/* [ST 32] The number of commands received in queue 2 */
+#define USDM_REG_NUM_OF_Q2_CMD                                  0xc4250
+/* [ST 32] The number of commands received in queue 3 */
+#define USDM_REG_NUM_OF_Q3_CMD                                  0xc4254
+/* [ST 32] The number of commands received in queue 4 */
+#define USDM_REG_NUM_OF_Q4_CMD                                  0xc4258
+/* [ST 32] The number of commands received in queue 5 */
+#define USDM_REG_NUM_OF_Q5_CMD                                  0xc425c
+/* [ST 32] The number of commands received in queue 6 */
+#define USDM_REG_NUM_OF_Q6_CMD                                  0xc4260
+/* [ST 32] The number of commands received in queue 7 */
+#define USDM_REG_NUM_OF_Q7_CMD                                  0xc4264
+/* [ST 32] The number of commands received in queue 8 */
+#define USDM_REG_NUM_OF_Q8_CMD                                  0xc4268
+/* [ST 32] The number of commands received in queue 9 */
+#define USDM_REG_NUM_OF_Q9_CMD                                  0xc426c
+/* [RW 13] The start address in the internal RAM for the packet end message */
+#define USDM_REG_PCK_END_MSG_START_ADDR                         0xc4014
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define USDM_REG_Q_COUNTER_START_ADDR                           0xc4010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                       0xc4550
+/* [R 1] parser fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_PARSER_EMPTY                              0xc4558
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define USDM_REG_SYNC_SYNC_EMPTY                                0xc4560
+/* [RW 32] Tick for timer counter. Applicable only when
+   ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
+#define USDM_REG_TIMER_TICK                                     0xc4000
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USDM_REG_USDM_INT_MASK_0                                0xc42a0
+#define USDM_REG_USDM_INT_MASK_1                                0xc42b0
+/* [R 32] Interrupt register #0 read */
+#define USDM_REG_USDM_INT_STS_0                                 0xc4294
+#define USDM_REG_USDM_INT_STS_1                                 0xc42a4
+/* [RW 11] Parity mask register #0 read/write */
+#define USDM_REG_USDM_PRTY_MASK                                 0xc42c0
+/* [R 11] Parity register #0 read */
+#define USDM_REG_USDM_PRTY_STS                                  0xc42b4
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define USEM_REG_ARB_CYCLE_SIZE                                 0x300034
+/* [RW 3] The source that is associated with arbitration element 0. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2 */
+#define USEM_REG_ARB_ELEMENT0                                   0x300020
+/* [RW 3] The source that is associated with arbitration element 1. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
+#define USEM_REG_ARB_ELEMENT1                                   0x300024
+/* [RW 3] The source that is associated with arbitration element 2. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~usem_registers_arb_element0.arb_element0
+   and ~usem_registers_arb_element1.arb_element1 */
+#define USEM_REG_ARB_ELEMENT2                                   0x300028
+/* [RW 3] The source that is associated with arbitration element 3. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+   not be equal to register ~usem_registers_arb_element0.arb_element0 and
+   ~usem_registers_arb_element1.arb_element1 and
+   ~usem_registers_arb_element2.arb_element2 */
+#define USEM_REG_ARB_ELEMENT3                                   0x30002c
+/* [RW 3] The source that is associated with arbitration element 4. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~usem_registers_arb_element0.arb_element0
+   and ~usem_registers_arb_element1.arb_element1 and
+   ~usem_registers_arb_element2.arb_element2 and
+   ~usem_registers_arb_element3.arb_element3 */
+#define USEM_REG_ARB_ELEMENT4                                   0x300030
+#define USEM_REG_ENABLE_IN                                      0x3000a4
+#define USEM_REG_ENABLE_OUT                                     0x3000a8
+/* [RW 32] This address space contains all registers and memories that are
+   placed in SEM_FAST block. The SEM_FAST registers are described in
+   appendix B. In order to access the sem_fast registers the base address
+   ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
+#define USEM_REG_FAST_MEMORY                                    0x320000
+/* [RW 1] Disables input messages from FIC0 May be updated during run_time
+   by the microcode */
+#define USEM_REG_FIC0_DISABLE                                   0x300224
+/* [RW 1] Disables input messages from FIC1 May be updated during run_time
+   by the microcode */
+#define USEM_REG_FIC1_DISABLE                                   0x300234
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+   the middle of the work */
+#define USEM_REG_INT_TABLE                                      0x300400
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC0 */
+#define USEM_REG_MSG_NUM_FIC0                                   0x300000
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC1 */
+#define USEM_REG_MSG_NUM_FIC1                                   0x300004
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC0 */
+#define USEM_REG_MSG_NUM_FOC0                                   0x300008
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC1 */
+#define USEM_REG_MSG_NUM_FOC1                                   0x30000c
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC2 */
+#define USEM_REG_MSG_NUM_FOC2                                   0x300010
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC3 */
+#define USEM_REG_MSG_NUM_FOC3                                   0x300014
+/* [RW 1] Disables input messages from the passive buffer May be updated
+   during run_time by the microcode */
+#define USEM_REG_PAS_DISABLE                                    0x30024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define USEM_REG_PASSIVE_BUFFER                                 0x302000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define USEM_REG_PRAM                                           0x340000
+/* [R 16] Valid sleeping threads indication have bit per thread */
+#define USEM_REG_SLEEP_THREADS_VALID                            0x30026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define USEM_REG_SLOW_EXT_STORE_EMPTY                           0x3002a0
+/* [RW 16] List of free threads . There is a bit per thread. */
+#define USEM_REG_THREADS_LIST                                   0x3002e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define USEM_REG_TS_0_AS                                        0x300038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define USEM_REG_TS_10_AS                                       0x300060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define USEM_REG_TS_11_AS                                       0x300064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define USEM_REG_TS_12_AS                                       0x300068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define USEM_REG_TS_13_AS                                       0x30006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define USEM_REG_TS_14_AS                                       0x300070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define USEM_REG_TS_15_AS                                       0x300074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define USEM_REG_TS_16_AS                                       0x300078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define USEM_REG_TS_17_AS                                       0x30007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define USEM_REG_TS_18_AS                                       0x300080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define USEM_REG_TS_1_AS                                        0x30003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define USEM_REG_TS_2_AS                                        0x300040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define USEM_REG_TS_3_AS                                        0x300044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define USEM_REG_TS_4_AS                                        0x300048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define USEM_REG_TS_5_AS                                        0x30004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define USEM_REG_TS_6_AS                                        0x300050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define USEM_REG_TS_7_AS                                        0x300054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define USEM_REG_TS_8_AS                                        0x300058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define USEM_REG_TS_9_AS                                        0x30005c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define USEM_REG_USEM_INT_MASK_0                                0x300110
+#define USEM_REG_USEM_INT_MASK_1                                0x300120
+/* [R 32] Interrupt register #0 read */
+#define USEM_REG_USEM_INT_STS_0                                 0x300104
+#define USEM_REG_USEM_INT_STS_1                                 0x300114
+/* [RW 32] Parity mask register #0 read/write */
+#define USEM_REG_USEM_PRTY_MASK_0                               0x300130
+#define USEM_REG_USEM_PRTY_MASK_1                               0x300140
+/* [R 32] Parity register #0 read */
+#define USEM_REG_USEM_PRTY_STS_0                                0x300124
+#define USEM_REG_USEM_PRTY_STS_1                                0x300134
+/* [RW 2] The queue index for registration on Aux1 counter flag. */
+#define XCM_REG_AUX1_Q                                          0x20134
+/* [RW 2] Per each decision rule the queue index to register to. */
+#define XCM_REG_AUX_CNT_FLG_Q_19                                0x201b0
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define XCM_REG_CAM_OCCUP                                       0x20244
+/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define XCM_REG_CDU_AG_RD_IFEN                                  0x20044
+/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
+   are disregarded; all other signals are treated as usual; if 1 - normal
+   activity. */
+#define XCM_REG_CDU_AG_WR_IFEN                                  0x20040
+/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
+   disregarded; valid output is deasserted; all other signals are treated as
+   usual; if 1 - normal activity. */
+#define XCM_REG_CDU_SM_RD_IFEN                                  0x2004c
+/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
+   input is disregarded; all other signals are treated as usual; if 1 -
+   normal activity. */
+#define XCM_REG_CDU_SM_WR_IFEN                                  0x20048
+/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 1 at start-up. */
+#define XCM_REG_CFC_INIT_CRD                                    0x20404
+/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_CP_WEIGHT                                       0x200dc
+/* [RW 1] Input csem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_CSEM_IFEN                                       0x20028
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the csem interface. */
+#define XCM_REG_CSEM_LENGTH_MIS                                 0x20228
+/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_CSEM_WEIGHT                                     0x200c4
+/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_DORQ_IFEN                                       0x20030
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the dorq interface. */
+#define XCM_REG_DORQ_LENGTH_MIS                                 0x20230
+/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_DORQ_WEIGHT                                     0x200cc
+/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
+#define XCM_REG_ERR_EVNT_ID                                     0x200b0
+/* [RW 28] The CM erroneous header for QM and Timers formatting. */
+#define XCM_REG_ERR_XCM_HDR                                     0x200ac
+/* [RW 8] The Event ID for Timers expiration. */
+#define XCM_REG_EXPR_EVNT_ID                                    0x200b4
+/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define XCM_REG_FIC0_INIT_CRD                                   0x2040c
+/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 64 at start-up. */
+#define XCM_REG_FIC1_INIT_CRD                                   0x20410
+#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0                           0x20118
+#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1                           0x2011c
+#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0                           0x20108
+#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1                           0x2010c
+/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
+   - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
+   ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
+   ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
+#define XCM_REG_GR_ARB_TYPE                                     0x2020c
+/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed that the Channel group is the
+   compliment of the other 3 groups. */
+#define XCM_REG_GR_LD0_PR                                       0x20214
+/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
+   highest priority is 3. It is supposed that the Channel group is the
+   compliment of the other 3 groups. */
+#define XCM_REG_GR_LD1_PR                                       0x20218
+/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_NIG0_IFEN                                       0x20038
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the nig0 interface. */
+#define XCM_REG_NIG0_LENGTH_MIS                                 0x20238
+/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_NIG0_WEIGHT                                     0x200d4
+/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_NIG1_IFEN                                       0x2003c
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the nig1 interface. */
+#define XCM_REG_NIG1_LENGTH_MIS                                 0x2023c
+/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
+   sent to STORM; for a specific connection type. The double REG-pairs are
+   used in order to align to STORM context row size of 128 bits. The offset
+   of these data in the STORM context is always 0. Index _i stands for the
+   connection type (one of 16). */
+#define XCM_REG_N_SM_CTX_LD_0                                   0x20060
+#define XCM_REG_N_SM_CTX_LD_1                                   0x20064
+#define XCM_REG_N_SM_CTX_LD_2                                   0x20068
+#define XCM_REG_N_SM_CTX_LD_3                                   0x2006c
+#define XCM_REG_N_SM_CTX_LD_4                                   0x20070
+#define XCM_REG_N_SM_CTX_LD_5                                   0x20074
+/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_PBF_IFEN                                        0x20034
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the pbf interface. */
+#define XCM_REG_PBF_LENGTH_MIS                                  0x20234
+/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_PBF_WEIGHT                                      0x200d0
+#define XCM_REG_PHYS_QNUM3_0                                    0x20100
+#define XCM_REG_PHYS_QNUM3_1                                    0x20104
+/* [RW 8] The Event ID for Timers formatting in case of stop done. */
+#define XCM_REG_STOP_EVNT_ID                                    0x200b8
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the STORM interface. */
+#define XCM_REG_STORM_LENGTH_MIS                                0x2021c
+/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_STORM_WEIGHT                                    0x200bc
+/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_STORM_XCM_IFEN                                  0x20010
+/* [RW 4] Timers output initial credit. Max credit available - 15.Write
+   writes the initial credit value; read returns the current value of the
+   credit counter. Must be initialized to 4 at start-up. */
+#define XCM_REG_TM_INIT_CRD                                     0x2041c
+/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_TM_WEIGHT                                       0x200ec
+/* [RW 28] The CM header for Timers expiration command. */
+#define XCM_REG_TM_XCM_HDR                                      0x200a8
+/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_TM_XCM_IFEN                                     0x2001c
+/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_TSEM_IFEN                                       0x20024
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the tsem interface. */
+#define XCM_REG_TSEM_LENGTH_MIS                                 0x20224
+/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_TSEM_WEIGHT                                     0x200c0
+/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
+#define XCM_REG_UNA_GT_NXT_Q                                    0x20120
+/* [RW 1] Input usem Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_USEM_IFEN                                       0x2002c
+/* [RC 1] Message length mismatch (relative to last indication) at the usem
+   interface. */
+#define XCM_REG_USEM_LENGTH_MIS                                 0x2022c
+/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_USEM_WEIGHT                                     0x200c8
+#define XCM_REG_WU_DA_CNT_CMD00                                 0x201d4
+#define XCM_REG_WU_DA_CNT_CMD01                                 0x201d8
+#define XCM_REG_WU_DA_CNT_CMD10                                 0x201dc
+#define XCM_REG_WU_DA_CNT_CMD11                                 0x201e0
+#define XCM_REG_WU_DA_CNT_UPD_VAL00                             0x201e4
+#define XCM_REG_WU_DA_CNT_UPD_VAL01                             0x201e8
+#define XCM_REG_WU_DA_CNT_UPD_VAL10                             0x201ec
+#define XCM_REG_WU_DA_CNT_UPD_VAL11                             0x201f0
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00                     0x201c4
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01                     0x201c8
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10                     0x201cc
+#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11                     0x201d0
+/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_XCM_CFC_IFEN                                    0x20050
+/* [RW 14] Interrupt mask register #0 read/write */
+#define XCM_REG_XCM_INT_MASK                                    0x202b4
+/* [R 14] Interrupt register #0 read */
+#define XCM_REG_XCM_INT_STS                                     0x202a8
+/* [R 30] Parity register #0 read */
+#define XCM_REG_XCM_PRTY_STS                                    0x202b8
+/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
+   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+   Is used to determine the number of the AG context REG-pairs written back;
+   when the Reg1WbFlg isn't set. */
+#define XCM_REG_XCM_REG0_SZ                                     0x200f4
+/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_XCM_STORM0_IFEN                                 0x20004
+/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_XCM_STORM1_IFEN                                 0x20008
+/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
+   disregarded; acknowledge output is deasserted; all other signals are
+   treated as usual; if 1 - normal activity. */
+#define XCM_REG_XCM_TM_IFEN                                     0x20020
+/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
+   disregarded; valid is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_XCM_XQM_IFEN                                    0x2000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
+#define XCM_REG_XCM_XQM_USE_Q                                   0x200f0
+/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
+#define XCM_REG_XQM_BYP_ACT_UPD                                 0x200fc
+/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
+   the initial credit value; read returns the current value of the credit
+   counter. Must be initialized to 32 at start-up. */
+#define XCM_REG_XQM_INIT_CRD                                    0x20420
+/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_XQM_P_WEIGHT                                    0x200e4
+/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_XQM_S_WEIGHT                                    0x200e8
+/* [RW 28] The CM header value for QM request (primary). */
+#define XCM_REG_XQM_XCM_HDR_P                                   0x200a0
+/* [RW 28] The CM header value for QM request (secondary). */
+#define XCM_REG_XQM_XCM_HDR_S                                   0x200a4
+/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_XQM_XCM_IFEN                                    0x20014
+/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
+   acknowledge output is deasserted; all other signals are treated as usual;
+   if 1 - normal activity. */
+#define XCM_REG_XSDM_IFEN                                       0x20018
+/* [RC 1] Set at message length mismatch (relative to last indication) at
+   the SDM interface. */
+#define XCM_REG_XSDM_LENGTH_MIS                                 0x20220
+/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+   weight 8 (the most prioritised); 1 stands for weight 1(least
+   prioritised); 2 stands for weight 2; tc. */
+#define XCM_REG_XSDM_WEIGHT                                     0x200e0
+/* [RW 17] Indirect access to the descriptor table of the XX protection
+   mechanism. The fields are: [5:0] - message length; 11:6] - message
+   pointer; 16:12] - next pointer. */
+#define XCM_REG_XX_DESCR_TABLE                                  0x20480
+#define XCM_REG_XX_DESCR_TABLE_SIZE                             32
+/* [R 6] Used to read the XX protection Free counter. */
+#define XCM_REG_XX_FREE                                         0x20240
+/* [RW 6] Initial value for the credit counter; responsible for fulfilling
+   of the Input Stage XX protection buffer by the XX protection pending
+   messages. Max credit available - 3.Write writes the initial credit value;
+   read returns the current value of the credit counter. Must be initialized
+   to 2 at start-up. */
+#define XCM_REG_XX_INIT_CRD                                     0x20424
+/* [RW 6] The maximum number of pending messages; which may be stored in XX
+   protection. ~xcm_registers_xx_free.xx_free read on read. */
+#define XCM_REG_XX_MSG_NUM                                      0x20428
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define XCM_REG_XX_OVFL_EVNT_ID                                 0x20058
+/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
+   The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
+   header pointer. */
+#define XCM_REG_XX_TABLE                                        0x20500
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define XSDM_REG_AGG_INT_EVENT_0                                0x166038
+#define XSDM_REG_AGG_INT_EVENT_1                                0x16603c
+#define XSDM_REG_AGG_INT_EVENT_10                               0x166060
+#define XSDM_REG_AGG_INT_EVENT_11                               0x166064
+#define XSDM_REG_AGG_INT_EVENT_12                               0x166068
+#define XSDM_REG_AGG_INT_EVENT_13                               0x16606c
+#define XSDM_REG_AGG_INT_EVENT_14                               0x166070
+#define XSDM_REG_AGG_INT_EVENT_2                                0x166040
+#define XSDM_REG_AGG_INT_EVENT_3                                0x166044
+#define XSDM_REG_AGG_INT_EVENT_4                                0x166048
+#define XSDM_REG_AGG_INT_EVENT_5                                0x16604c
+#define XSDM_REG_AGG_INT_EVENT_6                                0x166050
+#define XSDM_REG_AGG_INT_EVENT_7                                0x166054
+#define XSDM_REG_AGG_INT_EVENT_8                                0x166058
+#define XSDM_REG_AGG_INT_EVENT_9                                0x16605c
+/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
+   or auto-mask-mode (1) */
+#define XSDM_REG_AGG_INT_MODE_0                                 0x1661b8
+#define XSDM_REG_AGG_INT_MODE_1                                 0x1661bc
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define XSDM_REG_CFC_RSP_START_ADDR                             0x166008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define XSDM_REG_CMP_COUNTER_MAX0                               0x16601c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define XSDM_REG_CMP_COUNTER_MAX1                               0x166020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define XSDM_REG_CMP_COUNTER_MAX2                               0x166024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define XSDM_REG_CMP_COUNTER_MAX3                               0x166028
+/* [RW 13] The start address in the internal RAM for the completion
+   counters. */
+#define XSDM_REG_CMP_COUNTER_START_ADDR                         0x16600c
+#define XSDM_REG_ENABLE_IN1                                     0x166238
+#define XSDM_REG_ENABLE_IN2                                     0x16623c
+#define XSDM_REG_ENABLE_OUT1                                    0x166240
+#define XSDM_REG_ENABLE_OUT2                                    0x166244
+/* [RW 4] The initial number of messages that can be sent to the pxp control
+   interface without receiving any ACK. */
+#define XSDM_REG_INIT_CREDIT_PXP_CTRL                           0x1664bc
+/* [ST 32] The number of ACK after placement messages received */
+#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE                         0x16627c
+/* [ST 32] The number of packet end messages received from the parser */
+#define XSDM_REG_NUM_OF_PKT_END_MSG                             0x166274
+/* [ST 32] The number of requests received from the pxp async if */
+#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ                           0x166278
+/* [ST 32] The number of commands received in queue 0 */
+#define XSDM_REG_NUM_OF_Q0_CMD                                  0x166248
+/* [ST 32] The number of commands received in queue 10 */
+#define XSDM_REG_NUM_OF_Q10_CMD                                 0x16626c
+/* [ST 32] The number of commands received in queue 11 */
+#define XSDM_REG_NUM_OF_Q11_CMD                                 0x166270
+/* [ST 32] The number of commands received in queue 1 */
+#define XSDM_REG_NUM_OF_Q1_CMD                                  0x16624c
+/* [ST 32] The number of commands received in queue 3 */
+#define XSDM_REG_NUM_OF_Q3_CMD                                  0x166250
+/* [ST 32] The number of commands received in queue 4 */
+#define XSDM_REG_NUM_OF_Q4_CMD                                  0x166254
+/* [ST 32] The number of commands received in queue 5 */
+#define XSDM_REG_NUM_OF_Q5_CMD                                  0x166258
+/* [ST 32] The number of commands received in queue 6 */
+#define XSDM_REG_NUM_OF_Q6_CMD                                  0x16625c
+/* [ST 32] The number of commands received in queue 7 */
+#define XSDM_REG_NUM_OF_Q7_CMD                                  0x166260
+/* [ST 32] The number of commands received in queue 8 */
+#define XSDM_REG_NUM_OF_Q8_CMD                                  0x166264
+/* [ST 32] The number of commands received in queue 9 */
+#define XSDM_REG_NUM_OF_Q9_CMD                                  0x166268
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define XSDM_REG_Q_COUNTER_START_ADDR                           0x166010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                       0x166548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_PARSER_EMPTY                              0x166550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define XSDM_REG_SYNC_SYNC_EMPTY                                0x166558
+/* [RW 32] Tick for timer counter. Applicable only when
+   ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
+#define XSDM_REG_TIMER_TICK                                     0x166000
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSDM_REG_XSDM_INT_MASK_0                                0x16629c
+#define XSDM_REG_XSDM_INT_MASK_1                                0x1662ac
+/* [R 32] Interrupt register #0 read */
+#define XSDM_REG_XSDM_INT_STS_0                                 0x166290
+#define XSDM_REG_XSDM_INT_STS_1                                 0x1662a0
+/* [RW 11] Parity mask register #0 read/write */
+#define XSDM_REG_XSDM_PRTY_MASK                                 0x1662bc
+/* [R 11] Parity register #0 read */
+#define XSDM_REG_XSDM_PRTY_STS                                  0x1662b0
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define XSEM_REG_ARB_CYCLE_SIZE                                 0x280034
+/* [RW 3] The source that is associated with arbitration element 0. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2 */
+#define XSEM_REG_ARB_ELEMENT0                                   0x280020
+/* [RW 3] The source that is associated with arbitration element 1. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
+#define XSEM_REG_ARB_ELEMENT1                                   0x280024
+/* [RW 3] The source that is associated with arbitration element 2. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~xsem_registers_arb_element0.arb_element0
+   and ~xsem_registers_arb_element1.arb_element1 */
+#define XSEM_REG_ARB_ELEMENT2                                   0x280028
+/* [RW 3] The source that is associated with arbitration element 3. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+   not be equal to register ~xsem_registers_arb_element0.arb_element0 and
+   ~xsem_registers_arb_element1.arb_element1 and
+   ~xsem_registers_arb_element2.arb_element2 */
+#define XSEM_REG_ARB_ELEMENT3                                   0x28002c
+/* [RW 3] The source that is associated with arbitration element 4. Source
+   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+   sleeping thread with priority 1; 4- sleeping thread with priority 2.
+   Could not be equal to register ~xsem_registers_arb_element0.arb_element0
+   and ~xsem_registers_arb_element1.arb_element1 and
+   ~xsem_registers_arb_element2.arb_element2 and
+   ~xsem_registers_arb_element3.arb_element3 */
+#define XSEM_REG_ARB_ELEMENT4                                   0x280030
+#define XSEM_REG_ENABLE_IN                                      0x2800a4
+#define XSEM_REG_ENABLE_OUT                                     0x2800a8
+/* [RW 32] This address space contains all registers and memories that are
+   placed in SEM_FAST block. The SEM_FAST registers are described in
+   appendix B. In order to access the sem_fast registers the base address
+   ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
+#define XSEM_REG_FAST_MEMORY                                    0x2a0000
+/* [RW 1] Disables input messages from FIC0 May be updated during run_time
+   by the microcode */
+#define XSEM_REG_FIC0_DISABLE                                   0x280224
+/* [RW 1] Disables input messages from FIC1 May be updated during run_time
+   by the microcode */
+#define XSEM_REG_FIC1_DISABLE                                   0x280234
+/* [RW 15] Interrupt table Read and write access to it is not possible in
+   the middle of the work */
+#define XSEM_REG_INT_TABLE                                      0x280400
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC0 */
+#define XSEM_REG_MSG_NUM_FIC0                                   0x280000
+/* [ST 24] Statistics register. The number of messages that entered through
+   FIC1 */
+#define XSEM_REG_MSG_NUM_FIC1                                   0x280004
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC0 */
+#define XSEM_REG_MSG_NUM_FOC0                                   0x280008
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC1 */
+#define XSEM_REG_MSG_NUM_FOC1                                   0x28000c
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC2 */
+#define XSEM_REG_MSG_NUM_FOC2                                   0x280010
+/* [ST 24] Statistics register. The number of messages that were sent to
+   FOC3 */
+#define XSEM_REG_MSG_NUM_FOC3                                   0x280014
+/* [RW 1] Disables input messages from the passive buffer May be updated
+   during run_time by the microcode */
+#define XSEM_REG_PAS_DISABLE                                    0x28024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define XSEM_REG_PASSIVE_BUFFER                                 0x282000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define XSEM_REG_PRAM                                           0x2c0000
+/* [R 16] Valid sleeping threads indication have bit per thread */
+#define XSEM_REG_SLEEP_THREADS_VALID                            0x28026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define XSEM_REG_SLOW_EXT_STORE_EMPTY                           0x2802a0
+/* [RW 16] List of free threads . There is a bit per thread. */
+#define XSEM_REG_THREADS_LIST                                   0x2802e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define XSEM_REG_TS_0_AS                                        0x280038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define XSEM_REG_TS_10_AS                                       0x280060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define XSEM_REG_TS_11_AS                                       0x280064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define XSEM_REG_TS_12_AS                                       0x280068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define XSEM_REG_TS_13_AS                                       0x28006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define XSEM_REG_TS_14_AS                                       0x280070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define XSEM_REG_TS_15_AS                                       0x280074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define XSEM_REG_TS_16_AS                                       0x280078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define XSEM_REG_TS_17_AS                                       0x28007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define XSEM_REG_TS_18_AS                                       0x280080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define XSEM_REG_TS_1_AS                                        0x28003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define XSEM_REG_TS_2_AS                                        0x280040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define XSEM_REG_TS_3_AS                                        0x280044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define XSEM_REG_TS_4_AS                                        0x280048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define XSEM_REG_TS_5_AS                                        0x28004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define XSEM_REG_TS_6_AS                                        0x280050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define XSEM_REG_TS_7_AS                                        0x280054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define XSEM_REG_TS_8_AS                                        0x280058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define XSEM_REG_TS_9_AS                                        0x28005c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define XSEM_REG_XSEM_INT_MASK_0                                0x280110
+#define XSEM_REG_XSEM_INT_MASK_1                                0x280120
+/* [R 32] Interrupt register #0 read */
+#define XSEM_REG_XSEM_INT_STS_0                                 0x280104
+#define XSEM_REG_XSEM_INT_STS_1                                 0x280114
+/* [RW 32] Parity mask register #0 read/write */
+#define XSEM_REG_XSEM_PRTY_MASK_0                               0x280130
+#define XSEM_REG_XSEM_PRTY_MASK_1                               0x280140
+/* [R 32] Parity register #0 read */
+#define XSEM_REG_XSEM_PRTY_STS_0                                0x280124
+#define XSEM_REG_XSEM_PRTY_STS_1                                0x280134
+#define MCPR_NVM_ACCESS_ENABLE_EN                               (1L<<0)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN                            (1L<<1)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE                            (0xffffffL<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE                                (0x7L<<0)
+#define MCPR_NVM_COMMAND_DOIT                                   (1L<<4)
+#define MCPR_NVM_COMMAND_DONE                                   (1L<<3)
+#define MCPR_NVM_COMMAND_FIRST                                  (1L<<7)
+#define MCPR_NVM_COMMAND_LAST                                   (1L<<8)
+#define MCPR_NVM_COMMAND_WR                                     (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_ARB1                                (1L<<9)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1                            (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1                            (1L<<1)
+#define BIGMAC_REGISTER_BMAC_CONTROL                            (0x00<<3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL                       (0x01<<3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE                            (0x05<<3)
+#define BIGMAC_REGISTER_RX_CONTROL                              (0x21<<3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS                        (0x46<<3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE                             (0x23<<3)
+#define BIGMAC_REGISTER_RX_STAT_GR64                            (0x26<<3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ                           (0x42<<3)
+#define BIGMAC_REGISTER_TX_CONTROL                              (0x07<<3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE                             (0x09<<3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD                      (0x0A<<3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR                          (0x08<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT                           (0x20<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT                           (0x0C<<3)
+#define BIGMAC2_REGISTER_BMAC_CONTROL                           (0x00<<3)
+#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL                      (0x01<<3)
+#define BIGMAC2_REGISTER_PFC_CONTROL                            (0x06<<3)
+#define BIGMAC2_REGISTER_RX_CONTROL                             (0x3A<<3)
+#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS                       (0x62<<3)
+#define BIGMAC2_REGISTER_RX_MAX_SIZE                            (0x3C<<3)
+#define BIGMAC2_REGISTER_TX_CONTROL                             (0x1C<<3)
+#define BIGMAC2_REGISTER_TX_MAX_SIZE                            (0x1E<<3)
+#define BIGMAC2_REGISTER_TX_SOURCE_ADDR                         (0x1D<<3)
+#define EMAC_LED_1000MB_OVERRIDE                                (1L<<1)
+#define EMAC_LED_100MB_OVERRIDE                                 (1L<<2)
+#define EMAC_LED_10MB_OVERRIDE                                  (1L<<3)
+#define EMAC_LED_2500MB_OVERRIDE                                (1L<<12)
+#define EMAC_LED_OVERRIDE                                       (1L<<0)
+#define EMAC_LED_TRAFFIC                                        (1L<<6)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS                          (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45                          (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45                         (1L<<26)
+#define EMAC_MDIO_COMM_DATA                                     (0xffffL<<0)
+#define EMAC_MDIO_COMM_START_BUSY                               (1L<<29)
+#define EMAC_MDIO_MODE_AUTO_POLL                                (1L<<4)
+#define EMAC_MDIO_MODE_CLAUSE_45                                (1<<31)
+#define EMAC_MDIO_MODE_CLOCK_CNT                                (0x3fL<<16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT                       16
+#define EMAC_MODE_25G_MODE                                      (1L<<5)
+#define EMAC_MODE_HALF_DUPLEX                                   (1L<<1)
+#define EMAC_MODE_PORT_GMII                                     (2L<<2)
+#define EMAC_MODE_PORT_MII                                      (1L<<2)
+#define EMAC_MODE_PORT_MII_10M                                  (3L<<2)
+#define EMAC_MODE_RESET                                         (1L<<0)
+#define EMAC_REG_EMAC_LED                                       0xc
+#define EMAC_REG_EMAC_MAC_MATCH                                 0x10
+#define EMAC_REG_EMAC_MDIO_COMM                                 0xac
+#define EMAC_REG_EMAC_MDIO_MODE                                 0xb4
+#define EMAC_REG_EMAC_MODE                                      0x0
+#define EMAC_REG_EMAC_RX_MODE                                   0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE                               0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC                                0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_28                             0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT                          23
+#define EMAC_REG_EMAC_TX_MODE                                   0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC                                0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT                          22
+#define EMAC_RX_MODE_FLOW_EN                                    (1L<<2)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG                              (1L<<10)
+#define EMAC_RX_MODE_PROMISCUOUS                                (1L<<8)
+#define EMAC_RX_MODE_RESET                                      (1L<<0)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA                              (1<<31)
+#define EMAC_TX_MODE_EXT_PAUSE_EN                               (1L<<3)
+#define EMAC_TX_MODE_FLOW_EN                                    (1L<<4)
+#define EMAC_TX_MODE_RESET                                      (1L<<0)
+#define MISC_REGISTERS_GPIO_0                                   0
+#define MISC_REGISTERS_GPIO_1                                   1
+#define MISC_REGISTERS_GPIO_2                                   2
+#define MISC_REGISTERS_GPIO_3                                   3
+#define MISC_REGISTERS_GPIO_CLR_POS                             16
+#define MISC_REGISTERS_GPIO_FLOAT                               (0xffL<<24)
+#define MISC_REGISTERS_GPIO_FLOAT_POS                           24
+#define MISC_REGISTERS_GPIO_HIGH                                1
+#define MISC_REGISTERS_GPIO_INPUT_HI_Z                          2
+#define MISC_REGISTERS_GPIO_INT_CLR_POS                         24
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR                      0
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET                      1
+#define MISC_REGISTERS_GPIO_INT_SET_POS                         16
+#define MISC_REGISTERS_GPIO_LOW                                 0
+#define MISC_REGISTERS_GPIO_OUTPUT_HIGH                         1
+#define MISC_REGISTERS_GPIO_OUTPUT_LOW                          0
+#define MISC_REGISTERS_GPIO_PORT_SHIFT                          4
+#define MISC_REGISTERS_GPIO_SET_POS                             8
+#define MISC_REGISTERS_RESET_REG_1_CLEAR                        0x588
+#define MISC_REGISTERS_RESET_REG_1_RST_NIG                      (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_1_SET                          0x584
+#define MISC_REGISTERS_RESET_REG_2_CLEAR                        0x598
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0                    (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE          (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_SET                          0x594
+#define MISC_REGISTERS_RESET_REG_3_CLEAR                        0x5a8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ    (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN  (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW  (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ      (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN    (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD  (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW   (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_SET                          0x5a4
+#define MISC_REGISTERS_SPIO_4                                   4
+#define MISC_REGISTERS_SPIO_5                                   5
+#define MISC_REGISTERS_SPIO_7                                   7
+#define MISC_REGISTERS_SPIO_CLR_POS                             16
+#define MISC_REGISTERS_SPIO_FLOAT                               (0xffL<<24)
+#define MISC_REGISTERS_SPIO_FLOAT_POS                           24
+#define MISC_REGISTERS_SPIO_INPUT_HI_Z                          2
+#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS                     16
+#define MISC_REGISTERS_SPIO_OUTPUT_HIGH                         1
+#define MISC_REGISTERS_SPIO_OUTPUT_LOW                          0
+#define MISC_REGISTERS_SPIO_SET_POS                             8
+#define HW_LOCK_MAX_RESOURCE_VALUE                              31
+#define HW_LOCK_RESOURCE_GPIO                                   1
+#define HW_LOCK_RESOURCE_MDIO                                   0
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK                         3
+#define HW_LOCK_RESOURCE_SPIO                                   2
+#define HW_LOCK_RESOURCE_UNDI                                   5
+#define PRS_FLAG_OVERETH_IPV4                                   1
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR                (1UL<<18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT                (1UL<<31)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT                (1UL<<9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR                (1UL<<8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT                (1UL<<7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR                (1UL<<6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT               (1UL<<29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR               (1UL<<28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT              (1UL<<1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR              (1UL<<0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR              (1UL<<18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT               (1UL<<11)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT          (1UL<<13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR          (1UL<<12)
+#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0                (1UL<<5)
+#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1                (1UL<<9)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR                (1UL<<12)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT               (1UL<<15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR               (1UL<<14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR             (1UL<<20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR           (1UL<<0)
+#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT                (1UL<<31)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT                (1UL<<3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR                (1UL<<2)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT   (1UL<<5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR   (1UL<<4)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT                 (1UL<<3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR                 (1UL<<2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR           (1UL<<22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5                           (1UL<<15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT                (1UL<<27)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT             (1UL<<5)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT               (1UL<<25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR               (1UL<<24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT              (1UL<<29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR              (1UL<<28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT                (1UL<<23)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT                (1UL<<27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR                (1UL<<26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT               (1UL<<21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR               (1UL<<20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT              (1UL<<25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR              (1UL<<24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR       (1UL<<16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT                (1UL<<9)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT               (1UL<<7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR               (1UL<<6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT              (1UL<<11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR              (1UL<<10)
+#define RESERVED_GENERAL_ATTENTION_BIT_0       0
+
+#define EVEREST_GEN_ATTN_IN_USE_MASK           0x3ffe0
+#define EVEREST_LATCHED_ATTN_IN_USE_MASK       0xffe00000
+
+#define RESERVED_GENERAL_ATTENTION_BIT_6       6
+#define RESERVED_GENERAL_ATTENTION_BIT_7       7
+#define RESERVED_GENERAL_ATTENTION_BIT_8       8
+#define RESERVED_GENERAL_ATTENTION_BIT_9       9
+#define RESERVED_GENERAL_ATTENTION_BIT_10      10
+#define RESERVED_GENERAL_ATTENTION_BIT_11      11
+#define RESERVED_GENERAL_ATTENTION_BIT_12      12
+#define RESERVED_GENERAL_ATTENTION_BIT_13      13
+#define RESERVED_GENERAL_ATTENTION_BIT_14      14
+#define RESERVED_GENERAL_ATTENTION_BIT_15      15
+#define RESERVED_GENERAL_ATTENTION_BIT_16      16
+#define RESERVED_GENERAL_ATTENTION_BIT_17      17
+#define RESERVED_GENERAL_ATTENTION_BIT_18      18
+#define RESERVED_GENERAL_ATTENTION_BIT_19      19
+#define RESERVED_GENERAL_ATTENTION_BIT_20      20
+#define RESERVED_GENERAL_ATTENTION_BIT_21      21
+
+/* storm asserts attention bits */
+#define TSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_7
+#define USTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_8
+#define CSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_9
+#define XSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_10
+
+/* mcp error attention bit */
+#define MCP_FATAL_ASSERT_ATTENTION_BIT       RESERVED_GENERAL_ATTENTION_BIT_11
+
+/*E1H NIG status sync attention mapped to group 4-7*/
+#define LINK_SYNC_ATTENTION_BIT_FUNC_0     RESERVED_GENERAL_ATTENTION_BIT_12
+#define LINK_SYNC_ATTENTION_BIT_FUNC_1     RESERVED_GENERAL_ATTENTION_BIT_13
+#define LINK_SYNC_ATTENTION_BIT_FUNC_2     RESERVED_GENERAL_ATTENTION_BIT_14
+#define LINK_SYNC_ATTENTION_BIT_FUNC_3     RESERVED_GENERAL_ATTENTION_BIT_15
+#define LINK_SYNC_ATTENTION_BIT_FUNC_4     RESERVED_GENERAL_ATTENTION_BIT_16
+#define LINK_SYNC_ATTENTION_BIT_FUNC_5     RESERVED_GENERAL_ATTENTION_BIT_17
+#define LINK_SYNC_ATTENTION_BIT_FUNC_6     RESERVED_GENERAL_ATTENTION_BIT_18
+#define LINK_SYNC_ATTENTION_BIT_FUNC_7     RESERVED_GENERAL_ATTENTION_BIT_19
+
+
+#define LATCHED_ATTN_RBCR                      23
+#define LATCHED_ATTN_RBCT                      24
+#define LATCHED_ATTN_RBCN                      25
+#define LATCHED_ATTN_RBCU                      26
+#define LATCHED_ATTN_RBCP                      27
+#define LATCHED_ATTN_TIMEOUT_GRC               28
+#define LATCHED_ATTN_RSVD_GRC                  29
+#define LATCHED_ATTN_ROM_PARITY_MCP            30
+#define LATCHED_ATTN_UM_RX_PARITY_MCP          31
+#define LATCHED_ATTN_UM_TX_PARITY_MCP          32
+#define LATCHED_ATTN_SCPAD_PARITY_MCP          33
+
+#define GENERAL_ATTEN_WORD(atten_name)        ((94 + atten_name) / 32)
+#define GENERAL_ATTEN_OFFSET(atten_name)\
+       (1UL << ((94 + atten_name) % 32))
+/*
+ * This file defines GRC base address for every block.
+ * This file is included by chipsim, asm microcode and cpp microcode.
+ * These values are used in Design.xml on regBase attribute
+ * Use the base with the generated offsets of specific registers.
+ */
+
+#define GRCBASE_PXPCS          0x000000
+#define GRCBASE_PCICONFIG      0x002000
+#define GRCBASE_PCIREG         0x002400
+#define GRCBASE_EMAC0          0x008000
+#define GRCBASE_EMAC1          0x008400
+#define GRCBASE_DBU            0x008800
+#define GRCBASE_MISC           0x00A000
+#define GRCBASE_DBG            0x00C000
+#define GRCBASE_NIG            0x010000
+#define GRCBASE_XCM            0x020000
+#define GRCBASE_PRS            0x040000
+#define GRCBASE_SRCH           0x040400
+#define GRCBASE_TSDM           0x042000
+#define GRCBASE_TCM            0x050000
+#define GRCBASE_BRB1           0x060000
+#define GRCBASE_MCP            0x080000
+#define GRCBASE_UPB            0x0C1000
+#define GRCBASE_CSDM           0x0C2000
+#define GRCBASE_USDM           0x0C4000
+#define GRCBASE_CCM            0x0D0000
+#define GRCBASE_UCM            0x0E0000
+#define GRCBASE_CDU            0x101000
+#define GRCBASE_DMAE           0x102000
+#define GRCBASE_PXP            0x103000
+#define GRCBASE_CFC            0x104000
+#define GRCBASE_HC             0x108000
+#define GRCBASE_PXP2           0x120000
+#define GRCBASE_PBF            0x140000
+#define GRCBASE_XPB            0x161000
+#define GRCBASE_TIMERS         0x164000
+#define GRCBASE_XSDM           0x166000
+#define GRCBASE_QM             0x168000
+#define GRCBASE_DQ             0x170000
+#define GRCBASE_TSEM           0x180000
+#define GRCBASE_CSEM           0x200000
+#define GRCBASE_XSEM           0x280000
+#define GRCBASE_USEM           0x300000
+#define GRCBASE_MISC_AEU       GRCBASE_MISC
+
+
+/* offset of configuration space in the pci core register */
+#define PCICFG_OFFSET                                  0x2000
+#define PCICFG_VENDOR_ID_OFFSET                        0x00
+#define PCICFG_DEVICE_ID_OFFSET                        0x02
+#define PCICFG_COMMAND_OFFSET                          0x04
+#define PCICFG_COMMAND_IO_SPACE                (1<<0)
+#define PCICFG_COMMAND_MEM_SPACE               (1<<1)
+#define PCICFG_COMMAND_BUS_MASTER              (1<<2)
+#define PCICFG_COMMAND_SPECIAL_CYCLES          (1<<3)
+#define PCICFG_COMMAND_MWI_CYCLES              (1<<4)
+#define PCICFG_COMMAND_VGA_SNOOP               (1<<5)
+#define PCICFG_COMMAND_PERR_ENA                (1<<6)
+#define PCICFG_COMMAND_STEPPING                (1<<7)
+#define PCICFG_COMMAND_SERR_ENA                (1<<8)
+#define PCICFG_COMMAND_FAST_B2B                (1<<9)
+#define PCICFG_COMMAND_INT_DISABLE             (1<<10)
+#define PCICFG_COMMAND_RESERVED                (0x1f<<11)
+#define PCICFG_STATUS_OFFSET                           0x06
+#define PCICFG_REVESION_ID_OFFSET                      0x08
+#define PCICFG_CACHE_LINE_SIZE                         0x0c
+#define PCICFG_LATENCY_TIMER                           0x0d
+#define PCICFG_BAR_1_LOW                               0x10
+#define PCICFG_BAR_1_HIGH                              0x14
+#define PCICFG_BAR_2_LOW                               0x18
+#define PCICFG_BAR_2_HIGH                              0x1c
+#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET              0x2c
+#define PCICFG_SUBSYSTEM_ID_OFFSET                     0x2e
+#define PCICFG_INT_LINE                                0x3c
+#define PCICFG_INT_PIN                                 0x3d
+#define PCICFG_PM_CAPABILITY                           0x48
+#define PCICFG_PM_CAPABILITY_VERSION           (0x3<<16)
+#define PCICFG_PM_CAPABILITY_CLOCK             (1<<19)
+#define PCICFG_PM_CAPABILITY_RESERVED          (1<<20)
+#define PCICFG_PM_CAPABILITY_DSI               (1<<21)
+#define PCICFG_PM_CAPABILITY_AUX_CURRENT       (0x7<<22)
+#define PCICFG_PM_CAPABILITY_D1_SUPPORT        (1<<25)
+#define PCICFG_PM_CAPABILITY_D2_SUPPORT        (1<<26)
+#define PCICFG_PM_CAPABILITY_PME_IN_D0         (1<<27)
+#define PCICFG_PM_CAPABILITY_PME_IN_D1         (1<<28)
+#define PCICFG_PM_CAPABILITY_PME_IN_D2         (1<<29)
+#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT     (1<<30)
+#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD    (1<<31)
+#define PCICFG_PM_CSR_OFFSET                           0x4c
+#define PCICFG_PM_CSR_STATE                    (0x3<<0)
+#define PCICFG_PM_CSR_PME_ENABLE               (1<<8)
+#define PCICFG_PM_CSR_PME_STATUS               (1<<15)
+#define PCICFG_MSI_CAP_ID_OFFSET                       0x58
+#define PCICFG_MSI_CONTROL_ENABLE              (0x1<<16)
+#define PCICFG_MSI_CONTROL_MCAP                (0x7<<17)
+#define PCICFG_MSI_CONTROL_MENA                (0x7<<20)
+#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP     (0x1<<23)
+#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE  (0x1<<24)
+#define PCICFG_GRC_ADDRESS                             0x78
+#define PCICFG_GRC_DATA                                0x80
+#define PCICFG_MSIX_CAP_ID_OFFSET                      0xa0
+#define PCICFG_MSIX_CONTROL_TABLE_SIZE         (0x7ff<<16)
+#define PCICFG_MSIX_CONTROL_RESERVED           (0x7<<27)
+#define PCICFG_MSIX_CONTROL_FUNC_MASK          (0x1<<30)
+#define PCICFG_MSIX_CONTROL_MSIX_ENABLE        (0x1<<31)
+
+#define PCICFG_DEVICE_CONTROL                          0xb4
+#define PCICFG_DEVICE_STATUS                           0xb6
+#define PCICFG_DEVICE_STATUS_CORR_ERR_DET      (1<<0)
+#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
+#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET     (1<<2)
+#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET     (1<<3)
+#define PCICFG_DEVICE_STATUS_AUX_PWR_DET       (1<<4)
+#define PCICFG_DEVICE_STATUS_NO_PEND           (1<<5)
+#define PCICFG_LINK_CONTROL                            0xbc
+
+
+#define BAR_USTRORM_INTMEM                             0x400000
+#define BAR_CSTRORM_INTMEM                             0x410000
+#define BAR_XSTRORM_INTMEM                             0x420000
+#define BAR_TSTRORM_INTMEM                             0x430000
+
+/* for accessing the IGU in case of status block ACK */
+#define BAR_IGU_INTMEM                                 0x440000
+
+#define BAR_DOORBELL_OFFSET                            0x800000
+
+#define BAR_ME_REGISTER                                0x450000
+#define ME_REG_PF_NUM                  (7L<<0) /* Relative PF Num */
+#define ME_REG_PF_NUM_SHIFT            0
+#define ME_REG_ABS_PF_NUM              (7L<<16) /* Absolute PF Num */
+#define ME_REG_ABS_PF_NUM_SHIFT        16
+
+
+/* config_2 offset */
+#define GRC_CONFIG_2_SIZE_REG                          0x408
+#define PCI_CONFIG_2_BAR1_SIZE                 (0xfL<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_DISABLED        (0L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64K             (1L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128K            (2L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256K            (3L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512K            (4L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1M              (5L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_2M              (6L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_4M              (7L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_8M              (8L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_16M             (9L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_32M             (10L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64M             (11L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128M            (12L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256M            (13L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512M            (14L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1G              (15L<<0)
+#define PCI_CONFIG_2_BAR1_64ENA                (1L<<4)
+#define PCI_CONFIG_2_EXP_ROM_RETRY             (1L<<5)
+#define PCI_CONFIG_2_CFG_CYCLE_RETRY           (1L<<6)
+#define PCI_CONFIG_2_FIRST_CFG_DONE            (1L<<7)
+#define PCI_CONFIG_2_EXP_ROM_SIZE              (0xffL<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED     (0L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2K           (1L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4K           (2L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8K           (3L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16K          (4L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32K          (5L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_64K          (6L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_128K         (7L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_256K         (8L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_512K         (9L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_1M           (10L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2M           (11L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4M           (12L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8M           (13L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16M          (14L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32M          (15L<<8)
+#define PCI_CONFIG_2_BAR_PREFETCH              (1L<<16)
+#define PCI_CONFIG_2_RESERVED0                 (0x7fffL<<17)
+
+/* config_3 offset */
+#define GRC_CONFIG_3_SIZE_REG                          0x40c
+#define PCI_CONFIG_3_STICKY_BYTE                       (0xffL<<0)
+#define PCI_CONFIG_3_FORCE_PME                 (1L<<24)
+#define PCI_CONFIG_3_PME_STATUS                (1L<<25)
+#define PCI_CONFIG_3_PME_ENABLE                (1L<<26)
+#define PCI_CONFIG_3_PM_STATE                  (0x3L<<27)
+#define PCI_CONFIG_3_VAUX_PRESET                       (1L<<30)
+#define PCI_CONFIG_3_PCI_POWER                 (1L<<31)
+
+#define GRC_BAR2_CONFIG                                0x4e0
+#define PCI_CONFIG_2_BAR2_SIZE                 (0xfL<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_DISABLED        (0L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64K             (1L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128K            (2L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256K            (3L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512K            (4L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1M              (5L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_2M              (6L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_4M              (7L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_8M              (8L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_16M             (9L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_32M             (10L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64M             (11L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128M            (12L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256M            (13L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512M            (14L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1G              (15L<<0)
+#define PCI_CONFIG_2_BAR2_64ENA                (1L<<4)
+
+#define PCI_PM_DATA_A                                  0x410
+#define PCI_PM_DATA_B                                  0x414
+#define PCI_ID_VAL1                                    0x434
+#define PCI_ID_VAL2                                    0x438
+
+
+#define MDIO_REG_BANK_CL73_IEEEB0                      0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL               0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN    0x0200
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN         0x1000
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST      0x8000
+
+#define MDIO_REG_BANK_CL73_IEEEB1                      0x10
+#define MDIO_CL73_IEEEB1_AN_ADV2                               0x01
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M            0x0000
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX         0x0020
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4          0x0040
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR           0x0080
+
+#define MDIO_REG_BANK_RX0                              0x80b0
+#define MDIO_RX0_RX_EQ_BOOST                           0x1c
+#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK       0x7
+#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL               0x10
+
+#define MDIO_REG_BANK_RX1                              0x80c0
+#define MDIO_RX1_RX_EQ_BOOST                           0x1c
+#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK       0x7
+#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL               0x10
+
+#define MDIO_REG_BANK_RX2                              0x80d0
+#define MDIO_RX2_RX_EQ_BOOST                           0x1c
+#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK       0x7
+#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL               0x10
+
+#define MDIO_REG_BANK_RX3                              0x80e0
+#define MDIO_RX3_RX_EQ_BOOST                           0x1c
+#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK       0x7
+#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL               0x10
+
+#define MDIO_REG_BANK_RX_ALL                           0x80f0
+#define MDIO_RX_ALL_RX_EQ_BOOST                        0x1c
+#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK    0x7
+#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL    0x10
+
+#define MDIO_REG_BANK_TX0                              0x8060
+#define MDIO_TX0_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
+#define MDIO_REG_BANK_TX1                              0x8070
+#define MDIO_TX1_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
+#define MDIO_REG_BANK_TX2                              0x8080
+#define MDIO_TX2_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
+#define MDIO_REG_BANK_TX3                              0x8090
+#define MDIO_TX3_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
+#define MDIO_REG_BANK_XGXS_BLOCK0                      0x8000
+#define MDIO_BLOCK0_XGXS_CONTROL                       0x10
+
+#define MDIO_REG_BANK_XGXS_BLOCK1                      0x8010
+#define MDIO_BLOCK1_LANE_CTRL0                         0x15
+#define MDIO_BLOCK1_LANE_CTRL1                         0x16
+#define MDIO_BLOCK1_LANE_CTRL2                         0x17
+#define MDIO_BLOCK1_LANE_PRBS                          0x19
+
+#define MDIO_REG_BANK_XGXS_BLOCK2                      0x8100
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP                    0x10
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE             0x8000
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE       0x4000
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP            0x11
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE             0x8000
+#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G      0x14
+#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS     0x0001
+#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS   0x0010
+#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE        0x15
+
+#define MDIO_REG_BANK_GP_STATUS                        0x8120
+#define MDIO_GP_STATUS_TOP_AN_STATUS1                          0x1B
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE    0x0001
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE    0x0002
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS              0x0004
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS            0x0008
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE    0x0010
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE      0x0020
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE   0x0040
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE   0x0080
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK        0x3f00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M         0x0000
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M        0x0100
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G          0x0200
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G        0x0300
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G          0x0400
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G          0x0500
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG     0x0600
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4     0x0700
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG     0x0800
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G       0x0900
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G         0x0A00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G         0x0B00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G         0x0C00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX       0x0D00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4     0x0E00
+
+
+#define MDIO_REG_BANK_10G_PARALLEL_DETECT              0x8130
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL           0x11
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN      0x1
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK              0x13
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT          (0xb71<<1)
+
+#define MDIO_REG_BANK_SERDES_DIGITAL                   0x8300
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1                   0x10
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE                0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF                    0x0002
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN          0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT      0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET                   0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE                 0x0020
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2                   0x11
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN                 0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR                0x0040
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1                    0x14
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX                     0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK                 0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT                3
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G                 0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G                   0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M                 0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M                  0x0000
+#define MDIO_SERDES_DIGITAL_MISC1                              0x18
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK                      0xE000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M                       0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M                      0x2000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M                      0x4000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M                   0x6000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M                    0x8000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL                      0x0010
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK                     0x000f
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G                     0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G                       0x0001
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G                       0x0002
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG                  0x0003
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4                  0x0004
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G                      0x0005
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G                    0x0006
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G                      0x0007
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G                      0x0008
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G                      0x0009
+
+#define MDIO_REG_BANK_OVER_1G                          0x8320
+#define MDIO_OVER_1G_DIGCTL_3_4                                0x14
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK                             0xffe0
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT                            5
+#define MDIO_OVER_1G_UP1                                       0x19
+#define MDIO_OVER_1G_UP1_2_5G                                          0x0001
+#define MDIO_OVER_1G_UP1_5G                                            0x0002
+#define MDIO_OVER_1G_UP1_6G                                            0x0004
+#define MDIO_OVER_1G_UP1_10G                                           0x0010
+#define MDIO_OVER_1G_UP1_10GH                                          0x0008
+#define MDIO_OVER_1G_UP1_12G                                           0x0020
+#define MDIO_OVER_1G_UP1_12_5G                                         0x0040
+#define MDIO_OVER_1G_UP1_13G                                           0x0080
+#define MDIO_OVER_1G_UP1_15G                                           0x0100
+#define MDIO_OVER_1G_UP1_16G                                           0x0200
+#define MDIO_OVER_1G_UP2                                       0x1A
+#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK                               0x0007
+#define MDIO_OVER_1G_UP2_IDRIVER_MASK                                  0x0038
+#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK                              0x03C0
+#define MDIO_OVER_1G_UP3                                       0x1B
+#define MDIO_OVER_1G_UP3_HIGIG2                                        0x0001
+#define MDIO_OVER_1G_LP_UP1                                    0x1C
+#define MDIO_OVER_1G_LP_UP2                                    0x1D
+#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK                        0x03ff
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK                           0x0780
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT                          7
+#define MDIO_OVER_1G_LP_UP3                                            0x1E
+
+#define MDIO_REG_BANK_BAM_NEXT_PAGE                    0x8350
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL                  0x10
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE                 0x0001
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN                 0x0002
+
+#define MDIO_REG_BANK_CL73_USERB0              0x8370
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1                        0x12
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN                         0x8000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN            0x4000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN             0x2000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3                        0x14
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR                0x0001
+
+#define MDIO_REG_BANK_AER_BLOCK                0xFFD0
+#define MDIO_AER_BLOCK_AER_REG                                 0x1E
+
+#define MDIO_REG_BANK_COMBO_IEEE0              0xFFE0
+#define MDIO_COMBO_IEEE0_MII_CONTROL                           0x10
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK                  0x2040
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10                    0x0000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100                   0x2000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000                  0x0040
+#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX                        0x0100
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN                         0x0200
+#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN                              0x1000
+#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK                           0x4000
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESET                              0x8000
+#define MDIO_COMBO_IEEE0_MII_STATUS                            0x11
+#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS                          0x0004
+#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE                   0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV                          0x14
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX                      0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX                      0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK                       0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE                       0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC                  0x0080
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC                 0x0100
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH                       0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE                        0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1        0x15
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE      0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK            0x4000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK     0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE     0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH     0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP   0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP   0x0020
+/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
+bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
+Theotherbitsarereservedandshouldbezero*/
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE     0x0001
+
+
+#define MDIO_PMA_DEVAD                 0x1
+/*ieee*/
+#define MDIO_PMA_REG_CTRL              0x0
+#define MDIO_PMA_REG_STATUS            0x1
+#define MDIO_PMA_REG_10G_CTRL2         0x7
+#define MDIO_PMA_REG_RX_SD             0xa
+/*bcm*/
+#define MDIO_PMA_REG_BCM_CTRL          0x0096
+#define MDIO_PMA_REG_FEC_CTRL          0x00ab
+#define MDIO_PMA_REG_RX_ALARM_CTRL     0x9000
+#define MDIO_PMA_REG_LASI_CTRL         0x9002
+#define MDIO_PMA_REG_RX_ALARM          0x9003
+#define MDIO_PMA_REG_TX_ALARM          0x9004
+#define MDIO_PMA_REG_LASI_STATUS       0x9005
+#define MDIO_PMA_REG_PHY_IDENTIFIER    0xc800
+#define MDIO_PMA_REG_DIGITAL_CTRL      0xc808
+#define MDIO_PMA_REG_DIGITAL_STATUS    0xc809
+#define MDIO_PMA_REG_TX_POWER_DOWN     0xca02
+#define MDIO_PMA_REG_CMU_PLL_BYPASS    0xca09
+#define MDIO_PMA_REG_MISC_CTRL         0xca0a
+#define MDIO_PMA_REG_GEN_CTRL          0xca10
+#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP    0x0188
+#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET          0x018a
+#define MDIO_PMA_REG_M8051_MSGIN_REG   0xca12
+#define MDIO_PMA_REG_M8051_MSGOUT_REG  0xca13
+#define MDIO_PMA_REG_ROM_VER1          0xca19
+#define MDIO_PMA_REG_ROM_VER2          0xca1a
+#define MDIO_PMA_REG_EDC_FFE_MAIN      0xca1b
+#define MDIO_PMA_REG_PLL_BANDWIDTH     0xca1d
+#define MDIO_PMA_REG_PLL_CTRL          0xca1e
+#define MDIO_PMA_REG_MISC_CTRL0        0xca23
+#define MDIO_PMA_REG_LRM_MODE          0xca3f
+#define MDIO_PMA_REG_CDR_BANDWIDTH     0xca46
+#define MDIO_PMA_REG_MISC_CTRL1        0xca85
+
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL         0x8000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK     0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE          0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE      0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS   0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED        0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT     0x8002
+#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR     0x8003
+#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF    0xc820
+#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8726_TX_CTRL1             0xca01
+#define MDIO_PMA_REG_8726_TX_CTRL2             0xca05
+
+#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR  0x8005
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF    0x8007
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8727_MISC_CTRL            0x8309
+#define MDIO_PMA_REG_8727_TX_CTRL1             0xca02
+#define MDIO_PMA_REG_8727_TX_CTRL2             0xca05
+#define MDIO_PMA_REG_8727_PCS_OPT_CTRL         0xc808
+#define MDIO_PMA_REG_8727_GPIO_CTRL            0xc80e
+
+#define MDIO_PMA_REG_8073_CHIP_REV                     0xc801
+#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS            0xc820
+#define MDIO_PMA_REG_8073_XAUI_WA                      0xc841
+
+#define MDIO_PMA_REG_7101_RESET        0xc000
+#define MDIO_PMA_REG_7107_LED_CNTL     0xc007
+#define MDIO_PMA_REG_7101_VER1         0xc026
+#define MDIO_PMA_REG_7101_VER2         0xc027
+
+#define MDIO_PMA_REG_8481_PMD_SIGNAL   0xa811
+#define MDIO_PMA_REG_8481_SIGNAL_MASK  0xa835
+#define MDIO_PMA_REG_8481_LINK_SIGNAL  0xa83b
+
+
+#define MDIO_WIS_DEVAD                 0x2
+/*bcm*/
+#define MDIO_WIS_REG_LASI_CNTL         0x9002
+#define MDIO_WIS_REG_LASI_STATUS       0x9005
+
+#define MDIO_PCS_DEVAD                 0x3
+#define MDIO_PCS_REG_STATUS            0x0020
+#define MDIO_PCS_REG_LASI_STATUS       0x9005
+#define MDIO_PCS_REG_7101_DSP_ACCESS   0xD000
+#define MDIO_PCS_REG_7101_SPI_MUX      0xD008
+#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
+#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD  (0xC7)
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
+#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
+
+
+#define MDIO_XS_DEVAD                  0x4
+#define MDIO_XS_PLL_SEQUENCER          0x8000
+#define MDIO_XS_SFX7101_XGXS_TEST1     0xc00a
+
+#define MDIO_XS_8706_REG_BANK_RX0      0x80bc
+#define MDIO_XS_8706_REG_BANK_RX1      0x80cc
+#define MDIO_XS_8706_REG_BANK_RX2      0x80dc
+#define MDIO_XS_8706_REG_BANK_RX3      0x80ec
+#define MDIO_XS_8706_REG_BANK_RXA      0x80fc
+
+#define MDIO_AN_DEVAD                  0x7
+/*ieee*/
+#define MDIO_AN_REG_CTRL               0x0000
+#define MDIO_AN_REG_STATUS             0x0001
+#define MDIO_AN_REG_STATUS_AN_COMPLETE         0x0020
+#define MDIO_AN_REG_ADV_PAUSE          0x0010
+#define MDIO_AN_REG_ADV_PAUSE_PAUSE            0x0400
+#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC       0x0800
+#define MDIO_AN_REG_ADV_PAUSE_BOTH             0x0C00
+#define MDIO_AN_REG_ADV_PAUSE_MASK             0x0C00
+#define MDIO_AN_REG_ADV                0x0011
+#define MDIO_AN_REG_ADV2               0x0012
+#define MDIO_AN_REG_LP_AUTO_NEG        0x0013
+#define MDIO_AN_REG_MASTER_STATUS      0x0021
+/*bcm*/
+#define MDIO_AN_REG_LINK_STATUS        0x8304
+#define MDIO_AN_REG_CL37_CL73          0x8370
+#define MDIO_AN_REG_CL37_AN            0xffe0
+#define MDIO_AN_REG_CL37_FC_LD         0xffe4
+#define MDIO_AN_REG_CL37_FC_LP         0xffe5
+
+#define MDIO_AN_REG_8073_2_5G          0x8329
+
+#define MDIO_AN_REG_8481_LEGACY_MII_CTRL       0xffe0
+#define MDIO_AN_REG_8481_LEGACY_AN_ADV         0xffe4
+#define MDIO_AN_REG_8481_1000T_CTRL            0xffe9
+#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW   0xfff5
+#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS  0xfff7
+#define MDIO_AN_REG_8481_LEGACY_SHADOW         0xfffc
+
+#define IGU_FUNC_BASE                  0x0400
+
+#define IGU_ADDR_MSIX                  0x0000
+#define IGU_ADDR_INT_ACK               0x0200
+#define IGU_ADDR_PROD_UPD              0x0201
+#define IGU_ADDR_ATTN_BITS_UPD 0x0202
+#define IGU_ADDR_ATTN_BITS_SET 0x0203
+#define IGU_ADDR_ATTN_BITS_CLR 0x0204
+#define IGU_ADDR_COALESCE_NOW  0x0205
+#define IGU_ADDR_SIMD_MASK             0x0206
+#define IGU_ADDR_SIMD_NOMASK   0x0207
+#define IGU_ADDR_MSI_CTL               0x0210
+#define IGU_ADDR_MSI_ADDR_LO   0x0211
+#define IGU_ADDR_MSI_ADDR_HI   0x0212
+#define IGU_ADDR_MSI_DATA              0x0213
+
+#define IGU_INT_ENABLE                 0
+#define IGU_INT_DISABLE                1
+#define IGU_INT_NOP                            2
+#define IGU_INT_NOP2                   3
+
+#define COMMAND_REG_INT_ACK        0x0
+#define COMMAND_REG_PROD_UPD       0x4
+#define COMMAND_REG_ATTN_BITS_UPD   0x8
+#define COMMAND_REG_ATTN_BITS_SET   0xc
+#define COMMAND_REG_ATTN_BITS_CLR   0x10
+#define COMMAND_REG_COALESCE_NOW    0x14
+#define COMMAND_REG_SIMD_MASK      0x18
+#define COMMAND_REG_SIMD_NOMASK     0x1c
+
+
+#define IGU_MEM_BASE                                           0x0000
+
+#define IGU_MEM_MSIX_BASE                                      0x0000
+#define IGU_MEM_MSIX_UPPER                                     0x007f
+#define IGU_MEM_MSIX_RESERVED_UPPER                    0x01ff
+
+#define IGU_MEM_PBA_MSIX_BASE                          0x0200
+#define IGU_MEM_PBA_MSIX_UPPER                         0x0200
+
+#define IGU_CMD_BACKWARD_COMP_PROD_UPD         0x0201
+#define IGU_MEM_PBA_MSIX_RESERVED_UPPER        0x03ff
+
+#define IGU_CMD_INT_ACK_BASE                           0x0400
+#define IGU_CMD_INT_ACK_UPPER\
+       (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
+#define IGU_CMD_INT_ACK_RESERVED_UPPER         0x04ff
+
+#define IGU_CMD_E2_PROD_UPD_BASE                       0x0500
+#define IGU_CMD_E2_PROD_UPD_UPPER\
+       (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
+#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER     0x059f
+
+#define IGU_CMD_ATTN_BIT_UPD_UPPER                     0x05a0
+#define IGU_CMD_ATTN_BIT_SET_UPPER                     0x05a1
+#define IGU_CMD_ATTN_BIT_CLR_UPPER                     0x05a2
+
+#define IGU_REG_SISR_MDPC_WMASK_UPPER          0x05a3
+#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER      0x05a4
+#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER      0x05a5
+#define IGU_REG_SISR_MDPC_WOMASK_UPPER         0x05a6
+
+#define IGU_REG_RESERVED_UPPER                         0x05ff
+
+
+#define CDU_REGION_NUMBER_XCM_AG 2
+#define CDU_REGION_NUMBER_UCM_AG 4
+
+
+/**
+ * String-to-compress [31:8] = CID (all 24 bits)
+ * String-to-compress [7:4] = Region
+ * String-to-compress [3:0] = Type
+ */
+#define CDU_VALID_DATA(_cid, _region, _type)\
+       (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
+#define CDU_CRC8(_cid, _region, _type)\
+       (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
+#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
+       (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
+#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
+       (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
+#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
+
+/******************************************************************************
+ * Description:
+ *        Calculates crc 8 on a word value: polynomial 0-1-2-8
+ *        Code was translated from Verilog.
+ * Return:
+ *****************************************************************************/
+static inline u8 calc_crc8(u32 data, u8 crc)
+{
+    u8 D[32];
+    u8 NewCRC[8];
+    u8 C[8];
+    u8 crc_res;
+    u8 i;
+
+    /* split the data into 31 bits */
+    for (i = 0; i < 32; i++) {
+       D[i] = (u8)(data & 1);
+       data = data >> 1;
+    }
+
+    /* split the crc into 8 bits */
+    for (i = 0; i < 8; i++ ) {
+       C[i] = crc & 1;
+       crc = crc >> 1;
+    }
+
+    NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
+           D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
+           C[6] ^ C[7];
+    NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
+           D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
+           D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
+    NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
+           D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
+           C[0] ^ C[1] ^ C[4] ^ C[5];
+    NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
+           D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
+           C[1] ^ C[2] ^ C[5] ^ C[6];
+    NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
+           D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
+           C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
+    NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
+           D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
+           C[3] ^ C[4] ^ C[7];
+    NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
+           D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5];
+    NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
+           D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6];
+
+    crc_res = 0;
+    for (i = 0; i < 8; i++) {
+       crc_res |= (NewCRC[i] << i);
+    }
+
+    return crc_res;
+}
+
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_self_test.h linux-2.6.22-800/drivers/net/bnx2x/bnx2x_self_test.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/bnx2x_self_test.h   1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/bnx2x_self_test.h        2009-07-23 13:39:51.000000000 -0400
@@ -0,0 +1,1004 @@
+/* bnx2x_self_test.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007-2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Yitchak Gertner <gertner@broadcom.com>
+ */
+
+/* self test */
+
+static int idle_chk_errors;
+static int idle_chk_warnings;
+
+
+#define IDLE_CHK_E1                    0x1
+#define IDLE_CHK_E1H                   0x2
+
+#define IDLE_CHK_ERROR                 1
+#define IDLE_CHK_ERROR_NO_TRAFFIC      2
+#define IDLE_CHK_WARNING               3
+
+
+#define CHIP_MASK_CHK(chip_mask) \
+                       (((((chip_mask) & IDLE_CHK_E1) && is_e1) || \
+                         (((chip_mask) & IDLE_CHK_E1H) && is_e1h)) ? 1 : 0)
+
+#define CONDITION_CHK(condition, severity, fail_msg, arg_list...) \
+       do { \
+               if (condition) { \
+                       switch (severity) { \
+                       case IDLE_CHK_ERROR: \
+                               BNX2X_DBG_ERR("ERROR " fail_msg, ##arg_list); \
+                               idle_chk_errors++; \
+                               break; \
+                       case IDLE_CHK_ERROR_NO_TRAFFIC: \
+                               BNX2X_DBG_ERR("INFO " fail_msg, ##arg_list); \
+                               break; \
+                       case IDLE_CHK_WARNING: \
+                               BNX2X_DBG_ERR("WARNING " fail_msg, \
+                                             ##arg_list); \
+                               idle_chk_warnings++; \
+                               break; \
+                       } \
+               } \
+       } while (0);
+
+
+static void bnx2x_idle_chk6(struct bnx2x *bp, u32 chip_mask, u32 offset,
+                           int loop, int inc, int severity)
+{
+       int is_e1  = CHIP_IS_E1(bp);
+       int is_e1h = CHIP_IS_E1H(bp);
+       int i;
+       u32 val1, val2;
+       u32 rd_ptr, wr_ptr, rd_bank, wr_bank;
+
+       if (!CHIP_MASK_CHK(chip_mask))
+               return;
+
+       for (i = 0; i < loop; i++) {
+               val1 = REG_RD(bp, offset + i*inc);
+               val2 = REG_RD(bp, offset + i*inc + 4);
+               rd_ptr = ((val1 & 0x3FFFFFC0) >> 6);
+               wr_ptr = ((((val1 & 0xC0000000) >> 30) & 0x3) |
+                         ((val2 & 0x3FFFFF) << 2));
+               CONDITION_CHK((rd_ptr != wr_ptr), severity,
+                               "QM: PTRTBL entry %d - rd_ptr is not"
+                               " equal to wr_ptr. Values are 0x%x 0x%x\n",
+                               i, rd_ptr, wr_ptr);
+               rd_bank = ((val1 & 0x30) >> 4);
+               wr_bank = (val1 & 0x03);
+               CONDITION_CHK((rd_bank != wr_bank), severity,
+                               "QM: PTRTBL entry %d - rd_bank is not"
+                               " equal to wr_bank. Values are 0x%x 0x%x\n",
+                               i, rd_bank, wr_bank);
+       }
+}
+
+static int bnx2x_idle_chk(struct bnx2x *bp)
+{
+
+/* read one reg and check the condition */
+#define IDLE_CHK_1(chip_mask, offset, condition, severity, fail_msg) \
+       do { \
+               if (CHIP_MASK_CHK(chip_mask)) { \
+                       val = REG_RD(bp, offset); \
+                       CONDITION_CHK(condition, severity, \
+                                     fail_msg ". Value is 0x%x\n", val); \
+               } \
+       } while (0);
+
+/* loop to read one reg and check the condition */
+#define IDLE_CHK_2(chip_mask, offset, loop, inc, condition, severity, \
+                  fail_msg) \
+       do { \
+               if (CHIP_MASK_CHK(chip_mask)) \
+                       for (i = 0; i < (loop); i++) { \
+                               val = REG_RD(bp, offset + i*(inc)); \
+                               CONDITION_CHK(condition, severity, \
+                                             fail_msg ". Value is 0x%x\n", \
+                                             i, val); \
+                       } \
+       } while (0);
+
+/* read two regs and check the condition */
+#define IDLE_CHK_3(chip_mask, offset1, offset2, condition, severity, \
+                  fail_msg) \
+       do { \
+               if (CHIP_MASK_CHK(chip_mask)) { \
+                       val1 = REG_RD(bp, offset1); \
+                       val2 = REG_RD(bp, offset2); \
+                       CONDITION_CHK(condition, severity, \
+                                     fail_msg ". Values are 0x%x 0x%x\n", \
+                                     val1, val2); \
+               } \
+       } while (0);
+
+/* loop to read two regs and check the condition */
+#define IDLE_CHK_4(chip_mask, offset1, offset2, loop, inc, condition, \
+                  severity, fail_msg) \
+       do { \
+               if (CHIP_MASK_CHK(chip_mask)) \
+                       for (i = 0; i < (loop); i++) { \
+                               val1 = REG_RD(bp, offset1 + i*(inc)); \
+                               val2 = (REG_RD(bp, offset2 + i*(inc)) >> 1); \
+                               CONDITION_CHK(condition, severity, fail_msg \
+                                             " - LCID %d CID_CAM 0x%x" \
+                                             "  Value is 0x%x\n", \
+                                             i, val2, val1); \
+                       } \
+       } while (0);
+
+/* read one reg and check according to another reg */
+#define IDLE_CHK_5(chip_mask, offset, offset1, offset2, condition, severity, \
+                  fail_msg) \
+       do { \
+               if (CHIP_MASK_CHK(chip_mask)) \
+                       if (!REG_RD(bp, offset)) \
+                               IDLE_CHK_3(chip_mask, offset1, offset2, \
+                                          condition, severity, fail_msg); \
+       } while (0);
+
+/* read wide-bus reg and check sub-fields */
+#define IDLE_CHK_6(chip_mask, offset, loop, inc, severity) \
+       bnx2x_idle_chk6(bp, chip_mask, offset, loop, inc, severity)
+
+/* loop to read wide-bus reg and check according to another reg */
+#define IDLE_CHK_7(chip_mask, offset, offset1, offset2, loop, inc, condition, \
+                  severity, fail_msg) \
+       do { \
+               if (CHIP_MASK_CHK(chip_mask)) \
+                       for (i = 0; i < (loop); i++) { \
+                               if (REG_RD(bp, offset + i*4) == 1) { \
+                                       val1 = REG_RD(bp, offset1 + i*(inc)); \
+                                       val1 = REG_RD(bp, offset1 + i*(inc) + \
+                                                     4); \
+                                       val1 = ((REG_RD(bp, offset1 + i*(inc) \
+                                                + 8) & 0x00000078) >> 3); \
+                                       val2 = (REG_RD(bp, offset2 + i*4)>>1); \
+                                       CONDITION_CHK(condition, severity, \
+                                                     fail_msg " - LCID %d " \
+                                                     "CID_CAM 0x%x" \
+                                                     "  Value is 0x%x\n", \
+                                                     i, val2, val1); \
+                               } \
+                       } \
+       } while (0);
+
+
+       int is_e1  = CHIP_IS_E1(bp);
+       int is_e1h = CHIP_IS_E1H(bp);
+       int i;
+       u32 val, val1, val2;
+
+       idle_chk_errors = 0;
+       idle_chk_warnings = 0;
+
+       if (!netif_running(bp->dev))
+               return idle_chk_errors;
+
+       IDLE_CHK_1(0x7, 0x2114, ((val & 0x0ff010) != 0), IDLE_CHK_ERROR,
+                  "PCIE: ucorr_err_status is not 0");
+       IDLE_CHK_1(0x7, 0x2114, ((val & 0x100000) != 0), IDLE_CHK_WARNING,
+                  "PCIE: ucorr_err_status - Unsupported request error");
+       IDLE_CHK_1(0x7, 0x2120,
+                  (((val & 0x31c1) != 0x2000) && ((val & 0x31c1) != 0)),
+                  IDLE_CHK_WARNING, "PCIE: corr_err_status is not 0x2000");
+       IDLE_CHK_1(0x7, 0x2814, ((val & ~0x40100) != 0), IDLE_CHK_ERROR,
+                  "PCIE: attentions register is not 0x40100");
+       IDLE_CHK_1(0x6, 0x281c, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR,
+                  "PCIE: attentions register is not 0x40040100");
+       IDLE_CHK_1(0x6, 0x2820, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR,
+                  "PCIE: attentions register is not 0x40040100");
+       IDLE_CHK_1(0x1, PXP2_REG_PGL_EXP_ROM2, (val != 0xffffffff),
+                  IDLE_CHK_WARNING,
+                  "PXP2: There are outstanding read requests. Not all"
+                  " completions have arrived for read requests on tags that"
+                  " are marked with 0");
+       IDLE_CHK_2(0x7, 0x212c, 4, 4, ((val != 0) && (idle_chk_errors > 0)),
+                  IDLE_CHK_WARNING, "PCIE: error packet header %d is not 0");
+
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ0_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ0 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ1_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ1 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ2_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ2 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ3_ENTRY_CNT, (val > 2),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ3 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ4_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ4 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ5_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ5 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ6_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ6 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ7_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ7 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ8_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ8 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ9_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ9 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ10_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ10 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ11_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ11 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ12_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ12 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ13_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ13 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ14_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ14 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ15_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ15 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ16_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ16 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ17_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ17 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ18_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ18 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ19_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ19 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ20_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ20 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ21_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ21 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ22_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ22 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ23_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ23 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ24_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ24 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ25_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ25 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ26_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ26 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ27_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ27 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ28_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ28 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ29_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ29 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ30_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ30 is not empty");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_VQ31_ENTRY_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ31 is not empty");
+
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, (val != 0),
+                  IDLE_CHK_ERROR, "PXP2: rq_ufifo_num_of_entry is not 0");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_RBC_DONE, (val != 1), IDLE_CHK_ERROR,
+                  "PXP2: rq_rbc_done is not 1");
+       IDLE_CHK_1(0x7, PXP2_REG_RQ_CFG_DONE, (val != 1), IDLE_CHK_ERROR,
+                  "PXP2: rq_cfg_done is not 1");
+       IDLE_CHK_1(0x7, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x1b),
+                  IDLE_CHK_ERROR,
+                  "PXP2: rq_read_credit and rq_write_credit are not 3");
+       IDLE_CHK_1(0x7, PXP2_REG_RD_START_INIT, (val != 1), IDLE_CHK_ERROR,
+                  "PXP2: rd_start_init is not 1");
+       IDLE_CHK_1(0x7, PXP2_REG_RD_INIT_DONE, (val != 1), IDLE_CHK_ERROR,
+                  "PXP2: rd_init_done is not 1");
+
+       IDLE_CHK_3(0x7, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG,
+                  (val1 != (val2-1)), IDLE_CHK_WARNING,
+                  "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg");
+       IDLE_CHK_3(0x7, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG,
+                  (val1 != val2), IDLE_CHK_WARNING,
+                  "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg");
+
+       IDLE_CHK_3(0x7, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG,
+                  (val1 < (val2-3)), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: There are more than two unused SRs");
+       IDLE_CHK_3(0x7, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG,
+                  (val1 < (val2-2)), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: There are more than two unused blocks");
+
+       IDLE_CHK_1(0x7, PXP2_REG_RD_PORT_IS_IDLE_0, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: P0 All delivery ports are not idle");
+       IDLE_CHK_1(0x7, PXP2_REG_RD_PORT_IS_IDLE_1, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: P1 All delivery ports are not idle");
+
+       IDLE_CHK_2(0x7, PXP2_REG_RD_ALMOST_FULL_0, 11, 4, (val != 0),
+                  IDLE_CHK_ERROR, "PXP2: rd_almost_full_%d is not 0");
+
+       IDLE_CHK_1(0x7, PXP2_REG_RD_DISABLE_INPUTS, (val != 0),
+                  IDLE_CHK_ERROR, "PXP2: PSWRD inputs are disabled");
+       IDLE_CHK_1(0x7, PXP2_REG_HST_HEADER_FIFO_STATUS, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: HST header FIFO status is not 0");
+       IDLE_CHK_1(0x7, PXP2_REG_HST_DATA_FIFO_STATUS, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: HST data FIFO status is not 0");
+       IDLE_CHK_1(0x7, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0),
+                  IDLE_CHK_ERROR, "PXP2: pgl_write_blocked is not 0");
+       IDLE_CHK_1(0x7, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_ERROR,
+                  "PXP2: pgl_read_blocked is not 0");
+       IDLE_CHK_1(0x7, PXP2_REG_PGL_TXW_CDTS, (((val >> 17) & 1) != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PXP2: There is data which is ready");
+
+       IDLE_CHK_1(0x7, PXP_REG_HST_ARB_IS_IDLE, (val != 1), IDLE_CHK_WARNING,
+                  "PXP: HST arbiter is not idle");
+       IDLE_CHK_1(0x7, PXP_REG_HST_CLIENTS_WAITING_TO_ARB, (val != 0),
+                  IDLE_CHK_WARNING,
+                  "PXP: HST one of the clients is waiting for delivery");
+       IDLE_CHK_1(0x6, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
+                  (val != 0), IDLE_CHK_WARNING,
+                  "PXP: HST Close the gates: Discarding internal writes");
+       IDLE_CHK_1(0x6, PXP_REG_HST_DISCARD_DOORBELLS_STATUS, (val != 0),
+                  IDLE_CHK_WARNING,
+                  "PXP: HST Close the gates: Discarding doorbells");
+
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 0 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 1 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 2 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 3 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 4 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 5 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C6, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 6 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C7, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 7 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C8, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 8 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C9, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DMAE: command 9 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C10, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 10 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C11, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 11 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C12, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 12 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C13, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 13 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C14, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 14 go is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_GO_C15, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 15 go is not 0");
+
+       IDLE_CHK_1(0x7, CFC_REG_ERROR_VECTOR, (val != 0), IDLE_CHK_ERROR,
+                  "CFC: error vector is not 0");
+       IDLE_CHK_1(0x7, CFC_REG_NUM_LCIDS_ARRIVING, (val != 0),
+                  IDLE_CHK_ERROR, "CFC: number of arriving LCIDs is not 0");
+       IDLE_CHK_1(0x7, CFC_REG_NUM_LCIDS_ALLOC, (val != 0), IDLE_CHK_ERROR,
+                  "CFC: number of alloc LCIDs is not 0");
+       IDLE_CHK_1(0x7, CFC_REG_NUM_LCIDS_LEAVING, (val != 0), IDLE_CHK_ERROR,
+                  "CFC: number of leaving LCIDs is not 0");
+
+       IDLE_CHK_4(0x7, CFC_REG_ACTIVITY_COUNTER, CFC_REG_CID_CAM,
+                  (CFC_REG_ACTIVITY_COUNTER_SIZE >> 2), 4, (val1 > 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC > 1");
+       IDLE_CHK_7(0x7, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM,
+                  CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16,
+                  (val1 == 3), IDLE_CHK_WARNING,
+                  "CFC: AC is 1, connType is 3");
+       IDLE_CHK_7(0x7, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM,
+                  CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16,
+                  ((val1 != 0) && (val1 != 3)), IDLE_CHK_ERROR,
+                  "CFC: AC is 1, connType is not 0 nor 3");
+
+       IDLE_CHK_2(0x7, QM_REG_QTASKCTR_0, 64, 4, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Q_%d, queue is not empty");
+
+       IDLE_CHK_3(0x7, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0,
+                  (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "QM: VOQ_0, VOQ credit is not equal to initial credit");
+       IDLE_CHK_3(0x7, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1,
+                  (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "QM: VOQ_1, VOQ credit is not equal to initial credit");
+       IDLE_CHK_3(0x7, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4,
+                  (val1 != val2), IDLE_CHK_ERROR,
+                  "QM: VOQ_4, VOQ credit is not equal to initial credit");
+
+       IDLE_CHK_3(0x3, QM_REG_PORT0BYTECRD, QM_REG_BYTECRDINITVAL,
+                  (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "QM: P0 Byte credit is not equal to initial credit");
+       IDLE_CHK_3(0x3, QM_REG_PORT1BYTECRD, QM_REG_BYTECRDINITVAL,
+                  (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "QM: P1 Byte credit is not equal to initial credit");
+
+       IDLE_CHK_1(0x7, CCM_REG_CAM_OCCUP, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "CCM: XX protection CAM is not empty");
+       IDLE_CHK_1(0x7, TCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: XX protection CAM is not empty");
+       IDLE_CHK_1(0x7, UCM_REG_CAM_OCCUP, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "UCM: XX protection CAM is not empty");
+       IDLE_CHK_1(0x7, XCM_REG_CAM_OCCUP, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XCM: XX protection CAM is not empty");
+
+       IDLE_CHK_1(0x7, BRB1_REG_NUM_OF_FULL_BLOCKS, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "BRB1: BRB is not empty");
+
+       IDLE_CHK_1(0x7, CSEM_REG_SLEEP_THREADS_VALID, (val != 0),
+                  IDLE_CHK_ERROR, "CSEM: There are sleeping threads");
+       IDLE_CHK_1(0x7, TSEM_REG_SLEEP_THREADS_VALID, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSEM: There are sleeping threads");
+       IDLE_CHK_1(0x7, USEM_REG_SLEEP_THREADS_VALID, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USEM: There are sleeping threads");
+       IDLE_CHK_1(0x7, XSEM_REG_SLEEP_THREADS_VALID, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSEM: There are sleeping threads");
+
+       IDLE_CHK_1(0x7, CSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR, "CSEM: External store FIFO is not empty");
+       IDLE_CHK_1(0x7, TSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSEM: External store FIFO is not empty");
+       IDLE_CHK_1(0x7, USEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USEM: External store FIFO is not empty");
+       IDLE_CHK_1(0x7, XSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSEM: External store FIFO is not empty");
+
+       IDLE_CHK_1(0x7, CSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR, "CSDM: Parser serial FIFO is not empty");
+       IDLE_CHK_1(0x7, TSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSDM: Parser serial FIFO is not empty");
+       IDLE_CHK_1(0x7, USDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR, "USDM: Parser serial FIFO is not empty");
+       IDLE_CHK_1(0x7, XSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR, "XSDM: Parser serial FIFO is not empty");
+
+       IDLE_CHK_1(0x7, CSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+                  "CSDM: Parser SYNC serial FIFO is not empty");
+       IDLE_CHK_1(0x7, TSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+                  "TSDM: Parser SYNC serial FIFO is not empty");
+       IDLE_CHK_1(0x7, USDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+                  "USDM: Parser SYNC serial FIFO is not empty");
+       IDLE_CHK_1(0x7, XSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+                  "XSDM: Parser SYNC serial FIFO is not empty");
+
+       IDLE_CHK_1(0x7, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR,
+                  "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp"
+                  " block");
+       IDLE_CHK_1(0x7, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR,
+                  "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp"
+                  " block");
+       IDLE_CHK_1(0x7, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp"
+                  " block");
+       IDLE_CHK_1(0x7, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp"
+                  " block");
+
+       IDLE_CHK_1(0x7, DORQ_REG_DQ_FILL_LVLF, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "DQ: DORQ queue is not empty");
+
+       IDLE_CHK_1(0x7, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "CFC: interrupt status is not 0");
+       IDLE_CHK_1(0x7, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "CDU: interrupt status is not 0");
+       IDLE_CHK_1(0x7, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: interrupt status is not 0");
+       IDLE_CHK_1(0x7, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: interrupt status is not 0");
+       IDLE_CHK_1(0x7, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: interrupt status is not 0");
+       IDLE_CHK_1(0x7, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: interrupt status is not 0");
+       IDLE_CHK_1(0x7, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "PBF: interrupt status is not 0");
+       IDLE_CHK_1(0x7, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "TIMERS: interrupt status is not 0");
+       IDLE_CHK_1(0x7, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "DQ: interrupt status is not 0");
+       IDLE_CHK_1(0x7, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "SRCH: interrupt status is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_PRS_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "PRS: interrupt status is not 0");
+       IDLE_CHK_1(0x7, BRB1_REG_BRB1_INT_STS, ((val & ~0xfc00) != 0),
+                  IDLE_CHK_ERROR, "BRB1: interrupt status is not 0");
+       IDLE_CHK_1(0x7, GRCBASE_XPB + PB_REG_PB_INT_STS, (val != 0),
+                  IDLE_CHK_ERROR, "XPB: interrupt status is not 0");
+       IDLE_CHK_1(0x7, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0),
+                  IDLE_CHK_ERROR, "UPB: interrupt status is not 0");
+       IDLE_CHK_1(0x7, PXP2_REG_PXP2_INT_STS_0, (val != 0), IDLE_CHK_WARNING,
+                  "PXP2: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x6, PXP2_REG_PXP2_INT_STS_1, (val != 0), IDLE_CHK_WARNING,
+                  "PXP2: interrupt status 1 is not 0");
+       IDLE_CHK_1(0x7, QM_REG_QM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+                  "QM: interrupt status is not 0");
+       IDLE_CHK_1(0x7, PXP_REG_PXP_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+                  "PXP: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, PXP_REG_PXP_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "PXP: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, DORQ_REG_RSPA_CRD_CNT, (val != 2),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "DQ: Credit to XCM is not full");
+       IDLE_CHK_1(0x7, DORQ_REG_RSPB_CRD_CNT, (val != 2), IDLE_CHK_ERROR,
+                  "DQ: Credit to UCM is not full");
+
+       IDLE_CHK_1(0x3, QM_REG_VOQCRDERRREG, (val != 0), IDLE_CHK_ERROR,
+                  "QM: Credit error register is not 0 (byte or credit"
+                  " overflow/underflow)");
+       IDLE_CHK_1(0x7, DORQ_REG_DQ_FULL_ST, (val != 0), IDLE_CHK_ERROR,
+                  "DQ: DORQ queue is full");
+
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
+                  ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
+                  "AEU: P0 AFTER_INVERT_1 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0, (val != 0),
+                  IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_2 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
+                  ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
+                  "AEU: P0 AFTER_INVERT_3 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
+                  ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
+                  "AEU: P0 AFTER_INVERT_4 is not 0");
+
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
+                  ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
+                  "AEU: P1 AFTER_INVERT_1 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1, (val != 0),
+                  IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_2 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
+                  ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
+                  "AEU: P1 AFTER_INVERT_3 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
+                  ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
+                  "AEU: P1 AFTER_INVERT_4 is not 0");
+
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_1_MCP,
+                  ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
+                  "AEU: MCP AFTER_INVERT_1 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_2_MCP, (val != 0),
+                  IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_2 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_3_MCP,
+                  ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
+                  "AEU: MCP AFTER_INVERT_3 is not 0");
+       IDLE_CHK_1(0x7, MISC_REG_AEU_AFTER_INVERT_4_MCP,
+                  ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
+                  "AEU: MCP AFTER_INVERT_4 is not 0");
+
+       IDLE_CHK_5(0x7, PBF_REG_DISABLE_NEW_TASK_PROC_P0, PBF_REG_P0_CREDIT,
+                  PBF_REG_P0_INIT_CRD, (val1 != val2),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PBF: P0 credit is not equal to init_crd");
+       IDLE_CHK_5(0x7, PBF_REG_DISABLE_NEW_TASK_PROC_P1, PBF_REG_P1_CREDIT,
+                  PBF_REG_P1_INIT_CRD, (val1 != val2),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PBF: P1 credit is not equal to init_crd");
+       IDLE_CHK_3(0x7, PBF_REG_P4_CREDIT, PBF_REG_P4_INIT_CRD,
+                  (val1 != val2), IDLE_CHK_ERROR,
+                  "PBF: P4 credit is not equal to init_crd");
+
+       IDLE_CHK_1(0x7, PBF_REG_P0_TASK_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 task_cnt is not 0");
+       IDLE_CHK_1(0x7, PBF_REG_P1_TASK_CNT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 task_cnt is not 0");
+       IDLE_CHK_1(0x7, PBF_REG_P4_TASK_CNT, (val != 0), IDLE_CHK_ERROR,
+                  "PBF: P4 task_cnt is not 0");
+
+       IDLE_CHK_1(0x7, XCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
+                  "XCM: CFC_INIT_CRD is not 1");
+       IDLE_CHK_1(0x7, UCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
+                  "UCM: CFC_INIT_CRD is not 1");
+       IDLE_CHK_1(0x7, TCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
+                  "TCM: CFC_INIT_CRD is not 1");
+       IDLE_CHK_1(0x7, CCM_REG_CFC_INIT_CRD, (val != 1),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CFC_INIT_CRD is not 1");
+
+       IDLE_CHK_1(0x7, XCM_REG_XQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
+                  "XCM: XQM_INIT_CRD is not 32");
+       IDLE_CHK_1(0x7, UCM_REG_UQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
+                  "UCM: UQM_INIT_CRD is not 32");
+       IDLE_CHK_1(0x7, TCM_REG_TQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
+                  "TCM: TQM_INIT_CRD is not 32");
+       IDLE_CHK_1(0x7, CCM_REG_CQM_INIT_CRD, (val != 32),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CQM_INIT_CRD is not 32");
+
+       IDLE_CHK_1(0x7, XCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR,
+                  "XCM: TM_INIT_CRD is not 4");
+       IDLE_CHK_1(0x7, UCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR,
+                  "UCM: TM_INIT_CRD is not 4");
+
+       IDLE_CHK_1(0x7, XCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_WARNING,
+                  "XCM: FIC0_INIT_CRD is not 64");
+       IDLE_CHK_1(0x7, UCM_REG_FIC0_INIT_CRD, (val != 64),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC0_INIT_CRD is not 64");
+       IDLE_CHK_1(0x7, TCM_REG_FIC0_INIT_CRD, (val != 64),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC0_INIT_CRD is not 64");
+       IDLE_CHK_1(0x7, CCM_REG_FIC0_INIT_CRD, (val != 64),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC0_INIT_CRD is not 64");
+
+       IDLE_CHK_1(0x7, XCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+                  "XCM: FIC1_INIT_CRD is not 64");
+       IDLE_CHK_1(0x7, UCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+                  "UCM: FIC1_INIT_CRD is not 64");
+       IDLE_CHK_1(0x7, TCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+                  "TCM: FIC1_INIT_CRD is not 64");
+       IDLE_CHK_1(0x7, CCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+                  "CCM: FIC1_INIT_CRD is not 64");
+
+       IDLE_CHK_1(0x1, XCM_REG_XX_FREE, (val != 31), IDLE_CHK_ERROR,
+                  "XCM: XX_FREE is not 31");
+       IDLE_CHK_1(0x6, XCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR,
+                  "XCM: XX_FREE is not 32");
+       IDLE_CHK_1(0x7, UCM_REG_XX_FREE, (val != 27),
+                  IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX_FREE is not 27");
+       IDLE_CHK_1(0x7, TCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR,
+                  "TCM: XX_FREE is not 32");
+       IDLE_CHK_1(0x7, CCM_REG_XX_FREE, (val != 24), IDLE_CHK_ERROR,
+                  "CCM: XX_FREE is not 24");
+
+       IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x18000, (val !=  0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSEM: FOC0 credit less than initial credit");
+       IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x18040, (val !=  24),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSEM: FOC1 credit less than initial credit");
+       IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x18080, (val !=  12),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSEM: FOC2 credit less than initial credit");
+       IDLE_CHK_1(0x7, XSEM_REG_FAST_MEMORY + 0x180C0, (val !=  102),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "XSEM: FOC3 credit less than initial credit");
+
+       IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x18000, (val != 26),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USEM: FOC0 credit less than initial credit");
+       IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x18040, (val != 78),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USEM: FOC1 credit less than initial credit");
+       IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x18080, (val != 16),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USEM: FOC2 credit less than initial credit");
+       IDLE_CHK_1(0x7, USEM_REG_FAST_MEMORY + 0x180C0, (val != 32),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "USEM: FOC3 credit less than initial credit");
+
+       IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x18000, (val != 52),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSEM: FOC0 credit less than initial credit");
+       IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x18040, (val != 24),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSEM: FOC1 credit less than initial credit");
+       IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x18080, (val != 12),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSEM: FOC2 credit less than initial credit");
+       IDLE_CHK_1(0x7, TSEM_REG_FAST_MEMORY + 0x180C0, (val != 32),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "TSEM: FOC3 credit less than initial credit");
+
+       IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x18000, (val != 16),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "CSEM: FOC0 credit less than initial credit");
+       IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x18040, (val != 18),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "CSEM: FOC1 credit less than initial credit");
+       IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x18080, (val != 48),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "CSEM: FOC2 credit less than initial credit");
+       IDLE_CHK_1(0x7, CSEM_REG_FAST_MEMORY + 0x180C0, (val != 14),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "CSEM: FOC3 credit less than initial credit");
+
+       IDLE_CHK_1(0x7, PRS_REG_TSDM_CURRENT_CREDIT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: TSDM current credit is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_TCM_CURRENT_CREDIT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: TCM current credit is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_CFC_LD_CURRENT_CREDIT, (val != 0),
+                  IDLE_CHK_ERROR, "PRS: CFC_LD current credit is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_CFC_SEARCH_CURRENT_CREDIT, (val != 0),
+                  IDLE_CHK_ERROR, "PRS: CFC_SEARCH current credit is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_SRC_CURRENT_CREDIT, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: SRCH current credit is not 0");
+
+       IDLE_CHK_1(0x7, PRS_REG_PENDING_BRB_PRS_RQ, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: PENDING_BRB_PRS_RQ is not 0");
+       IDLE_CHK_2(0x7, PRS_REG_PENDING_BRB_CAC0_RQ, 5, 4, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: PENDING_BRB_CAC%d_RQ is not 0");
+
+       IDLE_CHK_1(0x7, PRS_REG_SERIAL_NUM_STATUS_LSB, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: SERIAL_NUM_STATUS_LSB is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_SERIAL_NUM_STATUS_MSB, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "PRS: SERIAL_NUM_STATUS_MSB is not 0");
+
+       IDLE_CHK_1(0x7, CDU_REG_ERROR_DATA, (val != 0), IDLE_CHK_ERROR,
+                  "CDU: ERROR_DATA is not 0");
+
+       IDLE_CHK_1(0x7, CCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: STORM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, CCM_REG_CSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: CSDM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, CCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: TSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, CCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: XSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, CCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: USEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, CCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "CCM: PBF declared message length unequal to actual");
+
+       IDLE_CHK_1(0x7, TCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: STORM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, TCM_REG_TSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: TSDM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, TCM_REG_PRS_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: PRS declared message length unequal to actual");
+       IDLE_CHK_1(0x7, TCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: PBF declared message length unequal to actual");
+       IDLE_CHK_1(0x7, TCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: USEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, TCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "TCM: CSEM declared message length unequal to actual");
+
+       IDLE_CHK_1(0x7, UCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: STORM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, UCM_REG_USDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: USDM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, UCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: TSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, UCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: CSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, UCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: XSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, UCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "UCM: DORQ declared message length unequal to actual");
+
+       IDLE_CHK_1(0x7, XCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: STORM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_XSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: XSDM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: TSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: CSEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: USEM declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: DORQ declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: PBF declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_NIG0_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: NIG0 declared message length unequal to actual");
+       IDLE_CHK_1(0x7, XCM_REG_NIG1_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+                  "XCM: NIG1 declared message length unequal to actual");
+
+       IDLE_CHK_1(0x7, QM_REG_XQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+                  "QM: XQM wrc_fifolvl is not 0");
+       IDLE_CHK_1(0x7, QM_REG_UQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+                  "QM: UQM wrc_fifolvl is not 0");
+       IDLE_CHK_1(0x7, QM_REG_TQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+                  "QM: TQM wrc_fifolvl is not 0");
+       IDLE_CHK_1(0x7, QM_REG_CQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+                  "QM: CQM wrc_fifolvl is not 0");
+       IDLE_CHK_1(0x7, QM_REG_QSTATUS_LOW, (val != 0), IDLE_CHK_ERROR,
+                  "QM: QSTATUS_LOW is not 0");
+       IDLE_CHK_1(0x7, QM_REG_QSTATUS_HIGH, (val != 0), IDLE_CHK_ERROR,
+                  "QM: QSTATUS_HIGH is not 0");
+       IDLE_CHK_1(0x7, QM_REG_PAUSESTATE0, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE0 is not 0");
+       IDLE_CHK_1(0x7, QM_REG_PAUSESTATE1, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE1 is not 0");
+       IDLE_CHK_1(0x7, QM_REG_OVFQNUM, (val != 0), IDLE_CHK_ERROR,
+                  "QM: OVFQNUM is not 0");
+       IDLE_CHK_1(0x7, QM_REG_OVFERROR, (val != 0), IDLE_CHK_ERROR,
+                  "QM: OVFERROR is not 0");
+
+       IDLE_CHK_6(0x7, QM_REG_PTRTBL, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC);
+
+       IDLE_CHK_1(0x7, BRB1_REG_BRB1_PRTY_STS, ((val & ~0x8) != 0),
+                  IDLE_CHK_WARNING, "BRB1: parity status is not 0");
+       IDLE_CHK_1(0x7, CDU_REG_CDU_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "CDU: parity status is not 0");
+       IDLE_CHK_1(0x7, CFC_REG_CFC_PRTY_STS, ((val & ~0x2) != 0),
+                  IDLE_CHK_WARNING, "CFC: parity status is not 0");
+       IDLE_CHK_1(0x7, CSDM_REG_CSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "CSDM: parity status is not 0");
+       IDLE_CHK_1(0x7, DBG_REG_DBG_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "DBG: parity status is not 0");
+       IDLE_CHK_1(0x7, DMAE_REG_DMAE_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "DMAE: parity status is not 0");
+       IDLE_CHK_1(0x7, DORQ_REG_DORQ_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "DQ: parity status is not 0");
+       IDLE_CHK_1(0x1, TCM_REG_TCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+                  IDLE_CHK_WARNING, "TCM: parity status is not 0");
+       IDLE_CHK_1(0x6, TCM_REG_TCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "TCM: parity status is not 0");
+       IDLE_CHK_1(0x1, CCM_REG_CCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+                  IDLE_CHK_WARNING, "CCM: parity status is not 0");
+       IDLE_CHK_1(0x6, CCM_REG_CCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "CCM: parity status is not 0");
+       IDLE_CHK_1(0x1, UCM_REG_UCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+                  IDLE_CHK_WARNING, "UCM: parity status is not 0");
+       IDLE_CHK_1(0x6, UCM_REG_UCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "UCM: parity status is not 0");
+       IDLE_CHK_1(0x1, XCM_REG_XCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+                  IDLE_CHK_WARNING, "XCM: parity status is not 0");
+       IDLE_CHK_1(0x6, XCM_REG_XCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "XCM: parity status is not 0");
+       IDLE_CHK_1(0x1, HC_REG_HC_PRTY_STS, ((val & ~0x1) != 0),
+                  IDLE_CHK_WARNING, "HC: parity status is not 0");
+       IDLE_CHK_1(0x1, MISC_REG_MISC_PRTY_STS, ((val & ~0x1) != 0),
+                  IDLE_CHK_WARNING, "MISC: parity status is not 0");
+       IDLE_CHK_1(0x7, PRS_REG_PRS_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "PRS: parity status is not 0");
+       IDLE_CHK_1(0x7, PXP_REG_PXP_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "PXP: parity status is not 0");
+       IDLE_CHK_1(0x7, QM_REG_QM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "QM: parity status is not 0");
+       IDLE_CHK_1(0x1, SRC_REG_SRC_PRTY_STS, ((val & ~0x4) != 0),
+                  IDLE_CHK_WARNING, "SRCH: parity status is not 0");
+       IDLE_CHK_1(0x7, TSDM_REG_TSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "TSDM: parity status is not 0");
+       IDLE_CHK_1(0x7, USDM_REG_USDM_PRTY_STS, ((val & ~0x20) != 0),
+                  IDLE_CHK_WARNING, "USDM: parity status is not 0");
+       IDLE_CHK_1(0x7, XSDM_REG_XSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "XSDM: parity status is not 0");
+       IDLE_CHK_1(0x7, GRCBASE_XPB + PB_REG_PB_PRTY_STS, (val != 0),
+                  IDLE_CHK_WARNING, "XPB: parity status is not 0");
+       IDLE_CHK_1(0x7, GRCBASE_UPB + PB_REG_PB_PRTY_STS, (val != 0),
+                  IDLE_CHK_WARNING, "UPB: parity status is not 0");
+
+       IDLE_CHK_1(0x7, CSEM_REG_CSEM_PRTY_STS_0, (val != 0),
+                  IDLE_CHK_WARNING, "CSEM: parity status 0 is not 0");
+       IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0xfff40020) != 0),
+                  IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0");
+       IDLE_CHK_1(0x6, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0x20) != 0),
+                  IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0");
+       IDLE_CHK_1(0x7, TSEM_REG_TSEM_PRTY_STS_0, (val != 0),
+                  IDLE_CHK_WARNING, "TSEM: parity status 0 is not 0");
+       IDLE_CHK_1(0x7, USEM_REG_USEM_PRTY_STS_0, (val != 0),
+                  IDLE_CHK_WARNING, "USEM: parity status 0 is not 0");
+       IDLE_CHK_1(0x7, XSEM_REG_XSEM_PRTY_STS_0, (val != 0),
+                  IDLE_CHK_WARNING, "XSEM: parity status 0 is not 0");
+
+       IDLE_CHK_1(0x7, CSEM_REG_CSEM_PRTY_STS_1, (val != 0),
+                  IDLE_CHK_WARNING, "CSEM: parity status 1 is not 0");
+       IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_1, ((val & ~0x20) != 0),
+                  IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0");
+       IDLE_CHK_1(0x6, PXP2_REG_PXP2_PRTY_STS_1, (val != 0),
+                  IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0");
+       IDLE_CHK_1(0x7, TSEM_REG_TSEM_PRTY_STS_1, (val != 0),
+                  IDLE_CHK_WARNING, "TSEM: parity status 1 is not 0");
+       IDLE_CHK_1(0x7, USEM_REG_USEM_PRTY_STS_1, (val != 0),
+                  IDLE_CHK_WARNING, "USEM: parity status 1 is not 0");
+       IDLE_CHK_1(0x7, XSEM_REG_XSEM_PRTY_STS_1, (val != 0),
+                  IDLE_CHK_WARNING, "XSEM: parity status 1 is not 0");
+
+       IDLE_CHK_2(0x2, QM_REG_QTASKCTR_EXT_A_0, 64, 4, (val != 0),
+                  IDLE_CHK_ERROR_NO_TRAFFIC,
+                  "QM: Q_EXT_A_%d, queue is not empty");
+       IDLE_CHK_1(0x2, QM_REG_QSTATUS_LOW_EXT_A, (val != 0), IDLE_CHK_ERROR,
+                  "QM: QSTATUS_LOW_EXT_A is not 0");
+       IDLE_CHK_1(0x2, QM_REG_QSTATUS_HIGH_EXT_A, (val != 0), IDLE_CHK_ERROR,
+                  "QM: QSTATUS_HIGH_EXT_A is not 0");
+       IDLE_CHK_1(0x6, QM_REG_PAUSESTATE2, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE2 is not 0");
+       IDLE_CHK_1(0x6, QM_REG_PAUSESTATE3, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE3 is not 0");
+       IDLE_CHK_1(0x2, QM_REG_PAUSESTATE4, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE4 is not 0");
+       IDLE_CHK_1(0x2, QM_REG_PAUSESTATE5, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE5 is not 0");
+       IDLE_CHK_1(0x2, QM_REG_PAUSESTATE6, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE6 is not 0");
+       IDLE_CHK_1(0x2, QM_REG_PAUSESTATE7, (val != 0), IDLE_CHK_ERROR,
+                  "QM: PAUSESTATE7 is not 0");
+       IDLE_CHK_6(0x2, QM_REG_PTRTBL_EXT_A, 64, 8,
+                  IDLE_CHK_ERROR_NO_TRAFFIC);
+
+       IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_OCCURRED, (val != 0),
+                  IDLE_CHK_ERROR, "MISC: system kill occurd;");
+       IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_0, (val != 0),
+                  IDLE_CHK_ERROR,
+                  "MISC: system kill occurd; status_0 register");
+       IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_1, (val != 0),
+                  IDLE_CHK_ERROR,
+                  "MISC: system kill occurd; status_1 register");
+       IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_2, (val != 0),
+                  IDLE_CHK_ERROR,
+                  "MISC: system kill occurd; status_2 register");
+       IDLE_CHK_1(0x6, MISC_REG_AEU_SYS_KILL_STATUS_3, (val != 0),
+                  IDLE_CHK_ERROR,
+                  "MISC: system kill occurd; status_3 register");
+       IDLE_CHK_1(0x6, MISC_REG_PCIE_HOT_RESET, (val != 0), IDLE_CHK_WARNING,
+                  "MISC: pcie_rst_b was asserted without perst assertion");
+
+       IDLE_CHK_1(0x7, NIG_REG_NIG_INT_STS_0, ((val & ~0x300) != 0),
+                  IDLE_CHK_ERROR, "NIG: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, NIG_REG_NIG_INT_STS_0, (val == 0x300),
+                  IDLE_CHK_WARNING,
+                  "NIG: Access to BMAC while not active. If tested on FPGA,"
+                  " ignore this warning.");
+       IDLE_CHK_1(0x7, NIG_REG_NIG_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "NIG: interrupt status 1 is not 0");
+       IDLE_CHK_1(0x6, NIG_REG_NIG_PRTY_STS, ((val & ~0xffc00000) != 0),
+                  IDLE_CHK_WARNING, "NIG: parity status is not 0");
+
+       IDLE_CHK_1(0x7, TSEM_REG_TSEM_INT_STS_0, ((val & ~0x10000000) != 0),
+                  IDLE_CHK_ERROR, "TSEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, TSEM_REG_TSEM_INT_STS_0, (val == 0x10000000),
+                  IDLE_CHK_WARNING, "TSEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, TSEM_REG_TSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "TSEM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, CSEM_REG_CSEM_INT_STS_0, ((val & ~0x10000000) != 0),
+                  IDLE_CHK_ERROR, "CSEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, CSEM_REG_CSEM_INT_STS_0, (val == 0x10000000),
+                  IDLE_CHK_WARNING, "CSEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, CSEM_REG_CSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "CSEM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, USEM_REG_USEM_INT_STS_0, ((val & ~0x10000000) != 0),
+                  IDLE_CHK_ERROR, "USEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, USEM_REG_USEM_INT_STS_0, (val == 0x10000000),
+                  IDLE_CHK_WARNING, "USEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, USEM_REG_USEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "USEM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, XSEM_REG_XSEM_INT_STS_0, ((val & ~0x10000000) != 0),
+                  IDLE_CHK_ERROR, "XSEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, XSEM_REG_XSEM_INT_STS_0, (val == 0x10000000),
+                  IDLE_CHK_WARNING, "XSEM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, XSEM_REG_XSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "XSEM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, TSDM_REG_TSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+                  "TSDM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, TSDM_REG_TSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "TSDM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, CSDM_REG_CSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+                  "CSDM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, CSDM_REG_CSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "CSDM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, USDM_REG_USDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+                  "USDM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, USDM_REG_USDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "USDM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x7, XSDM_REG_XSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+                  "XSDM: interrupt status 0 is not 0");
+       IDLE_CHK_1(0x7, XSDM_REG_XSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+                  "XSDM: interrupt status 1 is not 0");
+
+       IDLE_CHK_1(0x6, HC_REG_HC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "HC: parity status is not 0");
+       IDLE_CHK_1(0x6, MISC_REG_MISC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+                  "MISC: parity status is not 0");
+       IDLE_CHK_1(0x6, SRC_REG_SRC_PRTY_STS, (val  != 0), IDLE_CHK_WARNING,
+                  "SRCH: parity status is not 0");
+
+       if (idle_chk_errors == 0) {
+               BNX2X_DBG_ERR("completed successfully (with %d warnings)\n",
+                             idle_chk_warnings);
+       } else {
+               BNX2X_DBG_ERR("failed (with %d errors, %d warnings)\n",
+                             idle_chk_errors, idle_chk_warnings);
+       }
+       return idle_chk_errors;
+}
+
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/cnic_drv.h linux-2.6.22-800/drivers/net/bnx2x/cnic_drv.h
--- linux-2.6.22-800.orig/drivers/net/bnx2x/cnic_drv.h  1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/cnic_drv.h       2010-03-10 20:21:45.957168894 -0500
@@ -0,0 +1,125 @@
+/* cnic_drv.h: Broadcom CNIC core network driver.
+ *
+ * Copyright (c) 2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ */
+
+
+#ifndef CNIC_DRV_H
+#define CNIC_DRV_H
+
+#if !defined(__iomem)
+#define __iomem
+#endif
+
+struct kwqe;
+struct kcqe;
+struct kwqe_16;
+
+#define MAX_CNIC_CTL_DATA      64
+#define MAX_DRV_CTL_DATA       64
+
+#define CNIC_CTL_STOP_CMD              1
+#define CNIC_CTL_START_CMD             2
+#define CNIC_CTL_COMPLETION_CMD                3
+
+#define DRV_CTL_IO_WR_CMD              0x101
+#define DRV_CTL_IO_RD_CMD              0x102
+#define DRV_CTL_CTX_WR_CMD             0x103
+#define DRV_CTL_CTXTBL_WR_CMD          0x104
+#define DRV_CTL_COMPLETION_CMD         0x105
+
+struct cnic_ctl_completion {
+       u32     cid;
+};
+
+struct drv_ctl_completion {
+       u32     comp_count;
+};
+
+struct cnic_ctl_info {
+       int     cmd;
+       union {
+               struct cnic_ctl_completion comp;
+               char bytes[MAX_CNIC_CTL_DATA];
+       } data;
+};
+
+struct drv_ctl_io {
+       u32             cid_addr;
+       u32             offset;
+       u32             data;
+       dma_addr_t      dma_addr;
+};
+
+struct drv_ctl_info {
+       int     cmd;
+       union {
+               struct drv_ctl_completion comp;
+               struct drv_ctl_io io;
+               char bytes[MAX_DRV_CTL_DATA];
+       } data;
+};
+
+struct cnic_ops {
+       struct module   *cnic_owner;
+       /* Calls to these functions are protected by RCU.  When
+        * unregistering, we wait for any calls to complete before
+        * continuing.
+        */
+       int             (*cnic_handler)(void *, void *);
+       int             (*cnic_ctl)(void *, struct cnic_ctl_info *);
+       unsigned long   reserved[2];
+};
+
+#define MAX_CNIC_VEC   8
+
+struct cnic_irq {
+       unsigned int    vector;
+       void            *status_blk;
+       u32             status_blk_num;
+       u32             irq_flags;
+#define CNIC_IRQ_FL_MSIX               0x00000001
+};
+
+struct cnic_eth_dev {
+       struct module   *drv_owner;
+       u32             drv_state;
+#define CNIC_DRV_STATE_REGD            0x00000001
+#define CNIC_DRV_STATE_USING_MSIX      0x00000002
+       u32             chip_id;
+       u32             max_kwqe_pending;
+       struct pci_dev  *pdev;
+       void __iomem    *io_base;
+
+       u32             ctx_tbl_offset;
+       u32             ctx_tbl_len;
+       int             ctx_blk_size;
+       u32             starting_cid;
+       u32             max_iscsi_conn;
+       u32             max_fcoe_conn;
+       u32             max_rdma_conn;
+       u32             reserved0[2];
+
+       int             num_irq;
+       struct cnic_irq irq_arr[MAX_CNIC_VEC];
+       int             (*drv_register_cnic)(struct net_device *,
+                                            struct cnic_ops *, void *);
+       int             (*drv_unregister_cnic)(struct net_device *);
+       int             (*drv_submit_kwqes_32)(struct net_device *,
+                                              struct kwqe *[], u32);
+       int             (*drv_submit_kwqes_16)(struct net_device *,
+                                              struct kwqe_16 *[], u32);
+       int             (*drv_ctl)(struct net_device *, struct drv_ctl_info *);
+       unsigned long   reserved1[2];
+};
+
+#ifdef __VMKLNX__
+extern struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *);
+#endif
+
+#endif
diff -Nur linux-2.6.22-800.orig/drivers/net/bnx2x/Makefile linux-2.6.22-800/drivers/net/bnx2x/Makefile
--- linux-2.6.22-800.orig/drivers/net/bnx2x/Makefile    1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6.22-800/drivers/net/bnx2x/Makefile 2010-03-10 20:15:31.481644462 -0500
@@ -0,0 +1,2 @@
+obj-$(CONFIG_BNX2X) += bnx2x.o
+bnx2x-objs = bnx2x_main.o bnx2x_link.o bnx2x_init_values_e1.o bnx2x_init_values_e1h.o
diff -Nur linux-2.6.22-800.orig/drivers/net/Kconfig linux-2.6.22-800/drivers/net/Kconfig
--- linux-2.6.22-800.orig/drivers/net/Kconfig   2010-03-10 20:24:54.609427151 -0500
+++ linux-2.6.22-800/drivers/net/Kconfig        2010-03-10 20:10:25.803847904 -0500
@@ -2293,6 +2293,16 @@
          To compile this driver as a module, choose M here: the module
          will be called bnx2.  This is recommended.
 
+config BNX2X
+       tristate "Broadcom NetXtremeII 10Gb support"
+       depends on PCI
+       select ZLIB_INFLATE
+       select LIBCRC32C
+       help
+         This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
+         To compile this driver as a module, choose M here: the module
+         will be called bnx2x.  This is recommended.
+
 config SPIDER_NET
        tristate "Spider Gigabit Ethernet driver"
        depends on PCI && (PPC_IBM_CELL_BLADE || PPC_CELLEB)
diff -Nur linux-2.6.22-800.orig/drivers/net/Makefile linux-2.6.22-800/drivers/net/Makefile
--- linux-2.6.22-800.orig/drivers/net/Makefile  2010-03-10 20:25:05.164385046 -0500
+++ linux-2.6.22-800/drivers/net/Makefile       2010-03-10 20:11:00.502710298 -0500
@@ -60,6 +60,7 @@
 obj-$(CONFIG_FEALNX) += fealnx.o
 obj-$(CONFIG_TIGON3) += tg3.o
 obj-$(CONFIG_BNX2) += bnx2.o
+obj-$(CONFIG_BNX2X) += bnx2x/
 spidernet-y += spider_net.o spider_net_ethtool.o
 obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
 obj-$(CONFIG_TC35815) += tc35815.o