1 --- /build/BUILD/kernel-2.6.32-131.0.15.el6/linux-2.6.32-27.mlab.mlab.i686/drivers/net/tg3.c 2012-06-19 17:19:33.115164893 -0400
2 +++ linux-2.6.32-220.el6/drivers/net/tg3.c 2011-11-08 16:06:47.000000000 -0500
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 - * Copyright (C) 2005-2010 Broadcom Corporation.
8 + * Copyright (C) 2005-2011 Broadcom Corporation.
11 * Derived from proprietary unpublished source code,
15 #include <asm/system.h>
17 +#include <linux/io.h>
18 #include <asm/byteorder.h>
19 -#include <asm/uaccess.h>
20 +#include <linux/uaccess.h>
23 #include <asm/idprom.h>
28 +/* Functions & macros to verify TG3_FLAGS types */
30 +static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
32 + return test_bit(flag, bits);
35 +static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
37 + set_bit(flag, bits);
40 +static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
42 + clear_bit(flag, bits);
45 +#define tg3_flag(tp, flag) \
46 + _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
47 +#define tg3_flag_set(tp, flag) \
48 + _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
49 +#define tg3_flag_clear(tp, flag) \
50 + _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
52 #define DRV_MODULE_NAME "tg3"
54 -#define TG3_MIN_NUM 113
55 +#define TG3_MIN_NUM 119
56 #define DRV_MODULE_VERSION \
57 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
58 -#define DRV_MODULE_RELDATE "August 2, 2010"
59 +#define DRV_MODULE_RELDATE "May 18, 2011"
61 #define TG3_DEF_MAC_MODE 0
62 #define TG3_DEF_RX_MODE 0
67 +#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
69 /* length of time before we decide the hardware is borked,
70 * and dev->tx_timeout() should be called to fix the problem
73 #define TG3_TX_TIMEOUT (5 * HZ)
75 /* hardware minimum and maximum for a single frame's data payload */
76 #define TG3_MIN_MTU 60
77 #define TG3_MAX_MTU(tp) \
78 - ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
79 + (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
81 /* These numbers seem to be hard coded in the NIC firmware somehow.
82 * You can't change the ring sizes, but you can change where you place
83 * them in the NIC onboard memory.
85 #define TG3_RX_STD_RING_SIZE(tp) \
86 - ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
87 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
88 - RX_STD_MAX_SIZE_5717 : 512)
89 + (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
90 + TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
91 #define TG3_DEF_RX_RING_PENDING 200
92 #define TG3_RX_JMB_RING_SIZE(tp) \
93 - ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
94 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
96 + (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
97 + TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
98 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
99 #define TG3_RSS_INDIR_TBL_SIZE 128
103 #define TG3_RAW_IP_ALIGN 2
105 -/* number of ETHTOOL_GSTATS u64's */
106 -#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
108 -#define TG3_NUM_TEST 6
110 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
112 #define FIRMWARE_TG3 "tigon/tg3.bin"
114 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
115 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
116 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
117 - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
118 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
119 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
120 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
122 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
123 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
124 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
125 + {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
126 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
127 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
128 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
131 static const struct {
132 const char string[ETH_GSTRING_LEN];
133 -} ethtool_stats_keys[TG3_NUM_STATS] = {
134 +} ethtool_stats_keys[] = {
137 { "rx_ucast_packets" },
138 @@ -366,12 +386,17 @@
139 { "ring_status_update" },
141 { "nic_avoided_irqs" },
142 - { "nic_tx_threshold_hit" }
143 + { "nic_tx_threshold_hit" },
145 + { "mbuf_lwm_thresh_hit" },
148 +#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
151 static const struct {
152 const char string[ETH_GSTRING_LEN];
153 -} ethtool_test_keys[TG3_NUM_TEST] = {
154 +} ethtool_test_keys[] = {
155 { "nvram test (online) " },
156 { "link test (online) " },
157 { "register test (offline)" },
159 { "interrupt test (offline)" },
162 +#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
165 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
167 writel(val, tp->regs + off);
170 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
172 - if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
173 - (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
174 + if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
175 /* Non-posted methods */
176 tp->write32(tp, off, val);
179 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
181 tp->write32_mbox(tp, off, val);
182 - if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
183 - !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
184 + if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
185 tp->read32_mbox(tp, off);
190 void __iomem *mbox = tp->regs + off;
192 - if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
193 + if (tg3_flag(tp, TXD_MBOX_HWBUG))
195 - if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
196 + if (tg3_flag(tp, MBOX_WRITE_REORDER))
200 @@ -538,12 +564,12 @@
204 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
205 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
206 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
209 spin_lock_irqsave(&tp->indirect_lock, flags);
210 - if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
211 + if (tg3_flag(tp, SRAM_USE_CONFIG)) {
212 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
213 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
215 @@ -563,14 +589,14 @@
219 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
220 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
221 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
226 spin_lock_irqsave(&tp->indirect_lock, flags);
227 - if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
228 + if (tg3_flag(tp, SRAM_USE_CONFIG)) {
229 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
230 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
234 u32 status, req, gnt;
236 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
237 + if (!tg3_flag(tp, ENABLE_APE))
245 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
246 + if (!tg3_flag(tp, ENABLE_APE))
250 @@ -697,14 +723,14 @@
251 struct tg3_napi *tnapi = &tp->napi[i];
253 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
254 - if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
255 + if (tg3_flag(tp, 1SHOT_MSI))
256 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
258 tp->coal_now |= tnapi->coal_now;
261 /* Force an initial interrupt */
262 - if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
263 + if (!tg3_flag(tp, TAGGED_STATUS) &&
264 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
265 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
268 unsigned int work_exists = 0;
270 /* check for phy events */
271 - if (!(tp->tg3_flags &
272 - (TG3_FLAG_USE_LINKCHG_REG |
273 - TG3_FLAG_POLL_SERDES))) {
274 + if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
275 if (sblk->status & SD_STATUS_LINK_CHG)
278 @@ -750,55 +774,17 @@
279 * The last_tag we write above tells the chip which piece of
280 * work we've completed.
282 - if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
283 - tg3_has_work(tnapi))
284 + if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
285 tw32(HOSTCC_MODE, tp->coalesce_mode |
286 HOSTCC_MODE_ENABLE | tnapi->coal_now);
289 -static void tg3_napi_disable(struct tg3 *tp)
293 - for (i = tp->irq_cnt - 1; i >= 0; i--)
294 - napi_disable(&tp->napi[i].napi);
297 -static void tg3_napi_enable(struct tg3 *tp)
301 - for (i = 0; i < tp->irq_cnt; i++)
302 - napi_enable(&tp->napi[i].napi);
305 -static inline void tg3_netif_stop(struct tg3 *tp)
307 - tp->dev->trans_start = jiffies; /* prevent tx timeout */
308 - tg3_napi_disable(tp);
309 - netif_tx_disable(tp->dev);
312 -static inline void tg3_netif_start(struct tg3 *tp)
314 - /* NOTE: unconditional netif_tx_wake_all_queues is only
315 - * appropriate so long as all callers are assured to
316 - * have free tx slots (such as after tg3_init_hw)
318 - netif_tx_wake_all_queues(tp->dev);
320 - tg3_napi_enable(tp);
321 - tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
322 - tg3_enable_ints(tp);
325 static void tg3_switch_clocks(struct tg3 *tp)
330 - if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
331 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
332 + if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
335 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
338 tp->pci_clock_ctrl = clock_ctrl;
340 - if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
341 + if (tg3_flag(tp, 5705_PLUS)) {
342 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
343 tw32_wait_f(TG3PCI_CLOCK_CTRL,
344 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
345 @@ -926,6 +912,104 @@
349 +static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
353 + err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
357 + err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
361 + err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
362 + MII_TG3_MMD_CTRL_DATA_NOINC | devad);
366 + err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
372 +static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
376 + err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
380 + err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
384 + err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
385 + MII_TG3_MMD_CTRL_DATA_NOINC | devad);
389 + err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
395 +static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
399 + err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
401 + err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
406 +static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
410 + err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
412 + err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
417 +static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
421 + err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
422 + (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
423 + MII_TG3_AUXCTL_SHDWSEL_MISC);
425 + err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
430 +static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
432 + if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
433 + set |= MII_TG3_AUXCTL_MISC_WREN;
435 + return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
438 +#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
439 + tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
440 + MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
441 + MII_TG3_AUXCTL_ACTL_TX_6DB)
443 +#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
444 + tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
445 + MII_TG3_AUXCTL_ACTL_TX_6DB);
447 static int tg3_bmcr_reset(struct tg3 *tp)
450 @@ -1028,7 +1112,7 @@
454 - if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
455 + if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
456 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
457 MAC_PHYCFG2_FMODE_MASK_MASK |
458 MAC_PHYCFG2_GMODE_MASK_MASK |
459 @@ -1041,10 +1125,10 @@
460 val = tr32(MAC_PHYCFG1);
461 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
462 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
463 - if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
464 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
465 + if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
466 + if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
467 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
468 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
469 + if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
470 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
472 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
473 @@ -1059,13 +1143,13 @@
474 MAC_RGMII_MODE_TX_ENABLE |
475 MAC_RGMII_MODE_TX_LOWPWR |
476 MAC_RGMII_MODE_TX_RESET);
477 - if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
478 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
479 + if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
480 + if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
481 val |= MAC_RGMII_MODE_RX_INT_B |
482 MAC_RGMII_MODE_RX_QUALITY |
483 MAC_RGMII_MODE_RX_ACTIVITY |
484 MAC_RGMII_MODE_RX_ENG_DET;
485 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
486 + if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
487 val |= MAC_RGMII_MODE_TX_ENABLE |
488 MAC_RGMII_MODE_TX_LOWPWR |
489 MAC_RGMII_MODE_TX_RESET;
490 @@ -1079,7 +1163,7 @@
491 tw32_f(MAC_MI_MODE, tp->mi_mode);
494 - if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
495 + if (tg3_flag(tp, MDIOBUS_INITED) &&
496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
497 tg3_mdio_config_5785(tp);
499 @@ -1090,8 +1174,7 @@
501 struct phy_device *phydev;
503 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
504 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
505 + if (tg3_flag(tp, 5717_PLUS)) {
508 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
509 @@ -1108,8 +1191,7 @@
513 - if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
514 - (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
515 + if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
518 tp->mdio_bus = mdiobus_alloc();
519 @@ -1165,11 +1247,11 @@
520 PHY_BRCM_RX_REFCLK_UNUSED |
521 PHY_BRCM_DIS_TXCRXC_NOENRGY |
522 PHY_BRCM_AUTO_PWRDWN_ENABLE;
523 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
524 + if (tg3_flag(tp, RGMII_INBAND_DISABLE))
525 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
526 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
527 + if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
528 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
529 - if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
530 + if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
531 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
533 case PHY_ID_RTL8211C:
534 @@ -1183,7 +1265,7 @@
538 - tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
539 + tg3_flag_set(tp, MDIOBUS_INITED);
541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
542 tg3_mdio_config_5785(tp);
543 @@ -1193,59 +1275,13 @@
545 static void tg3_mdio_fini(struct tg3 *tp)
547 - if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
548 - tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
549 + if (tg3_flag(tp, MDIOBUS_INITED)) {
550 + tg3_flag_clear(tp, MDIOBUS_INITED);
551 mdiobus_unregister(tp->mdio_bus);
552 mdiobus_free(tp->mdio_bus);
556 -static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
560 - err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
564 - err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
568 - err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
569 - MII_TG3_MMD_CTRL_DATA_NOINC | devad);
573 - err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
579 -static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
583 - err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
587 - err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
591 - err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
592 - MII_TG3_MMD_CTRL_DATA_NOINC | devad);
596 - err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
602 /* tp->lock is held. */
603 static inline void tg3_generate_fw_event(struct tg3 *tp)
605 @@ -1293,8 +1329,7 @@
609 - if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
610 - !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
611 + if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
614 tg3_wait_for_event_ack(tp);
615 @@ -1354,6 +1389,11 @@
617 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
620 + if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
621 + netdev_info(tp->dev, "EEE is %s\n",
622 + tp->setlpicnt ? "enabled" : "disabled");
624 tg3_ump_link_report(tp);
627 @@ -1419,13 +1459,12 @@
628 u32 old_rx_mode = tp->rx_mode;
629 u32 old_tx_mode = tp->tx_mode;
631 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
632 + if (tg3_flag(tp, USE_PHYLIB))
633 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
635 autoneg = tp->link_config.autoneg;
637 - if (autoneg == AUTONEG_ENABLE &&
638 - (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
639 + if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
640 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
641 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
643 @@ -1622,28 +1661,6 @@
647 -static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
651 - err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
653 - err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
658 -static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
662 - err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
664 - err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
669 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
672 @@ -1668,9 +1685,8 @@
676 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
677 - ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
678 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
679 + if (!tg3_flag(tp, 5705_PLUS) ||
680 + (tg3_flag(tp, 5717_PLUS) &&
681 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
684 @@ -1704,7 +1720,7 @@
688 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
689 + if (!tg3_flag(tp, 5705_PLUS) ||
690 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
693 @@ -1726,31 +1742,33 @@
694 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
697 - phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
698 - MII_TG3_AUXCTL_SHDWSEL_MISC;
699 - if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
700 - !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
703 + ret = tg3_phy_auxctl_read(tp,
704 + MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
707 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
709 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
710 - phy |= MII_TG3_AUXCTL_MISC_WREN;
711 - tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
712 + tg3_phy_auxctl_write(tp,
713 + MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
718 static void tg3_phy_set_wirespeed(struct tg3 *tp)
723 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
726 - if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
727 - !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
728 - tg3_writephy(tp, MII_TG3_AUX_CTRL,
729 - (val | (1 << 15) | (1 << 4)));
730 + ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
732 + tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
733 + val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
736 static void tg3_phy_apply_otp(struct tg3 *tp)
737 @@ -1762,11 +1780,8 @@
741 - /* Enable SM_DSP clock and tx 6dB coding. */
742 - phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
743 - MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
744 - MII_TG3_AUXCTL_ACTL_TX_6DB;
745 - tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
746 + if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
749 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
750 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
751 @@ -1790,10 +1805,7 @@
752 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
753 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
755 - /* Turn off SM_DSP clock. */
756 - phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
757 - MII_TG3_AUXCTL_ACTL_TX_6DB;
758 - tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
759 + TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
762 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
763 @@ -1833,6 +1845,23 @@
767 +static void tg3_phy_eee_enable(struct tg3 *tp)
771 + if (tp->link_config.active_speed == SPEED_1000 &&
772 + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
773 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
774 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
775 + !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
776 + tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
777 + TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
780 + val = tr32(TG3_CPMU_EEE_MODE);
781 + tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
784 static int tg3_wait_macro_done(struct tg3 *tp)
787 @@ -1971,8 +2000,9 @@
788 (MII_TG3_CTRL_AS_MASTER |
789 MII_TG3_CTRL_ENABLE_AS_MASTER));
791 - /* Enable SM_DSP_CLOCK and 6dB. */
792 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
793 + err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
797 /* Block the PHY control access. */
798 tg3_phydsp_write(tp, 0x8005, 0x0800);
799 @@ -1991,13 +2021,7 @@
800 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
801 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
803 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
804 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
805 - /* Set Extended packet length bit for jumbo frames */
806 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
808 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
810 + TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
812 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
814 @@ -2015,19 +2039,16 @@
816 static int tg3_phy_reset(struct tg3 *tp)
823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
826 val = tr32(GRC_MISC_CFG);
827 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
830 - err = tg3_readphy(tp, MII_BMSR, &phy_status);
831 - err |= tg3_readphy(tp, MII_BMSR, &phy_status);
832 + err = tg3_readphy(tp, MII_BMSR, &val);
833 + err |= tg3_readphy(tp, MII_BMSR, &val);
837 @@ -2059,18 +2080,14 @@
840 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
843 - phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
844 - tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
845 + val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
846 + tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
848 tw32(TG3_CPMU_CTRL, cpmuctrl);
851 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
852 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
855 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
856 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
857 CPMU_LSPD_1000MB_MACCLK_12_5) {
858 @@ -2080,8 +2097,7 @@
862 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
863 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
864 + if (tg3_flag(tp, 5717_PLUS) &&
865 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
868 @@ -2093,56 +2109,60 @@
869 tg3_phy_toggle_apd(tp, false);
872 - if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
873 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
874 + if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
875 + !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
876 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
877 tg3_phydsp_write(tp, 0x000a, 0x0323);
878 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
879 + TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
882 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
883 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
884 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
887 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
888 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
889 - tg3_phydsp_write(tp, 0x000a, 0x310b);
890 - tg3_phydsp_write(tp, 0x201f, 0x9506);
891 - tg3_phydsp_write(tp, 0x401f, 0x14e2);
892 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
893 + if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
894 + tg3_phydsp_write(tp, 0x000a, 0x310b);
895 + tg3_phydsp_write(tp, 0x201f, 0x9506);
896 + tg3_phydsp_write(tp, 0x401f, 0x14e2);
897 + TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
899 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
900 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
901 - tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
902 - if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
903 - tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
904 - tg3_writephy(tp, MII_TG3_TEST1,
905 - MII_TG3_TEST1_TRIM_EN | 0x4);
907 - tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
908 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
909 + if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
910 + tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
911 + if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
912 + tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
913 + tg3_writephy(tp, MII_TG3_TEST1,
914 + MII_TG3_TEST1_TRIM_EN | 0x4);
916 + tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
918 + TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
922 /* Set Extended packet length bit (bit 14) on all chips that */
923 /* support jumbo frames */
924 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
925 /* Cannot do read-modify-write on 5401 */
926 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
927 - } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
930 + tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
931 + } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
932 /* Set bit 14 with read-modify-write to preserve other bits */
933 - if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
934 - !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
935 - tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
936 + err = tg3_phy_auxctl_read(tp,
937 + MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
939 + tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
940 + val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
943 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
944 * jumbo frames transmission.
946 - if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
949 - if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
950 + if (tg3_flag(tp, JUMBO_CAPABLE)) {
951 + if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
952 tg3_writephy(tp, MII_TG3_EXT_CTRL,
953 - phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
954 + val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
958 @@ -2155,120 +2175,158 @@
962 -static void tg3_frob_aux_power(struct tg3 *tp)
963 +static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
965 - struct tg3 *tp_peer = tp;
966 + if (!tg3_flag(tp, IS_NIC))
969 - /* The GPIOs do something completely different on 57765. */
970 - if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
971 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
972 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
973 + tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
974 + TG3_GRC_LCLCTL_PWRSW_DELAY);
979 +static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
981 + u32 grc_local_ctrl;
983 + if (!tg3_flag(tp, IS_NIC) ||
984 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
985 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
988 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
989 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
990 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
991 - struct net_device *dev_peer;
992 + grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
994 - dev_peer = pci_get_drvdata(tp->pdev_peer);
995 - /* remove_one() may have been run on the peer. */
999 - tp_peer = netdev_priv(dev_peer);
1001 + tw32_wait_f(GRC_LOCAL_CTRL,
1002 + grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
1003 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1005 - if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1006 - (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1007 - (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1008 - (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1009 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1010 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1011 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1012 - (GRC_LCLCTRL_GPIO_OE0 |
1013 + tw32_wait_f(GRC_LOCAL_CTRL,
1015 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1017 + tw32_wait_f(GRC_LOCAL_CTRL,
1018 + grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
1019 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1022 +static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
1024 + if (!tg3_flag(tp, IS_NIC))
1027 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1028 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1029 + tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1030 + (GRC_LCLCTRL_GPIO_OE0 |
1031 + GRC_LCLCTRL_GPIO_OE1 |
1032 + GRC_LCLCTRL_GPIO_OE2 |
1033 + GRC_LCLCTRL_GPIO_OUTPUT0 |
1034 + GRC_LCLCTRL_GPIO_OUTPUT1),
1035 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1036 + } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1037 + tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1038 + /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1039 + u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1040 GRC_LCLCTRL_GPIO_OE1 |
1041 GRC_LCLCTRL_GPIO_OE2 |
1042 GRC_LCLCTRL_GPIO_OUTPUT0 |
1043 - GRC_LCLCTRL_GPIO_OUTPUT1),
1045 - } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1046 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1047 - /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1048 - u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1049 - GRC_LCLCTRL_GPIO_OE1 |
1050 - GRC_LCLCTRL_GPIO_OE2 |
1051 - GRC_LCLCTRL_GPIO_OUTPUT0 |
1052 - GRC_LCLCTRL_GPIO_OUTPUT1 |
1053 - tp->grc_local_ctrl;
1054 - tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1056 - grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1057 - tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1058 + GRC_LCLCTRL_GPIO_OUTPUT1 |
1059 + tp->grc_local_ctrl;
1060 + tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
1061 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1063 - grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1064 - tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1067 - u32 grc_local_ctrl = 0;
1068 + grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1069 + tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
1070 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1072 - if (tp_peer != tp &&
1073 - (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1075 + grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1076 + tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
1077 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1080 + u32 grc_local_ctrl = 0;
1082 - /* Workaround to prevent overdrawing Amps. */
1083 - if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1085 - grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1086 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1087 - grc_local_ctrl, 100);
1089 + /* Workaround to prevent overdrawing Amps. */
1090 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
1091 + grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1092 + tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1097 - /* On 5753 and variants, GPIO2 cannot be used. */
1098 - no_gpio2 = tp->nic_sram_data_cfg &
1099 - NIC_SRAM_DATA_CFG_NO_GPIO2;
1100 + /* On 5753 and variants, GPIO2 cannot be used. */
1101 + no_gpio2 = tp->nic_sram_data_cfg &
1102 + NIC_SRAM_DATA_CFG_NO_GPIO2;
1104 - grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1105 - GRC_LCLCTRL_GPIO_OE1 |
1106 - GRC_LCLCTRL_GPIO_OE2 |
1107 - GRC_LCLCTRL_GPIO_OUTPUT1 |
1108 - GRC_LCLCTRL_GPIO_OUTPUT2;
1110 - grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1111 - GRC_LCLCTRL_GPIO_OUTPUT2);
1113 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 - grc_local_ctrl, 100);
1115 + grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1116 + GRC_LCLCTRL_GPIO_OE1 |
1117 + GRC_LCLCTRL_GPIO_OE2 |
1118 + GRC_LCLCTRL_GPIO_OUTPUT1 |
1119 + GRC_LCLCTRL_GPIO_OUTPUT2;
1121 + grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1122 + GRC_LCLCTRL_GPIO_OUTPUT2);
1124 + tw32_wait_f(GRC_LOCAL_CTRL,
1125 + tp->grc_local_ctrl | grc_local_ctrl,
1126 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1128 - grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1129 + grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1131 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132 - grc_local_ctrl, 100);
1133 + tw32_wait_f(GRC_LOCAL_CTRL,
1134 + tp->grc_local_ctrl | grc_local_ctrl,
1135 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1138 - grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1139 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 - grc_local_ctrl, 100);
1143 + grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1144 + tw32_wait_f(GRC_LOCAL_CTRL,
1145 + tp->grc_local_ctrl | grc_local_ctrl,
1146 + TG3_GRC_LCLCTL_PWRSW_DELAY);
1149 - if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1150 - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1151 - if (tp_peer != tp &&
1152 - (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1157 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1158 - (GRC_LCLCTRL_GPIO_OE1 |
1159 - GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1160 +static void tg3_frob_aux_power(struct tg3 *tp)
1162 + bool need_vaux = false;
1164 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1165 - GRC_LCLCTRL_GPIO_OE1, 100);
1166 + /* The GPIOs do something completely different on 57765. */
1167 + if (!tg3_flag(tp, IS_NIC) ||
1168 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
1169 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1172 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1173 - (GRC_LCLCTRL_GPIO_OE1 |
1174 - GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1175 + if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1176 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
1177 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1178 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
1179 + tp->pdev_peer != tp->pdev) {
1181 + struct net_device *dev_peer;
1183 + dev_peer = pci_get_drvdata(tp->pdev_peer);
1185 + /* remove_one() may have been run on the peer. */
1187 + struct tg3 *tp_peer = netdev_priv(dev_peer);
1189 + if (tg3_flag(tp_peer, INIT_COMPLETE))
1192 + if (tg3_flag(tp_peer, WOL_ENABLE) ||
1193 + tg3_flag(tp_peer, ENABLE_ASF))
1198 + if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF))
1202 + tg3_pwrsrc_switch_to_vaux(tp);
1204 + tg3_pwrsrc_die_with_vmain(tp);
1207 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1208 @@ -2340,11 +2398,10 @@
1209 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1210 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1212 - tg3_writephy(tp, MII_TG3_AUX_CTRL,
1213 - MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
1214 - MII_TG3_AUXCTL_PCTL_100TX_LPWR |
1215 - MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
1216 - MII_TG3_AUXCTL_PCTL_VREG_11V);
1217 + val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
1218 + MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
1219 + MII_TG3_AUXCTL_PCTL_VREG_11V;
1220 + tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
1223 /* The PHY should not be powered down on some chips because
1224 @@ -2370,7 +2427,7 @@
1225 /* tp->lock is held. */
1226 static int tg3_nvram_lock(struct tg3 *tp)
1228 - if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1229 + if (tg3_flag(tp, NVRAM)) {
1232 if (tp->nvram_lock_cnt == 0) {
1233 @@ -2393,7 +2450,7 @@
1234 /* tp->lock is held. */
1235 static void tg3_nvram_unlock(struct tg3 *tp)
1237 - if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1238 + if (tg3_flag(tp, NVRAM)) {
1239 if (tp->nvram_lock_cnt > 0)
1240 tp->nvram_lock_cnt--;
1241 if (tp->nvram_lock_cnt == 0)
1242 @@ -2404,8 +2461,7 @@
1243 /* tp->lock is held. */
1244 static void tg3_enable_nvram_access(struct tg3 *tp)
1246 - if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1247 - !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
1248 + if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
1249 u32 nvaccess = tr32(NVRAM_ACCESS);
1251 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
1252 @@ -2415,8 +2471,7 @@
1253 /* tp->lock is held. */
1254 static void tg3_disable_nvram_access(struct tg3 *tp)
1256 - if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1257 - !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
1258 + if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
1259 u32 nvaccess = tr32(NVRAM_ACCESS);
1261 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
1262 @@ -2486,10 +2541,10 @@
1264 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
1266 - if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
1267 - (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
1268 - (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
1269 - !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1270 + if (tg3_flag(tp, NVRAM) &&
1271 + tg3_flag(tp, NVRAM_BUFFERED) &&
1272 + tg3_flag(tp, FLASH) &&
1273 + !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
1274 (tp->nvram_jedecnum == JEDEC_ATMEL))
1276 addr = ((addr / tp->nvram_pagesize) <<
1277 @@ -2501,10 +2556,10 @@
1279 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
1281 - if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
1282 - (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
1283 - (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
1284 - !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1285 + if (tg3_flag(tp, NVRAM) &&
1286 + tg3_flag(tp, NVRAM_BUFFERED) &&
1287 + tg3_flag(tp, FLASH) &&
1288 + !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
1289 (tp->nvram_jedecnum == JEDEC_ATMEL))
1291 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
1292 @@ -2524,7 +2579,7 @@
1296 - if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
1297 + if (!tg3_flag(tp, NVRAM))
1298 return tg3_nvram_read_using_eeprom(tp, offset, val);
1300 offset = tg3_nvram_phys_addr(tp, offset);
1301 @@ -2599,42 +2654,37 @@
1302 tw32(MAC_TX_BACKOFF_SEED, addr_high);
1305 -static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1306 +static void tg3_enable_register_access(struct tg3 *tp)
1308 - u32 misc_host_ctrl;
1309 - bool device_should_wake, do_low_power;
1311 - /* Make sure register accesses (indirect or otherwise)
1312 - * will function correctly.
1314 + * Make sure register accesses (indirect or otherwise) will function
1317 pci_write_config_dword(tp->pdev,
1318 - TG3PCI_MISC_HOST_CTRL,
1319 - tp->misc_host_ctrl);
1320 + TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1325 - pci_enable_wake(tp->pdev, state, false);
1326 - pci_set_power_state(tp->pdev, PCI_D0);
1327 +static int tg3_power_up(struct tg3 *tp)
1329 + tg3_enable_register_access(tp);
1331 - /* Switch out of Vaux if it is a NIC */
1332 - if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1333 - tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1334 + pci_set_power_state(tp->pdev, PCI_D0);
1337 + /* Switch out of Vaux if it is a NIC */
1338 + tg3_pwrsrc_switch_to_vmain(tp);
1348 - netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
1352 +static int tg3_power_down_prepare(struct tg3 *tp)
1354 + u32 misc_host_ctrl;
1355 + bool device_should_wake, do_low_power;
1357 + tg3_enable_register_access(tp);
1359 /* Restore the CLKREQ setting. */
1360 - if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
1361 + if (tg3_flag(tp, CLKREQ_BUG)) {
1364 pci_read_config_word(tp->pdev,
1365 @@ -2650,11 +2700,10 @@
1366 tw32(TG3PCI_MISC_HOST_CTRL,
1367 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1369 - device_should_wake = pci_pme_capable(tp->pdev, state) &&
1370 - device_may_wakeup(&tp->pdev->dev) &&
1371 - (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
1372 + device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
1373 + tg3_flag(tp, WOL_ENABLE);
1375 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
1376 + if (tg3_flag(tp, USE_PHYLIB)) {
1377 do_low_power = false;
1378 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
1379 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1380 @@ -2675,9 +2724,8 @@
1381 ADVERTISED_Autoneg |
1382 ADVERTISED_10baseT_Half;
1384 - if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
1385 - device_should_wake) {
1386 - if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1387 + if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
1388 + if (tg3_flag(tp, WOL_SPEED_100MB))
1390 ADVERTISED_100baseT_Half |
1391 ADVERTISED_100baseT_Full |
1392 @@ -2722,7 +2770,7 @@
1394 val = tr32(GRC_VCPU_EXT_CTRL);
1395 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1396 - } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1397 + } else if (!tg3_flag(tp, ENABLE_ASF)) {
1401 @@ -2733,7 +2781,7 @@
1405 - if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1406 + if (tg3_flag(tp, WOL_CAP))
1407 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1408 WOL_DRV_STATE_SHUTDOWN |
1410 @@ -2743,8 +2791,13 @@
1413 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1414 - if (do_low_power) {
1415 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1416 + if (do_low_power &&
1417 + !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
1418 + tg3_phy_auxctl_write(tp,
1419 + MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
1420 + MII_TG3_AUXCTL_PCTL_WOL_EN |
1421 + MII_TG3_AUXCTL_PCTL_100TX_LPWR |
1422 + MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
1426 @@ -2756,8 +2809,7 @@
1427 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1428 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1430 - u32 speed = (tp->tg3_flags &
1431 - TG3_FLAG_WOL_SPEED_100MB) ?
1432 + u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
1433 SPEED_100 : SPEED_10;
1434 if (tg3_5700_link_polarity(tp, speed))
1435 mac_mode |= MAC_MODE_LINK_POLARITY;
1436 @@ -2768,22 +2820,18 @@
1437 mac_mode = MAC_MODE_PORT_MODE_TBI;
1440 - if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1441 + if (!tg3_flag(tp, 5750_PLUS))
1442 tw32(MAC_LED_CTRL, tp->led_ctrl);
1444 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1445 - if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
1446 - !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
1447 - ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
1448 - (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
1449 + if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
1450 + (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
1451 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1453 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
1454 - mac_mode |= tp->mac_mode &
1455 - (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
1456 - if (mac_mode & MAC_MODE_APE_TX_EN)
1457 - mac_mode |= MAC_MODE_TDE_ENABLE;
1459 + if (tg3_flag(tp, ENABLE_APE))
1460 + mac_mode |= MAC_MODE_APE_TX_EN |
1461 + MAC_MODE_APE_RX_EN |
1462 + MAC_MODE_TDE_ENABLE;
1464 tw32_f(MAC_MODE, mac_mode);
1466 @@ -2792,7 +2840,7 @@
1470 - if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1471 + if (!tg3_flag(tp, WOL_SPEED_100MB) &&
1472 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1475 @@ -2803,12 +2851,11 @@
1477 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1478 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1479 - } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1480 - (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1481 - (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1482 + } else if (tg3_flag(tp, 5780_CLASS) ||
1483 + tg3_flag(tp, CPMU_PRESENT) ||
1484 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1486 - } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1487 - (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1488 + } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1489 u32 newbits1, newbits2;
1491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1492 @@ -2817,7 +2864,7 @@
1493 CLOCK_CTRL_TXCLK_DISABLE |
1495 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1496 - } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1497 + } else if (tg3_flag(tp, 5705_PLUS)) {
1498 newbits1 = CLOCK_CTRL_625_CORE;
1499 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1501 @@ -2831,7 +2878,7 @@
1502 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1505 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1506 + if (!tg3_flag(tp, 5705_PLUS)) {
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1510 @@ -2848,8 +2895,7 @@
1514 - if (!(device_should_wake) &&
1515 - !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1516 + if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
1517 tg3_power_down_phy(tp, do_low_power);
1519 tg3_frob_aux_power(tp);
1520 @@ -2861,7 +2907,7 @@
1522 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1524 - if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1525 + if (!tg3_flag(tp, ENABLE_ASF)) {
1528 err = tg3_nvram_lock(tp);
1529 @@ -2873,13 +2919,15 @@
1531 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1533 - if (device_should_wake)
1534 - pci_enable_wake(tp->pdev, state, true);
1538 - /* Finally, set the new power state. */
1539 - pci_set_power_state(tp->pdev, state);
1540 +static void tg3_power_down(struct tg3 *tp)
1542 + tg3_power_down_prepare(tp);
1545 + pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
1546 + pci_set_power_state(tp->pdev, PCI_D3hot);
1549 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1550 @@ -2929,130 +2977,130 @@
1554 -static void tg3_phy_copper_begin(struct tg3 *tp)
1555 +static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1562 - if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1563 - /* Entering low power mode. Disable gigabit and
1564 - * 100baseT advertisements.
1566 - tg3_writephy(tp, MII_TG3_CTRL, 0);
1567 + new_adv = ADVERTISE_CSMA;
1568 + if (advertise & ADVERTISED_10baseT_Half)
1569 + new_adv |= ADVERTISE_10HALF;
1570 + if (advertise & ADVERTISED_10baseT_Full)
1571 + new_adv |= ADVERTISE_10FULL;
1572 + if (advertise & ADVERTISED_100baseT_Half)
1573 + new_adv |= ADVERTISE_100HALF;
1574 + if (advertise & ADVERTISED_100baseT_Full)
1575 + new_adv |= ADVERTISE_100FULL;
1577 - new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1578 - ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1579 - if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1580 - new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1581 + new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
1583 - tg3_writephy(tp, MII_ADVERTISE, new_adv);
1584 - } else if (tp->link_config.speed == SPEED_INVALID) {
1585 - if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
1586 - tp->link_config.advertising &=
1587 - ~(ADVERTISED_1000baseT_Half |
1588 - ADVERTISED_1000baseT_Full);
1589 + err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
1593 - new_adv = ADVERTISE_CSMA;
1594 - if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1595 - new_adv |= ADVERTISE_10HALF;
1596 - if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1597 - new_adv |= ADVERTISE_10FULL;
1598 - if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1599 - new_adv |= ADVERTISE_100HALF;
1600 - if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1601 - new_adv |= ADVERTISE_100FULL;
1602 + if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
1605 - new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1607 + if (advertise & ADVERTISED_1000baseT_Half)
1608 + new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1609 + if (advertise & ADVERTISED_1000baseT_Full)
1610 + new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1612 - tg3_writephy(tp, MII_ADVERTISE, new_adv);
1613 + if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1614 + tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1615 + new_adv |= (MII_TG3_CTRL_AS_MASTER |
1616 + MII_TG3_CTRL_ENABLE_AS_MASTER);
1618 - if (tp->link_config.advertising &
1619 - (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1621 - if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1622 - new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1623 - if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1624 - new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1625 - if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
1626 - (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1627 - tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1628 - new_adv |= (MII_TG3_CTRL_AS_MASTER |
1629 - MII_TG3_CTRL_ENABLE_AS_MASTER);
1630 - tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1632 - tg3_writephy(tp, MII_TG3_CTRL, 0);
1635 - new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1636 - new_adv |= ADVERTISE_CSMA;
1637 + err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1641 - /* Asking for a specific link mode. */
1642 - if (tp->link_config.speed == SPEED_1000) {
1643 - tg3_writephy(tp, MII_ADVERTISE, new_adv);
1644 + if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1647 - if (tp->link_config.duplex == DUPLEX_FULL)
1648 - new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1650 - new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1651 - if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1652 - tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1653 - new_adv |= (MII_TG3_CTRL_AS_MASTER |
1654 - MII_TG3_CTRL_ENABLE_AS_MASTER);
1656 - if (tp->link_config.speed == SPEED_100) {
1657 - if (tp->link_config.duplex == DUPLEX_FULL)
1658 - new_adv |= ADVERTISE_100FULL;
1660 - new_adv |= ADVERTISE_100HALF;
1662 - if (tp->link_config.duplex == DUPLEX_FULL)
1663 - new_adv |= ADVERTISE_10FULL;
1665 - new_adv |= ADVERTISE_10HALF;
1667 - tg3_writephy(tp, MII_ADVERTISE, new_adv);
1668 + tw32(TG3_CPMU_EEE_MODE,
1669 + tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1672 + err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
1676 + switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1677 + case ASIC_REV_5717:
1678 + case ASIC_REV_57765:
1679 + if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
1680 + tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
1681 + MII_TG3_DSP_CH34TP2_HIBW01);
1682 + /* Fall through */
1683 + case ASIC_REV_5719:
1684 + val = MII_TG3_DSP_TAP26_ALNOKO |
1685 + MII_TG3_DSP_TAP26_RMRXSTO |
1686 + MII_TG3_DSP_TAP26_OPCSINPT;
1687 + tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
1690 - tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1692 + /* Advertise 100-BaseTX EEE ability */
1693 + if (advertise & ADVERTISED_100baseT_Full)
1694 + val |= MDIO_AN_EEE_ADV_100TX;
1695 + /* Advertise 1000-BaseT EEE ability */
1696 + if (advertise & ADVERTISED_1000baseT_Full)
1697 + val |= MDIO_AN_EEE_ADV_1000T;
1698 + err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
1700 + err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1705 - if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
1711 - tw32(TG3_CPMU_EEE_MODE,
1712 - tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1713 +static void tg3_phy_copper_begin(struct tg3 *tp)
1718 - /* Enable SM_DSP clock and tx 6dB coding. */
1719 - val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1720 - MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1721 - MII_TG3_AUXCTL_ACTL_TX_6DB;
1722 - tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1723 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1724 + new_adv = ADVERTISED_10baseT_Half |
1725 + ADVERTISED_10baseT_Full;
1726 + if (tg3_flag(tp, WOL_SPEED_100MB))
1727 + new_adv |= ADVERTISED_100baseT_Half |
1728 + ADVERTISED_100baseT_Full;
1730 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1731 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
1732 - !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
1733 - tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
1734 - val | MII_TG3_DSP_CH34TP2_HIBW01);
1735 + tg3_phy_autoneg_cfg(tp, new_adv,
1736 + FLOW_CTRL_TX | FLOW_CTRL_RX);
1737 + } else if (tp->link_config.speed == SPEED_INVALID) {
1738 + if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
1739 + tp->link_config.advertising &=
1740 + ~(ADVERTISED_1000baseT_Half |
1741 + ADVERTISED_1000baseT_Full);
1744 - if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1745 - /* Advertise 100-BaseTX EEE ability */
1746 - if (tp->link_config.advertising &
1747 - ADVERTISED_100baseT_Full)
1748 - val |= MDIO_AN_EEE_ADV_100TX;
1749 - /* Advertise 1000-BaseT EEE ability */
1750 - if (tp->link_config.advertising &
1751 - ADVERTISED_1000baseT_Full)
1752 - val |= MDIO_AN_EEE_ADV_1000T;
1753 + tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
1754 + tp->link_config.flowctrl);
1756 + /* Asking for a specific link mode. */
1757 + if (tp->link_config.speed == SPEED_1000) {
1758 + if (tp->link_config.duplex == DUPLEX_FULL)
1759 + new_adv = ADVERTISED_1000baseT_Full;
1761 + new_adv = ADVERTISED_1000baseT_Half;
1762 + } else if (tp->link_config.speed == SPEED_100) {
1763 + if (tp->link_config.duplex == DUPLEX_FULL)
1764 + new_adv = ADVERTISED_100baseT_Full;
1766 + new_adv = ADVERTISED_100baseT_Half;
1768 + if (tp->link_config.duplex == DUPLEX_FULL)
1769 + new_adv = ADVERTISED_10baseT_Full;
1771 + new_adv = ADVERTISED_10baseT_Half;
1773 - tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
1775 - /* Turn off SM_DSP clock. */
1776 - val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1777 - MII_TG3_AUXCTL_ACTL_TX_6DB;
1778 - tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1779 + tg3_phy_autoneg_cfg(tp, new_adv,
1780 + tp->link_config.flowctrl);
1783 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1784 @@ -3110,7 +3158,7 @@
1786 /* Turn off tap power management. */
1787 /* Set Extended packet length bit */
1788 - err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1789 + err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1791 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
1792 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
1793 @@ -3173,7 +3221,7 @@
1794 if (curadv != reqadv)
1797 - if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
1798 + if (tg3_flag(tp, PAUSE_AUTONEG))
1799 tg3_readphy(tp, MII_LPA, rmtadv);
1801 /* Reprogram the advertisement register, even if it
1802 @@ -3195,7 +3243,7 @@
1803 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1805 int current_link_up;
1808 u32 lcl_adv, rmt_adv;
1811 @@ -3216,7 +3264,7 @@
1815 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1816 + tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1818 /* Some third-party PHYs need to be reset on link going
1820 @@ -3236,7 +3284,7 @@
1821 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1822 tg3_readphy(tp, MII_BMSR, &bmsr);
1823 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1824 - !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1825 + !tg3_flag(tp, INIT_COMPLETE))
1828 if (!(bmsr & BMSR_LSTATUS)) {
1829 @@ -3275,8 +3323,8 @@
1832 /* Clear pending interrupts... */
1833 - tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1834 - tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1835 + tg3_readphy(tp, MII_TG3_ISTAT, &val);
1836 + tg3_readphy(tp, MII_TG3_ISTAT, &val);
1838 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1839 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1840 @@ -3297,13 +3345,13 @@
1841 current_duplex = DUPLEX_INVALID;
1843 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
1846 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1847 - tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1848 - if (!(val & (1 << 10))) {
1850 - tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1851 + err = tg3_phy_auxctl_read(tp,
1852 + MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
1854 + if (!err && !(val & (1 << 10))) {
1855 + tg3_phy_auxctl_write(tp,
1856 + MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
1861 @@ -3373,13 +3421,11 @@
1864 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1867 tg3_phy_copper_begin(tp);
1869 - tg3_readphy(tp, MII_BMSR, &tmp);
1870 - if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1871 - (tmp & BMSR_LSTATUS))
1872 + tg3_readphy(tp, MII_BMSR, &bmsr);
1873 + if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1874 + (bmsr & BMSR_LSTATUS))
1875 current_link_up = 1;
1878 @@ -3422,7 +3468,7 @@
1880 tg3_phy_eee_adjust(tp, current_link_up);
1882 - if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1883 + if (tg3_flag(tp, USE_LINKCHG_REG)) {
1884 /* Polled via timer. */
1885 tw32_f(MAC_EVENT, 0);
1887 @@ -3433,8 +3479,7 @@
1888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1889 current_link_up == 1 &&
1890 tp->link_config.active_speed == SPEED_1000 &&
1891 - ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1892 - (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1893 + (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1896 (MAC_STATUS_SYNC_CHANGED |
1897 @@ -3446,7 +3491,7 @@
1900 /* Prevent send BD corruption. */
1901 - if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
1902 + if (tg3_flag(tp, CLKREQ_BUG)) {
1903 u16 oldlnkctl, newlnkctl;
1905 pci_read_config_word(tp->pdev,
1906 @@ -3841,7 +3886,7 @@
1909 /* Reset when initting first time or we have a link. */
1910 - if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
1911 + if (tg3_flag(tp, INIT_COMPLETE) &&
1912 !(mac_status & MAC_STATUS_PCS_SYNCED))
1915 @@ -4102,9 +4147,9 @@
1916 orig_active_speed = tp->link_config.active_speed;
1917 orig_active_duplex = tp->link_config.active_duplex;
1919 - if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
1920 + if (!tg3_flag(tp, HW_AUTONEG) &&
1921 netif_carrier_ok(tp->dev) &&
1922 - (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
1923 + tg3_flag(tp, INIT_COMPLETE)) {
1924 mac_status = tr32(MAC_STATUS);
1925 mac_status &= (MAC_STATUS_PCS_SYNCED |
1926 MAC_STATUS_SIGNAL_DET |
1927 @@ -4135,7 +4180,7 @@
1928 current_link_up = 0;
1929 mac_status = tr32(MAC_STATUS);
1931 - if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
1932 + if (tg3_flag(tp, HW_AUTONEG))
1933 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
1935 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
1936 @@ -4334,7 +4379,7 @@
1937 current_duplex = DUPLEX_FULL;
1939 current_duplex = DUPLEX_HALF;
1940 - } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1941 + } else if (!tg3_flag(tp, 5780_CLASS)) {
1942 /* Link is up via parallel detect */
1944 current_link_up = 0;
1945 @@ -4431,6 +4476,7 @@
1947 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
1952 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1953 @@ -4441,7 +4487,7 @@
1954 err = tg3_setup_copper_phy(tp, force_reset);
1956 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
1960 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
1961 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
1962 @@ -4456,19 +4502,22 @@
1963 tw32(GRC_MISC_CFG, val);
1966 + val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1967 + (6 << TX_LENGTHS_IPG_SHIFT);
1968 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
1969 + val |= tr32(MAC_TX_LENGTHS) &
1970 + (TX_LENGTHS_JMB_FRM_LEN_MSK |
1971 + TX_LENGTHS_CNT_DWN_VAL_MSK);
1973 if (tp->link_config.active_speed == SPEED_1000 &&
1974 tp->link_config.active_duplex == DUPLEX_HALF)
1975 - tw32(MAC_TX_LENGTHS,
1976 - ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1977 - (6 << TX_LENGTHS_IPG_SHIFT) |
1978 - (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1979 + tw32(MAC_TX_LENGTHS, val |
1980 + (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1982 - tw32(MAC_TX_LENGTHS,
1983 - ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1984 - (6 << TX_LENGTHS_IPG_SHIFT) |
1985 - (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1986 + tw32(MAC_TX_LENGTHS, val |
1987 + (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1989 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1990 + if (!tg3_flag(tp, 5705_PLUS)) {
1991 if (netif_carrier_ok(tp->dev)) {
1992 tw32(HOSTCC_STAT_COAL_TICKS,
1993 tp->coal.stats_block_coalesce_usecs);
1994 @@ -4477,8 +4526,8 @@
1998 - if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
1999 - u32 val = tr32(PCIE_PWR_MGMT_THRESH);
2000 + if (tg3_flag(tp, ASPM_WORKAROUND)) {
2001 + val = tr32(PCIE_PWR_MGMT_THRESH);
2002 if (!netif_carrier_ok(tp->dev))
2003 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
2005 @@ -4490,6 +4539,128 @@
2009 +static inline int tg3_irq_sync(struct tg3 *tp)
2011 + return tp->irq_sync;
2014 +static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
2018 + dst = (u32 *)((u8 *)dst + off);
2019 + for (i = 0; i < len; i += sizeof(u32))
2020 + *dst++ = tr32(off + i);
2023 +static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
2025 + tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
2026 + tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
2027 + tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
2028 + tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
2029 + tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
2030 + tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
2031 + tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
2032 + tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
2033 + tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
2034 + tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
2035 + tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
2036 + tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
2037 + tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
2038 + tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
2039 + tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
2040 + tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
2041 + tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
2042 + tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
2043 + tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
2045 + if (tg3_flag(tp, SUPPORT_MSIX))
2046 + tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
2048 + tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
2049 + tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
2050 + tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
2051 + tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
2052 + tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
2053 + tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
2054 + tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
2055 + tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
2057 + if (!tg3_flag(tp, 5705_PLUS)) {
2058 + tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
2059 + tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
2060 + tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
2063 + tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
2064 + tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
2065 + tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
2066 + tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
2067 + tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
2069 + if (tg3_flag(tp, NVRAM))
2070 + tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
2073 +static void tg3_dump_state(struct tg3 *tp)
2078 + regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
2080 + netdev_err(tp->dev, "Failed allocating register dump buffer\n");
2084 + if (tg3_flag(tp, PCI_EXPRESS)) {
2085 + /* Read up to but not including private PCI registers */
2086 + for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
2087 + regs[i / sizeof(u32)] = tr32(i);
2089 + tg3_dump_legacy_regs(tp, regs);
2091 + for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
2092 + if (!regs[i + 0] && !regs[i + 1] &&
2093 + !regs[i + 2] && !regs[i + 3])
2096 + netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
2098 + regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
2103 + for (i = 0; i < tp->irq_cnt; i++) {
2104 + struct tg3_napi *tnapi = &tp->napi[i];
2106 + /* SW status block */
2107 + netdev_err(tp->dev,
2108 + "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
2110 + tnapi->hw_status->status,
2111 + tnapi->hw_status->status_tag,
2112 + tnapi->hw_status->rx_jumbo_consumer,
2113 + tnapi->hw_status->rx_consumer,
2114 + tnapi->hw_status->rx_mini_consumer,
2115 + tnapi->hw_status->idx[0].rx_producer,
2116 + tnapi->hw_status->idx[0].tx_consumer);
2118 + netdev_err(tp->dev,
2119 + "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
2121 + tnapi->last_tag, tnapi->last_irq_tag,
2122 + tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
2123 + tnapi->rx_rcb_ptr,
2124 + tnapi->prodring.rx_std_prod_idx,
2125 + tnapi->prodring.rx_std_cons_idx,
2126 + tnapi->prodring.rx_jmb_prod_idx,
2127 + tnapi->prodring.rx_jmb_cons_idx);
2131 /* This is called whenever we suspect that the system chipset is re-
2132 * ordering the sequence of MMIO to the tx send mailbox. The symptom
2133 * is bogus tx completions. We try to recover by setting the
2134 @@ -4498,7 +4669,7 @@
2136 static void tg3_tx_recover(struct tg3 *tp)
2138 - BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
2139 + BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
2140 tp->write32_tx_mbox == tg3_write_indirect_mbox);
2142 netdev_warn(tp->dev,
2143 @@ -4508,7 +4679,7 @@
2144 "and include system chipset information.\n");
2146 spin_lock(&tp->lock);
2147 - tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
2148 + tg3_flag_set(tp, TX_RECOVERY_PENDING);
2149 spin_unlock(&tp->lock);
2152 @@ -4532,7 +4703,7 @@
2153 struct netdev_queue *txq;
2154 int index = tnapi - tp->napi;
2156 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
2157 + if (tg3_flag(tp, ENABLE_TSS))
2160 txq = netdev_get_tx_queue(tp->dev, index);
2161 @@ -4621,12 +4792,11 @@
2162 u32 opaque_key, u32 dest_idx_unmasked)
2164 struct tg3_rx_buffer_desc *desc;
2165 - struct ring_info *map, *src_map;
2166 + struct ring_info *map;
2167 struct sk_buff *skb;
2169 int skb_size, dest_idx;
2172 switch (opaque_key) {
2173 case RXD_OPAQUE_RING_STD:
2174 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
2175 @@ -4686,7 +4856,7 @@
2176 struct tg3 *tp = tnapi->tp;
2177 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2178 struct ring_info *src_map, *dest_map;
2179 - struct tg3_rx_prodring_set *spr = &tp->prodring[0];
2180 + struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
2183 switch (opaque_key) {
2184 @@ -4756,7 +4926,7 @@
2185 u32 sw_idx = tnapi->rx_rcb_ptr;
2188 - struct tg3_rx_prodring_set *tpr = tnapi->prodring;
2189 + struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
2191 hw_idx = *(tnapi->rx_rcb_prod_idx);
2193 @@ -4781,13 +4951,13 @@
2194 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2195 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2196 if (opaque_key == RXD_OPAQUE_RING_STD) {
2197 - ri = &tp->prodring[0].rx_std_buffers[desc_idx];
2198 + ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
2199 dma_addr = pci_unmap_addr(ri, mapping);
2201 post_ptr = &std_prod_idx;
2203 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2204 - ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
2205 + ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
2206 dma_addr = pci_unmap_addr(ri, mapping);
2208 post_ptr = &jmb_prod_idx;
2209 @@ -4850,13 +5020,13 @@
2213 - if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2214 + if ((tg3_flag(tp, RX_CHECKSUMS)) &&
2215 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2216 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2217 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2218 skb->ip_summed = CHECKSUM_UNNECESSARY;
2220 - skb->ip_summed = CHECKSUM_NONE;
2221 + skb_checksum_none_assert(skb);
2223 skb->protocol = eth_type_trans(skb, tp->dev);
2225 @@ -4922,7 +5092,7 @@
2226 tw32_rx_mbox(tnapi->consmbox, sw_idx);
2228 /* Refill RX ring(s). */
2229 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
2230 + if (!tg3_flag(tp, ENABLE_RSS)) {
2231 if (work_mask & RXD_OPAQUE_RING_STD) {
2232 tpr->rx_std_prod_idx = std_prod_idx &
2233 tp->rx_std_ring_mask;
2234 @@ -4955,16 +5125,14 @@
2235 static void tg3_poll_link(struct tg3 *tp)
2237 /* handle link change and other phy events */
2238 - if (!(tp->tg3_flags &
2239 - (TG3_FLAG_USE_LINKCHG_REG |
2240 - TG3_FLAG_POLL_SERDES))) {
2241 + if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
2242 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
2244 if (sblk->status & SD_STATUS_LINK_CHG) {
2245 sblk->status = SD_STATUS_UPDATED |
2246 (sblk->status & ~SD_STATUS_LINK_CHG);
2247 spin_lock(&tp->lock);
2248 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2249 + if (tg3_flag(tp, USE_PHYLIB)) {
2251 (MAC_STATUS_SYNC_CHANGED |
2252 MAC_STATUS_CFG_CHANGED |
2253 @@ -5111,7 +5279,7 @@
2254 /* run TX completion thread */
2255 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
2257 - if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
2258 + if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
2262 @@ -5122,15 +5290,15 @@
2263 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
2264 work_done += tg3_rx(tnapi, budget - work_done);
2266 - if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
2267 - struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
2268 + if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
2269 + struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
2271 u32 std_prod_idx = dpr->rx_std_prod_idx;
2272 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
2274 for (i = 1; i < tp->irq_cnt; i++)
2275 err |= tg3_rx_prodring_xfer(tp, dpr,
2276 - tp->napi[i].prodring);
2277 + &tp->napi[i].prodring);
2281 @@ -5161,7 +5329,7 @@
2283 work_done = tg3_poll_work(tnapi, work_done, budget);
2285 - if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
2286 + if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
2289 if (unlikely(work_done >= budget))
2290 @@ -5195,6 +5363,40 @@
2294 +static void tg3_process_error(struct tg3 *tp)
2297 + bool real_error = false;
2299 + if (tg3_flag(tp, ERROR_PROCESSED))
2302 + /* Check Flow Attention register */
2303 + val = tr32(HOSTCC_FLOW_ATTN);
2304 + if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
2305 + netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
2306 + real_error = true;
2309 + if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
2310 + netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
2311 + real_error = true;
2314 + if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
2315 + netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
2316 + real_error = true;
2322 + tg3_dump_state(tp);
2324 + tg3_flag_set(tp, ERROR_PROCESSED);
2325 + schedule_work(&tp->reset_task);
2328 static int tg3_poll(struct napi_struct *napi, int budget)
2330 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
2331 @@ -5203,17 +5405,20 @@
2332 struct tg3_hw_status *sblk = tnapi->hw_status;
2335 + if (sblk->status & SD_STATUS_ERROR)
2336 + tg3_process_error(tp);
2340 work_done = tg3_poll_work(tnapi, work_done, budget);
2342 - if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
2343 + if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
2346 if (unlikely(work_done >= budget))
2349 - if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
2350 + if (tg3_flag(tp, TAGGED_STATUS)) {
2351 /* tp->last_tag is used in tg3_int_reenable() below
2352 * to tell the hw how much work has been processed,
2353 * so we must read it before checking for more work.
2354 @@ -5240,6 +5445,59 @@
2358 +static void tg3_napi_disable(struct tg3 *tp)
2362 + for (i = tp->irq_cnt - 1; i >= 0; i--)
2363 + napi_disable(&tp->napi[i].napi);
2366 +static void tg3_napi_enable(struct tg3 *tp)
2370 + for (i = 0; i < tp->irq_cnt; i++)
2371 + napi_enable(&tp->napi[i].napi);
2374 +static void tg3_napi_init(struct tg3 *tp)
2378 + netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
2379 + for (i = 1; i < tp->irq_cnt; i++)
2380 + netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
2383 +static void tg3_napi_fini(struct tg3 *tp)
2387 + for (i = 0; i < tp->irq_cnt; i++)
2388 + netif_napi_del(&tp->napi[i].napi);
2391 +static inline void tg3_netif_stop(struct tg3 *tp)
2393 + tp->dev->trans_start = jiffies; /* prevent tx timeout */
2394 + tg3_napi_disable(tp);
2395 + netif_tx_disable(tp->dev);
2398 +static inline void tg3_netif_start(struct tg3 *tp)
2400 + /* NOTE: unconditional netif_tx_wake_all_queues is only
2401 + * appropriate so long as all callers are assured to
2402 + * have free tx slots (such as after tg3_init_hw)
2404 + netif_tx_wake_all_queues(tp->dev);
2406 + tg3_napi_enable(tp);
2407 + tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
2408 + tg3_enable_ints(tp);
2411 static void tg3_irq_quiesce(struct tg3 *tp)
2414 @@ -5253,11 +5511,6 @@
2415 synchronize_irq(tp->napi[i].irq_vec);
2418 -static inline int tg3_irq_sync(struct tg3 *tp)
2420 - return tp->irq_sync;
2423 /* Fully shutdown all tg3 driver activity elsewhere in the system.
2424 * If irq_sync is non-zero, then the IRQ handler must be synchronized
2425 * with as well. Most of the time, this is not necessary except when
2426 @@ -5332,7 +5585,7 @@
2427 * interrupt is ours and will flush the status block.
2429 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
2430 - if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
2431 + if (tg3_flag(tp, CHIP_RESETTING) ||
2432 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2435 @@ -5381,7 +5634,7 @@
2436 * interrupt is ours and will flush the status block.
2438 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
2439 - if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
2440 + if (tg3_flag(tp, CHIP_RESETTING) ||
2441 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2444 @@ -5494,14 +5747,14 @@
2446 tg3_full_lock(tp, 1);
2448 - restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
2449 - tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
2450 + restart_timer = tg3_flag(tp, RESTART_TIMER);
2451 + tg3_flag_clear(tp, RESTART_TIMER);
2453 - if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
2454 + if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
2455 tp->write32_tx_mbox = tg3_write32_tx_mbox;
2456 tp->write32_rx_mbox = tg3_write_flush_reg32;
2457 - tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
2458 - tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
2459 + tg3_flag_set(tp, MBOX_WRITE_REORDER);
2460 + tg3_flag_clear(tp, TX_RECOVERY_PENDING);
2463 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
2464 @@ -5521,21 +5774,13 @@
2468 -static void tg3_dump_short_state(struct tg3 *tp)
2470 - netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
2471 - tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
2472 - netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
2473 - tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
2476 static void tg3_tx_timeout(struct net_device *dev)
2478 struct tg3 *tp = netdev_priv(dev);
2480 if (netif_msg_tx_err(tp)) {
2481 netdev_err(dev, "transmit timed out, resetting\n");
2482 - tg3_dump_short_state(tp);
2483 + tg3_dump_state(tp);
2486 schedule_work(&tp->reset_task);
2487 @@ -5546,8 +5791,7 @@
2489 u32 base = (u32) mapping & 0xffffffff;
2491 - return ((base > 0xffffdcc0) &&
2492 - (base + len + 8 < base));
2493 + return (base > 0xffffdcc0) && (base + len + 8 < base);
2496 /* Test for DMA addresses > 40-bit */
2497 @@ -5555,15 +5799,36 @@
2500 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
2501 - if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
2502 - return (((u64) mapping + len) > DMA_BIT_MASK(40));
2503 + if (tg3_flag(tp, 40BIT_DMA_BUG))
2504 + return ((u64) mapping + len) > DMA_BIT_MASK(40);
2511 -static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
2512 +static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
2513 + dma_addr_t mapping, int len, u32 flags,
2514 + u32 mss_and_is_end)
2516 + struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
2517 + int is_end = (mss_and_is_end & 0x1);
2518 + u32 mss = (mss_and_is_end >> 1);
2522 + flags |= TXD_FLAG_END;
2523 + if (flags & TXD_FLAG_VLAN) {
2524 + vlan_tag = flags >> 16;
2527 + vlan_tag |= (mss << TXD_MSS_SHIFT);
2529 + txd->addr_hi = ((u64) mapping >> 32);
2530 + txd->addr_lo = ((u64) mapping & 0xffffffff);
2531 + txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
2532 + txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
2535 /* Workaround 4GB and 40-bit hardware DMA bugs. */
2536 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
2537 @@ -5602,8 +5867,8 @@
2538 /* Make sure new skb does not cross any 4G boundaries.
2539 * Drop the packet if it does.
2541 - } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
2542 - tg3_4g_overflow_test(new_addr, new_skb->len)) {
2543 + } else if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
2544 + tg3_4g_overflow_test(new_addr, new_skb->len)) {
2545 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
2548 @@ -5646,204 +5911,7 @@
2552 -static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
2553 - dma_addr_t mapping, int len, u32 flags,
2554 - u32 mss_and_is_end)
2556 - struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
2557 - int is_end = (mss_and_is_end & 0x1);
2558 - u32 mss = (mss_and_is_end >> 1);
2562 - flags |= TXD_FLAG_END;
2563 - if (flags & TXD_FLAG_VLAN) {
2564 - vlan_tag = flags >> 16;
2567 - vlan_tag |= (mss << TXD_MSS_SHIFT);
2569 - txd->addr_hi = ((u64) mapping >> 32);
2570 - txd->addr_lo = ((u64) mapping & 0xffffffff);
2571 - txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
2572 - txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
2575 -/* hard_start_xmit for devices that don't have any bugs and
2576 - * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
2578 -static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
2579 - struct net_device *dev)
2581 - struct tg3 *tp = netdev_priv(dev);
2582 - u32 len, entry, base_flags, mss;
2583 - dma_addr_t mapping;
2584 - struct tg3_napi *tnapi;
2585 - struct netdev_queue *txq;
2586 - unsigned int i, last;
2588 - txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2589 - tnapi = &tp->napi[skb_get_queue_mapping(skb)];
2590 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
2593 - /* We are running in BH disabled context with netif_tx_lock
2594 - * and TX reclaim runs via tp->napi.poll inside of a software
2595 - * interrupt. Furthermore, IRQ processing runs lockless so we have
2596 - * no IRQ context deadlocks to worry about either. Rejoice!
2598 - if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
2599 - if (!netif_tx_queue_stopped(txq)) {
2600 - netif_tx_stop_queue(txq);
2602 - /* This is a hard error, log it. */
2604 - "BUG! Tx Ring full when queue awake!\n");
2606 - return NETDEV_TX_BUSY;
2609 - entry = tnapi->tx_prod;
2611 - mss = skb_shinfo(skb)->gso_size;
2613 - int tcp_opt_len, ip_tcp_len;
2616 - if (skb_header_cloned(skb) &&
2617 - pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
2618 - dev_kfree_skb(skb);
2622 - if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
2623 - hdrlen = skb_headlen(skb) - ETH_HLEN;
2625 - struct iphdr *iph = ip_hdr(skb);
2627 - tcp_opt_len = tcp_optlen(skb);
2628 - ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
2631 - iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
2632 - hdrlen = ip_tcp_len + tcp_opt_len;
2635 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
2636 - mss |= (hdrlen & 0xc) << 12;
2637 - if (hdrlen & 0x10)
2638 - base_flags |= 0x00000010;
2639 - base_flags |= (hdrlen & 0x3e0) << 5;
2641 - mss |= hdrlen << 9;
2643 - base_flags |= (TXD_FLAG_CPU_PRE_DMA |
2644 - TXD_FLAG_CPU_POST_DMA);
2646 - tcp_hdr(skb)->check = 0;
2648 - } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2649 - base_flags |= TXD_FLAG_TCPUDP_CSUM;
2652 -#if TG3_VLAN_TAG_USED
2653 - if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
2654 - base_flags |= (TXD_FLAG_VLAN |
2655 - (vlan_tx_tag_get(skb) << 16));
2658 - len = skb_headlen(skb);
2660 - /* Queue skb data, a.k.a. the main skb fragment. */
2661 - mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2662 - if (pci_dma_mapping_error(tp->pdev, mapping)) {
2663 - dev_kfree_skb(skb);
2667 - tnapi->tx_buffers[entry].skb = skb;
2668 - pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
2670 - if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
2671 - !mss && skb->len > VLAN_ETH_FRAME_LEN)
2672 - base_flags |= TXD_FLAG_JMB_PKT;
2674 - tg3_set_txd(tnapi, entry, mapping, len, base_flags,
2675 - (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
2677 - entry = NEXT_TX(entry);
2679 - /* Now loop through additional data fragments, and queue them. */
2680 - if (skb_shinfo(skb)->nr_frags > 0) {
2681 - last = skb_shinfo(skb)->nr_frags - 1;
2682 - for (i = 0; i <= last; i++) {
2683 - skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2686 - mapping = pci_map_page(tp->pdev,
2688 - frag->page_offset,
2689 - len, PCI_DMA_TODEVICE);
2690 - if (pci_dma_mapping_error(tp->pdev, mapping))
2693 - tnapi->tx_buffers[entry].skb = NULL;
2694 - pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
2697 - tg3_set_txd(tnapi, entry, mapping, len,
2698 - base_flags, (i == last) | (mss << 1));
2700 - entry = NEXT_TX(entry);
2704 - /* Packets are ready, update Tx producer idx local and on card. */
2705 - tw32_tx_mbox(tnapi->prodmbox, entry);
2707 - tnapi->tx_prod = entry;
2708 - if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
2709 - netif_tx_stop_queue(txq);
2711 - /* netif_tx_stop_queue() must be done before checking
2712 - * checking tx index in tg3_tx_avail() below, because in
2713 - * tg3_tx(), we update tx index before checking for
2714 - * netif_tx_queue_stopped().
2717 - if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
2718 - netif_tx_wake_queue(txq);
2724 - return NETDEV_TX_OK;
2728 - entry = tnapi->tx_prod;
2729 - tnapi->tx_buffers[entry].skb = NULL;
2730 - pci_unmap_single(tp->pdev,
2731 - pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
2733 - PCI_DMA_TODEVICE);
2734 - for (i = 0; i <= last; i++) {
2735 - skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2736 - entry = NEXT_TX(entry);
2738 - pci_unmap_page(tp->pdev,
2739 - pci_unmap_addr(&tnapi->tx_buffers[entry],
2741 - frag->size, PCI_DMA_TODEVICE);
2744 - dev_kfree_skb(skb);
2745 - return NETDEV_TX_OK;
2748 -static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
2749 - struct net_device *);
2750 +static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
2752 /* Use GSO to workaround a rare TSO bug that may be triggered when the
2753 * TSO header is greater than 80 bytes.
2754 @@ -5877,7 +5945,7 @@
2758 - tg3_start_xmit_dma_bug(nskb, tp->dev);
2759 + tg3_start_xmit(nskb, tp->dev);
2763 @@ -5887,10 +5955,9 @@
2766 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
2767 - * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
2768 + * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
2770 -static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
2771 - struct net_device *dev)
2772 +static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
2774 struct tg3 *tp = netdev_priv(dev);
2775 u32 len, entry, base_flags, mss;
2776 @@ -5902,7 +5969,7 @@
2778 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2779 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
2780 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
2781 + if (tg3_flag(tp, ENABLE_TSS))
2784 /* We are running in BH disabled context with netif_tx_lock
2785 @@ -5940,7 +6007,7 @@
2787 tcp_opt_len = tcp_optlen(skb);
2789 - if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
2790 + if (skb_is_gso_v6(skb)) {
2791 hdr_len = skb_headlen(skb) - ETH_HLEN;
2794 @@ -5953,13 +6020,15 @@
2797 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
2798 - (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
2799 + tg3_flag(tp, TSO_BUG))
2800 return tg3_tso_bug(tp, skb);
2802 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
2803 TXD_FLAG_CPU_POST_DMA);
2805 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
2806 + if (tg3_flag(tp, HW_TSO_1) ||
2807 + tg3_flag(tp, HW_TSO_2) ||
2808 + tg3_flag(tp, HW_TSO_3)) {
2809 tcp_hdr(skb)->check = 0;
2810 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
2812 @@ -5968,14 +6037,14 @@
2816 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
2817 + if (tg3_flag(tp, HW_TSO_3)) {
2818 mss |= (hdr_len & 0xc) << 12;
2820 base_flags |= 0x00000010;
2821 base_flags |= (hdr_len & 0x3e0) << 5;
2822 - } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
2823 + } else if (tg3_flag(tp, HW_TSO_2))
2824 mss |= hdr_len << 9;
2825 - else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
2826 + else if (tg3_flag(tp, HW_TSO_1) ||
2827 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2828 if (tcp_opt_len || iph->ihl > 5) {
2830 @@ -5992,13 +6061,14 @@
2835 #if TG3_VLAN_TAG_USED
2836 - if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
2837 + if (vlan_tx_tag_present(skb))
2838 base_flags |= (TXD_FLAG_VLAN |
2839 (vlan_tx_tag_get(skb) << 16));
2842 - if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
2843 + if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
2844 !mss && skb->len > VLAN_ETH_FRAME_LEN)
2845 base_flags |= TXD_FLAG_JMB_PKT;
2847 @@ -6015,18 +6085,18 @@
2849 would_hit_hwbug = 0;
2851 - if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
2852 + if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
2853 would_hit_hwbug = 1;
2855 - if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
2856 + if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
2857 tg3_4g_overflow_test(mapping, len))
2858 would_hit_hwbug = 1;
2860 - if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
2861 + if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
2862 tg3_40bit_overflow_test(tp, mapping, len))
2863 would_hit_hwbug = 1;
2865 - if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
2866 + if (tg3_flag(tp, 5701_DMA_BUG))
2867 would_hit_hwbug = 1;
2869 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
2870 @@ -6052,19 +6122,21 @@
2871 if (pci_dma_mapping_error(tp->pdev, mapping))
2874 - if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
2875 + if (tg3_flag(tp, SHORT_DMA_BUG) &&
2877 would_hit_hwbug = 1;
2879 - if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
2880 + if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
2881 tg3_4g_overflow_test(mapping, len))
2882 would_hit_hwbug = 1;
2884 - if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
2885 + if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
2886 tg3_40bit_overflow_test(tp, mapping, len))
2887 would_hit_hwbug = 1;
2889 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
2890 + if (tg3_flag(tp, HW_TSO_1) ||
2891 + tg3_flag(tp, HW_TSO_2) ||
2892 + tg3_flag(tp, HW_TSO_3))
2893 tg3_set_txd(tnapi, entry, mapping, len,
2894 base_flags, (i == last)|(mss << 1));
2896 @@ -6142,16 +6214,16 @@
2899 if (new_mtu > ETH_DATA_LEN) {
2900 - if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
2901 - tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
2902 + if (tg3_flag(tp, 5780_CLASS)) {
2903 + tg3_flag_clear(tp, TSO_CAPABLE);
2904 ethtool_op_set_tso(dev, 0);
2906 - tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
2907 + tg3_flag_set(tp, JUMBO_RING_ENABLE);
2910 - if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
2911 - tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
2912 - tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
2913 + if (tg3_flag(tp, 5780_CLASS))
2914 + tg3_flag_set(tp, TSO_CAPABLE);
2915 + tg3_flag_clear(tp, JUMBO_RING_ENABLE);
2919 @@ -6199,13 +6271,13 @@
2923 - if (tpr != &tp->prodring[0]) {
2924 + if (tpr != &tp->napi[0].prodring) {
2925 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2926 i = (i + 1) & tp->rx_std_ring_mask)
2927 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
2930 - if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2931 + if (tg3_flag(tp, JUMBO_CAPABLE)) {
2932 for (i = tpr->rx_jmb_cons_idx;
2933 i != tpr->rx_jmb_prod_idx;
2934 i = (i + 1) & tp->rx_jmb_ring_mask) {
2935 @@ -6221,7 +6293,7 @@
2936 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
2939 - if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2940 + if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2941 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
2942 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
2944 @@ -6245,10 +6317,10 @@
2945 tpr->rx_jmb_cons_idx = 0;
2946 tpr->rx_jmb_prod_idx = 0;
2948 - if (tpr != &tp->prodring[0]) {
2949 + if (tpr != &tp->napi[0].prodring) {
2950 memset(&tpr->rx_std_buffers[0], 0,
2951 TG3_RX_STD_BUFF_RING_SIZE(tp));
2952 - if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
2953 + if (tpr->rx_jmb_buffers)
2954 memset(&tpr->rx_jmb_buffers[0], 0,
2955 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2957 @@ -6258,7 +6330,7 @@
2958 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
2960 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
2961 - if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
2962 + if (tg3_flag(tp, 5780_CLASS) &&
2963 tp->dev->mtu > ETH_DATA_LEN)
2964 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
2965 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
2966 @@ -6291,12 +6363,12 @@
2970 - if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
2971 + if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
2974 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
2976 - if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
2977 + if (!tg3_flag(tp, JUMBO_RING_ENABLE))
2980 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
2981 @@ -6339,13 +6411,13 @@
2982 kfree(tpr->rx_jmb_buffers);
2983 tpr->rx_jmb_buffers = NULL;
2985 - pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
2986 - tpr->rx_std, tpr->rx_std_mapping);
2987 + dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
2988 + tpr->rx_std, tpr->rx_std_mapping);
2992 - pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
2993 - tpr->rx_jmb, tpr->rx_jmb_mapping);
2994 + dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
2995 + tpr->rx_jmb, tpr->rx_jmb_mapping);
2999 @@ -6358,20 +6430,23 @@
3000 if (!tpr->rx_std_buffers)
3003 - tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
3004 - &tpr->rx_std_mapping);
3005 + tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
3006 + TG3_RX_STD_RING_BYTES(tp),
3007 + &tpr->rx_std_mapping,
3012 - if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
3013 + if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
3014 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
3016 if (!tpr->rx_jmb_buffers)
3019 - tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
3020 - TG3_RX_JMB_RING_BYTES(tp),
3021 - &tpr->rx_jmb_mapping);
3022 + tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
3023 + TG3_RX_JMB_RING_BYTES(tp),
3024 + &tpr->rx_jmb_mapping,
3029 @@ -6397,7 +6472,7 @@
3030 for (j = 0; j < tp->irq_cnt; j++) {
3031 struct tg3_napi *tnapi = &tp->napi[j];
3033 - tg3_rx_prodring_free(tp, &tp->prodring[j]);
3034 + tg3_rx_prodring_free(tp, &tnapi->prodring);
3036 if (!tnapi->tx_buffers)
3038 @@ -6469,7 +6544,7 @@
3040 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3042 - if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
3043 + if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
3047 @@ -6490,7 +6565,7 @@
3048 struct tg3_napi *tnapi = &tp->napi[i];
3050 if (tnapi->tx_ring) {
3051 - pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3052 + dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
3053 tnapi->tx_ring, tnapi->tx_desc_mapping);
3054 tnapi->tx_ring = NULL;
3056 @@ -6499,28 +6574,28 @@
3057 tnapi->tx_buffers = NULL;
3059 if (tnapi->rx_rcb) {
3060 - pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3062 - tnapi->rx_rcb_mapping);
3063 + dma_free_coherent(&tp->pdev->dev,
3064 + TG3_RX_RCB_RING_BYTES(tp),
3066 + tnapi->rx_rcb_mapping);
3067 tnapi->rx_rcb = NULL;
3070 + tg3_rx_prodring_fini(tp, &tnapi->prodring);
3072 if (tnapi->hw_status) {
3073 - pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3075 - tnapi->status_mapping);
3076 + dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
3078 + tnapi->status_mapping);
3079 tnapi->hw_status = NULL;
3084 - pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3085 - tp->hw_stats, tp->stats_mapping);
3086 + dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
3087 + tp->hw_stats, tp->stats_mapping);
3088 tp->hw_stats = NULL;
3091 - for (i = 0; i < tp->irq_cnt; i++)
3092 - tg3_rx_prodring_fini(tp, &tp->prodring[i]);
3096 @@ -6531,14 +6606,10 @@
3100 - for (i = 0; i < tp->irq_cnt; i++) {
3101 - if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
3105 - tp->hw_stats = pci_alloc_consistent(tp->pdev,
3106 - sizeof(struct tg3_hw_stats),
3107 - &tp->stats_mapping);
3108 + tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
3109 + sizeof(struct tg3_hw_stats),
3110 + &tp->stats_mapping,
3115 @@ -6548,29 +6619,34 @@
3116 struct tg3_napi *tnapi = &tp->napi[i];
3117 struct tg3_hw_status *sblk;
3119 - tnapi->hw_status = pci_alloc_consistent(tp->pdev,
3120 - TG3_HW_STATUS_SIZE,
3121 - &tnapi->status_mapping);
3122 + tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
3123 + TG3_HW_STATUS_SIZE,
3124 + &tnapi->status_mapping,
3126 if (!tnapi->hw_status)
3129 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
3130 sblk = tnapi->hw_status;
3132 + if (tg3_rx_prodring_init(tp, &tnapi->prodring))
3135 /* If multivector TSS is enabled, vector 0 does not handle
3136 * tx interrupts. Don't allocate any resources for it.
3138 - if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
3139 - (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
3140 + if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
3141 + (i && tg3_flag(tp, ENABLE_TSS))) {
3142 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
3145 if (!tnapi->tx_buffers)
3148 - tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
3149 - TG3_TX_RING_BYTES,
3150 - &tnapi->tx_desc_mapping);
3151 + tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
3152 + TG3_TX_RING_BYTES,
3153 + &tnapi->tx_desc_mapping,
3155 if (!tnapi->tx_ring)
3158 @@ -6596,18 +6672,17 @@
3162 - tnapi->prodring = &tp->prodring[i];
3165 * If multivector RSS is enabled, vector 0 does not handle
3166 * rx or tx interrupts. Don't allocate any resources for it.
3168 - if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
3169 + if (!i && tg3_flag(tp, ENABLE_RSS))
3172 - tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
3173 - TG3_RX_RCB_RING_BYTES(tp),
3174 - &tnapi->rx_rcb_mapping);
3175 + tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
3176 + TG3_RX_RCB_RING_BYTES(tp),
3177 + &tnapi->rx_rcb_mapping,
3182 @@ -6631,7 +6706,7 @@
3186 - if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3187 + if (tg3_flag(tp, 5705_PLUS)) {
3191 @@ -6740,6 +6815,10 @@
3195 + /* NCSI does not support APE events */
3196 + if (tg3_flag(tp, APE_HAS_NCSI))
3199 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
3200 if (apedata != APE_SEG_SIG_MAGIC)
3202 @@ -6776,7 +6855,7 @@
3206 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
3207 + if (!tg3_flag(tp, ENABLE_APE))
3211 @@ -6791,6 +6870,8 @@
3212 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
3213 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
3214 APE_HOST_BEHAV_NO_PHYLOCK);
3215 + tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
3216 + TG3_APE_HOST_DRVR_STATE_START);
3218 event = APE_EVENT_STATUS_STATE_START;
3220 @@ -6802,6 +6883,16 @@
3222 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
3224 + if (device_may_wakeup(&tp->pdev->dev) &&
3225 + tg3_flag(tp, WOL_ENABLE)) {
3226 + tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
3227 + TG3_APE_HOST_WOL_SPEED_AUTO);
3228 + apedata = TG3_APE_HOST_DRVR_STATE_WOL;
3230 + apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
3232 + tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
3234 event = APE_EVENT_STATUS_STATE_UNLOAD;
3236 case RESET_KIND_SUSPEND:
3237 @@ -6822,7 +6913,7 @@
3238 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3239 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3241 - if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3242 + if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
3244 case RESET_KIND_INIT:
3245 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3246 @@ -6852,7 +6943,7 @@
3247 /* tp->lock is held. */
3248 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3250 - if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3251 + if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
3253 case RESET_KIND_INIT:
3254 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3255 @@ -6876,7 +6967,7 @@
3256 /* tp->lock is held. */
3257 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3259 - if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3260 + if (tg3_flag(tp, ENABLE_ASF)) {
3262 case RESET_KIND_INIT:
3263 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3264 @@ -6927,9 +7018,8 @@
3265 * of the above loop as an error, but do report the lack of
3266 * running firmware once.
3268 - if (i >= 100000 &&
3269 - !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
3270 - tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
3271 + if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
3272 + tg3_flag_set(tp, NO_FWARE_REPORTED);
3274 netdev_info(tp->dev, "No firmware running\n");
3276 @@ -6962,10 +7052,10 @@
3277 /* Set MAX PCI retry to zero. */
3278 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
3279 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
3280 - (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
3281 + tg3_flag(tp, PCIX_MODE))
3282 val |= PCISTATE_RETRY_SAME_DMA;
3283 /* Allow reads and writes to the APE register and memory space. */
3284 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
3285 + if (tg3_flag(tp, ENABLE_APE))
3286 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
3287 PCISTATE_ALLOW_APE_SHMEM_WR |
3288 PCISTATE_ALLOW_APE_PSPACE_WR;
3289 @@ -6974,7 +7064,7 @@
3290 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
3292 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
3293 - if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
3294 + if (tg3_flag(tp, PCI_EXPRESS))
3295 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
3297 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
3298 @@ -6985,7 +7075,7 @@
3301 /* Make sure PCI-X relaxed ordering bit is clear. */
3302 - if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
3303 + if (tg3_flag(tp, PCIX_MODE)) {
3306 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
3307 @@ -6995,12 +7085,12 @@
3311 - if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
3312 + if (tg3_flag(tp, 5780_CLASS)) {
3314 /* Chip reset on 5780 will reset MSI enable bit,
3315 * so need to restore it.
3317 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
3318 + if (tg3_flag(tp, USING_MSI)) {
3321 pci_read_config_word(tp->pdev,
3322 @@ -7040,7 +7130,7 @@
3323 tg3_save_pci_state(tp);
3325 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
3326 - (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
3327 + tg3_flag(tp, 5755_PLUS))
3328 tw32(GRC_FASTBOOT_PC, 0);
3331 @@ -7059,7 +7149,7 @@
3332 * at this time, but the irq handler may still be called due to irq
3333 * sharing or irqpoll.
3335 - tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
3336 + tg3_flag_set(tp, CHIP_RESETTING);
3337 for (i = 0; i < tp->irq_cnt; i++) {
3338 struct tg3_napi *tnapi = &tp->napi[i];
3339 if (tnapi->hw_status) {
3340 @@ -7082,10 +7172,10 @@
3342 val = GRC_MISC_CFG_CORECLK_RESET;
3344 - if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3345 + if (tg3_flag(tp, PCI_EXPRESS)) {
3346 /* Force PCIe 1.0a mode */
3347 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
3348 - !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
3349 + !tg3_flag(tp, 57765_PLUS) &&
3350 tr32(TG3_PCIE_PHY_TSTCTL) ==
3351 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
3352 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
3353 @@ -7103,8 +7193,7 @@
3356 /* Manage gphy power for all CPMU absent PCIe devices. */
3357 - if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
3358 - !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
3359 + if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
3360 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3362 tw32(GRC_MISC_CFG, val);
3363 @@ -7137,7 +7226,7 @@
3367 - if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
3368 + if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) {
3371 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
3372 @@ -7163,7 +7252,7 @@
3373 * Older PCIe devices only support the 128 byte
3374 * MPS setting. Enforce the restriction.
3376 - if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
3377 + if (!tg3_flag(tp, CPMU_PRESENT))
3378 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
3379 pci_write_config_word(tp->pdev,
3380 tp->pcie_cap + PCI_EXP_DEVCTL,
3381 @@ -7182,10 +7271,11 @@
3383 tg3_restore_pci_state(tp);
3385 - tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
3386 + tg3_flag_clear(tp, CHIP_RESETTING);
3387 + tg3_flag_clear(tp, ERROR_PROCESSED);
3390 - if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
3391 + if (tg3_flag(tp, 5780_CLASS))
3392 val = tr32(MEMARB_MODE);
3393 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
3395 @@ -7210,19 +7300,21 @@
3396 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
3399 + if (tg3_flag(tp, ENABLE_APE))
3400 + tp->mac_mode = MAC_MODE_APE_TX_EN |
3401 + MAC_MODE_APE_RX_EN |
3402 + MAC_MODE_TDE_ENABLE;
3404 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3405 - tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
3406 - tw32_f(MAC_MODE, tp->mac_mode);
3407 + tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3408 + val = tp->mac_mode;
3409 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
3410 - tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
3411 - tw32_f(MAC_MODE, tp->mac_mode);
3412 - } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
3413 - tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
3414 - if (tp->mac_mode & MAC_MODE_APE_TX_EN)
3415 - tp->mac_mode |= MAC_MODE_TDE_ENABLE;
3416 - tw32_f(MAC_MODE, tp->mac_mode);
3417 + tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3418 + val = tp->mac_mode;
3420 - tw32_f(MAC_MODE, 0);
3423 + tw32_f(MAC_MODE, val);
3426 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
3427 @@ -7233,28 +7325,33 @@
3431 - if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
3432 + if (tg3_flag(tp, PCI_EXPRESS) &&
3433 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
3434 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
3435 - !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
3436 + !tg3_flag(tp, 57765_PLUS)) {
3439 tw32(0x7c00, val | (1 << 25));
3442 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
3443 + val = tr32(TG3_CPMU_CLCK_ORIDE);
3444 + tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
3447 /* Reprobe ASF enable state. */
3448 - tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
3449 - tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
3450 + tg3_flag_clear(tp, ENABLE_ASF);
3451 + tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
3452 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
3453 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
3456 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
3457 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
3458 - tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
3459 + tg3_flag_set(tp, ENABLE_ASF);
3460 tp->last_event_jiffies = jiffies;
3461 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
3462 - tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
3463 + if (tg3_flag(tp, 5750_PLUS))
3464 + tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
3468 @@ -7264,8 +7361,7 @@
3469 /* tp->lock is held. */
3470 static void tg3_stop_fw(struct tg3 *tp)
3472 - if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
3473 - !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
3474 + if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
3475 /* Wait for RX cpu to ACK the previous event. */
3476 tg3_wait_for_event_ack(tp);
3478 @@ -7311,8 +7407,7 @@
3482 - BUG_ON(offset == TX_CPU_BASE &&
3483 - (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
3484 + BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3487 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3488 @@ -7347,7 +7442,7 @@
3491 /* Clear firmware's nvram arbitration. */
3492 - if (tp->tg3_flags & TG3_FLAG_NVRAM)
3493 + if (tg3_flag(tp, NVRAM))
3494 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3497 @@ -7365,15 +7460,14 @@
3498 int err, lock_err, i;
3499 void (*write_op)(struct tg3 *, u32, u32);
3501 - if (cpu_base == TX_CPU_BASE &&
3502 - (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3503 + if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3505 "%s: Trying to load TX cpu firmware which is 5705\n",
3510 - if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3511 + if (tg3_flag(tp, 5705_PLUS))
3512 write_op = tg3_write_mem;
3514 write_op = tg3_write_indirect_reg32;
3515 @@ -7459,8 +7553,6 @@
3519 -/* 5705 needs a special version of the TSO firmware. */
3521 /* tp->lock is held. */
3522 static int tg3_load_tso_firmware(struct tg3 *tp)
3524 @@ -7469,7 +7561,9 @@
3525 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3528 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3529 + if (tg3_flag(tp, HW_TSO_1) ||
3530 + tg3_flag(tp, HW_TSO_2) ||
3531 + tg3_flag(tp, HW_TSO_3))
3534 fw_data = (void *)tp->fw->data;
3535 @@ -7538,7 +7632,7 @@
3536 if (!netif_running(dev))
3539 - if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3540 + if (tg3_flag(tp, ENABLE_ASF)) {
3541 u32 addr0_high, addr0_low, addr1_high, addr1_low;
3543 addr0_high = tr32(MAC_ADDR_0_HIGH);
3544 @@ -7573,7 +7667,7 @@
3545 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
3548 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
3549 + if (!tg3_flag(tp, 5705_PLUS))
3551 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
3553 @@ -7584,7 +7678,7 @@
3557 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
3558 + if (!tg3_flag(tp, ENABLE_TSS)) {
3559 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
3560 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
3561 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
3562 @@ -7594,7 +7688,7 @@
3563 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
3566 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
3567 + if (!tg3_flag(tp, ENABLE_RSS)) {
3568 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
3569 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
3570 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
3571 @@ -7604,7 +7698,7 @@
3572 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
3575 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3576 + if (!tg3_flag(tp, 5705_PLUS)) {
3577 u32 val = ec->stats_block_coalesce_usecs;
3579 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
3580 @@ -7626,7 +7720,7 @@
3581 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
3582 tw32(reg, ec->rx_max_coalesced_frames_irq);
3584 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
3585 + if (tg3_flag(tp, ENABLE_TSS)) {
3586 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
3587 tw32(reg, ec->tx_coalesce_usecs);
3588 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
3589 @@ -7641,7 +7735,7 @@
3590 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
3591 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
3593 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
3594 + if (tg3_flag(tp, ENABLE_TSS)) {
3595 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
3596 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
3597 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
3598 @@ -7657,8 +7751,10 @@
3599 struct tg3_napi *tnapi = &tp->napi[0];
3601 /* Disable all transmit rings but the first. */
3602 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
3603 + if (!tg3_flag(tp, 5705_PLUS))
3604 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
3605 + else if (tg3_flag(tp, 5717_PLUS))
3606 + limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
3607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
3608 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
3610 @@ -7671,10 +7767,9 @@
3613 /* Disable all receive return rings but the first. */
3614 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
3615 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
3616 + if (tg3_flag(tp, 5717_PLUS))
3617 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
3618 - else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
3619 + else if (!tg3_flag(tp, 5705_PLUS))
3620 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
3621 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
3622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
3623 @@ -7689,18 +7784,24 @@
3625 /* Disable interrupts */
3626 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
3627 + tp->napi[0].chk_msi_cnt = 0;
3628 + tp->napi[0].last_rx_cons = 0;
3629 + tp->napi[0].last_tx_cons = 0;
3631 /* Zero mailbox registers. */
3632 - if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
3633 - for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
3634 + if (tg3_flag(tp, SUPPORT_MSIX)) {
3635 + for (i = 1; i < tp->irq_max; i++) {
3636 tp->napi[i].tx_prod = 0;
3637 tp->napi[i].tx_cons = 0;
3638 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
3639 + if (tg3_flag(tp, ENABLE_TSS))
3640 tw32_mailbox(tp->napi[i].prodmbox, 0);
3641 tw32_rx_mbox(tp->napi[i].consmbox, 0);
3642 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
3643 + tp->napi[0].chk_msi_cnt = 0;
3644 + tp->napi[i].last_rx_cons = 0;
3645 + tp->napi[i].last_tx_cons = 0;
3647 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
3648 + if (!tg3_flag(tp, ENABLE_TSS))
3649 tw32_mailbox(tp->napi[0].prodmbox, 0);
3651 tp->napi[0].tx_prod = 0;
3652 @@ -7710,7 +7811,7 @@
3655 /* Make sure the NIC-based send BD rings are disabled. */
3656 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3657 + if (!tg3_flag(tp, 5705_PLUS)) {
3658 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
3659 for (i = 0; i < 16; i++)
3660 tw32_tx_mbox(mbox + i * 8, 0);
3661 @@ -7770,12 +7871,53 @@
3665 +static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
3667 + u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
3669 + if (!tg3_flag(tp, 5750_PLUS) ||
3670 + tg3_flag(tp, 5780_CLASS) ||
3671 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
3672 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
3673 + bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
3674 + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
3675 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
3676 + bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
3678 + bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
3680 + nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
3681 + host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
3683 + val = min(nic_rep_thresh, host_rep_thresh);
3684 + tw32(RCVBDI_STD_THRESH, val);
3686 + if (tg3_flag(tp, 57765_PLUS))
3687 + tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
3689 + if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
3692 + if (!tg3_flag(tp, 5705_PLUS))
3693 + bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
3695 + bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
3697 + host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
3699 + val = min(bdcache_maxcnt / 2, host_rep_thresh);
3700 + tw32(RCVBDI_JUMBO_THRESH, val);
3702 + if (tg3_flag(tp, 57765_PLUS))
3703 + tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
3706 /* tp->lock is held. */
3707 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
3709 u32 val, rdmac_mode;
3711 - struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
3712 + struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
3714 tg3_disable_ints(tp);
3716 @@ -7783,7 +7925,7 @@
3718 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
3720 - if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
3721 + if (tg3_flag(tp, INIT_COMPLETE))
3722 tg3_abort_hw(tp, 1);
3724 /* Enable MAC control of LPI */
3725 @@ -7803,7 +7945,7 @@
3726 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
3727 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
3729 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
3730 + if (tg3_flag(tp, ENABLE_APE))
3731 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
3733 tw32_f(TG3_CPMU_EEE_MODE, val);
3734 @@ -7813,7 +7955,7 @@
3735 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
3737 tw32_f(TG3_CPMU_EEE_DBTMR2,
3738 - TG3_CPMU_DBTMR1_APE_TX_2047US |
3739 + TG3_CPMU_DBTMR2_APE_TX_2047US |
3740 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
3743 @@ -7862,7 +8004,7 @@
3744 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
3747 - if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
3748 + if (tg3_flag(tp, L1PLLPD_EN)) {
3749 u32 grc_mode = tr32(GRC_MODE);
3751 /* Access the lower 1K of PL PCIE block registers. */
3752 @@ -7892,6 +8034,22 @@
3753 tw32(GRC_MODE, grc_mode);
3756 + if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
3757 + u32 grc_mode = tr32(GRC_MODE);
3759 + /* Access the lower 1K of DL PCIE block registers. */
3760 + val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
3761 + tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
3763 + val = tr32(TG3_PCIE_TLDLPL_PORT +
3764 + TG3_PCIE_DL_LO_FTSMAX);
3765 + val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
3766 + tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
3767 + val | TG3_PCIE_DL_LO_FTSMAX_VAL);
3769 + tw32(GRC_MODE, grc_mode);
3772 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
3773 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
3774 val |= CPMU_LSPD_10MB_MACCLK_6_25;
3775 @@ -7903,20 +8061,20 @@
3776 * other revision. But do not set this on PCI Express
3777 * chips and don't even touch the clocks if the CPMU is present.
3779 - if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
3780 - if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
3781 + if (!tg3_flag(tp, CPMU_PRESENT)) {
3782 + if (!tg3_flag(tp, PCI_EXPRESS))
3783 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
3784 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
3787 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
3788 - (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
3789 + tg3_flag(tp, PCIX_MODE)) {
3790 val = tr32(TG3PCI_PCISTATE);
3791 val |= PCISTATE_RETRY_SAME_DMA;
3792 tw32(TG3PCI_PCISTATE, val);
3795 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
3796 + if (tg3_flag(tp, ENABLE_APE)) {
3797 /* Allow reads and writes to the
3798 * APE register and memory space.
3800 @@ -7943,11 +8101,14 @@
3804 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
3805 + if (tg3_flag(tp, 57765_PLUS)) {
3806 val = tr32(TG3PCI_DMA_RW_CTRL) &
3807 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
3808 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
3809 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
3810 + if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
3811 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
3812 + val |= DMA_RWCTRL_TAGGED_STAT_WA;
3813 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
3814 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
3815 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
3816 @@ -7982,7 +8143,7 @@
3817 tw32(GRC_MISC_CFG, val);
3819 /* Initialize MBUF/DESC pool. */
3820 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
3821 + if (tg3_flag(tp, 5750_PLUS)) {
3823 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
3824 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
3825 @@ -7992,7 +8153,7 @@
3826 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
3827 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
3828 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
3829 - } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
3830 + } else if (tg3_flag(tp, TSO_CAPABLE)) {
3833 fw_len = tp->fw_len;
3834 @@ -8026,6 +8187,10 @@
3835 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
3836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
3837 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
3838 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
3839 + tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
3840 + tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
3841 + val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
3842 tw32(BUFMGR_MODE, val);
3843 for (i = 0; i < 2000; i++) {
3844 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
3845 @@ -8037,21 +8202,10 @@
3849 - /* Setup replenish threshold. */
3850 - val = tp->rx_pending / 8;
3853 - else if (val > tp->rx_std_max_post)
3854 - val = tp->rx_std_max_post;
3855 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3856 - if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
3857 - tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
3859 - if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
3860 - val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
3862 + if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
3863 + tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
3865 - tw32(RCVBDI_STD_THRESH, val);
3866 + tg3_setup_rxbd_thresholds(tp);
3868 /* Initialize TG3_BDINFO's at:
3869 * RCVDBDI_STD_BD: standard eth size rx ring
3870 @@ -8074,33 +8228,31 @@
3871 ((u64) tpr->rx_std_mapping >> 32));
3872 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
3873 ((u64) tpr->rx_std_mapping & 0xffffffff));
3874 - if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
3875 - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
3876 + if (!tg3_flag(tp, 5717_PLUS))
3877 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
3878 NIC_SRAM_RX_BUFFER_DESC);
3880 /* Disable the mini ring */
3881 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
3882 + if (!tg3_flag(tp, 5705_PLUS))
3883 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
3884 BDINFO_FLAGS_DISABLED);
3886 /* Program the jumbo buffer descriptor ring control
3887 * blocks on those devices that have them.
3889 - if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
3890 - !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
3891 - /* Setup replenish threshold. */
3892 - tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
3893 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
3894 + (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
3896 - if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3897 + if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
3898 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
3899 ((u64) tpr->rx_jmb_mapping >> 32));
3900 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
3901 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
3902 + val = TG3_RX_JMB_RING_SIZE(tp) <<
3903 + BDINFO_FLAGS_MAXLEN_SHIFT;
3904 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
3905 - (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
3906 - BDINFO_FLAGS_USE_EXT_RECV);
3907 - if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
3908 + val | BDINFO_FLAGS_USE_EXT_RECV);
3909 + if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
3910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
3911 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
3912 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
3913 @@ -8109,32 +8261,27 @@
3914 BDINFO_FLAGS_DISABLED);
3917 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
3918 + if (tg3_flag(tp, 57765_PLUS)) {
3919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
3920 - val = RX_STD_MAX_SIZE_5705;
3921 + val = TG3_RX_STD_MAX_SIZE_5700;
3923 - val = RX_STD_MAX_SIZE_5717;
3924 + val = TG3_RX_STD_MAX_SIZE_5717;
3925 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
3926 val |= (TG3_RX_STD_DMA_SZ << 2);
3928 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
3930 - val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
3931 + val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
3933 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
3935 tpr->rx_std_prod_idx = tp->rx_pending;
3936 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
3938 - tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
3939 - tp->rx_jumbo_pending : 0;
3940 + tpr->rx_jmb_prod_idx =
3941 + tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
3942 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
3944 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
3945 - tw32(STD_REPLENISH_LWM, 32);
3946 - tw32(JMB_REPLENISH_LWM, 16);
3949 tg3_rings_reset(tp);
3951 /* Initialize MAC address and backoff seed. */
3952 @@ -8147,10 +8294,16 @@
3953 /* The slot time is changed by tg3_setup_phy if we
3954 * run at gigabit with half duplex.
3956 - tw32(MAC_TX_LENGTHS,
3957 - (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3958 - (6 << TX_LENGTHS_IPG_SHIFT) |
3959 - (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
3960 + val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3961 + (6 << TX_LENGTHS_IPG_SHIFT) |
3962 + (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
3964 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
3965 + val |= tr32(MAC_TX_LENGTHS) &
3966 + (TX_LENGTHS_JMB_FRM_LEN_MSK |
3967 + TX_LENGTHS_CNT_DWN_VAL_MSK);
3969 + tw32(MAC_TX_LENGTHS, val);
3971 /* Receive rules. */
3972 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
3973 @@ -8175,45 +8328,54 @@
3974 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
3975 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
3977 - /* If statement applies to 5705 and 5750 PCI devices only */
3978 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
3979 - tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
3980 - (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
3981 - if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
3982 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
3983 + tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
3984 + if (tg3_flag(tp, TSO_CAPABLE) &&
3985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3986 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
3987 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
3988 - !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
3989 + !tg3_flag(tp, IS_5788)) {
3990 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
3994 - if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
3995 + if (tg3_flag(tp, PCI_EXPRESS))
3996 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
3998 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3999 + if (tg3_flag(tp, HW_TSO_1) ||
4000 + tg3_flag(tp, HW_TSO_2) ||
4001 + tg3_flag(tp, HW_TSO_3))
4002 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
4004 - if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
4005 + if (tg3_flag(tp, 57765_PLUS) ||
4006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
4007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
4008 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
4010 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4011 + rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
4013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
4014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
4015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
4016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
4017 - (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
4018 + tg3_flag(tp, 57765_PLUS)) {
4019 val = tr32(TG3_RDMA_RSRVCTRL_REG);
4020 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
4021 - val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
4022 - val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
4023 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
4024 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
4025 + val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
4026 + TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
4027 + TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
4028 + val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
4029 + TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
4030 + TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
4032 tw32(TG3_RDMA_RSRVCTRL_REG,
4033 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
4036 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
4037 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
4038 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
4039 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
4040 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
4041 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
4042 @@ -8221,12 +8383,12 @@
4045 /* Receive/send statistics. */
4046 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
4047 + if (tg3_flag(tp, 5750_PLUS)) {
4048 val = tr32(RCVLPC_STATS_ENABLE);
4049 val &= ~RCVLPC_STATSENAB_DACK_FIX;
4050 tw32(RCVLPC_STATS_ENABLE, val);
4051 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
4052 - (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
4053 + tg3_flag(tp, TSO_CAPABLE)) {
4054 val = tr32(RCVLPC_STATS_ENABLE);
4055 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
4056 tw32(RCVLPC_STATS_ENABLE, val);
4057 @@ -8249,7 +8411,7 @@
4059 __tg3_set_coalesce(tp, &tp->coal);
4061 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4062 + if (!tg3_flag(tp, 5705_PLUS)) {
4063 /* Status/statistics block address. See tg3_timer,
4064 * the tg3_periodic_fetch_stats call there, and
4065 * tg3_get_stats to see how this works for 5705/5750 chips.
4066 @@ -8275,7 +8437,7 @@
4068 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
4069 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
4070 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4071 + if (!tg3_flag(tp, 5705_PLUS))
4072 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
4074 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
4075 @@ -8285,13 +8447,13 @@
4079 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
4080 - tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
4081 + if (tg3_flag(tp, ENABLE_APE))
4082 + tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
4085 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
4086 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
4087 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
4088 + if (!tg3_flag(tp, 5705_PLUS) &&
4089 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4090 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
4091 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4092 @@ -8299,12 +8461,12 @@
4095 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
4096 - * If TG3_FLG2_IS_NIC is zero, we should read the
4097 + * If TG3_FLAG_IS_NIC is zero, we should read the
4098 * register to preserve the GPIO settings for LOMs. The GPIOs,
4099 * whether used as inputs or outputs, are set by boot code after
4102 - if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
4103 + if (!tg3_flag(tp, IS_NIC)) {
4106 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
4107 @@ -8322,20 +8484,20 @@
4108 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
4110 /* GPIO1 must be driven high for eeprom write protect */
4111 - if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
4112 + if (tg3_flag(tp, EEPROM_WRITE_PROT))
4113 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
4114 GRC_LCLCTRL_GPIO_OUTPUT1);
4116 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
4119 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
4120 + if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
4121 val = tr32(MSGINT_MODE);
4122 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
4123 tw32(MSGINT_MODE, val);
4126 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4127 + if (!tg3_flag(tp, 5705_PLUS)) {
4128 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
4131 @@ -8346,23 +8508,20 @@
4132 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
4133 WDMAC_MODE_LNGREAD_ENAB);
4135 - /* If statement applies to 5705 and 5750 PCI devices only */
4136 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
4137 - tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
4138 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
4139 - if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
4140 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
4141 + tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
4142 + if (tg3_flag(tp, TSO_CAPABLE) &&
4143 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
4144 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
4146 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
4147 - !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
4148 - !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
4149 + !tg3_flag(tp, IS_5788)) {
4150 val |= WDMAC_MODE_RX_ACCEL;
4154 /* Enable host coalescing bug fix */
4155 - if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
4156 + if (tg3_flag(tp, 5755_PLUS))
4157 val |= WDMAC_MODE_STATUS_TAG_FIX;
4159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
4160 @@ -8371,7 +8530,7 @@
4161 tw32_f(WDMAC_MODE, val);
4164 - if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
4165 + if (tg3_flag(tp, PCIX_MODE)) {
4168 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
4169 @@ -8391,7 +8550,7 @@
4172 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
4173 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4174 + if (!tg3_flag(tp, 5705_PLUS))
4175 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
4177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
4178 @@ -8403,15 +8562,16 @@
4179 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
4180 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
4181 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
4182 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
4183 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
4184 + if (tg3_flag(tp, LRG_PROD_RING_CAP))
4185 val |= RCVDBDI_MODE_LRG_RING_SZ;
4186 tw32(RCVDBDI_MODE, val);
4187 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
4188 - if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4189 + if (tg3_flag(tp, HW_TSO_1) ||
4190 + tg3_flag(tp, HW_TSO_2) ||
4191 + tg3_flag(tp, HW_TSO_3))
4192 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
4193 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
4194 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4195 + if (tg3_flag(tp, ENABLE_TSS))
4196 val |= SNDBDI_MODE_MULTI_TXQ_EN;
4197 tw32(SNDBDI_MODE, val);
4198 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
4199 @@ -8422,20 +8582,28 @@
4203 - if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
4204 + if (tg3_flag(tp, TSO_CAPABLE)) {
4205 err = tg3_load_tso_firmware(tp);
4210 tp->tx_mode = TX_MODE_ENABLE;
4211 - if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
4213 + if (tg3_flag(tp, 5755_PLUS) ||
4214 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
4215 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
4217 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
4218 + val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
4219 + tp->tx_mode &= ~val;
4220 + tp->tx_mode |= tr32(MAC_TX_MODE) & val;
4223 tw32_f(MAC_TX_MODE, tp->tx_mode);
4226 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
4227 + if (tg3_flag(tp, ENABLE_RSS)) {
4228 u32 reg = MAC_RSS_INDIR_TBL_0;
4229 u8 *ent = (u8 *)&val;
4231 @@ -8464,10 +8632,10 @@
4234 tp->rx_mode = RX_MODE_ENABLE;
4235 - if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
4236 + if (tg3_flag(tp, 5755_PLUS))
4237 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
4239 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
4240 + if (tg3_flag(tp, ENABLE_RSS))
4241 tp->rx_mode |= RX_MODE_RSS_ENABLE |
4242 RX_MODE_RSS_ITBL_HASH_BITS_7 |
4243 RX_MODE_RSS_IPV6_HASH_EN |
4244 @@ -8514,11 +8682,11 @@
4245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
4246 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4247 /* Use hardware link auto-negotiation */
4248 - tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
4249 + tg3_flag_set(tp, HW_AUTONEG);
4252 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4253 - (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
4254 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4257 tmp = tr32(SERDES_RX_CTRL);
4258 @@ -8528,7 +8696,7 @@
4259 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
4262 - if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
4263 + if (!tg3_flag(tp, USE_PHYLIB)) {
4264 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
4265 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
4266 tp->link_config.speed = tp->link_config.orig_speed;
4267 @@ -8561,12 +8729,11 @@
4268 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
4269 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
4271 - if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
4272 - !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4273 + if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
4277 - if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
4278 + if (tg3_flag(tp, ENABLE_ASF))
4282 @@ -8604,7 +8771,7 @@
4286 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
4287 + if (tg3_flag(tp, ENABLE_APE))
4288 /* Write our heartbeat update interval to APE. */
4289 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
4290 APE_HOST_HEARTBEAT_INT_DISABLE);
4291 @@ -8670,10 +8837,48 @@
4292 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
4294 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4295 - TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
4296 + if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
4297 + tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
4298 + tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
4299 + TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
4301 + u32 val = tr32(HOSTCC_FLOW_ATTN);
4302 + val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
4304 + tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
4305 + sp->rx_discards.low += val;
4306 + if (sp->rx_discards.low < val)
4307 + sp->rx_discards.high += 1;
4309 + sp->mbuf_lwm_thresh_hit = sp->rx_discards;
4311 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
4314 +static void tg3_chk_missed_msi(struct tg3 *tp)
4318 + for (i = 0; i < tp->irq_cnt; i++) {
4319 + struct tg3_napi *tnapi = &tp->napi[i];
4321 + if (tg3_has_work(tnapi)) {
4322 + if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
4323 + tnapi->last_tx_cons == tnapi->tx_cons) {
4324 + if (tnapi->chk_msi_cnt < 1) {
4325 + tnapi->chk_msi_cnt++;
4328 + tw32_mailbox(tnapi->int_mbox,
4329 + tnapi->last_tag << 24);
4332 + tnapi->chk_msi_cnt = 0;
4333 + tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
4334 + tnapi->last_tx_cons = tnapi->tx_cons;
4338 static void tg3_timer(unsigned long __opaque)
4340 struct tg3 *tp = (struct tg3 *) __opaque;
4341 @@ -8683,7 +8888,11 @@
4343 spin_lock(&tp->lock);
4345 - if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
4346 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
4347 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
4348 + tg3_chk_missed_msi(tp);
4350 + if (!tg3_flag(tp, TAGGED_STATUS)) {
4351 /* All of this garbage is because when using non-tagged
4352 * IRQ status the mailbox/status_block protocol the chip
4353 * uses with the cpu is race prone.
4354 @@ -8697,7 +8906,7 @@
4357 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
4358 - tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
4359 + tg3_flag_set(tp, RESTART_TIMER);
4360 spin_unlock(&tp->lock);
4361 schedule_work(&tp->reset_task);
4363 @@ -8706,16 +8915,13 @@
4365 /* This part only runs once per second. */
4366 if (!--tp->timer_counter) {
4367 - if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4368 + if (tg3_flag(tp, 5705_PLUS))
4369 tg3_periodic_fetch_stats(tp);
4371 - if (tp->setlpicnt && !--tp->setlpicnt) {
4372 - u32 val = tr32(TG3_CPMU_EEE_MODE);
4373 - tw32(TG3_CPMU_EEE_MODE,
4374 - val | TG3_CPMU_EEEMD_LPI_ENABLE);
4376 + if (tp->setlpicnt && !--tp->setlpicnt)
4377 + tg3_phy_eee_enable(tp);
4379 - if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
4380 + if (tg3_flag(tp, USE_LINKCHG_REG)) {
4384 @@ -8730,7 +8936,7 @@
4387 tg3_setup_phy(tp, 0);
4388 - } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
4389 + } else if (tg3_flag(tp, POLL_SERDES)) {
4390 u32 mac_stat = tr32(MAC_STATUS);
4393 @@ -8755,7 +8961,7 @@
4394 tg3_setup_phy(tp, 0);
4396 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4397 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4398 + tg3_flag(tp, 5780_CLASS)) {
4399 tg3_serdes_parallel_detect(tp);
4402 @@ -8780,8 +8986,7 @@
4405 if (!--tp->asf_counter) {
4406 - if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
4407 - !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
4408 + if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
4409 tg3_wait_for_event_ack(tp);
4411 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
4412 @@ -8817,16 +9022,16 @@
4413 name[IFNAMSIZ-1] = 0;
4416 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
4417 + if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
4419 - if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
4420 + if (tg3_flag(tp, 1SHOT_MSI))
4422 - flags = IRQF_SAMPLE_RANDOM;
4426 - if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
4427 + if (tg3_flag(tp, TAGGED_STATUS))
4428 fn = tg3_interrupt_tagged;
4429 - flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
4430 + flags = IRQF_SHARED;
4433 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
4434 @@ -8850,8 +9055,7 @@
4435 * Turn off MSI one shot mode. Otherwise this test has no
4436 * observable way to know whether the interrupt was delivered.
4438 - if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
4439 - (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
4440 + if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
4441 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
4442 tw32(MSGINT_MODE, val);
4444 @@ -8893,8 +9097,7 @@
4447 /* Reenable MSI one shot mode. */
4448 - if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
4449 - (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
4450 + if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
4451 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
4452 tw32(MSGINT_MODE, val);
4454 @@ -8912,7 +9115,7 @@
4458 - if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
4459 + if (!tg3_flag(tp, USING_MSI))
4462 /* Turn off SERR reporting in case MSI terminates with Master
4463 @@ -8942,7 +9145,7 @@
4465 pci_disable_msi(tp->pdev);
4467 - tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
4468 + tg3_flag_clear(tp, USING_MSI);
4469 tp->napi[0].irq_vec = tp->pdev->irq;
4471 err = tg3_request_irq(tp, 0);
4472 @@ -9031,11 +9234,13 @@
4473 for (i = 0; i < tp->irq_max; i++)
4474 tp->napi[i].irq_vec = msix_ent[i].vector;
4476 - tp->dev->real_num_tx_queues = 1;
4477 + netif_set_real_num_tx_queues(tp->dev, 1);
4478 if (tp->irq_cnt > 1) {
4479 - tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
4480 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
4481 - tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
4482 + tg3_flag_set(tp, ENABLE_RSS);
4484 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
4485 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
4486 + tg3_flag_set(tp, ENABLE_TSS);
4487 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
4490 @@ -9045,8 +9250,8 @@
4492 static void tg3_ints_init(struct tg3 *tp)
4494 - if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
4495 - !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
4496 + if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
4497 + !tg3_flag(tp, TAGGED_STATUS)) {
4498 /* All MSI supporting chips should support tagged
4499 * status. Assert that this is the case.
4501 @@ -9055,34 +9260,35 @@
4505 - if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
4506 - tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
4507 - else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
4508 - pci_enable_msi(tp->pdev) == 0)
4509 - tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
4510 + if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
4511 + tg3_flag_set(tp, USING_MSIX);
4512 + else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
4513 + tg3_flag_set(tp, USING_MSI);
4515 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
4516 + if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
4517 u32 msi_mode = tr32(MSGINT_MODE);
4518 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4519 + if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
4520 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
4521 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
4524 - if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
4525 + if (!tg3_flag(tp, USING_MSIX)) {
4527 tp->napi[0].irq_vec = tp->pdev->irq;
4528 - tp->dev->real_num_tx_queues = 1;
4529 + netif_set_real_num_tx_queues(tp->dev, 1);
4533 static void tg3_ints_fini(struct tg3 *tp)
4535 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4536 + if (tg3_flag(tp, USING_MSIX))
4537 pci_disable_msix(tp->pdev);
4538 - else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
4539 + else if (tg3_flag(tp, USING_MSI))
4540 pci_disable_msi(tp->pdev);
4541 - tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
4542 - tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
4543 + tg3_flag_clear(tp, USING_MSI);
4544 + tg3_flag_clear(tp, USING_MSIX);
4545 + tg3_flag_clear(tp, ENABLE_RSS);
4546 + tg3_flag_clear(tp, ENABLE_TSS);
4549 static int tg3_open(struct net_device *dev)
4550 @@ -9097,23 +9303,23 @@
4553 netdev_warn(tp->dev, "TSO capability disabled\n");
4554 - tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4555 - } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
4556 + tg3_flag_clear(tp, TSO_CAPABLE);
4557 + } else if (!tg3_flag(tp, TSO_CAPABLE)) {
4558 netdev_notice(tp->dev, "TSO capability restored\n");
4559 - tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4560 + tg3_flag_set(tp, TSO_CAPABLE);
4564 netif_carrier_off(tp->dev);
4566 - err = tg3_set_power_state(tp, PCI_D0);
4567 + err = tg3_power_up(tp);
4571 tg3_full_lock(tp, 0);
4573 tg3_disable_ints(tp);
4574 - tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
4575 + tg3_flag_clear(tp, INIT_COMPLETE);
4577 tg3_full_unlock(tp);
4579 @@ -9130,6 +9336,8 @@
4583 + tg3_napi_init(tp);
4585 tg3_napi_enable(tp);
4587 for (i = 0; i < tp->irq_cnt; i++) {
4588 @@ -9152,7 +9360,9 @@
4589 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4592 - if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
4593 + if (tg3_flag(tp, TAGGED_STATUS) &&
4594 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
4595 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
4596 tp->timer_offset = HZ;
4598 tp->timer_offset = HZ / 10;
4599 @@ -9174,7 +9384,7 @@
4603 - if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4604 + if (tg3_flag(tp, USING_MSI)) {
4605 err = tg3_test_msi(tp);
4608 @@ -9186,8 +9396,7 @@
4612 - if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
4613 - (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
4614 + if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
4615 u32 val = tr32(PCIE_TRANSACTION_CFG);
4617 tw32(PCIE_TRANSACTION_CFG,
4618 @@ -9200,7 +9409,7 @@
4619 tg3_full_lock(tp, 0);
4621 add_timer(&tp->timer);
4622 - tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
4623 + tg3_flag_set(tp, INIT_COMPLETE);
4624 tg3_enable_ints(tp);
4626 tg3_full_unlock(tp);
4627 @@ -9217,6 +9426,7 @@
4630 tg3_napi_disable(tp);
4631 + tg3_napi_fini(tp);
4632 tg3_free_consistent(tp);
4635 @@ -9247,7 +9457,7 @@
4637 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4639 - tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
4640 + tg3_flag_clear(tp, INIT_COMPLETE);
4642 tg3_full_unlock(tp);
4644 @@ -9263,9 +9473,11 @@
4645 memcpy(&tp->estats_prev, tg3_get_estats(tp),
4646 sizeof(tp->estats_prev));
4648 + tg3_napi_fini(tp);
4650 tg3_free_consistent(tp);
4652 - tg3_set_power_state(tp, PCI_D3hot);
4653 + tg3_power_down(tp);
4655 netif_carrier_off(tp->dev);
4657 @@ -9404,6 +9616,8 @@
4658 ESTAT_ADD(nic_avoided_irqs);
4659 ESTAT_ADD(nic_tx_threshold_hit);
4661 + ESTAT_ADD(mbuf_lwm_thresh_hit);
4666 @@ -9513,13 +9727,13 @@
4668 #if TG3_VLAN_TAG_USED
4670 - !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
4671 + !tg3_flag(tp, ENABLE_ASF))
4672 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
4674 /* By definition, VLAN is disabled always in this
4677 - if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
4678 + if (!tg3_flag(tp, ENABLE_ASF))
4679 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
4682 @@ -9573,82 +9787,26 @@
4683 tg3_full_unlock(tp);
4686 -#define TG3_REGDUMP_LEN (32 * 1024)
4688 static int tg3_get_regs_len(struct net_device *dev)
4690 - return TG3_REGDUMP_LEN;
4691 + return TG3_REG_BLK_SIZE;
4694 static void tg3_get_regs(struct net_device *dev,
4695 struct ethtool_regs *regs, void *_p)
4698 struct tg3 *tp = netdev_priv(dev);
4704 - memset(p, 0, TG3_REGDUMP_LEN);
4705 + memset(_p, 0, TG3_REG_BLK_SIZE);
4707 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
4710 tg3_full_lock(tp, 0);
4712 -#define __GET_REG32(reg) (*(p)++ = tr32(reg))
4713 -#define GET_REG32_LOOP(base, len) \
4714 -do { p = (u32 *)(orig_p + (base)); \
4715 - for (i = 0; i < len; i += 4) \
4716 - __GET_REG32((base) + i); \
4718 -#define GET_REG32_1(reg) \
4719 -do { p = (u32 *)(orig_p + (reg)); \
4720 - __GET_REG32((reg)); \
4723 - GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
4724 - GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
4725 - GET_REG32_LOOP(MAC_MODE, 0x4f0);
4726 - GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
4727 - GET_REG32_1(SNDDATAC_MODE);
4728 - GET_REG32_LOOP(SNDBDS_MODE, 0x80);
4729 - GET_REG32_LOOP(SNDBDI_MODE, 0x48);
4730 - GET_REG32_1(SNDBDC_MODE);
4731 - GET_REG32_LOOP(RCVLPC_MODE, 0x20);
4732 - GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
4733 - GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
4734 - GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
4735 - GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
4736 - GET_REG32_1(RCVDCC_MODE);
4737 - GET_REG32_LOOP(RCVBDI_MODE, 0x20);
4738 - GET_REG32_LOOP(RCVCC_MODE, 0x14);
4739 - GET_REG32_LOOP(RCVLSC_MODE, 0x08);
4740 - GET_REG32_1(MBFREE_MODE);
4741 - GET_REG32_LOOP(HOSTCC_MODE, 0x100);
4742 - GET_REG32_LOOP(MEMARB_MODE, 0x10);
4743 - GET_REG32_LOOP(BUFMGR_MODE, 0x58);
4744 - GET_REG32_LOOP(RDMAC_MODE, 0x08);
4745 - GET_REG32_LOOP(WDMAC_MODE, 0x08);
4746 - GET_REG32_1(RX_CPU_MODE);
4747 - GET_REG32_1(RX_CPU_STATE);
4748 - GET_REG32_1(RX_CPU_PGMCTR);
4749 - GET_REG32_1(RX_CPU_HWBKPT);
4750 - GET_REG32_1(TX_CPU_MODE);
4751 - GET_REG32_1(TX_CPU_STATE);
4752 - GET_REG32_1(TX_CPU_PGMCTR);
4753 - GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
4754 - GET_REG32_LOOP(FTQ_RESET, 0x120);
4755 - GET_REG32_LOOP(MSGINT_MODE, 0x0c);
4756 - GET_REG32_1(DMAC_MODE);
4757 - GET_REG32_LOOP(GRC_MODE, 0x4c);
4758 - if (tp->tg3_flags & TG3_FLAG_NVRAM)
4759 - GET_REG32_LOOP(NVRAM_CMD, 0x24);
4762 -#undef GET_REG32_LOOP
4764 + tg3_dump_legacy_regs(tp, (u32 *)_p);
4766 tg3_full_unlock(tp);
4768 @@ -9668,7 +9826,7 @@
4769 u32 i, offset, len, b_offset, b_count;
4772 - if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
4773 + if (tg3_flag(tp, NO_NVRAM))
4776 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
4777 @@ -9697,7 +9855,7 @@
4778 eeprom->len += b_count;
4781 - /* read bytes upto the last 4 byte boundary */
4782 + /* read bytes up to the last 4 byte boundary */
4783 pd = &data[eeprom->len];
4784 for (i = 0; i < (len - (len & 3)); i += 4) {
4785 ret = tg3_nvram_read_be32(tp, offset + i, &val);
4786 @@ -9736,7 +9894,7 @@
4787 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
4790 - if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
4791 + if (tg3_flag(tp, NO_NVRAM) ||
4792 eeprom->magic != TG3_EEPROM_MAGIC)
4795 @@ -9788,7 +9946,7 @@
4797 struct tg3 *tp = netdev_priv(dev);
4799 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4800 + if (tg3_flag(tp, USE_PHYLIB)) {
4801 struct phy_device *phydev;
4802 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
4804 @@ -9816,8 +9974,11 @@
4806 cmd->advertising = tp->link_config.advertising;
4807 if (netif_running(dev)) {
4808 - cmd->speed = tp->link_config.active_speed;
4809 + ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
4810 cmd->duplex = tp->link_config.active_duplex;
4812 + ethtool_cmd_speed_set(cmd, SPEED_INVALID);
4813 + cmd->duplex = DUPLEX_INVALID;
4815 cmd->phy_address = tp->phy_addr;
4816 cmd->transceiver = XCVR_INTERNAL;
4817 @@ -9830,8 +9991,9 @@
4818 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4820 struct tg3 *tp = netdev_priv(dev);
4821 + u32 speed = ethtool_cmd_speed(cmd);
4823 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4824 + if (tg3_flag(tp, USE_PHYLIB)) {
4825 struct phy_device *phydev;
4826 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
4828 @@ -9879,14 +10041,14 @@
4829 cmd->advertising &= mask;
4831 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
4832 - if (cmd->speed != SPEED_1000)
4833 + if (speed != SPEED_1000)
4836 if (cmd->duplex != DUPLEX_FULL)
4839 - if (cmd->speed != SPEED_100 &&
4840 - cmd->speed != SPEED_10)
4841 + if (speed != SPEED_100 &&
4842 + speed != SPEED_10)
4846 @@ -9901,7 +10063,7 @@
4847 tp->link_config.duplex = DUPLEX_INVALID;
4849 tp->link_config.advertising = 0;
4850 - tp->link_config.speed = cmd->speed;
4851 + tp->link_config.speed = speed;
4852 tp->link_config.duplex = cmd->duplex;
4855 @@ -9931,14 +10093,12 @@
4857 struct tg3 *tp = netdev_priv(dev);
4859 - if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
4860 - device_can_wakeup(&tp->pdev->dev))
4861 + if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
4862 wol->supported = WAKE_MAGIC;
4866 - if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
4867 - device_can_wakeup(&tp->pdev->dev))
4868 + if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
4869 wol->wolopts = WAKE_MAGIC;
4870 memset(&wol->sopass, 0, sizeof(wol->sopass));
4872 @@ -9951,17 +10111,16 @@
4873 if (wol->wolopts & ~WAKE_MAGIC)
4875 if ((wol->wolopts & WAKE_MAGIC) &&
4876 - !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
4877 + !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
4880 + device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
4882 spin_lock_bh(&tp->lock);
4883 - if (wol->wolopts & WAKE_MAGIC) {
4884 - tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
4885 - device_set_wakeup_enable(dp, true);
4887 - tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
4888 - device_set_wakeup_enable(dp, false);
4890 + if (device_may_wakeup(dp))
4891 + tg3_flag_set(tp, WOL_ENABLE);
4893 + tg3_flag_clear(tp, WOL_ENABLE);
4894 spin_unlock_bh(&tp->lock);
4897 @@ -9983,17 +10142,17 @@
4899 struct tg3 *tp = netdev_priv(dev);
4901 - if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
4902 + if (!tg3_flag(tp, TSO_CAPABLE)) {
4907 if ((dev->features & NETIF_F_IPV6_CSUM) &&
4908 - ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
4909 - (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
4910 + ((tg3_flag(tp, HW_TSO_2)) ||
4911 + (tg3_flag(tp, HW_TSO_3)))) {
4913 dev->features |= NETIF_F_TSO6;
4914 - if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
4915 + if ((tg3_flag(tp, HW_TSO_3)) ||
4916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
4917 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
4918 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
4919 @@ -10017,7 +10176,7 @@
4920 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4923 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4924 + if (tg3_flag(tp, USE_PHYLIB)) {
4925 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
4927 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
4928 @@ -10046,7 +10205,7 @@
4930 ering->rx_max_pending = tp->rx_std_ring_mask;
4931 ering->rx_mini_max_pending = 0;
4932 - if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
4933 + if (tg3_flag(tp, JUMBO_RING_ENABLE))
4934 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4936 ering->rx_jumbo_max_pending = 0;
4937 @@ -10055,7 +10214,7 @@
4939 ering->rx_pending = tp->rx_pending;
4940 ering->rx_mini_pending = 0;
4941 - if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
4942 + if (tg3_flag(tp, JUMBO_RING_ENABLE))
4943 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
4945 ering->rx_jumbo_pending = 0;
4946 @@ -10072,7 +10231,7 @@
4947 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
4948 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
4949 (ering->tx_pending <= MAX_SKB_FRAGS) ||
4950 - ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
4951 + (tg3_flag(tp, TSO_BUG) &&
4952 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
4955 @@ -10086,12 +10245,12 @@
4957 tp->rx_pending = ering->rx_pending;
4959 - if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
4960 + if (tg3_flag(tp, MAX_RXPEND_64) &&
4961 tp->rx_pending > 63)
4962 tp->rx_pending = 63;
4963 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
4965 - for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
4966 + for (i = 0; i < tp->irq_max; i++)
4967 tp->napi[i].tx_pending = ering->tx_pending;
4969 if (netif_running(dev)) {
4970 @@ -10113,7 +10272,7 @@
4972 struct tg3 *tp = netdev_priv(dev);
4974 - epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
4975 + epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
4977 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
4978 epause->rx_pause = 1;
4979 @@ -10131,7 +10290,7 @@
4980 struct tg3 *tp = netdev_priv(dev);
4983 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4984 + if (tg3_flag(tp, USE_PHYLIB)) {
4986 struct phy_device *phydev;
4988 @@ -10139,8 +10298,7 @@
4990 if (!(phydev->supported & SUPPORTED_Pause) ||
4991 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
4992 - ((epause->rx_pause && !epause->tx_pause) ||
4993 - (!epause->rx_pause && epause->tx_pause))))
4994 + (epause->rx_pause != epause->tx_pause)))
4997 tp->link_config.flowctrl = 0;
4998 @@ -10160,9 +10318,9 @@
5001 if (epause->autoneg)
5002 - tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
5003 + tg3_flag_set(tp, PAUSE_AUTONEG);
5005 - tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
5006 + tg3_flag_clear(tp, PAUSE_AUTONEG);
5008 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
5009 u32 oldadv = phydev->advertising &
5010 @@ -10204,9 +10362,9 @@
5011 tg3_full_lock(tp, irq_sync);
5013 if (epause->autoneg)
5014 - tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
5015 + tg3_flag_set(tp, PAUSE_AUTONEG);
5017 - tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
5018 + tg3_flag_clear(tp, PAUSE_AUTONEG);
5019 if (epause->rx_pause)
5020 tp->link_config.flowctrl |= FLOW_CTRL_RX;
5022 @@ -10232,14 +10390,14 @@
5023 static u32 tg3_get_rx_csum(struct net_device *dev)
5025 struct tg3 *tp = netdev_priv(dev);
5026 - return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
5027 + return (tg3_flag(tp, RX_CHECKSUMS)) != 0;
5030 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
5032 struct tg3 *tp = netdev_priv(dev);
5034 - if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
5035 + if (tg3_flag(tp, BROKEN_CHECKSUMS)) {
5039 @@ -10247,9 +10405,9 @@
5041 spin_lock_bh(&tp->lock);
5043 - tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
5044 + tg3_flag_set(tp, RX_CHECKSUMS);
5046 - tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
5047 + tg3_flag_clear(tp, RX_CHECKSUMS);
5048 spin_unlock_bh(&tp->lock);
5051 @@ -10259,13 +10417,13 @@
5053 struct tg3 *tp = netdev_priv(dev);
5055 - if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
5056 + if (tg3_flag(tp, BROKEN_CHECKSUMS)) {
5062 - if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
5063 + if (tg3_flag(tp, 5755_PLUS))
5064 ethtool_op_set_tx_ipv6_csum(dev, data);
5066 ethtool_op_set_tx_csum(dev, data);
5067 @@ -10339,10 +10497,87 @@
5068 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
5071 +static __be32 * tg3_vpd_readblock(struct tg3 *tp)
5075 + u32 offset = 0, len = 0;
5078 + if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
5081 + if (magic == TG3_EEPROM_MAGIC) {
5082 + for (offset = TG3_NVM_DIR_START;
5083 + offset < TG3_NVM_DIR_END;
5084 + offset += TG3_NVM_DIRENT_SIZE) {
5085 + if (tg3_nvram_read(tp, offset, &val))
5088 + if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
5089 + TG3_NVM_DIRTYPE_EXTVPD)
5093 + if (offset != TG3_NVM_DIR_END) {
5094 + len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
5095 + if (tg3_nvram_read(tp, offset + 4, &offset))
5098 + offset = tg3_nvram_logical_addr(tp, offset);
5102 + if (!offset || !len) {
5103 + offset = TG3_NVM_VPD_OFF;
5104 + len = TG3_NVM_VPD_LEN;
5107 + buf = kmalloc(len, GFP_KERNEL);
5111 + if (magic == TG3_EEPROM_MAGIC) {
5112 + for (i = 0; i < len; i += 4) {
5113 + /* The data is in little-endian format in NVRAM.
5114 + * Use the big-endian read routines to preserve
5115 + * the byte order as it exists in NVRAM.
5117 + if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
5123 + unsigned int pos = 0;
5125 + ptr = (u8 *)&buf[0];
5126 + for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
5127 + cnt = pci_read_vpd(tp->pdev, pos,
5129 + if (cnt == -ETIMEDOUT || cnt == -EINTR)
5145 #define NVRAM_TEST_SIZE 0x100
5146 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
5147 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
5148 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
5149 +#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
5150 +#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
5151 +#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x4c
5152 #define NVRAM_SELFBOOT_HW_SIZE 0x20
5153 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
5155 @@ -10352,7 +10587,7 @@
5157 int i, j, k, err = 0, size;
5159 - if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
5160 + if (tg3_flag(tp, NO_NVRAM))
5163 if (tg3_nvram_read(tp, 0, &magic) != 0)
5164 @@ -10373,8 +10608,17 @@
5165 case TG3_EEPROM_SB_REVISION_3:
5166 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
5168 + case TG3_EEPROM_SB_REVISION_4:
5169 + size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
5171 + case TG3_EEPROM_SB_REVISION_5:
5172 + size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
5174 + case TG3_EEPROM_SB_REVISION_6:
5175 + size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
5183 @@ -10466,16 +10710,50 @@
5189 /* Bootstrap checksum at offset 0x10 */
5190 csum = calc_crc((unsigned char *) buf, 0x10);
5191 - if (csum != be32_to_cpu(buf[0x10/4]))
5192 + if (csum != le32_to_cpu(buf[0x10/4]))
5195 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
5196 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
5197 - if (csum != be32_to_cpu(buf[0xfc/4]))
5198 + if (csum != le32_to_cpu(buf[0xfc/4]))
5203 + buf = tg3_vpd_readblock(tp);
5207 + i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
5208 + PCI_VPD_LRDT_RO_DATA);
5210 + j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
5214 + if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
5217 + i += PCI_VPD_LRDT_TAG_SIZE;
5218 + j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
5219 + PCI_VPD_RO_KEYWORD_CHKSUM);
5223 + j += PCI_VPD_INFO_FLD_HDR_SIZE;
5225 + for (i = 0; i <= j; i++)
5226 + csum8 += ((u8 *)buf)[i];
5236 @@ -10660,9 +10938,9 @@
5239 is_5705 = is_5750 = 0;
5240 - if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5241 + if (tg3_flag(tp, 5705_PLUS)) {
5243 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5244 + if (tg3_flag(tp, 5750_PLUS))
5248 @@ -10673,7 +10951,7 @@
5249 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
5252 - if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5253 + if (tg3_flag(tp, IS_5788) &&
5254 (reg_tbl[i].flags & TG3_FL_NOT_5788))
5257 @@ -10796,16 +11074,15 @@
5261 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
5262 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
5263 + if (tg3_flag(tp, 5717_PLUS))
5264 mem_tbl = mem_tbl_5717;
5265 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
5266 mem_tbl = mem_tbl_57765;
5267 - else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
5268 + else if (tg3_flag(tp, 5755_PLUS))
5269 mem_tbl = mem_tbl_5755;
5270 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5271 mem_tbl = mem_tbl_5906;
5272 - else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5273 + else if (tg3_flag(tp, 5705_PLUS))
5274 mem_tbl = mem_tbl_5705;
5276 mem_tbl = mem_tbl_570x;
5277 @@ -10832,13 +11109,14 @@
5278 int num_pkts, tx_len, rx_len, i, err;
5279 struct tg3_rx_buffer_desc *desc;
5280 struct tg3_napi *tnapi, *rnapi;
5281 - struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
5282 + struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
5284 tnapi = &tp->napi[0];
5285 rnapi = &tp->napi[0];
5286 if (tp->irq_cnt > 1) {
5287 - rnapi = &tp->napi[1];
5288 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5289 + if (tg3_flag(tp, ENABLE_RSS))
5290 + rnapi = &tp->napi[1];
5291 + if (tg3_flag(tp, ENABLE_TSS))
5292 tnapi = &tp->napi[1];
5294 coal_now = tnapi->coal_now | rnapi->coal_now;
5295 @@ -10846,14 +11124,17 @@
5296 if (loopback_mode == TG3_MAC_LOOPBACK) {
5297 /* HW errata - mac loopback fails in some cases on 5780.
5298 * Normal traffic and PHY loopback are not affected by
5300 + * errata. Also, the MAC loopback test is deprecated for
5301 + * all newer ASIC revisions.
5303 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
5304 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
5305 + tg3_flag(tp, CPMU_PRESENT))
5308 - mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
5309 - MAC_MODE_PORT_INT_LPBACK;
5310 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5311 + mac_mode = tp->mac_mode &
5312 + ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5313 + mac_mode |= MAC_MODE_PORT_INT_LPBACK;
5314 + if (!tg3_flag(tp, 5705_PLUS))
5315 mac_mode |= MAC_MODE_LINK_POLARITY;
5316 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
5317 mac_mode |= MAC_MODE_PORT_MODE_MII;
5318 @@ -10874,7 +11155,8 @@
5319 tg3_writephy(tp, MII_BMCR, val);
5322 - mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5323 + mac_mode = tp->mac_mode &
5324 + ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5325 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
5326 tg3_writephy(tp, MII_TG3_FET_PTEST,
5327 MII_TG3_FET_PTEST_FRC_TX_LINK |
5328 @@ -10902,6 +11184,13 @@
5329 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
5331 tw32(MAC_MODE, mac_mode);
5333 + /* Wait for link */
5334 + for (i = 0; i < 100; i++) {
5335 + if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5342 @@ -11000,28 +11289,44 @@
5346 -#define TG3_MAC_LOOPBACK_FAILED 1
5347 -#define TG3_PHY_LOOPBACK_FAILED 2
5348 -#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
5349 - TG3_PHY_LOOPBACK_FAILED)
5350 +#define TG3_STD_LOOPBACK_FAILED 1
5351 +#define TG3_JMB_LOOPBACK_FAILED 2
5353 +#define TG3_MAC_LOOPBACK_SHIFT 0
5354 +#define TG3_PHY_LOOPBACK_SHIFT 4
5355 +#define TG3_LOOPBACK_FAILED 0x00000033
5357 static int tg3_test_loopback(struct tg3 *tp)
5361 + u32 eee_cap, cpmuctrl = 0;
5363 if (!netif_running(tp->dev))
5364 return TG3_LOOPBACK_FAILED;
5366 + eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
5367 + tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
5369 err = tg3_reset_hw(tp, 1);
5371 - return TG3_LOOPBACK_FAILED;
5373 + err = TG3_LOOPBACK_FAILED;
5377 + if (tg3_flag(tp, ENABLE_RSS)) {
5380 + /* Reroute all rx packets to the 1st queue */
5381 + for (i = MAC_RSS_INDIR_TBL_0;
5382 + i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
5386 /* Turn off gphy autopowerdown. */
5387 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
5388 tg3_phy_toggle_apd(tp, false);
5390 - if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
5391 + if (tg3_flag(tp, CPMU_PRESENT)) {
5395 @@ -11035,8 +11340,10 @@
5399 - if (status != CPMU_MUTEX_GNT_DRIVER)
5400 - return TG3_LOOPBACK_FAILED;
5401 + if (status != CPMU_MUTEX_GNT_DRIVER) {
5402 + err = TG3_LOOPBACK_FAILED;
5406 /* Turn off link-based power management. */
5407 cpmuctrl = tr32(TG3_CPMU_CTRL);
5408 @@ -11046,9 +11353,9 @@
5411 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
5412 - err |= TG3_MAC_LOOPBACK_FAILED;
5413 + err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
5415 - if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
5416 + if (tg3_flag(tp, CPMU_PRESENT)) {
5417 tw32(TG3_CPMU_CTRL, cpmuctrl);
5419 /* Release the mutex */
5420 @@ -11056,15 +11363,19 @@
5423 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
5424 - !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
5425 + !tg3_flag(tp, USE_PHYLIB)) {
5426 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
5427 - err |= TG3_PHY_LOOPBACK_FAILED;
5428 + err |= TG3_STD_LOOPBACK_FAILED <<
5429 + TG3_PHY_LOOPBACK_SHIFT;
5432 /* Re-enable gphy autopowerdown. */
5433 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
5434 tg3_phy_toggle_apd(tp, true);
5437 + tp->phy_flags |= eee_cap;
5442 @@ -11074,7 +11385,7 @@
5443 struct tg3 *tp = netdev_priv(dev);
5445 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5446 - tg3_set_power_state(tp, PCI_D0);
5449 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
5451 @@ -11100,7 +11411,7 @@
5452 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
5453 err = tg3_nvram_lock(tp);
5454 tg3_halt_cpu(tp, RX_CPU_BASE);
5455 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5456 + if (!tg3_flag(tp, 5705_PLUS))
5457 tg3_halt_cpu(tp, TX_CPU_BASE);
5459 tg3_nvram_unlock(tp);
5460 @@ -11130,7 +11441,7 @@
5462 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5463 if (netif_running(dev)) {
5464 - tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
5465 + tg3_flag_set(tp, INIT_COMPLETE);
5466 err2 = tg3_restart_hw(tp, 1);
5468 tg3_netif_start(tp);
5469 @@ -11142,7 +11453,7 @@
5472 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5473 - tg3_set_power_state(tp, PCI_D3hot);
5474 + tg3_power_down(tp);
5478 @@ -11152,7 +11463,7 @@
5479 struct tg3 *tp = netdev_priv(dev);
5482 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5483 + if (tg3_flag(tp, USE_PHYLIB)) {
5484 struct phy_device *phydev;
5485 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
5487 @@ -11171,7 +11482,7 @@
5488 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5489 break; /* We have no PHY */
5491 - if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5492 + if (!netif_running(dev))
5495 spin_lock_bh(&tp->lock);
5496 @@ -11187,7 +11498,7 @@
5497 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5498 break; /* We have no PHY */
5500 - if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5501 + if (!netif_running(dev))
5504 spin_lock_bh(&tp->lock);
5505 @@ -11227,7 +11538,6 @@
5506 tg3_full_unlock(tp);
5510 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
5512 struct tg3 *tp = netdev_priv(dev);
5513 @@ -11242,7 +11552,7 @@
5514 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
5515 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
5517 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5518 + if (!tg3_flag(tp, 5705_PLUS)) {
5519 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
5520 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
5521 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
5522 @@ -11361,8 +11671,7 @@
5526 - if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
5527 - tg3_nvram_read(tp, 0, &val) != 0)
5528 + if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
5531 /* Selfboot format */
5532 @@ -11397,19 +11706,19 @@
5534 nvcfg1 = tr32(NVRAM_CFG1);
5535 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
5536 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5537 + tg3_flag_set(tp, FLASH);
5539 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
5540 tw32(NVRAM_CFG1, nvcfg1);
5543 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
5544 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
5545 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
5546 + tg3_flag(tp, 5780_CLASS)) {
5547 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
5548 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
5549 tp->nvram_jedecnum = JEDEC_ATMEL;
5550 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
5551 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5552 + tg3_flag_set(tp, NVRAM_BUFFERED);
5554 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
5555 tp->nvram_jedecnum = JEDEC_ATMEL;
5556 @@ -11418,12 +11727,12 @@
5557 case FLASH_VENDOR_ATMEL_EEPROM:
5558 tp->nvram_jedecnum = JEDEC_ATMEL;
5559 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
5560 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5561 + tg3_flag_set(tp, NVRAM_BUFFERED);
5563 case FLASH_VENDOR_ST:
5564 tp->nvram_jedecnum = JEDEC_ST;
5565 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
5566 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5567 + tg3_flag_set(tp, NVRAM_BUFFERED);
5569 case FLASH_VENDOR_SAIFUN:
5570 tp->nvram_jedecnum = JEDEC_SAIFUN;
5571 @@ -11438,7 +11747,7 @@
5573 tp->nvram_jedecnum = JEDEC_ATMEL;
5574 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
5575 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5576 + tg3_flag_set(tp, NVRAM_BUFFERED);
5580 @@ -11477,29 +11786,29 @@
5582 /* NVRAM protection for TPM */
5583 if (nvcfg1 & (1 << 27))
5584 - tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
5585 + tg3_flag_set(tp, PROTECTED_NVRAM);
5587 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
5588 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
5589 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
5590 tp->nvram_jedecnum = JEDEC_ATMEL;
5591 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5592 + tg3_flag_set(tp, NVRAM_BUFFERED);
5594 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
5595 tp->nvram_jedecnum = JEDEC_ATMEL;
5596 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5597 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5598 + tg3_flag_set(tp, NVRAM_BUFFERED);
5599 + tg3_flag_set(tp, FLASH);
5601 case FLASH_5752VENDOR_ST_M45PE10:
5602 case FLASH_5752VENDOR_ST_M45PE20:
5603 case FLASH_5752VENDOR_ST_M45PE40:
5604 tp->nvram_jedecnum = JEDEC_ST;
5605 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5606 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5607 + tg3_flag_set(tp, NVRAM_BUFFERED);
5608 + tg3_flag_set(tp, FLASH);
5612 - if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
5613 + if (tg3_flag(tp, FLASH)) {
5614 tg3_nvram_get_pagesize(tp, nvcfg1);
5616 /* For eeprom, set pagesize to maximum eeprom size */
5617 @@ -11518,7 +11827,7 @@
5619 /* NVRAM protection for TPM */
5620 if (nvcfg1 & (1 << 27)) {
5621 - tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
5622 + tg3_flag_set(tp, PROTECTED_NVRAM);
5626 @@ -11529,8 +11838,8 @@
5627 case FLASH_5755VENDOR_ATMEL_FLASH_3:
5628 case FLASH_5755VENDOR_ATMEL_FLASH_5:
5629 tp->nvram_jedecnum = JEDEC_ATMEL;
5630 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5631 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5632 + tg3_flag_set(tp, NVRAM_BUFFERED);
5633 + tg3_flag_set(tp, FLASH);
5634 tp->nvram_pagesize = 264;
5635 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
5636 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
5637 @@ -11547,8 +11856,8 @@
5638 case FLASH_5752VENDOR_ST_M45PE20:
5639 case FLASH_5752VENDOR_ST_M45PE40:
5640 tp->nvram_jedecnum = JEDEC_ST;
5641 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5642 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5643 + tg3_flag_set(tp, NVRAM_BUFFERED);
5644 + tg3_flag_set(tp, FLASH);
5645 tp->nvram_pagesize = 256;
5646 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
5647 tp->nvram_size = (protect ?
5648 @@ -11578,7 +11887,7 @@
5649 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
5650 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
5651 tp->nvram_jedecnum = JEDEC_ATMEL;
5652 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5653 + tg3_flag_set(tp, NVRAM_BUFFERED);
5654 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
5656 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
5657 @@ -11589,16 +11898,16 @@
5658 case FLASH_5755VENDOR_ATMEL_FLASH_2:
5659 case FLASH_5755VENDOR_ATMEL_FLASH_3:
5660 tp->nvram_jedecnum = JEDEC_ATMEL;
5661 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5662 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5663 + tg3_flag_set(tp, NVRAM_BUFFERED);
5664 + tg3_flag_set(tp, FLASH);
5665 tp->nvram_pagesize = 264;
5667 case FLASH_5752VENDOR_ST_M45PE10:
5668 case FLASH_5752VENDOR_ST_M45PE20:
5669 case FLASH_5752VENDOR_ST_M45PE40:
5670 tp->nvram_jedecnum = JEDEC_ST;
5671 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5672 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5673 + tg3_flag_set(tp, NVRAM_BUFFERED);
5674 + tg3_flag_set(tp, FLASH);
5675 tp->nvram_pagesize = 256;
5678 @@ -11612,7 +11921,7 @@
5680 /* NVRAM protection for TPM */
5681 if (nvcfg1 & (1 << 27)) {
5682 - tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
5683 + tg3_flag_set(tp, PROTECTED_NVRAM);
5687 @@ -11627,9 +11936,9 @@
5688 case FLASH_5761VENDOR_ATMEL_MDB081D:
5689 case FLASH_5761VENDOR_ATMEL_MDB161D:
5690 tp->nvram_jedecnum = JEDEC_ATMEL;
5691 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5692 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5693 - tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
5694 + tg3_flag_set(tp, NVRAM_BUFFERED);
5695 + tg3_flag_set(tp, FLASH);
5696 + tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
5697 tp->nvram_pagesize = 256;
5699 case FLASH_5761VENDOR_ST_A_M45PE20:
5700 @@ -11641,8 +11950,8 @@
5701 case FLASH_5761VENDOR_ST_M_M45PE80:
5702 case FLASH_5761VENDOR_ST_M_M45PE16:
5703 tp->nvram_jedecnum = JEDEC_ST;
5704 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5705 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5706 + tg3_flag_set(tp, NVRAM_BUFFERED);
5707 + tg3_flag_set(tp, FLASH);
5708 tp->nvram_pagesize = 256;
5711 @@ -11682,7 +11991,7 @@
5712 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
5714 tp->nvram_jedecnum = JEDEC_ATMEL;
5715 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5716 + tg3_flag_set(tp, NVRAM_BUFFERED);
5717 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
5720 @@ -11696,7 +12005,7 @@
5721 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
5722 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
5723 tp->nvram_jedecnum = JEDEC_ATMEL;
5724 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5725 + tg3_flag_set(tp, NVRAM_BUFFERED);
5726 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
5728 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
5729 @@ -11710,8 +12019,8 @@
5730 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
5731 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
5732 tp->nvram_jedecnum = JEDEC_ATMEL;
5733 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5734 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5735 + tg3_flag_set(tp, NVRAM_BUFFERED);
5736 + tg3_flag_set(tp, FLASH);
5738 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
5739 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
5740 @@ -11733,8 +12042,8 @@
5741 case FLASH_5752VENDOR_ST_M45PE20:
5742 case FLASH_5752VENDOR_ST_M45PE40:
5743 tp->nvram_jedecnum = JEDEC_ST;
5744 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5745 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5746 + tg3_flag_set(tp, NVRAM_BUFFERED);
5747 + tg3_flag_set(tp, FLASH);
5749 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
5750 case FLASH_5752VENDOR_ST_M45PE10:
5751 @@ -11749,13 +12058,13 @@
5755 - tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
5756 + tg3_flag_set(tp, NO_NVRAM);
5760 tg3_nvram_get_pagesize(tp, nvcfg1);
5761 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
5762 - tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
5763 + tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
5767 @@ -11769,7 +12078,7 @@
5768 case FLASH_5717VENDOR_ATMEL_EEPROM:
5769 case FLASH_5717VENDOR_MICRO_EEPROM:
5770 tp->nvram_jedecnum = JEDEC_ATMEL;
5771 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5772 + tg3_flag_set(tp, NVRAM_BUFFERED);
5773 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
5775 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
5776 @@ -11783,11 +12092,13 @@
5777 case FLASH_5717VENDOR_ATMEL_ADB021D:
5778 case FLASH_5717VENDOR_ATMEL_45USPT:
5779 tp->nvram_jedecnum = JEDEC_ATMEL;
5780 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5781 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5782 + tg3_flag_set(tp, NVRAM_BUFFERED);
5783 + tg3_flag_set(tp, FLASH);
5785 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
5786 case FLASH_5717VENDOR_ATMEL_MDB021D:
5787 + /* Detect size with tg3_nvram_get_size() */
5789 case FLASH_5717VENDOR_ATMEL_ADB021B:
5790 case FLASH_5717VENDOR_ATMEL_ADB021D:
5791 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
5792 @@ -11808,13 +12119,15 @@
5793 case FLASH_5717VENDOR_ST_25USPT:
5794 case FLASH_5717VENDOR_ST_45USPT:
5795 tp->nvram_jedecnum = JEDEC_ST;
5796 - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
5797 - tp->tg3_flags2 |= TG3_FLG2_FLASH;
5798 + tg3_flag_set(tp, NVRAM_BUFFERED);
5799 + tg3_flag_set(tp, FLASH);
5801 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
5802 case FLASH_5717VENDOR_ST_M_M25PE20:
5803 - case FLASH_5717VENDOR_ST_A_M25PE20:
5804 case FLASH_5717VENDOR_ST_M_M45PE20:
5805 + /* Detect size with tg3_nvram_get_size() */
5807 + case FLASH_5717VENDOR_ST_A_M25PE20:
5808 case FLASH_5717VENDOR_ST_A_M45PE20:
5809 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
5811 @@ -11824,13 +12137,125 @@
5815 - tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
5816 + tg3_flag_set(tp, NO_NVRAM);
5820 tg3_nvram_get_pagesize(tp, nvcfg1);
5821 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
5822 - tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
5823 + tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
5826 +static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
5828 + u32 nvcfg1, nvmpinstrp;
5830 + nvcfg1 = tr32(NVRAM_CFG1);
5831 + nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
5833 + switch (nvmpinstrp) {
5834 + case FLASH_5720_EEPROM_HD:
5835 + case FLASH_5720_EEPROM_LD:
5836 + tp->nvram_jedecnum = JEDEC_ATMEL;
5837 + tg3_flag_set(tp, NVRAM_BUFFERED);
5839 + nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
5840 + tw32(NVRAM_CFG1, nvcfg1);
5841 + if (nvmpinstrp == FLASH_5720_EEPROM_HD)
5842 + tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
5844 + tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
5846 + case FLASH_5720VENDOR_M_ATMEL_DB011D:
5847 + case FLASH_5720VENDOR_A_ATMEL_DB011B:
5848 + case FLASH_5720VENDOR_A_ATMEL_DB011D:
5849 + case FLASH_5720VENDOR_M_ATMEL_DB021D:
5850 + case FLASH_5720VENDOR_A_ATMEL_DB021B:
5851 + case FLASH_5720VENDOR_A_ATMEL_DB021D:
5852 + case FLASH_5720VENDOR_M_ATMEL_DB041D:
5853 + case FLASH_5720VENDOR_A_ATMEL_DB041B:
5854 + case FLASH_5720VENDOR_A_ATMEL_DB041D:
5855 + case FLASH_5720VENDOR_M_ATMEL_DB081D:
5856 + case FLASH_5720VENDOR_A_ATMEL_DB081D:
5857 + case FLASH_5720VENDOR_ATMEL_45USPT:
5858 + tp->nvram_jedecnum = JEDEC_ATMEL;
5859 + tg3_flag_set(tp, NVRAM_BUFFERED);
5860 + tg3_flag_set(tp, FLASH);
5862 + switch (nvmpinstrp) {
5863 + case FLASH_5720VENDOR_M_ATMEL_DB021D:
5864 + case FLASH_5720VENDOR_A_ATMEL_DB021B:
5865 + case FLASH_5720VENDOR_A_ATMEL_DB021D:
5866 + tp->nvram_size = TG3_NVRAM_SIZE_256KB;
5868 + case FLASH_5720VENDOR_M_ATMEL_DB041D:
5869 + case FLASH_5720VENDOR_A_ATMEL_DB041B:
5870 + case FLASH_5720VENDOR_A_ATMEL_DB041D:
5871 + tp->nvram_size = TG3_NVRAM_SIZE_512KB;
5873 + case FLASH_5720VENDOR_M_ATMEL_DB081D:
5874 + case FLASH_5720VENDOR_A_ATMEL_DB081D:
5875 + tp->nvram_size = TG3_NVRAM_SIZE_1MB;
5878 + tp->nvram_size = TG3_NVRAM_SIZE_128KB;
5882 + case FLASH_5720VENDOR_M_ST_M25PE10:
5883 + case FLASH_5720VENDOR_M_ST_M45PE10:
5884 + case FLASH_5720VENDOR_A_ST_M25PE10:
5885 + case FLASH_5720VENDOR_A_ST_M45PE10:
5886 + case FLASH_5720VENDOR_M_ST_M25PE20:
5887 + case FLASH_5720VENDOR_M_ST_M45PE20:
5888 + case FLASH_5720VENDOR_A_ST_M25PE20:
5889 + case FLASH_5720VENDOR_A_ST_M45PE20:
5890 + case FLASH_5720VENDOR_M_ST_M25PE40:
5891 + case FLASH_5720VENDOR_M_ST_M45PE40:
5892 + case FLASH_5720VENDOR_A_ST_M25PE40:
5893 + case FLASH_5720VENDOR_A_ST_M45PE40:
5894 + case FLASH_5720VENDOR_M_ST_M25PE80:
5895 + case FLASH_5720VENDOR_M_ST_M45PE80:
5896 + case FLASH_5720VENDOR_A_ST_M25PE80:
5897 + case FLASH_5720VENDOR_A_ST_M45PE80:
5898 + case FLASH_5720VENDOR_ST_25USPT:
5899 + case FLASH_5720VENDOR_ST_45USPT:
5900 + tp->nvram_jedecnum = JEDEC_ST;
5901 + tg3_flag_set(tp, NVRAM_BUFFERED);
5902 + tg3_flag_set(tp, FLASH);
5904 + switch (nvmpinstrp) {
5905 + case FLASH_5720VENDOR_M_ST_M25PE20:
5906 + case FLASH_5720VENDOR_M_ST_M45PE20:
5907 + case FLASH_5720VENDOR_A_ST_M25PE20:
5908 + case FLASH_5720VENDOR_A_ST_M45PE20:
5909 + tp->nvram_size = TG3_NVRAM_SIZE_256KB;
5911 + case FLASH_5720VENDOR_M_ST_M25PE40:
5912 + case FLASH_5720VENDOR_M_ST_M45PE40:
5913 + case FLASH_5720VENDOR_A_ST_M25PE40:
5914 + case FLASH_5720VENDOR_A_ST_M45PE40:
5915 + tp->nvram_size = TG3_NVRAM_SIZE_512KB;
5917 + case FLASH_5720VENDOR_M_ST_M25PE80:
5918 + case FLASH_5720VENDOR_M_ST_M45PE80:
5919 + case FLASH_5720VENDOR_A_ST_M25PE80:
5920 + case FLASH_5720VENDOR_A_ST_M45PE80:
5921 + tp->nvram_size = TG3_NVRAM_SIZE_1MB;
5924 + tp->nvram_size = TG3_NVRAM_SIZE_128KB;
5929 + tg3_flag_set(tp, NO_NVRAM);
5933 + tg3_nvram_get_pagesize(tp, nvcfg1);
5934 + if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
5935 + tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
5938 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
5939 @@ -11850,7 +12275,7 @@
5941 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
5942 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
5943 - tp->tg3_flags |= TG3_FLAG_NVRAM;
5944 + tg3_flag_set(tp, NVRAM);
5946 if (tg3_nvram_lock(tp)) {
5947 netdev_warn(tp->dev,
5948 @@ -11880,6 +12305,8 @@
5949 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
5950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
5951 tg3_get_5717_nvram_info(tp);
5952 + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5953 + tg3_get_5720_nvram_info(tp);
5955 tg3_get_nvram_info(tp);
5957 @@ -11890,7 +12317,8 @@
5958 tg3_nvram_unlock(tp);
5961 - tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
5962 + tg3_flag_clear(tp, NVRAM);
5963 + tg3_flag_clear(tp, NVRAM_BUFFERED);
5965 tg3_get_eeprom_size(tp);
5967 @@ -12073,7 +12501,7 @@
5968 nvram_cmd |= NVRAM_CMD_LAST;
5970 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
5971 - !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
5972 + !tg3_flag(tp, 5755_PLUS) &&
5973 (tp->nvram_jedecnum == JEDEC_ST) &&
5974 (nvram_cmd & NVRAM_CMD_FIRST)) {
5976 @@ -12083,7 +12511,7 @@
5980 - if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
5981 + if (!tg3_flag(tp, FLASH)) {
5982 /* We always do complete word writes to eeprom. */
5983 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
5985 @@ -12099,13 +12527,13 @@
5989 - if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5990 + if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
5991 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
5992 ~GRC_LCLCTRL_GPIO_OUTPUT1);
5996 - if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
5997 + if (!tg3_flag(tp, NVRAM)) {
5998 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
6001 @@ -12115,16 +12543,13 @@
6004 tg3_enable_nvram_access(tp);
6005 - if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6006 - !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
6007 + if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
6008 tw32(NVRAM_WRITE1, 0x406);
6010 grc_mode = tr32(GRC_MODE);
6011 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
6013 - if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
6014 - !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
6016 + if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
6017 ret = tg3_nvram_write_block_buffered(tp, offset, len,
6020 @@ -12139,7 +12564,7 @@
6021 tg3_nvram_unlock(tp);
6024 - if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6025 + if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
6026 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6029 @@ -12261,19 +12686,22 @@
6030 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
6032 /* Assume an onboard device and WOL capable by default. */
6033 - tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
6034 + tg3_flag_set(tp, EEPROM_WRITE_PROT);
6035 + tg3_flag_set(tp, WOL_CAP);
6037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6038 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
6039 - tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
6040 - tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
6041 + tg3_flag_clear(tp, EEPROM_WRITE_PROT);
6042 + tg3_flag_set(tp, IS_NIC);
6044 val = tr32(VCPU_CFGSHDW);
6045 if (val & VCPU_CFGSHDW_ASPM_DBNC)
6046 - tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
6047 + tg3_flag_set(tp, ASPM_WORKAROUND);
6048 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6049 - (val & VCPU_CFGSHDW_WOL_MAGPKT))
6050 - tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6051 + (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
6052 + tg3_flag_set(tp, WOL_ENABLE);
6053 + device_set_wakeup_enable(&tp->pdev->dev, true);
6058 @@ -12288,9 +12716,9 @@
6060 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
6061 ver >>= NIC_SRAM_DATA_VER_SHIFT;
6062 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
6063 - (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
6064 - (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
6065 + if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
6066 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
6067 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
6068 (ver > 0) && (ver < 0x100))
6069 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
6071 @@ -12314,13 +12742,13 @@
6073 tp->phy_id = eeprom_phy_id;
6074 if (eeprom_phy_serdes) {
6075 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6076 + if (!tg3_flag(tp, 5705_PLUS))
6077 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
6079 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
6082 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6083 + if (tg3_flag(tp, 5750_PLUS))
6084 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
6085 SHASTA_EXT_LED_MODE_MASK);
6087 @@ -12380,34 +12808,36 @@
6088 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
6090 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
6091 - tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
6092 + tg3_flag_set(tp, EEPROM_WRITE_PROT);
6093 if ((tp->pdev->subsystem_vendor ==
6094 PCI_VENDOR_ID_ARIMA) &&
6095 (tp->pdev->subsystem_device == 0x205a ||
6096 tp->pdev->subsystem_device == 0x2063))
6097 - tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
6098 + tg3_flag_clear(tp, EEPROM_WRITE_PROT);
6100 - tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
6101 - tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
6102 + tg3_flag_clear(tp, EEPROM_WRITE_PROT);
6103 + tg3_flag_set(tp, IS_NIC);
6106 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6107 - tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6108 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6109 - tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6110 + tg3_flag_set(tp, ENABLE_ASF);
6111 + if (tg3_flag(tp, 5750_PLUS))
6112 + tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
6115 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
6116 - (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
6117 - tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
6118 + tg3_flag(tp, 5750_PLUS))
6119 + tg3_flag_set(tp, ENABLE_APE);
6121 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
6122 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
6123 - tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
6124 + tg3_flag_clear(tp, WOL_CAP);
6126 - if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
6127 - (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
6128 - tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6129 + if (tg3_flag(tp, WOL_CAP) &&
6130 + (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
6131 + tg3_flag_set(tp, WOL_ENABLE);
6132 + device_set_wakeup_enable(&tp->pdev->dev, true);
6135 if (cfg2 & (1 << 17))
6136 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
6137 @@ -12417,33 +12847,35 @@
6138 if (cfg2 & (1 << 18))
6139 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
6141 - if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
6142 - ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
6143 - GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
6144 + if ((tg3_flag(tp, 57765_PLUS) ||
6145 + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
6146 + GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6147 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
6148 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6150 - if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6151 + if (tg3_flag(tp, PCI_EXPRESS) &&
6152 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6153 - !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
6154 + !tg3_flag(tp, 57765_PLUS)) {
6157 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
6158 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
6159 - tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
6160 + tg3_flag_set(tp, ASPM_WORKAROUND);
6163 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
6164 - tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
6165 + tg3_flag_set(tp, RGMII_INBAND_DISABLE);
6166 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
6167 - tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
6168 + tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
6169 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
6170 - tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
6171 + tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
6174 - device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
6175 - device_set_wakeup_enable(&tp->pdev->dev,
6176 - tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
6177 + if (tg3_flag(tp, WOL_CAP))
6178 + device_set_wakeup_enable(&tp->pdev->dev,
6179 + tg3_flag(tp, WOL_ENABLE));
6181 + device_set_wakeup_capable(&tp->pdev->dev, false);
6184 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
6185 @@ -12495,21 +12927,53 @@
6186 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
6189 +static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
6191 + u32 adv = ADVERTISED_Autoneg |
6194 + if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
6195 + adv |= ADVERTISED_1000baseT_Half |
6196 + ADVERTISED_1000baseT_Full;
6198 + if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
6199 + adv |= ADVERTISED_100baseT_Half |
6200 + ADVERTISED_100baseT_Full |
6201 + ADVERTISED_10baseT_Half |
6202 + ADVERTISED_10baseT_Full |
6205 + adv |= ADVERTISED_FIBRE;
6207 + tp->link_config.advertising = adv;
6208 + tp->link_config.speed = SPEED_INVALID;
6209 + tp->link_config.duplex = DUPLEX_INVALID;
6210 + tp->link_config.autoneg = AUTONEG_ENABLE;
6211 + tp->link_config.active_speed = SPEED_INVALID;
6212 + tp->link_config.active_duplex = DUPLEX_INVALID;
6213 + tp->link_config.orig_speed = SPEED_INVALID;
6214 + tp->link_config.orig_duplex = DUPLEX_INVALID;
6215 + tp->link_config.orig_autoneg = AUTONEG_INVALID;
6218 static int __devinit tg3_phy_probe(struct tg3 *tp)
6220 u32 hw_phy_id_1, hw_phy_id_2;
6221 u32 hw_phy_id, hw_phy_id_masked;
6224 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
6225 + /* flow control autonegotiation is default behavior */
6226 + tg3_flag_set(tp, PAUSE_AUTONEG);
6227 + tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
6229 + if (tg3_flag(tp, USE_PHYLIB))
6230 return tg3_phy_init(tp);
6232 /* Reading the PHY ID register can conflict with ASF
6233 * firmware access to the PHY hardware.
6236 - if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
6237 - (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6238 + if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
6239 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
6241 /* Now read the physical PHY_ID from the chip and verify
6242 @@ -12562,10 +13026,12 @@
6243 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
6244 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
6246 + tg3_phy_init_link_config(tp);
6248 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
6249 - !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
6250 - !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6251 - u32 bmsr, adv_reg, tg3_ctrl, mask;
6252 + !tg3_flag(tp, ENABLE_APE) &&
6253 + !tg3_flag(tp, ENABLE_ASF)) {
6256 tg3_readphy(tp, MII_BMSR, &bmsr);
6257 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
6258 @@ -12576,36 +13042,18 @@
6262 - adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
6263 - ADVERTISE_100HALF | ADVERTISE_100FULL |
6264 - ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
6266 - if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
6267 - tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
6268 - MII_TG3_CTRL_ADV_1000_FULL);
6269 - if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
6270 - tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
6271 - tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
6272 - MII_TG3_CTRL_ENABLE_AS_MASTER);
6274 + tg3_phy_set_wirespeed(tp);
6276 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
6277 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
6278 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
6279 if (!tg3_copper_is_advertising_all(tp, mask)) {
6280 - tg3_writephy(tp, MII_ADVERTISE, adv_reg);
6282 - if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
6283 - tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
6284 + tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
6285 + tp->link_config.flowctrl);
6287 tg3_writephy(tp, MII_BMCR,
6288 BMCR_ANENABLE | BMCR_ANRESTART);
6290 - tg3_phy_set_wirespeed(tp);
6292 - tg3_writephy(tp, MII_ADVERTISE, adv_reg);
6293 - if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
6294 - tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
6298 @@ -12617,60 +13065,18 @@
6299 err = tg3_init_5401phy_dsp(tp);
6302 - if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
6303 - tp->link_config.advertising =
6304 - (ADVERTISED_1000baseT_Half |
6305 - ADVERTISED_1000baseT_Full |
6306 - ADVERTISED_Autoneg |
6307 - ADVERTISED_FIBRE);
6308 - if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6309 - tp->link_config.advertising &=
6310 - ~(ADVERTISED_1000baseT_Half |
6311 - ADVERTISED_1000baseT_Full);
6316 static void __devinit tg3_read_vpd(struct tg3 *tp)
6318 - u8 vpd_data[TG3_NVM_VPD_LEN];
6320 unsigned int block_end, rosize, len;
6324 - if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
6325 - tg3_nvram_read(tp, 0x0, &magic))
6326 - goto out_not_found;
6328 - if (magic == TG3_EEPROM_MAGIC) {
6329 - for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
6332 - /* The data is in little-endian format in NVRAM.
6333 - * Use the big-endian read routines to preserve
6334 - * the byte order as it exists in NVRAM.
6336 - if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
6337 - goto out_not_found;
6339 - memcpy(&vpd_data[i], &tmp, sizeof(tmp));
6343 - unsigned int pos = 0;
6345 - for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
6346 - cnt = pci_read_vpd(tp->pdev, pos,
6347 - TG3_NVM_VPD_LEN - pos,
6349 - if (cnt == -ETIMEDOUT || -EINTR)
6352 - goto out_not_found;
6354 - if (pos != TG3_NVM_VPD_LEN)
6355 - goto out_not_found;
6357 + vpd_data = (u8 *)tg3_vpd_readblock(tp);
6361 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
6362 PCI_VPD_LRDT_RO_DATA);
6363 @@ -12724,43 +13130,51 @@
6365 memcpy(tp->board_part_number, &vpd_data[i], len);
6370 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6372 + if (tp->board_part_number[0])
6376 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
6377 + if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
6378 + strcpy(tp->board_part_number, "BCM5717");
6379 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
6380 + strcpy(tp->board_part_number, "BCM5718");
6383 + } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6384 + if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
6385 + strcpy(tp->board_part_number, "BCM57780");
6386 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
6387 + strcpy(tp->board_part_number, "BCM57760");
6388 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
6389 + strcpy(tp->board_part_number, "BCM57790");
6390 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
6391 + strcpy(tp->board_part_number, "BCM57788");
6394 + } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
6395 + if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
6396 + strcpy(tp->board_part_number, "BCM57761");
6397 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
6398 + strcpy(tp->board_part_number, "BCM57765");
6399 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
6400 + strcpy(tp->board_part_number, "BCM57781");
6401 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
6402 + strcpy(tp->board_part_number, "BCM57785");
6403 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
6404 + strcpy(tp->board_part_number, "BCM57791");
6405 + else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
6406 + strcpy(tp->board_part_number, "BCM57795");
6409 + } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6410 strcpy(tp->board_part_number, "BCM95906");
6411 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
6412 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
6413 - strcpy(tp->board_part_number, "BCM57780");
6414 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
6415 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
6416 - strcpy(tp->board_part_number, "BCM57760");
6417 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
6418 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
6419 - strcpy(tp->board_part_number, "BCM57790");
6420 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
6421 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
6422 - strcpy(tp->board_part_number, "BCM57788");
6423 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
6424 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
6425 - strcpy(tp->board_part_number, "BCM57761");
6426 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
6427 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
6428 - strcpy(tp->board_part_number, "BCM57765");
6429 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
6430 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
6431 - strcpy(tp->board_part_number, "BCM57781");
6432 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
6433 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
6434 - strcpy(tp->board_part_number, "BCM57785");
6435 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
6436 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
6437 - strcpy(tp->board_part_number, "BCM57791");
6438 - else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
6439 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
6440 - strcpy(tp->board_part_number, "BCM57795");
6444 strcpy(tp->board_part_number, "none");
6448 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
6449 @@ -12869,6 +13283,9 @@
6450 case TG3_EEPROM_SB_REVISION_5:
6451 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
6453 + case TG3_EEPROM_SB_REVISION_6:
6454 + offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
6459 @@ -12914,7 +13331,7 @@
6460 if (offset == TG3_NVM_DIR_END)
6463 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6464 + if (!tg3_flag(tp, 5705_PLUS))
6466 else if (tg3_nvram_read(tp, offset - 4, &start))
6468 @@ -12954,8 +13371,7 @@
6472 - if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
6473 - !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6474 + if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
6477 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6478 @@ -12968,10 +13384,12 @@
6480 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
6482 - if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
6483 + if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
6484 + tg3_flag_set(tp, APE_HAS_NCSI);
6491 vlen = strlen(tp->fw_ver);
6493 @@ -12991,7 +13409,7 @@
6494 if (tp->fw_ver[0] != 0)
6497 - if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
6498 + if (tg3_flag(tp, NO_NVRAM)) {
6499 strcat(tp->fw_ver, "sb");
6502 @@ -13008,8 +13426,7 @@
6506 - if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
6507 - (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
6508 + if (!tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || vpd_vers)
6511 tg3_read_mgmtfw_ver(tp);
6512 @@ -13020,7 +13437,7 @@
6514 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
6516 -static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
6517 +static inline void vlan_features_add(struct net_device *dev, unsigned long flags)
6519 #if TG3_VLAN_TAG_USED
6520 dev->vlan_features |= flags;
6521 @@ -13029,27 +13446,23 @@
6523 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
6525 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
6526 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
6528 - else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6529 - !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6531 + if (tg3_flag(tp, LRG_PROD_RING_CAP))
6532 + return TG3_RX_RET_MAX_SIZE_5717;
6533 + else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
6534 + return TG3_RX_RET_MAX_SIZE_5700;
6537 + return TG3_RX_RET_MAX_SIZE_5705;
6540 +static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
6541 + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
6542 + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
6543 + { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
6547 static int __devinit tg3_get_invariants(struct tg3 *tp)
6549 - static struct pci_device_id write_reorder_chipsets[] = {
6550 - { PCI_DEVICE(PCI_VENDOR_ID_AMD,
6551 - PCI_DEVICE_ID_AMD_FE_GATE_700C) },
6552 - { PCI_DEVICE(PCI_VENDOR_ID_AMD,
6553 - PCI_DEVICE_ID_AMD_8131_BRIDGE) },
6554 - { PCI_DEVICE(PCI_VENDOR_ID_VIA,
6555 - PCI_DEVICE_ID_VIA_8385_0) },
6559 u32 pci_state_reg, grc_misc_cfg;
6561 @@ -13083,8 +13496,8 @@
6563 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
6564 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
6565 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
6566 - tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
6567 + tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
6568 + tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
6569 pci_read_config_dword(tp->pdev,
6570 TG3PCI_GEN2_PRODID_ASICREV,
6572 @@ -13161,15 +13574,14 @@
6573 if (bridge->subordinate &&
6574 (bridge->subordinate->number ==
6575 tp->pdev->bus->number)) {
6577 - tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
6578 + tg3_flag_set(tp, ICH_WORKAROUND);
6579 pci_dev_put(bridge);
6585 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6586 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
6587 static struct tg3_dev_id {
6590 @@ -13194,7 +13606,7 @@
6591 tp->pdev->bus->number) &&
6592 (bridge->subordinate->subordinate >=
6593 tp->pdev->bus->number)) {
6594 - tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
6595 + tg3_flag_set(tp, 5701_DMA_BUG);
6596 pci_dev_put(bridge);
6599 @@ -13209,8 +13621,8 @@
6601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
6602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
6603 - tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
6604 - tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
6605 + tg3_flag_set(tp, 5780_CLASS);
6606 + tg3_flag_set(tp, 40BIT_DMA_BUG);
6607 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
6609 struct pci_dev *bridge = NULL;
6610 @@ -13224,7 +13636,7 @@
6611 tp->pdev->bus->number) &&
6612 (bridge->subordinate->subordinate >=
6613 tp->pdev->bus->number)) {
6614 - tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
6615 + tg3_flag_set(tp, 40BIT_DMA_BUG);
6616 pci_dev_put(bridge);
6619 @@ -13239,13 +13651,18 @@
6621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
6622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
6623 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
6624 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
6625 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
6626 tp->pdev_peer = tg3_find_peer(tp);
6628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
6629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
6630 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
6631 - tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
6632 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
6633 + tg3_flag_set(tp, 5717_PLUS);
6635 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
6636 + tg3_flag(tp, 5717_PLUS))
6637 + tg3_flag_set(tp, 57765_PLUS);
6639 /* Intentionally exclude ASIC_REV_5906 */
6640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
6641 @@ -13254,94 +13671,103 @@
6642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
6643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
6645 - (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
6646 - tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
6647 + tg3_flag(tp, 57765_PLUS))
6648 + tg3_flag_set(tp, 5755_PLUS);
6650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
6651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
6653 - (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
6654 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6655 - tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
6657 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
6658 - (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
6659 - tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
6661 - /* 5700 B0 chips do not support checksumming correctly due
6662 - * to hardware bugs.
6664 - if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
6665 - tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
6667 - unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
6668 + tg3_flag(tp, 5755_PLUS) ||
6669 + tg3_flag(tp, 5780_CLASS))
6670 + tg3_flag_set(tp, 5750_PLUS);
6672 - tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
6673 - if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6674 - features |= NETIF_F_IPV6_CSUM;
6675 - tp->dev->features |= features;
6676 - vlan_features_add(tp->dev, features);
6678 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
6679 + tg3_flag(tp, 5750_PLUS))
6680 + tg3_flag_set(tp, 5705_PLUS);
6682 /* Determine TSO capabilities */
6683 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
6684 - tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
6685 - else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
6686 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
6687 + ; /* Do nothing. HW bug. */
6688 + else if (tg3_flag(tp, 57765_PLUS))
6689 + tg3_flag_set(tp, HW_TSO_3);
6690 + else if (tg3_flag(tp, 5755_PLUS) ||
6691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6692 - tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
6693 - else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6694 - tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
6695 + tg3_flag_set(tp, HW_TSO_2);
6696 + else if (tg3_flag(tp, 5750_PLUS)) {
6697 + tg3_flag_set(tp, HW_TSO_1);
6698 + tg3_flag_set(tp, TSO_BUG);
6699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
6700 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
6701 - tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
6702 + tg3_flag_clear(tp, TSO_BUG);
6703 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
6704 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
6705 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
6706 - tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
6707 + tg3_flag_set(tp, TSO_BUG);
6708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
6709 tp->fw_needed = FIRMWARE_TG3TSO5;
6711 tp->fw_needed = FIRMWARE_TG3TSO;
6714 + /* Selectively allow TSO based on operating conditions */
6715 + if (tg3_flag(tp, HW_TSO_1) ||
6716 + tg3_flag(tp, HW_TSO_2) ||
6717 + tg3_flag(tp, HW_TSO_3) ||
6718 + (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
6719 + tg3_flag_set(tp, TSO_CAPABLE);
6721 + tg3_flag_clear(tp, TSO_CAPABLE);
6722 + tg3_flag_clear(tp, TSO_BUG);
6723 + tp->fw_needed = NULL;
6726 + if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
6727 + tp->fw_needed = FIRMWARE_TG3;
6731 - if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6732 - tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
6733 + if (tg3_flag(tp, 5750_PLUS)) {
6734 + tg3_flag_set(tp, SUPPORT_MSI);
6735 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
6736 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
6737 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
6738 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
6739 tp->pdev_peer == tp->pdev))
6740 - tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
6741 + tg3_flag_clear(tp, SUPPORT_MSI);
6743 - if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
6744 + if (tg3_flag(tp, 5755_PLUS) ||
6745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6746 - tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
6747 + tg3_flag_set(tp, 1SHOT_MSI);
6750 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
6751 - tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
6752 + if (tg3_flag(tp, 57765_PLUS)) {
6753 + tg3_flag_set(tp, SUPPORT_MSIX);
6754 tp->irq_max = TG3_IRQ_MAX_VECS;
6758 + /* All chips can get confused if TX buffers
6759 + * straddle the 4GB address boundary.
6761 + tg3_flag_set(tp, 4G_DMA_BNDRY_BUG);
6763 + if (tg3_flag(tp, 5755_PLUS))
6764 + tg3_flag_set(tp, SHORT_DMA_BUG);
6766 + tg3_flag_set(tp, 40BIT_DMA_LIMIT_BUG);
6768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
6769 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
6770 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6771 - tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
6772 - else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
6773 - tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
6774 - tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
6776 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
6777 + tg3_flag_set(tp,LRG_PROD_RING_CAP);
6779 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
6780 - tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
6781 + if (tg3_flag(tp, 57765_PLUS) &&
6782 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
6783 + tg3_flag_set(tp, USE_JUMBO_BDFLAG);
6785 - if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
6786 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
6787 - (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
6788 - tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
6789 + if (!tg3_flag(tp, 5705_PLUS) ||
6790 + tg3_flag(tp, 5780_CLASS) ||
6791 + tg3_flag(tp, USE_JUMBO_BDFLAG))
6792 + tg3_flag_set(tp, JUMBO_CAPABLE);
6794 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
6796 @@ -13350,45 +13776,12 @@
6797 if (tp->pcie_cap != 0) {
6800 - tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
6801 + tg3_flag_set(tp, PCI_EXPRESS);
6803 tp->pcie_readrq = 4096;
6804 - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
6807 - pci_read_config_word(tp->pdev,
6808 - tp->pcie_cap + PCI_EXP_LNKSTA,
6810 - switch (word & PCI_EXP_LNKSTA_CLS) {
6811 - case PCI_EXP_LNKSTA_CLS_2_5GB:
6812 - word &= PCI_EXP_LNKSTA_NLW;
6813 - word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
6816 - tp->pcie_readrq = 2048;
6819 - tp->pcie_readrq = 1024;
6824 - case PCI_EXP_LNKSTA_CLS_5_0GB:
6825 - word &= PCI_EXP_LNKSTA_NLW;
6826 - word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
6829 - tp->pcie_readrq = 2048;
6832 - tp->pcie_readrq = 1024;
6835 - tp->pcie_readrq = 512;
6840 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
6841 + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
6842 + tp->pcie_readrq = 2048;
6844 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6846 @@ -13397,19 +13790,20 @@
6848 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
6849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6850 - tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
6851 + tg3_flag_clear(tp, HW_TSO_2);
6852 + tg3_flag_clear(tp, TSO_CAPABLE);
6853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
6854 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
6855 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
6856 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
6857 - tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
6858 + tg3_flag_set(tp, CLKREQ_BUG);
6859 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
6860 - tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
6861 + tg3_flag_set(tp, L1PLLPD_EN);
6863 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
6864 - tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
6865 - } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
6866 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6867 + tg3_flag_set(tp, PCI_EXPRESS);
6868 + } else if (!tg3_flag(tp, 5705_PLUS) ||
6869 + tg3_flag(tp, 5780_CLASS)) {
6870 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
6871 if (!tp->pcix_cap) {
6872 dev_err(&tp->pdev->dev,
6873 @@ -13418,7 +13812,7 @@
6876 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
6877 - tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
6878 + tg3_flag_set(tp, PCIX_MODE);
6881 /* If we have an AMD 762 or VIA K8T800 chipset, write
6882 @@ -13427,9 +13821,9 @@
6883 * every mailbox register write to force the writes to be
6884 * posted to the chip in order.
6886 - if (pci_dev_present(write_reorder_chipsets) &&
6887 - !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6888 - tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
6889 + if (pci_dev_present(tg3_write_reorder_chipsets) &&
6890 + !tg3_flag(tp, PCI_EXPRESS))
6891 + tg3_flag_set(tp, MBOX_WRITE_REORDER);
6893 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6894 &tp->pci_cacheline_sz);
6895 @@ -13446,17 +13840,17 @@
6896 /* 5700 BX chips need to have their TX producer index
6897 * mailboxes written twice to workaround a bug.
6899 - tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
6900 + tg3_flag_set(tp, TXD_MBOX_HWBUG);
6902 /* If we are in PCI-X mode, enable register write workaround.
6904 * The workaround is to use indirect register accesses
6905 * for all chip writes not to mailbox registers.
6907 - if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6908 + if (tg3_flag(tp, PCIX_MODE)) {
6911 - tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
6912 + tg3_flag_set(tp, PCIX_TARGET_HWBUG);
6914 /* The chip can have it's power management PCI config
6915 * space registers clobbered due to this bug.
6916 @@ -13479,9 +13873,9 @@
6919 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
6920 - tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
6921 + tg3_flag_set(tp, PCI_HIGH_SPEED);
6922 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
6923 - tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
6924 + tg3_flag_set(tp, PCI_32BIT);
6926 /* Chip-specific fixup from Broadcom driver */
6927 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
6928 @@ -13499,10 +13893,10 @@
6929 tp->write32_rx_mbox = tg3_write32;
6931 /* Various workaround register access methods */
6932 - if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
6933 + if (tg3_flag(tp, PCIX_TARGET_HWBUG))
6934 tp->write32 = tg3_write_indirect_reg32;
6935 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
6936 - ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6937 + (tg3_flag(tp, PCI_EXPRESS) &&
6938 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
6940 * Back to back register writes can cause problems on these
6941 @@ -13514,14 +13908,13 @@
6942 tp->write32 = tg3_write_flush_reg32;
6945 - if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
6946 - (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
6947 + if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
6948 tp->write32_tx_mbox = tg3_write32_tx_mbox;
6949 - if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
6950 + if (tg3_flag(tp, MBOX_WRITE_REORDER))
6951 tp->write32_rx_mbox = tg3_write_flush_reg32;
6954 - if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
6955 + if (tg3_flag(tp, ICH_WORKAROUND)) {
6956 tp->read32 = tg3_read_indirect_reg32;
6957 tp->write32 = tg3_write_indirect_reg32;
6958 tp->read32_mbox = tg3_read_indirect_mbox;
6959 @@ -13544,13 +13937,13 @@
6962 if (tp->write32 == tg3_write_indirect_reg32 ||
6963 - ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
6964 + (tg3_flag(tp, PCIX_MODE) &&
6965 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
6967 - tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
6968 + tg3_flag_set(tp, SRAM_USE_CONFIG);
6970 /* Get eeprom hw config before calling tg3_set_power_state().
6971 - * In particular, the TG3_FLG2_IS_NIC flag must be
6972 + * In particular, the TG3_FLAG_IS_NIC flag must be
6973 * determined before calling tg3_set_power_state() so that
6974 * we know whether or not to switch out of Vaux power.
6975 * When the flag is set, it means that GPIO1 is used for eeprom
6976 @@ -13559,7 +13952,7 @@
6978 tg3_get_eeprom_hw_cfg(tp);
6980 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6981 + if (tg3_flag(tp, ENABLE_APE)) {
6982 /* Allow reads and writes to the
6983 * APE register and memory space.
6985 @@ -13574,16 +13967,16 @@
6986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
6987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
6989 - (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
6990 - tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
6991 + tg3_flag(tp, 57765_PLUS))
6992 + tg3_flag_set(tp, CPMU_PRESENT);
6994 - /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
6995 + /* Set up tp->grc_local_ctrl before calling tg3_power_up().
6996 * GPIO1 driven high will bring 5700's external PHY out of reset.
6997 * It is also used as eeprom write protect on LOMs.
6999 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
7000 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
7001 - (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
7002 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7003 + tg3_flag(tp, EEPROM_WRITE_PROT))
7004 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7005 GRC_LCLCTRL_GPIO_OUTPUT1);
7006 /* Unused GPIO3 must be driven as output on 5752 because there
7007 @@ -13601,14 +13994,14 @@
7008 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
7009 /* Turn off the debug UART. */
7010 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
7011 - if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
7012 + if (tg3_flag(tp, IS_NIC))
7013 /* Keep VMain power. */
7014 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
7015 GRC_LCLCTRL_GPIO_OUTPUT0;
7018 /* Force the chip into D0. */
7019 - err = tg3_set_power_state(tp, PCI_D0);
7020 + err = tg3_power_up(tp);
7022 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
7024 @@ -13617,26 +14010,25 @@
7025 /* Derive initial jumbo mode from MTU assigned in
7026 * ether_setup() via the alloc_etherdev() call
7028 - if (tp->dev->mtu > ETH_DATA_LEN &&
7029 - !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7030 - tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
7031 + if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
7032 + tg3_flag_set(tp, JUMBO_RING_ENABLE);
7034 /* Determine WakeOnLan speed to use. */
7035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7036 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
7037 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
7038 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
7039 - tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
7040 + tg3_flag_clear(tp, WOL_SPEED_100MB);
7042 - tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
7043 + tg3_flag_set(tp, WOL_SPEED_100MB);
7046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
7047 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7049 /* A few boards don't want Ethernet@WireSpeed phy feature */
7050 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
7051 - ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
7052 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7053 + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7054 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
7055 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7056 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
7057 @@ -13649,11 +14041,11 @@
7058 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
7059 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
7061 - if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7062 + if (tg3_flag(tp, 5705_PLUS) &&
7063 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7064 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7065 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
7066 - !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7067 + !tg3_flag(tp, 57765_PLUS)) {
7068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
7070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7071 @@ -13674,7 +14066,7 @@
7072 tp->phy_otp = TG3_OTP_DEFAULT;
7075 - if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
7076 + if (tg3_flag(tp, CPMU_PRESENT))
7077 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
7079 tp->mi_mode = MAC_MI_MODE_BASE;
7080 @@ -13684,9 +14076,17 @@
7081 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
7082 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
7084 + /* Set these bits to enable statistics workaround. */
7085 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7086 + tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
7087 + tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
7088 + tp->coalesce_mode |= HOSTCC_MODE_ATTN;
7089 + tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
7092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7094 - tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
7095 + tg3_flag_set(tp, USE_PHYLIB);
7097 err = tg3_mdio_init(tp);
7099 @@ -13694,7 +14094,15 @@
7101 /* Initialize data/descriptor byte/word swapping. */
7102 val = tr32(GRC_MODE);
7103 - val &= GRC_MODE_HOST_STACKUP;
7104 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
7105 + val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
7106 + GRC_MODE_WORD_SWAP_B2HRX_DATA |
7107 + GRC_MODE_B2HRX_ENABLE |
7108 + GRC_MODE_HTX2B_ENABLE |
7109 + GRC_MODE_HOST_STACKUP);
7111 + val &= GRC_MODE_HOST_STACKUP;
7113 tw32(GRC_MODE, val | tp->grc_mode);
7115 tg3_switch_clocks(tp);
7116 @@ -13705,7 +14113,7 @@
7117 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
7119 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
7120 - (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
7121 + !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
7122 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
7124 if (chiprevid == CHIPREV_ID_5701_A0 ||
7125 @@ -13724,7 +14132,7 @@
7126 writel(0x00000000, sram_base + 4);
7127 writel(0xffffffff, sram_base + 4);
7128 if (readl(sram_base) != 0x00000000)
7129 - tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
7130 + tg3_flag_set(tp, PCIX_TARGET_HWBUG);
7134 @@ -13737,12 +14145,12 @@
7135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7136 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
7137 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
7138 - tp->tg3_flags2 |= TG3_FLG2_IS_5788;
7139 + tg3_flag_set(tp, IS_5788);
7141 - if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7142 - (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
7143 - tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
7144 - if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
7145 + if (!tg3_flag(tp, IS_5788) &&
7146 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7147 + tg3_flag_set(tp, TAGGED_STATUS);
7148 + if (tg3_flag(tp, TAGGED_STATUS)) {
7149 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
7150 HOSTCC_MODE_CLRTICK_TXBD);
7152 @@ -13752,9 +14160,8 @@
7155 /* Preserve the APE MAC_MODE bits */
7156 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7157 - tp->mac_mode = tr32(MAC_MODE) |
7158 - MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7159 + if (tg3_flag(tp, ENABLE_APE))
7160 + tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7162 tp->mac_mode = TG3_DEF_MAC_MODE;
7164 @@ -13800,9 +14207,9 @@
7165 * status register in those cases.
7167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7168 - tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
7169 + tg3_flag_set(tp, USE_LINKCHG_REG);
7171 - tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
7172 + tg3_flag_clear(tp, USE_LINKCHG_REG);
7174 /* The led_ctrl is set during tg3_phy_probe, here we might
7175 * have to force the link status polling mechanism based
7176 @@ -13812,19 +14219,19 @@
7177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
7178 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
7179 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
7180 - tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
7181 + tg3_flag_set(tp, USE_LINKCHG_REG);
7184 /* For all SERDES we poll the MAC status register. */
7185 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
7186 - tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
7187 + tg3_flag_set(tp, POLL_SERDES);
7189 - tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
7190 + tg3_flag_clear(tp, POLL_SERDES);
7192 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
7193 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
7194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
7195 - (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
7196 + tg3_flag(tp, PCIX_MODE)) {
7197 tp->rx_offset -= NET_IP_ALIGN;
7198 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
7199 tp->rx_copy_thresh = ~(u16)0;
7200 @@ -13845,7 +14252,7 @@
7201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7202 tp->rx_std_max_post = 8;
7204 - if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
7205 + if (tg3_flag(tp, ASPM_WORKAROUND))
7206 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
7207 PCIE_PWR_MGMT_L1_THRESH_MSK;
7209 @@ -13892,16 +14299,15 @@
7213 - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
7214 - (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7215 + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
7216 + tg3_flag(tp, 5780_CLASS)) {
7217 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
7219 if (tg3_nvram_lock(tp))
7220 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
7222 tg3_nvram_unlock(tp);
7223 - } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7224 - GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
7225 + } else if (tg3_flag(tp, 5717_PLUS)) {
7226 if (PCI_FUNC(tp->pdev->devfn) & 1)
7228 if (PCI_FUNC(tp->pdev->devfn) > 1)
7229 @@ -13926,7 +14332,7 @@
7232 /* Next, try NVRAM. */
7233 - if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
7234 + if (!tg3_flag(tp, NO_NVRAM) &&
7235 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
7236 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
7237 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
7238 @@ -13977,7 +14383,7 @@
7240 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
7241 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
7242 - !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7243 + !tg3_flag(tp, PCI_EXPRESS))
7246 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
7247 @@ -13990,7 +14396,7 @@
7251 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7252 + if (tg3_flag(tp, 57765_PLUS)) {
7253 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7256 @@ -14009,8 +14415,7 @@
7257 * other than 5700 and 5701 which do not implement the
7260 - if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
7261 - !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7262 + if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
7263 switch (cacheline_size) {
7266 @@ -14035,7 +14440,7 @@
7267 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
7270 - } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7271 + } else if (tg3_flag(tp, PCI_EXPRESS)) {
7272 switch (cacheline_size) {
7275 @@ -14184,13 +14589,19 @@
7277 #define TEST_BUFFER_SIZE 0x2000
7279 +static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
7280 + { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
7284 static int __devinit tg3_test_dma(struct tg3 *tp)
7287 u32 *buf, saved_dma_rwctrl;
7290 - buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
7291 + buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
7292 + &buf_dma, GFP_KERNEL);
7296 @@ -14201,13 +14612,13 @@
7298 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
7300 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7301 + if (tg3_flag(tp, 57765_PLUS))
7304 - if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7305 + if (tg3_flag(tp, PCI_EXPRESS)) {
7306 /* DMA read watermark not used on PCIE */
7307 tp->dma_rwctrl |= 0x00180000;
7308 - } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7309 + } else if (!tg3_flag(tp, PCIX_MODE)) {
7310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
7311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
7312 tp->dma_rwctrl |= 0x003f0000;
7313 @@ -14223,7 +14634,7 @@
7314 * do the less restrictive ONE_DMA workaround for
7315 * better performance.
7317 - if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
7318 + if (tg3_flag(tp, 40BIT_DMA_BUG) &&
7319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7320 tp->dma_rwctrl |= 0x8000;
7321 else if (ccval == 0x6 || ccval == 0x7)
7322 @@ -14352,17 +14763,11 @@
7324 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
7325 DMA_RWCTRL_WRITE_BNDRY_16) {
7326 - static struct pci_device_id dma_wait_state_chipsets[] = {
7327 - { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
7328 - PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
7332 /* DMA test passed without adjusting DMA boundary,
7333 * now look for chipsets that are known to expose the
7334 * DMA bug without failing the test.
7336 - if (pci_dev_present(dma_wait_state_chipsets)) {
7337 + if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
7338 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
7339 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
7341 @@ -14374,31 +14779,14 @@
7345 - pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
7346 + dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
7351 -static void __devinit tg3_init_link_config(struct tg3 *tp)
7353 - tp->link_config.advertising =
7354 - (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
7355 - ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
7356 - ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
7357 - ADVERTISED_Autoneg | ADVERTISED_MII);
7358 - tp->link_config.speed = SPEED_INVALID;
7359 - tp->link_config.duplex = DUPLEX_INVALID;
7360 - tp->link_config.autoneg = AUTONEG_ENABLE;
7361 - tp->link_config.active_speed = SPEED_INVALID;
7362 - tp->link_config.active_duplex = DUPLEX_INVALID;
7363 - tp->link_config.orig_speed = SPEED_INVALID;
7364 - tp->link_config.orig_duplex = DUPLEX_INVALID;
7365 - tp->link_config.orig_autoneg = AUTONEG_INVALID;
7368 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
7370 - if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7371 + if (tg3_flag(tp, 57765_PLUS)) {
7372 tp->bufmgr_config.mbuf_read_dma_low_water =
7373 DEFAULT_MB_RDMA_LOW_WATER_5705;
7374 tp->bufmgr_config.mbuf_mac_rx_low_water =
7375 @@ -14412,7 +14800,7 @@
7376 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
7377 tp->bufmgr_config.mbuf_high_water_jumbo =
7378 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
7379 - } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7380 + } else if (tg3_flag(tp, 5705_PLUS)) {
7381 tp->bufmgr_config.mbuf_read_dma_low_water =
7382 DEFAULT_MB_RDMA_LOW_WATER_5705;
7383 tp->bufmgr_config.mbuf_mac_rx_low_water =
7384 @@ -14476,6 +14864,7 @@
7385 case TG3_PHY_ID_BCM5718S: return "5718S";
7386 case TG3_PHY_ID_BCM57765: return "57765";
7387 case TG3_PHY_ID_BCM5719C: return "5719C";
7388 + case TG3_PHY_ID_BCM5720C: return "5720C";
7389 case TG3_PHY_ID_BCM8002: return "8002/serdes";
7390 case 0: return "serdes";
7391 default: return "unknown";
7392 @@ -14484,10 +14873,10 @@
7394 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
7396 - if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7397 + if (tg3_flag(tp, PCI_EXPRESS)) {
7398 strcpy(str, "PCI Express");
7400 - } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7401 + } else if (tg3_flag(tp, PCIX_MODE)) {
7402 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
7404 strcpy(str, "PCIX:");
7405 @@ -14506,12 +14895,12 @@
7406 strcat(str, "100MHz");
7408 strcpy(str, "PCI:");
7409 - if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
7410 + if (tg3_flag(tp, PCI_HIGH_SPEED))
7411 strcat(str, "66MHz");
7413 strcat(str, "33MHz");
7415 - if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
7416 + if (tg3_flag(tp, PCI_32BIT))
7417 strcat(str, ":32-bit");
7419 strcat(str, ":64-bit");
7420 @@ -14570,7 +14959,7 @@
7421 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
7424 - if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7425 + if (tg3_flag(tp, 5705_PLUS)) {
7426 ec->rx_coalesce_usecs_irq = 0;
7427 ec->tx_coalesce_usecs_irq = 0;
7428 ec->stats_block_coalesce_usecs = 0;
7429 @@ -14596,25 +14985,6 @@
7433 -static const struct net_device_ops tg3_netdev_ops_dma_bug = {
7434 - .ndo_open = tg3_open,
7435 - .ndo_stop = tg3_close,
7436 - .ndo_start_xmit = tg3_start_xmit_dma_bug,
7437 - .ndo_get_stats = tg3_get_stats,
7438 - .ndo_validate_addr = eth_validate_addr,
7439 - .ndo_set_multicast_list = tg3_set_rx_mode,
7440 - .ndo_set_mac_address = tg3_set_mac_addr,
7441 - .ndo_do_ioctl = tg3_ioctl,
7442 - .ndo_tx_timeout = tg3_tx_timeout,
7443 - .ndo_change_mtu = tg3_change_mtu,
7444 -#if TG3_VLAN_TAG_USED
7445 - .ndo_vlan_rx_register = tg3_vlan_rx_register,
7447 -#ifdef CONFIG_NET_POLL_CONTROLLER
7448 - .ndo_poll_controller = tg3_poll_controller,
7452 static int __devinit tg3_init_one(struct pci_dev *pdev,
7453 const struct pci_device_id *ent)
7455 @@ -14624,6 +14994,7 @@
7456 u32 sndmbx, rcvmbx, intmbx;
7458 u64 dma_mask, persist_dma_mask;
7461 printk_once(KERN_INFO "%s\n", version);
7463 @@ -14662,7 +15033,6 @@
7464 #if TG3_VLAN_TAG_USED
7465 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7468 tp = netdev_priv(dev);
7471 @@ -14707,13 +15077,12 @@
7472 goto err_out_free_dev;
7475 - tg3_init_link_config(tp);
7477 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
7478 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
7480 dev->ethtool_ops = &tg3_ethtool_ops;
7481 dev->watchdog_timeo = TG3_TX_TIMEOUT;
7482 + dev->netdev_ops = &tg3_netdev_ops;
7483 dev->irq = pdev->irq;
7485 err = tg3_get_invariants(tp);
7486 @@ -14723,23 +15092,15 @@
7487 goto err_out_iounmap;
7490 - if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
7491 - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7492 - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7493 - dev->netdev_ops = &tg3_netdev_ops;
7495 - dev->netdev_ops = &tg3_netdev_ops_dma_bug;
7498 /* The EPB bridge inside 5714, 5715, and 5780 and any
7499 * device behind the EPB cannot support DMA addresses > 40-bit.
7500 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
7501 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
7502 * do DMA address check in tg3_start_xmit().
7504 - if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
7505 + if (tg3_flag(tp, IS_5788))
7506 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
7507 - else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
7508 + else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
7509 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7510 #ifdef CONFIG_HIGHMEM
7511 dma_mask = DMA_BIT_MASK(64);
7512 @@ -14751,7 +15112,7 @@
7513 if (dma_mask > DMA_BIT_MASK(32)) {
7514 err = pci_set_dma_mask(pdev, dma_mask);
7516 - dev->features |= NETIF_F_HIGHDMA;
7517 + features |= NETIF_F_HIGHDMA;
7518 err = pci_set_consistent_dma_mask(pdev,
7521 @@ -14772,48 +15133,53 @@
7523 tg3_init_bufmgr_config(tp);
7525 - /* Selectively allow TSO based on operating conditions */
7526 - if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
7527 - (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
7528 - tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7530 - tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
7531 - tp->fw_needed = NULL;
7533 + features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7535 - if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
7536 - tp->fw_needed = FIRMWARE_TG3;
7537 + /* 5700 B0 chips do not support checksumming correctly due
7538 + * to hardware bugs.
7540 + if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
7541 + features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_GRO;
7543 + if (tg3_flag(tp, 5755_PLUS))
7544 + features |= NETIF_F_IPV6_CSUM;
7547 /* TSO is on by default on chips that support hardware TSO.
7548 * Firmware TSO on older chips gives lower performance, so it
7549 * is off by default, but can be enabled using ethtool.
7551 - if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
7552 - (dev->features & NETIF_F_IP_CSUM)) {
7553 - dev->features |= NETIF_F_TSO;
7554 + if ((tg3_flag(tp, HW_TSO_1) ||
7555 + tg3_flag(tp, HW_TSO_2) ||
7556 + tg3_flag(tp, HW_TSO_3)) &&
7557 + (features & NETIF_F_IP_CSUM)) {
7558 + features |= NETIF_F_TSO;
7559 vlan_features_add(dev, NETIF_F_TSO);
7561 - if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
7562 - (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
7563 - if (dev->features & NETIF_F_IPV6_CSUM) {
7564 - dev->features |= NETIF_F_TSO6;
7566 + if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
7567 + if (features & NETIF_F_IPV6_CSUM) {
7568 + features |= NETIF_F_TSO6;
7569 vlan_features_add(dev, NETIF_F_TSO6);
7571 - if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7572 + if (tg3_flag(tp, HW_TSO_3) ||
7573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7574 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
7575 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
7576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7577 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7578 - dev->features |= NETIF_F_TSO_ECN;
7579 + features |= NETIF_F_TSO_ECN;
7580 vlan_features_add(dev, NETIF_F_TSO_ECN);
7584 + dev->features |= features;
7585 + dev->vlan_features |= features;
7587 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
7588 - !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7589 + !tg3_flag(tp, TSO_CAPABLE) &&
7590 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
7591 - tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
7592 + tg3_flag_set(tp, MAX_RXPEND_64);
7593 tp->rx_pending = 63;
7596 @@ -14824,7 +15190,7 @@
7597 goto err_out_iounmap;
7600 - if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7601 + if (tg3_flag(tp, ENABLE_APE)) {
7602 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
7605 @@ -14835,7 +15201,7 @@
7607 tg3_ape_lock_init(tp);
7609 - if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7610 + if (tg3_flag(tp, ENABLE_ASF))
7611 tg3_read_dash_ver(tp);
7614 @@ -14856,14 +15222,10 @@
7615 goto err_out_apeunmap;
7618 - /* flow control autonegotiation is default behavior */
7619 - tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7620 - tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
7622 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
7623 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
7624 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7625 - for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
7626 + for (i = 0; i < tp->irq_max; i++) {
7627 struct tg3_napi *tnapi = &tp->napi[i];
7630 @@ -14878,15 +15240,12 @@
7631 tnapi->consmbox = rcvmbx;
7632 tnapi->prodmbox = sndmbx;
7636 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
7637 - netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
7640 tnapi->coal_now = HOSTCC_MODE_NOW;
7641 - netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
7644 - if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
7645 + if (!tg3_flag(tp, SUPPORT_MSIX))
7649 @@ -14917,6 +15276,9 @@
7650 goto err_out_apeunmap;
7653 + /* RHEL: Set an initial value for operstate, after registration */
7654 + netif_carrier_off(dev);
7656 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
7657 tp->board_part_number,
7658 tp->pci_chip_rev_id,
7659 @@ -14940,21 +15302,25 @@
7660 ethtype = "10/100/1000Base-T";
7662 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
7663 - "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
7664 - (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
7665 + "(WireSpeed[%d], EEE[%d])\n",
7666 + tg3_phy_string(tp), ethtype,
7667 + (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
7668 + (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
7671 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
7672 - (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
7673 - (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
7674 + tg3_flag(tp, RX_CHECKSUMS) != 0,
7675 + tg3_flag(tp, USE_LINKCHG_REG) != 0,
7676 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
7677 - (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
7678 - (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
7679 + tg3_flag(tp, ENABLE_ASF) != 0,
7680 + tg3_flag(tp, TSO_CAPABLE) != 0);
7681 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
7683 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
7684 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
7686 + pci_save_state(pdev);
7691 @@ -14993,7 +15359,7 @@
7693 flush_scheduled_work();
7695 - if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
7696 + if (tg3_flag(tp, USE_PHYLIB)) {
7700 @@ -15014,19 +15380,14 @@
7704 -static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
7705 +#ifdef CONFIG_PM_SLEEP
7706 +static int tg3_suspend(struct device *device)
7708 + struct pci_dev *pdev = to_pci_dev(device);
7709 struct net_device *dev = pci_get_drvdata(pdev);
7710 struct tg3 *tp = netdev_priv(dev);
7711 - pci_power_t target_state;
7714 - /* PCI register 4 needs to be saved whether netif_running() or not.
7715 - * MSI address and data need to be saved if using MSI and
7716 - * netif_running().
7718 - pci_save_state(pdev);
7720 if (!netif_running(dev))
7723 @@ -15044,18 +15405,16 @@
7725 tg3_full_lock(tp, 0);
7726 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7727 - tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7728 + tg3_flag_clear(tp, INIT_COMPLETE);
7729 tg3_full_unlock(tp);
7731 - target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
7733 - err = tg3_set_power_state(tp, target_state);
7734 + err = tg3_power_down_prepare(tp);
7738 tg3_full_lock(tp, 0);
7740 - tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7741 + tg3_flag_set(tp, INIT_COMPLETE);
7742 err2 = tg3_restart_hw(tp, 1);
7745 @@ -15076,26 +15435,21 @@
7749 -static int tg3_resume(struct pci_dev *pdev)
7750 +static int tg3_resume(struct device *device)
7752 + struct pci_dev *pdev = to_pci_dev(device);
7753 struct net_device *dev = pci_get_drvdata(pdev);
7754 struct tg3 *tp = netdev_priv(dev);
7757 - pci_restore_state(tp->pdev);
7759 if (!netif_running(dev))
7762 - err = tg3_set_power_state(tp, PCI_D0);
7766 netif_device_attach(dev);
7768 tg3_full_lock(tp, 0);
7770 - tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7771 + tg3_flag_set(tp, INIT_COMPLETE);
7772 err = tg3_restart_hw(tp, 1);
7775 @@ -15114,13 +15468,166 @@
7779 +static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
7780 +#define TG3_PM_OPS (&tg3_pm_ops)
7784 +#define TG3_PM_OPS NULL
7786 +#endif /* CONFIG_PM_SLEEP */
7789 + * tg3_io_error_detected - called when PCI error is detected
7790 + * @pdev: Pointer to PCI device
7791 + * @state: The current pci connection state
7793 + * This function is called after a PCI bus error affecting
7794 + * this device has been detected.
7796 +static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
7797 + pci_channel_state_t state)
7799 + struct net_device *netdev = pci_get_drvdata(pdev);
7800 + struct tg3 *tp = netdev_priv(netdev);
7801 + pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
7803 + netdev_info(netdev, "PCI I/O error detected\n");
7807 + if (!netif_running(netdev))
7812 + tg3_netif_stop(tp);
7814 + del_timer_sync(&tp->timer);
7815 + tg3_flag_clear(tp, RESTART_TIMER);
7817 + /* Want to make sure that the reset task doesn't run */
7818 + cancel_work_sync(&tp->reset_task);
7819 + tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7820 + tg3_flag_clear(tp, RESTART_TIMER);
7822 + netif_device_detach(netdev);
7824 + /* Clean up software state, even if MMIO is blocked */
7825 + tg3_full_lock(tp, 0);
7826 + tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
7827 + tg3_full_unlock(tp);
7830 + if (state == pci_channel_io_perm_failure)
7831 + err = PCI_ERS_RESULT_DISCONNECT;
7833 + pci_disable_device(pdev);
7841 + * tg3_io_slot_reset - called after the pci bus has been reset.
7842 + * @pdev: Pointer to PCI device
7844 + * Restart the card from scratch, as if from a cold-boot.
7845 + * At this point, the card has exprienced a hard reset,
7846 + * followed by fixups by BIOS, and has its config space
7847 + * set up identically to what it was at cold boot.
7849 +static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
7851 + struct net_device *netdev = pci_get_drvdata(pdev);
7852 + struct tg3 *tp = netdev_priv(netdev);
7853 + pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
7858 + if (pci_enable_device(pdev)) {
7859 + netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
7863 + pci_set_master(pdev);
7864 + pci_restore_state(pdev);
7865 + pci_save_state(pdev);
7867 + if (!netif_running(netdev)) {
7868 + rc = PCI_ERS_RESULT_RECOVERED;
7872 + err = tg3_power_up(tp);
7874 + netdev_err(netdev, "Failed to restore register access.\n");
7878 + rc = PCI_ERS_RESULT_RECOVERED;
7887 + * tg3_io_resume - called when traffic can start flowing again.
7888 + * @pdev: Pointer to PCI device
7890 + * This callback is called when the error recovery driver tells
7891 + * us that its OK to resume normal operation.
7893 +static void tg3_io_resume(struct pci_dev *pdev)
7895 + struct net_device *netdev = pci_get_drvdata(pdev);
7896 + struct tg3 *tp = netdev_priv(netdev);
7901 + if (!netif_running(netdev))
7904 + tg3_full_lock(tp, 0);
7905 + tg3_flag_set(tp, INIT_COMPLETE);
7906 + err = tg3_restart_hw(tp, 1);
7907 + tg3_full_unlock(tp);
7909 + netdev_err(netdev, "Cannot restart hardware after reset.\n");
7913 + netif_device_attach(netdev);
7915 + tp->timer.expires = jiffies + tp->timer_offset;
7916 + add_timer(&tp->timer);
7918 + tg3_netif_start(tp);
7920 + tg3_phy_start(tp);
7926 +static struct pci_error_handlers tg3_err_handler = {
7927 + .error_detected = tg3_io_error_detected,
7928 + .slot_reset = tg3_io_slot_reset,
7929 + .resume = tg3_io_resume
7932 static struct pci_driver tg3_driver = {
7933 .name = DRV_MODULE_NAME,
7934 .id_table = tg3_pci_tbl,
7935 .probe = tg3_init_one,
7936 .remove = __devexit_p(tg3_remove_one),
7937 - .suspend = tg3_suspend,
7938 - .resume = tg3_resume
7939 + .err_handler = &tg3_err_handler,
7940 + .driver.pm = TG3_PM_OPS,
7943 static int __init tg3_init(void)
7944 --- /build/BUILD/kernel-2.6.32-131.0.15.el6/linux-2.6.32-27.mlab.mlab.i686/drivers/net/tg3.h 2012-06-19 17:20:05.376166782 -0400
7945 +++ linux-2.6.32-220.el6/drivers/net/tg3.h 2012-06-19 17:20:29.182150176 -0400
7947 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
7948 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
7949 * Copyright (C) 2004 Sun Microsystems Inc.
7950 - * Copyright (C) 2007-2010 Broadcom Corporation.
7951 + * Copyright (C) 2007-2011 Broadcom Corporation.
7957 #define TG3_64BIT_REG_HIGH 0x00UL
7958 #define TG3_64BIT_REG_LOW 0x04UL
7959 +#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
7961 /* Descriptor block info. */
7962 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
7964 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
7965 #define TG3_BDINFO_SIZE 0x10UL
7967 -#define TG3_RX_INTERNAL_RING_SZ_5906 32
7969 -#define RX_STD_MAX_SIZE_5705 512
7970 -#define RX_STD_MAX_SIZE_5717 2048
7971 -#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
7972 +#define TG3_RX_STD_MAX_SIZE_5700 512
7973 +#define TG3_RX_STD_MAX_SIZE_5717 2048
7974 +#define TG3_RX_JMB_MAX_SIZE_5700 256
7975 +#define TG3_RX_JMB_MAX_SIZE_5717 1024
7976 +#define TG3_RX_RET_MAX_SIZE_5700 1024
7977 +#define TG3_RX_RET_MAX_SIZE_5705 512
7978 +#define TG3_RX_RET_MAX_SIZE_5717 4096
7980 /* First 256 bytes are a mirror of PCI config space. */
7981 #define TG3PCI_VENDOR 0x00000000
7983 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
7984 #define TG3PCI_DEVICE_TIGON3_5717 0x1655
7985 #define TG3PCI_DEVICE_TIGON3_5718 0x1656
7986 -#define TG3PCI_DEVICE_TIGON3_5724 0x165c
7987 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1
7988 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5
7989 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0
7991 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2
7992 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6
7993 #define TG3PCI_DEVICE_TIGON3_5719 0x1657
7994 +#define TG3PCI_DEVICE_TIGON3_5720 0x165f
7995 /* 0x04 --> 0x2c unused */
7996 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
7997 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
7999 #define CHIPREV_ID_57780_A1 0x57780001
8000 #define CHIPREV_ID_5717_A0 0x05717000
8001 #define CHIPREV_ID_57765_A0 0x57785000
8002 +#define CHIPREV_ID_5719_A0 0x05719000
8003 +#define CHIPREV_ID_5720_A0 0x05720000
8004 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
8005 #define ASIC_REV_5700 0x07
8006 #define ASIC_REV_5701 0x00
8008 #define ASIC_REV_5717 0x5717
8009 #define ASIC_REV_57765 0x57785
8010 #define ASIC_REV_5719 0x5719
8011 +#define ASIC_REV_5720 0x5720
8012 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
8013 #define CHIPREV_5700_AX 0x70
8014 #define CHIPREV_5700_BX 0x71
8016 #define CHIPREV_5750_BX 0x41
8017 #define CHIPREV_5784_AX 0x57840
8018 #define CHIPREV_5761_AX 0x57610
8019 +#define CHIPREV_57765_AX 0x577650
8020 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
8021 #define METAL_REV_A0 0x00
8022 #define METAL_REV_A1 0x01
8024 #define METAL_REV_B2 0x02
8025 #define TG3PCI_DMA_RW_CTRL 0x0000006c
8026 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
8027 +#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
8028 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
8029 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
8030 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
8032 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
8033 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
8034 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
8035 +#define TX_MODE_JMB_FRM_LEN 0x00400000
8036 +#define TX_MODE_CNT_DN_MODE 0x00800000
8037 #define MAC_TX_STATUS 0x00000460
8038 #define TX_STATUS_XOFFED 0x00000001
8039 #define TX_STATUS_SENT_XOFF 0x00000002
8041 #define TX_LENGTHS_IPG_SHIFT 8
8042 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
8043 #define TX_LENGTHS_IPG_CRS_SHIFT 12
8044 +#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
8045 +#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
8046 #define MAC_RX_MODE 0x00000468
8047 #define RX_MODE_RESET 0x00000001
8048 #define RX_MODE_ENABLE 0x00000002
8049 @@ -1079,6 +1091,9 @@
8050 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
8051 /* 0x3620 --> 0x3630 unused */
8053 +#define TG3_CPMU_CLCK_ORIDE 0x00003624
8054 +#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
8056 #define TG3_CPMU_CLCK_STAT 0x00003630
8057 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
8058 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
8059 @@ -1106,7 +1121,7 @@
8060 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
8061 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000070ff
8062 #define TG3_CPMU_EEE_DBTMR2 0x000036b8
8063 -#define TG3_CPMU_DBTMR1_APE_TX_2047US 0x07ff0000
8064 +#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
8065 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000070ff
8066 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
8067 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
8068 @@ -1188,6 +1203,7 @@
8069 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
8070 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
8071 #define HOSTCC_FLOW_ATTN 0x00003c48
8072 +#define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
8073 /* 0x3c4c --> 0x3c50 unused */
8074 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
8075 #define HOSTCC_STD_CON_IDX 0x00003c54
8076 @@ -1321,6 +1337,7 @@
8077 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
8078 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000
8079 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000
8080 +#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
8081 #define RDMAC_STATUS 0x00004804
8082 #define RDMAC_STATUS_TGTABORT 0x00000004
8083 #define RDMAC_STATUS_MSTABORT 0x00000008
8084 @@ -1334,6 +1351,10 @@
8086 #define TG3_RDMA_RSRVCTRL_REG 0x00004900
8087 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
8088 +#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
8089 +#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
8090 +#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
8091 +#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
8092 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
8093 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
8094 /* 0x4904 --> 0x4910 unused */
8095 @@ -1593,6 +1614,7 @@
8096 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
8097 #define MSGINT_MODE_MULTIVEC_EN 0x00000080
8098 #define MSGINT_STATUS 0x00006004
8099 +#define MSGINT_STATUS_MSI_REQ 0x00000001
8100 #define MSGINT_FIFO 0x00006008
8101 /* 0x600c --> 0x6400 unused */
8103 @@ -1609,6 +1631,8 @@
8104 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
8105 #define GRC_MODE_BSWAP_DATA 0x00000010
8106 #define GRC_MODE_WSWAP_DATA 0x00000020
8107 +#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
8108 +#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
8109 #define GRC_MODE_SPLITHDR 0x00000100
8110 #define GRC_MODE_NOFRM_CRACKING 0x00000200
8111 #define GRC_MODE_INCL_CRC 0x00000400
8112 @@ -1616,8 +1640,10 @@
8113 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
8114 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
8115 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
8116 +#define GRC_MODE_B2HRX_ENABLE 0x00008000
8117 #define GRC_MODE_HOST_STACKUP 0x00010000
8118 #define GRC_MODE_HOST_SENDBDS 0x00020000
8119 +#define GRC_MODE_HTX2B_ENABLE 0x00040000
8120 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
8121 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
8122 #define GRC_MODE_PCIE_TL_SEL 0x00000000
8123 @@ -1814,6 +1840,38 @@
8124 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
8125 #define FLASH_5717VENDOR_ST_25USPT 0x03400002
8126 #define FLASH_5717VENDOR_ST_45USPT 0x03400001
8127 +#define FLASH_5720_EEPROM_HD 0x00000001
8128 +#define FLASH_5720_EEPROM_LD 0x00000003
8129 +#define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
8130 +#define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
8131 +#define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
8132 +#define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
8133 +#define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
8134 +#define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
8135 +#define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
8136 +#define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
8137 +#define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
8138 +#define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
8139 +#define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
8140 +#define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
8141 +#define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
8142 +#define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
8143 +#define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
8144 +#define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
8145 +#define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
8146 +#define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
8147 +#define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
8148 +#define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
8149 +#define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
8150 +#define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
8151 +#define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
8152 +#define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
8153 +#define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
8154 +#define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
8155 +#define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
8156 +#define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
8157 +#define FLASH_5720VENDOR_ST_25USPT 0x03c00002
8158 +#define FLASH_5720VENDOR_ST_45USPT 0x03c00001
8159 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
8160 #define FLASH_5752PAGE_SIZE_256 0x00000000
8161 #define FLASH_5752PAGE_SIZE_512 0x10000000
8162 @@ -1895,11 +1953,16 @@
8164 /* Alternate PCIE definitions */
8165 #define TG3_PCIE_TLDLPL_PORT 0x00007c00
8166 +#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
8167 +#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
8168 +#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
8169 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
8170 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
8171 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
8172 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
8174 +#define TG3_REG_BLK_SIZE 0x00008000
8176 /* OTP bit definitions */
8177 #define TG3_OTP_AGCTGT_MASK 0x000000e0
8178 #define TG3_OTP_AGCTGT_SHIFT 1
8179 @@ -1943,6 +2006,7 @@
8180 #define TG3_EEPROM_SB_REVISION_3 0x00030000
8181 #define TG3_EEPROM_SB_REVISION_4 0x00040000
8182 #define TG3_EEPROM_SB_REVISION_5 0x00050000
8183 +#define TG3_EEPROM_SB_REVISION_6 0x00060000
8184 #define TG3_EEPROM_MAGIC_HW 0xabcd
8185 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
8187 @@ -1950,7 +2014,9 @@
8188 #define TG3_NVM_DIR_END 0x78
8189 #define TG3_NVM_DIRENT_SIZE 0xc
8190 #define TG3_NVM_DIRTYPE_SHIFT 24
8191 +#define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
8192 #define TG3_NVM_DIRTYPE_ASFINI 1
8193 +#define TG3_NVM_DIRTYPE_EXTVPD 20
8194 #define TG3_NVM_PTREV_BCVER 0x94
8195 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00
8196 #define TG3_NVM_BCVER_MAJSFT 8
8197 @@ -1962,6 +2028,7 @@
8198 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
8199 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
8200 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
8201 +#define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
8202 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
8203 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
8204 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
8205 @@ -2073,6 +2140,13 @@
8206 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
8207 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
8209 +#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
8210 +#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
8211 +#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
8213 +#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
8214 +#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
8217 /* Currently this is fixed. */
8218 #define TG3_PHY_MII_ADDR 0x01
8219 @@ -2107,9 +2181,13 @@
8221 #define MII_TG3_DSP_TAP1 0x0001
8222 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
8223 +#define MII_TG3_DSP_TAP26 0x001a
8224 +#define MII_TG3_DSP_TAP26_ALNOKO 0x0001
8225 +#define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
8226 +#define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
8227 #define MII_TG3_DSP_AADJ1CH0 0x001f
8228 #define MII_TG3_DSP_CH34TP2 0x4022
8229 -#define MII_TG3_DSP_CH34TP2_HIBW01 0x0010
8230 +#define MII_TG3_DSP_CH34TP2_HIBW01 0x017b
8231 #define MII_TG3_DSP_AADJ1CH3 0x601f
8232 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
8233 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
8234 @@ -2120,23 +2198,30 @@
8235 #define MII_TG3_DSP_EXP96 0x0f96
8236 #define MII_TG3_DSP_EXP97 0x0f97
8238 -#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
8239 +#define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
8241 +#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
8242 +#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
8243 +#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
8244 +#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
8246 +#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
8247 +#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
8248 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
8249 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
8250 +#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
8251 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
8252 -#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
8254 -#define MII_TG3_AUXCTL_MISC_WREN 0x8000
8255 -#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
8256 -#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
8257 +#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
8259 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
8260 +#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
8261 +#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
8262 +#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
8263 +#define MII_TG3_AUXCTL_MISC_WREN 0x8000
8265 -#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
8266 -#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
8267 -#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
8269 -#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
8270 +#define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
8271 #define MII_TG3_AUX_STAT_LPASS 0x0004
8272 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
8273 #define MII_TG3_AUX_STAT_10HALF 0x0100
8274 @@ -2226,7 +2311,7 @@
8275 #define TG3_APE_HOST_SEG_SIG 0x4200
8276 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
8277 #define TG3_APE_HOST_SEG_LEN 0x4204
8278 -#define APE_HOST_SEG_LEN_MAGIC 0x0000001c
8279 +#define APE_HOST_SEG_LEN_MAGIC 0x00000020
8280 #define TG3_APE_HOST_INIT_COUNT 0x4208
8281 #define TG3_APE_HOST_DRIVER_ID 0x420c
8282 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000
8283 @@ -2238,6 +2323,12 @@
8284 #define APE_HOST_HEARTBEAT_INT_DISABLE 0
8285 #define APE_HOST_HEARTBEAT_INT_5SEC 5000
8286 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
8287 +#define TG3_APE_HOST_DRVR_STATE 0x421c
8288 +#define TG3_APE_HOST_DRVR_STATE_START 0x00000001
8289 +#define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
8290 +#define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
8291 +#define TG3_APE_HOST_WOL_SPEED 0x4224
8292 +#define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
8294 #define TG3_APE_EVENT_STATUS 0x4300
8296 @@ -2548,7 +2639,12 @@
8297 tg3_stat64_t nic_avoided_irqs;
8298 tg3_stat64_t nic_tx_threshold_hit;
8300 - u8 __reserved4[0xb00-0x9c0];
8301 + /* NOT a part of the hardware statistics block format.
8302 + * These stats are here as storage for tg3_periodic_fetch_stats().
8304 + tg3_stat64_t mbuf_lwm_thresh_hit;
8306 + u8 __reserved4[0xb00-0x9c8];
8309 /* 'mapping' is superfluous as the chip does not write into
8310 @@ -2684,6 +2780,8 @@
8312 u64 nic_avoided_irqs;
8313 u64 nic_tx_threshold_hit;
8315 + u64 mbuf_lwm_thresh_hit;
8318 struct tg3_rx_prodring_set {
8319 @@ -2699,13 +2797,15 @@
8320 dma_addr_t rx_jmb_mapping;
8323 -#define TG3_IRQ_MAX_VECS 5
8324 +#define TG3_IRQ_MAX_VECS_RSS 5
8325 +#define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
8328 struct napi_struct napi ____cacheline_aligned;
8330 struct tg3_hw_status *hw_status;
8336 @@ -2713,12 +2813,14 @@
8346 u16 *rx_rcb_prod_idx;
8347 - struct tg3_rx_prodring_set *prodring;
8348 + struct tg3_rx_prodring_set prodring;
8350 struct tg3_rx_buffer_desc *rx_rcb;
8351 struct tg3_tx_buffer_desc *tx_ring;
8352 @@ -2732,6 +2834,87 @@
8353 unsigned int irq_vec;
8357 + TG3_FLAG_TAGGED_STATUS = 0,
8358 + TG3_FLAG_TXD_MBOX_HWBUG,
8359 + TG3_FLAG_USE_LINKCHG_REG,
8360 + TG3_FLAG_ERROR_PROCESSED,
8361 + TG3_FLAG_ENABLE_ASF,
8362 + TG3_FLAG_ASPM_WORKAROUND,
8363 + TG3_FLAG_POLL_SERDES,
8364 + TG3_FLAG_MBOX_WRITE_REORDER,
8365 + TG3_FLAG_PCIX_TARGET_HWBUG,
8366 + TG3_FLAG_WOL_SPEED_100MB,
8367 + TG3_FLAG_WOL_ENABLE,
8368 + TG3_FLAG_EEPROM_WRITE_PROT,
8370 + TG3_FLAG_NVRAM_BUFFERED,
8371 + TG3_FLAG_SUPPORT_MSI,
8372 + TG3_FLAG_SUPPORT_MSIX,
8373 + TG3_FLAG_PCIX_MODE,
8374 + TG3_FLAG_PCI_HIGH_SPEED,
8375 + TG3_FLAG_PCI_32BIT,
8376 + TG3_FLAG_SRAM_USE_CONFIG,
8377 + TG3_FLAG_TX_RECOVERY_PENDING,
8379 + TG3_FLAG_JUMBO_RING_ENABLE,
8380 + TG3_FLAG_PAUSE_AUTONEG,
8381 + TG3_FLAG_CPMU_PRESENT,
8382 + TG3_FLAG_40BIT_DMA_BUG,
8383 + TG3_FLAG_BROKEN_CHECKSUMS,
8384 + TG3_FLAG_JUMBO_CAPABLE,
8385 + TG3_FLAG_CHIP_RESETTING,
8386 + TG3_FLAG_INIT_COMPLETE,
8387 + TG3_FLAG_RESTART_TIMER,
8390 + TG3_FLAG_MAX_RXPEND_64,
8391 + TG3_FLAG_TSO_CAPABLE,
8392 + TG3_FLAG_PCI_EXPRESS,
8393 + TG3_FLAG_ASF_NEW_HANDSHAKE,
8394 + TG3_FLAG_HW_AUTONEG,
8397 + TG3_FLAG_HW_TSO_1,
8398 + TG3_FLAG_5705_PLUS,
8399 + TG3_FLAG_5750_PLUS,
8400 + TG3_FLAG_HW_TSO_3,
8401 + TG3_FLAG_USING_MSI,
8402 + TG3_FLAG_USING_MSIX,
8403 + TG3_FLAG_ICH_WORKAROUND,
8404 + TG3_FLAG_5780_CLASS,
8405 + TG3_FLAG_HW_TSO_2,
8406 + TG3_FLAG_1SHOT_MSI,
8407 + TG3_FLAG_NO_FWARE_REPORTED,
8408 + TG3_FLAG_NO_NVRAM_ADDR_TRANS,
8409 + TG3_FLAG_ENABLE_APE,
8410 + TG3_FLAG_PROTECTED_NVRAM,
8411 + TG3_FLAG_5701_DMA_BUG,
8412 + TG3_FLAG_USE_PHYLIB,
8413 + TG3_FLAG_MDIOBUS_INITED,
8414 + TG3_FLAG_LRG_PROD_RING_CAP,
8415 + TG3_FLAG_RGMII_INBAND_DISABLE,
8416 + TG3_FLAG_RGMII_EXT_IBND_RX_EN,
8417 + TG3_FLAG_RGMII_EXT_IBND_TX_EN,
8418 + TG3_FLAG_CLKREQ_BUG,
8419 + TG3_FLAG_5755_PLUS,
8420 + TG3_FLAG_NO_NVRAM,
8421 + TG3_FLAG_ENABLE_RSS,
8422 + TG3_FLAG_ENABLE_TSS,
8423 + TG3_FLAG_4G_DMA_BNDRY_BUG,
8424 + TG3_FLAG_40BIT_DMA_LIMIT_BUG,
8425 + TG3_FLAG_SHORT_DMA_BUG,
8426 + TG3_FLAG_USE_JUMBO_BDFLAG,
8427 + TG3_FLAG_L1PLLPD_EN,
8428 + TG3_FLAG_57765_PLUS,
8429 + TG3_FLAG_APE_HAS_NCSI,
8430 + TG3_FLAG_5717_PLUS,
8431 + TG3_FLAG_RX_CHECKSUMS,
8433 + /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
8434 + TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
8438 /* begin "general, frequently-used members" cacheline section */
8440 @@ -2755,7 +2938,7 @@
8441 /* SMP locking strategy:
8443 * lock: Held during reset, PHY access, timer, and when
8444 - * updating tg3_flags and tg3_flags2.
8445 + * updating tg3_flags.
8447 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
8448 * netif_tx_lock when it needs to call
8449 @@ -2808,8 +2991,6 @@
8450 struct vlan_group *vlgrp;
8453 - struct tg3_rx_prodring_set prodring[TG3_IRQ_MAX_VECS];
8456 /* begin "everything else" cacheline(s) section */
8457 struct net_device_stats net_stats;
8458 @@ -2817,93 +2998,13 @@
8459 struct tg3_ethtool_stats estats;
8460 struct tg3_ethtool_stats estats_prev;
8462 + DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
8465 unsigned long phy_crc_errors;
8466 unsigned long last_event_jiffies;
8470 -#define TG3_FLAG_TAGGED_STATUS 0x00000001
8471 -#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
8472 -#define TG3_FLAG_RX_CHECKSUMS 0x00000004
8473 -#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
8474 -#define TG3_FLAG_ENABLE_ASF 0x00000020
8475 -#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
8476 -#define TG3_FLAG_POLL_SERDES 0x00000080
8477 -#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
8478 -#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
8479 -#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
8480 -#define TG3_FLAG_WOL_ENABLE 0x00000800
8481 -#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
8482 -#define TG3_FLAG_NVRAM 0x00002000
8483 -#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
8484 -#define TG3_FLAG_SUPPORT_MSI 0x00008000
8485 -#define TG3_FLAG_SUPPORT_MSIX 0x00010000
8486 -#define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \
8487 - TG3_FLAG_SUPPORT_MSIX)
8488 -#define TG3_FLAG_PCIX_MODE 0x00020000
8489 -#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
8490 -#define TG3_FLAG_PCI_32BIT 0x00080000
8491 -#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
8492 -#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
8493 -#define TG3_FLAG_WOL_CAP 0x00400000
8494 -#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
8495 -#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
8496 -#define TG3_FLAG_CPMU_PRESENT 0x04000000
8497 -#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
8498 -#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
8499 -#define TG3_FLAG_JUMBO_CAPABLE 0x20000000
8500 -#define TG3_FLAG_CHIP_RESETTING 0x40000000
8501 -#define TG3_FLAG_INIT_COMPLETE 0x80000000
8503 -#define TG3_FLG2_RESTART_TIMER 0x00000001
8504 -#define TG3_FLG2_TSO_BUG 0x00000002
8505 -#define TG3_FLG2_IS_5788 0x00000008
8506 -#define TG3_FLG2_MAX_RXPEND_64 0x00000010
8507 -#define TG3_FLG2_TSO_CAPABLE 0x00000020
8508 -#define TG3_FLG2_PCI_EXPRESS 0x00000200
8509 -#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
8510 -#define TG3_FLG2_HW_AUTONEG 0x00000800
8511 -#define TG3_FLG2_IS_NIC 0x00001000
8512 -#define TG3_FLG2_FLASH 0x00008000
8513 -#define TG3_FLG2_HW_TSO_1 0x00010000
8514 -#define TG3_FLG2_5705_PLUS 0x00040000
8515 -#define TG3_FLG2_5750_PLUS 0x00080000
8516 -#define TG3_FLG2_HW_TSO_3 0x00100000
8517 -#define TG3_FLG2_USING_MSI 0x00200000
8518 -#define TG3_FLG2_USING_MSIX 0x00400000
8519 -#define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
8520 - TG3_FLG2_USING_MSIX)
8521 -#define TG3_FLG2_ICH_WORKAROUND 0x02000000
8522 -#define TG3_FLG2_5780_CLASS 0x04000000
8523 -#define TG3_FLG2_HW_TSO_2 0x08000000
8524 -#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
8525 - TG3_FLG2_HW_TSO_2 | \
8526 - TG3_FLG2_HW_TSO_3)
8527 -#define TG3_FLG2_1SHOT_MSI 0x10000000
8528 -#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
8530 -#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
8531 -#define TG3_FLG3_ENABLE_APE 0x00000002
8532 -#define TG3_FLG3_PROTECTED_NVRAM 0x00000004
8533 -#define TG3_FLG3_5701_DMA_BUG 0x00000008
8534 -#define TG3_FLG3_USE_PHYLIB 0x00000010
8535 -#define TG3_FLG3_MDIOBUS_INITED 0x00000020
8536 -#define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100
8537 -#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
8538 -#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
8539 -#define TG3_FLG3_CLKREQ_BUG 0x00000800
8540 -#define TG3_FLG3_5755_PLUS 0x00002000
8541 -#define TG3_FLG3_NO_NVRAM 0x00004000
8542 -#define TG3_FLG3_ENABLE_RSS 0x00020000
8543 -#define TG3_FLG3_ENABLE_TSS 0x00040000
8544 -#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
8545 -#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
8546 -#define TG3_FLG3_SHORT_DMA_BUG 0x00200000
8547 -#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
8548 -#define TG3_FLG3_L1PLLPD_EN 0x00800000
8549 -#define TG3_FLG3_5717_PLUS 0x01000000
8551 struct timer_list timer;
8553 u16 timer_multiplier;
8554 @@ -2974,6 +3075,7 @@
8555 #define TG3_PHY_ID_BCM5718S 0xbc050ff0
8556 #define TG3_PHY_ID_BCM57765 0x5c0d8a40
8557 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20
8558 +#define TG3_PHY_ID_BCM5720C 0x5c0d8b60
8559 #define TG3_PHY_ID_BCM5906 0xdc00ac40
8560 #define TG3_PHY_ID_BCM8002 0x60010140
8561 #define TG3_PHY_ID_INVALID 0xffffffff
8562 @@ -3040,6 +3142,7 @@
8566 +#define TG3_NVRAM_SIZE_2KB 0x00000800
8567 #define TG3_NVRAM_SIZE_64KB 0x00010000
8568 #define TG3_NVRAM_SIZE_128KB 0x00020000
8569 #define TG3_NVRAM_SIZE_256KB 0x00040000
8570 @@ -3055,6 +3158,9 @@
8571 #define JEDEC_SAIFUN 0x4f
8572 #define JEDEC_SST 0xbf
8574 +#define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
8575 +#define ATMEL_AT24C02_PAGE_SIZE (8)
8577 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
8578 #define ATMEL_AT24C64_PAGE_SIZE (32)