2 * Philips UDA1341 mixer device driver
3 * Copyright (c) 2002 Tomas Kasparek <tomas.kasparek@seznam.cz>
5 * Portions are Copyright (C) 2000 Lernout & Hauspie Speech Products, N.V.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License.
12 * 2002-03-13 Tomas Kasparek initial release - based on uda1341.c from OSS
13 * 2002-03-28 Tomas Kasparek basic mixer is working (volume, bass, treble)
14 * 2002-03-30 Tomas Kasparek proc filesystem support, complete mixer and DSP
16 * 2002-04-12 Tomas Kasparek proc interface update, code cleanup
17 * 2002-05-12 Tomas Kasparek another code cleanup
20 /* $Id: uda1341.c,v 1.10 2003/10/23 14:34:52 perex Exp $ */
22 #include <sound/driver.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/ioctl.h>
30 #include <asm/uaccess.h>
32 #include <sound/core.h>
33 #include <sound/control.h>
34 #include <sound/initval.h>
35 #include <sound/info.h>
37 #include <linux/l3/l3.h>
39 #include <sound/uda1341.h>
41 /* {{{ HW regs definition */
45 #define STAT_MASK 0x80
50 #define DATA_MASK 0xc0
52 #define IS_DATA0(x) ((x) >= data0_0 && (x) <= data0_2)
53 #define IS_DATA1(x) ((x) == data1)
54 #define IS_STATUS(x) ((x) == stat0 || (x) == stat1)
55 #define IS_EXTEND(x) ((x) >= ext0 && (x) <= ext6)
59 enum uda1341_regs_names {
76 const char *uda1341_reg_names[] = {
92 const int uda1341_enum_items[] = {
93 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
94 2, //peak - before/after
95 4, //deemp - none/32/44.1/48
97 4, //filter - flat/min/min/max
99 4, //mixer - differ/line/mic/mixer
103 const char ** uda1341_enum_names[] = {
104 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
105 peak_names, //peak - before/after
106 deemp_names, //deemp - none/32/44.1/48
108 filter_names, //filter - flat/min/min/max
110 mixer_names, //mixer - differ/line/mic/mixer
111 NULL, NULL, NULL, NULL, NULL,
114 typedef int uda1341_cfg[CMD_LAST];
116 typedef struct uda1341 uda1341_t;
119 int (*write) (struct l3_client *uda1341, unsigned short reg, unsigned short val);
120 int (*read) (struct l3_client *uda1341, unsigned short reg);
121 unsigned char regs[uda1341_reg_last];
127 unsigned char suspend_regs[uda1341_reg_last];
128 uda1341_cfg suspend_cfg;
132 //hack for ALSA magic casting
133 typedef struct l3_client l3_client_t;
134 #define chip_t l3_client_t
136 /* transfer 8bit integer into string with binary representation */
137 void int2str_bin8(uint8_t val, char *buf){
138 const int size = sizeof(val) * 8;
141 for (i= 0; i < size; i++){
142 *(buf++) = (val >> (size - 1)) ? '1' : '0';
145 *buf = '\0'; //end the string with zero
148 /* {{{ HW manipulation routines */
150 int snd_uda1341_codec_write(struct l3_client *clnt, unsigned short reg, unsigned short val)
152 struct uda1341 *uda = clnt->driver_data;
153 unsigned char buf[2] = { 0xc0, 0xe0 }; // for EXT addressing
156 uda->regs[reg] = val;
160 err = l3_write(clnt, UDA1341_DATA0, (const unsigned char *)&val, 1);
161 } else if (IS_DATA1(reg)) {
162 err = l3_write(clnt, UDA1341_DATA1, (const unsigned char *)&val, 1);
163 } else if (IS_STATUS(reg)) {
164 err = l3_write(clnt, UDA1341_STATUS, (const unsigned char *)&val, 1);
165 } else if (IS_EXTEND(reg)) {
166 buf[0] |= (reg - ext0) & 0x7; //EXT address
167 buf[1] |= val; //EXT data
168 err = l3_write(clnt, UDA1341_DATA0, (const unsigned char *)buf, 2);
171 printk(KERN_ERR "UDA1341 codec not active!\n");
175 int snd_uda1341_codec_read(struct l3_client *clnt, unsigned short reg)
180 err = l3_read(clnt, reg, &val, 1);
182 // use just 6bits - the rest is address of the reg
184 return err < 0 ? err : -EIO;
187 static inline int snd_uda1341_valid_reg(struct l3_client *clnt, unsigned short reg)
189 return reg < uda1341_reg_last;
192 int snd_uda1341_update_bits(struct l3_client *clnt, unsigned short reg, unsigned short mask,
193 unsigned short shift, unsigned short value, int flush)
196 unsigned short old, new;
197 struct uda1341 *uda = clnt->driver_data;
200 printk(KERN_DEBUG "update_bits: reg: %s mask: %d shift: %d val: %d\n",
201 uda1341_reg_names[reg], mask, shift, value);
204 if (!snd_uda1341_valid_reg(clnt, reg))
206 spin_lock(&uda->reg_lock);
207 old = uda->regs[reg];
208 new = (old & ~(mask << shift)) | (value << shift);
211 if (flush) uda->write(clnt, reg, new);
212 uda->regs[reg] = new;
214 spin_unlock(&uda->reg_lock);
218 int snd_uda1341_cfg_write(struct l3_client *clnt, unsigned short what,
219 unsigned short value, int flush)
221 struct uda1341 *uda = clnt->driver_data;
228 printk(KERN_DEBUG "cfg_write what: %d value: %d\n", what, value);
231 uda->cfg[what] = value;
235 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 2, 1, flush); // MUTE
236 ret = snd_uda1341_update_bits(clnt, stat0, 1, 6, 1, flush); // RESET
237 ret = snd_uda1341_update_bits(clnt, stat0, 1, 6, 0, flush); // RESTORE
238 uda->cfg[CMD_RESET]=0;
241 ret = snd_uda1341_update_bits(clnt, stat0, 3, 4, value, flush);
244 ret = snd_uda1341_update_bits(clnt, stat0, 7, 1, value, flush);
247 ret = snd_uda1341_update_bits(clnt, stat1, 1, 6, value, flush);
250 ret = snd_uda1341_update_bits(clnt, stat1, 1, 5, value, flush);
253 ret = snd_uda1341_update_bits(clnt, stat1, 1, 0, value, flush);
256 ret = snd_uda1341_update_bits(clnt, stat1, 1, 1, value, flush);
259 ret = snd_uda1341_update_bits(clnt, data0_0, 63, 0, value, flush);
262 ret = snd_uda1341_update_bits(clnt, data0_1, 15, 2, value, flush);
265 ret = snd_uda1341_update_bits(clnt, data0_1, 3, 0, value, flush);
268 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 5, value, flush);
271 ret = snd_uda1341_update_bits(clnt, data0_2, 3, 3, value, flush);
274 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 2, value, flush);
277 ret = snd_uda1341_update_bits(clnt, data0_2, 3, 0, value, flush);
280 ret = snd_uda1341_update_bits(clnt, ext0, 31, 0, value, flush);
283 ret = snd_uda1341_update_bits(clnt, ext1, 31, 0, value, flush);
286 ret = snd_uda1341_update_bits(clnt, ext2, 7, 2, value, flush);
289 ret = snd_uda1341_update_bits(clnt, ext2, 3, 0, value, flush);
292 ret = snd_uda1341_update_bits(clnt, ext4, 1, 4, value, flush);
295 ret = snd_uda1341_update_bits(clnt, ext4, 3, 0, value & 0x3, flush);
296 ret = snd_uda1341_update_bits(clnt, ext5, 31, 0, value >> 2, flush);
299 ret = snd_uda1341_update_bits(clnt, ext6, 7, 2, value, flush);
302 ret = snd_uda1341_update_bits(clnt, ext6, 3, 0, value, flush);
306 for (reg = stat0; reg < uda1341_reg_last; reg++)
307 uda->suspend_regs[reg] = uda->regs[reg];
308 for (reg = 0; reg < CMD_LAST; reg++)
309 uda->suspend_cfg[reg] = uda->cfg[reg];
312 for (reg = stat0; reg < uda1341_reg_last; reg++)
313 snd_uda1341_codec_write(clnt, reg, uda->suspend_regs[reg]);
314 for (reg = 0; reg < CMD_LAST; reg++)
315 uda->cfg[reg] = uda->suspend_cfg[reg];
324 printk(KERN_ERR "UDA1341 codec not active!\n");
330 /* {{{ Proc interface */
332 static void snd_uda1341_proc_read(snd_info_entry_t *entry,
333 snd_info_buffer_t * buffer)
335 struct l3_client *clnt = snd_magic_cast(l3_client_t, entry->private_data, return);
336 struct uda1341 *uda = clnt->driver_data;
339 peak = snd_uda1341_codec_read(clnt, UDA1341_DATA1);
343 snd_iprintf(buffer, "%s\n\n", uda->card->longname);
345 // for information about computed values see UDA1341TS datasheet pages 15 - 21
346 snd_iprintf(buffer, "DAC power : %s\n", uda->cfg[CMD_DAC] ? "on" : "off");
347 snd_iprintf(buffer, "ADC power : %s\n", uda->cfg[CMD_ADC] ? "on" : "off");
348 snd_iprintf(buffer, "Clock frequency : %s\n", fs_names[uda->cfg[CMD_FS]]);
349 snd_iprintf(buffer, "Data format : %s\n\n", format_names[uda->cfg[CMD_FORMAT]]);
351 snd_iprintf(buffer, "Filter mode : %s\n", filter_names[uda->cfg[CMD_FILTER]]);
352 snd_iprintf(buffer, "Mixer mode : %s\n", mixer_names[uda->cfg[CMD_MIXER]]);
353 snd_iprintf(buffer, "De-emphasis : %s\n", deemp_names[uda->cfg[CMD_DEEMP]]);
354 snd_iprintf(buffer, "Peak detection pos. : %s\n", uda->cfg[CMD_PEAK] ? "after" : "before");
355 snd_iprintf(buffer, "Peak value : %s\n\n", peak_value[peak]);
357 snd_iprintf(buffer, "Automatic Gain Ctrl : %s\n", uda->cfg[CMD_AGC] ? "on" : "off");
358 snd_iprintf(buffer, "AGC attack time : %d ms\n", AGC_atime[uda->cfg[CMD_AGC_TIME]]);
359 snd_iprintf(buffer, "AGC decay time : %d ms\n", AGC_dtime[uda->cfg[CMD_AGC_TIME]]);
360 snd_iprintf(buffer, "AGC output level : %s dB\n\n", AGC_level[uda->cfg[CMD_AGC_LEVEL]]);
362 snd_iprintf(buffer, "Mute : %s\n", uda->cfg[CMD_MUTE] ? "on" : "off");
364 if (uda->cfg[CMD_VOLUME] == 0)
365 snd_iprintf(buffer, "Volume : 0 dB\n");
366 else if (uda->cfg[CMD_VOLUME] < 62)
367 snd_iprintf(buffer, "Volume : %d dB\n", -1*uda->cfg[CMD_VOLUME] +1);
369 snd_iprintf(buffer, "Volume : -INF dB\n");
370 snd_iprintf(buffer, "Bass : %s\n", bass_values[uda->cfg[CMD_FILTER]][uda->cfg[CMD_BASS]]);
371 snd_iprintf(buffer, "Trebble : %d dB\n", uda->cfg[CMD_FILTER] ? 2*uda->cfg[CMD_TREBBLE] : 0);
372 snd_iprintf(buffer, "Input Gain (6dB) : %s\n", uda->cfg[CMD_IGAIN] ? "on" : "off");
373 snd_iprintf(buffer, "Output Gain (6dB) : %s\n", uda->cfg[CMD_OGAIN] ? "on" : "off");
374 snd_iprintf(buffer, "Mic sensitivity : %s\n", mic_sens_value[uda->cfg[CMD_MIC]]);
377 if(uda->cfg[CMD_CH1] < 31)
378 snd_iprintf(buffer, "Mixer gain channel 1: -%d.%c dB\n",
379 ((uda->cfg[CMD_CH1] >> 1) * 3) + (uda->cfg[CMD_CH1] & 1),
380 uda->cfg[CMD_CH1] & 1 ? '5' : '0');
382 snd_iprintf(buffer, "Mixer gain channel 1: -INF dB\n");
383 if(uda->cfg[CMD_CH2] < 31)
384 snd_iprintf(buffer, "Mixer gain channel 2: -%d.%c dB\n",
385 ((uda->cfg[CMD_CH2] >> 1) * 3) + (uda->cfg[CMD_CH2] & 1),
386 uda->cfg[CMD_CH2] & 1 ? '5' : '0');
388 snd_iprintf(buffer, "Mixer gain channel 2: -INF dB\n");
390 if(uda->cfg[CMD_IG] > 5)
391 snd_iprintf(buffer, "Input Amp. Gain ch 2: %d.%c dB\n",
392 (uda->cfg[CMD_IG] >> 1) -3, uda->cfg[CMD_IG] & 1 ? '5' : '0');
394 snd_iprintf(buffer, "Input Amp. Gain ch 2: %s dB\n", ig_small_value[uda->cfg[CMD_IG]]);
397 static void snd_uda1341_proc_regs_read(snd_info_entry_t *entry,
398 snd_info_buffer_t * buffer)
400 struct l3_client *clnt = snd_magic_cast(l3_client_t, entry->private_data, return);
401 struct uda1341 *uda = clnt->driver_data;
405 spin_lock(&uda->reg_lock);
406 for (reg = 0; reg < uda1341_reg_last; reg ++) {
409 int2str_bin8(uda->regs[reg], buf);
410 snd_iprintf(buffer, "%s = %s\n", uda1341_reg_names[reg], buf);
413 int2str_bin8(snd_uda1341_codec_read(clnt, UDA1341_DATA1), buf);
414 snd_iprintf(buffer, "DATA1 = %s\n", buf);
416 spin_unlock(&uda->reg_lock);
419 static void __devinit snd_uda1341_proc_init(snd_card_t *card, struct l3_client *clnt)
421 snd_info_entry_t *entry;
423 if (! snd_card_proc_new(card, "uda1341", &entry))
424 snd_info_set_text_ops(entry, clnt, 1024, snd_uda1341_proc_read);
425 if (! snd_card_proc_new(card, "uda1341-regs", &entry))
426 snd_info_set_text_ops(entry, clnt, 1024, snd_uda1341_proc_regs_read);
431 /* {{{ Mixer controls setting */
433 /* {{{ UDA1341 single functions */
435 #define UDA1341_SINGLE(xname, where, reg, shift, mask, invert) \
436 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_uda1341_info_single, \
437 .get = snd_uda1341_get_single, .put = snd_uda1341_put_single, \
438 .private_value = where | (reg << 5) | (shift << 9) | (mask << 12) | (invert << 18) \
441 static int snd_uda1341_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
443 int mask = (kcontrol->private_value >> 12) & 63;
445 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
447 uinfo->value.integer.min = 0;
448 uinfo->value.integer.max = mask;
452 static int snd_uda1341_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
454 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
455 uda1341_t *uda = clnt->driver_data;
456 int where = kcontrol->private_value & 31;
457 int mask = (kcontrol->private_value >> 12) & 63;
458 int invert = (kcontrol->private_value >> 18) & 1;
460 ucontrol->value.integer.value[0] = uda->cfg[where];
462 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
467 static int snd_uda1341_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
469 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
470 uda1341_t *uda = clnt->driver_data;
471 int where = kcontrol->private_value & 31;
472 int reg = (kcontrol->private_value >> 5) & 15;
473 int shift = (kcontrol->private_value >> 9) & 7;
474 int mask = (kcontrol->private_value >> 12) & 63;
475 int invert = (kcontrol->private_value >> 18) & 1;
478 val = (ucontrol->value.integer.value[0] & mask);
482 uda->cfg[where] = val;
483 return snd_uda1341_update_bits(clnt, reg, mask, shift, val, FLUSH);
488 /* {{{ UDA1341 enum functions */
490 #define UDA1341_ENUM(xname, where, reg, shift, mask, invert) \
491 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_uda1341_info_enum, \
492 .get = snd_uda1341_get_enum, .put = snd_uda1341_put_enum, \
493 .private_value = where | (reg << 5) | (shift << 9) | (mask << 12) | (invert << 18) \
496 static int snd_uda1341_info_enum(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
498 int where = kcontrol->private_value & 31;
501 // this register we don't handle this way
502 if (!uda1341_enum_items[where])
505 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
507 uinfo->value.enumerated.items = uda1341_enum_items[where];
509 if (uinfo->value.enumerated.item >= uda1341_enum_items[where])
510 uinfo->value.enumerated.item = uda1341_enum_items[where] - 1;
512 texts = uda1341_enum_names[where];
513 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
517 static int snd_uda1341_get_enum(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
519 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
520 uda1341_t *uda = clnt->driver_data;
521 int where = kcontrol->private_value & 31;
523 ucontrol->value.enumerated.item[0] = uda->cfg[where];
527 static int snd_uda1341_put_enum(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
529 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
530 uda1341_t *uda = clnt->driver_data;
531 int where = kcontrol->private_value & 31;
532 int reg = (kcontrol->private_value >> 5) & 15;
533 int shift = (kcontrol->private_value >> 9) & 7;
534 int mask = (kcontrol->private_value >> 12) & 63;
536 uda->cfg[where] = (ucontrol->value.enumerated.item[0] & mask);
538 return snd_uda1341_update_bits(clnt, reg, mask, shift, uda->cfg[where], FLUSH);
543 /* {{{ UDA1341 2regs functions */
545 #define UDA1341_2REGS(xname, where, reg_1, reg_2, shift_1, shift_2, mask_1, mask_2, invert) \
546 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .info = snd_uda1341_info_2regs, \
547 .get = snd_uda1341_get_2regs, .put = snd_uda1341_put_2regs, \
548 .private_value = where | (reg_1 << 5) | (reg_2 << 9) | (shift_1 << 13) | (shift_2 << 16) | \
549 (mask_1 << 19) | (mask_2 << 25) | (invert << 31) \
553 static int snd_uda1341_info_2regs(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
555 int mask_1 = (kcontrol->private_value >> 19) & 63;
556 int mask_2 = (kcontrol->private_value >> 25) & 63;
559 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
560 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
562 uinfo->value.integer.min = 0;
563 uinfo->value.integer.max = mask;
567 static int snd_uda1341_get_2regs(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
569 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
570 uda1341_t *uda = clnt->driver_data;
571 int where = kcontrol->private_value & 31;
572 int mask_1 = (kcontrol->private_value >> 19) & 63;
573 int mask_2 = (kcontrol->private_value >> 25) & 63;
574 int invert = (kcontrol->private_value >> 31) & 1;
577 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
579 ucontrol->value.integer.value[0] = uda->cfg[where];
581 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
585 static int snd_uda1341_put_2regs(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
587 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
588 uda1341_t *uda = clnt->driver_data;
589 int where = kcontrol->private_value & 31;
590 int reg_1 = (kcontrol->private_value >> 5) & 15;
591 int reg_2 = (kcontrol->private_value >> 9) & 15;
592 int shift_1 = (kcontrol->private_value >> 13) & 7;
593 int shift_2 = (kcontrol->private_value >> 16) & 7;
594 int mask_1 = (kcontrol->private_value >> 19) & 63;
595 int mask_2 = (kcontrol->private_value >> 25) & 63;
596 int invert = (kcontrol->private_value >> 31) & 1;
598 unsigned short val1, val2, val;
600 val = ucontrol->value.integer.value[0];
602 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
605 val2 = (val / (mask_1 + 1)) & mask_2;
608 val1 = mask_1 - val1;
609 val2 = mask_2 - val2;
612 uda->cfg[where] = invert ? mask - val : val;
614 //FIXME - return value
615 snd_uda1341_update_bits(clnt, reg_1, mask_1, shift_1, val1, FLUSH);
616 return snd_uda1341_update_bits(clnt, reg_2, mask_2, shift_2, val2, FLUSH);
621 #define UDA1341_CONTROLS (sizeof(snd_uda1341_controls)/sizeof(snd_kcontrol_new_t))
623 static snd_kcontrol_new_t snd_uda1341_controls[] = {
624 UDA1341_SINGLE("Master Playback Switch", CMD_MUTE, data0_2, 2, 1, 1),
625 UDA1341_SINGLE("Master Playback Volume", CMD_VOLUME, data0_0, 0, 63, 1),
627 UDA1341_SINGLE("Bass Playback Volume", CMD_BASS, data0_1, 2, 15, 0),
628 UDA1341_SINGLE("Treble Playback Volume", CMD_TREBBLE, data0_1, 0, 3, 0),
630 UDA1341_SINGLE("Input Gain Switch", CMD_IGAIN, stat1, 5, 1, 0),
631 UDA1341_SINGLE("Output Gain Switch", CMD_OGAIN, stat1, 6, 1, 0),
633 UDA1341_SINGLE("Mixer Gain Channel 1 Volume", CMD_CH1, ext0, 0, 31, 1),
634 UDA1341_SINGLE("Mixer Gain Channel 2 Volume", CMD_CH2, ext1, 0, 31, 1),
636 UDA1341_SINGLE("Mic Sensitivity Volume", CMD_MIC, ext2, 2, 7, 0),
638 UDA1341_SINGLE("AGC Output Level", CMD_AGC_LEVEL, ext6, 0, 3, 0),
639 UDA1341_SINGLE("AGC Time Constant", CMD_AGC_TIME, ext6, 2, 7, 0),
640 UDA1341_SINGLE("AGC Time Constant Switch", CMD_AGC, ext4, 4, 1, 0),
642 UDA1341_SINGLE("DAC Power", CMD_DAC, stat1, 0, 1, 0),
643 UDA1341_SINGLE("ADC Power", CMD_ADC, stat1, 1, 1, 0),
645 UDA1341_ENUM("Peak detection", CMD_PEAK, data0_2, 5, 1, 0),
646 UDA1341_ENUM("De-emphasis", CMD_DEEMP, data0_2, 3, 3, 0),
647 UDA1341_ENUM("Mixer mode", CMD_MIXER, ext2, 0, 3, 0),
648 UDA1341_ENUM("Filter mode", CMD_FILTER, data0_2, 0, 3, 0),
650 UDA1341_2REGS("Gain Input Amplifier Gain (channel 2)", CMD_IG, ext4, ext5, 0, 0, 3, 31, 0),
653 static void uda1341_free(struct l3_client *uda1341)
655 l3_detach_client(uda1341); // calls kfree for driver_data (uda1341_t)
656 snd_magic_kfree(uda1341);
659 static int uda1341_dev_free(snd_device_t *device)
661 struct l3_client *clnt = snd_magic_cast(l3_client_t, device->device_data, return);
666 int __init snd_chip_uda1341_mixer_new(snd_card_t *card, struct l3_client **clnt)
668 static snd_device_ops_t ops = {
669 .dev_free = uda1341_dev_free,
671 struct l3_client *uda1341;
674 snd_assert(card != NULL, return -EINVAL);
676 uda1341 = snd_magic_kcalloc(l3_client_t, 0, GFP_KERNEL);
680 if ((err = l3_attach_client(uda1341, "l3-bit-sa1100-gpio", "snd-uda1341"))) {
685 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, uda1341, &ops)) < 0) {
686 l3_detach_client(uda1341);
691 for (idx = 0; idx < UDA1341_CONTROLS; idx++) {
692 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_uda1341_controls[idx], uda1341))) < 0)
697 strcpy(card->mixername, "UDA1341TS Mixer");
698 ((uda1341_t *)uda1341->driver_data)->card = card;
700 snd_uda1341_proc_init(card, uda1341);
707 /* {{{ L3 operations */
709 static int uda1341_attach(struct l3_client *clnt)
713 uda = snd_magic_kcalloc(uda1341_t, 0, GFP_KERNEL);
717 /* init fixed parts of my copy of registers */
718 uda->regs[stat0] = STAT0;
719 uda->regs[stat1] = STAT1;
721 uda->regs[data0_0] = DATA0_0;
722 uda->regs[data0_1] = DATA0_1;
723 uda->regs[data0_2] = DATA0_2;
725 uda->write = snd_uda1341_codec_write;
726 uda->read = snd_uda1341_codec_read;
728 spin_lock_init(&uda->reg_lock);
730 clnt->driver_data = uda;
734 static void uda1341_detach(struct l3_client *clnt)
736 if (clnt->driver_data)
737 snd_magic_kfree(clnt->driver_data);
741 uda1341_command(struct l3_client *clnt, int cmd, void *arg)
743 if (cmd != CMD_READ_REG)
744 return snd_uda1341_cfg_write(clnt, cmd, (int) arg, FLUSH);
746 return snd_uda1341_codec_read(clnt, (int) arg);
749 static int uda1341_open(struct l3_client *clnt)
751 struct uda1341 *uda = clnt->driver_data;
755 /* init default configuration */
756 snd_uda1341_cfg_write(clnt, CMD_RESET, 0, REGS_ONLY);
757 snd_uda1341_cfg_write(clnt, CMD_FS, F256, FLUSH); // unknown state after reset
758 snd_uda1341_cfg_write(clnt, CMD_FORMAT, LSB16, FLUSH); // unknown state after reset
759 snd_uda1341_cfg_write(clnt, CMD_OGAIN, ON, FLUSH); // default off after reset
760 snd_uda1341_cfg_write(clnt, CMD_IGAIN, ON, FLUSH); // default off after reset
761 snd_uda1341_cfg_write(clnt, CMD_DAC, ON, FLUSH); // ??? default value after reset
762 snd_uda1341_cfg_write(clnt, CMD_ADC, ON, FLUSH); // ??? default value after reset
763 snd_uda1341_cfg_write(clnt, CMD_VOLUME, 20, FLUSH); // default 0dB after reset
764 snd_uda1341_cfg_write(clnt, CMD_BASS, 0, REGS_ONLY); // default value after reset
765 snd_uda1341_cfg_write(clnt, CMD_TREBBLE, 0, REGS_ONLY); // default value after reset
766 snd_uda1341_cfg_write(clnt, CMD_PEAK, AFTER, REGS_ONLY);// default value after reset
767 snd_uda1341_cfg_write(clnt, CMD_DEEMP, NONE, REGS_ONLY);// default value after reset
768 //at this moment should be QMUTED by h3600_audio_init
769 snd_uda1341_cfg_write(clnt, CMD_MUTE, OFF, REGS_ONLY); // default value after reset
770 snd_uda1341_cfg_write(clnt, CMD_FILTER, MAX, FLUSH); // defaul flat after reset
771 snd_uda1341_cfg_write(clnt, CMD_CH1, 31, FLUSH); // default value after reset
772 snd_uda1341_cfg_write(clnt, CMD_CH2, 4, FLUSH); // default value after reset
773 snd_uda1341_cfg_write(clnt, CMD_MIC, 4, FLUSH); // default 0dB after reset
774 snd_uda1341_cfg_write(clnt, CMD_MIXER, MIXER, FLUSH); // default doub.dif.mode
775 snd_uda1341_cfg_write(clnt, CMD_AGC, OFF, FLUSH); // default value after reset
776 snd_uda1341_cfg_write(clnt, CMD_IG, 0, FLUSH); // unknown state after reset
777 snd_uda1341_cfg_write(clnt, CMD_AGC_TIME, 0, FLUSH); // default value after reset
778 snd_uda1341_cfg_write(clnt, CMD_AGC_LEVEL, 0, FLUSH); // default value after reset
783 static void uda1341_close(struct l3_client *clnt)
785 struct uda1341 *uda = clnt->driver_data;
792 /* {{{ Module and L3 initialization */
794 static struct l3_ops uda1341_ops = {
795 .open = uda1341_open,
796 .command = uda1341_command,
797 .close = uda1341_close,
800 static struct l3_driver uda1341_driver = {
801 .name = UDA1341_ALSA_NAME,
802 .attach_client = uda1341_attach,
803 .detach_client = uda1341_detach,
805 .owner = THIS_MODULE,
808 static int __init uda1341_init(void)
810 return l3_add_driver(&uda1341_driver);
813 static void __exit uda1341_exit(void)
815 l3_del_driver(&uda1341_driver);
818 module_init(uda1341_init);
819 module_exit(uda1341_exit);
821 MODULE_AUTHOR("Tomas Kasparek <tomas.kasparek@seznam.cz>");
822 MODULE_LICENSE("GPL");
823 MODULE_DESCRIPTION("Philips UDA1341 CODEC driver for ALSA");
824 MODULE_CLASSES("{sound}");
825 MODULE_DEVICES("{{UDA1341,UDA1341TS}}");
827 EXPORT_SYMBOL(snd_chip_uda1341_mixer_new);
833 * indent-tabs-mode: t