sound/oss/ad1848.c

   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  *
  16  *
  17  *
  18  * Copyright (C) by Hannu Savolainen 1993-1997
  19  *
  20  * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
  21  * Version 2 (June 1991). See the "COPYING" file distributed with this software
  22  * for more info.
  23  *
  24  *
  25  * Thomas Sailer        : ioctl code reworked (vmalloc/vfree removed)
  26  *                        general sleep/wakeup clean up.
  27  * Alan Cox             : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
  28  *                        of irqs. Use dev_id.
  29  * Christoph Hellwig    : adapted to module_init/module_exit
  30  * Aki Laukkanen        : added power management support
  31  * Arnaldo C. de Melo   : added missing restore_flags in ad1848_resume
  32  * Miguel Freitas       : added ISA PnP support
  33  * Alan Cox             : Added CS4236->4239 identification
  34  * Daniel T. Cobra      : Alernate config/mixer for later chips
  35  * Alan Cox             : Merged chip idents and config code
  36  *
  37  * TODO
  38  *              APM save restore assist code on IBM thinkpad
  39  *
  40  * Status:
  41  *              Tested. Believed fully functional.
  42  */
  43
  44 #include <linux/config.h>
  45 #include <linux/init.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/module.h>
  48 #include <linux/stddef.h>
  49 #include <linux/pm.h>
  50 #include <linux/isapnp.h>
  51 #include <linux/pnp.h>
  52 #include <linux/spinlock.h>
  53
  54 #define DEB(x)
  55 #define DEB1(x)
  56 #include "sound_config.h"
  57
  58 #include "ad1848.h"
  59 #include "ad1848_mixer.h"
  60
  61 typedef struct
  62 {
  63         spinlock_t      lock;
  64         int             base;
  65         int             irq;
  66         int             dma1, dma2;
  67         int             dual_dma;       /* 1, when two DMA channels allocated */
  68         int             subtype;
  69         unsigned char   MCE_bit;
  70         unsigned char   saved_regs[64]; /* Includes extended register space */
  71         int             debug_flag;
  72
  73         int             audio_flags;
  74         int             record_dev, playback_dev;
  75
  76         int             xfer_count;
  77         int             audio_mode;
  78         int             open_mode;
  79         int             intr_active;
  80         char           *chip_name, *name;
  81         int             model;
  82 #define MD_1848         1
  83 #define MD_4231         2
  84 #define MD_4231A        3
  85 #define MD_1845         4
  86 #define MD_4232         5
  87 #define MD_C930         6
  88 #define MD_IWAVE        7
  89 #define MD_4235         8 /* Crystal Audio CS4235  */
  90 #define MD_1845_SSCAPE  9 /* Ensoniq Soundscape PNP*/
  91 #define MD_4236         10 /* 4236 and higher */
  92 #define MD_42xB         11 /* CS 42xB */
  93 #define MD_4239         12 /* CS4239 */
  94
  95         /* Mixer parameters */
  96         int             recmask;
  97         int             supported_devices, orig_devices;
  98         int             supported_rec_devices, orig_rec_devices;
  99         int            *levels;
 100         short           mixer_reroute[32];
 101         int             dev_no;
 102         volatile unsigned long timer_ticks;
 103         int             timer_running;
 104         int             irq_ok;
 105         mixer_ents     *mix_devices;
 106         int             mixer_output_port;
 107
 108         /* Power management */
 109         struct          pm_dev *pmdev;
 110 } ad1848_info;
 111
 112 typedef struct ad1848_port_info
 113 {
 114         int             open_mode;
 115         int             speed;
 116         unsigned char   speed_bits;
 117         int             channels;
 118         int             audio_format;
 119         unsigned char   format_bits;
 120 }
 121 ad1848_port_info;
 122
 123 static struct address_info cfg;
 124 static int nr_ad1848_devs;
 125
 126 int deskpro_xl;
 127 int deskpro_m;
 128 int soundpro;
 129
 130 static volatile signed char irq2dev[17] = {
 131         -1, -1, -1, -1, -1, -1, -1, -1,
 132         -1, -1, -1, -1, -1, -1, -1, -1, -1
 133 };
 134
 135 #ifndef EXCLUDE_TIMERS
 136 static int timer_installed = -1;
 137 #endif
 138
 139 static int loaded;
 140
 141 static int ad_format_mask[13 /*devc->model */ ] =
 142 {
 143         0,
 144         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 145         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 146         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 147         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,       /* AD1845 */
 148         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 149         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 150         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 151         AFMT_U8 | AFMT_S16_LE /* CS4235 */,
 152         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW        /* Ensoniq Soundscape*/,
 153         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 154         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 155         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
 156 };
 157
 158 static ad1848_info adev_info[MAX_AUDIO_DEV];
 159
 160 #define io_Index_Addr(d)        ((d)->base)
 161 #define io_Indexed_Data(d)      ((d)->base+1)
 162 #define io_Status(d)            ((d)->base+2)
 163 #define io_Polled_IO(d)         ((d)->base+3)
 164
 165 static struct {
 166      unsigned char flags;
 167 #define CAP_F_TIMER 0x01
 168 } capabilities [10 /*devc->model */ ] = {
 169      {0}
 170     ,{0}           /* MD_1848  */
 171     ,{CAP_F_TIMER} /* MD_4231  */
 172     ,{CAP_F_TIMER} /* MD_4231A */
 173     ,{CAP_F_TIMER} /* MD_1845  */
 174     ,{CAP_F_TIMER} /* MD_4232  */
 175     ,{0}           /* MD_C930  */
 176     ,{CAP_F_TIMER} /* MD_IWAVE */
 177     ,{0}           /* MD_4235  */
 178     ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
 179 };
 180
 181 #ifdef CONFIG_PNP
 182 static int isapnp       = 1;
 183 static int isapnpjump;
 184 static int reverse;
 185
 186 static int audio_activated;
 187 #else
 188 static int isapnp;
 189 #endif
 190
 191
 192
 193 static int      ad1848_open(int dev, int mode);
 194 static void     ad1848_close(int dev);
 195 static void     ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
 196 static void     ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
 197 static int      ad1848_prepare_for_output(int dev, int bsize, int bcount);
 198 static int      ad1848_prepare_for_input(int dev, int bsize, int bcount);
 199 static void     ad1848_halt(int dev);
 200 static void     ad1848_halt_input(int dev);
 201 static void     ad1848_halt_output(int dev);
 202 static void     ad1848_trigger(int dev, int bits);
 203 static int      ad1848_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data);
 204
 205 #ifndef EXCLUDE_TIMERS
 206 static int ad1848_tmr_install(int dev);
 207 static void ad1848_tmr_reprogram(int dev);
 208 #endif
 209
 210 static int ad_read(ad1848_info * devc, int reg)
 211 {
 212         int x;
 213         int timeout = 900000;
 214
 215         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 216                 timeout--;
 217
 218         if(reg < 32)
 219         {
 220                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 221                 x = inb(io_Indexed_Data(devc));
 222         }
 223         else
 224         {
 225                 int xreg, xra;
 226
 227                 xreg = (reg & 0xff) - 32;
 228                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 229                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 230                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 231                 x = inb(io_Indexed_Data(devc));
 232         }
 233
 234         return x;
 235 }
 236
 237 static void ad_write(ad1848_info * devc, int reg, int data)
 238 {
 239         int timeout = 900000;
 240
 241         while (timeout > 0 && inb(devc->base) == 0x80)  /* Are we initializing */
 242                 timeout--;
 243
 244         if(reg < 32)
 245         {
 246                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 247                 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
 248         }
 249         else
 250         {
 251                 int xreg, xra;
 252
 253                 xreg = (reg & 0xff) - 32;
 254                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 255                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 256                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 257                 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
 258         }
 259 }
 260
 261 static void wait_for_calibration(ad1848_info * devc)
 262 {
 263         int timeout = 0;
 264
 265         /*
 266          * Wait until the auto calibration process has finished.
 267          *
 268          * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 269          * 2)       Wait until the ACI bit of I11 gets on and then off.
 270          */
 271
 272         timeout = 100000;
 273         while (timeout > 0 && inb(devc->base) == 0x80)
 274                 timeout--;
 275         if (inb(devc->base) & 0x80)
 276                 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
 277
 278         timeout = 100;
 279         while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
 280                 timeout--;
 281         if (!(ad_read(devc, 11) & 0x20))
 282                 return;
 283
 284         timeout = 80000;
 285         while (timeout > 0 && (ad_read(devc, 11) & 0x20))
 286                 timeout--;
 287         if (ad_read(devc, 11) & 0x20)
 288                 if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
 289                         printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
 290 }
 291
 292 static void ad_mute(ad1848_info * devc)
 293 {
 294         int i;
 295         unsigned char prev;
 296
 297         /*
 298          * Save old register settings and mute output channels
 299          */
 300
 301         for (i = 6; i < 8; i++)
 302         {
 303                 prev = devc->saved_regs[i] = ad_read(devc, i);
 304         }
 305
 306 }
 307
 308 static void ad_unmute(ad1848_info * devc)
 309 {
 310 }
 311
 312 static void ad_enter_MCE(ad1848_info * devc)
 313 {
 314         int timeout = 1000;
 315         unsigned short prev;
 316
 317         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 318                 timeout--;
 319
 320         devc->MCE_bit = 0x40;
 321         prev = inb(io_Index_Addr(devc));
 322         if (prev & 0x40)
 323         {
 324                 return;
 325         }
 326         outb((devc->MCE_bit), io_Index_Addr(devc));
 327 }
 328
 329 static void ad_leave_MCE(ad1848_info * devc)
 330 {
 331         unsigned char prev, acal;
 332         int timeout = 1000;
 333
 334         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 335                 timeout--;
 336
 337         acal = ad_read(devc, 9);
 338
 339         devc->MCE_bit = 0x00;
 340         prev = inb(io_Index_Addr(devc));
 341         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 342
 343         if ((prev & 0x40) == 0) /* Not in MCE mode */
 344         {
 345                 return;
 346         }
 347         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 348         if (acal & 0x08)        /* Auto calibration is enabled */
 349                 wait_for_calibration(devc);
 350 }
 351
 352 static int ad1848_set_recmask(ad1848_info * devc, int mask)
 353 {
 354         unsigned char   recdev;
 355         int             i, n;
 356         unsigned long flags;
 357
 358         mask &= devc->supported_rec_devices;
 359
 360         /* Rename the mixer bits if necessary */
 361         for (i = 0; i < 32; i++)
 362         {
 363                 if (devc->mixer_reroute[i] != i)
 364                 {
 365                         if (mask & (1 << i))
 366                         {
 367                                 mask &= ~(1 << i);
 368                                 mask |= (1 << devc->mixer_reroute[i]);
 369                         }
 370                 }
 371         }
 372
 373         n = 0;
 374         for (i = 0; i < 32; i++)        /* Count selected device bits */
 375                 if (mask & (1 << i))
 376                         n++;
 377
 378         spin_lock_irqsave(&devc->lock,flags);
 379         if (!soundpro) {
 380                 if (n == 0)
 381                         mask = SOUND_MASK_MIC;
 382                 else if (n != 1) {      /* Too many devices selected */
 383                         mask &= ~devc->recmask; /* Filter out active settings */
 384
 385                         n = 0;
 386                         for (i = 0; i < 32; i++)        /* Count selected device bits */
 387                                 if (mask & (1 << i))
 388                                         n++;
 389
 390                         if (n != 1)
 391                                 mask = SOUND_MASK_MIC;
 392                 }
 393                 switch (mask) {
 394                 case SOUND_MASK_MIC:
 395                         recdev = 2;
 396                         break;
 397
 398                 case SOUND_MASK_LINE:
 399                 case SOUND_MASK_LINE3:
 400                         recdev = 0;
 401                         break;
 402
 403                 case SOUND_MASK_CD:
 404                 case SOUND_MASK_LINE1:
 405                         recdev = 1;
 406                         break;
 407
 408                 case SOUND_MASK_IMIX:
 409                         recdev = 3;
 410                         break;
 411
 412                 default:
 413                         mask = SOUND_MASK_MIC;
 414                         recdev = 2;
 415                 }
 416
 417                 recdev <<= 6;
 418                 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
 419                 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
 420         } else { /* soundpro */
 421                 unsigned char val;
 422                 int set_rec_bit;
 423                 int j;
 424
 425                 for (i = 0; i < 32; i++) {      /* For each bit */
 426                         if ((devc->supported_rec_devices & (1 << i)) == 0)
 427                                 continue;       /* Device not supported */
 428
 429                         for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
 430                                 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
 431                                         continue;
 432
 433                                 /*
 434                                  * This is tricky:
 435                                  * set_rec_bit becomes 1 if the corresponding bit in mask is set
 436                                  * then it gets flipped if the polarity is inverse
 437                                  */
 438                                 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
 439
 440                                 val = ad_read(devc, devc->mix_devices[i][j].recreg);
 441                                 val &= ~(1 << devc->mix_devices[i][j].recpos);
 442                                 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
 443                                 ad_write(devc, devc->mix_devices[i][j].recreg, val);
 444                         }
 445                 }
 446         }
 447         spin_unlock_irqrestore(&devc->lock,flags);
 448
 449         /* Rename the mixer bits back if necessary */
 450         for (i = 0; i < 32; i++)
 451         {
 452                 if (devc->mixer_reroute[i] != i)
 453                 {
 454                         if (mask & (1 << devc->mixer_reroute[i]))
 455                         {
 456                                 mask &= ~(1 << devc->mixer_reroute[i]);
 457                                 mask |= (1 << i);
 458                         }
 459                 }
 460         }
 461         devc->recmask = mask;
 462         return mask;
 463 }
 464
 465 static void change_bits(ad1848_info * devc, unsigned char *regval,
 466                         unsigned char *muteval, int dev, int chn, int newval)
 467 {
 468         unsigned char mask;
 469         int shift;
 470         int mute;
 471         int mutemask;
 472         int set_mute_bit;
 473
 474         set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
 475
 476         if (devc->mix_devices[dev][chn].polarity == 1)  /* Reverse */
 477                 newval = 100 - newval;
 478
 479         mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
 480         shift = devc->mix_devices[dev][chn].bitpos;
 481
 482         if (devc->mix_devices[dev][chn].mutepos == 8)
 483         {                       /* if there is no mute bit */
 484                 mute = 0;       /* No mute bit; do nothing special */
 485                 mutemask = ~0;  /* No mute bit; do nothing special */
 486         }
 487         else
 488         {
 489                 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
 490                 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
 491         }
 492
 493         newval = (int) ((newval * mask) + 50) / 100;    /* Scale it */
 494         *regval &= ~(mask << shift);                    /* Clear bits */
 495         *regval |= (newval & mask) << shift;            /* Set new value */
 496
 497         *muteval &= mutemask;
 498         *muteval |= mute;
 499 }
 500
 501 static int ad1848_mixer_get(ad1848_info * devc, int dev)
 502 {
 503         if (!((1 << dev) & devc->supported_devices))
 504                 return -EINVAL;
 505
 506         dev = devc->mixer_reroute[dev];
 507
 508         return devc->levels[dev];
 509 }
 510
 511 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
 512 {
 513         int regoffs, muteregoffs;
 514         unsigned char val, muteval;
 515         unsigned long flags;
 516
 517         regoffs = devc->mix_devices[dev][channel].regno;
 518         muteregoffs = devc->mix_devices[dev][channel].mutereg;
 519         val = ad_read(devc, regoffs);
 520
 521         if (muteregoffs != regoffs) {
 522                 muteval = ad_read(devc, muteregoffs);
 523                 change_bits(devc, &val, &muteval, dev, channel, value);
 524         }
 525         else
 526                 change_bits(devc, &val, &val, dev, channel, value);
 527
 528         spin_lock_irqsave(&devc->lock,flags);
 529         ad_write(devc, regoffs, val);
 530         devc->saved_regs[regoffs] = val;
 531         if (muteregoffs != regoffs) {
 532                 ad_write(devc, muteregoffs, muteval);
 533                 devc->saved_regs[muteregoffs] = muteval;
 534         }
 535         spin_unlock_irqrestore(&devc->lock,flags);
 536 }
 537
 538 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
 539 {
 540         int left = value & 0x000000ff;
 541         int right = (value & 0x0000ff00) >> 8;
 542         int retvol;
 543
 544         if (dev > 31)
 545                 return -EINVAL;
 546
 547         if (!(devc->supported_devices & (1 << dev)))
 548                 return -EINVAL;
 549
 550         dev = devc->mixer_reroute[dev];
 551
 552         if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
 553                 return -EINVAL;
 554
 555         if (left > 100)
 556                 left = 100;
 557         if (right > 100)
 558                 right = 100;
 559
 560         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)       /* Mono control */
 561                 right = left;
 562
 563         retvol = left | (right << 8);
 564
 565         /* Scale volumes */
 566         left = mix_cvt[left];
 567         right = mix_cvt[right];
 568
 569         devc->levels[dev] = retvol;
 570
 571         /*
 572          * Set the left channel
 573          */
 574         ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
 575
 576         /*
 577          * Set the right channel
 578          */
 579         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
 580                 goto out;
 581         ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
 582
 583  out:
 584         return retvol;
 585 }
 586
 587 static void ad1848_mixer_reset(ad1848_info * devc)
 588 {
 589         int i;
 590         char name[32];
 591         unsigned long flags;
 592
 593         devc->mix_devices = &(ad1848_mix_devices[0]);
 594
 595         sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
 596
 597         for (i = 0; i < 32; i++)
 598                 devc->mixer_reroute[i] = i;
 599
 600         devc->supported_rec_devices = MODE1_REC_DEVICES;
 601
 602         switch (devc->model)
 603         {
 604                 case MD_4231:
 605                 case MD_4231A:
 606                 case MD_1845:
 607                 case MD_1845_SSCAPE:
 608                         devc->supported_devices = MODE2_MIXER_DEVICES;
 609                         break;
 610
 611                 case MD_C930:
 612                         devc->supported_devices = C930_MIXER_DEVICES;
 613                         devc->mix_devices = &(c930_mix_devices[0]);
 614                         break;
 615
 616                 case MD_IWAVE:
 617                         devc->supported_devices = MODE3_MIXER_DEVICES;
 618                         devc->mix_devices = &(iwave_mix_devices[0]);
 619                         break;
 620
 621                 case MD_42xB:
 622                 case MD_4239:
 623                         devc->mix_devices = &(cs42xb_mix_devices[0]);
 624                         devc->supported_devices = MODE3_MIXER_DEVICES;
 625                         break;
 626                 case MD_4232:
 627                 case MD_4236:
 628                         devc->supported_devices = MODE3_MIXER_DEVICES;
 629                         break;
 630
 631                 case MD_1848:
 632                         if (soundpro) {
 633                                 devc->supported_devices = SPRO_MIXER_DEVICES;
 634                                 devc->supported_rec_devices = SPRO_REC_DEVICES;
 635                                 devc->mix_devices = &(spro_mix_devices[0]);
 636                                 break;
 637                         }
 638
 639                 default:
 640                         devc->supported_devices = MODE1_MIXER_DEVICES;
 641         }
 642
 643         devc->orig_devices = devc->supported_devices;
 644         devc->orig_rec_devices = devc->supported_rec_devices;
 645
 646         devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
 647
 648         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 649         {
 650                 if (devc->supported_devices & (1 << i))
 651                         ad1848_mixer_set(devc, i, devc->levels[i]);
 652         }
 653
 654         ad1848_set_recmask(devc, SOUND_MASK_MIC);
 655
 656         devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
 657
 658         spin_lock_irqsave(&devc->lock,flags);
 659         if (!soundpro) {
 660                 if (devc->mixer_output_port & AUDIO_SPEAKER)
 661                         ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 662                 else
 663                         ad_write(devc, 26, ad_read(devc, 26) | 0x40);   /* Mute mono out */
 664         } else {
 665                 /*
 666                  * From the "wouldn't it be nice if the mixer API had (better)
 667                  * support for custom stuff" category
 668                  */
 669                 /* Enable surround mode and SB16 mixer */
 670                 ad_write(devc, 16, 0x60);
 671         }
 672         spin_unlock_irqrestore(&devc->lock,flags);
 673 }
 674
 675 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, caddr_t arg)
 676 {
 677         ad1848_info *devc = mixer_devs[dev]->devc;
 678         int val;
 679
 680         if (cmd == SOUND_MIXER_PRIVATE1)
 681         {
 682                 if (get_user(val, (int *)arg))
 683                         return -EFAULT;
 684
 685                 if (val != 0xffff)
 686                 {
 687                         unsigned long flags;
 688                         val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
 689                         devc->mixer_output_port = val;
 690                         val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT;        /* Always on */
 691                         devc->mixer_output_port = val;
 692                         spin_lock_irqsave(&devc->lock,flags);
 693                         if (val & AUDIO_SPEAKER)
 694                                 ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 695                         else
 696                                 ad_write(devc, 26, ad_read(devc, 26) | 0x40);           /* Mute mono out */
 697                         spin_unlock_irqrestore(&devc->lock,flags);
 698                 }
 699                 val = devc->mixer_output_port;
 700                 return put_user(val, (int *)arg);
 701         }
 702         if (cmd == SOUND_MIXER_PRIVATE2)
 703         {
 704                 if (get_user(val, (int *)arg))
 705                         return -EFAULT;
 706                 return(ad1848_control(AD1848_MIXER_REROUTE, val));
 707         }
 708         if (((cmd >> 8) & 0xff) == 'M')
 709         {
 710                 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
 711                 {
 712                         switch (cmd & 0xff)
 713                         {
 714                                 case SOUND_MIXER_RECSRC:
 715                                         if (get_user(val, (int *)arg))
 716                                                 return -EFAULT;
 717                                         val = ad1848_set_recmask(devc, val);
 718                                         break;
 719
 720                                 default:
 721                                         if (get_user(val, (int *)arg))
 722                                         return -EFAULT;
 723                                         val = ad1848_mixer_set(devc, cmd & 0xff, val);
 724                                         break;
 725                         }
 726                         return put_user(val, (int *)arg);
 727                 }
 728                 else
 729                 {
 730                         switch (cmd & 0xff)
 731                         {
 732                                 /*
 733                                  * Return parameters
 734                                  */
 735
 736                                 case SOUND_MIXER_RECSRC:
 737                                         val = devc->recmask;
 738                                         break;
 739
 740                                 case SOUND_MIXER_DEVMASK:
 741                                         val = devc->supported_devices;
 742                                         break;
 743
 744                                 case SOUND_MIXER_STEREODEVS:
 745                                         val = devc->supported_devices;
 746                                         if (devc->model != MD_C930)
 747                                                 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
 748                                         break;
 749
 750                                 case SOUND_MIXER_RECMASK:
 751                                         val = devc->supported_rec_devices;
 752                                         break;
 753
 754                                 case SOUND_MIXER_CAPS:
 755                                         val=SOUND_CAP_EXCL_INPUT;
 756                                         break;
 757
 758                                 default:
 759                                         val = ad1848_mixer_get(devc, cmd & 0xff);
 760                                         break;
 761                         }
 762                         return put_user(val, (int *)arg);
 763                 }
 764         }
 765         else
 766                 return -EINVAL;
 767 }
 768
 769 static int ad1848_set_speed(int dev, int arg)
 770 {
 771         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
 772         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 773
 774         /*
 775          * The sampling speed is encoded in the least significant nibble of I8. The
 776          * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
 777          * three bits select the divisor (indirectly):
 778          *
 779          * The available speeds are in the following table. Keep the speeds in
 780          * the increasing order.
 781          */
 782         typedef struct
 783         {
 784                 int             speed;
 785                 unsigned char   bits;
 786         }
 787         speed_struct;
 788
 789         static speed_struct speed_table[] =
 790         {
 791                 {5510, (0 << 1) | 1},
 792                 {5510, (0 << 1) | 1},
 793                 {6620, (7 << 1) | 1},
 794                 {8000, (0 << 1) | 0},
 795                 {9600, (7 << 1) | 0},
 796                 {11025, (1 << 1) | 1},
 797                 {16000, (1 << 1) | 0},
 798                 {18900, (2 << 1) | 1},
 799                 {22050, (3 << 1) | 1},
 800                 {27420, (2 << 1) | 0},
 801                 {32000, (3 << 1) | 0},
 802                 {33075, (6 << 1) | 1},
 803                 {37800, (4 << 1) | 1},
 804                 {44100, (5 << 1) | 1},
 805                 {48000, (6 << 1) | 0}
 806         };
 807
 808         int i, n, selected = -1;
 809
 810         n = sizeof(speed_table) / sizeof(speed_struct);
 811
 812         if (arg <= 0)
 813                 return portc->speed;
 814
 815         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)    /* AD1845 has different timer than others */
 816         {
 817                 if (arg < 4000)
 818                         arg = 4000;
 819                 if (arg > 50000)
 820                         arg = 50000;
 821
 822                 portc->speed = arg;
 823                 portc->speed_bits = speed_table[3].bits;
 824                 return portc->speed;
 825         }
 826         if (arg < speed_table[0].speed)
 827                 selected = 0;
 828         if (arg > speed_table[n - 1].speed)
 829                 selected = n - 1;
 830
 831         for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 832         {
 833                 if (speed_table[i].speed == arg)
 834                         selected = i;
 835                 else if (speed_table[i].speed > arg)
 836                 {
 837                         int diff1, diff2;
 838
 839                         diff1 = arg - speed_table[i - 1].speed;
 840                         diff2 = speed_table[i].speed - arg;
 841
 842                         if (diff1 < diff2)
 843                                 selected = i - 1;
 844                         else
 845                                 selected = i;
 846                 }
 847         }
 848         if (selected == -1)
 849         {
 850                 printk(KERN_WARNING "ad1848: Can't find speed???\n");
 851                 selected = 3;
 852         }
 853         portc->speed = speed_table[selected].speed;
 854         portc->speed_bits = speed_table[selected].bits;
 855         return portc->speed;
 856 }
 857
 858 static short ad1848_set_channels(int dev, short arg)
 859 {
 860         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 861
 862         if (arg != 1 && arg != 2)
 863                 return portc->channels;
 864
 865         portc->channels = arg;
 866         return arg;
 867 }
 868
 869 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
 870 {
 871         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 872         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 873
 874         static struct format_tbl
 875         {
 876                   int             format;
 877                   unsigned char   bits;
 878         }
 879         format2bits[] =
 880         {
 881                 {
 882                         0, 0
 883                 }
 884                 ,
 885                 {
 886                         AFMT_MU_LAW, 1
 887                 }
 888                 ,
 889                 {
 890                         AFMT_A_LAW, 3
 891                 }
 892                 ,
 893                 {
 894                         AFMT_IMA_ADPCM, 5
 895                 }
 896                 ,
 897                 {
 898                         AFMT_U8, 0
 899                 }
 900                 ,
 901                 {
 902                         AFMT_S16_LE, 2
 903                 }
 904                 ,
 905                 {
 906                         AFMT_S16_BE, 6
 907                 }
 908                 ,
 909                 {
 910                         AFMT_S8, 0
 911                 }
 912                 ,
 913                 {
 914                         AFMT_U16_LE, 0
 915                 }
 916                 ,
 917                 {
 918                         AFMT_U16_BE, 0
 919                 }
 920         };
 921         int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
 922
 923         if (arg == 0)
 924                 return portc->audio_format;
 925
 926         if (!(arg & ad_format_mask[devc->model]))
 927                 arg = AFMT_U8;
 928
 929         portc->audio_format = arg;
 930
 931         for (i = 0; i < n; i++)
 932                 if (format2bits[i].format == arg)
 933                 {
 934                         if ((portc->format_bits = format2bits[i].bits) == 0)
 935                                 return portc->audio_format = AFMT_U8;           /* Was not supported */
 936
 937                         return arg;
 938                 }
 939         /* Still hanging here. Something must be terribly wrong */
 940         portc->format_bits = 0;
 941         return portc->audio_format = AFMT_U8;
 942 }
 943
 944 static struct audio_driver ad1848_audio_driver =
 945 {
 946         .owner                  = THIS_MODULE,
 947         .open                   = ad1848_open,
 948         .close                  = ad1848_close,
 949         .output_block           = ad1848_output_block,
 950         .start_input            = ad1848_start_input,
 951         .prepare_for_input      = ad1848_prepare_for_input,
 952         .prepare_for_output     = ad1848_prepare_for_output,
 953         .halt_io                = ad1848_halt,
 954         .halt_input             = ad1848_halt_input,
 955         .halt_output            = ad1848_halt_output,
 956         .trigger                = ad1848_trigger,
 957         .set_speed              = ad1848_set_speed,
 958         .set_bits               = ad1848_set_bits,
 959         .set_channels           = ad1848_set_channels
 960 };
 961
 962 static struct mixer_operations ad1848_mixer_operations =
 963 {
 964         .owner  = THIS_MODULE,
 965         .id     = "SOUNDPORT",
 966         .name   = "AD1848/CS4248/CS4231",
 967         .ioctl  = ad1848_mixer_ioctl
 968 };
 969
 970 static int ad1848_open(int dev, int mode)
 971 {
 972         ad1848_info    *devc;
 973         ad1848_port_info *portc;
 974         unsigned long   flags;
 975
 976         if (dev < 0 || dev >= num_audiodevs)
 977                 return -ENXIO;
 978
 979         devc = (ad1848_info *) audio_devs[dev]->devc;
 980         portc = (ad1848_port_info *) audio_devs[dev]->portc;
 981
 982         /* here we don't have to protect against intr */
 983         spin_lock(&devc->lock);
 984         if (portc->open_mode || (devc->open_mode & mode))
 985         {
 986                 spin_unlock(&devc->lock);
 987                 return -EBUSY;
 988         }
 989         devc->dual_dma = 0;
 990
 991         if (audio_devs[dev]->flags & DMA_DUPLEX)
 992         {
 993                 devc->dual_dma = 1;
 994         }
 995         devc->intr_active = 0;
 996         devc->audio_mode = 0;
 997         devc->open_mode |= mode;
 998         portc->open_mode = mode;
 999         spin_unlock(&devc->lock);
1000         ad1848_trigger(dev, 0);
1001
1002         if (mode & OPEN_READ)
1003                 devc->record_dev = dev;
1004         if (mode & OPEN_WRITE)
1005                 devc->playback_dev = dev;
1006 /*
1007  * Mute output until the playback really starts. This decreases clicking (hope so).
1008  */
1009         spin_lock_irqsave(&devc->lock,flags);
1010         ad_mute(devc);
1011         spin_unlock_irqrestore(&devc->lock,flags);
1012
1013         return 0;
1014 }
1015
1016 static void ad1848_close(int dev)
1017 {
1018         unsigned long   flags;
1019         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1020         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1021
1022         DEB(printk("ad1848_close(void)\n"));
1023
1024         devc->intr_active = 0;
1025         ad1848_halt(dev);
1026
1027         spin_lock_irqsave(&devc->lock,flags);
1028
1029         devc->audio_mode = 0;
1030         devc->open_mode &= ~portc->open_mode;
1031         portc->open_mode = 0;
1032
1033         ad_unmute(devc);
1034         spin_unlock_irqrestore(&devc->lock,flags);
1035 }
1036
1037 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1038 {
1039         unsigned long   flags, cnt;
1040         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1041         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1042
1043         cnt = count;
1044
1045         if (portc->audio_format == AFMT_IMA_ADPCM)
1046         {
1047                 cnt /= 4;
1048         }
1049         else
1050         {
1051                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1052                         cnt >>= 1;
1053         }
1054         if (portc->channels > 1)
1055                 cnt >>= 1;
1056         cnt--;
1057
1058         if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1059             intrflag &&
1060             cnt == devc->xfer_count)
1061         {
1062                 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1063                 devc->intr_active = 1;
1064                 return; /*
1065                          * Auto DMA mode on. No need to react
1066                          */
1067         }
1068         spin_lock_irqsave(&devc->lock,flags);
1069
1070         ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1071         ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1072
1073         devc->xfer_count = cnt;
1074         devc->audio_mode |= PCM_ENABLE_OUTPUT;
1075         devc->intr_active = 1;
1076         spin_unlock_irqrestore(&devc->lock,flags);
1077 }
1078
1079 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1080 {
1081         unsigned long   flags, cnt;
1082         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1083         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1084
1085         cnt = count;
1086         if (portc->audio_format == AFMT_IMA_ADPCM)
1087         {
1088                 cnt /= 4;
1089         }
1090         else
1091         {
1092                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1093                         cnt >>= 1;
1094         }
1095         if (portc->channels > 1)
1096                 cnt >>= 1;
1097         cnt--;
1098
1099         if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1100                 intrflag &&
1101                 cnt == devc->xfer_count)
1102         {
1103                 devc->audio_mode |= PCM_ENABLE_INPUT;
1104                 devc->intr_active = 1;
1105                 return; /*
1106                          * Auto DMA mode on. No need to react
1107                          */
1108         }
1109         spin_lock_irqsave(&devc->lock,flags);
1110
1111         if (devc->model == MD_1848)
1112         {
1113                   ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1114                   ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1115         }
1116         else
1117         {
1118                   ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1119                   ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1120         }
1121
1122         ad_unmute(devc);
1123
1124         devc->xfer_count = cnt;
1125         devc->audio_mode |= PCM_ENABLE_INPUT;
1126         devc->intr_active = 1;
1127         spin_unlock_irqrestore(&devc->lock,flags);
1128 }
1129
1130 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1131 {
1132         int             timeout;
1133         unsigned char   fs, old_fs, tmp = 0;
1134         unsigned long   flags;
1135         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1136         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1137
1138         ad_mute(devc);
1139
1140         spin_lock_irqsave(&devc->lock,flags);
1141         fs = portc->speed_bits | (portc->format_bits << 5);
1142
1143         if (portc->channels > 1)
1144                 fs |= 0x10;
1145
1146         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1147
1148         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1149         {
1150                 fs &= 0xf0;     /* Mask off the rate select bits */
1151
1152                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1153                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1154         }
1155         old_fs = ad_read(devc, 8);
1156
1157         if (devc->model == MD_4232 || devc->model >= MD_4236)
1158         {
1159                 tmp = ad_read(devc, 16);
1160                 ad_write(devc, 16, tmp | 0x30);
1161         }
1162         if (devc->model == MD_IWAVE)
1163                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1164
1165         ad_write(devc, 8, fs);
1166
1167         /*
1168          * Write to I8 starts resynchronization. Wait until it completes.
1169          */
1170
1171         timeout = 0;
1172         while (timeout < 100 && inb(devc->base) != 0x80)
1173                 timeout++;
1174         timeout = 0;
1175         while (timeout < 10000 && inb(devc->base) == 0x80)
1176                 timeout++;
1177
1178         if (devc->model >= MD_4232)
1179                 ad_write(devc, 16, tmp & ~0x30);
1180
1181         ad_leave_MCE(devc);     /*
1182                                  * Starts the calibration process.
1183                                  */
1184         spin_unlock_irqrestore(&devc->lock,flags);
1185         devc->xfer_count = 0;
1186
1187 #ifndef EXCLUDE_TIMERS
1188         if (dev == timer_installed && devc->timer_running)
1189                 if ((fs & 0x01) != (old_fs & 0x01))
1190                 {
1191                         ad1848_tmr_reprogram(dev);
1192                 }
1193 #endif
1194         ad1848_halt_output(dev);
1195         return 0;
1196 }
1197
1198 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1199 {
1200         int timeout;
1201         unsigned char fs, old_fs, tmp = 0;
1202         unsigned long flags;
1203         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1204         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1205
1206         if (devc->audio_mode)
1207                 return 0;
1208
1209         spin_lock_irqsave(&devc->lock,flags);
1210         fs = portc->speed_bits | (portc->format_bits << 5);
1211
1212         if (portc->channels > 1)
1213                 fs |= 0x10;
1214
1215         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1216
1217         if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE))        /* Use alternate speed select registers */
1218         {
1219                 fs &= 0xf0;     /* Mask off the rate select bits */
1220
1221                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1222                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1223         }
1224         if (devc->model == MD_4232)
1225         {
1226                 tmp = ad_read(devc, 16);
1227                 ad_write(devc, 16, tmp | 0x30);
1228         }
1229         if (devc->model == MD_IWAVE)
1230                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1231
1232         /*
1233          * If mode >= 2 (CS4231), set I28. It's the capture format register.
1234          */
1235
1236         if (devc->model != MD_1848)
1237         {
1238                 old_fs = ad_read(devc, 28);
1239                 ad_write(devc, 28, fs);
1240
1241                 /*
1242                  * Write to I28 starts resynchronization. Wait until it completes.
1243                  */
1244
1245                 timeout = 0;
1246                 while (timeout < 100 && inb(devc->base) != 0x80)
1247                         timeout++;
1248
1249                 timeout = 0;
1250                 while (timeout < 10000 && inb(devc->base) == 0x80)
1251                         timeout++;
1252
1253                 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1254                 {
1255                         /*
1256                          * CS4231 compatible devices don't have separate sampling rate selection
1257                          * register for recording an playback. The I8 register is shared so we have to
1258                          * set the speed encoding bits of it too.
1259                          */
1260                         unsigned char   tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1261
1262                         ad_write(devc, 8, tmp);
1263                         /*
1264                          * Write to I8 starts resynchronization. Wait until it completes.
1265                          */
1266                         timeout = 0;
1267                         while (timeout < 100 && inb(devc->base) != 0x80)
1268                                 timeout++;
1269
1270                         timeout = 0;
1271                         while (timeout < 10000 && inb(devc->base) == 0x80)
1272                                 timeout++;
1273                 }
1274         }
1275         else
1276         {                       /* For AD1848 set I8. */
1277
1278                 old_fs = ad_read(devc, 8);
1279                 ad_write(devc, 8, fs);
1280                 /*
1281                  * Write to I8 starts resynchronization. Wait until it completes.
1282                  */
1283                 timeout = 0;
1284                 while (timeout < 100 && inb(devc->base) != 0x80)
1285                         timeout++;
1286                 timeout = 0;
1287                 while (timeout < 10000 && inb(devc->base) == 0x80)
1288                         timeout++;
1289         }
1290
1291         if (devc->model == MD_4232)
1292                 ad_write(devc, 16, tmp & ~0x30);
1293
1294         ad_leave_MCE(devc);     /*
1295                                  * Starts the calibration process.
1296                                  */
1297         spin_unlock_irqrestore(&devc->lock,flags);
1298         devc->xfer_count = 0;
1299
1300 #ifndef EXCLUDE_TIMERS
1301         if (dev == timer_installed && devc->timer_running)
1302         {
1303                 if ((fs & 0x01) != (old_fs & 0x01))
1304                 {
1305                         ad1848_tmr_reprogram(dev);
1306                 }
1307         }
1308 #endif
1309         ad1848_halt_input(dev);
1310         return 0;
1311 }
1312
1313 static void ad1848_halt(int dev)
1314 {
1315         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1316         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1317
1318         unsigned char   bits = ad_read(devc, 9);
1319
1320         if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1321                 ad1848_halt_output(dev);
1322
1323         if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1324                 ad1848_halt_input(dev);
1325         devc->audio_mode = 0;
1326 }
1327
1328 static void ad1848_halt_input(int dev)
1329 {
1330         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1331         unsigned long   flags;
1332
1333         if (!(ad_read(devc, 9) & 0x02))
1334                 return;         /* Capture not enabled */
1335
1336         spin_lock_irqsave(&devc->lock,flags);
1337
1338         ad_mute(devc);
1339
1340         {
1341                 int             tmout;
1342
1343                 if(!isa_dma_bridge_buggy)
1344                         disable_dma(audio_devs[dev]->dmap_in->dma);
1345
1346                 for (tmout = 0; tmout < 100000; tmout++)
1347                         if (ad_read(devc, 11) & 0x10)
1348                                 break;
1349                 ad_write(devc, 9, ad_read(devc, 9) & ~0x02);    /* Stop capture */
1350
1351                 if(!isa_dma_bridge_buggy)
1352                         enable_dma(audio_devs[dev]->dmap_in->dma);
1353                 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1354         }
1355
1356         outb(0, io_Status(devc));       /* Clear interrupt status */
1357         outb(0, io_Status(devc));       /* Clear interrupt status */
1358
1359         devc->audio_mode &= ~PCM_ENABLE_INPUT;
1360
1361         spin_unlock_irqrestore(&devc->lock,flags);
1362 }
1363
1364 static void ad1848_halt_output(int dev)
1365 {
1366         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1367         unsigned long flags;
1368
1369         if (!(ad_read(devc, 9) & 0x01))
1370                 return;         /* Playback not enabled */
1371
1372         spin_lock_irqsave(&devc->lock,flags);
1373
1374         ad_mute(devc);
1375         {
1376                 int             tmout;
1377
1378                 if(!isa_dma_bridge_buggy)
1379                         disable_dma(audio_devs[dev]->dmap_out->dma);
1380
1381                 for (tmout = 0; tmout < 100000; tmout++)
1382                         if (ad_read(devc, 11) & 0x10)
1383                                 break;
1384                 ad_write(devc, 9, ad_read(devc, 9) & ~0x01);    /* Stop playback */
1385
1386                 if(!isa_dma_bridge_buggy)
1387                        enable_dma(audio_devs[dev]->dmap_out->dma);
1388
1389                 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1390         }
1391
1392         outb((0), io_Status(devc));     /* Clear interrupt status */
1393         outb((0), io_Status(devc));     /* Clear interrupt status */
1394
1395         devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1396
1397         spin_unlock_irqrestore(&devc->lock,flags);
1398 }
1399
1400 static void ad1848_trigger(int dev, int state)
1401 {
1402         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1403         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1404         unsigned long   flags;
1405         unsigned char   tmp, old;
1406
1407         spin_lock_irqsave(&devc->lock,flags);
1408         state &= devc->audio_mode;
1409
1410         tmp = old = ad_read(devc, 9);
1411
1412         if (portc->open_mode & OPEN_READ)
1413         {
1414                   if (state & PCM_ENABLE_INPUT)
1415                           tmp |= 0x02;
1416                   else
1417                           tmp &= ~0x02;
1418         }
1419         if (portc->open_mode & OPEN_WRITE)
1420         {
1421                 if (state & PCM_ENABLE_OUTPUT)
1422                         tmp |= 0x01;
1423                 else
1424                         tmp &= ~0x01;
1425         }
1426         /* ad_mute(devc); */
1427         if (tmp != old)
1428         {
1429                   ad_write(devc, 9, tmp);
1430                   ad_unmute(devc);
1431         }
1432         spin_unlock_irqrestore(&devc->lock,flags);
1433 }
1434
1435 static void ad1848_init_hw(ad1848_info * devc)
1436 {
1437         int i;
1438         int *init_values;
1439
1440         /*
1441          * Initial values for the indirect registers of CS4248/AD1848.
1442          */
1443         static int      init_values_a[] =
1444         {
1445                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1446                 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1447
1448         /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1449                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1450                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1451         };
1452
1453         static int      init_values_b[] =
1454         {
1455                 /*
1456                    Values for the newer chips
1457                    Some of the register initialization values were changed. In
1458                    order to get rid of the click that preceded PCM playback,
1459                    calibration was disabled on the 10th byte. On that same byte,
1460                    dual DMA was enabled; on the 11th byte, ADC dithering was
1461                    enabled, since that is theoretically desirable; on the 13th
1462                    byte, Mode 3 was selected, to enable access to extended
1463                    registers.
1464                  */
1465                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1466                 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1467                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1468                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1469         };
1470
1471         /*
1472          *      Select initialisation data
1473          */
1474
1475         init_values = init_values_a;
1476         if(devc->model >= MD_4236)
1477                 init_values = init_values_b;
1478
1479         for (i = 0; i < 16; i++)
1480                 ad_write(devc, i, init_values[i]);
1481
1482
1483         ad_mute(devc);          /* Initialize some variables */
1484         ad_unmute(devc);        /* Leave it unmuted now */
1485
1486         if (devc->model > MD_1848)
1487         {
1488                 if (devc->model == MD_1845_SSCAPE)
1489                         ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1490                 else
1491                         ad_write(devc, 12, ad_read(devc, 12) | 0x40);           /* Mode2 = enabled */
1492
1493                 if (devc->model == MD_IWAVE)
1494                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1495
1496                 if (devc->model != MD_1845_SSCAPE)
1497                         for (i = 16; i < 32; i++)
1498                                 ad_write(devc, i, init_values[i]);
1499
1500                 if (devc->model == MD_IWAVE)
1501                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1502         }
1503         if (devc->model > MD_1848)
1504         {
1505                 if (devc->audio_flags & DMA_DUPLEX)
1506                         ad_write(devc, 9, ad_read(devc, 9) & ~0x04);    /* Dual DMA mode */
1507                 else
1508                         ad_write(devc, 9, ad_read(devc, 9) | 0x04);     /* Single DMA mode */
1509
1510                 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1511                         ad_write(devc, 27, ad_read(devc, 27) | 0x08);           /* Alternate freq select enabled */
1512
1513                 if (devc->model == MD_IWAVE)
1514                 {               /* Some magic Interwave specific initialization */
1515                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1516                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1517                         ad_write(devc, 17, 0xc2);       /* Alternate feature enable */
1518                 }
1519         }
1520         else
1521         {
1522                   devc->audio_flags &= ~DMA_DUPLEX;
1523                   ad_write(devc, 9, ad_read(devc, 9) | 0x04);   /* Single DMA mode */
1524                   if (soundpro)
1525                           ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1526         }
1527
1528         outb((0), io_Status(devc));     /* Clear pending interrupts */
1529
1530         /*
1531          * Toggle the MCE bit. It completes the initialization phase.
1532          */
1533
1534         ad_enter_MCE(devc);     /* In case the bit was off */
1535         ad_leave_MCE(devc);
1536
1537         ad1848_mixer_reset(devc);
1538 }
1539
1540 int ad1848_detect(int io_base, int *ad_flags, int *osp)
1541 {
1542         unsigned char tmp;
1543         ad1848_info *devc = &adev_info[nr_ad1848_devs];
1544         unsigned char tmp1 = 0xff, tmp2 = 0xff;
1545         int optiC930 = 0;       /* OPTi 82C930 flag */
1546         int interwave = 0;
1547         int ad1847_flag = 0;
1548         int cs4248_flag = 0;
1549         int sscape_flag = 0;
1550
1551         int i;
1552
1553         DDB(printk("ad1848_detect(%x)\n", io_base));
1554
1555         if (ad_flags)
1556         {
1557                 if (*ad_flags == 0x12345678)
1558                 {
1559                         interwave = 1;
1560                         *ad_flags = 0;
1561                 }
1562
1563                 if (*ad_flags == 0x87654321)
1564                 {
1565                         sscape_flag = 1;
1566                         *ad_flags = 0;
1567                 }
1568
1569                 if (*ad_flags == 0x12345677)
1570                 {
1571                     cs4248_flag = 1;
1572                     *ad_flags = 0;
1573                 }
1574         }
1575         if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1576         {
1577                 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1578                 return 0;
1579         }
1580         if (check_region(io_base, 4))
1581         {
1582                 printk(KERN_ERR "ad1848.c: Port %x not free.\n", io_base);
1583                 return 0;
1584         }
1585         spin_lock_init(&devc->lock);
1586         devc->base = io_base;
1587         devc->irq_ok = 0;
1588         devc->timer_running = 0;
1589         devc->MCE_bit = 0x40;
1590         devc->irq = 0;
1591         devc->open_mode = 0;
1592         devc->chip_name = devc->name = "AD1848";
1593         devc->model = MD_1848;  /* AD1848 or CS4248 */
1594         devc->levels = NULL;
1595         devc->debug_flag = 0;
1596
1597         /*
1598          * Check that the I/O address is in use.
1599          *
1600          * The bit 0x80 of the base I/O port is known to be 0 after the
1601          * chip has performed its power on initialization. Just assume
1602          * this has happened before the OS is starting.
1603          *
1604          * If the I/O address is unused, it typically returns 0xff.
1605          */
1606
1607         if (inb(devc->base) == 0xff)
1608         {
1609                 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1610         }
1611
1612         /*
1613          * Wait for the device to stop initialization
1614          */
1615
1616         DDB(printk("ad1848_detect() - step 0\n"));
1617
1618         for (i = 0; i < 10000000; i++)
1619         {
1620                 unsigned char   x = inb(devc->base);
1621
1622                 if (x == 0xff || !(x & 0x80))
1623                         break;
1624         }
1625
1626         DDB(printk("ad1848_detect() - step A\n"));
1627
1628         if (inb(devc->base) == 0x80)    /* Not ready. Let's wait */
1629                 ad_leave_MCE(devc);
1630
1631         if ((inb(devc->base) & 0x80) != 0x00)   /* Not a AD1848 */
1632         {
1633                 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1634                 return 0;
1635         }
1636
1637         /*
1638          * Test if it's possible to change contents of the indirect registers.
1639          * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1640          * so try to avoid using it.
1641          */
1642
1643         DDB(printk("ad1848_detect() - step B\n"));
1644         ad_write(devc, 0, 0xaa);
1645         ad_write(devc, 1, 0x45);        /* 0x55 with bit 0x10 clear */
1646
1647         if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1648         {
1649                 if (tmp2 == 0x65)       /* AD1847 has couple of bits hardcoded to 1 */
1650                         ad1847_flag = 1;
1651                 else
1652                 {
1653                         DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1654                         return 0;
1655                 }
1656         }
1657         DDB(printk("ad1848_detect() - step C\n"));
1658         ad_write(devc, 0, 0x45);
1659         ad_write(devc, 1, 0xaa);
1660
1661         if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1662         {
1663                 if (tmp2 == 0x8a)       /* AD1847 has few bits hardcoded to 1 */
1664                         ad1847_flag = 1;
1665                 else
1666                 {
1667                         DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1668                         return 0;
1669                 }
1670         }
1671
1672         /*
1673          * The indirect register I12 has some read only bits. Let's
1674          * try to change them.
1675          */
1676
1677         DDB(printk("ad1848_detect() - step D\n"));
1678         tmp = ad_read(devc, 12);
1679         ad_write(devc, 12, (~tmp) & 0x0f);
1680
1681         if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1682         {
1683                 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1684                 return 0;
1685         }
1686
1687         /*
1688          * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1689          *   0x01=RevB and 0x0A=RevC.
1690          */
1691
1692         /*
1693          * The original AD1848/CS4248 has just 15 indirect registers. This means
1694          * that I0 and I16 should return the same value (etc.).
1695          * However this doesn't work with CS4248. Actually it seems to be impossible
1696          * to detect if the chip is a CS4231 or CS4248.
1697          * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1698          * with CS4231.
1699          */
1700
1701         /*
1702          * OPTi 82C930 has mode2 control bit in another place. This test will fail
1703          * with it. Accept this situation as a possible indication of this chip.
1704          */
1705
1706         DDB(printk("ad1848_detect() - step F\n"));
1707         ad_write(devc, 12, 0);  /* Mode2=disabled */
1708
1709         for (i = 0; i < 16; i++)
1710         {
1711                 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1712                 {
1713                         DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1714                         if (!ad1847_flag)
1715                                 optiC930 = 1;
1716                         break;
1717                 }
1718         }
1719
1720         /*
1721          * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1722          * The bit 0x80 is always 1 in CS4248 and CS4231.
1723          */
1724
1725         DDB(printk("ad1848_detect() - step G\n"));
1726
1727         if (ad_flags && *ad_flags == 400)
1728                 *ad_flags = 0;
1729         else
1730                 ad_write(devc, 12, 0x40);       /* Set mode2, clear 0x80 */
1731
1732
1733         if (ad_flags)
1734                 *ad_flags = 0;
1735
1736         tmp1 = ad_read(devc, 12);
1737         if (tmp1 & 0x80)
1738         {
1739                 if (ad_flags)
1740                         *ad_flags |= AD_F_CS4248;
1741
1742                 devc->chip_name = "CS4248";     /* Our best knowledge just now */
1743         }
1744         if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1745         {
1746                 /*
1747                  *      CS4231 detected - is it?
1748                  *
1749                  *      Verify that setting I0 doesn't change I16.
1750                  */
1751
1752                 DDB(printk("ad1848_detect() - step H\n"));
1753                 ad_write(devc, 16, 0);  /* Set I16 to known value */
1754
1755                 ad_write(devc, 0, 0x45);
1756                 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1757                 {
1758                         ad_write(devc, 0, 0xaa);
1759                         if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1760                         {
1761                                 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1762                                 return 0;
1763                         }
1764
1765                         /*
1766                          * Verify that some bits of I25 are read only.
1767                          */
1768
1769                         DDB(printk("ad1848_detect() - step I\n"));
1770                         tmp1 = ad_read(devc, 25);       /* Original bits */
1771                         ad_write(devc, 25, ~tmp1);      /* Invert all bits */
1772                         if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1773                         {
1774                                 int id;
1775
1776                                 /*
1777                                  *      It's at least CS4231
1778                                  */
1779
1780                                 devc->chip_name = "CS4231";
1781                                 devc->model = MD_4231;
1782
1783                                 /*
1784                                  * It could be an AD1845 or CS4231A as well.
1785                                  * CS4231 and AD1845 report the same revision info in I25
1786                                  * while the CS4231A reports different.
1787                                  */
1788
1789                                 id = ad_read(devc, 25);
1790                                 if ((id & 0xe7) == 0x80)        /* Device busy??? */
1791                                         id = ad_read(devc, 25);
1792                                 if ((id & 0xe7) == 0x80)        /* Device still busy??? */
1793                                         id = ad_read(devc, 25);
1794                                 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1795
1796                                 if ((id & 0xe7) == 0x80) {
1797                                         /*
1798                                          * It must be a CS4231 or AD1845. The register I23 of
1799                                          * CS4231 is undefined and it appears to be read only.
1800                                          * AD1845 uses I23 for setting sample rate. Assume
1801                                          * the chip is AD1845 if I23 is changeable.
1802                                          */
1803
1804                                         unsigned char   tmp = ad_read(devc, 23);
1805                                         ad_write(devc, 23, ~tmp);
1806
1807                                         if (interwave)
1808                                         {
1809                                                 devc->model = MD_IWAVE;
1810                                                 devc->chip_name = "IWave";
1811                                         }
1812                                         else if (ad_read(devc, 23) != tmp)      /* AD1845 ? */
1813                                         {
1814                                                 devc->chip_name = "AD1845";
1815                                                 devc->model = MD_1845;
1816                                         }
1817                                         else if (cs4248_flag)
1818                                         {
1819                                                 if (ad_flags)
1820                                                           *ad_flags |= AD_F_CS4248;
1821                                                 devc->chip_name = "CS4248";
1822                                                 devc->model = MD_1848;
1823                                                 ad_write(devc, 12, ad_read(devc, 12) & ~0x40);  /* Mode2 off */
1824                                         }
1825                                         ad_write(devc, 23, tmp);        /* Restore */
1826                                 }
1827                                 else
1828                                 {
1829                                         switch (id & 0x1f) {
1830                                         case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1831                                                 {
1832                                                         int xid;
1833                                                         ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1834                                                         ad_write(devc, 23, 0x9c); /* select extended register 25 */
1835                                                         xid = inb(io_Indexed_Data(devc));
1836                                                         ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1837                                                         switch (xid & 0x1f)
1838                                                         {
1839                                                                 case 0x00:
1840                                                                         devc->chip_name = "CS4237B(B)";
1841                                                                         devc->model = MD_42xB;
1842                                                                         break;
1843                                                                 case 0x08:
1844                                                                         /* Seems to be a 4238 ?? */
1845                                                                         devc->chip_name = "CS4238";
1846                                                                         devc->model = MD_42xB;
1847                                                                         break;
1848                                                                 case 0x09:
1849                                                                         devc->chip_name = "CS4238B";
1850                                                                         devc->model = MD_42xB;
1851                                                                         break;
1852                                                                 case 0x0b:
1853                                                                         devc->chip_name = "CS4236B";
1854                                                                         devc->model = MD_4236;
1855                                                                         break;
1856                                                                 case 0x10:
1857                                                                         devc->chip_name = "CS4237B";
1858                                                                         devc->model = MD_42xB;
1859                                                                         break;
1860                                                                 case 0x1d:
1861                                                                         devc->chip_name = "CS4235";
1862                                                                         devc->model = MD_4235;
1863                                                                         break;
1864                                                                 case 0x1e:
1865                                                                         devc->chip_name = "CS4239";
1866                                                                         devc->model = MD_4239;
1867                                                                         break;
1868                                                                 default:
1869                                                                         printk("Chip ident is %X.\n", xid&0x1F);
1870                                                                         devc->chip_name = "CS42xx";
1871                                                                         devc->model = MD_4232;
1872                                                                         break;
1873                                                         }
1874                                                 }
1875                                                 break;
1876
1877                                         case 2: /* CS4232/CS4232A */
1878                                                 devc->chip_name = "CS4232";
1879                                                 devc->model = MD_4232;
1880                                                 break;
1881
1882                                         case 0:
1883                                                 if ((id & 0xe0) == 0xa0)
1884                                                 {
1885                                                         devc->chip_name = "CS4231A";
1886                                                         devc->model = MD_4231A;
1887                                                 }
1888                                                 else
1889                                                 {
1890                                                         devc->chip_name = "CS4321";
1891                                                         devc->model = MD_4231;
1892                                                 }
1893                                                 break;
1894
1895                                         default: /* maybe */
1896                                                 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1897                                                 if (optiC930)
1898                                                 {
1899                                                         devc->chip_name = "82C930";
1900                                                         devc->model = MD_C930;
1901                                                 }
1902                                                 else
1903                                                 {
1904                                                         devc->chip_name = "CS4231";
1905                                                         devc->model = MD_4231;
1906                                                 }
1907                                         }
1908                                 }
1909                         }
1910                         ad_write(devc, 25, tmp1);       /* Restore bits */
1911
1912                         DDB(printk("ad1848_detect() - step K\n"));
1913                 }
1914         } else if (tmp1 == 0x0a) {
1915                 /*
1916                  * Is it perhaps a SoundPro CMI8330?
1917                  * If so, then we should be able to change indirect registers
1918                  * greater than I15 after activating MODE2, even though reading
1919                  * back I12 does not show it.
1920                  */
1921
1922                 /*
1923                  * Let's try comparing register values
1924                  */
1925                 for (i = 0; i < 16; i++) {
1926                         if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1927                                 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1928                                 soundpro = 1;
1929                                 devc->chip_name = "SoundPro CMI 8330";
1930                                 break;
1931                         }
1932                 }
1933         }
1934
1935         DDB(printk("ad1848_detect() - step L\n"));
1936         if (ad_flags)
1937         {
1938                   if (devc->model != MD_1848)
1939                           *ad_flags |= AD_F_CS4231;
1940         }
1941         DDB(printk("ad1848_detect() - Detected OK\n"));
1942
1943         if (devc->model == MD_1848 && ad1847_flag)
1944                 devc->chip_name = "AD1847";
1945
1946
1947         if (sscape_flag == 1)
1948                 devc->model = MD_1845_SSCAPE;
1949
1950         return 1;
1951 }
1952
1953 int ad1848_init (char *name, int io_base, int irq, int dma_playback,
1954                 int dma_capture, int share_dma, int *osp, struct module *owner)
1955 {
1956         /*
1957          * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1958          *   so that this driver doesn't need to allocate/deallocate it.
1959          *   The actually used IRQ is ABS(irq).
1960          */
1961
1962         int my_dev;
1963         char dev_name[100];
1964         int e;
1965
1966         ad1848_info  *devc = &adev_info[nr_ad1848_devs];
1967
1968         ad1848_port_info *portc = NULL;
1969
1970         devc->irq = (irq > 0) ? irq : 0;
1971         devc->open_mode = 0;
1972         devc->timer_ticks = 0;
1973         devc->dma1 = dma_playback;
1974         devc->dma2 = dma_capture;
1975         devc->subtype = cfg.card_subtype;
1976         devc->audio_flags = DMA_AUTOMODE;
1977         devc->playback_dev = devc->record_dev = 0;
1978         if (name != NULL)
1979                 devc->name = name;
1980
1981         if (name != NULL && name[0] != 0)
1982                 sprintf(dev_name,
1983                         "%s (%s)", name, devc->chip_name);
1984         else
1985                 sprintf(dev_name,
1986                         "Generic audio codec (%s)", devc->chip_name);
1987
1988         if (!request_region(devc->base, 4, devc->name))
1989                 return -1;
1990
1991         conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1992
1993         if (devc->model == MD_1848 || devc->model == MD_C930)
1994                 devc->audio_flags |= DMA_HARDSTOP;
1995
1996         if (devc->model > MD_1848)
1997         {
1998                 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1999                         devc->audio_flags &= ~DMA_DUPLEX;
2000                 else
2001                         devc->audio_flags |= DMA_DUPLEX;
2002         }
2003
2004         portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
2005         if(portc==NULL) {
2006                 release_region(devc->base, 4);
2007                 return -1;
2008         }
2009
2010         if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2011                                              dev_name,
2012                                              &ad1848_audio_driver,
2013                                              sizeof(struct audio_driver),
2014                                              devc->audio_flags,
2015                                              ad_format_mask[devc->model],
2016                                              devc,
2017                                              dma_playback,
2018                                              dma_capture)) < 0)
2019         {
2020                 release_region(devc->base, 4);
2021                 kfree(portc);
2022                 return -1;
2023         }
2024
2025         audio_devs[my_dev]->portc = portc;
2026         audio_devs[my_dev]->mixer_dev = -1;
2027         if (owner)
2028                 audio_devs[my_dev]->d->owner = owner;
2029         memset((char *) portc, 0, sizeof(*portc));
2030
2031         nr_ad1848_devs++;
2032
2033         devc->pmdev = pm_register(PM_ISA_DEV, my_dev, ad1848_pm_callback);
2034         if (devc->pmdev)
2035                 devc->pmdev->data = devc;
2036
2037         ad1848_init_hw(devc);
2038
2039         if (irq > 0)
2040         {
2041                 devc->dev_no = my_dev;
2042                 if (request_irq(devc->irq, adintr, 0, devc->name, (void *)my_dev) < 0)
2043                 {
2044                         printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2045                         /* Don't free it either then.. */
2046                         devc->irq = 0;
2047                 }
2048                 if (capabilities[devc->model].flags & CAP_F_TIMER)
2049                 {
2050 #ifndef CONFIG_SMP
2051                         int x;
2052                         unsigned char tmp = ad_read(devc, 16);
2053 #endif
2054
2055                         devc->timer_ticks = 0;
2056
2057                         ad_write(devc, 21, 0x00);       /* Timer MSB */
2058                         ad_write(devc, 20, 0x10);       /* Timer LSB */
2059 #ifndef CONFIG_SMP
2060                         ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2061                         for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2062                         ad_write(devc, 16, tmp & ~0x40);        /* Disable timer */
2063
2064                         if (devc->timer_ticks == 0)
2065                                 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2066                         else
2067                         {
2068                                 DDB(printk("Interrupt test OK\n"));
2069                                 devc->irq_ok = 1;
2070                         }
2071 #else
2072                         devc->irq_ok = 1;
2073 #endif
2074                 }
2075                 else
2076                         devc->irq_ok = 1;       /* Couldn't test. assume it's OK */
2077         } else if (irq < 0)
2078                 irq2dev[-irq] = devc->dev_no = my_dev;
2079
2080 #ifndef EXCLUDE_TIMERS
2081         if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2082             devc->irq_ok)
2083                 ad1848_tmr_install(my_dev);
2084 #endif
2085
2086         if (!share_dma)
2087         {
2088                 if (sound_alloc_dma(dma_playback, devc->name))
2089                         printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2090
2091                 if (dma_capture != dma_playback)
2092                         if (sound_alloc_dma(dma_capture, devc->name))
2093                                 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2094         }
2095
2096         if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2097                                      dev_name,
2098                                      &ad1848_mixer_operations,
2099                                      sizeof(struct mixer_operations),
2100                                      devc)) >= 0)
2101         {
2102                 audio_devs[my_dev]->mixer_dev = e;
2103                 if (owner)
2104                         mixer_devs[e]->owner = owner;
2105         }
2106         return my_dev;
2107 }
2108
2109 int ad1848_control(int cmd, int arg)
2110 {
2111         ad1848_info *devc;
2112         unsigned long flags;
2113
2114         if (nr_ad1848_devs < 1)
2115                 return -ENODEV;
2116
2117         devc = &adev_info[nr_ad1848_devs - 1];
2118
2119         switch (cmd)
2120         {
2121                 case AD1848_SET_XTAL:   /* Change clock frequency of AD1845 (only ) */
2122                         if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
2123                                 return -EINVAL;
2124                         spin_lock_irqsave(&devc->lock,flags);
2125                         ad_enter_MCE(devc);
2126                         ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2127                         ad_leave_MCE(devc);
2128                         spin_unlock_irqrestore(&devc->lock,flags);
2129                         break;
2130
2131                 case AD1848_MIXER_REROUTE:
2132                 {
2133                         int o = (arg >> 8) & 0xff;
2134                         int n = arg & 0xff;
2135
2136                         if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2137                                 return -EINVAL;
2138
2139                         if (!(devc->supported_devices & (1 << o)) &&
2140                             !(devc->supported_rec_devices & (1 << o)))
2141                                 return -EINVAL;
2142
2143                         if (n == SOUND_MIXER_NONE)
2144                         {       /* Just hide this control */
2145                                 ad1848_mixer_set(devc, o, 0);   /* Shut up it */
2146                                 devc->supported_devices &= ~(1 << o);
2147                                 devc->supported_rec_devices &= ~(1 << o);
2148                                 break;
2149                         }
2150
2151                         /* Make the mixer control identified by o to appear as n */
2152                         if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2153                                 return -EINVAL;
2154
2155                         devc->mixer_reroute[n] = o;     /* Rename the control */
2156                         if (devc->supported_devices & (1 << o))
2157                                 devc->supported_devices |= (1 << n);
2158                         if (devc->supported_rec_devices & (1 << o))
2159                                 devc->supported_rec_devices |= (1 << n);
2160
2161                         devc->supported_devices &= ~(1 << o);
2162                         devc->supported_rec_devices &= ~(1 << o);
2163                 }
2164                 break;
2165         }
2166         return 0;
2167 }
2168
2169 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2170 {
2171         int i, mixer, dev = 0;
2172         ad1848_info *devc = NULL;
2173
2174         for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2175         {
2176                 if (adev_info[i].base == io_base)
2177                 {
2178                         devc = &adev_info[i];
2179                         dev = devc->dev_no;
2180                 }
2181         }
2182
2183         if (devc != NULL)
2184         {
2185                 if(audio_devs[dev]->portc!=NULL)
2186                         kfree(audio_devs[dev]->portc);
2187                 release_region(devc->base, 4);
2188
2189                 if (!share_dma)
2190                 {
2191                         if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2192                                 free_irq(devc->irq, (void *)devc->dev_no);
2193
2194                         sound_free_dma(dma_playback);
2195
2196                         if (dma_playback != dma_capture)
2197                                 sound_free_dma(dma_capture);
2198
2199                 }
2200                 mixer = audio_devs[devc->dev_no]->mixer_dev;
2201                 if(mixer>=0)
2202                         sound_unload_mixerdev(mixer);
2203
2204                 if (devc->pmdev)
2205                         pm_unregister(devc->pmdev);
2206
2207                 nr_ad1848_devs--;
2208                 for ( ; i < nr_ad1848_devs ; i++)
2209                         adev_info[i] = adev_info[i+1];
2210         }
2211         else
2212                 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2213 }
2214
2215 irqreturn_t adintr(int irq, void *dev_id, struct pt_regs *dummy)
2216 {
2217         unsigned char status;
2218         ad1848_info *devc;
2219         int dev;
2220         int alt_stat = 0xff;
2221         unsigned char c930_stat = 0;
2222         int cnt = 0;
2223
2224         dev = (int)dev_id;
2225         devc = (ad1848_info *) audio_devs[dev]->devc;
2226
2227 interrupt_again:                /* Jump back here if int status doesn't reset */
2228
2229         status = inb(io_Status(devc));
2230
2231         if (status == 0x80)
2232                 printk(KERN_DEBUG "adintr: Why?\n");
2233         if (devc->model == MD_1848)
2234                 outb((0), io_Status(devc));     /* Clear interrupt status */
2235
2236         if (status & 0x01)
2237         {
2238                 if (devc->model == MD_C930)
2239                 {               /* 82C930 has interrupt status register in MAD16 register MC11 */
2240
2241                         spin_lock(&devc->lock);
2242
2243                         /* 0xe0e is C930 address port
2244                          * 0xe0f is C930 data port
2245                          */
2246                         outb(11, 0xe0e);
2247                         c930_stat = inb(0xe0f);
2248                         outb((~c930_stat), 0xe0f);
2249
2250                         spin_unlock(&devc->lock);
2251
2252                         alt_stat = (c930_stat << 2) & 0x30;
2253                 }
2254                 else if (devc->model != MD_1848)
2255                 {
2256                         spin_lock(&devc->lock);
2257                         alt_stat = ad_read(devc, 24);
2258                         ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat);      /* Selective ack */
2259                         spin_unlock(&devc->lock);
2260                 }
2261
2262                 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2263                 {
2264                         DMAbuf_inputintr(devc->record_dev);
2265                 }
2266                 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2267                       (alt_stat & 0x10))
2268                 {
2269                         DMAbuf_outputintr(devc->playback_dev, 1);
2270                 }
2271                 if (devc->model != MD_1848 && (alt_stat & 0x40))        /* Timer interrupt */
2272                 {
2273                         devc->timer_ticks++;
2274 #ifndef EXCLUDE_TIMERS
2275                         if (timer_installed == dev && devc->timer_running)
2276                                 sound_timer_interrupt();
2277 #endif
2278                 }
2279         }
2280 /*
2281  * Sometimes playback or capture interrupts occur while a timer interrupt
2282  * is being handled. The interrupt will not be retriggered if we don't
2283  * handle it now. Check if an interrupt is still pending and restart
2284  * the handler in this case.
2285  */
2286         if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2287         {
2288                   goto interrupt_again;
2289         }
2290         return IRQ_HANDLED;
2291 }
2292
2293 /*
2294  *      Experimental initialization sequence for the integrated sound system
2295  *      of the Compaq Deskpro M.
2296  */
2297
2298 static int init_deskpro_m(struct address_info *hw_config)
2299 {
2300         unsigned char   tmp;
2301
2302         if ((tmp = inb(0xc44)) == 0xff)
2303         {
2304                 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2305                 return 0;
2306         }
2307
2308         outb(0x10, 0xc44);
2309         outb(0x40, 0xc45);
2310         outb(0x00, 0xc46);
2311         outb(0xe8, 0xc47);
2312         outb(0x14, 0xc44);
2313         outb(0x40, 0xc45);
2314         outb(0x00, 0xc46);
2315         outb(0xe8, 0xc47);
2316         outb(0x10, 0xc44);
2317
2318         return 1;
2319 }
2320
2321 /*
2322  *      Experimental initialization sequence for the integrated sound system
2323  *      of Compaq Deskpro XL.
2324  */
2325
2326 static int init_deskpro(struct address_info *hw_config)
2327 {
2328         unsigned char   tmp;
2329
2330         if ((tmp = inb(0xc44)) == 0xff)
2331         {
2332                 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2333                 return 0;
2334         }
2335         outb((tmp | 0x04), 0xc44);      /* Select bank 1 */
2336         if (inb(0xc44) != 0x04)
2337         {
2338                 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2339                 return 0;
2340         }
2341         /*
2342          * OK. It looks like a Deskpro so let's proceed.
2343          */
2344
2345         /*
2346          * I/O port 0xc44 Audio configuration register.
2347          *
2348          * bits 0xc0:   Audio revision bits
2349          *              0x00 = Compaq Business Audio
2350          *              0x40 = MS Sound System Compatible (reset default)
2351          *              0x80 = Reserved
2352          *              0xc0 = Reserved
2353          * bit 0x20:    No Wait State Enable
2354          *              0x00 = Disabled (reset default, DMA mode)
2355          *              0x20 = Enabled (programmed I/O mode)
2356          * bit 0x10:    MS Sound System Decode Enable
2357          *              0x00 = Decoding disabled (reset default)
2358          *              0x10 = Decoding enabled
2359          * bit 0x08:    FM Synthesis Decode Enable
2360          *              0x00 = Decoding Disabled (reset default)
2361          *              0x08 = Decoding enabled
2362          * bit 0x04     Bank select
2363          *              0x00 = Bank 0
2364          *              0x04 = Bank 1
2365          * bits 0x03    MSS Base address
2366          *              0x00 = 0x530 (reset default)
2367          *              0x01 = 0x604
2368          *              0x02 = 0xf40
2369          *              0x03 = 0xe80
2370          */
2371
2372 #ifdef DEBUGXL
2373         /* Debug printing */
2374         printk("Port 0xc44 (before): ");
2375         outb((tmp & ~0x04), 0xc44);
2376         printk("%02x ", inb(0xc44));
2377         outb((tmp | 0x04), 0xc44);
2378         printk("%02x\n", inb(0xc44));
2379 #endif
2380
2381         /* Set bank 1 of the register */
2382         tmp = 0x58;             /* MSS Mode, MSS&FM decode enabled */
2383
2384         switch (hw_config->io_base)
2385         {
2386                 case 0x530:
2387                         tmp |= 0x00;
2388                         break;
2389                 case 0x604:
2390                         tmp |= 0x01;
2391                         break;
2392                 case 0xf40:
2393                         tmp |= 0x02;
2394                         break;
2395                 case 0xe80:
2396                         tmp |= 0x03;
2397                         break;
2398                 default:
2399                         DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2400                         return 0;
2401         }
2402         outb((tmp & ~0x04), 0xc44);     /* Write to bank=0 */
2403
2404 #ifdef DEBUGXL
2405         /* Debug printing */
2406         printk("Port 0xc44 (after): ");
2407         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2408         printk("%02x ", inb(0xc44));
2409         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2410         printk("%02x\n", inb(0xc44));
2411 #endif
2412
2413         /*
2414          * I/O port 0xc45 FM Address Decode/MSS ID Register.
2415          *
2416          * bank=0, bits 0xfe:   FM synthesis Decode Compare bits 7:1 (default=0x88)
2417          * bank=0, bit 0x01:    SBIC Power Control Bit
2418          *                      0x00 = Powered up
2419          *                      0x01 = Powered down
2420          * bank=1, bits 0xfc:   MSS ID (default=0x40)
2421          */
2422
2423 #ifdef DEBUGXL
2424         /* Debug printing */
2425         printk("Port 0xc45 (before): ");
2426         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2427         printk("%02x ", inb(0xc45));
2428         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2429         printk("%02x\n", inb(0xc45));
2430 #endif
2431
2432         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2433         outb((0x88), 0xc45);    /* FM base 7:0 = 0x88 */
2434         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2435         outb((0x10), 0xc45);    /* MSS ID = 0x10 (MSS port returns 0x04) */
2436
2437 #ifdef DEBUGXL
2438         /* Debug printing */
2439         printk("Port 0xc45 (after): ");
2440         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2441         printk("%02x ", inb(0xc45));
2442         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2443         printk("%02x\n", inb(0xc45));
2444 #endif
2445
2446
2447         /*
2448          * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2449          *
2450          * bank=0, bits 0xff:   FM synthesis Decode Compare bits 15:8 (default=0x03)
2451          * bank=1, bits 0xff:   Audio addressing ASIC id
2452          */
2453
2454 #ifdef DEBUGXL
2455         /* Debug printing */
2456         printk("Port 0xc46 (before): ");
2457         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2458         printk("%02x ", inb(0xc46));
2459         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2460         printk("%02x\n", inb(0xc46));
2461 #endif
2462
2463         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2464         outb((0x03), 0xc46);    /* FM base 15:8 = 0x03 */
2465         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2466         outb((0x11), 0xc46);    /* ASIC ID = 0x11 */
2467
2468 #ifdef DEBUGXL
2469         /* Debug printing */
2470         printk("Port 0xc46 (after): ");
2471         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2472         printk("%02x ", inb(0xc46));
2473         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2474         printk("%02x\n", inb(0xc46));
2475 #endif
2476
2477         /*
2478          * I/O port 0xc47 FM Address Decode Register.
2479          *
2480          * bank=0, bits 0xff:   Decode enable selection for various FM address bits
2481          * bank=1, bits 0xff:   Reserved
2482          */
2483
2484 #ifdef DEBUGXL
2485         /* Debug printing */
2486         printk("Port 0xc47 (before): ");
2487         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2488         printk("%02x ", inb(0xc47));
2489         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2490         printk("%02x\n", inb(0xc47));
2491 #endif
2492
2493         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2494         outb((0x7c), 0xc47);    /* FM decode enable bits = 0x7c */
2495         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2496         outb((0x00), 0xc47);    /* Reserved bank1 = 0x00 */
2497
2498 #ifdef DEBUGXL
2499         /* Debug printing */
2500         printk("Port 0xc47 (after): ");
2501         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2502         printk("%02x ", inb(0xc47));
2503         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2504         printk("%02x\n", inb(0xc47));
2505 #endif
2506
2507         /*
2508          * I/O port 0xc6f = Audio Disable Function Register
2509          */
2510
2511 #ifdef DEBUGXL
2512         printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2513 #endif
2514
2515         outb((0x80), 0xc6f);
2516
2517 #ifdef DEBUGXL
2518         printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2519 #endif
2520
2521         return 1;
2522 }
2523
2524 int probe_ms_sound(struct address_info *hw_config)
2525 {
2526         unsigned char   tmp;
2527
2528         DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2529
2530         if (check_region(hw_config->io_base, 8))
2531         {
2532                 printk(KERN_ERR "MSS: I/O port conflict\n");
2533                 return 0;
2534         }
2535         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2536         {
2537                 /* check_opl3(0x388, hw_config); */
2538                 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2539         }
2540
2541         if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2542         {
2543                 if (!init_deskpro(hw_config))
2544                         return 0;
2545         }
2546
2547         if (deskpro_m)  /* Compaq Deskpro M */
2548         {
2549                 if (!init_deskpro_m(hw_config))
2550                         return 0;
2551         }
2552
2553         /*
2554            * Check if the IO port returns valid signature. The original MS Sound
2555            * system returns 0x04 while some cards (AudioTrix Pro for example)
2556            * return 0x00 or 0x0f.
2557          */
2558
2559         if ((tmp = inb(hw_config->io_base + 3)) == 0xff)        /* Bus float */
2560         {
2561                   int             ret;
2562
2563                   DDB(printk("I/O address is inactive (%x)\n", tmp));
2564                   if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2565                           return 0;
2566                   return 1;
2567         }
2568         DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2569         if ((tmp & 0x3f) != 0x04 &&
2570             (tmp & 0x3f) != 0x0f &&
2571             (tmp & 0x3f) != 0x00)
2572         {
2573                 int ret;
2574
2575                 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2576                 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2577                 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2578                         return 0;
2579
2580                 hw_config->card_subtype = 1;
2581                 return 1;
2582         }
2583         if ((hw_config->irq != 5)  &&
2584             (hw_config->irq != 7)  &&
2585             (hw_config->irq != 9)  &&
2586             (hw_config->irq != 10) &&
2587             (hw_config->irq != 11) &&
2588             (hw_config->irq != 12))
2589         {
2590                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2591                 return 0;
2592         }
2593         if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2594         {
2595                   printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2596                   return 0;
2597         }
2598         /*
2599          * Check that DMA0 is not in use with a 8 bit board.
2600          */
2601
2602         if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2603         {
2604                 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2605                 return 0;
2606         }
2607         if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2608         {
2609                 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2610                 return 0;
2611         }
2612         return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2613 }
2614
2615 void attach_ms_sound(struct address_info *hw_config, struct module *owner)
2616 {
2617         static signed char interrupt_bits[12] =
2618         {
2619                 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2620         };
2621         signed char     bits;
2622         char            dma2_bit = 0;
2623
2624         static char     dma_bits[4] =
2625         {
2626                 1, 2, 0, 3
2627         };
2628
2629         int config_port = hw_config->io_base + 0;
2630         int version_port = hw_config->io_base + 3;
2631         int dma = hw_config->dma;
2632         int dma2 = hw_config->dma2;
2633
2634         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2635         {
2636                 hw_config->slots[0] = ad1848_init("MS Sound System", hw_config->io_base + 4,
2637                                                     hw_config->irq,
2638                                                     hw_config->dma,
2639                                                     hw_config->dma2, 0,
2640                                                     hw_config->osp,
2641                                                     owner);
2642                 request_region(hw_config->io_base, 4, "WSS config");
2643                 return;
2644         }
2645         /*
2646          * Set the IRQ and DMA addresses.
2647          */
2648
2649         bits = interrupt_bits[hw_config->irq];
2650         if (bits == -1)
2651         {
2652                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2653                 return;
2654         }
2655         outb((bits | 0x40), config_port);
2656         if ((inb(version_port) & 0x40) == 0)
2657                 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2658
2659 /*
2660  * Handle the capture DMA channel
2661  */
2662
2663         if (dma2 != -1 && dma2 != dma)
2664         {
2665                 if (!((dma == 0 && dma2 == 1) ||
2666                         (dma == 1 && dma2 == 0) ||
2667                         (dma == 3 && dma2 == 0)))
2668                 {       /* Unsupported combination. Try to swap channels */
2669                         int tmp = dma;
2670
2671                         dma = dma2;
2672                         dma2 = tmp;
2673                 }
2674                 if ((dma == 0 && dma2 == 1) ||
2675                         (dma == 1 && dma2 == 0) ||
2676                         (dma == 3 && dma2 == 0))
2677                 {
2678                         dma2_bit = 0x04;        /* Enable capture DMA */
2679                 }
2680                 else
2681                 {
2682                         printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2683                         dma2 = dma;
2684                 }
2685         }
2686         else
2687         {
2688                 dma2 = dma;
2689         }
2690
2691         hw_config->dma = dma;
2692         hw_config->dma2 = dma2;
2693
2694         outb((bits | dma_bits[dma] | dma2_bit), config_port);   /* Write IRQ+DMA setup */
2695
2696         hw_config->slots[0] = ad1848_init("MS Sound System", hw_config->io_base + 4,
2697                                           hw_config->irq,
2698                                           dma, dma2, 0,
2699                                           hw_config->osp,
2700                                           THIS_MODULE);
2701         request_region(hw_config->io_base, 4, "WSS config");
2702 }
2703
2704 void unload_ms_sound(struct address_info *hw_config)
2705 {
2706         ad1848_unload(hw_config->io_base + 4,
2707                       hw_config->irq,
2708                       hw_config->dma,
2709                       hw_config->dma2, 0);
2710         sound_unload_audiodev(hw_config->slots[0]);
2711         release_region(hw_config->io_base, 4);
2712 }
2713
2714 #ifndef EXCLUDE_TIMERS
2715
2716 /*
2717  * Timer stuff (for /dev/music).
2718  */
2719
2720 static unsigned int current_interval;
2721
2722 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2723 {
2724         unsigned long   flags;
2725         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2726         unsigned long   xtal_nsecs;     /* nanoseconds per xtal oscillator tick */
2727         unsigned long   divider;
2728
2729         spin_lock_irqsave(&devc->lock,flags);
2730
2731         /*
2732          * Length of the timer interval (in nanoseconds) depends on the
2733          * selected crystal oscillator. Check this from bit 0x01 of I8.
2734          *
2735          * AD1845 has just one oscillator which has cycle time of 10.050 us
2736          * (when a 24.576 MHz xtal oscillator is used).
2737          *
2738          * Convert requested interval to nanoseconds before computing
2739          * the timer divider.
2740          */
2741
2742         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2743                 xtal_nsecs = 10050;
2744         else if (ad_read(devc, 8) & 0x01)
2745                 xtal_nsecs = 9920;
2746         else
2747                 xtal_nsecs = 9969;
2748
2749         divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2750
2751         if (divider < 100)      /* Don't allow shorter intervals than about 1ms */
2752                 divider = 100;
2753
2754         if (divider > 65535)    /* Overflow check */
2755                 divider = 65535;
2756
2757         ad_write(devc, 21, (divider >> 8) & 0xff);      /* Set upper bits */
2758         ad_write(devc, 20, divider & 0xff);     /* Set lower bits */
2759         ad_write(devc, 16, ad_read(devc, 16) | 0x40);   /* Start the timer */
2760         devc->timer_running = 1;
2761         spin_unlock_irqrestore(&devc->lock,flags);
2762
2763         return current_interval = (divider * xtal_nsecs + 500) / 1000;
2764 }
2765
2766 static void ad1848_tmr_reprogram(int dev)
2767 {
2768         /*
2769          *    Audio driver has changed sampling rate so that a different xtal
2770          *      oscillator was selected. We have to reprogram the timer rate.
2771          */
2772
2773         ad1848_tmr_start(dev, current_interval);
2774         sound_timer_syncinterval(current_interval);
2775 }
2776
2777 static void ad1848_tmr_disable(int dev)
2778 {
2779         unsigned long   flags;
2780         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2781
2782         spin_lock_irqsave(&devc->lock,flags);
2783         ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2784         devc->timer_running = 0;
2785         spin_unlock_irqrestore(&devc->lock,flags);
2786 }
2787
2788 static void ad1848_tmr_restart(int dev)
2789 {
2790         unsigned long   flags;
2791         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2792
2793         if (current_interval == 0)
2794                 return;
2795
2796         spin_lock_irqsave(&devc->lock,flags);
2797         ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2798         devc->timer_running = 1;
2799         spin_unlock_irqrestore(&devc->lock,flags);
2800 }
2801
2802 static struct sound_lowlev_timer ad1848_tmr =
2803 {
2804         0,
2805         2,
2806         ad1848_tmr_start,
2807         ad1848_tmr_disable,
2808         ad1848_tmr_restart
2809 };
2810
2811 static int ad1848_tmr_install(int dev)
2812 {
2813         if (timer_installed != -1)
2814                 return 0;       /* Don't install another timer */
2815
2816         timer_installed = ad1848_tmr.dev = dev;
2817         sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2818
2819         return 1;
2820 }
2821 #endif /* EXCLUDE_TIMERS */
2822
2823 static int ad1848_suspend(ad1848_info *devc)
2824 {
2825         unsigned long flags;
2826
2827         spin_lock_irqsave(&devc->lock,flags);
2828
2829         ad_mute(devc);
2830
2831         spin_unlock_irqrestore(&devc->lock,flags);
2832         return 0;
2833 }
2834
2835 static int ad1848_resume(ad1848_info *devc)
2836 {
2837         int mixer_levels[32], i;
2838
2839         /* Thinkpad is a bit more of PITA than normal. The BIOS tends to
2840            restore it in a different config to the one we use.  Need to
2841            fix this somehow */
2842
2843         /* store old mixer levels */
2844         memcpy(mixer_levels, devc->levels, sizeof (mixer_levels));
2845         ad1848_init_hw(devc);
2846
2847         /* restore mixer levels */
2848         for (i = 0; i < 32; i++)
2849                 ad1848_mixer_set(devc, devc->dev_no, mixer_levels[i]);
2850
2851         if (!devc->subtype) {
2852                 static signed char interrupt_bits[12] = { -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20 };
2853                 static char dma_bits[4] = { 1, 2, 0, 3 };
2854                 unsigned long flags;
2855                 signed char bits;
2856                 char dma2_bit = 0;
2857
2858                 int config_port = devc->base + 0;
2859
2860                 bits = interrupt_bits[devc->irq];
2861                 if (bits == -1) {
2862                         printk(KERN_ERR "MSS: Bad IRQ %d\n", devc->irq);
2863                         return -1;
2864                 }
2865
2866                 spin_lock_irqsave(&devc->lock,flags);
2867
2868                 outb((bits | 0x40), config_port);
2869
2870                 if (devc->dma2 != -1 && devc->dma2 != devc->dma1)
2871                         if ( (devc->dma1 == 0 && devc->dma2 == 1) ||
2872                              (devc->dma1 == 1 && devc->dma2 == 0) ||
2873                              (devc->dma1 == 3 && devc->dma2 == 0))
2874                                 dma2_bit = 0x04;
2875
2876                 outb((bits | dma_bits[devc->dma1] | dma2_bit), config_port);
2877                 spin_unlock_irqrestore(&devc->lock,flags);
2878         }
2879
2880         return 0;
2881 }
2882
2883 static int ad1848_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
2884 {
2885         ad1848_info *devc = dev->data;
2886         if (devc) {
2887                 DEB(printk("ad1848: pm event received: 0x%x\n", rqst));
2888
2889                 switch (rqst) {
2890                 case PM_SUSPEND:
2891                         ad1848_suspend(devc);
2892                         break;
2893                 case PM_RESUME:
2894                         ad1848_resume(devc);
2895                         break;
2896                 }
2897         }
2898         return 0;
2899 }
2900
2901
2902 EXPORT_SYMBOL(ad1848_detect);
2903 EXPORT_SYMBOL(ad1848_init);
2904 EXPORT_SYMBOL(ad1848_unload);
2905 EXPORT_SYMBOL(ad1848_control);
2906 EXPORT_SYMBOL(adintr);
2907 EXPORT_SYMBOL(probe_ms_sound);
2908 EXPORT_SYMBOL(attach_ms_sound);
2909 EXPORT_SYMBOL(unload_ms_sound);
2910
2911 static int __initdata io = -1;
2912 static int __initdata irq = -1;
2913 static int __initdata dma = -1;
2914 static int __initdata dma2 = -1;
2915 static int __initdata type = 0;
2916
2917 MODULE_PARM(io, "i");                   /* I/O for a raw AD1848 card */
2918 MODULE_PARM(irq, "i");                  /* IRQ to use */
2919 MODULE_PARM(dma, "i");                  /* First DMA channel */
2920 MODULE_PARM(dma2, "i");                 /* Second DMA channel */
2921 MODULE_PARM(type, "i");                 /* Card type */
2922 MODULE_PARM(deskpro_xl, "i");           /* Special magic for Deskpro XL boxen */
2923 MODULE_PARM(deskpro_m, "i");            /* Special magic for Deskpro M box */
2924 MODULE_PARM(soundpro, "i");             /* More special magic for SoundPro chips */
2925
2926 #ifdef CONFIG_PNP
2927 MODULE_PARM(isapnp,     "i");
2928 MODULE_PARM(isapnpjump, "i");
2929 MODULE_PARM(reverse,    "i");
2930 MODULE_PARM_DESC(isapnp,        "When set to 0, Plug & Play support will be disabled");
2931 MODULE_PARM_DESC(isapnpjump,    "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2932 MODULE_PARM_DESC(reverse,       "When set to 1, will reverse ISAPnP search order");
2933
2934 struct pnp_dev  *ad1848_dev  = NULL;
2935
2936 /* Please add new entries at the end of the table */
2937 static struct {
2938         char *name;
2939         unsigned short  card_vendor, card_device,
2940                         vendor, function;
2941         short mss_io, irq, dma, dma2;   /* index into isapnp table */
2942         int type;
2943 } ad1848_isapnp_list[] __initdata = {
2944         {"CMI 8330 SoundPRO",
2945                 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2946                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2947                 0, 0, 0,-1, 0},
2948         {"CS4232 based card",
2949                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2950                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2951                 0, 0, 0, 1, 0},
2952         {"CS4232 based card",
2953                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2954                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2955                 0, 0, 0, 1, 0},
2956         {"OPL3-SA2 WSS mode",
2957                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2958                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2959                 1, 0, 0, 1, 1},
2960         {"Advanced Gravis InterWave Audio",
2961                 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2962                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2963                 0, 0, 0, 1, 0},
2964         {0}
2965 };
2966
2967 static struct isapnp_device_id id_table[] __devinitdata = {
2968         {       ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2969                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2970         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2971                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2972         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2973                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2974         /* The main driver for this card is opl3sa2
2975         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2976                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2977         */
2978         {       ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2979                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2980         {0}
2981 };
2982
2983 MODULE_DEVICE_TABLE(isapnp, id_table);
2984
2985 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2986 {
2987         int err;
2988
2989         err = pnp_device_attach(dev);
2990         if (err < 0)
2991                 return(NULL);
2992
2993         if((err = pnp_activate_dev(dev)) < 0) {
2994                 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2995
2996                 pnp_device_detach(dev);
2997
2998                 return(NULL);
2999         }
3000         audio_activated = 1;
3001         return(dev);
3002 }
3003
3004 static struct pnp_dev *ad1848_init_generic(struct pnp_card *bus, struct address_info *hw_config, int slot)
3005 {
3006
3007         /* Configure Audio device */
3008         if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
3009         {
3010                 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
3011                 {
3012                         hw_config->io_base      = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
3013                         hw_config->irq          = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
3014                         hw_config->dma          = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
3015                         if(ad1848_isapnp_list[slot].dma2 != -1)
3016                                 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
3017                         else
3018                                 hw_config->dma2 = -1;
3019                         hw_config->card_subtype = ad1848_isapnp_list[slot].type;
3020                 } else
3021                         return(NULL);
3022         } else
3023                 return(NULL);
3024
3025         return(ad1848_dev);
3026 }
3027
3028 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
3029 {
3030         char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
3031
3032         /* Initialize this baby. */
3033
3034         if(ad1848_init_generic(bus, hw_config, slot)) {
3035                 /* We got it. */
3036
3037                 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
3038                        busname,
3039                        hw_config->io_base, hw_config->irq, hw_config->dma,
3040                        hw_config->dma2);
3041                 return 1;
3042         }
3043         return 0;
3044 }
3045
3046 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
3047 {
3048         static int first = 1;
3049         int i;
3050
3051         /* Count entries in sb_isapnp_list */
3052         for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
3053         i--;
3054
3055         /* Check and adjust isapnpjump */
3056         if( isapnpjump < 0 || isapnpjump > i) {
3057                 isapnpjump = reverse ? i : 0;
3058                 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
3059         }
3060
3061         if(!first || !reverse)
3062                 i = isapnpjump;
3063         first = 0;
3064         while(ad1848_isapnp_list[i].card_vendor != 0) {
3065                 static struct pnp_card *bus = NULL;
3066
3067                 while ((bus = pnp_find_card(
3068                                 ad1848_isapnp_list[i].card_vendor,
3069                                 ad1848_isapnp_list[i].card_device,
3070                                 bus))) {
3071
3072                         if(ad1848_isapnp_init(hw_config, bus, i)) {
3073                                 isapnpjump = i; /* start next search from here */
3074                                 return 0;
3075                         }
3076                 }
3077                 i += reverse ? -1 : 1;
3078         }
3079
3080         return -ENODEV;
3081 }
3082 #endif
3083
3084
3085 static int __init init_ad1848(void)
3086 {
3087         printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
3088
3089 #ifdef CONFIG_PNP
3090         if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
3091                 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
3092                 isapnp = 0;
3093         }
3094 #endif
3095
3096         if(io != -1) {
3097                 if( isapnp == 0 )
3098                 {
3099                         if(irq == -1 || dma == -1) {
3100                                 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3101                                 return -EINVAL;
3102                         }
3103
3104                         cfg.irq = irq;
3105                         cfg.io_base = io;
3106                         cfg.dma = dma;
3107                         cfg.dma2 = dma2;
3108                         cfg.card_subtype = type;
3109                 }
3110
3111                 if(!probe_ms_sound(&cfg))
3112                         return -ENODEV;
3113                 attach_ms_sound(&cfg, THIS_MODULE);
3114                 loaded = 1;
3115         }
3116         return 0;
3117 }
3118
3119 static void __exit cleanup_ad1848(void)
3120 {
3121         if(loaded)
3122                 unload_ms_sound(&cfg);
3123
3124 #ifdef CONFIG_PNP
3125         if(ad1848_dev){
3126                 if(audio_activated)
3127                         pnp_device_detach(ad1848_dev);
3128         }
3129 #endif
3130 }
3131
3132 module_init(init_ad1848);
3133 module_exit(cleanup_ad1848);
3134
3135 #ifndef MODULE
3136 static int __init setup_ad1848(char *str)
3137 {
3138         /* io, irq, dma, dma2, type */
3139         int ints[6];
3140
3141         str = get_options(str, ARRAY_SIZE(ints), ints);
3142
3143         io      = ints[1];
3144         irq     = ints[2];
3145         dma     = ints[3];
3146         dma2    = ints[4];
3147         type    = ints[5];
3148
3149         return 1;
3150 }
3151
3152 __setup("ad1848=", setup_ad1848);
3153 #endif
3154 MODULE_LICENSE("GPL");