sound/oss/cmpci.c

   1 /*
   2  *      cmpci.c  --  C-Media PCI audio driver.
   3  *
   4  *      Copyright (C) 1999  C-media support (support@cmedia.com.tw)
   5  *
   6  *      Based on the PCI drivers by Thomas Sailer (sailer@ife.ee.ethz.ch)
   7  *
   8  *      For update, visit:
   9  *              http://www.cmedia.com.tw
  10  *
  11  *      This program is free software; you can redistribute it and/or modify
  12  *      it under the terms of the GNU General Public License as published by
  13  *      the Free Software Foundation; either version 2 of the License, or
  14  *      (at your option) any later version.
  15  *
  16  *      This program is distributed in the hope that it will be useful,
  17  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *      GNU General Public License for more details.
  20  *
  21  *      You should have received a copy of the GNU General Public License
  22  *      along with this program; if not, write to the Free Software
  23  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  * Special thanks to David C. Niemi, Jan Pfeifer
  26  *
  27  *
  28  * Module command line parameters:
  29  *   none so far
  30  *
  31  *
  32  *  Supported devices:
  33  *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  34  *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  35  *  /dev/midi   simple MIDI UART interface, no ioctl
  36  *
  37  *  The card has both an FM and a Wavetable synth, but I have to figure
  38  *  out first how to drive them...
  39  *
  40  *  Revision history
  41  *    06.05.98   0.1   Initial release
  42  *    10.05.98   0.2   Fixed many bugs, esp. ADC rate calculation
  43  *                     First stab at a simple midi interface (no bells&whistles)
  44  *    13.05.98   0.3   Fix stupid cut&paste error: set_adc_rate was called instead of
  45  *                     set_dac_rate in the FMODE_WRITE case in cm_open
  46  *                     Fix hwptr out of bounds (now mpg123 works)
  47  *    14.05.98   0.4   Don't allow excessive interrupt rates
  48  *    08.06.98   0.5   First release using Alan Cox' soundcore instead of miscdevice
  49  *    03.08.98   0.6   Do not include modversions.h
  50  *                     Now mixer behaviour can basically be selected between
  51  *                     "OSS documented" and "OSS actual" behaviour
  52  *    31.08.98   0.7   Fix realplayer problems - dac.count issues
  53  *    10.12.98   0.8   Fix drain_dac trying to wait on not yet initialized DMA
  54  *    16.12.98   0.9   Fix a few f_file & FMODE_ bugs
  55  *    06.01.99   0.10  remove the silly SA_INTERRUPT flag.
  56  *                     hopefully killed the egcs section type conflict
  57  *    12.03.99   0.11  cinfo.blocks should be reset after GETxPTR ioctl.
  58  *                     reported by Johan Maes <joma@telindus.be>
  59  *    22.03.99   0.12  return EAGAIN instead of EBUSY when O_NONBLOCK
  60  *                     read/write cannot be executed
  61  *    18.08.99   1.5   Only deallocate DMA buffer when unloading.
  62  *    02.09.99   1.6   Enable SPDIF LOOP
  63  *                     Change the mixer read back
  64  *    21.09.99   2.33  Use RCS version as driver version.
  65  *                     Add support for modem, S/PDIF loop and 4 channels.
  66  *                     (8738 only)
  67  *                     Fix bug cause x11amp cannot play.
  68  *
  69  *    Fixes:
  70  *    Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  71  *    18/05/2001 - .bss nitpicks, fix a bug in set_dac_channels where it
  72  *                 was calling prog_dmabuf with s->lock held, call missing
  73  *                 unlock_kernel in cm_midi_release
  74  *    08/10/2001 - use set_current_state in some more places
  75  *
  76  *      Carlos Eduardo Gorges <carlos@techlinux.com.br>
  77  *      Fri May 25 2001
  78  *      - SMP support ( spin[un]lock* revision )
  79  *      - speaker mixer support
  80  *      Mon Aug 13 2001
  81  *      - optimizations and cleanups
  82  *
  83  *    03/01/2003 - open_mode fixes from Georg Acher <acher@in.tum.de>
  84  *      Simon Braunschmidt <brasimon@web.de>
  85  *     Sat Jan 31 2004
  86  *      - provide support for opl3 FM by releasing IO range after initialization
  87  *
  88  *    ChenLi Tien <cltien@cmedia.com.tw>
  89  *    Mar 9 2004
  90  *      - Fix S/PDIF out if spdif_loop enabled
  91  *      - Load opl3 driver if enabled (fmio in proper range)
  92  *      - Load mpu401 if enabled (mpuio in proper range)
  93  *    Apr 5 2004
  94  *      - Fix DUAL_DAC dma synchronization bug
  95  *      - Check exist FM/MPU401 I/O before activate.
  96  *      - Add AFTM_S16_BE format support, so MPlayer/Xine can play AC3/mutlichannel
  97  *        on Mac
  98  *      - Change to support kernel 2.6 so only small patch needed
  99  *      - All parameters default to 0
 100  *      - Add spdif_out to send PCM through S/PDIF out jack
 101  *      - Add hw_copy to get 4-spaker output for general PCM/analog output
 102  *
 103  *    Stefan Thater <stefan.thaeter@gmx.de>
 104  *    Apr 5 2004
 105  *      - Fix mute single channel for CD/Line-in/AUX-in
 106  */
 107 /*****************************************************************************/
 108
 109 #include <linux/config.h>
 110 #include <linux/module.h>
 111 #include <linux/string.h>
 112 #include <linux/interrupt.h>
 113 #include <linux/ioport.h>
 114 #include <linux/sched.h>
 115 #include <linux/delay.h>
 116 #include <linux/sound.h>
 117 #include <linux/slab.h>
 118 #include <linux/soundcard.h>
 119 #include <linux/pci.h>
 120 #include <linux/init.h>
 121 #include <linux/poll.h>
 122 #include <linux/spinlock.h>
 123 #include <linux/smp_lock.h>
 124 #include <linux/bitops.h>
 125 #include <linux/wait.h>
 126
 127 #include <asm/io.h>
 128 #include <asm/page.h>
 129 #include <asm/uaccess.h>
 130
 131 #ifdef CONFIG_SOUND_CMPCI_MIDI
 132 #include "sound_config.h"
 133 #include "mpu401.h"
 134 #endif
 135 #ifdef CONFIG_SOUND_CMPCI_FM
 136 #include "opl3.h"
 137 #endif
 138 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
 139 #include <linux/gameport.h>
 140 #endif
 141
 142 /* --------------------------------------------------------------------- */
 143 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 144 #undef DMABYTEIO
 145 #define DBG(x) {}
 146 /* --------------------------------------------------------------------- */
 147
 148 #define CM_MAGIC  ((PCI_VENDOR_ID_CMEDIA<<16)|PCI_DEVICE_ID_CMEDIA_CM8338A)
 149
 150 /* CM8338 registers definition ****************/
 151
 152 #define CODEC_CMI_FUNCTRL0              (0x00)
 153 #define CODEC_CMI_FUNCTRL1              (0x04)
 154 #define CODEC_CMI_CHFORMAT              (0x08)
 155 #define CODEC_CMI_INT_HLDCLR            (0x0C)
 156 #define CODEC_CMI_INT_STATUS            (0x10)
 157 #define CODEC_CMI_LEGACY_CTRL           (0x14)
 158 #define CODEC_CMI_MISC_CTRL             (0x18)
 159 #define CODEC_CMI_TDMA_POS              (0x1C)
 160 #define CODEC_CMI_MIXER                 (0x20)
 161 #define CODEC_SB16_DATA                 (0x22)
 162 #define CODEC_SB16_ADDR                 (0x23)
 163 #define CODEC_CMI_MIXER1                (0x24)
 164 #define CODEC_CMI_MIXER2                (0x25)
 165 #define CODEC_CMI_AUX_VOL               (0x26)
 166 #define CODEC_CMI_MISC                  (0x27)
 167 #define CODEC_CMI_AC97                  (0x28)
 168
 169 #define CODEC_CMI_CH0_FRAME1            (0x80)
 170 #define CODEC_CMI_CH0_FRAME2            (0x84)
 171 #define CODEC_CMI_CH1_FRAME1            (0x88)
 172 #define CODEC_CMI_CH1_FRAME2            (0x8C)
 173
 174 #define CODEC_CMI_SPDIF_CTRL            (0x90)
 175 #define CODEC_CMI_MISC_CTRL2            (0x92)
 176
 177 #define CODEC_CMI_EXT_REG               (0xF0)
 178
 179 /*  Mixer registers for SB16 ******************/
 180
 181 #define DSP_MIX_DATARESETIDX            ((unsigned char)(0x00))
 182
 183 #define DSP_MIX_MASTERVOLIDX_L          ((unsigned char)(0x30))
 184 #define DSP_MIX_MASTERVOLIDX_R          ((unsigned char)(0x31))
 185 #define DSP_MIX_VOICEVOLIDX_L           ((unsigned char)(0x32))
 186 #define DSP_MIX_VOICEVOLIDX_R           ((unsigned char)(0x33))
 187 #define DSP_MIX_FMVOLIDX_L              ((unsigned char)(0x34))
 188 #define DSP_MIX_FMVOLIDX_R              ((unsigned char)(0x35))
 189 #define DSP_MIX_CDVOLIDX_L              ((unsigned char)(0x36))
 190 #define DSP_MIX_CDVOLIDX_R              ((unsigned char)(0x37))
 191 #define DSP_MIX_LINEVOLIDX_L            ((unsigned char)(0x38))
 192 #define DSP_MIX_LINEVOLIDX_R            ((unsigned char)(0x39))
 193
 194 #define DSP_MIX_MICVOLIDX               ((unsigned char)(0x3A))
 195 #define DSP_MIX_SPKRVOLIDX              ((unsigned char)(0x3B))
 196
 197 #define DSP_MIX_OUTMIXIDX               ((unsigned char)(0x3C))
 198
 199 #define DSP_MIX_ADCMIXIDX_L             ((unsigned char)(0x3D))
 200 #define DSP_MIX_ADCMIXIDX_R             ((unsigned char)(0x3E))
 201
 202 #define DSP_MIX_INGAINIDX_L             ((unsigned char)(0x3F))
 203 #define DSP_MIX_INGAINIDX_R             ((unsigned char)(0x40))
 204 #define DSP_MIX_OUTGAINIDX_L            ((unsigned char)(0x41))
 205 #define DSP_MIX_OUTGAINIDX_R            ((unsigned char)(0x42))
 206
 207 #define DSP_MIX_AGCIDX                  ((unsigned char)(0x43))
 208
 209 #define DSP_MIX_TREBLEIDX_L             ((unsigned char)(0x44))
 210 #define DSP_MIX_TREBLEIDX_R             ((unsigned char)(0x45))
 211 #define DSP_MIX_BASSIDX_L               ((unsigned char)(0x46))
 212 #define DSP_MIX_BASSIDX_R               ((unsigned char)(0x47))
 213 #define DSP_MIX_EXTENSION               ((unsigned char)(0xf0))
 214 // pseudo register for AUX
 215 #define DSP_MIX_AUXVOL_L                ((unsigned char)(0x50))
 216 #define DSP_MIX_AUXVOL_R                ((unsigned char)(0x51))
 217
 218 // I/O length
 219 #define CM_EXTENT_CODEC   0x100
 220 #define CM_EXTENT_MIDI    0x2
 221 #define CM_EXTENT_SYNTH   0x4
 222 #define CM_EXTENT_GAME    0x8
 223
 224 // Function Control Register 0 (00h)
 225 #define CHADC0          0x01
 226 #define CHADC1          0x02
 227 #define PAUSE0          0x04
 228 #define PAUSE1          0x08
 229
 230 // Function Control Register 0+2 (02h)
 231 #define CHEN0           0x01
 232 #define CHEN1           0x02
 233 #define RST_CH0         0x04
 234 #define RST_CH1         0x08
 235
 236 // Function Control Register 1 (04h)
 237 #define JYSTK_EN        0x02
 238 #define UART_EN         0x04
 239 #define SPDO2DAC        0x40
 240 #define SPDFLOOP        0x80
 241
 242 // Function Control Register 1+1 (05h)
 243 #define SPDF_0          0x01
 244 #define SPDF_1          0x02
 245 #define ASFC            0x1c
 246 #define DSFC            0xe0
 247 #define SPDIF2DAC       (SPDF_1 << 8 | SPDO2DAC)
 248
 249 // Channel Format Register (08h)
 250 #define CM_CFMT_STEREO  0x01
 251 #define CM_CFMT_16BIT   0x02
 252 #define CM_CFMT_MASK    0x03
 253 #define POLVALID        0x20
 254 #define INVSPDIFI       0x80
 255
 256 // Channel Format Register+2 (0ah)
 257 #define SPD24SEL        0x20
 258
 259 // Channel Format Register+3 (0bh)
 260 #define CHB3D           0x20
 261 #define CHB3D5C         0x80
 262
 263 // Interrupt Hold/Clear Register+2 (0eh)
 264 #define CH0_INT_EN      0x01
 265 #define CH1_INT_EN      0x02
 266
 267 // Interrupt Register (10h)
 268 #define CHINT0          0x01
 269 #define CHINT1          0x02
 270 #define CH0BUSY         0x04
 271 #define CH1BUSY         0x08
 272
 273 // Legacy Control/Status Register+1 (15h)
 274 #define EXBASEN         0x10
 275 #define BASE2LIN        0x20
 276 #define CENTR2LIN       0x40
 277 #define CB2LIN          (BASE2LIN | CENTR2LIN)
 278 #define CHB3D6C         0x80
 279
 280 // Legacy Control/Status Register+2 (16h)
 281 #define DAC2SPDO        0x20
 282 #define SPDCOPYRHT      0x40
 283 #define ENSPDOUT        0x80
 284
 285 // Legacy Control/Status Register+3 (17h)
 286 #define FMSEL           0x03
 287 #define VSBSEL          0x0c
 288 #define VMPU            0x60
 289 #define NXCHG           0x80
 290
 291 // Miscellaneous Control Register (18h)
 292 #define REAR2LIN        0x20
 293 #define MUTECH1         0x40
 294 #define ENCENTER        0x80
 295
 296 // Miscellaneous Control Register+1 (19h)
 297 #define SELSPDIFI2      0x01
 298 #define SPDF_AC97       0x80
 299
 300 // Miscellaneous Control Register+2 (1ah)
 301 #define AC3_EN          0x04
 302 #define FM_EN           0x08
 303 #define SPD32SEL        0x20
 304 #define XCHGDAC         0x40
 305 #define ENDBDAC         0x80
 306
 307 // Miscellaneous Control Register+3 (1bh)
 308 #define SPDIFI48K       0x01
 309 #define SPDO5V          0x02
 310 #define N4SPK3D         0x04
 311 #define RESET           0x40
 312 #define PWD             0x80
 313 #define SPDIF48K        (SPDIFI48K << 24 | SPDF_AC97 << 8)
 314
 315 // Mixer1 (24h)
 316 #define CDPLAY          0x01
 317 #define X3DEN           0x02
 318 #define REAR2FRONT      0x10
 319 #define SPK4            0x20
 320 #define WSMUTE          0x40
 321 #define FMMUTE          0x80
 322
 323 // Miscellaneous Register (27h)
 324 #define SPDVALID        0x02
 325 #define CENTR2MIC       0x04
 326
 327 // Miscellaneous Register2 (92h)
 328 #define SPD32KFMT       0x10
 329
 330 #define CM_CFMT_DACSHIFT   2
 331 #define CM_CFMT_ADCSHIFT   0
 332 #define CM_FREQ_DACSHIFT   5
 333 #define CM_FREQ_ADCSHIFT   2
 334 #define RSTDAC  RST_CH1
 335 #define RSTADC  RST_CH0
 336 #define ENDAC   CHEN1
 337 #define ENADC   CHEN0
 338 #define PAUSEDAC        PAUSE1
 339 #define PAUSEADC        PAUSE0
 340 #define CODEC_CMI_ADC_FRAME1    CODEC_CMI_CH0_FRAME1
 341 #define CODEC_CMI_ADC_FRAME2    CODEC_CMI_CH0_FRAME2
 342 #define CODEC_CMI_DAC_FRAME1    CODEC_CMI_CH1_FRAME1
 343 #define CODEC_CMI_DAC_FRAME2    CODEC_CMI_CH1_FRAME2
 344 #define DACINT  CHINT1
 345 #define ADCINT  CHINT0
 346 #define DACBUSY CH1BUSY
 347 #define ADCBUSY CH0BUSY
 348 #define ENDACINT        CH1_INT_EN
 349 #define ENADCINT        CH0_INT_EN
 350
 351 static const unsigned sample_size[] = { 1, 2, 2, 4 };
 352 static const unsigned sample_shift[]    = { 0, 1, 1, 2 };
 353
 354 #define SND_DEV_DSP16   5
 355
 356 #define NR_DEVICE 3             /* maximum number of devices */
 357
 358 #define set_dac1_rate   set_adc_rate
 359 #define set_dac1_rate_unlocked  set_adc_rate_unlocked
 360 #define stop_dac1       stop_adc
 361 #define stop_dac1_unlocked      stop_adc_unlocked
 362 #define get_dmadac1     get_dmaadc
 363
 364 static unsigned int devindex = 0;
 365
 366 //*********************************************/
 367
 368 struct cm_state {
 369         /* magic */
 370         unsigned int magic;
 371
 372         /* list of cmedia devices */
 373         struct list_head devs;
 374
 375         /* the corresponding pci_dev structure */
 376         struct pci_dev *dev;
 377
 378         int dev_audio;                  /* soundcore stuff */
 379         int dev_mixer;
 380
 381         unsigned int iosb, iobase, iosynth,
 382                          iomidi, iogame, irq;   /* hardware resources */
 383         unsigned short deviceid;                /* pci_id */
 384
 385         struct {                                /* mixer stuff */
 386                 unsigned int modcnt;
 387                 unsigned short vol[13];
 388         } mix;
 389
 390         unsigned int rateadc, ratedac;          /* wave stuff */
 391         unsigned char fmt, enable;
 392
 393         spinlock_t lock;
 394         struct semaphore open_sem;
 395         mode_t open_mode;
 396         wait_queue_head_t open_wait;
 397
 398         struct dmabuf {
 399                 void *rawbuf;
 400                 dma_addr_t dmaaddr;
 401                 unsigned buforder;
 402                 unsigned numfrag;
 403                 unsigned fragshift;
 404                 unsigned hwptr, swptr;
 405                 unsigned total_bytes;
 406                 int count;
 407                 unsigned error;         /* over/underrun */
 408                 wait_queue_head_t wait;
 409
 410                 unsigned fragsize;      /* redundant, but makes calculations easier */
 411                 unsigned dmasize;
 412                 unsigned fragsamples;
 413                 unsigned dmasamples;
 414
 415                 unsigned mapped:1;      /* OSS stuff */
 416                 unsigned ready:1;
 417                 unsigned endcleared:1;
 418                 unsigned enabled:1;
 419                 unsigned ossfragshift;
 420                 int ossmaxfrags;
 421                 unsigned subdivision;
 422         } dma_dac, dma_adc;
 423
 424 #ifdef CONFIG_SOUND_CMPCI_MIDI
 425         int midi_devc;
 426         struct address_info mpu_data;
 427 #endif
 428 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
 429         struct gameport gameport;
 430 #endif
 431
 432         int     chip_version;
 433         int     max_channels;
 434         int     curr_channels;
 435         int     capability;             /* HW capability, various for chip versions */
 436
 437         int     status;                 /* HW or SW state */
 438
 439         int     spdif_counter;          /* spdif frame counter */
 440 };
 441
 442 /* flags used for capability */
 443 #define CAN_AC3_HW              0x00000001              /* 037 or later */
 444 #define CAN_AC3_SW              0x00000002              /* 033 or later */
 445 #define CAN_AC3                 (CAN_AC3_HW | CAN_AC3_SW)
 446 #define CAN_DUAL_DAC            0x00000004              /* 033 or later */
 447 #define CAN_MULTI_CH_HW         0x00000008              /* 039 or later */
 448 #define CAN_MULTI_CH            (CAN_MULTI_CH_HW | CAN_DUAL_DAC)
 449 #define CAN_LINE_AS_REAR        0x00000010              /* 033 or later */
 450 #define CAN_LINE_AS_BASS        0x00000020              /* 039 or later */
 451 #define CAN_MIC_AS_BASS         0x00000040              /* 039 or later */
 452
 453 /* flags used for status */
 454 #define DO_AC3_HW               0x00000001
 455 #define DO_AC3_SW               0x00000002
 456 #define DO_AC3                  (DO_AC3_HW | DO_AC3_SW)
 457 #define DO_DUAL_DAC             0x00000004
 458 #define DO_MULTI_CH_HW          0x00000008
 459 #define DO_MULTI_CH             (DO_MULTI_CH_HW | DO_DUAL_DAC)
 460 #define DO_LINE_AS_REAR         0x00000010              /* 033 or later */
 461 #define DO_LINE_AS_BASS         0x00000020              /* 039 or later */
 462 #define DO_MIC_AS_BASS          0x00000040              /* 039 or later */
 463 #define DO_SPDIF_OUT            0x00000100
 464 #define DO_SPDIF_IN             0x00000200
 465 #define DO_SPDIF_LOOP           0x00000400
 466 #define DO_BIGENDIAN_W          0x00001000              /* used in PowerPC */
 467 #define DO_BIGENDIAN_R          0x00002000              /* used in PowerPC */
 468
 469 static LIST_HEAD(devs);
 470
 471 static  int     mpuio = 0;
 472 static  int     fmio = 0;
 473 static  int     joystick = 0;
 474 static  int     spdif_inverse = 0;
 475 static  int     spdif_loop = 0;
 476 static  int     spdif_out = 0;
 477 static  int     use_line_as_rear = 0;
 478 static  int     use_line_as_bass = 0;
 479 static  int     use_mic_as_bass = 0;
 480 static  int     mic_boost = 0;
 481 static  int     hw_copy = 0;
 482 MODULE_PARM(mpuio, "i");
 483 MODULE_PARM(fmio, "i");
 484 MODULE_PARM(joystick, "i");
 485 MODULE_PARM(spdif_inverse, "i");
 486 MODULE_PARM(spdif_loop, "i");
 487 MODULE_PARM(spdif_out, "i");
 488 MODULE_PARM(use_line_as_rear, "i");
 489 MODULE_PARM(use_line_as_bass, "i");
 490 MODULE_PARM(use_mic_as_bass, "i");
 491 MODULE_PARM(mic_boost, "i");
 492 MODULE_PARM(hw_copy, "i");
 493 MODULE_PARM_DESC(mpuio, "(0x330, 0x320, 0x310, 0x300) Base of MPU-401, 0 to disable");
 494 MODULE_PARM_DESC(fmio, "(0x388, 0x3C8, 0x3E0) Base of OPL3, 0 to disable");
 495 MODULE_PARM_DESC(joystick, "(1/0) Enable joystick interface, still need joystick driver");
 496 MODULE_PARM_DESC(spdif_inverse, "(1/0) Invert S/PDIF-in signal");
 497 MODULE_PARM_DESC(spdif_loop, "(1/0) Route S/PDIF-in to S/PDIF-out directly");
 498 MODULE_PARM_DESC(spdif_out, "(1/0) Send PCM to S/PDIF-out (PCM volume will not function)");
 499 MODULE_PARM_DESC(use_line_as_rear, "(1/0) Use line-in jack as rear-out");
 500 MODULE_PARM_DESC(use_line_as_bass, "(1/0) Use line-in jack as bass/center");
 501 MODULE_PARM_DESC(use_mic_as_bass, "(1/0) Use mic-in jack as bass/center");
 502 MODULE_PARM_DESC(mic_boost, "(1/0) Enable microphone boost");
 503 MODULE_PARM_DESC(hw_copy, "Copy front channel to surround channel");
 504
 505 /* --------------------------------------------------------------------- */
 506
 507 static inline unsigned ld2(unsigned int x)
 508 {
 509         unsigned exp=16,l=5,r=0;
 510         static const unsigned num[]={0x2,0x4,0x10,0x100,0x10000};
 511
 512         /* num: 2, 4, 16, 256, 65536 */
 513         /* exp: 1, 2,  4,   8,    16 */
 514
 515         while(l--) {
 516                 if( x >= num[l] ) {
 517                         if(num[l]>2) x >>= exp;
 518                         r+=exp;
 519                 }
 520                 exp>>=1;
 521         }
 522
 523         return r;
 524 }
 525
 526 /* --------------------------------------------------------------------- */
 527
 528 static void maskb(unsigned int addr, unsigned int mask, unsigned int value)
 529 {
 530         outb((inb(addr) & mask) | value, addr);
 531 }
 532
 533 static void maskw(unsigned int addr, unsigned int mask, unsigned int value)
 534 {
 535         outw((inw(addr) & mask) | value, addr);
 536 }
 537
 538 static void maskl(unsigned int addr, unsigned int mask, unsigned int value)
 539 {
 540         outl((inl(addr) & mask) | value, addr);
 541 }
 542
 543 static void set_dmadac1(struct cm_state *s, unsigned int addr, unsigned int count)
 544 {
 545         if (addr)
 546             outl(addr, s->iobase + CODEC_CMI_ADC_FRAME1);
 547         outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2);
 548         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC0, 0);
 549 }
 550
 551 static void set_dmaadc(struct cm_state *s, unsigned int addr, unsigned int count)
 552 {
 553         outl(addr, s->iobase + CODEC_CMI_ADC_FRAME1);
 554         outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2);
 555         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, CHADC0);
 556 }
 557
 558 static void set_dmadac(struct cm_state *s, unsigned int addr, unsigned int count)
 559 {
 560         outl(addr, s->iobase + CODEC_CMI_DAC_FRAME1);
 561         outw(count - 1, s->iobase + CODEC_CMI_DAC_FRAME2);
 562         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC1, 0);
 563         if (s->status & DO_DUAL_DAC)
 564                 set_dmadac1(s, 0, count);
 565 }
 566
 567 static void set_countadc(struct cm_state *s, unsigned count)
 568 {
 569         outw(count - 1, s->iobase + CODEC_CMI_ADC_FRAME2 + 2);
 570 }
 571
 572 static void set_countdac(struct cm_state *s, unsigned count)
 573 {
 574         outw(count - 1, s->iobase + CODEC_CMI_DAC_FRAME2 + 2);
 575         if (s->status & DO_DUAL_DAC)
 576             set_countadc(s, count);
 577 }
 578
 579 static unsigned get_dmadac(struct cm_state *s)
 580 {
 581         unsigned int curr_addr;
 582
 583         curr_addr = inw(s->iobase + CODEC_CMI_DAC_FRAME2) + 1;
 584         curr_addr <<= sample_shift[(s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK];
 585         curr_addr = s->dma_dac.dmasize - curr_addr;
 586
 587         return curr_addr;
 588 }
 589
 590 static unsigned get_dmaadc(struct cm_state *s)
 591 {
 592         unsigned int curr_addr;
 593
 594         curr_addr = inw(s->iobase + CODEC_CMI_ADC_FRAME2) + 1;
 595         curr_addr <<= sample_shift[(s->fmt >> CM_CFMT_ADCSHIFT) & CM_CFMT_MASK];
 596         curr_addr = s->dma_adc.dmasize - curr_addr;
 597
 598         return curr_addr;
 599 }
 600
 601 static void wrmixer(struct cm_state *s, unsigned char idx, unsigned char data)
 602 {
 603         unsigned char regval, pseudo;
 604
 605         // pseudo register
 606         if (idx == DSP_MIX_AUXVOL_L) {
 607                 data >>= 4;
 608                 data &= 0x0f;
 609                 regval = inb(s->iobase + CODEC_CMI_AUX_VOL) & ~0x0f;
 610                 outb(regval | data, s->iobase + CODEC_CMI_AUX_VOL);
 611                 return;
 612         }
 613         if (idx == DSP_MIX_AUXVOL_R) {
 614                 data &= 0xf0;
 615                 regval = inb(s->iobase + CODEC_CMI_AUX_VOL) & ~0xf0;
 616                 outb(regval | data, s->iobase + CODEC_CMI_AUX_VOL);
 617                 return;
 618         }
 619         outb(idx, s->iobase + CODEC_SB16_ADDR);
 620         udelay(10);
 621         // pseudo bits
 622         if (idx == DSP_MIX_OUTMIXIDX) {
 623                 pseudo = data & ~0x1f;
 624                 pseudo >>= 1;
 625                 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x30;
 626                 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
 627         }
 628         if (idx == DSP_MIX_ADCMIXIDX_L) {
 629                 pseudo = data & 0x80;
 630                 pseudo >>= 1;
 631                 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x40;
 632                 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
 633         }
 634         if (idx == DSP_MIX_ADCMIXIDX_R) {
 635                 pseudo = data & 0x80;
 636                 regval = inb(s->iobase + CODEC_CMI_MIXER2) & ~0x80;
 637                 outb(regval | pseudo, s->iobase + CODEC_CMI_MIXER2);
 638         }
 639         outb(data, s->iobase + CODEC_SB16_DATA);
 640         udelay(10);
 641 }
 642
 643 static unsigned char rdmixer(struct cm_state *s, unsigned char idx)
 644 {
 645         unsigned char v, pseudo;
 646
 647         // pseudo register
 648         if (idx == DSP_MIX_AUXVOL_L) {
 649                 v = inb(s->iobase + CODEC_CMI_AUX_VOL) & 0x0f;
 650                 v <<= 4;
 651                 return v;
 652         }
 653         if (idx == DSP_MIX_AUXVOL_L) {
 654                 v = inb(s->iobase + CODEC_CMI_AUX_VOL) & 0xf0;
 655                 return v;
 656         }
 657         outb(idx, s->iobase + CODEC_SB16_ADDR);
 658         udelay(10);
 659         v = inb(s->iobase + CODEC_SB16_DATA);
 660         udelay(10);
 661         // pseudo bits
 662         if (idx == DSP_MIX_OUTMIXIDX) {
 663                 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x30;
 664                 pseudo <<= 1;
 665                 v |= pseudo;
 666         }
 667         if (idx == DSP_MIX_ADCMIXIDX_L) {
 668                 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x40;
 669                 pseudo <<= 1;
 670                 v |= pseudo;
 671         }
 672         if (idx == DSP_MIX_ADCMIXIDX_R) {
 673                 pseudo = inb(s->iobase + CODEC_CMI_MIXER2) & 0x80;
 674                 v |= pseudo;
 675         }
 676         return v;
 677 }
 678
 679 static void set_fmt_unlocked(struct cm_state *s, unsigned char mask, unsigned char data)
 680 {
 681         if (mask && s->chip_version > 0) {      /* 8338 cannot keep this */
 682                 s->fmt = inb(s->iobase + CODEC_CMI_CHFORMAT);
 683                 udelay(10);
 684         }
 685         s->fmt = (s->fmt & mask) | data;
 686         outb(s->fmt, s->iobase + CODEC_CMI_CHFORMAT);
 687         udelay(10);
 688 }
 689
 690 static void set_fmt(struct cm_state *s, unsigned char mask, unsigned char data)
 691 {
 692         unsigned long flags;
 693
 694         spin_lock_irqsave(&s->lock, flags);
 695         set_fmt_unlocked(s,mask,data);
 696         spin_unlock_irqrestore(&s->lock, flags);
 697 }
 698
 699 static void frobindir(struct cm_state *s, unsigned char idx, unsigned char mask, unsigned char data)
 700 {
 701         outb(idx, s->iobase + CODEC_SB16_ADDR);
 702         udelay(10);
 703         outb((inb(s->iobase + CODEC_SB16_DATA) & mask) | data, s->iobase + CODEC_SB16_DATA);
 704         udelay(10);
 705 }
 706
 707 static struct {
 708         unsigned        rate;
 709         unsigned        lower;
 710         unsigned        upper;
 711         unsigned char   freq;
 712 } rate_lookup[] =
 713 {
 714         { 5512,         (0 + 5512) / 2,         (5512 + 8000) / 2,      0 },
 715         { 8000,         (5512 + 8000) / 2,      (8000 + 11025) / 2,     4 },
 716         { 11025,        (8000 + 11025) / 2,     (11025 + 16000) / 2,    1 },
 717         { 16000,        (11025 + 16000) / 2,    (16000 + 22050) / 2,    5 },
 718         { 22050,        (16000 + 22050) / 2,    (22050 + 32000) / 2,    2 },
 719         { 32000,        (22050 + 32000) / 2,    (32000 + 44100) / 2,    6 },
 720         { 44100,        (32000 + 44100) / 2,    (44100 + 48000) / 2,    3 },
 721         { 48000,        (44100 + 48000) / 2,    48000,                  7 }
 722 };
 723
 724 static void set_spdif_copyright(struct cm_state *s, int spdif_copyright)
 725 {
 726         /* enable SPDIF-in Copyright */
 727         maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~SPDCOPYRHT, spdif_copyright ? SPDCOPYRHT : 0);
 728 }
 729
 730 static void set_spdif_loop(struct cm_state *s, int spdif_loop)
 731 {
 732         /* enable SPDIF loop */
 733         if (spdif_loop) {
 734                 s->status |= DO_SPDIF_LOOP;
 735                 /* turn on spdif-in to spdif-out */
 736                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, SPDFLOOP);
 737         } else {
 738                 s->status &= ~DO_SPDIF_LOOP;
 739                 /* turn off spdif-in to spdif-out */
 740                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~SPDFLOOP, 0);
 741         }
 742 }
 743
 744 static void set_spdif_monitor(struct cm_state *s, int channel)
 745 {
 746         // SPDO2DAC
 747         maskw(s->iobase + CODEC_CMI_FUNCTRL1, ~SPDO2DAC, channel == 2 ? SPDO2DAC : 0);
 748         // CDPLAY
 749         if (s->chip_version >= 39)
 750                 maskb(s->iobase + CODEC_CMI_MIXER1, ~CDPLAY, channel ? CDPLAY : 0);
 751 }
 752
 753 static void set_spdifout_level(struct cm_state *s, int level5v)
 754 {
 755         /* SPDO5V */
 756         if (s->chip_version > 0)
 757                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~SPDO5V, level5v ? SPDO5V : 0);
 758 }
 759
 760 static void set_spdifin_inverse(struct cm_state *s, int spdif_inverse)
 761 {
 762         if (s->chip_version == 0)       /* 8338 has not this feature */
 763                 return;
 764         if (spdif_inverse) {
 765                 /* turn on spdif-in inverse */
 766                 if (s->chip_version >= 39)
 767                         maskb(s->iobase + CODEC_CMI_CHFORMAT, ~0, INVSPDIFI);
 768                 else
 769                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 1);
 770         } else {
 771                 /* turn off spdif-ininverse */
 772                 if (s->chip_version >= 39)
 773                         maskb(s->iobase + CODEC_CMI_CHFORMAT, ~INVSPDIFI, 0);
 774                 else
 775                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~1, 0);
 776         }
 777 }
 778
 779 static void set_spdifin_channel2(struct cm_state *s, int channel2)
 780 {
 781         /* SELSPDIFI2 */
 782         if (s->chip_version >= 39)
 783                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 1, ~SELSPDIFI2, channel2 ? SELSPDIFI2 : 0);
 784 }
 785
 786 static void set_spdifin_valid(struct cm_state *s, int valid)
 787 {
 788         /* SPDVALID */
 789         maskb(s->iobase + CODEC_CMI_MISC, ~SPDVALID, valid ? SPDVALID : 0);
 790 }
 791
 792 static void set_spdifout_unlocked(struct cm_state *s, unsigned rate)
 793 {
 794         if (rate != 48000 && rate != 44100)
 795                 rate = 0;
 796         if (rate == 48000 || rate == 44100) {
 797                 set_spdif_loop(s, 0);
 798                 // SPDF_1
 799                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~0, SPDF_1);
 800                 // SPDIFI48K SPDF_AC97
 801                 maskl(s->iobase + CODEC_CMI_MISC_CTRL, ~SPDIF48K, rate == 48000 ? SPDIF48K : 0);
 802                 if (s->chip_version >= 55)
 803                 // SPD32KFMT
 804                         maskb(s->iobase + CODEC_CMI_MISC_CTRL2, ~SPD32KFMT, rate == 48000 ? SPD32KFMT : 0);
 805                 if (s->chip_version > 0)
 806                 // ENSPDOUT
 807                         maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~0, ENSPDOUT);
 808                 // monitor SPDIF out
 809                 set_spdif_monitor(s, 2);
 810                 s->status |= DO_SPDIF_OUT;
 811         } else {
 812                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~SPDF_1, 0);
 813                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 2, ~ENSPDOUT, 0);
 814                 // monitor none
 815                 set_spdif_monitor(s, 0);
 816                 s->status &= ~DO_SPDIF_OUT;
 817         }
 818 }
 819
 820 static void set_spdifout(struct cm_state *s, unsigned rate)
 821 {
 822         unsigned long flags;
 823
 824         spin_lock_irqsave(&s->lock, flags);
 825         set_spdifout_unlocked(s,rate);
 826         spin_unlock_irqrestore(&s->lock, flags);
 827 }
 828
 829 static void set_spdifin_unlocked(struct cm_state *s, unsigned rate)
 830 {
 831         if (rate == 48000 || rate == 44100) {
 832                 // SPDF_1
 833                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~0, SPDF_1);
 834                 // SPDIFI48K SPDF_AC97
 835                 maskl(s->iobase + CODEC_CMI_MISC_CTRL, ~SPDIF48K, rate == 48000 ? SPDIF48K : 0);
 836                 s->status |= DO_SPDIF_IN;
 837         } else {
 838                 maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~SPDF_1, 0);
 839                 s->status &= ~DO_SPDIF_IN;
 840         }
 841 }
 842
 843 static void set_spdifin(struct cm_state *s, unsigned rate)
 844 {
 845         unsigned long flags;
 846
 847         spin_lock_irqsave(&s->lock, flags);
 848         set_spdifin_unlocked(s,rate);
 849         spin_unlock_irqrestore(&s->lock, flags);
 850 }
 851
 852 /* find parity for bit 4~30 */
 853 static unsigned parity(unsigned data)
 854 {
 855         unsigned parity = 0;
 856         int counter = 4;
 857
 858         data >>= 4;     // start from bit 4
 859         while (counter <= 30) {
 860                 if (data & 1)
 861                         parity++;
 862                 data >>= 1;
 863                 counter++;
 864         }
 865         return parity & 1;
 866 }
 867
 868 static void set_ac3_unlocked(struct cm_state *s, unsigned rate)
 869 {
 870         if (!(s->capability & CAN_AC3))
 871                 return;
 872         /* enable AC3 */
 873         if (rate && rate != 44100)
 874                 rate = 48000;
 875         if (rate == 48000 || rate == 44100) {
 876                 // mute DAC
 877                 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, WSMUTE);
 878                 if (s->chip_version >= 39)
 879                         maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~0, MUTECH1);
 880                 // AC3EN for 039, 0x04
 881                 if (s->chip_version >= 39) {
 882                         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, AC3_EN);
 883                         if (s->chip_version == 55)
 884                                 maskb(s->iobase + CODEC_CMI_SPDIF_CTRL, ~2, 0);
 885                 // AC3EN for 037, 0x10
 886                 } else if (s->chip_version == 37)
 887                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 0x10);
 888                 if (s->capability & CAN_AC3_HW) {
 889                         // SPD24SEL for 039, 0x20, but cannot be set
 890                         if (s->chip_version == 39)
 891                                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, SPD24SEL);
 892                         // SPD24SEL for 037, 0x02
 893                         else if (s->chip_version == 37)
 894                                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~0, 0x02);
 895                         if (s->chip_version >= 39)
 896                                 maskb(s->iobase + CODEC_CMI_MIXER1, ~CDPLAY, 0);
 897
 898                         s->status |= DO_AC3_HW;
 899                  } else {
 900                         // SPD32SEL for 037 & 039
 901                         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, SPD32SEL);
 902                         // set 176K sample rate to fix 033 HW bug
 903                         if (s->chip_version == 33) {
 904                                 if (rate == 48000)
 905                                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0, 0x08);
 906                                 else
 907                                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0x08, 0);
 908                         }
 909                         s->status |= DO_AC3_SW;
 910                 }
 911         } else {
 912                 maskb(s->iobase + CODEC_CMI_MIXER1, ~WSMUTE, 0);
 913                 if (s->chip_version >= 39)
 914                         maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~MUTECH1, 0);
 915                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 2, ~(SPD24SEL|0x12), 0);
 916                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~(SPD32SEL|AC3_EN), 0);
 917                 if (s->chip_version == 33)
 918                         maskb(s->iobase + CODEC_CMI_CHFORMAT + 1, ~0x08, 0);
 919                 if (s->chip_version >= 39)
 920                         maskb(s->iobase + CODEC_CMI_MIXER1, ~0, CDPLAY);
 921                 s->status &= ~DO_AC3;
 922         }
 923         s->spdif_counter = 0;
 924 }
 925
 926 static void set_line_as_rear(struct cm_state *s, int use_line_as_rear)
 927 {
 928         if (!(s->capability & CAN_LINE_AS_REAR))
 929                 return;
 930         if (use_line_as_rear) {
 931                 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, SPK4);
 932                 s->status |= DO_LINE_AS_REAR;
 933         } else {
 934                 maskb(s->iobase + CODEC_CMI_MIXER1, ~SPK4, 0);
 935                 s->status &= ~DO_LINE_AS_REAR;
 936         }
 937 }
 938
 939 static void set_line_as_bass(struct cm_state *s, int use_line_as_bass)
 940 {
 941         if (!(s->capability & CAN_LINE_AS_BASS))
 942                 return;
 943         if (use_line_as_bass) {
 944                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~0, CB2LIN);
 945                 s->status |= DO_LINE_AS_BASS;
 946         } else {
 947                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CB2LIN, 0);
 948                 s->status &= ~DO_LINE_AS_BASS;
 949         }
 950 }
 951
 952 static void set_mic_as_bass(struct cm_state *s, int use_mic_as_bass)
 953 {
 954         if (!(s->capability & CAN_MIC_AS_BASS))
 955                 return;
 956         if (use_mic_as_bass) {
 957                 maskb(s->iobase + CODEC_CMI_MISC, ~0, 0x04);
 958                 s->status |= DO_MIC_AS_BASS;
 959         } else {
 960                 maskb(s->iobase + CODEC_CMI_MISC, ~0x04, 0);
 961                 s->status &= ~DO_MIC_AS_BASS;
 962         }
 963 }
 964
 965 static void set_hw_copy(struct cm_state *s, int hw_copy)
 966 {
 967         if (s->max_channels > 2 && hw_copy)
 968                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~0, N4SPK3D);
 969         else
 970                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 3, ~N4SPK3D, 0);
 971 }
 972
 973 static void set_ac3(struct cm_state *s, unsigned rate)
 974 {
 975         unsigned long flags;
 976
 977         spin_lock_irqsave(&s->lock, flags);
 978         set_spdifout_unlocked(s, rate);
 979         set_ac3_unlocked(s, rate);
 980         spin_unlock_irqrestore(&s->lock, flags);
 981 }
 982
 983 static int trans_ac3(struct cm_state *s, void *dest, const char __user *source, int size)
 984 {
 985         int   i = size / 2;
 986         unsigned long data;
 987         unsigned short data16;
 988         unsigned long *dst = (unsigned long *) dest;
 989         unsigned short __user *src = (unsigned short __user *)source;
 990         int err;
 991
 992         do {
 993                 if ((err = __get_user(data16, src++)))
 994                         return err;
 995                 data = (unsigned long)le16_to_cpu(data16);
 996                 data <<= 12;                    // ok for 16-bit data
 997                 if (s->spdif_counter == 2 || s->spdif_counter == 3)
 998                         data |= 0x40000000;     // indicate AC-3 raw data
 999                 if (parity(data))
1000                         data |= 0x80000000;     // parity
1001                 if (s->spdif_counter == 0)
1002                         data |= 3;              // preamble 'M'
1003                 else if (s->spdif_counter & 1)
1004                         data |= 5;              // odd, 'W'
1005                 else
1006                         data |= 9;              // even, 'M'
1007                 *dst++ = cpu_to_le32(data);
1008                 s->spdif_counter++;
1009                 if (s->spdif_counter == 384)
1010                         s->spdif_counter = 0;
1011         } while (--i);
1012
1013         return 0;
1014 }
1015
1016 static void set_adc_rate_unlocked(struct cm_state *s, unsigned rate)
1017 {
1018         unsigned char freq = 4;
1019         int     i;
1020
1021         if (rate > 48000)
1022                 rate = 48000;
1023         if (rate < 8000)
1024                 rate = 8000;
1025         for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1026                 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1027                         rate = rate_lookup[i].rate;
1028                         freq = rate_lookup[i].freq;
1029                         break;
1030                 }
1031         }
1032         s->rateadc = rate;
1033         freq <<= CM_FREQ_ADCSHIFT;
1034
1035         maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~ASFC, freq);
1036 }
1037
1038 static void set_adc_rate(struct cm_state *s, unsigned rate)
1039 {
1040         unsigned long flags;
1041         unsigned char freq = 4;
1042         int     i;
1043
1044         if (rate > 48000)
1045                 rate = 48000;
1046         if (rate < 8000)
1047                 rate = 8000;
1048         for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1049                 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1050                         rate = rate_lookup[i].rate;
1051                         freq = rate_lookup[i].freq;
1052                         break;
1053                 }
1054         }
1055         s->rateadc = rate;
1056         freq <<= CM_FREQ_ADCSHIFT;
1057
1058         spin_lock_irqsave(&s->lock, flags);
1059         maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~ASFC, freq);
1060         spin_unlock_irqrestore(&s->lock, flags);
1061 }
1062
1063 static void set_dac_rate(struct cm_state *s, unsigned rate)
1064 {
1065         unsigned long flags;
1066         unsigned char freq = 4;
1067         int     i;
1068
1069         if (rate > 48000)
1070                 rate = 48000;
1071         if (rate < 8000)
1072                 rate = 8000;
1073         for (i = 0; i < sizeof(rate_lookup) / sizeof(rate_lookup[0]); i++) {
1074                 if (rate > rate_lookup[i].lower && rate <= rate_lookup[i].upper) {
1075                         rate = rate_lookup[i].rate;
1076                         freq = rate_lookup[i].freq;
1077                         break;
1078                 }
1079         }
1080         s->ratedac = rate;
1081         freq <<= CM_FREQ_DACSHIFT;
1082
1083         spin_lock_irqsave(&s->lock, flags);
1084         maskb(s->iobase + CODEC_CMI_FUNCTRL1 + 1, ~DSFC, freq);
1085         spin_unlock_irqrestore(&s->lock, flags);
1086
1087         if (s->curr_channels <= 2 && spdif_out)
1088                 set_spdifout(s, rate);
1089         if (s->status & DO_DUAL_DAC)
1090                 set_dac1_rate(s, rate);
1091 }
1092
1093 /* --------------------------------------------------------------------- */
1094 static inline void reset_adc(struct cm_state *s)
1095 {
1096         /* reset bus master */
1097         outb(s->enable | RSTADC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1098         udelay(10);
1099         outb(s->enable & ~RSTADC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1100 }
1101
1102 static inline void reset_dac(struct cm_state *s)
1103 {
1104         /* reset bus master */
1105         outb(s->enable | RSTDAC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1106         udelay(10);
1107         outb(s->enable & ~RSTDAC, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1108         if (s->status & DO_DUAL_DAC)
1109                 reset_adc(s);
1110 }
1111
1112 static inline void pause_adc(struct cm_state *s)
1113 {
1114         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, PAUSEADC);
1115 }
1116
1117 static inline void pause_dac(struct cm_state *s)
1118 {
1119         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~0, PAUSEDAC);
1120         if (s->status & DO_DUAL_DAC)
1121                 pause_adc(s);
1122 }
1123
1124 static inline void disable_adc(struct cm_state *s)
1125 {
1126         /* disable channel */
1127         s->enable &= ~ENADC;
1128         outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1129         reset_adc(s);
1130 }
1131
1132 static inline void disable_dac(struct cm_state *s)
1133 {
1134         /* disable channel */
1135         s->enable &= ~ENDAC;
1136         outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1137         reset_dac(s);
1138         if (s->status & DO_DUAL_DAC)
1139                 disable_adc(s);
1140 }
1141
1142 static inline void enable_adc(struct cm_state *s)
1143 {
1144         if (!(s->enable & ENADC)) {
1145                 /* enable channel */
1146                 s->enable |= ENADC;
1147                 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1148         }
1149         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~PAUSEADC, 0);
1150 }
1151
1152 static inline void enable_dac_unlocked(struct cm_state *s)
1153 {
1154         if (!(s->enable & ENDAC)) {
1155                 /* enable channel */
1156                 s->enable |= ENDAC;
1157                 outb(s->enable, s->iobase + CODEC_CMI_FUNCTRL0 + 2);
1158         }
1159         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~PAUSEDAC, 0);
1160
1161         if (s->status & DO_DUAL_DAC)
1162                 enable_adc(s);
1163 }
1164
1165 static inline void enable_dac(struct cm_state *s)
1166 {
1167         unsigned long flags;
1168
1169         spin_lock_irqsave(&s->lock, flags);
1170         enable_dac_unlocked(s);
1171         spin_unlock_irqrestore(&s->lock, flags);
1172 }
1173
1174 static inline void stop_adc_unlocked(struct cm_state *s)
1175 {
1176         if (s->enable & ENADC) {
1177                 /* disable interrupt */
1178                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~ENADCINT, 0);
1179                 disable_adc(s);
1180         }
1181 }
1182
1183 static inline void stop_adc(struct cm_state *s)
1184 {
1185         unsigned long flags;
1186
1187         spin_lock_irqsave(&s->lock, flags);
1188         stop_adc_unlocked(s);
1189         spin_unlock_irqrestore(&s->lock, flags);
1190
1191 }
1192
1193 static inline void stop_dac_unlocked(struct cm_state *s)
1194 {
1195         if (s->enable & ENDAC) {
1196                 /* disable interrupt */
1197                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~ENDACINT, 0);
1198                 disable_dac(s);
1199         }
1200         if (s->status & DO_DUAL_DAC)
1201                 stop_dac1_unlocked(s);
1202 }
1203
1204 static inline void stop_dac(struct cm_state *s)
1205 {
1206         unsigned long flags;
1207
1208         spin_lock_irqsave(&s->lock, flags);
1209         stop_dac_unlocked(s);
1210         spin_unlock_irqrestore(&s->lock, flags);
1211 }
1212
1213 static inline void start_adc_unlocked(struct cm_state *s)
1214 {
1215         if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
1216             && s->dma_adc.ready) {
1217                 /* enable interrupt */
1218                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENADCINT);
1219                 enable_adc(s);
1220         }
1221 }
1222
1223 static void start_adc(struct cm_state *s)
1224 {
1225         unsigned long flags;
1226
1227         spin_lock_irqsave(&s->lock, flags);
1228         start_adc_unlocked(s);
1229         spin_unlock_irqrestore(&s->lock, flags);
1230 }
1231
1232 static void start_dac1_unlocked(struct cm_state *s)
1233 {
1234         if ((s->dma_adc.mapped || s->dma_adc.count > 0) && s->dma_adc.ready) {
1235                 /* enable interrupt */
1236                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENADCINT);
1237                 enable_dac_unlocked(s);
1238         }
1239 }
1240
1241 static void start_dac_unlocked(struct cm_state *s)
1242 {
1243         if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
1244                 /* enable interrupt */
1245                 maskb(s->iobase + CODEC_CMI_INT_HLDCLR + 2, ~0, ENDACINT);
1246                 enable_dac_unlocked(s);
1247         }
1248         if (s->status & DO_DUAL_DAC)
1249                 start_dac1_unlocked(s);
1250 }
1251
1252 static void start_dac(struct cm_state *s)
1253 {
1254         unsigned long flags;
1255
1256         spin_lock_irqsave(&s->lock, flags);
1257         start_dac_unlocked(s);
1258         spin_unlock_irqrestore(&s->lock, flags);
1259 }
1260
1261 static int prog_dmabuf(struct cm_state *s, unsigned rec);
1262
1263 static int set_dac_channels(struct cm_state *s, int channels)
1264 {
1265         unsigned long flags;
1266         static unsigned int fmmute = 0;
1267
1268         spin_lock_irqsave(&s->lock, flags);
1269
1270         if ((channels > 2) && (channels <= s->max_channels)
1271          && (((s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK) == (CM_CFMT_STEREO | CM_CFMT_16BIT))) {
1272             set_spdifout_unlocked(s, 0);
1273             if (s->capability & CAN_MULTI_CH_HW) {
1274                 // NXCHG
1275                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0, NXCHG);
1276                 // CHB3D or CHB3D5C
1277                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 3, ~(CHB3D5C|CHB3D), channels > 4 ? CHB3D5C : CHB3D);
1278                 // CHB3D6C
1279                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CHB3D6C, channels == 6 ? CHB3D6C : 0);
1280                 // ENCENTER
1281                 maskb(s->iobase + CODEC_CMI_MISC_CTRL, ~ENCENTER, channels == 6 ? ENCENTER : 0);
1282                 s->status |= DO_MULTI_CH_HW;
1283             } else if (s->capability & CAN_DUAL_DAC) {
1284                 unsigned char fmtm = ~0, fmts = 0;
1285                 ssize_t ret;
1286
1287                 // ENDBDAC, turn on double DAC mode
1288                 // XCHGDAC, CH0 -> back, CH1->front
1289                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, ENDBDAC|XCHGDAC);
1290                 // mute FM
1291                 fmmute = inb(s->iobase + CODEC_CMI_MIXER1) & FMMUTE;
1292                 maskb(s->iobase + CODEC_CMI_MIXER1, ~0, FMMUTE);
1293                 s->status |= DO_DUAL_DAC;
1294                 // prepare secondary buffer
1295                 spin_unlock_irqrestore(&s->lock, flags);
1296                 ret = prog_dmabuf(s, 1);
1297                 if (ret) return ret;
1298                 spin_lock_irqsave(&s->lock, flags);
1299
1300                 // copy the hw state
1301                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_DACSHIFT);
1302                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_ADCSHIFT);
1303                 // the HW only support 16-bit stereo
1304                 fmts |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
1305                 fmts |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
1306                 fmts |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
1307                 fmts |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
1308
1309                 set_fmt_unlocked(s, fmtm, fmts);
1310                 set_adc_rate_unlocked(s, s->ratedac);
1311             }
1312             // disable 4 speaker mode (analog duplicate)
1313             set_hw_copy(s, 0);
1314             s->curr_channels = channels;
1315
1316             // enable jack redirect
1317             set_line_as_rear(s, use_line_as_rear);
1318             if (channels > 4) {
1319                     set_line_as_bass(s, use_line_as_bass);
1320                     set_mic_as_bass(s, use_mic_as_bass);
1321             }
1322         } else {
1323             if (s->status & DO_MULTI_CH_HW) {
1324                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~NXCHG, 0);
1325                 maskb(s->iobase + CODEC_CMI_CHFORMAT + 3, ~(CHB3D5C|CHB3D), 0);
1326                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 1, ~CHB3D6C, 0);
1327             } else if (s->status & DO_DUAL_DAC) {
1328                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~ENDBDAC, 0);
1329                 maskb(s->iobase + CODEC_CMI_MIXER1, ~FMMUTE, fmmute);
1330             }
1331             // enable 4 speaker mode (analog duplicate)
1332             set_hw_copy(s, hw_copy);
1333             s->status &= ~DO_MULTI_CH;
1334             s->curr_channels = s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1;
1335             // disable jack redirect
1336             set_line_as_rear(s, hw_copy ? use_line_as_rear : 0);
1337             set_line_as_bass(s, 0);
1338             set_mic_as_bass(s, 0);
1339         }
1340         spin_unlock_irqrestore(&s->lock, flags);
1341         return s->curr_channels;
1342 }
1343
1344 /* --------------------------------------------------------------------- */
1345
1346 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
1347 #define DMABUF_MINORDER 1
1348
1349 static void dealloc_dmabuf(struct cm_state *s, struct dmabuf *db)
1350 {
1351         struct page *pstart, *pend;
1352
1353         if (db->rawbuf) {
1354                 /* undo marking the pages as reserved */
1355                 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1356                 for (pstart = virt_to_page(db->rawbuf); pstart <= pend; pstart++)
1357                         ClearPageReserved(pstart);
1358                 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
1359         }
1360         db->rawbuf = NULL;
1361         db->mapped = db->ready = 0;
1362 }
1363
1364 /* Ch1 is used for playback, Ch0 is used for recording */
1365
1366 static int prog_dmabuf(struct cm_state *s, unsigned rec)
1367 {
1368         struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1369         unsigned rate = rec ? s->rateadc : s->ratedac;
1370         int order;
1371         unsigned bytepersec;
1372         unsigned bufs;
1373         struct page *pstart, *pend;
1374         unsigned char fmt;
1375         unsigned long flags;
1376
1377         fmt = s->fmt;
1378         if (rec) {
1379                 stop_adc(s);
1380                 fmt >>= CM_CFMT_ADCSHIFT;
1381         } else {
1382                 stop_dac(s);
1383                 fmt >>= CM_CFMT_DACSHIFT;
1384         }
1385
1386         fmt &= CM_CFMT_MASK;
1387         db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1388         if (!db->rawbuf) {
1389                 db->ready = db->mapped = 0;
1390                 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
1391                         if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
1392                                 break;
1393                 if (!db->rawbuf || !db->dmaaddr)
1394                         return -ENOMEM;
1395                 db->buforder = order;
1396                 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
1397                 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1398                 for (pstart = virt_to_page(db->rawbuf); pstart <= pend; pstart++)
1399                         SetPageReserved(pstart);
1400         }
1401         bytepersec = rate << sample_shift[fmt];
1402         bufs = PAGE_SIZE << db->buforder;
1403         if (db->ossfragshift) {
1404                 if ((1000 << db->ossfragshift) < bytepersec)
1405                         db->fragshift = ld2(bytepersec/1000);
1406                 else
1407                         db->fragshift = db->ossfragshift;
1408         } else {
1409                 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1410                 if (db->fragshift < 3)
1411                         db->fragshift = 3;
1412         }
1413         db->numfrag = bufs >> db->fragshift;
1414         while (db->numfrag < 4 && db->fragshift > 3) {
1415                 db->fragshift--;
1416                 db->numfrag = bufs >> db->fragshift;
1417         }
1418         db->fragsize = 1 << db->fragshift;
1419         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1420                 db->numfrag = db->ossmaxfrags;
1421         /* to make fragsize >= 4096 */
1422         db->fragsamples = db->fragsize >> sample_shift[fmt];
1423         db->dmasize = db->numfrag << db->fragshift;
1424         db->dmasamples = db->dmasize >> sample_shift[fmt];
1425         memset(db->rawbuf, (fmt & CM_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
1426         spin_lock_irqsave(&s->lock, flags);
1427         if (rec) {
1428                 if (s->status & DO_DUAL_DAC)
1429                     set_dmadac1(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1430                 else
1431                     set_dmaadc(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1432                 /* program sample counts */
1433                 set_countdac(s, db->fragsamples);
1434         } else {
1435                 set_dmadac(s, db->dmaaddr, db->dmasize >> sample_shift[fmt]);
1436                 /* program sample counts */
1437                 set_countdac(s, db->fragsamples);
1438         }
1439         spin_unlock_irqrestore(&s->lock, flags);
1440         db->enabled = 1;
1441         db->ready = 1;
1442         return 0;
1443 }
1444
1445 static inline void clear_advance(struct cm_state *s)
1446 {
1447         unsigned char c = (s->fmt & (CM_CFMT_16BIT << CM_CFMT_DACSHIFT)) ? 0 : 0x80;
1448         unsigned char *buf = s->dma_dac.rawbuf;
1449         unsigned char *buf1 = s->dma_adc.rawbuf;
1450         unsigned bsize = s->dma_dac.dmasize;
1451         unsigned bptr = s->dma_dac.swptr;
1452         unsigned len = s->dma_dac.fragsize;
1453
1454         if (bptr + len > bsize) {
1455                 unsigned x = bsize - bptr;
1456                 memset(buf + bptr, c, x);
1457                 if (s->status & DO_DUAL_DAC)
1458                         memset(buf1 + bptr, c, x);
1459                 bptr = 0;
1460                 len -= x;
1461         }
1462         memset(buf + bptr, c, len);
1463         if (s->status & DO_DUAL_DAC)
1464                 memset(buf1 + bptr, c, len);
1465 }
1466
1467 /* call with spinlock held! */
1468 static void cm_update_ptr(struct cm_state *s)
1469 {
1470         unsigned hwptr;
1471         int diff;
1472
1473         /* update ADC pointer */
1474         if (s->dma_adc.ready) {
1475             if (s->status & DO_DUAL_DAC) {
1476                     /* the dac part will finish for this */
1477             } else {
1478                 hwptr = get_dmaadc(s) % s->dma_adc.dmasize;
1479                 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1480                 s->dma_adc.hwptr = hwptr;
1481                 s->dma_adc.total_bytes += diff;
1482                 s->dma_adc.count += diff;
1483                 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1484                         wake_up(&s->dma_adc.wait);
1485                 if (!s->dma_adc.mapped) {
1486                         if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1487                                 pause_adc(s);
1488                                 s->dma_adc.error++;
1489                         }
1490                 }
1491             }
1492         }
1493         /* update DAC pointer */
1494         if (s->dma_dac.ready) {
1495                 hwptr = get_dmadac(s) % s->dma_dac.dmasize;
1496                 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1497                 s->dma_dac.hwptr = hwptr;
1498                 s->dma_dac.total_bytes += diff;
1499                 if (s->status & DO_DUAL_DAC) {
1500                         s->dma_adc.hwptr = hwptr;
1501                         s->dma_adc.total_bytes += diff;
1502                 }
1503                 if (s->dma_dac.mapped) {
1504                         s->dma_dac.count += diff;
1505                         if (s->status & DO_DUAL_DAC)
1506                                 s->dma_adc.count += diff;
1507                         if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1508                                 wake_up(&s->dma_dac.wait);
1509                 } else {
1510                         s->dma_dac.count -= diff;
1511                         if (s->status & DO_DUAL_DAC)
1512                                 s->dma_adc.count -= diff;
1513                         if (s->dma_dac.count <= 0) {
1514                                 pause_dac(s);
1515                                 s->dma_dac.error++;
1516                         } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1517                                 clear_advance(s);
1518                                 s->dma_dac.endcleared = 1;
1519                                 if (s->status & DO_DUAL_DAC)
1520                                         s->dma_adc.endcleared = 1;
1521                         }
1522                         if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
1523                                 wake_up(&s->dma_dac.wait);
1524                 }
1525         }
1526 }
1527
1528 static irqreturn_t cm_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1529 {
1530         struct cm_state *s = (struct cm_state *)dev_id;
1531         unsigned int intsrc, intstat;
1532         unsigned char mask = 0;
1533
1534         /* fastpath out, to ease interrupt sharing */
1535         intsrc = inl(s->iobase + CODEC_CMI_INT_STATUS);
1536         if (!(intsrc & 0x80000000))
1537                 return IRQ_NONE;
1538         spin_lock(&s->lock);
1539         intstat = inb(s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1540         /* acknowledge interrupt */
1541         if (intsrc & ADCINT)
1542                 mask |= ENADCINT;
1543         if (intsrc & DACINT)
1544                 mask |= ENDACINT;
1545         outb(intstat & ~mask, s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1546         outb(intstat | mask, s->iobase + CODEC_CMI_INT_HLDCLR + 2);
1547         cm_update_ptr(s);
1548         spin_unlock(&s->lock);
1549 #ifdef CONFIG_SOUND_CMPCI_MIDI
1550         if (intsrc & 0x00010000) {      // UART interrupt
1551                 if (s->midi_devc && intchk_mpu401((void *)s->midi_devc))
1552                         mpuintr(irq, (void *)s->midi_devc, regs);
1553                 else
1554                         inb(s->iomidi);// dummy read
1555         }
1556 #endif
1557         return IRQ_HANDLED;
1558 }
1559
1560 /* --------------------------------------------------------------------- */
1561
1562 static const char invalid_magic[] = KERN_CRIT "cmpci: invalid magic value\n";
1563
1564 #define VALIDATE_STATE(s)                         \
1565 ({                                                \
1566         if (!(s) || (s)->magic != CM_MAGIC) { \
1567                 printk(invalid_magic);            \
1568                 return -ENXIO;                    \
1569         }                                         \
1570 })
1571
1572 /* --------------------------------------------------------------------- */
1573
1574 #define MT_4          1
1575 #define MT_5MUTE      2
1576 #define MT_4MUTEMONO  3
1577 #define MT_6MUTE      4
1578 #define MT_5MUTEMONO  5
1579
1580 static const struct {
1581         unsigned left;
1582         unsigned right;
1583         unsigned type;
1584         unsigned rec;
1585         unsigned play;
1586 } mixtable[SOUND_MIXER_NRDEVICES] = {
1587         [SOUND_MIXER_CD]     = { DSP_MIX_CDVOLIDX_L,     DSP_MIX_CDVOLIDX_R,     MT_5MUTE,     0x04, 0x06 },
1588         [SOUND_MIXER_LINE]   = { DSP_MIX_LINEVOLIDX_L,   DSP_MIX_LINEVOLIDX_R,   MT_5MUTE,     0x10, 0x18 },
1589         [SOUND_MIXER_MIC]    = { DSP_MIX_MICVOLIDX,      DSP_MIX_MICVOLIDX,      MT_5MUTEMONO, 0x01, 0x01 },
1590         [SOUND_MIXER_SYNTH]  = { DSP_MIX_FMVOLIDX_L,     DSP_MIX_FMVOLIDX_R,     MT_5MUTE,     0x40, 0x00 },
1591         [SOUND_MIXER_VOLUME] = { DSP_MIX_MASTERVOLIDX_L, DSP_MIX_MASTERVOLIDX_R, MT_5MUTE,     0x00, 0x00 },
1592         [SOUND_MIXER_PCM]    = { DSP_MIX_VOICEVOLIDX_L,  DSP_MIX_VOICEVOLIDX_R,  MT_5MUTE,     0x00, 0x00 },
1593         [SOUND_MIXER_LINE1]  = { DSP_MIX_AUXVOL_L,       DSP_MIX_AUXVOL_R,       MT_5MUTE,     0x80, 0x60 },
1594         [SOUND_MIXER_SPEAKER]= { DSP_MIX_SPKRVOLIDX,     DSP_MIX_SPKRVOLIDX,     MT_5MUTEMONO, 0x00, 0x01 }
1595 };
1596
1597 static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
1598 {
1599         [SOUND_MIXER_CD]     = 1,
1600         [SOUND_MIXER_LINE]   = 2,
1601         [SOUND_MIXER_MIC]    = 3,
1602         [SOUND_MIXER_SYNTH]  = 4,
1603         [SOUND_MIXER_VOLUME] = 5,
1604         [SOUND_MIXER_PCM]    = 6,
1605         [SOUND_MIXER_LINE1]  = 7,
1606         [SOUND_MIXER_SPEAKER]= 8
1607 };
1608
1609 static unsigned mixer_outmask(struct cm_state *s)
1610 {
1611         unsigned long flags;
1612         int i, j, k;
1613
1614         spin_lock_irqsave(&s->lock, flags);
1615         j = rdmixer(s, DSP_MIX_OUTMIXIDX);
1616         spin_unlock_irqrestore(&s->lock, flags);
1617         for (k = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1618                 if (j & mixtable[i].play)
1619                         k |= 1 << i;
1620         return k;
1621 }
1622
1623 static unsigned mixer_recmask(struct cm_state *s)
1624 {
1625         unsigned long flags;
1626         int i, j, k;
1627
1628         spin_lock_irqsave(&s->lock, flags);
1629         j = rdmixer(s, DSP_MIX_ADCMIXIDX_L);
1630         spin_unlock_irqrestore(&s->lock, flags);
1631         for (k = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1632                 if (j & mixtable[i].rec)
1633                         k |= 1 << i;
1634         return k;
1635 }
1636
1637 static int mixer_ioctl(struct cm_state *s, unsigned int cmd, unsigned long arg)
1638 {
1639         unsigned long flags;
1640         int i, val, j;
1641         unsigned char l, r, rl, rr;
1642         void __user *argp = (void __user *)arg;
1643         int __user *p = argp;
1644
1645         VALIDATE_STATE(s);
1646         if (cmd == SOUND_MIXER_INFO) {
1647                 mixer_info info;
1648                 memset(&info, 0, sizeof(info));
1649                 strlcpy(info.id, "cmpci", sizeof(info.id));
1650                 strlcpy(info.name, "C-Media PCI", sizeof(info.name));
1651                 info.modify_counter = s->mix.modcnt;
1652                 if (copy_to_user(argp, &info, sizeof(info)))
1653                         return -EFAULT;
1654                 return 0;
1655         }
1656         if (cmd == SOUND_OLD_MIXER_INFO) {
1657                 _old_mixer_info info;
1658                 memset(&info, 0, sizeof(info));
1659                 strlcpy(info.id, "cmpci", sizeof(info.id));
1660                 strlcpy(info.name, "C-Media cmpci", sizeof(info.name));
1661                 if (copy_to_user(argp, &info, sizeof(info)))
1662                         return -EFAULT;
1663                 return 0;
1664         }
1665         if (cmd == OSS_GETVERSION)
1666                 return put_user(SOUND_VERSION, p);
1667         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1668                 return -EINVAL;
1669         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1670                 switch (_IOC_NR(cmd)) {
1671                 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1672                         val = mixer_recmask(s);
1673                         return put_user(val, p);
1674
1675                 case SOUND_MIXER_OUTSRC: /* Arg contains a bit for each recording source */
1676                         val = mixer_outmask(s);
1677                         return put_user(val, p);
1678
1679                 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
1680                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1681                                 if (mixtable[i].type)
1682                                         val |= 1 << i;
1683                         return put_user(val, p);
1684
1685                 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1686                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1687                                 if (mixtable[i].rec)
1688                                         val |= 1 << i;
1689                         return put_user(val, p);
1690
1691                 case SOUND_MIXER_OUTMASK: /* Arg contains a bit for each supported recording source */
1692                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1693                                 if (mixtable[i].play)
1694                                         val |= 1 << i;
1695                         return put_user(val, p);
1696
1697                  case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1698                         for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1699                                 if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
1700                                         val |= 1 << i;
1701                         return put_user(val, p);
1702
1703                 case SOUND_MIXER_CAPS:
1704                         return put_user(0, p);
1705
1706                 default:
1707                         i = _IOC_NR(cmd);
1708                         if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1709                                 return -EINVAL;
1710                         if (!volidx[i])
1711                                 return -EINVAL;
1712                         return put_user(s->mix.vol[volidx[i]-1], p);
1713                 }
1714         }
1715         if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
1716                 return -EINVAL;
1717         s->mix.modcnt++;
1718         switch (_IOC_NR(cmd)) {
1719         case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1720                 if (get_user(val, p))
1721                         return -EFAULT;
1722                 i = generic_hweight32(val);
1723                 for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1724                         if (!(val & (1 << i)))
1725                                 continue;
1726                         if (!mixtable[i].rec) {
1727                                 val &= ~(1 << i);
1728                                 continue;
1729                         }
1730                         j |= mixtable[i].rec;
1731                 }
1732                 spin_lock_irqsave(&s->lock, flags);
1733                 wrmixer(s, DSP_MIX_ADCMIXIDX_L, j);
1734                 wrmixer(s, DSP_MIX_ADCMIXIDX_R, (j & 1) | (j>>1) | (j & 0x80));
1735                 spin_unlock_irqrestore(&s->lock, flags);
1736                 return 0;
1737
1738         case SOUND_MIXER_OUTSRC: /* Arg contains a bit for each recording source */
1739                 if (get_user(val, p))
1740                         return -EFAULT;
1741                 for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1742                         if (!(val & (1 << i)))
1743                                 continue;
1744                         if (!mixtable[i].play) {
1745                                 val &= ~(1 << i);
1746                                 continue;
1747                         }
1748                         j |= mixtable[i].play;
1749                 }
1750                 spin_lock_irqsave(&s->lock, flags);
1751                 wrmixer(s, DSP_MIX_OUTMIXIDX, j);
1752                 spin_unlock_irqrestore(&s->lock, flags);
1753                 return 0;
1754
1755         default:
1756                 i = _IOC_NR(cmd);
1757                 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1758                         return -EINVAL;
1759                 if (get_user(val, p))
1760                         return -EFAULT;
1761                 l = val & 0xff;
1762                 r = (val >> 8) & 0xff;
1763                 if (l > 100)
1764                         l = 100;
1765                 if (r > 100)
1766                         r = 100;
1767                 spin_lock_irqsave(&s->lock, flags);
1768                 switch (mixtable[i].type) {
1769                 case MT_4:
1770                         if (l >= 10)
1771                                 l -= 10;
1772                         if (r >= 10)
1773                                 r -= 10;
1774                         frobindir(s, mixtable[i].left, 0xf0, l / 6);
1775                         frobindir(s, mixtable[i].right, 0xf0, l / 6);
1776                         break;
1777
1778                 case MT_4MUTEMONO:
1779                         rl = (l < 4 ? 0 : (l - 5) / 3) & 31;
1780                         rr = (rl >> 2) & 7;
1781                         wrmixer(s, mixtable[i].left, rl<<3);
1782                         if (i == SOUND_MIXER_MIC)
1783                                 maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, rr<<1);
1784                         break;
1785
1786                 case MT_5MUTEMONO:
1787                         rl = l < 4 ? 0 : (l - 5) / 3;
1788                         wrmixer(s, mixtable[i].left, rl<<3);
1789                         l = rdmixer(s, DSP_MIX_OUTMIXIDX) & ~mixtable[i].play;
1790                         r = rl ? mixtable[i].play : 0;
1791                         wrmixer(s, DSP_MIX_OUTMIXIDX, l | r);
1792                         /* for recording */
1793                         if (i == SOUND_MIXER_MIC) {
1794                                 if (s->chip_version >= 37) {
1795                                         rr = rl >> 1;
1796                                         maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, (rr&0x07)<<1);
1797                                         frobindir(s, DSP_MIX_EXTENSION, ~0x01, rr>>3);
1798                                 } else {
1799                                         rr = rl >> 2;
1800                                         maskb(s->iobase + CODEC_CMI_MIXER2, ~0x0e, rr<<1);
1801                                 }
1802                         }
1803                         break;
1804
1805                 case MT_5MUTE:
1806                         rl = l < 4 ? 0 : (l - 5) / 3;
1807                         rr = r < 4 ? 0 : (r - 5) / 3;
1808                         wrmixer(s, mixtable[i].left, rl<<3);
1809                         wrmixer(s, mixtable[i].right, rr<<3);
1810                         l = rdmixer(s, DSP_MIX_OUTMIXIDX);
1811                         l &= ~mixtable[i].play;
1812                         r = (rl|rr) ? mixtable[i].play : 0;
1813                         wrmixer(s, DSP_MIX_OUTMIXIDX, l | r);
1814                         break;
1815
1816                 case MT_6MUTE:
1817                         if (l < 6)
1818                                 rl = 0x00;
1819                         else
1820                                 rl = l * 2 / 3;
1821                         if (r < 6)
1822                                 rr = 0x00;
1823                         else
1824                                 rr = r * 2 / 3;
1825                         wrmixer(s, mixtable[i].left, rl);
1826                         wrmixer(s, mixtable[i].right, rr);
1827                         break;
1828                 }
1829                 spin_unlock_irqrestore(&s->lock, flags);
1830
1831                 if (!volidx[i])
1832                         return -EINVAL;
1833                 s->mix.vol[volidx[i]-1] = val;
1834                 return put_user(s->mix.vol[volidx[i]-1], p);
1835         }
1836 }
1837
1838 /* --------------------------------------------------------------------- */
1839
1840 static int cm_open_mixdev(struct inode *inode, struct file *file)
1841 {
1842         int minor = iminor(inode);
1843         struct list_head *list;
1844         struct cm_state *s;
1845
1846         for (list = devs.next; ; list = list->next) {
1847                 if (list == &devs)
1848                         return -ENODEV;
1849                 s = list_entry(list, struct cm_state, devs);
1850                 if (s->dev_mixer == minor)
1851                         break;
1852         }
1853         VALIDATE_STATE(s);
1854         file->private_data = s;
1855         return 0;
1856 }
1857
1858 static int cm_release_mixdev(struct inode *inode, struct file *file)
1859 {
1860         struct cm_state *s = (struct cm_state *)file->private_data;
1861
1862         VALIDATE_STATE(s);
1863         return 0;
1864 }
1865
1866 static int cm_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1867 {
1868         return mixer_ioctl((struct cm_state *)file->private_data, cmd, arg);
1869 }
1870
1871 static /*const*/ struct file_operations cm_mixer_fops = {
1872         .owner   = THIS_MODULE,
1873         .llseek  = no_llseek,
1874         .ioctl   = cm_ioctl_mixdev,
1875         .open    = cm_open_mixdev,
1876         .release = cm_release_mixdev,
1877 };
1878
1879
1880 /* --------------------------------------------------------------------- */
1881
1882 static int drain_dac(struct cm_state *s, int nonblock)
1883 {
1884         DECLARE_WAITQUEUE(wait, current);
1885         unsigned long flags;
1886         int count, tmo;
1887
1888         if (s->dma_dac.mapped || !s->dma_dac.ready)
1889                 return 0;
1890         add_wait_queue(&s->dma_dac.wait, &wait);
1891         for (;;) {
1892                 __set_current_state(TASK_INTERRUPTIBLE);
1893                 spin_lock_irqsave(&s->lock, flags);
1894                 count = s->dma_dac.count;
1895                 spin_unlock_irqrestore(&s->lock, flags);
1896                 if (count <= 0)
1897                         break;
1898                 if (signal_pending(current))
1899                         break;
1900                 if (nonblock) {
1901                         remove_wait_queue(&s->dma_dac.wait, &wait);
1902                         set_current_state(TASK_RUNNING);
1903                         return -EBUSY;
1904                 }
1905                 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
1906                 tmo >>= sample_shift[(s->fmt >> CM_CFMT_DACSHIFT) & CM_CFMT_MASK];
1907                 if (!schedule_timeout(tmo + 1))
1908                         DBG(printk(KERN_DEBUG "cmpci: dma timed out??\n");)
1909         }
1910         remove_wait_queue(&s->dma_dac.wait, &wait);
1911         set_current_state(TASK_RUNNING);
1912         if (signal_pending(current))
1913                 return -ERESTARTSYS;
1914         return 0;
1915 }
1916
1917 /* --------------------------------------------------------------------- */
1918
1919 static ssize_t cm_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1920 {
1921         struct cm_state *s = (struct cm_state *)file->private_data;
1922         DECLARE_WAITQUEUE(wait, current);
1923         ssize_t ret;
1924         unsigned long flags;
1925         unsigned swptr;
1926         int cnt;
1927
1928         VALIDATE_STATE(s);
1929         if (ppos != &file->f_pos)
1930                 return -ESPIPE;
1931         if (s->dma_adc.mapped)
1932                 return -ENXIO;
1933         if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1934                 return ret;
1935         if (!access_ok(VERIFY_WRITE, buffer, count))
1936                 return -EFAULT;
1937         ret = 0;
1938
1939         add_wait_queue(&s->dma_adc.wait, &wait);
1940         while (count > 0) {
1941                 spin_lock_irqsave(&s->lock, flags);
1942                 swptr = s->dma_adc.swptr;
1943                 cnt = s->dma_adc.dmasize-swptr;
1944                 if (s->dma_adc.count < cnt)
1945                         cnt = s->dma_adc.count;
1946                 if (cnt <= 0)
1947                         __set_current_state(TASK_INTERRUPTIBLE);
1948                 spin_unlock_irqrestore(&s->lock, flags);
1949                 if (cnt > count)
1950                         cnt = count;
1951                 if (cnt <= 0) {
1952                         if (s->dma_adc.enabled)
1953                                 start_adc(s);
1954                         if (file->f_flags & O_NONBLOCK) {
1955                                 if (!ret)
1956                                         ret = -EAGAIN;
1957                                 goto out;
1958                         }
1959                         if (!schedule_timeout(HZ)) {
1960                                 printk(KERN_DEBUG "cmpci: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1961                                        s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1962                                        s->dma_adc.hwptr, s->dma_adc.swptr);
1963                                 spin_lock_irqsave(&s->lock, flags);
1964                                 stop_adc_unlocked(s);
1965                                 set_dmaadc(s, s->dma_adc.dmaaddr, s->dma_adc.dmasamples);
1966                                 /* program sample counts */
1967                                 set_countadc(s, s->dma_adc.fragsamples);
1968                                 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1969                                 spin_unlock_irqrestore(&s->lock, flags);
1970                         }
1971                         if (signal_pending(current)) {
1972                                 if (!ret)
1973                                         ret = -ERESTARTSYS;
1974                                 goto out;
1975                         }
1976                         continue;
1977                 }
1978                 if (s->status & DO_BIGENDIAN_R) {
1979                         int     i, err;
1980                         unsigned char *src;
1981                         char __user *dst = buffer;
1982                         unsigned char data[2];
1983
1984                         src = (unsigned char *) (s->dma_adc.rawbuf + swptr);
1985                         // copy left/right sample at one time
1986                         for (i = 0; i < cnt / 2; i++) {
1987                                 data[0] = src[1];
1988                                 data[1] = src[0];
1989                                 if ((err = __put_user(data[0], dst++))) {
1990                                         ret = err;
1991                                         goto out;
1992                                 }
1993                                 if ((err = __put_user(data[1], dst++))) {
1994                                         ret = err;
1995                                         goto out;
1996                                 }
1997                                 src += 2;
1998                         }
1999                 } else if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
2000                         if (!ret)
2001                                 ret = -EFAULT;
2002                         goto out;
2003                 }
2004                 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2005                 spin_lock_irqsave(&s->lock, flags);
2006                 s->dma_adc.swptr = swptr;
2007                 s->dma_adc.count -= cnt;
2008                 count -= cnt;
2009                 buffer += cnt;
2010                 ret += cnt;
2011                 if (s->dma_adc.enabled)
2012                         start_adc_unlocked(s);
2013                 spin_unlock_irqrestore(&s->lock, flags);
2014         }
2015 out:
2016         remove_wait_queue(&s->dma_adc.wait, &wait);
2017         set_current_state(TASK_RUNNING);
2018         return ret;
2019 }
2020
2021 static ssize_t cm_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2022 {
2023         struct cm_state *s = (struct cm_state *)file->private_data;
2024         DECLARE_WAITQUEUE(wait, current);
2025         ssize_t ret;
2026         unsigned long flags;
2027         unsigned swptr;
2028         int cnt;
2029
2030         VALIDATE_STATE(s);
2031         if (ppos != &file->f_pos)
2032                 return -ESPIPE;
2033         if (s->dma_dac.mapped)
2034                 return -ENXIO;
2035         if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2036                 return ret;
2037         if (!access_ok(VERIFY_READ, buffer, count))
2038                 return -EFAULT;
2039         if (s->status & DO_DUAL_DAC) {
2040                 if (s->dma_adc.mapped)
2041                         return -ENXIO;
2042                 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2043                         return ret;
2044         }
2045         if (!access_ok(VERIFY_READ, buffer, count))
2046                 return -EFAULT;
2047         ret = 0;
2048
2049         add_wait_queue(&s->dma_dac.wait, &wait);
2050         while (count > 0) {
2051                 spin_lock_irqsave(&s->lock, flags);
2052                 if (s->dma_dac.count < 0) {
2053                         s->dma_dac.count = 0;
2054                         s->dma_dac.swptr = s->dma_dac.hwptr;
2055                 }
2056                 if (s->status & DO_DUAL_DAC) {
2057                         s->dma_adc.swptr = s->dma_dac.swptr;
2058                         s->dma_adc.count = s->dma_dac.count;
2059                         s->dma_adc.endcleared = s->dma_dac.endcleared;
2060                 }
2061                 swptr = s->dma_dac.swptr;
2062                 cnt = s->dma_dac.dmasize-swptr;
2063                 if (s->status & DO_AC3_SW) {
2064                         if (s->dma_dac.count + 2 * cnt > s->dma_dac.dmasize)
2065                                 cnt = (s->dma_dac.dmasize - s->dma_dac.count) / 2;
2066                 } else {
2067                         if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
2068                                 cnt = s->dma_dac.dmasize - s->dma_dac.count;
2069                 }
2070                 if (cnt <= 0)
2071                         __set_current_state(TASK_INTERRUPTIBLE);
2072                 spin_unlock_irqrestore(&s->lock, flags);
2073                 if (cnt > count)
2074                         cnt = count;
2075                 if ((s->status & DO_DUAL_DAC) && (cnt > count / 2))
2076                     cnt = count / 2;
2077                 if (cnt <= 0) {
2078                         if (s->dma_dac.enabled)
2079                                 start_dac(s);
2080                         if (file->f_flags & O_NONBLOCK) {
2081                                 if (!ret)
2082                                         ret = -EAGAIN;
2083                                 goto out;
2084                         }
2085                         if (!schedule_timeout(HZ)) {
2086                                 printk(KERN_DEBUG "cmpci: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
2087                                        s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
2088                                        s->dma_dac.hwptr, s->dma_dac.swptr);
2089                                 spin_lock_irqsave(&s->lock, flags);
2090                                 stop_dac_unlocked(s);
2091                                 set_dmadac(s, s->dma_dac.dmaaddr, s->dma_dac.dmasamples);
2092                                 /* program sample counts */
2093                                 set_countdac(s, s->dma_dac.fragsamples);
2094                                 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
2095                                 if (s->status & DO_DUAL_DAC)  {
2096                                         set_dmadac1(s, s->dma_adc.dmaaddr, s->dma_adc.dmasamples);
2097                                         s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
2098                                 }
2099                                 spin_unlock_irqrestore(&s->lock, flags);
2100                         }
2101                         if (signal_pending(current)) {
2102                                 if (!ret)
2103                                         ret = -ERESTARTSYS;
2104                                 goto out;
2105                         }
2106                         continue;
2107                 }
2108                 if (s->status & DO_AC3_SW) {
2109                         int err;
2110
2111                         // clip exceeded data, caught by 033 and 037
2112                         if (swptr + 2 * cnt > s->dma_dac.dmasize)
2113                                 cnt = (s->dma_dac.dmasize - swptr) / 2;
2114                         if ((err = trans_ac3(s, s->dma_dac.rawbuf + swptr, buffer, cnt))) {
2115                                 ret = err;
2116                                 goto out;
2117                         }
2118                         swptr = (swptr + 2 * cnt) % s->dma_dac.dmasize;
2119                 } else if ((s->status & DO_DUAL_DAC) && (s->status & DO_BIGENDIAN_W)) {
2120                         int     i, err;
2121                         const char __user *src = buffer;
2122                         unsigned char *dst0, *dst1;
2123                         unsigned char data[8];
2124
2125                         dst0 = (unsigned char *) (s->dma_dac.rawbuf + swptr);
2126                         dst1 = (unsigned char *) (s->dma_adc.rawbuf + swptr);
2127                         // copy left/right sample at one time
2128                         for (i = 0; i < cnt / 4; i++) {
2129                                 if ((err = __get_user(data[0], src++))) {
2130                                         ret = err;
2131                                         goto out;
2132                                 }
2133                                 if ((err = __get_user(data[1], src++))) {
2134                                         ret = err;
2135                                         goto out;
2136                                 }
2137                                 if ((err = __get_user(data[2], src++))) {
2138                                         ret = err;
2139                                         goto out;
2140                                 }
2141                                 if ((err = __get_user(data[3], src++))) {
2142                                         ret = err;
2143                                         goto out;
2144                                 }
2145                                 if ((err = __get_user(data[4], src++))) {
2146                                         ret = err;
2147                                         goto out;
2148                                 }
2149                                 if ((err = __get_user(data[5], src++))) {
2150                                         ret = err;
2151                                         goto out;
2152                                 }
2153                                 if ((err = __get_user(data[6], src++))) {
2154                                         ret = err;
2155                                         goto out;
2156                                 }
2157                                 if ((err = __get_user(data[7], src++))) {
2158                                         ret = err;
2159                                         goto out;
2160                                 }
2161                                 dst0[0] = data[1];
2162                                 dst0[1] = data[0];
2163                                 dst0[2] = data[3];
2164                                 dst0[3] = data[2];
2165                                 dst1[0] = data[5];
2166                                 dst1[1] = data[4];
2167                                 dst1[2] = data[7];
2168                                 dst1[3] = data[6];
2169                                 dst0 += 4;
2170                                 dst1 += 4;
2171                         }
2172                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2173                 } else if (s->status & DO_DUAL_DAC) {
2174                         int     i, err;
2175                         unsigned long __user *src = (unsigned long __user *) buffer;
2176                         unsigned long *dst0, *dst1;
2177
2178                         dst0 = (unsigned long *) (s->dma_dac.rawbuf + swptr);
2179                         dst1 = (unsigned long *) (s->dma_adc.rawbuf + swptr);
2180                         // copy left/right sample at one time
2181                         for (i = 0; i < cnt / 4; i++) {
2182                                 if ((err = __get_user(*dst0++, src++))) {
2183                                         ret = err;
2184                                         goto out;
2185                                 }
2186                                 if ((err = __get_user(*dst1++, src++))) {
2187                                         ret = err;
2188                                         goto out;
2189                                 }
2190                         }
2191                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2192                 } else if (s->status & DO_BIGENDIAN_W) {
2193                         int     i, err;
2194                         const char __user *src = buffer;
2195                         unsigned char *dst;
2196                         unsigned char data[2];
2197
2198                         dst = (unsigned char *) (s->dma_dac.rawbuf + swptr);
2199                         // swap hi/lo bytes for each sample
2200                         for (i = 0; i < cnt / 2; i++) {
2201                                 if ((err = __get_user(data[0], src++))) {
2202                                         ret = err;
2203                                         goto out;
2204                                 }
2205                                 if ((err = __get_user(data[1], src++))) {
2206                                         ret = err;
2207                                         goto out;
2208                                 }
2209                                 dst[0] = data[1];
2210                                 dst[1] = data[0];
2211                                 dst += 2;
2212                         }
2213                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2214                 } else {
2215                         if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
2216                                 if (!ret)
2217                                         ret = -EFAULT;
2218                                 goto out;
2219                         }
2220                         swptr = (swptr + cnt) % s->dma_dac.dmasize;
2221                 }
2222                 spin_lock_irqsave(&s->lock, flags);
2223                 s->dma_dac.swptr = swptr;
2224                 s->dma_dac.count += cnt;
2225                 if (s->status & DO_AC3_SW)
2226                         s->dma_dac.count += cnt;
2227                 s->dma_dac.endcleared = 0;
2228                 spin_unlock_irqrestore(&s->lock, flags);
2229                 count -= cnt;
2230                 buffer += cnt;
2231                 ret += cnt;
2232                 if (s->status & DO_DUAL_DAC) {
2233                         count -= cnt;
2234                         buffer += cnt;
2235                         ret += cnt;
2236                 }
2237                 if (s->dma_dac.enabled)
2238                         start_dac(s);
2239         }
2240 out:
2241         remove_wait_queue(&s->dma_dac.wait, &wait);
2242         set_current_state(TASK_RUNNING);
2243         return ret;
2244 }
2245
2246 static unsigned int cm_poll(struct file *file, struct poll_table_struct *wait)
2247 {
2248         struct cm_state *s = (struct cm_state *)file->private_data;
2249         unsigned long flags;
2250         unsigned int mask = 0;
2251
2252         VALIDATE_STATE(s);
2253         if (file->f_mode & FMODE_WRITE) {
2254                 if (!s->dma_dac.ready && prog_dmabuf(s, 0))
2255                         return 0;
2256                 poll_wait(file, &s->dma_dac.wait, wait);
2257         }
2258         if (file->f_mode & FMODE_READ) {
2259                 if (!s->dma_adc.ready && prog_dmabuf(s, 1))
2260                         return 0;
2261                 poll_wait(file, &s->dma_adc.wait, wait);
2262         }
2263         spin_lock_irqsave(&s->lock, flags);
2264         cm_update_ptr(s);
2265         if (file->f_mode & FMODE_READ) {
2266                 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
2267                         mask |= POLLIN | POLLRDNORM;
2268         }
2269         if (file->f_mode & FMODE_WRITE) {
2270                 if (s->dma_dac.mapped) {
2271                         if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
2272                                 mask |= POLLOUT | POLLWRNORM;
2273                 } else {
2274                         if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
2275                                 mask |= POLLOUT | POLLWRNORM;
2276                 }
2277         }
2278         spin_unlock_irqrestore(&s->lock, flags);
2279         return mask;
2280 }
2281
2282 static int cm_mmap(struct file *file, struct vm_area_struct *vma)
2283 {
2284         struct cm_state *s = (struct cm_state *)file->private_data;
2285         struct dmabuf *db;
2286         int ret = -EINVAL;
2287         unsigned long size;
2288
2289         VALIDATE_STATE(s);
2290         lock_kernel();
2291         if (vma->vm_flags & VM_WRITE) {
2292                 if ((ret = prog_dmabuf(s, 0)) != 0)
2293                         goto out;
2294                 db = &s->dma_dac;
2295         } else if (vma->vm_flags & VM_READ) {
2296                 if ((ret = prog_dmabuf(s, 1)) != 0)
2297                         goto out;
2298                 db = &s->dma_adc;
2299         } else
2300                 goto out;
2301         ret = -EINVAL;
2302         if (vma->vm_pgoff != 0)
2303                 goto out;
2304         size = vma->vm_end - vma->vm_start;
2305         if (size > (PAGE_SIZE << db->buforder))
2306                 goto out;
2307         ret = -EINVAL;
2308         if (remap_page_range(vma, vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
2309                 goto out;
2310         db->mapped = 1;
2311         ret = 0;
2312 out:
2313         unlock_kernel();
2314         return ret;
2315 }
2316
2317 #define SNDCTL_SPDIF_COPYRIGHT  _SIOW('S',  0, int)       // set/reset S/PDIF copy protection
2318 #define SNDCTL_SPDIF_LOOP       _SIOW('S',  1, int)       // set/reset S/PDIF loop
2319 #define SNDCTL_SPDIF_MONITOR    _SIOW('S',  2, int)       // set S/PDIF monitor
2320 #define SNDCTL_SPDIF_LEVEL      _SIOW('S',  3, int)       // set/reset S/PDIF out level
2321 #define SNDCTL_SPDIF_INV        _SIOW('S',  4, int)       // set/reset S/PDIF in inverse
2322 #define SNDCTL_SPDIF_SEL2       _SIOW('S',  5, int)       // set S/PDIF in #2
2323 #define SNDCTL_SPDIF_VALID      _SIOW('S',  6, int)       // set S/PDIF valid
2324 #define SNDCTL_SPDIFOUT         _SIOW('S',  7, int)       // set S/PDIF out
2325 #define SNDCTL_SPDIFIN          _SIOW('S',  8, int)       // set S/PDIF out
2326
2327 static int cm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2328 {
2329         struct cm_state *s = (struct cm_state *)file->private_data;
2330         unsigned long flags;
2331         audio_buf_info abinfo;
2332         count_info cinfo;
2333         int val, mapped, ret;
2334         unsigned char fmtm, fmtd;
2335         void __user *argp = (void __user *)arg;
2336         int __user *p = argp;
2337
2338         VALIDATE_STATE(s);
2339         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
2340                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
2341         switch (cmd) {
2342         case OSS_GETVERSION:
2343                 return put_user(SOUND_VERSION, p);
2344
2345         case SNDCTL_DSP_SYNC:
2346                 if (file->f_mode & FMODE_WRITE)
2347                         return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
2348                 return 0;
2349
2350         case SNDCTL_DSP_SETDUPLEX:
2351                 return 0;
2352
2353         case SNDCTL_DSP_GETCAPS:
2354                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP | DSP_CAP_BIND, p);
2355
2356         case SNDCTL_DSP_RESET:
2357                 if (file->f_mode & FMODE_WRITE) {
2358                         stop_dac(s);
2359                         synchronize_irq(s->irq);
2360                         s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
2361                         if (s->status & DO_DUAL_DAC)
2362                                 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2363                 }
2364                 if (file->f_mode & FMODE_READ) {
2365                         stop_adc(s);
2366                         synchronize_irq(s->irq);
2367                         s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2368                 }
2369                 return 0;
2370
2371         case SNDCTL_DSP_SPEED:
2372                 if (get_user(val, p))
2373                         return -EFAULT;
2374                 if (val >= 0) {
2375                         if (file->f_mode & FMODE_READ) {
2376                                 spin_lock_irqsave(&s->lock, flags);
2377                                 stop_adc_unlocked(s);
2378                                 s->dma_adc.ready = 0;
2379                                 set_adc_rate_unlocked(s, val);
2380                                 spin_unlock_irqrestore(&s->lock, flags);
2381                         }
2382                         if (file->f_mode & FMODE_WRITE) {
2383                                 stop_dac(s);
2384                                 s->dma_dac.ready = 0;
2385                                 if (s->status & DO_DUAL_DAC)
2386                                         s->dma_adc.ready = 0;
2387                                 set_dac_rate(s, val);
2388                         }
2389                 }
2390                 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
2391
2392         case SNDCTL_DSP_STEREO:
2393                 if (get_user(val, p))
2394                         return -EFAULT;
2395                 fmtd = 0;
2396                 fmtm = ~0;
2397                 if (file->f_mode & FMODE_READ) {
2398                         stop_adc(s);
2399                         s->dma_adc.ready = 0;
2400                         if (val)
2401                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2402                         else
2403                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2404                 }
2405                 if (file->f_mode & FMODE_WRITE) {
2406                         stop_dac(s);
2407                         s->dma_dac.ready = 0;
2408                         if (val)
2409                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2410                         else
2411                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_DACSHIFT);
2412                         if (s->status & DO_DUAL_DAC) {
2413                                 s->dma_adc.ready = 0;
2414                                 if (val)
2415                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2416                                 else
2417                                         fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2418                         }
2419                 }
2420                 set_fmt(s, fmtm, fmtd);
2421                 return 0;
2422
2423         case SNDCTL_DSP_CHANNELS:
2424                 if (get_user(val, p))
2425                         return -EFAULT;
2426                 if (val != 0) {
2427                         fmtd = 0;
2428                         fmtm = ~0;
2429                         if (file->f_mode & FMODE_READ) {
2430                                 stop_adc(s);
2431                                 s->dma_adc.ready = 0;
2432                                 if (val >= 2)
2433                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2434                                 else
2435                                         fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2436                         }
2437                         if (file->f_mode & FMODE_WRITE) {
2438                                 stop_dac(s);
2439                                 s->dma_dac.ready = 0;
2440                                 if (val >= 2)
2441                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2442                                 else
2443                                         fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_DACSHIFT);
2444                                 if (s->status & DO_DUAL_DAC) {
2445                                         s->dma_adc.ready = 0;
2446                                         if (val >= 2)
2447                                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2448                                         else
2449                                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2450                                 }
2451                         }
2452                         set_fmt(s, fmtm, fmtd);
2453                         if ((s->capability & CAN_MULTI_CH)
2454                              && (file->f_mode & FMODE_WRITE)) {
2455                                 val = set_dac_channels(s, val);
2456                                 return put_user(val, p);
2457                         }
2458                 }
2459                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_STEREO << CM_CFMT_ADCSHIFT)
2460                                            : (CM_CFMT_STEREO << CM_CFMT_DACSHIFT))) ? 2 : 1, p);
2461
2462         case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2463                 return put_user(AFMT_S16_BE|AFMT_S16_LE|AFMT_U8|
2464                         ((s->capability & CAN_AC3) ? AFMT_AC3 : 0), p);
2465
2466         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2467                 if (get_user(val, p))
2468                         return -EFAULT;
2469                 if (val != AFMT_QUERY) {
2470                         fmtd = 0;
2471                         fmtm = ~0;
2472                         if (file->f_mode & FMODE_READ) {
2473                                 stop_adc(s);
2474                                 s->dma_adc.ready = 0;
2475                                 if (val == AFMT_S16_BE || val == AFMT_S16_LE)
2476                                         fmtd |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
2477                                 else
2478                                         fmtm &= ~(CM_CFMT_16BIT << CM_CFMT_ADCSHIFT);
2479                                 if (val == AFMT_S16_BE)
2480                                         s->status |= DO_BIGENDIAN_R;
2481                                 else
2482                                         s->status &= ~DO_BIGENDIAN_R;
2483                         }
2484                         if (file->f_mode & FMODE_WRITE) {
2485                                 stop_dac(s);
2486                                 s->dma_dac.ready = 0;
2487                                 if (val == AFMT_S16_BE || val == AFMT_S16_LE || val == AFMT_AC3)
2488                                         fmtd |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
2489                                 else
2490                                         fmtm &= ~(CM_CFMT_16BIT << CM_CFMT_DACSHIFT);
2491                                 if (val == AFMT_AC3) {
2492                                         fmtd |= CM_CFMT_STEREO << CM_CFMT_DACSHIFT;
2493                                         set_ac3(s, 48000);
2494                                 } else
2495                                         set_ac3(s, 0);
2496                                 if (s->status & DO_DUAL_DAC) {
2497                                         s->dma_adc.ready = 0;
2498                                         if (val == AFMT_S16_BE || val == AFMT_S16_LE)
2499                                                 fmtd |= CM_CFMT_STEREO << CM_CFMT_ADCSHIFT;
2500                                         else
2501                                                 fmtm &= ~(CM_CFMT_STEREO << CM_CFMT_ADCSHIFT);
2502                                 }
2503                                 if (val == AFMT_S16_BE)
2504                                         s->status |= DO_BIGENDIAN_W;
2505                                 else
2506                                         s->status &= ~DO_BIGENDIAN_W;
2507                         }
2508                         set_fmt(s, fmtm, fmtd);
2509                 }
2510                 if (s->status & DO_AC3) return put_user(AFMT_AC3, p);
2511                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_16BIT << CM_CFMT_ADCSHIFT)
2512                                            : (CM_CFMT_16BIT << CM_CFMT_DACSHIFT))) ? val : AFMT_U8, p);
2513
2514         case SNDCTL_DSP_POST:
2515                 return 0;
2516
2517         case SNDCTL_DSP_GETTRIGGER:
2518                 val = 0;
2519                 if (s->status & DO_DUAL_DAC) {
2520                         if (file->f_mode & FMODE_WRITE &&
2521                          (s->enable & ENDAC) &&
2522                          (s->enable & ENADC))
2523                                 val |= PCM_ENABLE_OUTPUT;
2524                         return put_user(val, p);
2525                 }
2526                 if (file->f_mode & FMODE_READ && s->enable & ENADC)
2527                         val |= PCM_ENABLE_INPUT;
2528                 if (file->f_mode & FMODE_WRITE && s->enable & ENDAC)
2529                         val |= PCM_ENABLE_OUTPUT;
2530                 return put_user(val, p);
2531
2532         case SNDCTL_DSP_SETTRIGGER:
2533                 if (get_user(val, p))
2534                         return -EFAULT;
2535                 if (file->f_mode & FMODE_READ) {
2536                         if (val & PCM_ENABLE_INPUT) {
2537                                 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2538                                         return ret;
2539                                 s->dma_adc.enabled = 1;
2540                                 start_adc(s);
2541                         } else {
2542                                 s->dma_adc.enabled = 0;
2543                                 stop_adc(s);
2544                         }
2545                 }
2546                 if (file->f_mode & FMODE_WRITE) {
2547                         if (val & PCM_ENABLE_OUTPUT) {
2548                                 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2549                                         return ret;
2550                                 if (s->status & DO_DUAL_DAC) {
2551                                         if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2552                                                 return ret;
2553                                 }
2554                                 s->dma_dac.enabled = 1;
2555                                 start_dac(s);
2556                         } else {
2557                                 s->dma_dac.enabled = 0;
2558                                 stop_dac(s);
2559                         }
2560                 }
2561                 return 0;
2562
2563         case SNDCTL_DSP_GETOSPACE:
2564                 if (!(file->f_mode & FMODE_WRITE))
2565                         return -EINVAL;
2566                 if (!(s->enable & ENDAC) && (val = prog_dmabuf(s, 0)) != 0)
2567                         return val;
2568                 spin_lock_irqsave(&s->lock, flags);
2569                 cm_update_ptr(s);
2570                 abinfo.fragsize = s->dma_dac.fragsize;
2571                 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
2572                 abinfo.fragstotal = s->dma_dac.numfrag;
2573                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2574                 spin_unlock_irqrestore(&s->lock, flags);
2575                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2576
2577         case SNDCTL_DSP_GETISPACE:
2578                 if (!(file->f_mode & FMODE_READ))
2579                         return -EINVAL;
2580                 if (!(s->enable & ENADC) && (val = prog_dmabuf(s, 1)) != 0)
2581                         return val;
2582                 spin_lock_irqsave(&s->lock, flags);
2583                 cm_update_ptr(s);
2584                 abinfo.fragsize = s->dma_adc.fragsize;
2585                 abinfo.bytes = s->dma_adc.count;
2586                 abinfo.fragstotal = s->dma_adc.numfrag;
2587                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
2588                 spin_unlock_irqrestore(&s->lock, flags);
2589                 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2590
2591         case SNDCTL_DSP_NONBLOCK:
2592                 file->f_flags |= O_NONBLOCK;
2593                 return 0;
2594
2595         case SNDCTL_DSP_GETODELAY:
2596                 if (!(file->f_mode & FMODE_WRITE))
2597                         return -EINVAL;
2598                 spin_lock_irqsave(&s->lock, flags);
2599                 cm_update_ptr(s);
2600                 val = s->dma_dac.count;
2601                 spin_unlock_irqrestore(&s->lock, flags);
2602                 return put_user(val, p);
2603
2604         case SNDCTL_DSP_GETIPTR:
2605                 if (!(file->f_mode & FMODE_READ))
2606                         return -EINVAL;
2607                 spin_lock_irqsave(&s->lock, flags);
2608                 cm_update_ptr(s);
2609                 cinfo.bytes = s->dma_adc.total_bytes;
2610                 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
2611                 cinfo.ptr = s->dma_adc.hwptr;
2612                 if (s->dma_adc.mapped)
2613                         s->dma_adc.count &= s->dma_adc.fragsize-1;
2614                 spin_unlock_irqrestore(&s->lock, flags);
2615                 return copy_to_user(argp, &cinfo, sizeof(cinfo))  ? -EFAULT : 0;
2616
2617         case SNDCTL_DSP_GETOPTR:
2618                 if (!(file->f_mode & FMODE_WRITE))
2619                         return -EINVAL;
2620                 spin_lock_irqsave(&s->lock, flags);
2621                 cm_update_ptr(s);
2622                 cinfo.bytes = s->dma_dac.total_bytes;
2623                 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
2624                 cinfo.ptr = s->dma_dac.hwptr;
2625                 if (s->dma_dac.mapped)
2626                         s->dma_dac.count &= s->dma_dac.fragsize-1;
2627                 if (s->status & DO_DUAL_DAC) {
2628                         if (s->dma_adc.mapped)
2629                                 s->dma_adc.count &= s->dma_adc.fragsize-1;
2630                 }
2631                 spin_unlock_irqrestore(&s->lock, flags);
2632                 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2633
2634         case SNDCTL_DSP_GETBLKSIZE:
2635                 if (file->f_mode & FMODE_WRITE) {
2636                         if ((val = prog_dmabuf(s, 0)))
2637                                 return val;
2638                         if (s->status & DO_DUAL_DAC) {
2639                                 if ((val = prog_dmabuf(s, 1)))
2640                                         return val;
2641                                 return put_user(2 * s->dma_dac.fragsize, p);
2642                         }
2643                         return put_user(s->dma_dac.fragsize, p);
2644                 }
2645                 if ((val = prog_dmabuf(s, 1)))
2646                         return val;
2647                 return put_user(s->dma_adc.fragsize, p);
2648
2649         case SNDCTL_DSP_SETFRAGMENT:
2650                 if (get_user(val, p))
2651                         return -EFAULT;
2652                 if (file->f_mode & FMODE_READ) {
2653                         s->dma_adc.ossfragshift = val & 0xffff;
2654                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
2655                         if (s->dma_adc.ossfragshift < 4)
2656                                 s->dma_adc.ossfragshift = 4;
2657                         if (s->dma_adc.ossfragshift > 15)
2658                                 s->dma_adc.ossfragshift = 15;
2659                         if (s->dma_adc.ossmaxfrags < 4)
2660                                 s->dma_adc.ossmaxfrags = 4;
2661                 }
2662                 if (file->f_mode & FMODE_WRITE) {
2663                         s->dma_dac.ossfragshift = val & 0xffff;
2664                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
2665                         if (s->dma_dac.ossfragshift < 4)
2666                                 s->dma_dac.ossfragshift = 4;
2667                         if (s->dma_dac.ossfragshift > 15)
2668                                 s->dma_dac.ossfragshift = 15;
2669                         if (s->dma_dac.ossmaxfrags < 4)
2670                                 s->dma_dac.ossmaxfrags = 4;
2671                         if (s->status & DO_DUAL_DAC) {
2672                                 s->dma_adc.ossfragshift = s->dma_dac.ossfragshift;
2673                                 s->dma_adc.ossmaxfrags = s->dma_dac.ossmaxfrags;
2674                         }
2675                 }
2676                 return 0;
2677
2678         case SNDCTL_DSP_SUBDIVIDE:
2679                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
2680                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
2681                         return -EINVAL;
2682                 if (get_user(val, p))
2683                         return -EFAULT;
2684                 if (val != 1 && val != 2 && val != 4)
2685                         return -EINVAL;
2686                 if (file->f_mode & FMODE_READ)
2687                         s->dma_adc.subdivision = val;
2688                 if (file->f_mode & FMODE_WRITE) {
2689                         s->dma_dac.subdivision = val;
2690                         if (s->status & DO_DUAL_DAC)
2691                                 s->dma_adc.subdivision = val;
2692                 }
2693                 return 0;
2694
2695         case SOUND_PCM_READ_RATE:
2696                 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
2697
2698         case SOUND_PCM_READ_CHANNELS:
2699                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_STEREO << CM_CFMT_ADCSHIFT) : (CM_CFMT_STEREO << CM_CFMT_DACSHIFT))) ? 2 : 1, p);
2700
2701         case SOUND_PCM_READ_BITS:
2702                 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (CM_CFMT_16BIT << CM_CFMT_ADCSHIFT) : (CM_CFMT_16BIT << CM_CFMT_DACSHIFT))) ? 16 : 8, p);
2703
2704         case SOUND_PCM_READ_FILTER:
2705                 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
2706
2707         case SNDCTL_DSP_GETCHANNELMASK:
2708                 return put_user(DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE|DSP_BIND_SPDIF, p);
2709
2710         case SNDCTL_DSP_BIND_CHANNEL:
2711                 if (get_user(val, p))
2712                         return -EFAULT;
2713                 if (val == DSP_BIND_QUERY) {
2714                         val = DSP_BIND_FRONT;
2715                         if (s->status & DO_SPDIF_OUT)
2716                                 val |= DSP_BIND_SPDIF;
2717                         else {
2718                                 if (s->curr_channels == 4)
2719                                         val |= DSP_BIND_SURR;
2720                                 if (s->curr_channels > 4)
2721                                         val |= DSP_BIND_CENTER_LFE;
2722                         }
2723                 } else {
2724                         if (file->f_mode & FMODE_READ) {
2725                                 stop_adc(s);
2726                                 s->dma_adc.ready = 0;
2727                                 if (val & DSP_BIND_SPDIF) {
2728                                         set_spdifin(s, s->rateadc);
2729                                         if (!(s->status & DO_SPDIF_OUT))
2730                                                 val &= ~DSP_BIND_SPDIF;
2731                                 }
2732                         }
2733                         if (file->f_mode & FMODE_WRITE) {
2734                                 stop_dac(s);
2735                                 s->dma_dac.ready = 0;
2736                                 if (val & DSP_BIND_SPDIF) {
2737                                         set_spdifout(s, s->ratedac);
2738                                         set_dac_channels(s, s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1);
2739                                         if (!(s->status & DO_SPDIF_OUT))
2740                                                 val &= ~DSP_BIND_SPDIF;
2741                                 } else {
2742                                         int channels;
2743                                         int mask;
2744
2745                                         mask = val & (DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE);
2746                                         switch (mask) {
2747                                             case DSP_BIND_FRONT:
2748                                                 channels = 2;
2749                                                 break;
2750                                             case DSP_BIND_FRONT|DSP_BIND_SURR:
2751                                                 channels = 4;
2752                                                 break;
2753                                             case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2754                                                 channels = 6;
2755                                                 break;
2756                                             default:
2757                                                 channels = s->fmt & (CM_CFMT_STEREO << CM_CFMT_DACSHIFT) ? 2 : 1;
2758                                                 break;
2759                                         }
2760                                         set_dac_channels(s, channels);
2761                                 }
2762                         }
2763                 }
2764                 return put_user(val, p);
2765
2766         case SOUND_PCM_WRITE_FILTER:
2767         case SNDCTL_DSP_MAPINBUF:
2768         case SNDCTL_DSP_MAPOUTBUF:
2769         case SNDCTL_DSP_SETSYNCRO:
2770                 return -EINVAL;
2771         case SNDCTL_SPDIF_COPYRIGHT:
2772                 if (get_user(val, p))
2773                         return -EFAULT;
2774                 set_spdif_copyright(s, val);
2775                 return 0;
2776         case SNDCTL_SPDIF_LOOP:
2777                 if (get_user(val, p))
2778                         return -EFAULT;
2779                 set_spdif_loop(s, val);
2780                 return 0;
2781         case SNDCTL_SPDIF_MONITOR:
2782                 if (get_user(val, p))
2783                         return -EFAULT;
2784                 set_spdif_monitor(s, val);
2785                 return 0;
2786         case SNDCTL_SPDIF_LEVEL:
2787                 if (get_user(val, p))
2788                         return -EFAULT;
2789                 set_spdifout_level(s, val);
2790                 return 0;
2791         case SNDCTL_SPDIF_INV:
2792                 if (get_user(val, p))
2793                         return -EFAULT;
2794                 set_spdifin_inverse(s, val);
2795                 return 0;
2796         case SNDCTL_SPDIF_SEL2:
2797                 if (get_user(val, p))
2798                         return -EFAULT;
2799                 set_spdifin_channel2(s, val);
2800                 return 0;
2801         case SNDCTL_SPDIF_VALID:
2802                 if (get_user(val, p))
2803                         return -EFAULT;
2804                 set_spdifin_valid(s, val);
2805                 return 0;
2806         case SNDCTL_SPDIFOUT:
2807                 if (get_user(val, p))
2808                         return -EFAULT;
2809                 set_spdifout(s, val ? s->ratedac : 0);
2810                 return 0;
2811         case SNDCTL_SPDIFIN:
2812                 if (get_user(val, p))
2813                         return -EFAULT;
2814                 set_spdifin(s, val ? s->rateadc : 0);
2815                 return 0;
2816         }
2817         return mixer_ioctl(s, cmd, arg);
2818 }
2819
2820 static int cm_open(struct inode *inode, struct file *file)
2821 {
2822         int minor = iminor(inode);
2823         DECLARE_WAITQUEUE(wait, current);
2824         unsigned char fmtm = ~0, fmts = 0;
2825         struct list_head *list;
2826         struct cm_state *s;
2827
2828         for (list = devs.next; ; list = list->next) {
2829                 if (list == &devs)
2830                         return -ENODEV;
2831                 s = list_entry(list, struct cm_state, devs);
2832                 if (!((s->dev_audio ^ minor) & ~0xf))
2833                         break;
2834         }
2835         VALIDATE_STATE(s);
2836         file->private_data = s;
2837         /* wait for device to become free */
2838         down(&s->open_sem);
2839         while (s->open_mode & file->f_mode) {
2840                 if (file->f_flags & O_NONBLOCK) {
2841                         up(&s->open_sem);
2842                         return -EBUSY;
2843                 }
2844                 add_wait_queue(&s->open_wait, &wait);
2845                 __set_current_state(TASK_INTERRUPTIBLE);
2846                 up(&s->open_sem);
2847                 schedule();
2848                 remove_wait_queue(&s->open_wait, &wait);
2849                 set_current_state(TASK_RUNNING);
2850                 if (signal_pending(current))
2851                         return -ERESTARTSYS;
2852                 down(&s->open_sem);
2853         }
2854         if (file->f_mode & FMODE_READ) {
2855                 s->status &= ~DO_BIGENDIAN_R;
2856                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_ADCSHIFT);
2857                 if ((minor & 0xf) == SND_DEV_DSP16)
2858                         fmts |= CM_CFMT_16BIT << CM_CFMT_ADCSHIFT;
2859                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2860                 s->dma_adc.enabled = 1;
2861                 set_adc_rate(s, 8000);
2862                 // spdif-in is turnned off by default
2863                 set_spdifin(s, 0);
2864         }
2865         if (file->f_mode & FMODE_WRITE) {
2866                 s->status &= ~DO_BIGENDIAN_W;
2867                 fmtm &= ~((CM_CFMT_STEREO | CM_CFMT_16BIT) << CM_CFMT_DACSHIFT);
2868                 if ((minor & 0xf) == SND_DEV_DSP16)
2869                         fmts |= CM_CFMT_16BIT << CM_CFMT_DACSHIFT;
2870                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2871                 s->dma_dac.enabled = 1;
2872                 set_dac_rate(s, 8000);
2873                 // clear previous multichannel, spdif, ac3 state
2874                 set_spdifout(s, 0);
2875                 set_ac3(s, 0);
2876                 set_dac_channels(s, 1);
2877         }
2878         set_fmt(s, fmtm, fmts);
2879         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2880         up(&s->open_sem);
2881         return 0;
2882 }
2883
2884 static int cm_release(struct inode *inode, struct file *file)
2885 {
2886         struct cm_state *s = (struct cm_state *)file->private_data;
2887
2888         VALIDATE_STATE(s);
2889         lock_kernel();
2890         if (file->f_mode & FMODE_WRITE)
2891                 drain_dac(s, file->f_flags & O_NONBLOCK);
2892         down(&s->open_sem);
2893         if (file->f_mode & FMODE_WRITE) {
2894                 stop_dac(s);
2895
2896                 dealloc_dmabuf(s, &s->dma_dac);
2897                 if (s->status & DO_DUAL_DAC)
2898                         dealloc_dmabuf(s, &s->dma_adc);
2899
2900                 if (s->status & DO_MULTI_CH)
2901                         set_dac_channels(s, 1);
2902                 if (s->status & DO_AC3)
2903                         set_ac3(s, 0);
2904                 if (s->status & DO_SPDIF_OUT)
2905                         set_spdifout(s, 0);
2906                 /* enable SPDIF loop */
2907                 set_spdif_loop(s, spdif_loop);
2908                 s->status &= ~DO_BIGENDIAN_W;
2909         }
2910         if (file->f_mode & FMODE_READ) {
2911                 stop_adc(s);
2912                 dealloc_dmabuf(s, &s->dma_adc);
2913                 s->status &= ~DO_BIGENDIAN_R;
2914         }
2915         s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2916         up(&s->open_sem);
2917         wake_up(&s->open_wait);
2918         unlock_kernel();
2919         return 0;
2920 }
2921
2922 static /*const*/ struct file_operations cm_audio_fops = {
2923         .owner   = THIS_MODULE,
2924         .llseek  = no_llseek,
2925         .read    = cm_read,
2926         .write   = cm_write,
2927         .poll    = cm_poll,
2928         .ioctl   = cm_ioctl,
2929         .mmap    = cm_mmap,
2930         .open    = cm_open,
2931         .release = cm_release,
2932 };
2933
2934 /* --------------------------------------------------------------------- */
2935
2936 static struct initvol {
2937         int mixch;
2938         int vol;
2939 } initvol[] __initdata = {
2940         { SOUND_MIXER_WRITE_CD, 0x4f4f },
2941         { SOUND_MIXER_WRITE_LINE, 0x4f4f },
2942         { SOUND_MIXER_WRITE_MIC, 0x4f4f },
2943         { SOUND_MIXER_WRITE_SYNTH, 0x4f4f },
2944         { SOUND_MIXER_WRITE_VOLUME, 0x4f4f },
2945         { SOUND_MIXER_WRITE_PCM, 0x4f4f }
2946 };
2947
2948 /* check chip version and capability */
2949 static int query_chip(struct cm_state *s)
2950 {
2951         int ChipVersion = -1;
2952         unsigned char RegValue;
2953
2954         // check reg 0Ch, bit 24-31
2955         RegValue = inb(s->iobase + CODEC_CMI_INT_HLDCLR + 3);
2956         if (RegValue == 0) {
2957             // check reg 08h, bit 24-28
2958             RegValue = inb(s->iobase + CODEC_CMI_CHFORMAT + 3);
2959             RegValue &= 0x1f;
2960             if (RegValue == 0) {
2961                 ChipVersion = 33;
2962                 s->max_channels = 4;
2963                 s->capability |= CAN_AC3_SW;
2964                 s->capability |= CAN_DUAL_DAC;
2965             } else {
2966                 ChipVersion = 37;
2967                 s->max_channels = 4;
2968                 s->capability |= CAN_AC3_HW;
2969                 s->capability |= CAN_DUAL_DAC;
2970             }
2971         } else {
2972             // check reg 0Ch, bit 26
2973             if (RegValue & (1 << (26-24))) {
2974                 ChipVersion = 39;
2975                 if (RegValue & (1 << (24-24)))
2976                     s->max_channels = 6;
2977                 else
2978                     s->max_channels = 4;
2979                 s->capability |= CAN_AC3_HW;
2980                 s->capability |= CAN_DUAL_DAC;
2981                 s->capability |= CAN_MULTI_CH_HW;
2982                 s->capability |= CAN_LINE_AS_BASS;
2983                 s->capability |= CAN_MIC_AS_BASS;
2984             } else {
2985                 ChipVersion = 55; // 4 or 6 channels
2986                 s->max_channels = 6;
2987                 s->capability |= CAN_AC3_HW;
2988                 s->capability |= CAN_DUAL_DAC;
2989                 s->capability |= CAN_MULTI_CH_HW;
2990                 s->capability |= CAN_LINE_AS_BASS;
2991                 s->capability |= CAN_MIC_AS_BASS;
2992             }
2993         }
2994         s->capability |= CAN_LINE_AS_REAR;
2995         return ChipVersion;
2996 }
2997
2998 #define echo_option(x)\
2999 if (x) strcat(options, "" #x " ")
3000
3001 static int __devinit cm_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
3002 {
3003         struct cm_state *s;
3004         mm_segment_t fs;
3005         int i, val, ret;
3006         unsigned char reg_mask;
3007         struct {
3008                 unsigned short  deviceid;
3009                 char            *devicename;
3010         } devicetable[] = {
3011                 { PCI_DEVICE_ID_CMEDIA_CM8338A, "CM8338A" },
3012                 { PCI_DEVICE_ID_CMEDIA_CM8338B, "CM8338B" },
3013                 { PCI_DEVICE_ID_CMEDIA_CM8738,  "CM8738" },
3014                 { PCI_DEVICE_ID_CMEDIA_CM8738B, "CM8738B" },
3015         };
3016         char    *devicename = "unknown";
3017         char    options[256];
3018
3019         if ((ret = pci_enable_device(pcidev)))
3020                 return ret;
3021         if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
3022                 return -ENODEV;
3023         if (pcidev->irq == 0)
3024                 return -ENODEV;
3025         i = pci_set_dma_mask(pcidev, 0xffffffff);
3026         if (i) {
3027                 printk(KERN_WARNING "cmpci: architecture does not support 32bit PCI busmaster DMA\n");
3028                 return i;
3029         }
3030         s = kmalloc(sizeof(*s), GFP_KERNEL);
3031         if (!s) {
3032                 printk(KERN_WARNING "cmpci: out of memory\n");
3033                 return -ENOMEM;
3034         }
3035         /* search device name */
3036         for (i = 0; i < sizeof(devicetable) / sizeof(devicetable[0]); i++) {
3037                 if (devicetable[i].deviceid == pcidev->device) {
3038                         devicename = devicetable[i].devicename;
3039                         break;
3040                 }
3041         }
3042         memset(s, 0, sizeof(struct cm_state));
3043         init_waitqueue_head(&s->dma_adc.wait);
3044         init_waitqueue_head(&s->dma_dac.wait);
3045         init_waitqueue_head(&s->open_wait);
3046         init_MUTEX(&s->open_sem);
3047         spin_lock_init(&s->lock);
3048         s->magic = CM_MAGIC;
3049         s->dev = pcidev;
3050         s->iobase = pci_resource_start(pcidev, 0);
3051         s->iosynth = fmio;
3052         s->iomidi = mpuio;
3053 #ifdef CONFIG_SOUND_CMPCI_MIDI
3054         s->midi_devc = 0;
3055 #endif
3056         s->status = 0;
3057         if (s->iobase == 0)
3058                 return -ENODEV;
3059         s->irq = pcidev->irq;
3060
3061         if (!request_region(s->iobase, CM_EXTENT_CODEC, "cmpci")) {
3062                 printk(KERN_ERR "cmpci: io ports %#x-%#x in use\n", s->iobase, s->iobase+CM_EXTENT_CODEC-1);
3063                 ret = -EBUSY;
3064                 goto err_region5;
3065         }
3066         /* dump parameters */
3067         strcpy(options, "cmpci: ");
3068         echo_option(joystick);
3069         echo_option(spdif_inverse);
3070         echo_option(spdif_loop);
3071         echo_option(spdif_out);
3072         echo_option(use_line_as_rear);
3073         echo_option(use_line_as_bass);
3074         echo_option(use_mic_as_bass);
3075         echo_option(mic_boost);
3076         echo_option(hw_copy);
3077         printk(KERN_INFO "%s\n", options);
3078
3079         /* initialize codec registers */
3080         outb(0, s->iobase + CODEC_CMI_INT_HLDCLR + 2);  /* disable ints */
3081         outb(0, s->iobase + CODEC_CMI_FUNCTRL0 + 2); /* disable channels */
3082         /* reset mixer */
3083         wrmixer(s, DSP_MIX_DATARESETIDX, 0);
3084
3085         /* request irq */
3086         if ((ret = request_irq(s->irq, cm_interrupt, SA_SHIRQ, "cmpci", s))) {
3087                 printk(KERN_ERR "cmpci: irq %u in use\n", s->irq);
3088                 goto err_irq;
3089         }
3090         printk(KERN_INFO "cmpci: found %s adapter at io %#x irq %u\n",
3091                devicename, s->iobase, s->irq);
3092         /* register devices */
3093         if ((s->dev_audio = register_sound_dsp(&cm_audio_fops, -1)) < 0) {
3094                 ret = s->dev_audio;
3095                 goto err_dev1;
3096         }
3097         if ((s->dev_mixer = register_sound_mixer(&cm_mixer_fops, -1)) < 0) {
3098                 ret = s->dev_mixer;
3099                 goto err_dev2;
3100         }
3101         pci_set_master(pcidev); /* enable bus mastering */
3102         /* initialize the chips */
3103         fs = get_fs();
3104         set_fs(KERNEL_DS);
3105         /* set mixer output */
3106         frobindir(s, DSP_MIX_OUTMIXIDX, 0x1f, 0x1f);
3107         /* set mixer input */
3108         val = SOUND_MASK_LINE|SOUND_MASK_SYNTH|SOUND_MASK_CD|SOUND_MASK_MIC;
3109         mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
3110         for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
3111                 val = initvol[i].vol;
3112                 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
3113         }
3114         set_fs(fs);
3115         /* use channel 1 for playback, channel 0 for record */
3116         maskb(s->iobase + CODEC_CMI_FUNCTRL0, ~CHADC1, CHADC0);
3117         /* turn off VMIC3 - mic boost */
3118         if (mic_boost)
3119                 maskb(s->iobase + CODEC_CMI_MIXER2, ~1, 0);
3120         else
3121                 maskb(s->iobase + CODEC_CMI_MIXER2, ~0, 1);
3122         s->deviceid = pcidev->device;
3123
3124         if (pcidev->device == PCI_DEVICE_ID_CMEDIA_CM8738
3125          || pcidev->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
3126
3127                 /* chip version and hw capability check */
3128                 s->chip_version = query_chip(s);
3129                 printk(KERN_INFO "cmpci: chip version = 0%d\n", s->chip_version);
3130
3131                 /* set SPDIF-in inverse before enable SPDIF loop */
3132                 set_spdifin_inverse(s, spdif_inverse);
3133
3134                 /* use SPDIF in #1 */
3135                 set_spdifin_channel2(s, 0);
3136         } else {
3137                 s->chip_version = 0;
3138                 /* 8338 will fall here */
3139                 s->max_channels = 4;
3140                 s->capability |= CAN_DUAL_DAC;
3141                 s->capability |= CAN_LINE_AS_REAR;
3142         }
3143         /* enable SPDIF loop */
3144         set_spdif_loop(s, spdif_loop);
3145
3146         // enable 4 speaker mode (analog duplicate)
3147         set_hw_copy(s, hw_copy);
3148
3149         reg_mask = 0;
3150 #ifdef CONFIG_SOUND_CMPCI_FM
3151         /* disable FM */
3152         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3153         if (s->iosynth) {
3154             /* don't enable OPL3 if there is one */
3155             if (opl3_detect(s->iosynth, NULL)) {
3156                 s->iosynth = 0;
3157             } else {
3158                 /* set IO based at 0x388 */
3159                 switch (s->iosynth) {
3160                     case 0x388:
3161                         reg_mask = 0;
3162                         break;
3163                     case 0x3C8:
3164                         reg_mask = 0x01;
3165                         break;
3166                     case 0x3E0:
3167                         reg_mask = 0x02;
3168                         break;
3169                     case 0x3E8:
3170                         reg_mask = 0x03;
3171                         break;
3172                     default:
3173                         s->iosynth = 0;
3174                         break;
3175                 }
3176                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0x03, reg_mask);
3177                 /* enable FM */
3178                 if (s->iosynth) {
3179                         maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~0, 8);
3180                         if (opl3_detect(s->iosynth, NULL))
3181                                 ret = opl3_init(s->iosynth, NULL, THIS_MODULE);
3182                         else {
3183                                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3184                                 s->iosynth = 0;
3185                         }
3186                 }
3187             }
3188         }
3189 #endif
3190 #ifdef CONFIG_SOUND_CMPCI_MIDI
3191         /* disable MPU-401 */
3192         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x04, 0);
3193         s->mpu_data.name = "cmpci mpu";
3194         s->mpu_data.io_base = s->iomidi;
3195         s->mpu_data.irq = -s->irq;      // tell mpu401 to share irq
3196         if (probe_mpu401(&s->mpu_data))
3197                 s->iomidi = 0;
3198         if (s->iomidi) {
3199                 /* set IO based at 0x330 */
3200                 switch (s->iomidi) {
3201                     case 0x330:
3202                         reg_mask = 0;
3203                         break;
3204                     case 0x320:
3205                         reg_mask = 0x20;
3206                         break;
3207                     case 0x310:
3208                         reg_mask = 0x40;
3209                         break;
3210                     case 0x300:
3211                         reg_mask = 0x60;
3212                         break;
3213                     default:
3214                         s->iomidi = 0;
3215                         break;
3216                 }
3217                 maskb(s->iobase + CODEC_CMI_LEGACY_CTRL + 3, ~0x60, reg_mask);
3218                 /* enable MPU-401 */
3219                 if (s->iomidi) {
3220                         int timeout;
3221
3222                         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x04);
3223                         /* clear all previously received interrupt */
3224                         for (timeout = 900000; timeout > 0; timeout--) {
3225                                 if ((inb(s->iomidi + 1) && 0x80) == 0)
3226                                         inb(s->iomidi);
3227                                 else
3228                                         break;
3229                         }
3230                         if (!probe_mpu401(&s->mpu_data)) {
3231                                 s->iomidi = 0;
3232                                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x04);
3233                         } else {
3234                                 attach_mpu401(&s->mpu_data, THIS_MODULE);
3235                                 s->midi_devc = s->mpu_data.slots[1];
3236                         }
3237                 }
3238         }
3239 #endif
3240 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
3241         /* enable joystick */
3242         if (joystick) {
3243                 s->gameport.io = 0x200;
3244                 if (!request_region(s->gameport.io, CM_EXTENT_GAME, "cmpci GAME")) {
3245                         printk(KERN_ERR "cmpci: gameport io ports in use\n");
3246                         s->gameport.io = 0;
3247                 } else {
3248                         maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0, 0x02);
3249                         gameport_register_port(&s->gameport);
3250                 }
3251         } else {
3252                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x02, 0);
3253                 s->gameport.io = 0;
3254         }
3255 #endif
3256         /* store it in the driver field */
3257         pci_set_drvdata(pcidev, s);
3258         /* put it into driver list */
3259         list_add_tail(&s->devs, &devs);
3260         /* increment devindex */
3261         if (devindex < NR_DEVICE-1)
3262                 devindex++;
3263         return 0;
3264
3265 err_dev2:
3266         unregister_sound_dsp(s->dev_audio);
3267 err_dev1:
3268         printk(KERN_ERR "cmpci: cannot register misc device\n");
3269         free_irq(s->irq, s);
3270 err_irq:
3271         release_region(s->iobase, CM_EXTENT_CODEC);
3272 err_region5:
3273         kfree(s);
3274         return ret;
3275 }
3276
3277 /* --------------------------------------------------------------------- */
3278
3279 MODULE_AUTHOR("ChenLi Tien, cltien@cmedia.com.tw");
3280 MODULE_DESCRIPTION("CM8x38 Audio Driver");
3281 MODULE_LICENSE("GPL");
3282
3283 static void __devinit cm_remove(struct pci_dev *dev)
3284 {
3285         struct cm_state *s = pci_get_drvdata(dev);
3286
3287         if (!s)
3288                 return;
3289 #ifdef CONFIG_SOUND_CMPCI_JOYSTICK
3290         if (s->gameport.io) {
3291                 gameport_unregister_port(&s->gameport);
3292                 release_region(s->gameport.io, CM_EXTENT_GAME);
3293                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x02, 0);
3294         }
3295 #endif
3296 #ifdef CONFIG_SOUND_CMPCI_FM
3297         if (s->iosynth) {
3298                 /* disable FM */
3299                 maskb(s->iobase + CODEC_CMI_MISC_CTRL + 2, ~8, 0);
3300         }
3301 #endif
3302 #ifdef CONFIG_SOUND_CMPCI_MIDI
3303         if (s->iomidi) {
3304                 unload_mpu401(&s->mpu_data);
3305                 /* disable MPU-401 */
3306                 maskb(s->iobase + CODEC_CMI_FUNCTRL1, ~0x04, 0);
3307         }
3308 #endif
3309         set_spdif_loop(s, 0);
3310         list_del(&s->devs);
3311         outb(0, s->iobase + CODEC_CMI_INT_HLDCLR + 2);  /* disable ints */
3312         synchronize_irq(s->irq);
3313         outb(0, s->iobase + CODEC_CMI_FUNCTRL0 + 2); /* disable channels */
3314         free_irq(s->irq, s);
3315
3316         /* reset mixer */
3317         wrmixer(s, DSP_MIX_DATARESETIDX, 0);
3318
3319         release_region(s->iobase, CM_EXTENT_CODEC);
3320         unregister_sound_dsp(s->dev_audio);
3321         unregister_sound_mixer(s->dev_mixer);
3322         kfree(s);
3323         pci_set_drvdata(dev, NULL);
3324 }
3325
3326 static struct pci_device_id id_table[] __devinitdata = {
3327         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3328         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3329         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3330         { PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3331         { 0, }
3332 };
3333
3334 MODULE_DEVICE_TABLE(pci, id_table);
3335
3336 static struct pci_driver cm_driver = {
3337        .name     = "cmpci",
3338        .id_table = id_table,
3339        .probe    = cm_probe,
3340        .remove   = cm_remove
3341 };
3342
3343 static int __init init_cmpci(void)
3344 {
3345         printk(KERN_INFO "cmpci: version $Revision: 6.82 $ time " __TIME__ " " __DATE__ "\n");
3346         return pci_module_init(&cm_driver);
3347 }
3348
3349 static void __exit cleanup_cmpci(void)
3350 {
3351         printk(KERN_INFO "cmpci: unloading\n");
3352         pci_unregister_driver(&cm_driver);
3353 }
3354
3355 module_init(init_cmpci);
3356 module_exit(cleanup_cmpci);