sound/oss/cs4281/cs4281m.c

   1 /*******************************************************************************
   2 *
   3 *      "cs4281.c" --  Cirrus Logic-Crystal CS4281 linux audio driver.
   4 *
   5 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   6 *            -- adapted from drivers by Thomas Sailer,
   7 *            -- but don't bug him; Problems should go to:
   8 *            -- tom woller (twoller@crystal.cirrus.com) or
   9 *               (audio@crystal.cirrus.com).
  10 *
  11 *      This program is free software; you can redistribute it and/or modify
  12 *      it under the terms of the GNU General Public License as published by
  13 *      the Free Software Foundation; either version 2 of the License, or
  14 *      (at your option) any later version.
  15 *
  16 *      This program is distributed in the hope that it will be useful,
  17 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *      GNU General Public License for more details.
  20 *
  21 *      You should have received a copy of the GNU General Public License
  22 *      along with this program; if not, write to the Free Software
  23 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 * Module command line parameters:
  26 *   none
  27 *
  28 *  Supported devices:
  29 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  30 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  31 *  /dev/midi   simple MIDI UART interface, no ioctl
  32 *
  33 * Modification History
  34 * 08/20/00 trw - silence and no stopping DAC until release
  35 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  36 * 09/18/00 trw - added 16bit only record with conversion
  37 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  38 *                capture/playback rates)
  39 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  40 *                libOSSm.so)
  41 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  42 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  43 * 11/10/00 bkz - added __devinit to cs4281_hw_init()
  44 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  45 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  46 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  47 * 12/08/00 trw - added PM support.
  48 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  49 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  50 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  51 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  52 *                defaultorder-100 as power of 2 for the buffer size. example:
  53 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  54 *
  55 *******************************************************************************/
  56
  57 /* uncomment the following line to disable building PM support into the driver */
  58 //#define NOT_CS4281_PM 1
  59
  60 #include <linux/list.h>
  61 #include <linux/module.h>
  62 #include <linux/string.h>
  63 #include <linux/ioport.h>
  64 #include <linux/sched.h>
  65 #include <linux/delay.h>
  66 #include <linux/sound.h>
  67 #include <linux/slab.h>
  68 #include <linux/soundcard.h>
  69 #include <linux/pci.h>
  70 #include <linux/bitops.h>
  71 #include <linux/init.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/poll.h>
  74 #include <linux/fs.h>
  75 #include <linux/wait.h>
  76
  77 #include <asm/current.h>
  78 #include <asm/io.h>
  79 #include <asm/dma.h>
  80 #include <asm/page.h>
  81 #include <asm/uaccess.h>
  82
  83 //#include "cs_dm.h"
  84 #include "cs4281_hwdefs.h"
  85 #include "cs4281pm.h"
  86
  87 struct cs4281_state;
  88
  89 static void stop_dac(struct cs4281_state *s);
  90 static void stop_adc(struct cs4281_state *s);
  91 static void start_dac(struct cs4281_state *s);
  92 static void start_adc(struct cs4281_state *s);
  93 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  94
  95 // ---------------------------------------------------------------------
  96
  97 #ifndef PCI_VENDOR_ID_CIRRUS
  98 #define PCI_VENDOR_ID_CIRRUS          0x1013
  99 #endif
 100 #ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
 101 #define PCI_DEVICE_ID_CRYSTAL_CS4281  0x6005
 102 #endif
 103
 104 #define CS4281_MAGIC  ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
 105 #define CS4281_CFLR_DEFAULT     0x00000001  /* CFLR must be in AC97 link mode */
 106
 107 // buffer order determines the size of the dma buffer for the driver.
 108 // under Linux, a smaller buffer allows more responsiveness from many of the
 109 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 110 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 111 // rather than 64k as some of the games work more responsively.
 112 // log base 2( buff sz = 32k).
 113 static unsigned long defaultorder = 3;
 114 MODULE_PARM(defaultorder, "i");
 115
 116 //
 117 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 118 //
 119 #define CSDEBUG 1
 120 #if CSDEBUG
 121 #define CSDEBUG_INTERFACE 1
 122 #else
 123 #undef CSDEBUG_INTERFACE
 124 #endif
 125 //
 126 // cs_debugmask areas
 127 //
 128 #define CS_INIT         0x00000001      // initialization and probe functions
 129 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 130 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 131 #define CS_FUNCTION     0x00000008      // enter/leave functions
 132 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 133 #define CS_WAVE_READ    0x00000020      // read information for wave
 134 #define CS_MIDI_WRITE   0x00000040      // write information for midi
 135 #define CS_MIDI_READ    0x00000080      // read information for midi
 136 #define CS_MPU401_WRITE 0x00000100      // write information for mpu401
 137 #define CS_MPU401_READ  0x00000200      // read information for mpu401
 138 #define CS_OPEN         0x00000400      // all open functions in the driver
 139 #define CS_RELEASE      0x00000800      // all release functions in the driver
 140 #define CS_PARMS        0x00001000      // functional and operational parameters
 141 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 142 #define CS_PM           0x00004000      // power management
 143 #define CS_TMP          0x10000000      // tmp debug mask bit
 144
 145 #define CS_IOCTL_CMD_SUSPEND    0x1     // suspend
 146 #define CS_IOCTL_CMD_RESUME     0x2     // resume
 147 //
 148 // CSDEBUG is usual mode is set to 1, then use the
 149 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 150 // Debug level of 1 has been defined to be kernel errors and info
 151 // that should be printed on any released driver.
 152 //
 153 #if CSDEBUG
 154 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 155 #else
 156 #define CS_DBGOUT(mask,level,x)
 157 #endif
 158
 159 #if CSDEBUG
 160 static unsigned long cs_debuglevel = 1; // levels range from 1-9
 161 static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
 162 MODULE_PARM(cs_debuglevel, "i");
 163 MODULE_PARM(cs_debugmask, "i");
 164 #endif
 165 #define CS_TRUE         1
 166 #define CS_FALSE        0
 167
 168 // MIDI buffer sizes
 169 #define MIDIINBUF  500
 170 #define MIDIOUTBUF 500
 171
 172 #define FMODE_MIDI_SHIFT 3
 173 #define FMODE_MIDI_READ  (FMODE_READ << FMODE_MIDI_SHIFT)
 174 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
 175
 176 #define CS4281_MAJOR_VERSION    1
 177 #define CS4281_MINOR_VERSION    13
 178 #ifdef __ia64__
 179 #define CS4281_ARCH             64      //architecture key
 180 #else
 181 #define CS4281_ARCH             32      //architecture key
 182 #endif
 183
 184 #define CS_TYPE_ADC 0
 185 #define CS_TYPE_DAC 1
 186
 187
 188 static const char invalid_magic[] =
 189     KERN_CRIT "cs4281: invalid magic value\n";
 190
 191 #define VALIDATE_STATE(s)                         \
 192 ({                                                \
 193         if (!(s) || (s)->magic != CS4281_MAGIC) { \
 194                 printk(invalid_magic);            \
 195                 return -ENXIO;                    \
 196         }                                         \
 197 })
 198
 199 //LIST_HEAD(cs4281_devs);
 200 struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs };
 201
 202 struct cs4281_state;
 203
 204 #include "cs4281_wrapper-24.c"
 205
 206 struct cs4281_state {
 207         // magic
 208         unsigned int magic;
 209
 210         // we keep the cards in a linked list
 211         struct cs4281_state *next;
 212
 213         // pcidev is needed to turn off the DDMA controller at driver shutdown
 214         struct pci_dev *pcidev;
 215         struct list_head list;
 216
 217         // soundcore stuff
 218         int dev_audio;
 219         int dev_mixer;
 220         int dev_midi;
 221
 222         // hardware resources
 223         unsigned int pBA0phys, pBA1phys;
 224         char *pBA0, *pBA1;
 225         unsigned int irq;
 226
 227         // mixer registers
 228         struct {
 229                 unsigned short vol[10];
 230                 unsigned int recsrc;
 231                 unsigned int modcnt;
 232                 unsigned short micpreamp;
 233         } mix;
 234
 235         // wave stuff
 236         struct properties {
 237                 unsigned fmt;
 238                 unsigned fmt_original;  // original requested format
 239                 unsigned channels;
 240                 unsigned rate;
 241                 unsigned char clkdiv;
 242         } prop_dac, prop_adc;
 243         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 244         void *tmpbuff;          // tmp buffer for sample conversions
 245         unsigned ena;
 246         spinlock_t lock;
 247         struct semaphore open_sem;
 248         struct semaphore open_sem_adc;
 249         struct semaphore open_sem_dac;
 250         mode_t open_mode;
 251         wait_queue_head_t open_wait;
 252         wait_queue_head_t open_wait_adc;
 253         wait_queue_head_t open_wait_dac;
 254
 255         dma_addr_t dmaaddr_tmpbuff;
 256         unsigned buforder_tmpbuff;      // Log base 2 of 'rawbuf' size in bytes..
 257         struct dmabuf {
 258                 void *rawbuf;   // Physical address of
 259                 dma_addr_t dmaaddr;
 260                 unsigned buforder;      // Log base 2 of 'rawbuf' size in bytes..
 261                 unsigned numfrag;       // # of 'fragments' in the buffer.
 262                 unsigned fragshift;     // Log base 2 of fragment size.
 263                 unsigned hwptr, swptr;
 264                 unsigned total_bytes;   // # bytes process since open.
 265                 unsigned blocks;        // last returned blocks value GETOPTR
 266                 unsigned wakeup;        // interrupt occurred on block
 267                 int count;
 268                 unsigned underrun;      // underrun flag
 269                 unsigned error; // over/underrun
 270                 wait_queue_head_t wait;
 271                 // redundant, but makes calculations easier
 272                 unsigned fragsize;      // 2**fragshift..
 273                 unsigned dmasize;       // 2**buforder.
 274                 unsigned fragsamples;
 275                 // OSS stuff
 276                 unsigned mapped:1;      // Buffer mapped in cs4281_mmap()?
 277                 unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 278                 unsigned endcleared:1;
 279                 unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 280                 unsigned ossfragshift;
 281                 int ossmaxfrags;
 282                 unsigned subdivision;
 283         } dma_dac, dma_adc;
 284
 285         // midi stuff
 286         struct {
 287                 unsigned ird, iwr, icnt;
 288                 unsigned ord, owr, ocnt;
 289                 wait_queue_head_t iwait;
 290                 wait_queue_head_t owait;
 291                 struct timer_list timer;
 292                 unsigned char ibuf[MIDIINBUF];
 293                 unsigned char obuf[MIDIOUTBUF];
 294         } midi;
 295
 296         struct cs4281_pm pm;
 297         struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES];
 298 };
 299
 300 #include "cs4281pm-24.c"
 301
 302 #if CSDEBUG
 303
 304 // DEBUG ROUTINES
 305
 306 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 307 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 308 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 309 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 310
 311 #define SOUND_MIXER_CS_APM              _SIOWR('M',124, int)
 312
 313
 314 static void cs_printioctl(unsigned int x)
 315 {
 316         unsigned int i;
 317         unsigned char vidx;
 318         // Index of mixtable1[] member is Device ID
 319         // and must be <= SOUND_MIXER_NRDEVICES.
 320         // Value of array member is index into s->mix.vol[]
 321         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 322                 [SOUND_MIXER_PCM] = 1,  // voice
 323                 [SOUND_MIXER_LINE1] = 2,        // AUX
 324                 [SOUND_MIXER_CD] = 3,   // CD
 325                 [SOUND_MIXER_LINE] = 4, // Line
 326                 [SOUND_MIXER_SYNTH] = 5,        // FM
 327                 [SOUND_MIXER_MIC] = 6,  // Mic
 328                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 329                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 330                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 331         };
 332
 333         switch (x) {
 334         case SOUND_MIXER_CS_GETDBGMASK:
 335                 CS_DBGOUT(CS_IOCTL, 4,
 336                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 337                 break;
 338         case SOUND_MIXER_CS_GETDBGLEVEL:
 339                 CS_DBGOUT(CS_IOCTL, 4,
 340                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 341                 break;
 342         case SOUND_MIXER_CS_SETDBGMASK:
 343                 CS_DBGOUT(CS_IOCTL, 4,
 344                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 345                 break;
 346         case SOUND_MIXER_CS_SETDBGLEVEL:
 347                 CS_DBGOUT(CS_IOCTL, 4,
 348                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 349                 break;
 350         case OSS_GETVERSION:
 351                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 352                 break;
 353         case SNDCTL_DSP_SYNC:
 354                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 355                 break;
 356         case SNDCTL_DSP_SETDUPLEX:
 357                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 358                 break;
 359         case SNDCTL_DSP_GETCAPS:
 360                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 361                 break;
 362         case SNDCTL_DSP_RESET:
 363                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 364                 break;
 365         case SNDCTL_DSP_SPEED:
 366                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 367                 break;
 368         case SNDCTL_DSP_STEREO:
 369                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 370                 break;
 371         case SNDCTL_DSP_CHANNELS:
 372                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 373                 break;
 374         case SNDCTL_DSP_GETFMTS:
 375                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 376                 break;
 377         case SNDCTL_DSP_SETFMT:
 378                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 379                 break;
 380         case SNDCTL_DSP_POST:
 381                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 382                 break;
 383         case SNDCTL_DSP_GETTRIGGER:
 384                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 385                 break;
 386         case SNDCTL_DSP_SETTRIGGER:
 387                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 388                 break;
 389         case SNDCTL_DSP_GETOSPACE:
 390                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 391                 break;
 392         case SNDCTL_DSP_GETISPACE:
 393                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 394                 break;
 395         case SNDCTL_DSP_NONBLOCK:
 396                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 397                 break;
 398         case SNDCTL_DSP_GETODELAY:
 399                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 400                 break;
 401         case SNDCTL_DSP_GETIPTR:
 402                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 403                 break;
 404         case SNDCTL_DSP_GETOPTR:
 405                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 406                 break;
 407         case SNDCTL_DSP_GETBLKSIZE:
 408                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 409                 break;
 410         case SNDCTL_DSP_SETFRAGMENT:
 411                 CS_DBGOUT(CS_IOCTL, 4,
 412                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 413                 break;
 414         case SNDCTL_DSP_SUBDIVIDE:
 415                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 416                 break;
 417         case SOUND_PCM_READ_RATE:
 418                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 419                 break;
 420         case SOUND_PCM_READ_CHANNELS:
 421                 CS_DBGOUT(CS_IOCTL, 4,
 422                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 423                 break;
 424         case SOUND_PCM_READ_BITS:
 425                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 426                 break;
 427         case SOUND_PCM_WRITE_FILTER:
 428                 CS_DBGOUT(CS_IOCTL, 4,
 429                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 430                 break;
 431         case SNDCTL_DSP_SETSYNCRO:
 432                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 433                 break;
 434         case SOUND_PCM_READ_FILTER:
 435                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 436                 break;
 437         case SOUND_MIXER_PRIVATE1:
 438                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 439                 break;
 440         case SOUND_MIXER_PRIVATE2:
 441                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 442                 break;
 443         case SOUND_MIXER_PRIVATE3:
 444                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 445                 break;
 446         case SOUND_MIXER_PRIVATE4:
 447                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 448                 break;
 449         case SOUND_MIXER_PRIVATE5:
 450                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 451                 break;
 452         case SOUND_MIXER_INFO:
 453                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 454                 break;
 455         case SOUND_OLD_MIXER_INFO:
 456                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 457                 break;
 458
 459         default:
 460                 switch (_IOC_NR(x)) {
 461                 case SOUND_MIXER_VOLUME:
 462                         CS_DBGOUT(CS_IOCTL, 4,
 463                                   printk("SOUND_MIXER_VOLUME:\n"));
 464                         break;
 465                 case SOUND_MIXER_SPEAKER:
 466                         CS_DBGOUT(CS_IOCTL, 4,
 467                                   printk("SOUND_MIXER_SPEAKER:\n"));
 468                         break;
 469                 case SOUND_MIXER_RECLEV:
 470                         CS_DBGOUT(CS_IOCTL, 4,
 471                                   printk("SOUND_MIXER_RECLEV:\n"));
 472                         break;
 473                 case SOUND_MIXER_MIC:
 474                         CS_DBGOUT(CS_IOCTL, 4,
 475                                   printk("SOUND_MIXER_MIC:\n"));
 476                         break;
 477                 case SOUND_MIXER_SYNTH:
 478                         CS_DBGOUT(CS_IOCTL, 4,
 479                                   printk("SOUND_MIXER_SYNTH:\n"));
 480                         break;
 481                 case SOUND_MIXER_RECSRC:
 482                         CS_DBGOUT(CS_IOCTL, 4,
 483                                   printk("SOUND_MIXER_RECSRC:\n"));
 484                         break;
 485                 case SOUND_MIXER_DEVMASK:
 486                         CS_DBGOUT(CS_IOCTL, 4,
 487                                   printk("SOUND_MIXER_DEVMASK:\n"));
 488                         break;
 489                 case SOUND_MIXER_RECMASK:
 490                         CS_DBGOUT(CS_IOCTL, 4,
 491                                   printk("SOUND_MIXER_RECMASK:\n"));
 492                         break;
 493                 case SOUND_MIXER_STEREODEVS:
 494                         CS_DBGOUT(CS_IOCTL, 4,
 495                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 496                         break;
 497                 case SOUND_MIXER_CAPS:
 498                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 499                         break;
 500                 default:
 501                         i = _IOC_NR(x);
 502                         if (i >= SOUND_MIXER_NRDEVICES
 503                             || !(vidx = mixtable1[i])) {
 504                                 CS_DBGOUT(CS_IOCTL, 4, printk
 505                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 506                                                 x, i));
 507                         } else {
 508                                 CS_DBGOUT(CS_IOCTL, 4, printk
 509                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 510                                                 x, i));
 511                         }
 512                         break;
 513                 }
 514         }
 515 }
 516 #endif
 517 static int prog_dmabuf_adc(struct cs4281_state *s);
 518 static void prog_codec(struct cs4281_state *s, unsigned type);
 519
 520 // ---------------------------------------------------------------------
 521 //
 522 //              Hardware Interfaces For the CS4281
 523 //
 524
 525
 526 //******************************************************************************
 527 // "delayus()-- Delay for the specified # of microseconds.
 528 //******************************************************************************
 529 static void delayus(struct cs4281_state *s, u32 delay)
 530 {
 531         u32 j;
 532         if ((delay > 9999) && (s->pm.flags & CS4281_PM_IDLE)) {
 533                 j = (delay * HZ) / 1000000;     /* calculate delay in jiffies  */
 534                 if (j < 1)
 535                         j = 1;  /* minimum one jiffy. */
 536                 current->state = TASK_UNINTERRUPTIBLE;
 537                 schedule_timeout(j);
 538         } else
 539                 udelay(delay);
 540         return;
 541 }
 542
 543
 544 //******************************************************************************
 545 // "cs4281_read_ac97" -- Reads a word from the specified location in the
 546 //               CS4281's address space(based on the BA0 register).
 547 //
 548 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 549 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
 550 //                                            0h for reads.
 551 // 3. Write ACCTL = Control Register = 460h for initiating the write
 552 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 553 // 5. if DCV not cleared, break and return error
 554 // 6. Read ACSTS = Status Register = 464h, check VSTS bit
 555 //****************************************************************************
 556 static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
 557                             u32 * value)
 558 {
 559         u32 count, status;
 560
 561         // Make sure that there is not data sitting
 562         // around from a previous uncompleted access.
 563         // ACSDA = Status Data Register = 47Ch
 564         status = readl(card->pBA0 + BA0_ACSDA);
 565
 566         // Setup the AC97 control registers on the CS4281 to send the
 567         // appropriate command to the AC97 to perform the read.
 568         // ACCAD = Command Address Register = 46Ch
 569         // ACCDA = Command Data Register = 470h
 570         // ACCTL = Control Register = 460h
 571         // bit DCV - will clear when process completed
 572         // bit CRW - Read command
 573         // bit VFRM - valid frame enabled
 574         // bit ESYN - ASYNC generation enabled
 575
 576         // Get the actual AC97 register from the offset
 577         writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
 578         writel(0, card->pBA0 + BA0_ACCDA);
 579         writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
 580                card->pBA0 + BA0_ACCTL);
 581
 582         // Wait for the read to occur.
 583         for (count = 0; count < 10; count++) {
 584                 // First, we want to wait for a short time.
 585                 udelay(25);
 586
 587                 // Now, check to see if the read has completed.
 588                 // ACCTL = 460h, DCV should be reset by now and 460h = 17h
 589                 if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
 590                         break;
 591         }
 592
 593         // Make sure the read completed.
 594         if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
 595                 return 1;
 596
 597         // Wait for the valid status bit to go active.
 598         for (count = 0; count < 10; count++) {
 599                 // Read the AC97 status register.
 600                 // ACSTS = Status Register = 464h
 601                 status = readl(card->pBA0 + BA0_ACSTS);
 602
 603                 // See if we have valid status.
 604                 // VSTS - Valid Status
 605                 if (status & ACSTS_VSTS)
 606                         break;
 607                 // Wait for a short while.
 608                 udelay(25);
 609         }
 610
 611         // Make sure we got valid status.
 612         if (!(status & ACSTS_VSTS))
 613                 return 1;
 614
 615         // Read the data returned from the AC97 register.
 616         // ACSDA = Status Data Register = 474h
 617         *value = readl(card->pBA0 + BA0_ACSDA);
 618
 619         // Success.
 620         return (0);
 621 }
 622
 623
 624 //****************************************************************************
 625 //
 626 // "cs4281_write_ac97()"-- writes a word to the specified location in the
 627 // CS461x's address space (based on the part's base address zero register).
 628 //
 629 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 630 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
 631 // 3. Write ACCTL = Control Register = 460h for initiating the write
 632 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 633 // 5. if DCV not cleared, break and return error
 634 //
 635 //****************************************************************************
 636 static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
 637                              u32 value)
 638 {
 639         u32 count, status=0;
 640
 641         CS_DBGOUT(CS_FUNCTION, 2,
 642                   printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n"));
 643
 644         // Setup the AC97 control registers on the CS4281 to send the
 645         // appropriate command to the AC97 to perform the read.
 646         // ACCAD = Command Address Register = 46Ch
 647         // ACCDA = Command Data Register = 470h
 648         // ACCTL = Control Register = 460h
 649         // set DCV - will clear when process completed
 650         // reset CRW - Write command
 651         // set VFRM - valid frame enabled
 652         // set ESYN - ASYNC generation enabled
 653         // set RSTN - ARST# inactive, AC97 codec not reset
 654
 655         // Get the actual AC97 register from the offset
 656
 657         writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
 658         writel(value, card->pBA0 + BA0_ACCDA);
 659         writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
 660                card->pBA0 + BA0_ACCTL);
 661
 662         // Wait for the write to occur.
 663         for (count = 0; count < 100; count++) {
 664                 // First, we want to wait for a short time.
 665                 udelay(25);
 666                 // Now, check to see if the write has completed.
 667                 // ACCTL = 460h, DCV should be reset by now and 460h = 07h
 668                 status = readl(card->pBA0 + BA0_ACCTL);
 669                 if (!(status & ACCTL_DCV))
 670                         break;
 671         }
 672
 673         // Make sure the write completed.
 674         if (status & ACCTL_DCV) {
 675                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
 676                         "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n"));
 677                 return 1;
 678         }
 679         CS_DBGOUT(CS_FUNCTION, 2,
 680                   printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n"));
 681         // Success.
 682         return 0;
 683 }
 684
 685
 686 //******************************************************************************
 687 // "Init4281()" -- Bring up the part.
 688 //******************************************************************************
 689 static __devinit int cs4281_hw_init(struct cs4281_state *card)
 690 {
 691         u32 ac97_slotid;
 692         u32 temp1, temp2;
 693
 694         CS_DBGOUT(CS_FUNCTION, 2,
 695                   printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n"));
 696 #ifndef NOT_CS4281_PM
 697         if(!card)
 698                 return 1;
 699 #endif
 700         temp2 = readl(card->pBA0 + BA0_CFLR);
 701         CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO
 702                 "cs4281: cs4281_hw_init() CFLR 0x%x\n", temp2));
 703         if(temp2 != CS4281_CFLR_DEFAULT)
 704         {
 705                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
 706                         "cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%x\n",
 707                                 temp2,CS4281_CFLR_DEFAULT));
 708                 writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR);
 709                 temp2 = readl(card->pBA0 + BA0_CFLR);
 710                 if(temp2 != CS4281_CFLR_DEFAULT)
 711                 {
 712                         CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
 713                                 "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR\n"));
 714                         return 1;
 715                 }
 716         }
 717
 718         //***************************************7
 719         //  Set up the Sound System Configuration
 720         //***************************************
 721
 722         // Set the 'Configuration Write Protect' register
 723         // to 4281h.  Allows vendor-defined configuration
 724         // space between 0e4h and 0ffh to be written.
 725
 726         writel(0x4281, card->pBA0 + BA0_CWPR);  // (3e0h)
 727
 728         // (0), Blast the clock control register to zero so that the
 729         // PLL starts out in a known state, and blast the master serial
 730         // port control register to zero so that the serial ports also
 731         // start out in a known state.
 732
 733         writel(0, card->pBA0 + BA0_CLKCR1);     // (400h)
 734         writel(0, card->pBA0 + BA0_SERMC);      // (420h)
 735
 736
 737         // (1), Make ESYN go to zero to turn off
 738         // the Sync pulse on the AC97 link.
 739
 740         writel(0, card->pBA0 + BA0_ACCTL);
 741         udelay(50);
 742
 743
 744         // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
 745         // the AC97 spec) and then drive it high.  This is done for non
 746         // AC97 modes since there might be logic external to the CS461x
 747         // that uses the ARST# line for a reset.
 748
 749         writel(0, card->pBA0 + BA0_SPMC);       // (3ech)
 750         udelay(100);
 751         writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
 752         delayus(card,50000);            // Wait 50 ms for ABITCLK to become stable.
 753
 754         // (3) Turn on the Sound System Clocks.
 755         writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1);   // (400h)
 756         delayus(card,50000);            // Wait for the PLL to stabilize.
 757         // Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
 758         writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
 759
 760         // (4) Power on everything for now..
 761         writel(0x7E, card->pBA0 + BA0_SSPM);    // (740h)
 762
 763         // (5) Wait for clock stabilization.
 764         for (temp1 = 0; temp1 < 1000; temp1++) {
 765                 udelay(1000);
 766                 if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
 767                         break;
 768         }
 769         if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
 770                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
 771                         "cs4281: DLLRDY failed!\n"));
 772                 return -EIO;
 773         }
 774         // (6) Enable ASYNC generation.
 775         writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL);     // (460h)
 776
 777         // Now wait 'for a short while' to allow the  AC97
 778         // part to start generating bit clock. (so we don't
 779         // Try to start the PLL without an input clock.)
 780         delayus(card,50000);
 781
 782         // Set the serial port timing configuration, so that the
 783         // clock control circuit gets its clock from the right place.
 784         writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
 785
 786         // (7) Wait for the codec ready signal from the AC97 codec.
 787
 788         for (temp1 = 0; temp1 < 1000; temp1++) {
 789                 // Delay a mil to let things settle out and
 790                 // to prevent retrying the read too quickly.
 791                 udelay(1000);
 792                 if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready,  (464h)
 793                         break;  //   exit the 'for' loop.
 794         }
 795         if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY))      // If never came ready,
 796         {
 797                 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
 798                          "cs4281: ACSTS never came ready!\n"));
 799                 return -EIO;    //   exit initialization.
 800         }
 801         // (8) Assert the 'valid frame' signal so we can
 802         // begin sending commands to the AC97 codec.
 803         writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL);        // (460h)
 804
 805         // (9), Wait until CODEC calibration is finished.
 806         // Print an error message if it doesn't.
 807         for (temp1 = 0; temp1 < 1000; temp1++) {
 808                 delayus(card,10000);
 809                 // Read the AC97 Powerdown Control/Status Register.
 810                 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
 811                 if ((temp2 & 0x0000000F) == 0x0000000F)
 812                         break;
 813         }
 814         if ((temp2 & 0x0000000F) != 0x0000000F) {
 815                 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
 816                         "cs4281: Codec failed to calibrate.  Status = %.8x.\n",
 817                                 temp2));
 818                 return -EIO;
 819         }
 820         // (10), Set the serial port timing configuration, so that the
 821         // clock control circuit gets its clock from the right place.
 822         writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
 823
 824
 825         // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
 826         // that the codec is pumping ADC data across the AC link.
 827         for (temp1 = 0; temp1 < 1000; temp1++) {
 828                 // Delay a mil to let things settle out and
 829                 // to prevent retrying the read too quickly.
 830                 delayus(card,1000);     //(test)
 831
 832                 // Read the input slot valid register;  See
 833                 // if input slots 3 and 4 are valid yet.
 834                 if (
 835                     (readl(card->pBA0 + BA0_ACISV) &
 836                      (ACISV_ISV3 | ACISV_ISV4)) ==
 837                     (ACISV_ISV3 | ACISV_ISV4)) break;   // Exit the 'for' if slots are valid.
 838         }
 839         // If we never got valid data, exit initialization.
 840         if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
 841             != (ACISV_ISV3 | ACISV_ISV4)) {
 842                 CS_DBGOUT(CS_FUNCTION, 2,
 843                           printk(KERN_ERR
 844                                  "cs4281: Never got valid data!\n"));
 845                 return -EIO;    // If no valid data, exit initialization.
 846         }
 847         // (12), Start digital data transfer of audio data to the codec.
 848         writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV);        // (468h)
 849
 850
 851         //**************************************
 852         // Unmute the Master and Alternate
 853         // (headphone) volumes.  Set to max.
 854         //**************************************
 855         cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
 856         cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
 857
 858         //******************************************
 859         // Power on the DAC(AddDACUser()from main())
 860         //******************************************
 861         cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 862         cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
 863
 864         // Wait until we sample a DAC ready state.
 865         for (temp2 = 0; temp2 < 32; temp2++) {
 866                 // Let's wait a mil to let things settle.
 867                 delayus(card,1000);
 868                 // Read the current state of the power control reg.
 869                 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 870                 // If the DAC ready state bit is set, stop waiting.
 871                 if (temp1 & 0x2)
 872                         break;
 873         }
 874
 875         //******************************************
 876         // Power on the ADC(AddADCUser()from main())
 877         //******************************************
 878         cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 879         cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
 880
 881         // Wait until we sample ADC ready state.
 882         for (temp2 = 0; temp2 < 32; temp2++) {
 883                 // Let's wait a mil to let things settle.
 884                 delayus(card,1000);
 885                 // Read the current state of the power control reg.
 886                 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 887                 // If the ADC ready state bit is set, stop waiting.
 888                 if (temp1 & 0x1)
 889                         break;
 890         }
 891         // Set up 4281 Register contents that
 892         // don't change for boot duration.
 893
 894         // For playback, we map AC97 slot 3 and 4(Left
 895         // & Right PCM playback) to DMA Channel 0.
 896         // Set the fifo to be 15 bytes at offset zero.
 897
 898         ac97_slotid = 0x01000f00;       // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
 899         // FCR0.LS[4:0]=0(=>slot3, left PCM playback).
 900         // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
 901         writel(ac97_slotid, card->pBA0 + BA0_FCR0);     // (180h)
 902         writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0);  // Turn on FIFO Enable.
 903
 904         // For capture, we map AC97 slot 10 and 11(Left
 905         // and Right PCM Record) to DMA Channel 1.
 906         // Set the fifo to be 15 bytes at offset sixteen.
 907         ac97_slotid = 0x0B0A0f10;       // FCR1.RS[4:0]=11(=>slot11, right PCM record).
 908         // FCR1.LS[4:0]=10(=>slot10, left PCM record).
 909         // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
 910         writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1);  // (184h)
 911         writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1);  // Turn on FIFO Enable.
 912
 913         // Map the Playback SRC to the same AC97 slots(3 & 4--
 914         // --Playback left & right)as DMA channel 0.
 915         // Map the record SRC to the same AC97 slots(10 & 11--
 916         // -- Record left & right) as DMA channel 1.
 917
 918         ac97_slotid = 0x0b0a0100;       // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
 919         // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
 920         // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
 921         // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
 922         writel(ac97_slotid, card->pBA0 + BA0_SRCSA);    // (75ch)
 923
 924         // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
 925         // Count Interrupt Enable' in DMA Control Registers 0 & 1.
 926         // Set 'MSK' flag to 1 to keep the DMA engines paused.
 927         temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK);    // (00030001h)
 928         writel(temp1, card->pBA0 + BA0_DCR0);   // (154h
 929         writel(temp1, card->pBA0 + BA0_DCR1);   // (15ch)
 930
 931         // Set 'Auto-Initialize Control' to 'enabled'; For playback,
 932         // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
 933         // for record, set Transfer Type Control to 'write transfer'.
 934         // All other bits set to zero;  Some will be changed @ transfer start.
 935         temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ);  // (20000018h)
 936         writel(temp1, card->pBA0 + BA0_DMR0);   // (150h)
 937         temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
 938         writel(temp1, card->pBA0 + BA0_DMR1);   // (158h)
 939
 940         // Enable DMA interrupts generally, and
 941         // DMA0 & DMA1 interrupts specifically.
 942         temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
 943         writel(temp1, card->pBA0 + BA0_HIMR);
 944
 945         CS_DBGOUT(CS_FUNCTION, 2,
 946                   printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n"));
 947         return 0;
 948 }
 949
 950 #ifndef NOT_CS4281_PM
 951 static void printpm(struct cs4281_state *s)
 952 {
 953         CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
 954         CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%x\n",
 955                 (unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue));
 956         CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%x\n",
 957                 s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue));
 958         CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%x\n",
 959                 s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue));
 960         CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%x\n",
 961                 s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue));
 962         CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%x\n",
 963                 s->pm.u32SSCR,s->pm.u32SRCSA));
 964         CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%x\n",
 965                 s->pm.u32DacASR,s->pm.u32AdcASR));
 966         CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%x\n",
 967                 s->pm.u32DacSR,s->pm.u32AdcSR));
 968         CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%x\n",
 969                 s->pm.u32MIDCR_Save));
 970
 971 }
 972 static void printpipe(struct cs4281_pipeline *pl)
 973 {
 974
 975         CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
 976         CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%x\n",
 977                 (unsigned)pl->flags,pl->number));
 978         CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%x\n",
 979                 pl->u32DBAnValue,pl->u32DBCnValue));
 980         CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%x\n",
 981                 pl->u32DMRnValue,pl->u32DCRnValue));
 982         CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%x\n",
 983                 pl->u32DBAnAddress,pl->u32DBCnAddress));
 984         CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%x\n",
 985                 pl->u32DCCnAddress,pl->u32DCCnAddress));
 986         CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%x\n",
 987                 pl->u32DMRnAddress,pl->u32DCRnAddress));
 988         CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%x\n",
 989                 pl->u32HDSRnAddress,pl->u32DBAn_Save));
 990         CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%x\n",
 991                 pl->u32DBCn_Save,pl->u32DMRn_Save));
 992         CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%x\n",
 993                 pl->u32DCRn_Save,pl->u32DCCn_Save));
 994         CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%x\n",
 995                 pl->u32DCAn_Save));
 996         CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%x\n",
 997                 pl->u32FCRn_Save,pl->u32FSICn_Save));
 998         CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%x\n",
 999                 pl->u32FCRnValue,pl->u32FSICnValue));
1000         CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%x\n",
1001                 pl->u32FCRnAddress,pl->u32FSICnAddress));
1002         CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%x\n",
1003                 pl->u32FPDRnValue,pl->u32FPDRnAddress));
1004 }
1005 static void printpipelines(struct cs4281_state *s)
1006 {
1007         int i;
1008         for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
1009         {
1010                 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1011                 {
1012                         printpipe(&s->pl[i]);
1013                 }
1014         }
1015 }
1016 /****************************************************************************
1017 *
1018 *  Suspend - save the ac97 regs, mute the outputs and power down the part.
1019 *
1020 ****************************************************************************/
1021 void cs4281_ac97_suspend(struct cs4281_state *s)
1022 {
1023         int Count,i;
1024
1025         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+\n"));
1026 /*
1027 * change the state, save the current hwptr, then stop the dac/adc
1028 */
1029         s->pm.flags &= ~CS4281_PM_IDLE;
1030         s->pm.flags |= CS4281_PM_SUSPENDING;
1031         s->pm.u32hwptr_playback = readl(s->pBA0 + BA0_DCA0);
1032         s->pm.u32hwptr_capture = readl(s->pBA0 + BA0_DCA1);
1033         stop_dac(s);
1034         stop_adc(s);
1035
1036         for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1037                         && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1038                 Count += 2, i++)
1039         {
1040                 cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]);
1041         }
1042 /*
1043 * Save the ac97 volume registers as well as the current powerdown state.
1044 * Now, mute the all the outputs (master, headphone, and mono), as well
1045 * as the PCM volume, in preparation for powering down the entire part.
1046 */
1047         cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume);
1048         cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume);
1049         cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono);
1050         cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume);
1051
1052         cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000);
1053         cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000);
1054         cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000);
1055         cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000);
1056
1057         cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown);
1058         cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose);
1059
1060 /*
1061 * And power down everything on the AC97 codec.
1062 */
1063         cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00);
1064         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-\n"));
1065 }
1066
1067 /****************************************************************************
1068 *
1069 *  Resume - power up the part and restore its registers..
1070 *
1071 ****************************************************************************/
1072 void cs4281_ac97_resume(struct cs4281_state *s)
1073 {
1074         int Count,i;
1075
1076         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+\n"));
1077
1078 /* do not save the power state registers at this time
1079     //
1080     // If we saved away the power control registers, write them into the
1081     // shadows so those saved values get restored instead of the current
1082     // shadowed value.
1083     //
1084     if( bPowerStateSaved )
1085     {
1086         PokeShadow( 0x26, ulSaveReg0x26 );
1087         bPowerStateSaved = FALSE;
1088     }
1089 */
1090
1091 //
1092 // First, we restore the state of the general purpose register.  This
1093 // contains the mic select (mic1 or mic2) and if we restore this after
1094 // we restore the mic volume/boost state and mic2 was selected at
1095 // suspend time, we will end up with a brief period of time where mic1
1096 // is selected with the volume/boost settings for mic2, causing
1097 // acoustic feedback.  So we restore the general purpose register
1098 // first, thereby getting the correct mic selected before we restore
1099 // the mic volume/boost.
1100 //
1101         cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose);
1102
1103 //
1104 // Now, while the outputs are still muted, restore the state of power
1105 // on the AC97 part.
1106 //
1107         cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown);
1108
1109 /*
1110 * Restore just the first set of registers, from register number
1111 * 0x02 to the register number that ulHighestRegToRestore specifies.
1112 */
1113         for(    Count = 0x2, i=0;
1114                 (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1115                         && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1116                 Count += 2, i++)
1117         {
1118                 cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]);
1119         }
1120         CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-\n"));
1121 }
1122
1123 /* do not save the power state registers at this time
1124 ****************************************************************************
1125 *
1126 *  SavePowerState - Save the power registers away.
1127 *
1128 ****************************************************************************
1129 void
1130 HWAC97codec::SavePowerState(void)
1131 {
1132     ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()\r\n");
1133
1134     ulSaveReg0x26 = PeekShadow(0x26);
1135
1136     //
1137     // Note that we have saved registers that need to be restored during a
1138     // resume instead of ulAC97Regs[].
1139     //
1140     bPowerStateSaved = TRUE;
1141
1142 } // SavePowerState
1143 */
1144
1145 void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1146 {
1147  /*
1148  * We need to save the contents of the BASIC FIFO Registers.
1149  */
1150         pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress);
1151         pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress);
1152 }
1153 void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1154 {
1155  /*
1156  * We need to restore the contents of the BASIC FIFO Registers.
1157  */
1158         writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress);
1159         writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress);
1160 }
1161 void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1162 {
1163         //
1164         // We need to save the contents of the BASIC DMA Registers.
1165         //
1166         pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress);
1167         pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress);
1168         pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress);
1169         pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress);
1170         pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress);
1171         pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress);
1172 }
1173 void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1174 {
1175         //
1176         // We need to save the contents of the BASIC DMA Registers.
1177         //
1178         writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress);
1179         writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress);
1180         writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress);
1181         writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress);
1182         writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress);
1183         writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress);
1184 }
1185
1186 int cs4281_suspend(struct cs4281_state *s)
1187 {
1188         int i;
1189         u32 u32CLKCR1;
1190         struct cs4281_pm *pm = &s->pm;
1191         CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1192                 printk("cs4281: cs4281_suspend()+ flags=%d\n",
1193                         (unsigned)s->pm.flags));
1194 /*
1195 * check the current state, only suspend if IDLE
1196 */
1197         if(!(s->pm.flags & CS4281_PM_IDLE))
1198         {
1199                 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1200                         printk("cs4281: cs4281_suspend() unable to suspend, not IDLE\n"));
1201                 return 1;
1202         }
1203         s->pm.flags &= ~CS4281_PM_IDLE;
1204         s->pm.flags |= CS4281_PM_SUSPENDING;
1205
1206 //
1207 // Gershwin CLKRUN - Set CKRA
1208 //
1209         u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1210
1211         pm->u32CLKCR1_SAVE = u32CLKCR1;
1212         if(!(u32CLKCR1 & 0x00010000 ) )
1213                 writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1214
1215 //
1216 // First, turn on the clocks (yikes) to the devices, so that they will
1217 // respond when we try to save their state.
1218 //
1219         if(!(u32CLKCR1 & CLKCR1_SWCE))
1220         {
1221                 writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1);
1222         }
1223
1224         //
1225         // Save the power state
1226         //
1227         pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM);
1228
1229         //
1230         // Disable interrupts.
1231         //
1232         writel(HICR_CHGM, s->pBA0 + BA0_HICR);
1233
1234         //
1235         // Save the PCM Playback Left and Right Volume Control.
1236         //
1237         pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC);
1238         pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC);
1239
1240         //
1241         // Save the FM Synthesis Left and Right Volume Control.
1242         //
1243         pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC);
1244         pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC);
1245
1246         //
1247         // Save the GPIOR value.
1248         //
1249         pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR);
1250
1251         //
1252         // Save the JSCTL value.
1253         //
1254         pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR);
1255
1256         //
1257         // Save Sound System Control Register
1258         //
1259         pm->u32SSCR = readl(s->pBA0 + BA0_SSCR);
1260
1261         //
1262         // Save SRC Slot Assinment register
1263         //
1264         pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA);
1265
1266         //
1267         // Save sample rate
1268         //
1269         pm->u32DacASR = readl(s->pBA0 + BA0_PASR);
1270         pm->u32AdcASR = readl(s->pBA0 + BA0_CASR);
1271         pm->u32DacSR = readl(s->pBA0 + BA0_DACSR);
1272         pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR);
1273
1274         //
1275         // Loop through all of the PipeLines
1276         //
1277         for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1278         {
1279                 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1280                 {
1281                 //
1282                 // Ask the DMAengines and FIFOs to Suspend.
1283                 //
1284                         cs4281_SuspendDMAengine(s,&s->pl[i]);
1285                         cs4281_SuspendFIFO(s,&s->pl[i]);
1286                 }
1287         }
1288         //
1289         // We need to save the contents of the Midi Control Register.
1290         //
1291         pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR);
1292 /*
1293 * save off the AC97 part information
1294 */
1295         cs4281_ac97_suspend(s);
1296
1297         //
1298         // Turn off the serial ports.
1299         //
1300         writel(0, s->pBA0 + BA0_SERMC);
1301
1302         //
1303         // Power off FM, Joystick, AC link,
1304         //
1305         writel(0, s->pBA0 + BA0_SSPM);
1306
1307         //
1308         // DLL off.
1309         //
1310         writel(0, s->pBA0 + BA0_CLKCR1);
1311
1312         //
1313         // AC link off.
1314         //
1315         writel(0, s->pBA0 + BA0_SPMC);
1316
1317         //
1318         // Put the chip into D3(hot) state.
1319         //
1320         // PokeBA0(BA0_PMCS, 0x00000003);
1321
1322         //
1323         // Gershwin CLKRUN - Clear CKRA
1324         //
1325         u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1326         writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1);
1327
1328 #ifdef CSDEBUG
1329         printpm(s);
1330         printpipelines(s);
1331 #endif
1332
1333         s->pm.flags &= ~CS4281_PM_SUSPENDING;
1334         s->pm.flags |= CS4281_PM_SUSPENDED;
1335
1336         CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1337                 printk("cs4281: cs4281_suspend()- flags=%d\n",
1338                         (unsigned)s->pm.flags));
1339         return 0;
1340 }
1341
1342 int cs4281_resume(struct cs4281_state *s)
1343 {
1344         int i;
1345         unsigned temp1;
1346         u32 u32CLKCR1;
1347         struct cs4281_pm *pm = &s->pm;
1348         CS_DBGOUT(CS_PM | CS_FUNCTION, 4,
1349                 printk( "cs4281: cs4281_resume()+ flags=%d\n",
1350                         (unsigned)s->pm.flags));
1351         if(!(s->pm.flags & CS4281_PM_SUSPENDED))
1352         {
1353                 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1354                         printk("cs4281: cs4281_resume() unable to resume, not SUSPENDED\n"));
1355                 return 1;
1356         }
1357         s->pm.flags &= ~CS4281_PM_SUSPENDED;
1358         s->pm.flags |= CS4281_PM_RESUMING;
1359
1360 //
1361 // Gershwin CLKRUN - Set CKRA
1362 //
1363         u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1364         writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1365
1366         //
1367         // set the power state.
1368         //
1369         //old PokeBA0(BA0_PMCS, 0);
1370
1371         //
1372         // Program the clock circuit and serial ports.
1373         //
1374         temp1 = cs4281_hw_init(s);
1375         if (temp1) {
1376                 CS_DBGOUT(CS_ERROR | CS_INIT, 1,
1377                     printk(KERN_ERR
1378                         "cs4281: resume cs4281_hw_init() error.\n"));
1379                 return -1;
1380         }
1381
1382         //
1383         // restore the Power state
1384         //
1385         writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM);
1386
1387         //
1388         // Set post SRC mix setting (FM or ALT48K)
1389         //
1390         writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM);
1391
1392         //
1393         // Loop through all of the PipeLines
1394         //
1395         for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1396         {
1397                 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1398                 {
1399                 //
1400                 // Ask the DMAengines and FIFOs to Resume.
1401                 //
1402                         cs4281_ResumeDMAengine(s,&s->pl[i]);
1403                         cs4281_ResumeFIFO(s,&s->pl[i]);
1404                 }
1405         }
1406         //
1407         // We need to restore the contents of the Midi Control Register.
1408         //
1409         writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR);
1410
1411         cs4281_ac97_resume(s);
1412         //
1413         // Restore the PCM Playback Left and Right Volume Control.
1414         //
1415         writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC);
1416         writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC);
1417
1418         //
1419         // Restore the FM Synthesis Left and Right Volume Control.
1420         //
1421         writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC);
1422         writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC);
1423
1424         //
1425         // Restore the JSCTL value.
1426         //
1427         writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL);
1428
1429         //
1430         // Restore the GPIOR register value.
1431         //
1432         writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR);
1433
1434         //
1435         // Restore Sound System Control Register
1436         //
1437         writel(pm->u32SSCR, s->pBA0 + BA0_SSCR);
1438
1439         //
1440         // Restore SRC Slot Assignment register
1441         //
1442         writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA);
1443
1444         //
1445         // Restore sample rate
1446         //
1447         writel(pm->u32DacASR, s->pBA0 + BA0_PASR);
1448         writel(pm->u32AdcASR, s->pBA0 + BA0_CASR);
1449         writel(pm->u32DacSR, s->pBA0 + BA0_DACSR);
1450         writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR);
1451
1452         //
1453         // Restore CFL1/2 registers we saved to compensate for OEM bugs.
1454         //
1455         //      PokeBA0(BA0_CFLR, ulConfig);
1456
1457         //
1458         // Gershwin CLKRUN - Clear CKRA
1459         //
1460         writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1);
1461
1462         //
1463         // Enable interrupts on the part.
1464         //
1465         writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
1466
1467 #ifdef CSDEBUG
1468         printpm(s);
1469         printpipelines(s);
1470 #endif
1471 /*
1472 * change the state, restore the current hwptrs, then stop the dac/adc
1473 */
1474         s->pm.flags |= CS4281_PM_IDLE;
1475         s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED
1476                         | CS4281_PM_RESUMING | CS4281_PM_RESUMED);
1477
1478         writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0);
1479         writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1);
1480         start_dac(s);
1481         start_adc(s);
1482
1483         CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%d\n",
1484                 (unsigned)s->pm.flags));
1485         return 0;
1486 }
1487
1488 #endif
1489
1490 //******************************************************************************
1491 // "cs4281_play_rate()" --
1492 //******************************************************************************
1493 static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
1494 {
1495         u32 DACSRvalue = 1;
1496
1497         // Based on the sample rate, program the DACSR register.
1498         if (playrate == 8000)
1499                 DACSRvalue = 5;
1500         if (playrate == 11025)
1501                 DACSRvalue = 4;
1502         else if (playrate == 22050)
1503                 DACSRvalue = 2;
1504         else if (playrate == 44100)
1505                 DACSRvalue = 1;
1506         else if ((playrate <= 48000) && (playrate >= 6023))
1507                 DACSRvalue = 24576000 / (playrate * 16);
1508         else if (playrate < 6023)
1509                 // Not allowed by open.
1510                 return;
1511         else if (playrate > 48000)
1512                 // Not allowed by open.
1513                 return;
1514         CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
1515                 "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n",
1516                         DACSRvalue, playrate));
1517         //  Write the 'sample rate select code'
1518         //  to the 'DAC Sample Rate' register.
1519         writel(DACSRvalue, card->pBA0 + BA0_DACSR);     // (744h)
1520 }
1521
1522 //******************************************************************************
1523 // "cs4281_record_rate()" -- Initialize the record sample rate converter.
1524 //******************************************************************************
1525 static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
1526 {
1527         u32 ADCSRvalue = 1;
1528
1529         //
1530         // Based on the sample rate, program the ADCSR register
1531         //
1532         if (outrate == 8000)
1533                 ADCSRvalue = 5;
1534         if (outrate == 11025)
1535                 ADCSRvalue = 4;
1536         else if (outrate == 22050)
1537                 ADCSRvalue = 2;
1538         else if (outrate == 44100)
1539                 ADCSRvalue = 1;
1540         else if ((outrate <= 48000) && (outrate >= 6023))
1541                 ADCSRvalue = 24576000 / (outrate * 16);
1542         else if (outrate < 6023) {
1543                 // Not allowed by open.
1544                 return;
1545         } else if (outrate > 48000) {
1546                 // Not allowed by open.
1547                 return;
1548         }
1549         CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
1550                 "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n",
1551                         ADCSRvalue, outrate));
1552         //  Write the 'sample rate select code
1553         //  to the 'ADC Sample Rate' register.
1554         writel(ADCSRvalue, card->pBA0 + BA0_ADCSR);     // (748h)
1555 }
1556
1557
1558
1559 static void stop_dac(struct cs4281_state *s)
1560 {
1561         unsigned long flags;
1562         unsigned temp1;
1563
1564         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():\n"));
1565         spin_lock_irqsave(&s->lock, flags);
1566         s->ena &= ~FMODE_WRITE;
1567         temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
1568         writel(temp1, s->pBA0 + BA0_DCR0);
1569
1570         spin_unlock_irqrestore(&s->lock, flags);
1571 }
1572
1573
1574 static void start_dac(struct cs4281_state *s)
1575 {
1576         unsigned long flags;
1577         unsigned temp1;
1578
1579         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+\n"));
1580         spin_lock_irqsave(&s->lock, flags);
1581         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
1582                                         (s->dma_dac.count > 0
1583                                         && s->dma_dac.ready))
1584 #ifndef NOT_CS4281_PM
1585         && (s->pm.flags & CS4281_PM_IDLE))
1586 #else
1587 )
1588 #endif
1589  {
1590                 s->ena |= FMODE_WRITE;
1591                 temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK;  // Clear DMA0 channel mask.
1592                 writel(temp1, s->pBA0 + BA0_DCR0);      // Start DMA'ing.
1593                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts.
1594
1595                 writel(7, s->pBA0 + BA0_PPRVC);
1596                 writel(7, s->pBA0 + BA0_PPLVC);
1597                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
1598                         "cs4281: start_dac(): writel 0x%x start dma\n", temp1));
1599
1600         }
1601         spin_unlock_irqrestore(&s->lock, flags);
1602         CS_DBGOUT(CS_FUNCTION, 3,
1603                   printk(KERN_INFO "cs4281: start_dac()-\n"));
1604 }
1605
1606
1607 static void stop_adc(struct cs4281_state *s)
1608 {
1609         unsigned long flags;
1610         unsigned temp1;
1611
1612         CS_DBGOUT(CS_FUNCTION, 3,
1613                   printk(KERN_INFO "cs4281: stop_adc()+\n"));
1614
1615         spin_lock_irqsave(&s->lock, flags);
1616         s->ena &= ~FMODE_READ;
1617
1618         if (s->conversion == 1) {
1619                 s->conversion = 0;
1620                 s->prop_adc.fmt = s->prop_adc.fmt_original;
1621         }
1622         temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
1623         writel(temp1, s->pBA0 + BA0_DCR1);
1624         spin_unlock_irqrestore(&s->lock, flags);
1625         CS_DBGOUT(CS_FUNCTION, 3,
1626                   printk(KERN_INFO "cs4281: stop_adc()-\n"));
1627 }
1628
1629
1630 static void start_adc(struct cs4281_state *s)
1631 {
1632         unsigned long flags;
1633         unsigned temp1;
1634
1635         CS_DBGOUT(CS_FUNCTION, 2,
1636                   printk(KERN_INFO "cs4281: start_adc()+\n"));
1637
1638         if (!(s->ena & FMODE_READ) &&
1639             (s->dma_adc.mapped || s->dma_adc.count <=
1640              (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
1641             && s->dma_adc.ready
1642 #ifndef NOT_CS4281_PM
1643         && (s->pm.flags & CS4281_PM_IDLE))
1644 #else
1645 )
1646 #endif
1647         {
1648                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
1649                         //
1650                         // now only use 16 bit capture, due to truncation issue
1651                         // in the chip, noticable distortion occurs.
1652                         // allocate buffer and then convert from 16 bit to
1653                         // 8 bit for the user buffer.
1654                         //
1655                         s->prop_adc.fmt_original = s->prop_adc.fmt;
1656                         if (s->prop_adc.fmt & AFMT_S8) {
1657                                 s->prop_adc.fmt &= ~AFMT_S8;
1658                                 s->prop_adc.fmt |= AFMT_S16_LE;
1659                         }
1660                         if (s->prop_adc.fmt & AFMT_U8) {
1661                                 s->prop_adc.fmt &= ~AFMT_U8;
1662                                 s->prop_adc.fmt |= AFMT_U16_LE;
1663                         }
1664                         //
1665                         // prog_dmabuf_adc performs a stop_adc() but that is
1666                         // ok since we really haven't started the DMA yet.
1667                         //
1668                         prog_codec(s, CS_TYPE_ADC);
1669
1670                         if (prog_dmabuf_adc(s) != 0) {
1671                                 CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
1672                                          "cs4281: start_adc(): error in prog_dmabuf_adc\n"));
1673                         }
1674                         s->conversion = 1;
1675                 }
1676                 spin_lock_irqsave(&s->lock, flags);
1677                 s->ena |= FMODE_READ;
1678                 temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK;  // Clear DMA1 channel mask bit.
1679                 writel(temp1, s->pBA0 + BA0_DCR1);      // Start recording
1680                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts.
1681                 spin_unlock_irqrestore(&s->lock, flags);
1682
1683                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
1684                          "cs4281: start_adc(): writel 0x%x \n", temp1));
1685         }
1686         CS_DBGOUT(CS_FUNCTION, 2,
1687                   printk(KERN_INFO "cs4281: start_adc()-\n"));
1688
1689 }
1690
1691
1692 // ---------------------------------------------------------------------
1693
1694 #define DMABUF_MINORDER 1       // ==> min buffer size = 8K.
1695
1696
1697 void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1698 {
1699         struct page *map, *mapend;
1700
1701         if (db->rawbuf) {
1702                 // Undo prog_dmabuf()'s marking the pages as reserved
1703                 mapend =
1704                     virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -
1705                                  1);
1706                 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1707                         ClearPageReserved(map);
1708                 free_dmabuf(s, db);
1709         }
1710         if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1711                 // Undo prog_dmabuf()'s marking the pages as reserved
1712                 mapend =
1713                     virt_to_page(s->tmpbuff +
1714                                  (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1715                 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1716                         ClearPageReserved(map);
1717                 free_dmabuf2(s, db);
1718         }
1719         s->tmpbuff = NULL;
1720         db->rawbuf = NULL;
1721         db->mapped = db->ready = 0;
1722 }
1723
1724 static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1725 {
1726         int order;
1727         unsigned bytespersec, temp1;
1728         unsigned bufs, sample_shift = 0;
1729         struct page *map, *mapend;
1730         unsigned long df;
1731
1732         CS_DBGOUT(CS_FUNCTION, 2,
1733                   printk(KERN_INFO "cs4281: prog_dmabuf()+\n"));
1734         db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
1735             db->endcleared = db->blocks = db->wakeup = db->underrun = 0;
1736 /*
1737 * check for order within limits, but do not overwrite value, check
1738 * later for a fractional defaultorder (i.e. 100+).
1739 */
1740         if((defaultorder > 0) && (defaultorder < 12))
1741                 df = defaultorder;
1742         else
1743                 df = 1;
1744
1745         if (!db->rawbuf) {
1746                 db->ready = db->mapped = 0;
1747                 for (order = df; order >= DMABUF_MINORDER; order--)
1748                         if ( (db->rawbuf = (void *) pci_alloc_consistent(
1749                                 s->pcidev, PAGE_SIZE << order, &db-> dmaaddr)))
1750                                     break;
1751                 if (!db->rawbuf) {
1752                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1753                                 "cs4281: prog_dmabuf(): unable to allocate rawbuf\n"));
1754                         return -ENOMEM;
1755                 }
1756                 db->buforder = order;
1757                 // Now mark the pages as reserved; otherwise the
1758                 // remap_page_range() in cs4281_mmap doesn't work.
1759                 // 1. get index to last page in mem_map array for rawbuf.
1760                 mapend = virt_to_page(db->rawbuf +
1761                         (PAGE_SIZE << db->buforder) - 1);
1762
1763                 // 2. mark each physical page in range as 'reserved'.
1764                 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1765                         SetPageReserved(map);
1766         }
1767         if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1768                 for (order = df; order >= DMABUF_MINORDER;
1769                      order--)
1770                         if ( (s->tmpbuff = (void *) pci_alloc_consistent(
1771                                         s->pcidev, PAGE_SIZE << order,
1772                                         &s->dmaaddr_tmpbuff)))
1773                                     break;
1774                 if (!s->tmpbuff) {
1775                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1776                                 "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n"));
1777                         return -ENOMEM;
1778                 }
1779                 s->buforder_tmpbuff = order;
1780                 // Now mark the pages as reserved; otherwise the
1781                 // remap_page_range() in cs4281_mmap doesn't work.
1782                 // 1. get index to last page in mem_map array for rawbuf.
1783                 mapend = virt_to_page(s->tmpbuff +
1784                                 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1785
1786                 // 2. mark each physical page in range as 'reserved'.
1787                 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1788                         SetPageReserved(map);
1789         }
1790         if (db->type == CS_TYPE_DAC) {
1791                 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1792                         sample_shift++;
1793                 if (s->prop_dac.channels > 1)
1794                         sample_shift++;
1795                 bytespersec = s->prop_dac.rate << sample_shift;
1796         } else                  // CS_TYPE_ADC
1797         {
1798                 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1799                         sample_shift++;
1800                 if (s->prop_adc.channels > 1)
1801                         sample_shift++;
1802                 bytespersec = s->prop_adc.rate << sample_shift;
1803         }
1804         bufs = PAGE_SIZE << db->buforder;
1805
1806 /*
1807 * added fractional "defaultorder" inputs. if >100 then use
1808 * defaultorder-100 as power of 2 for the buffer size. example:
1809 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
1810 */
1811         if(defaultorder >= 100)
1812         {
1813                 bufs = 1 << (defaultorder-100);
1814         }
1815
1816 #define INTERRUPT_RATE_MS       100     // Interrupt rate in milliseconds.
1817         db->numfrag = 2;
1818 /*
1819 * Nominal frag size(bytes/interrupt)
1820 */
1821         temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS);
1822         db->fragshift = 8;      // Min 256 bytes.
1823         while (1 << db->fragshift < temp1)      // Calc power of 2 frag size.
1824                 db->fragshift += 1;
1825         db->fragsize = 1 << db->fragshift;
1826         db->dmasize = db->fragsize * 2;
1827         db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1828
1829 // If the calculated size is larger than the allocated
1830 //  buffer, divide the allocated buffer into 2 fragments.
1831         if (db->dmasize > bufs) {
1832
1833                 db->numfrag = 2;        // Two fragments.
1834                 db->fragsize = bufs >> 1;       // Each 1/2 the alloc'ed buffer.
1835                 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1836                 db->dmasize = bufs;     // Use all the alloc'ed buffer.
1837
1838                 db->fragshift = 0;      // Calculate 'fragshift'.
1839                 temp1 = db->fragsize;   // update_ptr() uses it
1840                 while ((temp1 >>= 1) > 1)       // to calc 'total-bytes'
1841                         db->fragshift += 1;     // returned in DSP_GETI/OPTR.
1842         }
1843         CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO
1844                 "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n",
1845                         db->numfrag, db->fragsize, db->fragsamples,
1846                         db->fragshift, bufs,
1847                         (db->type == CS_TYPE_DAC) ? s->prop_dac.fmt :
1848                                 s->prop_adc.fmt,
1849                         (db->type == CS_TYPE_DAC) ? s->prop_dac.channels :
1850                                 s->prop_adc.channels));
1851         CS_DBGOUT(CS_FUNCTION, 2,
1852                   printk(KERN_INFO "cs4281: prog_dmabuf()-\n"));
1853         return 0;
1854 }
1855
1856
1857 static int prog_dmabuf_adc(struct cs4281_state *s)
1858 {
1859         unsigned long va;
1860         unsigned count;
1861         int c;
1862         stop_adc(s);
1863         s->dma_adc.type = CS_TYPE_ADC;
1864         if ((c = prog_dmabuf(s, &s->dma_adc)))
1865                 return c;
1866
1867         if (s->dma_adc.rawbuf) {
1868                 memset(s->dma_adc.rawbuf,
1869                        (s->prop_adc.
1870                         fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1871                        s->dma_adc.dmasize);
1872         }
1873         if (s->tmpbuff) {
1874                 memset(s->tmpbuff,
1875                        (s->prop_adc.
1876                         fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1877                        PAGE_SIZE << s->buforder_tmpbuff);
1878         }
1879
1880         va = virt_to_bus(s->dma_adc.rawbuf);
1881
1882         count = s->dma_adc.dmasize;
1883
1884         if (s->prop_adc.
1885             fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1886                     count /= 2; // 16-bit.
1887
1888         if (s->prop_adc.channels > 1)
1889                 count /= 2;     // Assume stereo.
1890
1891         CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
1892                 "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n",
1893                         count, (unsigned) va));
1894
1895         writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
1896         writel(count - 1, s->pBA0 + BA0_DBC1);  // Set count.
1897         s->dma_adc.ready = 1;
1898         return 0;
1899 }
1900
1901
1902 static int prog_dmabuf_dac(struct cs4281_state *s)
1903 {
1904         unsigned long va;
1905         unsigned count;
1906         int c;
1907         stop_dac(s);
1908         s->dma_dac.type = CS_TYPE_DAC;
1909         if ((c = prog_dmabuf(s, &s->dma_dac)))
1910                 return c;
1911         memset(s->dma_dac.rawbuf,
1912                (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1913                s->dma_dac.dmasize);
1914
1915         va = virt_to_bus(s->dma_dac.rawbuf);
1916
1917         count = s->dma_dac.dmasize;
1918         if (s->prop_dac.
1919             fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1920                     count /= 2; // 16-bit.
1921
1922         if (s->prop_dac.channels > 1)
1923                 count /= 2;     // Assume stereo.
1924
1925         writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
1926         writel(count - 1, s->pBA0 + BA0_DBC0);  // Set count.
1927
1928         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
1929                 "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n",
1930                         count, (unsigned) va));
1931
1932         s->dma_dac.ready = 1;
1933         return 0;
1934 }
1935
1936
1937 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
1938                           unsigned len, unsigned char c)
1939 {
1940         if (bptr + len > bsize) {
1941                 unsigned x = bsize - bptr;
1942                 memset(((char *) buf) + bptr, c, x);
1943                 bptr = 0;
1944                 len -= x;
1945         }
1946         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1947                 "cs4281: clear_advance(): memset %d at %p for %d size \n",
1948                         (unsigned)c, ((char *) buf) + bptr, len));
1949         memset(((char *) buf) + bptr, c, len);
1950 }
1951
1952
1953
1954 // call with spinlock held!
1955 static void cs4281_update_ptr(struct cs4281_state *s, int intflag)
1956 {
1957         int diff;
1958         unsigned hwptr, va;
1959
1960         // update ADC pointer
1961         if (s->ena & FMODE_READ) {
1962                 hwptr = readl(s->pBA0 + BA0_DCA1);      // Read capture DMA address.
1963                 va = virt_to_bus(s->dma_adc.rawbuf);
1964                 hwptr -= (unsigned) va;
1965                 diff =
1966                     (s->dma_adc.dmasize + hwptr -
1967                      s->dma_adc.hwptr) % s->dma_adc.dmasize;
1968                 s->dma_adc.hwptr = hwptr;
1969                 s->dma_adc.total_bytes += diff;
1970                 s->dma_adc.count += diff;
1971                 if (s->dma_adc.count > s->dma_adc.dmasize)
1972                         s->dma_adc.count = s->dma_adc.dmasize;
1973                 if (s->dma_adc.mapped) {
1974                         if (s->dma_adc.count >=
1975                             (signed) s->dma_adc.fragsize) wake_up(&s->
1976                                                                   dma_adc.
1977                                                                   wait);
1978                 } else {
1979                         if (s->dma_adc.count > 0)
1980                                 wake_up(&s->dma_adc.wait);
1981                 }
1982                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1983                         "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n",
1984                                 s, s->dma_adc.hwptr, s->dma_adc.total_bytes, s->dma_adc.count));
1985         }
1986         // update DAC pointer
1987         //
1988         // check for end of buffer, means that we are going to wait for another interrupt
1989         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1990         //
1991         if (s->ena & FMODE_WRITE) {
1992                 hwptr = readl(s->pBA0 + BA0_DCA0);      // Read play DMA address.
1993                 va = virt_to_bus(s->dma_dac.rawbuf);
1994                 hwptr -= (unsigned) va;
1995                 diff = (s->dma_dac.dmasize + hwptr -
1996                      s->dma_dac.hwptr) % s->dma_dac.dmasize;
1997                 s->dma_dac.hwptr = hwptr;
1998                 s->dma_dac.total_bytes += diff;
1999                 if (s->dma_dac.mapped) {
2000                         s->dma_dac.count += diff;
2001                         if (s->dma_dac.count >= s->dma_dac.fragsize) {
2002                                 s->dma_dac.wakeup = 1;
2003                                 wake_up(&s->dma_dac.wait);
2004                                 if (s->dma_dac.count > s->dma_dac.dmasize)
2005                                         s->dma_dac.count &=
2006                                             s->dma_dac.dmasize - 1;
2007                         }
2008                 } else {
2009                         s->dma_dac.count -= diff;
2010                         if (s->dma_dac.count <= 0) {
2011                                 //
2012                                 // fill with silence, and do not shut down the DAC.
2013                                 // Continue to play silence until the _release.
2014                                 //
2015                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
2016                                         "cs4281: cs4281_update_ptr(): memset %d at %p for %d size \n",
2017                                                 (unsigned)(s->prop_dac.fmt &
2018                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
2019                                                 s->dma_dac.rawbuf, s->dma_dac.dmasize));
2020                                 memset(s->dma_dac.rawbuf,
2021                                        (s->prop_dac.
2022                                         fmt & (AFMT_U8 | AFMT_U16_LE)) ?
2023                                        0x80 : 0, s->dma_dac.dmasize);
2024                                 if (s->dma_dac.count < 0) {
2025                                         s->dma_dac.underrun = 1;
2026                                         s->dma_dac.count = 0;
2027                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
2028                                          "cs4281: cs4281_update_ptr(): underrun\n"));
2029                                 }
2030                         } else if (s->dma_dac.count <=
2031                                    (signed) s->dma_dac.fragsize
2032                                    && !s->dma_dac.endcleared) {
2033                                 clear_advance(s->dma_dac.rawbuf,
2034                                               s->dma_dac.dmasize,
2035                                               s->dma_dac.swptr,
2036                                               s->dma_dac.fragsize,
2037                                               (s->prop_dac.
2038                                                fmt & (AFMT_U8 |
2039                                                       AFMT_U16_LE)) ? 0x80
2040                                               : 0);
2041                                 s->dma_dac.endcleared = 1;
2042                         }
2043                         if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) ||
2044                                 intflag)
2045                         {
2046                                 wake_up(&s->dma_dac.wait);
2047                         }
2048                 }
2049                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
2050                         "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n",
2051                                 s, s->dma_dac.hwptr, s->dma_dac.total_bytes, s->dma_dac.count));
2052         }
2053 }
2054
2055
2056 // ---------------------------------------------------------------------
2057
2058 static void prog_codec(struct cs4281_state *s, unsigned type)
2059 {
2060         unsigned long flags;
2061         unsigned temp1, format;
2062
2063         CS_DBGOUT(CS_FUNCTION, 2,
2064                   printk(KERN_INFO "cs4281: prog_codec()+ \n"));
2065
2066         spin_lock_irqsave(&s->lock, flags);
2067         if (type == CS_TYPE_ADC) {
2068                 temp1 = readl(s->pBA0 + BA0_DCR1);
2069                 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1);   // Stop capture DMA, if active.
2070
2071                 // program sampling rates
2072                 // Note, for CS4281, capture & play rates can be set independently.
2073                 cs4281_record_rate(s, s->prop_adc.rate);
2074
2075                 // program ADC parameters
2076                 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
2077                 if (s->prop_adc.
2078                     fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) {    // 16-bit
2079                         if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE))      // Big-endian?
2080                                 format |= DMRn_BEND;
2081                         if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2082                                 format |= DMRn_USIGN;   // Unsigned.
2083                 } else
2084                         format |= DMRn_SIZE8 | DMRn_USIGN;      // 8-bit, unsigned
2085                 if (s->prop_adc.channels < 2)
2086                         format |= DMRn_MONO;
2087
2088                 writel(format, s->pBA0 + BA0_DMR1);
2089
2090                 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2091                         "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n",
2092                                 (format & DMRn_SIZE8) ? "8" : "16",
2093                                 (format & DMRn_USIGN) ?  "Unsigned" : "Signed",
2094                                 (format & DMRn_MONO) ? "Mono" : "Stereo",
2095                                 s->prop_adc.rate, format));
2096
2097                 s->ena &= ~FMODE_READ;  // not capturing data yet
2098         }
2099
2100
2101         if (type == CS_TYPE_DAC) {
2102                 temp1 = readl(s->pBA0 + BA0_DCR0);
2103                 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0);   // Stop play DMA, if active.
2104
2105                 // program sampling rates
2106                 // Note, for CS4281, capture & play rates can be set independently.
2107                 cs4281_play_rate(s, s->prop_dac.rate);
2108
2109                 // program DAC parameters
2110                 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
2111                 if (s->prop_dac.
2112                     fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) {    // 16-bit
2113                         if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
2114                                 format |= DMRn_BEND;    // Big Endian.
2115                         if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2116                                 format |= DMRn_USIGN;   // Unsigned.
2117                 } else
2118                         format |= DMRn_SIZE8 | DMRn_USIGN;      // 8-bit, unsigned
2119
2120                 if (s->prop_dac.channels < 2)
2121                         format |= DMRn_MONO;
2122
2123                 writel(format, s->pBA0 + BA0_DMR0);
2124
2125
2126                 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2127                         "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n",
2128                                 (format & DMRn_SIZE8) ? "8" : "16",
2129                                 (format & DMRn_USIGN) ?  "Unsigned" : "Signed",
2130                                 (format & DMRn_MONO) ? "Mono" : "Stereo",
2131                                 s->prop_dac.rate, format));
2132
2133                 s->ena &= ~FMODE_WRITE; // not capturing data yet
2134
2135         }
2136         spin_unlock_irqrestore(&s->lock, flags);
2137         CS_DBGOUT(CS_FUNCTION, 2,
2138                   printk(KERN_INFO "cs4281: prog_codec()- \n"));
2139 }
2140
2141
2142 static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
2143                        unsigned long arg)
2144 {
2145         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
2146         // Value of array member is recording source Device ID Mask.
2147         static const unsigned int mixer_src[8] = {
2148                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
2149                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
2150         };
2151         void __user *argp = (void __user *)arg;
2152
2153         // Index of mixtable1[] member is Device ID
2154         // and must be <= SOUND_MIXER_NRDEVICES.
2155         // Value of array member is index into s->mix.vol[]
2156         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
2157                 [SOUND_MIXER_PCM] = 1,  // voice
2158                 [SOUND_MIXER_LINE1] = 2,        // AUX
2159                 [SOUND_MIXER_CD] = 3,   // CD
2160                 [SOUND_MIXER_LINE] = 4, // Line
2161                 [SOUND_MIXER_SYNTH] = 5,        // FM
2162                 [SOUND_MIXER_MIC] = 6,  // Mic
2163                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
2164                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
2165                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
2166         };
2167
2168
2169         static const unsigned mixreg[] = {
2170                 BA0_AC97_PCM_OUT_VOLUME,
2171                 BA0_AC97_AUX_VOLUME,
2172                 BA0_AC97_CD_VOLUME,
2173                 BA0_AC97_LINE_IN_VOLUME
2174         };
2175         unsigned char l, r, rl, rr, vidx;
2176         unsigned char attentbl[11] =
2177             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
2178         unsigned temp1;
2179         int i, val;
2180
2181         VALIDATE_STATE(s);
2182         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
2183                  "cs4281: mixer_ioctl(): s=%p cmd=0x%.8x\n", s, cmd));
2184 #if CSDEBUG
2185         cs_printioctl(cmd);
2186 #endif
2187 #if CSDEBUG_INTERFACE
2188
2189         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
2190             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
2191             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
2192             (cmd == SOUND_MIXER_CS_SETDBGLEVEL) ||
2193             (cmd == SOUND_MIXER_CS_APM))
2194         {
2195                 switch (cmd) {
2196
2197                 case SOUND_MIXER_CS_GETDBGMASK:
2198                         return put_user(cs_debugmask,
2199                                         (unsigned long __user *) argp);
2200
2201                 case SOUND_MIXER_CS_GETDBGLEVEL:
2202                         return put_user(cs_debuglevel,
2203                                         (unsigned long __user *) argp);
2204
2205                 case SOUND_MIXER_CS_SETDBGMASK:
2206                         if (get_user(val, (unsigned long __user *) argp))
2207                                 return -EFAULT;
2208                         cs_debugmask = val;
2209                         return 0;
2210
2211                 case SOUND_MIXER_CS_SETDBGLEVEL:
2212                         if (get_user(val, (unsigned long __user *) argp))
2213                                 return -EFAULT;
2214                         cs_debuglevel = val;
2215                         return 0;
2216 #ifndef NOT_CS4281_PM
2217                 case SOUND_MIXER_CS_APM:
2218                         if (get_user(val, (unsigned long __user *) argp))
2219                                 return -EFAULT;
2220                         if(val == CS_IOCTL_CMD_SUSPEND)
2221                                 cs4281_suspend(s);
2222                         else if(val == CS_IOCTL_CMD_RESUME)
2223                                 cs4281_resume(s);
2224                         else
2225                         {
2226                                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2227                                     "cs4281: mixer_ioctl(): invalid APM cmd (%d)\n",
2228                                         val));
2229                         }
2230                         return 0;
2231 #endif
2232                 default:
2233                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2234                                 "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n"));
2235                         return 0;
2236                 }
2237         }
2238 #endif
2239
2240         if (cmd == SOUND_MIXER_PRIVATE1) {
2241                 // enable/disable/query mixer preamp
2242                 if (get_user(val, (int __user *) argp))
2243                         return -EFAULT;
2244                 if (val != -1) {
2245                         cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2246                         temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
2247                         cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2248                 }
2249                 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2250                 val = (temp1 & 0x40) ? 1 : 0;
2251                 return put_user(val, (int __user *) argp);
2252         }
2253         if (cmd == SOUND_MIXER_PRIVATE2) {
2254                 // enable/disable/query spatializer
2255                 if (get_user(val, (int __user *)argp))
2256                         return -EFAULT;
2257                 if (val != -1) {
2258                         temp1 = (val & 0x3f) >> 2;
2259                         cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
2260                         cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2261                                          &temp1);
2262                         cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2263                                           temp1 | 0x2000);
2264                 }
2265                 cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
2266                 return put_user((temp1 << 2) | 3, (int __user *)argp);
2267         }
2268         if (cmd == SOUND_MIXER_INFO) {
2269                 mixer_info info;
2270                 strlcpy(info.id, "CS4281", sizeof(info.id));
2271                 strlcpy(info.name, "Crystal CS4281", sizeof(info.name));
2272                 info.modify_counter = s->mix.modcnt;
2273                 if (copy_to_user(argp, &info, sizeof(info)))
2274                         return -EFAULT;
2275                 return 0;
2276         }
2277         if (cmd == SOUND_OLD_MIXER_INFO) {
2278                 _old_mixer_info info;
2279                 strlcpy(info.id, "CS4281", sizeof(info.id));
2280                 strlcpy(info.name, "Crystal CS4281", sizeof(info.name));
2281                 if (copy_to_user(argp, &info, sizeof(info)))
2282                         return -EFAULT;
2283                 return 0;
2284         }
2285         if (cmd == OSS_GETVERSION)
2286                 return put_user(SOUND_VERSION, (int __user *) argp);
2287
2288         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
2289                 return -EINVAL;
2290
2291         // If ioctl has only the SIOC_READ bit(bit 31)
2292         // on, process the only-read commands.
2293         if (_SIOC_DIR(cmd) == _SIOC_READ) {
2294                 switch (_IOC_NR(cmd)) {
2295                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
2296                         cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT, &temp1);
2297                         return put_user(mixer_src[temp1&7], (int __user *)argp);
2298
2299                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
2300                         return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2301                                         SOUND_MASK_CD | SOUND_MASK_LINE |
2302                                         SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2303                                         SOUND_MASK_VOLUME |
2304                                         SOUND_MASK_RECLEV |
2305                                         SOUND_MASK_SPEAKER, (int __user *)argp);
2306
2307                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
2308                         return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC |
2309                                         SOUND_MASK_CD | SOUND_MASK_VOLUME |
2310                                         SOUND_MASK_LINE1, (int __user *) argp);
2311
2312                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
2313                         return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2314                                         SOUND_MASK_CD | SOUND_MASK_LINE |
2315                                         SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2316                                         SOUND_MASK_VOLUME |
2317                                         SOUND_MASK_RECLEV, (int __user *)argp);
2318
2319                 case SOUND_MIXER_CAPS:
2320                         return put_user(SOUND_CAP_EXCL_INPUT, (int __user *)argp);
2321
2322                 default:
2323                         i = _IOC_NR(cmd);
2324                         if (i >= SOUND_MIXER_NRDEVICES
2325                             || !(vidx = mixtable1[i]))
2326                                 return -EINVAL;
2327                         return put_user(s->mix.vol[vidx - 1], (int __user *)argp);
2328                 }
2329         }
2330         // If ioctl doesn't have both the SIOC_READ and
2331         // the SIOC_WRITE bit set, return invalid.
2332         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
2333                 return -EINVAL;
2334
2335         // Increment the count of volume writes.
2336         s->mix.modcnt++;
2337
2338         // Isolate the command; it must be a write.
2339         switch (_IOC_NR(cmd)) {
2340
2341         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
2342                 if (get_user(val, (int __user *)argp))
2343                         return -EFAULT;
2344                 i = hweight32(val);     // i = # bits on in val.
2345                 if (i != 1)     // One & only 1 bit must be on.
2346                         return 0;
2347                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
2348                         if (val == mixer_src[i]) {
2349                                 temp1 = (i << 8) | i;
2350                                 cs4281_write_ac97(s,
2351                                                   BA0_AC97_RECORD_SELECT,
2352                                                   temp1);
2353                                 return 0;
2354                         }
2355                 }
2356                 return 0;
2357
2358         case SOUND_MIXER_VOLUME:
2359                 if (get_user(val, (int __user *)argp))
2360                         return -EFAULT;
2361                 l = val & 0xff;
2362                 if (l > 100)
2363                         l = 100;        // Max soundcard.h vol is 100.
2364                 if (l < 6) {
2365                         rl = 63;
2366                         l = 0;
2367                 } else
2368                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
2369
2370                 r = (val >> 8) & 0xff;
2371                 if (r > 100)
2372                         r = 100;        // Max right volume is 100, too
2373                 if (r < 6) {
2374                         rr = 63;
2375                         r = 0;
2376                 } else
2377                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
2378
2379                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
2380                         temp1 = 0x8000; //  turn on the mute bit.
2381                 else
2382                         temp1 = 0;
2383
2384                 temp1 |= (rl << 8) | rr;
2385
2386                 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
2387                 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
2388
2389 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2390                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
2391 #else
2392                 s->mix.vol[8] = val;
2393 #endif
2394                 return put_user(s->mix.vol[8], (int __user *)argp);
2395
2396         case SOUND_MIXER_SPEAKER:
2397                 if (get_user(val, (int __user *)argp))
2398                         return -EFAULT;
2399                 l = val & 0xff;
2400                 if (l > 100)
2401                         l = 100;
2402                 if (l < 3) {
2403                         rl = 0;
2404                         l = 0;
2405                 } else {
2406                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
2407                         l = (rl * 13 + 5) / 2;
2408                 }
2409
2410                 if (rl < 3) {
2411                         temp1 = 0x8000;
2412                         rl = 0;
2413                 } else
2414                         temp1 = 0;
2415                 rl = 15 - rl;   // Convert volume to attenuation.
2416                 temp1 |= rl << 1;
2417                 cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
2418
2419 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2420                 s->mix.vol[6] = l << 8;
2421 #else
2422                 s->mix.vol[6] = val;
2423 #endif
2424                 return put_user(s->mix.vol[6], (int __user *)argp);
2425
2426         case SOUND_MIXER_RECLEV:
2427                 if (get_user(val, (int __user *)argp))
2428                         return -EFAULT;
2429                 l = val & 0xff;
2430                 if (l > 100)
2431                         l = 100;
2432                 r = (val >> 8) & 0xff;
2433                 if (r > 100)
2434                         r = 100;
2435                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
2436                 rr = (r * 2 - 5) / 13;
2437                 if (rl < 3 && rr < 3)
2438                         temp1 = 0x8000;
2439                 else
2440                         temp1 = 0;
2441
2442                 temp1 = temp1 | (rl << 8) | rr;
2443                 cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1);
2444
2445 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2446                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
2447 #else
2448                 s->mix.vol[7] = val;
2449 #endif
2450                 return put_user(s->mix.vol[7], (int __user *)argp);
2451
2452         case SOUND_MIXER_MIC:
2453                 if (get_user(val, (int __user *)argp))
2454                         return -EFAULT;
2455                 l = val & 0xff;
2456                 if (l > 100)
2457                         l = 100;
2458                 if (l < 1) {
2459                         l = 0;
2460                         rl = 0;
2461                 } else {
2462                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
2463                         l = (rl * 16 + 4) / 5;
2464                 }
2465                 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2466                 temp1 &= 0x40;  // Isolate 20db gain bit.
2467                 if (rl < 3) {
2468                         temp1 |= 0x8000;
2469                         rl = 0;
2470                 }
2471                 rl = 31 - rl;   // Convert volume to attenuation.
2472                 temp1 |= rl;
2473                 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2474
2475 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2476                 s->mix.vol[5] = val << 8;
2477 #else
2478                 s->mix.vol[5] = val;
2479 #endif
2480                 return put_user(s->mix.vol[5], (int __user *)argp);
2481
2482
2483         case SOUND_MIXER_SYNTH:
2484                 if (get_user(val, (int __user *)argp))
2485                         return -EFAULT;
2486                 l = val & 0xff;
2487                 if (l > 100)
2488                         l = 100;
2489                 if (get_user(val, (int __user *)argp))
2490                         return -EFAULT;
2491                 r = (val >> 8) & 0xff;
2492                 if (r > 100)
2493                         r = 100;
2494                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
2495                 rr = (r * 2 - 11) / 3;
2496                 if (rl < 3)     // If l is low, turn on
2497                         temp1 = 0x0080; //  the mute bit.
2498                 else
2499                         temp1 = 0;
2500
2501                 rl = 63 - rl;   // Convert vol to attenuation.
2502                 writel(temp1 | rl, s->pBA0 + BA0_FMLVC);
2503                 if (rr < 3)     //  If rr is low, turn on
2504                         temp1 = 0x0080; //   the mute bit.
2505                 else
2506                         temp1 = 0;
2507                 rr = 63 - rr;   // Convert vol to attenuation.
2508                 writel(temp1 | rr, s->pBA0 + BA0_FMRVC);
2509
2510 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2511                 s->mix.vol[4] = (r << 8) | l;
2512 #else
2513                 s->mix.vol[4] = val;
2514 #endif
2515                 return put_user(s->mix.vol[4], (int __user *)argp);
2516
2517
2518         default:
2519                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2520                         "cs4281: mixer_ioctl(): default\n"));
2521
2522                 i = _IOC_NR(cmd);
2523                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
2524                         return -EINVAL;
2525                 if (get_user(val, (int __user *)argp))
2526                         return -EFAULT;
2527                 l = val & 0xff;
2528                 if (l > 100)
2529                         l = 100;
2530                 if (l < 1) {
2531                         l = 0;
2532                         rl = 31;
2533                 } else
2534                         rl = (attentbl[(l * 10) / 100]) >> 1;
2535
2536                 r = (val >> 8) & 0xff;
2537                 if (r > 100)
2538                         r = 100;
2539                 if (r < 1) {
2540                         r = 0;
2541                         rr = 31;
2542                 } else
2543                         rr = (attentbl[(r * 10) / 100]) >> 1;
2544                 if ((rl > 30) && (rr > 30))
2545                         temp1 = 0x8000;
2546                 else
2547                         temp1 = 0;
2548                 temp1 = temp1 | (rl << 8) | rr;
2549                 cs4281_write_ac97(s, mixreg[vidx - 1], temp1);
2550
2551 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2552                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
2553 #else
2554                 s->mix.vol[vidx - 1] = val;
2555 #endif
2556 #ifndef NOT_CS4281_PM
2557                 CS_DBGOUT(CS_PM, 9, printk(KERN_INFO
2558                         "write ac97 mixreg[%d]=0x%x mix.vol[]=0x%x\n",
2559                                 vidx-1,temp1,s->mix.vol[vidx-1]));
2560 #endif
2561                 return put_user(s->mix.vol[vidx - 1], (int __user *)argp);
2562         }
2563 }
2564
2565
2566 // ---------------------------------------------------------------------
2567
2568 static int cs4281_open_mixdev(struct inode *inode, struct file *file)
2569 {
2570         unsigned int minor = iminor(inode);
2571         struct cs4281_state *s=NULL;
2572         struct list_head *entry;
2573
2574         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2575                   printk(KERN_INFO "cs4281: cs4281_open_mixdev()+\n"));
2576
2577         list_for_each(entry, &cs4281_devs)
2578         {
2579                 s = list_entry(entry, struct cs4281_state, list);
2580                 if(s->dev_mixer == minor)
2581                         break;
2582         }
2583         if (!s)
2584         {
2585                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
2586                         printk(KERN_INFO "cs4281: cs4281_open_mixdev()- -ENODEV\n"));
2587                 return -ENODEV;
2588         }
2589         VALIDATE_STATE(s);
2590         file->private_data = s;
2591
2592         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2593                   printk(KERN_INFO "cs4281: cs4281_open_mixdev()- 0\n"));
2594
2595         return 0;
2596 }
2597
2598
2599 static int cs4281_release_mixdev(struct inode *inode, struct file *file)
2600 {
2601         struct cs4281_state *s =
2602             (struct cs4281_state *) file->private_data;
2603
2604         VALIDATE_STATE(s);
2605         return 0;
2606 }
2607
2608
2609 static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
2610                                unsigned int cmd, unsigned long arg)
2611 {
2612         return mixer_ioctl((struct cs4281_state *) file->private_data, cmd,
2613                            arg);
2614 }
2615
2616
2617 // ******************************************************************************************
2618 //   Mixer file operations struct.
2619 // ******************************************************************************************
2620 static /*const */ struct file_operations cs4281_mixer_fops = {
2621         .owner   = THIS_MODULE,
2622         .llseek  = no_llseek,
2623         .ioctl   = cs4281_ioctl_mixdev,
2624         .open    = cs4281_open_mixdev,
2625         .release = cs4281_release_mixdev,
2626 };
2627
2628 // ---------------------------------------------------------------------
2629
2630
2631 static int drain_adc(struct cs4281_state *s, int nonblock)
2632 {
2633         DECLARE_WAITQUEUE(wait, current);
2634         unsigned long flags;
2635         int count;
2636         unsigned tmo;
2637
2638         if (s->dma_adc.mapped)
2639                 return 0;
2640         add_wait_queue(&s->dma_adc.wait, &wait);
2641         for (;;) {
2642                 set_current_state(TASK_INTERRUPTIBLE);
2643                 spin_lock_irqsave(&s->lock, flags);
2644                 count = s->dma_adc.count;
2645                 CS_DBGOUT(CS_FUNCTION, 2,
2646                           printk(KERN_INFO "cs4281: drain_adc() %d\n", count));
2647                 spin_unlock_irqrestore(&s->lock, flags);
2648                 if (count <= 0) {
2649                         CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2650                                  "cs4281: drain_adc() count<0\n"));
2651                         break;
2652                 }
2653                 if (signal_pending(current))
2654                         break;
2655                 if (nonblock) {
2656                         remove_wait_queue(&s->dma_adc.wait, &wait);
2657                         current->state = TASK_RUNNING;
2658                         return -EBUSY;
2659                 }
2660                 tmo =
2661                     3 * HZ * (count +
2662                               s->dma_adc.fragsize) / 2 / s->prop_adc.rate;
2663                 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2664                         tmo >>= 1;
2665                 if (s->prop_adc.channels > 1)
2666                         tmo >>= 1;
2667                 if (!schedule_timeout(tmo + 1))
2668                         printk(KERN_DEBUG "cs4281: dma timed out??\n");
2669         }
2670         remove_wait_queue(&s->dma_adc.wait, &wait);
2671         current->state = TASK_RUNNING;
2672         if (signal_pending(current))
2673                 return -ERESTARTSYS;
2674         return 0;
2675 }
2676
2677 static int drain_dac(struct cs4281_state *s, int nonblock)
2678 {
2679         DECLARE_WAITQUEUE(wait, current);
2680         unsigned long flags;
2681         int count;
2682         unsigned tmo;
2683
2684         if (s->dma_dac.mapped)
2685                 return 0;
2686         add_wait_queue(&s->dma_dac.wait, &wait);
2687         for (;;) {
2688                 set_current_state(TASK_INTERRUPTIBLE);
2689                 spin_lock_irqsave(&s->lock, flags);
2690                 count = s->dma_dac.count;
2691                 spin_unlock_irqrestore(&s->lock, flags);
2692                 if (count <= 0)
2693                         break;
2694                 if (signal_pending(current))
2695                         break;
2696                 if (nonblock) {
2697                         remove_wait_queue(&s->dma_dac.wait, &wait);
2698                         current->state = TASK_RUNNING;
2699                         return -EBUSY;
2700                 }
2701                 tmo =
2702                     3 * HZ * (count +
2703                               s->dma_dac.fragsize) / 2 / s->prop_dac.rate;
2704                 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2705                         tmo >>= 1;
2706                 if (s->prop_dac.channels > 1)
2707                         tmo >>= 1;
2708                 if (!schedule_timeout(tmo + 1))
2709                         printk(KERN_DEBUG "cs4281: dma timed out??\n");
2710         }
2711         remove_wait_queue(&s->dma_dac.wait, &wait);
2712         current->state = TASK_RUNNING;
2713         if (signal_pending(current))
2714                 return -ERESTARTSYS;
2715         return 0;
2716 }
2717
2718 //****************************************************************************
2719 //
2720 // CopySamples copies 16-bit stereo samples from the source to the
2721 // destination, possibly converting down to either 8-bit or mono or both.
2722 // count specifies the number of output bytes to write.
2723 //
2724 //  Arguments:
2725 //
2726 //  dst             - Pointer to a destination buffer.
2727 //  src             - Pointer to a source buffer
2728 //  count           - The number of bytes to copy into the destination buffer.
2729 //  iChannels       - Stereo - 2
2730 //                    Mono   - 1
2731 //  fmt             - AFMT_xxx (soundcard.h formats)
2732 //
2733 // NOTES: only call this routine for conversion to 8bit from 16bit
2734 //
2735 //****************************************************************************
2736 static void CopySamples(char *dst, char *src, int count, int iChannels,
2737                         unsigned fmt)
2738 {
2739
2740         unsigned short *psSrc;
2741         long lAudioSample;
2742
2743         CS_DBGOUT(CS_FUNCTION, 2,
2744                   printk(KERN_INFO "cs4281: CopySamples()+ "));
2745         CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2746                  " dst=%p src=%p count=%d iChannels=%d fmt=0x%x\n",
2747                          dst, src, (unsigned) count, (unsigned) iChannels, (unsigned) fmt));
2748
2749         // Gershwin does format conversion in hardware so normally
2750         // we don't do any host based coversion. The data formatter
2751         // truncates 16 bit data to 8 bit and that causes some hiss.
2752         // We have already forced the HW to do 16 bit sampling and
2753         // 2 channel so that we can use software to round instead
2754         // of truncate
2755
2756         //
2757         // See if the data should be output as 8-bit unsigned stereo.
2758         // or if the data should be output at 8-bit unsigned mono.
2759         //
2760         if ( ((iChannels == 2) && (fmt & AFMT_U8)) ||
2761                 ((iChannels == 1) && (fmt & AFMT_U8)) ) {
2762                 //
2763                 // Convert each 16-bit unsigned stereo sample to 8-bit unsigned
2764                 // stereo using rounding.
2765                 //
2766                 psSrc = (unsigned short *) src;
2767                 count = count / 2;
2768                 while (count--) {
2769                         lAudioSample = (long) psSrc[count] + (long) 0x80;
2770                         if (lAudioSample > 0xffff) {
2771                                 lAudioSample = 0xffff;
2772                         }
2773                         dst[count] = (char) (lAudioSample >> 8);
2774                 }
2775         }
2776         //
2777         // check for 8-bit signed stereo.
2778         //
2779         else if ((iChannels == 2) && (fmt & AFMT_S8)) {
2780                 //
2781                 // Convert each 16-bit stereo sample to 8-bit stereo using rounding.
2782                 //
2783                 psSrc = (short *) src;
2784                 while (count--) {
2785                         lAudioSample =
2786                             (((long) psSrc[0] + (long) psSrc[1]) / 2);
2787                         psSrc += 2;
2788                         *dst++ = (char) ((short) lAudioSample >> 8);
2789                 }
2790         }
2791         //
2792         // Otherwise, the data should be output as 8-bit signed mono.
2793         //
2794         else if ((iChannels == 1) && (fmt & AFMT_S8)) {
2795                 //
2796                 // Convert each 16-bit signed mono sample to 8-bit signed mono
2797                 // using rounding.
2798                 //
2799                 psSrc = (short *) src;
2800                 count = count / 2;
2801                 while (count--) {
2802                         lAudioSample =
2803                             (((long) psSrc[0] + (long) psSrc[1]) / 2);
2804                         if (lAudioSample > 0x7fff) {
2805                                 lAudioSample = 0x7fff;
2806                         }
2807                         psSrc += 2;
2808                         *dst++ = (char) ((short) lAudioSample >> 8);
2809                 }
2810         }
2811 }
2812
2813 //
2814 // cs_copy_to_user()
2815 // replacement for the standard copy_to_user, to allow for a conversion from
2816 // 16 bit to 8 bit if the record conversion is active.  the cs4281 has some
2817 // issues with 8 bit capture, so the driver always captures data in 16 bit
2818 // and then if the user requested 8 bit, converts from 16 to 8 bit.
2819 //
2820 static unsigned cs_copy_to_user(struct cs4281_state *s, void __user *dest,
2821                                 unsigned *hwsrc, unsigned cnt,
2822                                 unsigned *copied)
2823 {
2824         void *src = hwsrc;      //default to the standard destination buffer addr
2825
2826         CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO
2827                 "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=%p\n",
2828                         s->prop_adc.fmt, s->prop_adc.fmt_original,
2829                         (unsigned) cnt, dest));
2830
2831         if (cnt > s->dma_adc.dmasize) {
2832                 cnt = s->dma_adc.dmasize;
2833         }
2834         if (!cnt) {
2835                 *copied = 0;
2836                 return 0;
2837         }
2838         if (s->conversion) {
2839                 if (!s->tmpbuff) {
2840                         *copied = cnt / 2;
2841                         return 0;
2842                 }
2843                 CopySamples(s->tmpbuff, (void *) hwsrc, cnt,
2844                             (unsigned) s->prop_adc.channels,
2845                             s->prop_adc.fmt_original);
2846                 src = s->tmpbuff;
2847                 cnt = cnt / 2;
2848         }
2849
2850         if (copy_to_user(dest, src, cnt)) {
2851                 *copied = 0;
2852                 return -EFAULT;
2853         }
2854         *copied = cnt;
2855         CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2856                 "cs4281: cs_copy_to_user()- copied bytes is %d \n", cnt));
2857         return 0;
2858 }
2859
2860 // ---------------------------------------------------------------------
2861
2862 static ssize_t cs4281_read(struct file *file, char __user *buffer, size_t count,
2863                            loff_t * ppos)
2864 {
2865         struct cs4281_state *s =
2866             (struct cs4281_state *) file->private_data;
2867         ssize_t ret;
2868         unsigned long flags;
2869         unsigned swptr;
2870         int cnt;
2871         unsigned copied = 0;
2872
2873         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2874                   printk(KERN_INFO "cs4281: cs4281_read()+ %Zu \n", count));
2875
2876         VALIDATE_STATE(s);
2877         if (ppos != &file->f_pos)
2878                 return -ESPIPE;
2879         if (s->dma_adc.mapped)
2880                 return -ENXIO;
2881         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
2882                 return ret;
2883         if (!access_ok(VERIFY_WRITE, buffer, count))
2884                 return -EFAULT;
2885         ret = 0;
2886 //
2887 // "count" is the amount of bytes to read (from app), is decremented each loop
2888 //      by the amount of bytes that have been returned to the user buffer.
2889 // "cnt" is the running total of each read from the buffer (changes each loop)
2890 // "buffer" points to the app's buffer
2891 // "ret" keeps a running total of the amount of bytes that have been copied
2892 //      to the user buffer.
2893 // "copied" is the total bytes copied into the user buffer for each loop.
2894 //
2895         while (count > 0) {
2896                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2897                         "_read() count>0 count=%Zu .count=%d .swptr=%d .hwptr=%d \n",
2898                                 count, s->dma_adc.count,
2899                                 s->dma_adc.swptr, s->dma_adc.hwptr));
2900                 spin_lock_irqsave(&s->lock, flags);
2901
2902                 // get the current copy point of the sw buffer
2903                 swptr = s->dma_adc.swptr;
2904
2905                 // cnt is the amount of unread bytes from the end of the
2906                 // hw buffer to the current sw pointer
2907                 cnt = s->dma_adc.dmasize - swptr;
2908
2909                 // dma_adc.count is the current total bytes that have not been read.
2910                 // if the amount of unread bytes from the current sw pointer to the
2911                 // end of the buffer is greater than the current total bytes that
2912                 // have not been read, then set the "cnt" (unread bytes) to the
2913                 // amount of unread bytes.
2914
2915                 if (s->dma_adc.count < cnt)
2916                         cnt = s->dma_adc.count;
2917                 spin_unlock_irqrestore(&s->lock, flags);
2918                 //
2919                 // if we are converting from 8/16 then we need to copy
2920                 // twice the number of 16 bit bytes then 8 bit bytes.
2921                 //
2922                 if (s->conversion) {
2923                         if (cnt > (count * 2))
2924                                 cnt = (count * 2);
2925                 } else {
2926                         if (cnt > count)
2927                                 cnt = count;
2928                 }
2929                 //
2930                 // "cnt" NOW is the smaller of the amount that will be read,
2931                 // and the amount that is requested in this read (or partial).
2932                 // if there are no bytes in the buffer to read, then start the
2933                 // ADC and wait for the interrupt handler to wake us up.
2934                 //
2935                 if (cnt <= 0) {
2936
2937                         // start up the dma engine and then continue back to the top of
2938                         // the loop when wake up occurs.
2939                         start_adc(s);
2940                         if (file->f_flags & O_NONBLOCK)
2941                                 return ret ? ret : -EAGAIN;
2942                         interruptible_sleep_on(&s->dma_adc.wait);
2943                         if (signal_pending(current))
2944                                 return ret ? ret : -ERESTARTSYS;
2945                         continue;
2946                 }
2947                 // there are bytes in the buffer to read.
2948                 // copy from the hw buffer over to the user buffer.
2949                 // user buffer is designated by "buffer"
2950                 // virtual address to copy from is rawbuf+swptr
2951                 // the "cnt" is the number of bytes to read.
2952
2953                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
2954                         "_read() copy_to cnt=%d count=%Zu ", cnt, count));
2955                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2956                          " .dmasize=%d .count=%d buffer=%p ret=%Zd\n",
2957                                  s->dma_adc.dmasize, s->dma_adc.count, buffer, ret));
2958
2959                 if (cs_copy_to_user
2960                     (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied))
2961                         return ret ? ret : -EFAULT;
2962                 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2963                 spin_lock_irqsave(&s->lock, flags);
2964                 s->dma_adc.swptr = swptr;
2965                 s->dma_adc.count -= cnt;
2966                 spin_unlock_irqrestore(&s->lock, flags);
2967                 count -= copied;
2968                 buffer += copied;
2969                 ret += copied;
2970                 start_adc(s);
2971         }
2972         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2973                   printk(KERN_INFO "cs4281: cs4281_read()- %Zd\n", ret));
2974         return ret;
2975 }
2976
2977
2978 static ssize_t cs4281_write(struct file *file, const char __user *buffer,
2979                             size_t count, loff_t * ppos)
2980 {
2981         struct cs4281_state *s =
2982             (struct cs4281_state *) file->private_data;
2983         ssize_t ret;
2984         unsigned long flags;
2985         unsigned swptr, hwptr, busaddr;
2986         int cnt;
2987
2988         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
2989                   printk(KERN_INFO "cs4281: cs4281_write()+ count=%Zu\n",
2990                          count));
2991         VALIDATE_STATE(s);
2992
2993         if (ppos != &file->f_pos)
2994                 return -ESPIPE;
2995         if (s->dma_dac.mapped)
2996                 return -ENXIO;
2997         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
2998                 return ret;
2999         if (!access_ok(VERIFY_READ, buffer, count))
3000                 return -EFAULT;
3001         ret = 0;
3002         while (count > 0) {
3003                 spin_lock_irqsave(&s->lock, flags);
3004                 if (s->dma_dac.count < 0) {
3005                         s->dma_dac.count = 0;
3006                         s->dma_dac.swptr = s->dma_dac.hwptr;
3007                 }
3008                 if (s->dma_dac.underrun) {
3009                         s->dma_dac.underrun = 0;
3010                         hwptr = readl(s->pBA0 + BA0_DCA0);
3011                         busaddr = virt_to_bus(s->dma_dac.rawbuf);
3012                         hwptr -= (unsigned) busaddr;
3013                         s->dma_dac.swptr = s->dma_dac.hwptr = hwptr;
3014                 }
3015                 swptr = s->dma_dac.swptr;
3016                 cnt = s->dma_dac.dmasize - swptr;
3017                 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
3018                         cnt = s->dma_dac.dmasize - s->dma_dac.count;
3019                 spin_unlock_irqrestore(&s->lock, flags);
3020                 if (cnt > count)
3021                         cnt = count;
3022                 if (cnt <= 0) {
3023                         start_dac(s);
3024                         if (file->f_flags & O_NONBLOCK)
3025                                 return ret ? ret : -EAGAIN;
3026                         interruptible_sleep_on(&s->dma_dac.wait);
3027                         if (signal_pending(current))
3028                                 return ret ? ret : -ERESTARTSYS;
3029                         continue;
3030                 }
3031                 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
3032                         return ret ? ret : -EFAULT;
3033                 swptr = (swptr + cnt) % s->dma_dac.dmasize;
3034                 spin_lock_irqsave(&s->lock, flags);
3035                 s->dma_dac.swptr = swptr;
3036                 s->dma_dac.count += cnt;
3037                 s->dma_dac.endcleared = 0;
3038                 spin_unlock_irqrestore(&s->lock, flags);
3039                 count -= cnt;
3040                 buffer += cnt;
3041                 ret += cnt;
3042                 start_dac(s);
3043         }
3044         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
3045                   printk(KERN_INFO "cs4281: cs4281_write()- %Zd\n", ret));
3046         return ret;
3047 }
3048
3049
3050 static unsigned int cs4281_poll(struct file *file,
3051                                 struct poll_table_struct *wait)
3052 {
3053         struct cs4281_state *s =
3054             (struct cs4281_state *) file->private_data;
3055         unsigned long flags;
3056         unsigned int mask = 0;
3057
3058         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3059                   printk(KERN_INFO "cs4281: cs4281_poll()+\n"));
3060         VALIDATE_STATE(s);
3061         if (file->f_mode & FMODE_WRITE) {
3062                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3063                           printk(KERN_INFO
3064                                  "cs4281: cs4281_poll() wait on FMODE_WRITE\n"));
3065                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3066                         return 0;
3067                 poll_wait(file, &s->dma_dac.wait, wait);
3068         }
3069         if (file->f_mode & FMODE_READ) {
3070                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3071                           printk(KERN_INFO
3072                                  "cs4281: cs4281_poll() wait on FMODE_READ\n"));
3073                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
3074                         return 0;
3075                 poll_wait(file, &s->dma_adc.wait, wait);
3076         }
3077         spin_lock_irqsave(&s->lock, flags);
3078         cs4281_update_ptr(s,CS_FALSE);
3079         if (file->f_mode & FMODE_WRITE) {
3080                 if (s->dma_dac.mapped) {
3081                         if (s->dma_dac.count >=
3082                             (signed) s->dma_dac.fragsize) {
3083                                 if (s->dma_dac.wakeup)
3084                                         mask |= POLLOUT | POLLWRNORM;
3085                                 else
3086                                         mask = 0;
3087                                 s->dma_dac.wakeup = 0;
3088                         }
3089                 } else {
3090                         if ((signed) (s->dma_dac.dmasize/2) >= s->dma_dac.count)
3091                                 mask |= POLLOUT | POLLWRNORM;
3092                 }
3093         } else if (file->f_mode & FMODE_READ) {
3094                 if (s->dma_adc.mapped) {
3095                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
3096                                 mask |= POLLIN | POLLRDNORM;
3097                 } else {
3098                         if (s->dma_adc.count > 0)
3099                                 mask |= POLLIN | POLLRDNORM;
3100                 }
3101         }
3102         spin_unlock_irqrestore(&s->lock, flags);
3103         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3104                   printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n",
3105                          mask));
3106         return mask;
3107 }
3108
3109
3110 static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
3111 {
3112         struct cs4281_state *s =
3113             (struct cs4281_state *) file->private_data;
3114         struct dmabuf *db;
3115         int ret;
3116         unsigned long size;
3117
3118         CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3119                   printk(KERN_INFO "cs4281: cs4281_mmap()+\n"));
3120
3121         VALIDATE_STATE(s);
3122         if (vma->vm_flags & VM_WRITE) {
3123                 if ((ret = prog_dmabuf_dac(s)) != 0)
3124                         return ret;
3125                 db = &s->dma_dac;
3126         } else if (vma->vm_flags & VM_READ) {
3127                 if ((ret = prog_dmabuf_adc(s)) != 0)
3128                         return ret;
3129                 db = &s->dma_adc;
3130         } else
3131                 return -EINVAL;
3132 //
3133 // only support PLAYBACK for now
3134 //
3135         db = &s->dma_dac;
3136
3137         if (cs4x_pgoff(vma) != 0)
3138                 return -EINVAL;
3139         size = vma->vm_end - vma->vm_start;
3140         if (size > (PAGE_SIZE << db->buforder))
3141                 return -EINVAL;
3142         if (remap_page_range
3143             (vma, vma->vm_start, virt_to_phys(db->rawbuf), size,
3144              vma->vm_page_prot)) return -EAGAIN;
3145         db->mapped = 1;
3146
3147         CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3148                   printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n",
3149                          (unsigned) size));
3150
3151         return 0;
3152 }
3153
3154
3155 static int cs4281_ioctl(struct inode *inode, struct file *file,
3156                         unsigned int cmd, unsigned long arg)
3157 {
3158         struct cs4281_state *s =
3159             (struct cs4281_state *) file->private_data;
3160         unsigned long flags;
3161         audio_buf_info abinfo;
3162         count_info cinfo;
3163         int val, mapped, ret;
3164         int __user *p = (int __user *)arg;
3165
3166         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
3167                  "cs4281: cs4281_ioctl(): file=%p cmd=0x%.8x\n", file, cmd));
3168 #if CSDEBUG
3169         cs_printioctl(cmd);
3170 #endif
3171         VALIDATE_STATE(s);
3172         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
3173             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
3174         switch (cmd) {
3175         case OSS_GETVERSION:
3176                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3177                         "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n",
3178                                  SOUND_VERSION));
3179                 return put_user(SOUND_VERSION, p);
3180
3181         case SNDCTL_DSP_SYNC:
3182                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3183                          "cs4281: cs4281_ioctl(): DSP_SYNC\n"));
3184                 if (file->f_mode & FMODE_WRITE)
3185                         return drain_dac(s,
3186                                          0 /*file->f_flags & O_NONBLOCK */
3187                                          );
3188                 return 0;
3189
3190         case SNDCTL_DSP_SETDUPLEX:
3191                 return 0;
3192
3193         case SNDCTL_DSP_GETCAPS:
3194                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
3195                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
3196                                 p);
3197
3198         case SNDCTL_DSP_RESET:
3199                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3200                          "cs4281: cs4281_ioctl(): DSP_RESET\n"));
3201                 if (file->f_mode & FMODE_WRITE) {
3202                         stop_dac(s);
3203                         synchronize_irq(s->irq);
3204                         s->dma_dac.swptr = s->dma_dac.hwptr =
3205                             s->dma_dac.count = s->dma_dac.total_bytes =
3206                             s->dma_dac.blocks = s->dma_dac.wakeup = 0;
3207                         prog_codec(s, CS_TYPE_DAC);
3208                 }
3209                 if (file->f_mode & FMODE_READ) {
3210                         stop_adc(s);
3211                         synchronize_irq(s->irq);
3212                         s->dma_adc.swptr = s->dma_adc.hwptr =
3213                             s->dma_adc.count = s->dma_adc.total_bytes =
3214                             s->dma_adc.blocks = s->dma_dac.wakeup = 0;
3215                         prog_codec(s, CS_TYPE_ADC);
3216                 }
3217                 return 0;
3218
3219         case SNDCTL_DSP_SPEED:
3220                 if (get_user(val, p))
3221                         return -EFAULT;
3222                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3223                          "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n", val));
3224                 //
3225                 // support independent capture and playback channels
3226                 // assume that the file mode bit determines the
3227                 // direction of the data flow.
3228                 //
3229                 if (file->f_mode & FMODE_READ) {
3230                         if (val >= 0) {
3231                                 stop_adc(s);
3232                                 s->dma_adc.ready = 0;
3233                                 // program sampling rates
3234                                 if (val > 48000)
3235                                         val = 48000;
3236                                 if (val < 6300)
3237                                         val = 6300;
3238                                 s->prop_adc.rate = val;
3239                                 prog_codec(s, CS_TYPE_ADC);
3240                         }
3241                 }
3242                 if (file->f_mode & FMODE_WRITE) {
3243                         if (val >= 0) {
3244                                 stop_dac(s);
3245                                 s->dma_dac.ready = 0;
3246                                 // program sampling rates
3247                                 if (val > 48000)
3248                                         val = 48000;
3249                                 if (val < 6300)
3250                                         val = 6300;
3251                                 s->prop_dac.rate = val;
3252                                 prog_codec(s, CS_TYPE_DAC);
3253                         }
3254                 }
3255
3256                 if (file->f_mode & FMODE_WRITE)
3257                         val = s->prop_dac.rate;
3258                 else if (file->f_mode & FMODE_READ)
3259                         val = s->prop_adc.rate;
3260
3261                 return put_user(val, p);
3262
3263         case SNDCTL_DSP_STEREO:
3264                 if (get_user(val, p))
3265                         return -EFAULT;
3266                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3267                          "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n", val));
3268                 if (file->f_mode & FMODE_READ) {
3269                         stop_adc(s);
3270                         s->dma_adc.ready = 0;
3271                         s->prop_adc.channels = val ? 2 : 1;
3272                         prog_codec(s, CS_TYPE_ADC);
3273                 }
3274                 if (file->f_mode & FMODE_WRITE) {
3275                         stop_dac(s);
3276                         s->dma_dac.ready = 0;
3277                         s->prop_dac.channels = val ? 2 : 1;
3278                         prog_codec(s, CS_TYPE_DAC);
3279                 }
3280                 return 0;
3281
3282         case SNDCTL_DSP_CHANNELS:
3283                 if (get_user(val, p))
3284                         return -EFAULT;
3285                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3286                          "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n",
3287                                  val));
3288                 if (val != 0) {
3289                         if (file->f_mode & FMODE_READ) {
3290                                 stop_adc(s);
3291                                 s->dma_adc.ready = 0;
3292                                 if (val >= 2)
3293                                         s->prop_adc.channels = 2;
3294                                 else
3295                                         s->prop_adc.channels = 1;
3296                                 prog_codec(s, CS_TYPE_ADC);
3297                         }
3298                         if (file->f_mode & FMODE_WRITE) {
3299                                 stop_dac(s);
3300                                 s->dma_dac.ready = 0;
3301                                 if (val >= 2)
3302                                         s->prop_dac.channels = 2;
3303                                 else
3304                                         s->prop_dac.channels = 1;
3305                                 prog_codec(s, CS_TYPE_DAC);
3306                         }
3307                 }
3308
3309                 if (file->f_mode & FMODE_WRITE)
3310                         val = s->prop_dac.channels;
3311                 else if (file->f_mode & FMODE_READ)
3312                         val = s->prop_adc.channels;
3313
3314                 return put_user(val, p);
3315
3316         case SNDCTL_DSP_GETFMTS:        // Returns a mask
3317                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3318                         "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n",
3319                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3320                                  AFMT_U8));
3321                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3322                                 AFMT_U8, p);
3323
3324         case SNDCTL_DSP_SETFMT:
3325                 if (get_user(val, p))
3326                         return -EFAULT;
3327                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3328                          "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n",
3329                                  val));
3330                 if (val != AFMT_QUERY) {
3331                         if (file->f_mode & FMODE_READ) {
3332                                 stop_adc(s);
3333                                 s->dma_adc.ready = 0;
3334                                 if (val != AFMT_S16_LE
3335                                     && val != AFMT_U16_LE && val != AFMT_S8
3336                                     && val != AFMT_U8)
3337                                         val = AFMT_U8;
3338                                 s->prop_adc.fmt = val;
3339                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
3340                                 prog_codec(s, CS_TYPE_ADC);
3341                         }
3342                         if (file->f_mode & FMODE_WRITE) {
3343                                 stop_dac(s);
3344                                 s->dma_dac.ready = 0;
3345                                 if (val != AFMT_S16_LE
3346                                     && val != AFMT_U16_LE && val != AFMT_S8
3347                                     && val != AFMT_U8)
3348                                         val = AFMT_U8;
3349                                 s->prop_dac.fmt = val;
3350                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
3351                                 prog_codec(s, CS_TYPE_DAC);
3352                         }
3353                 } else {
3354                         if (file->f_mode & FMODE_WRITE)
3355                                 val = s->prop_dac.fmt_original;
3356                         else if (file->f_mode & FMODE_READ)
3357                                 val = s->prop_adc.fmt_original;
3358                 }
3359                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3360                   "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n",
3361                         val));
3362                 return put_user(val, p);
3363
3364         case SNDCTL_DSP_POST:
3365                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3366                          "cs4281: cs4281_ioctl(): DSP_POST\n"));
3367                 return 0;
3368
3369         case SNDCTL_DSP_GETTRIGGER:
3370                 val = 0;
3371                 if (file->f_mode & s->ena & FMODE_READ)
3372                         val |= PCM_ENABLE_INPUT;
3373                 if (file->f_mode & s->ena & FMODE_WRITE)
3374                         val |= PCM_ENABLE_OUTPUT;
3375                 return put_user(val, p);
3376
3377         case SNDCTL_DSP_SETTRIGGER:
3378                 if (get_user(val, p))
3379                         return -EFAULT;
3380                 if (file->f_mode & FMODE_READ) {
3381                         if (val & PCM_ENABLE_INPUT) {
3382                                 if (!s->dma_adc.ready
3383                                     && (ret = prog_dmabuf_adc(s)))
3384                                         return ret;
3385                                 start_adc(s);
3386                         } else
3387                                 stop_adc(s);
3388                 }
3389                 if (file->f_mode & FMODE_WRITE) {
3390                         if (val & PCM_ENABLE_OUTPUT) {
3391                                 if (!s->dma_dac.ready
3392                                     && (ret = prog_dmabuf_dac(s)))
3393                                         return ret;
3394                                 start_dac(s);
3395                         } else
3396                                 stop_dac(s);
3397                 }
3398                 return 0;
3399
3400         case SNDCTL_DSP_GETOSPACE:
3401                 if (!(file->f_mode & FMODE_WRITE))
3402                         return -EINVAL;
3403                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
3404                         return val;
3405                 spin_lock_irqsave(&s->lock, flags);
3406                 cs4281_update_ptr(s,CS_FALSE);
3407                 abinfo.fragsize = s->dma_dac.fragsize;
3408                 if (s->dma_dac.mapped)
3409                         abinfo.bytes = s->dma_dac.dmasize;
3410                 else
3411                         abinfo.bytes =
3412                             s->dma_dac.dmasize - s->dma_dac.count;
3413                 abinfo.fragstotal = s->dma_dac.numfrag;
3414                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
3415                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
3416                         "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
3417                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
3418                                 abinfo.fragments));
3419                 spin_unlock_irqrestore(&s->lock, flags);
3420                 return copy_to_user(p, &abinfo,
3421                                     sizeof(abinfo)) ? -EFAULT : 0;
3422
3423         case SNDCTL_DSP_GETISPACE:
3424                 if (!(file->f_mode & FMODE_READ))
3425                         return -EINVAL;
3426                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
3427                         return val;
3428                 spin_lock_irqsave(&s->lock, flags);
3429                 cs4281_update_ptr(s,CS_FALSE);
3430                 if (s->conversion) {
3431                         abinfo.fragsize = s->dma_adc.fragsize / 2;
3432                         abinfo.bytes = s->dma_adc.count / 2;
3433                         abinfo.fragstotal = s->dma_adc.numfrag;
3434                         abinfo.fragments =
3435                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
3436                 } else {
3437                         abinfo.fragsize = s->dma_adc.fragsize;
3438                         abinfo.bytes = s->dma_adc.count;
3439                         abinfo.fragstotal = s->dma_adc.numfrag;
3440                         abinfo.fragments =
3441                             abinfo.bytes >> s->dma_adc.fragshift;
3442                 }
3443                 spin_unlock_irqrestore(&s->lock, flags);
3444                 return copy_to_user(p, &abinfo,
3445                                     sizeof(abinfo)) ? -EFAULT : 0;
3446
3447         case SNDCTL_DSP_NONBLOCK:
3448                 file->f_flags |= O_NONBLOCK;
3449                 return 0;
3450
3451         case SNDCTL_DSP_GETODELAY:
3452                 if (!(file->f_mode & FMODE_WRITE))
3453                         return -EINVAL;
3454                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3455                         return 0;
3456                 spin_lock_irqsave(&s->lock, flags);
3457                 cs4281_update_ptr(s,CS_FALSE);
3458                 val = s->dma_dac.count;
3459                 spin_unlock_irqrestore(&s->lock, flags);
3460                 return put_user(val, p);
3461
3462         case SNDCTL_DSP_GETIPTR:
3463                 if (!(file->f_mode & FMODE_READ))
3464                         return -EINVAL;
3465                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
3466                         return 0;
3467                 spin_lock_irqsave(&s->lock, flags);
3468                 cs4281_update_ptr(s,CS_FALSE);
3469                 cinfo.bytes = s->dma_adc.total_bytes;
3470                 if (s->dma_adc.mapped) {
3471                         cinfo.blocks =
3472                             (cinfo.bytes >> s->dma_adc.fragshift) -
3473                             s->dma_adc.blocks;
3474                         s->dma_adc.blocks =
3475                             cinfo.bytes >> s->dma_adc.fragshift;
3476                 } else {
3477                         if (s->conversion) {
3478                                 cinfo.blocks =
3479                                     s->dma_adc.count /
3480                                     2 >> (s->dma_adc.fragshift - 1);
3481                         } else
3482                                 cinfo.blocks =
3483                                     s->dma_adc.count >> s->dma_adc.
3484                                     fragshift;
3485                 }
3486                 if (s->conversion)
3487                         cinfo.ptr = s->dma_adc.hwptr / 2;
3488                 else
3489                         cinfo.ptr = s->dma_adc.hwptr;
3490                 if (s->dma_adc.mapped)
3491                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
3492                 spin_unlock_irqrestore(&s->lock, flags);
3493                 if (copy_to_user(p, &cinfo, sizeof(cinfo)))
3494                         return -EFAULT;
3495                 return 0;
3496
3497         case SNDCTL_DSP_GETOPTR:
3498                 if (!(file->f_mode & FMODE_WRITE))
3499                         return -EINVAL;
3500                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3501                         return 0;
3502                 spin_lock_irqsave(&s->lock, flags);
3503                 cs4281_update_ptr(s,CS_FALSE);
3504                 cinfo.bytes = s->dma_dac.total_bytes;
3505                 if (s->dma_dac.mapped) {
3506                         cinfo.blocks =
3507                             (cinfo.bytes >> s->dma_dac.fragshift) -
3508                             s->dma_dac.blocks;
3509                         s->dma_dac.blocks =
3510                             cinfo.bytes >> s->dma_dac.fragshift;
3511                 } else {
3512                         cinfo.blocks =
3513                             s->dma_dac.count >> s->dma_dac.fragshift;
3514                 }
3515                 cinfo.ptr = s->dma_dac.hwptr;
3516                 if (s->dma_dac.mapped)
3517                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
3518                 spin_unlock_irqrestore(&s->lock, flags);
3519                 if (copy_to_user(p, &cinfo, sizeof(cinfo)))
3520                         return -EFAULT;
3521                 return 0;
3522
3523         case SNDCTL_DSP_GETBLKSIZE:
3524                 if (file->f_mode & FMODE_WRITE) {
3525                         if ((val = prog_dmabuf_dac(s)))
3526                                 return val;
3527                         return put_user(s->dma_dac.fragsize, p);
3528                 }
3529                 if ((val = prog_dmabuf_adc(s)))
3530                         return val;
3531                 if (s->conversion)
3532                         return put_user(s->dma_adc.fragsize / 2, p);
3533                 else
3534                         return put_user(s->dma_adc.fragsize, p);
3535
3536         case SNDCTL_DSP_SETFRAGMENT:
3537                 if (get_user(val, p))
3538                         return -EFAULT;
3539                 return 0;       // Say OK, but do nothing.
3540
3541         case SNDCTL_DSP_SUBDIVIDE:
3542                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
3543                     || (file->f_mode & FMODE_WRITE
3544                         && s->dma_dac.subdivision)) return -EINVAL;
3545                 if (get_user(val, p))
3546                         return -EFAULT;
3547                 if (val != 1 && val != 2 && val != 4)
3548                         return -EINVAL;
3549                 if (file->f_mode & FMODE_READ)
3550                         s->dma_adc.subdivision = val;
3551                 else if (file->f_mode & FMODE_WRITE)
3552                         s->dma_dac.subdivision = val;
3553                 return 0;
3554
3555         case SOUND_PCM_READ_RATE:
3556                 if (file->f_mode & FMODE_READ)
3557                         return put_user(s->prop_adc.rate, p);
3558                 else if (file->f_mode & FMODE_WRITE)
3559                         return put_user(s->prop_dac.rate, p);
3560
3561         case SOUND_PCM_READ_CHANNELS:
3562                 if (file->f_mode & FMODE_READ)
3563                         return put_user(s->prop_adc.channels, p);
3564                 else if (file->f_mode & FMODE_WRITE)
3565                         return put_user(s->prop_dac.channels, p);
3566
3567         case SOUND_PCM_READ_BITS:
3568                 if (file->f_mode & FMODE_READ)
3569                         return
3570                             put_user(
3571                                      (s->prop_adc.
3572                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3573                                      p);
3574                 else if (file->f_mode & FMODE_WRITE)
3575                         return
3576                             put_user(
3577                                      (s->prop_dac.
3578                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3579                                      p);
3580
3581         case SOUND_PCM_WRITE_FILTER:
3582         case SNDCTL_DSP_SETSYNCRO:
3583         case SOUND_PCM_READ_FILTER:
3584                 return -EINVAL;
3585         }
3586         return mixer_ioctl(s, cmd, arg);
3587 }
3588
3589
3590 static int cs4281_release(struct inode *inode, struct file *file)
3591 {
3592         struct cs4281_state *s =
3593             (struct cs4281_state *) file->private_data;
3594
3595         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
3596                  "cs4281: cs4281_release(): inode=%p file=%p f_mode=%d\n",
3597                          inode, file, file->f_mode));
3598
3599         VALIDATE_STATE(s);
3600
3601         if (file->f_mode & FMODE_WRITE) {
3602                 drain_dac(s, file->f_flags & O_NONBLOCK);
3603                 down(&s->open_sem_dac);
3604                 stop_dac(s);
3605                 dealloc_dmabuf(s, &s->dma_dac);
3606                 s->open_mode &= ~FMODE_WRITE;
3607                 up(&s->open_sem_dac);
3608                 wake_up(&s->open_wait_dac);
3609         }
3610         if (file->f_mode & FMODE_READ) {
3611                 drain_adc(s, file->f_flags & O_NONBLOCK);
3612                 down(&s->open_sem_adc);
3613                 stop_adc(s);
3614                 dealloc_dmabuf(s, &s->dma_adc);
3615                 s->open_mode &= ~FMODE_READ;
3616                 up(&s->open_sem_adc);
3617                 wake_up(&s->open_wait_adc);
3618         }
3619         return 0;
3620 }
3621
3622 static int cs4281_open(struct inode *inode, struct file *file)
3623 {
3624         unsigned int minor = iminor(inode);
3625         struct cs4281_state *s=NULL;
3626         struct list_head *entry;
3627
3628         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3629                 "cs4281: cs4281_open(): inode=%p file=%p f_mode=0x%x\n",
3630                         inode, file, file->f_mode));
3631
3632         list_for_each(entry, &cs4281_devs)
3633         {
3634                 s = list_entry(entry, struct cs4281_state, list);
3635
3636                 if (!((s->dev_audio ^ minor) & ~0xf))
3637                         break;
3638         }
3639         if (entry == &cs4281_devs)
3640                 return -ENODEV;
3641         if (!s) {
3642                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3643                         "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3644                 return -ENODEV;
3645         }
3646         VALIDATE_STATE(s);
3647         file->private_data = s;
3648
3649         // wait for device to become free
3650         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
3651                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
3652                          "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n"));
3653                 return -ENODEV;
3654         }
3655         if (file->f_mode & FMODE_WRITE) {
3656                 down(&s->open_sem_dac);
3657                 while (s->open_mode & FMODE_WRITE) {
3658                         if (file->f_flags & O_NONBLOCK) {
3659                                 up(&s->open_sem_dac);
3660                                 return -EBUSY;
3661                         }
3662                         up(&s->open_sem_dac);
3663                         interruptible_sleep_on(&s->open_wait_dac);
3664
3665                         if (signal_pending(current))
3666                                 return -ERESTARTSYS;
3667                         down(&s->open_sem_dac);
3668                 }
3669         }
3670         if (file->f_mode & FMODE_READ) {
3671                 down(&s->open_sem_adc);
3672                 while (s->open_mode & FMODE_READ) {
3673                         if (file->f_flags & O_NONBLOCK) {
3674                                 up(&s->open_sem_adc);
3675                                 return -EBUSY;
3676                         }
3677                         up(&s->open_sem_adc);
3678                         interruptible_sleep_on(&s->open_wait_adc);
3679
3680                         if (signal_pending(current))
3681                                 return -ERESTARTSYS;
3682                         down(&s->open_sem_adc);
3683                 }
3684         }
3685         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
3686         if (file->f_mode & FMODE_READ) {
3687                 s->prop_adc.fmt = AFMT_U8;
3688                 s->prop_adc.fmt_original = s->prop_adc.fmt;
3689                 s->prop_adc.channels = 1;
3690                 s->prop_adc.rate = 8000;
3691                 s->prop_adc.clkdiv = 96 | 0x80;
3692                 s->conversion = 0;
3693                 s->ena &= ~FMODE_READ;
3694                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
3695                     s->dma_adc.subdivision = 0;
3696                 up(&s->open_sem_adc);
3697
3698                 if (prog_dmabuf_adc(s)) {
3699                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3700                                 "cs4281: adc Program dmabufs failed.\n"));
3701                         cs4281_release(inode, file);
3702                         return -ENOMEM;
3703                 }
3704                 prog_codec(s, CS_TYPE_ADC);
3705         }
3706         if (file->f_mode & FMODE_WRITE) {
3707                 s->prop_dac.fmt = AFMT_U8;
3708                 s->prop_dac.fmt_original = s->prop_dac.fmt;
3709                 s->prop_dac.channels = 1;
3710                 s->prop_dac.rate = 8000;
3711                 s->prop_dac.clkdiv = 96 | 0x80;
3712                 s->conversion = 0;
3713                 s->ena &= ~FMODE_WRITE;
3714                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
3715                     s->dma_dac.subdivision = 0;
3716                 up(&s->open_sem_dac);
3717
3718                 if (prog_dmabuf_dac(s)) {
3719                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3720                                 "cs4281: dac Program dmabufs failed.\n"));
3721                         cs4281_release(inode, file);
3722                         return -ENOMEM;
3723                 }
3724                 prog_codec(s, CS_TYPE_DAC);
3725         }
3726         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3727                   printk(KERN_INFO "cs4281: cs4281_open()- 0\n"));
3728         return 0;
3729 }
3730
3731
3732 // ******************************************************************************************
3733 //   Wave (audio) file operations struct.
3734 // ******************************************************************************************
3735 static /*const */ struct file_operations cs4281_audio_fops = {
3736         .owner   = THIS_MODULE,
3737         .llseek  = no_llseek,
3738         .read    = cs4281_read,
3739         .write   = cs4281_write,
3740         .poll    = cs4281_poll,
3741         .ioctl   = cs4281_ioctl,
3742         .mmap    = cs4281_mmap,
3743         .open    = cs4281_open,
3744         .release = cs4281_release,
3745 };
3746
3747 // ---------------------------------------------------------------------
3748
3749 // hold spinlock for the following!
3750 static void cs4281_handle_midi(struct cs4281_state *s)
3751 {
3752         unsigned char ch;
3753         int wake;
3754         unsigned temp1;
3755
3756         wake = 0;
3757         while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) {
3758                 ch = readl(s->pBA0 + BA0_MIDRP);
3759                 if (s->midi.icnt < MIDIINBUF) {
3760                         s->midi.ibuf[s->midi.iwr] = ch;
3761                         s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
3762                         s->midi.icnt++;
3763                 }
3764                 wake = 1;
3765         }
3766         if (wake)
3767                 wake_up(&s->midi.iwait);
3768         wake = 0;
3769         while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
3770                 temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff;
3771                 writel(temp1, s->pBA0 + BA0_MIDWP);
3772                 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
3773                 s->midi.ocnt--;
3774                 if (s->midi.ocnt < MIDIOUTBUF - 16)
3775                         wake = 1;
3776         }
3777         if (wake)
3778                 wake_up(&s->midi.owait);
3779 }
3780
3781
3782
3783 static irqreturn_t cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3784 {
3785         struct cs4281_state *s = (struct cs4281_state *) dev_id;
3786         unsigned int temp1;
3787
3788         // fastpath out, to ease interrupt sharing
3789         temp1 = readl(s->pBA0 + BA0_HISR);      // Get Int Status reg.
3790
3791         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
3792                   "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n", temp1));
3793 /*
3794 * If not DMA or MIDI interrupt, then just return.
3795 */
3796         if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) {
3797                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
3798                 CS_DBGOUT(CS_INTERRUPT, 9, printk(KERN_INFO
3799                         "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n"));
3800                 return IRQ_NONE;
3801         }
3802
3803         if (temp1 & HISR_DMA0)  // If play interrupt,
3804                 readl(s->pBA0 + BA0_HDSR0);     //   clear the source.
3805
3806         if (temp1 & HISR_DMA1)  // Same for play.
3807                 readl(s->pBA0 + BA0_HDSR1);
3808         writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Local EOI
3809
3810         spin_lock(&s->lock);
3811         cs4281_update_ptr(s,CS_TRUE);
3812         cs4281_handle_midi(s);
3813         spin_unlock(&s->lock);
3814         return IRQ_HANDLED;
3815 }
3816
3817 // **************************************************************************
3818
3819 static void cs4281_midi_timer(unsigned long data)
3820 {
3821         struct cs4281_state *s = (struct cs4281_state *) data;
3822         unsigned long flags;
3823
3824         spin_lock_irqsave(&s->lock, flags);
3825         cs4281_handle_midi(s);
3826         spin_unlock_irqrestore(&s->lock, flags);
3827         s->midi.timer.expires = jiffies + 1;
3828         add_timer(&s->midi.timer);
3829 }
3830
3831
3832 // ---------------------------------------------------------------------
3833
3834 static ssize_t cs4281_midi_read(struct file *file, char __user *buffer,
3835                                 size_t count, loff_t * ppos)
3836 {
3837         struct cs4281_state *s =
3838             (struct cs4281_state *) file->private_data;
3839         ssize_t ret;
3840         unsigned long flags;
3841         unsigned ptr;
3842         int cnt;
3843
3844         VALIDATE_STATE(s);
3845         if (ppos != &file->f_pos)
3846                 return -ESPIPE;
3847         if (!access_ok(VERIFY_WRITE, buffer, count))
3848                 return -EFAULT;
3849         ret = 0;
3850         while (count > 0) {
3851                 spin_lock_irqsave(&s->lock, flags);
3852                 ptr = s->midi.ird;
3853                 cnt = MIDIINBUF - ptr;
3854                 if (s->midi.icnt < cnt)
3855                         cnt = s->midi.icnt;
3856                 spin_unlock_irqrestore(&s->lock, flags);
3857                 if (cnt > count)
3858                         cnt = count;
3859                 if (cnt <= 0) {
3860                         if (file->f_flags & O_NONBLOCK)
3861                                 return ret ? ret : -EAGAIN;
3862                         interruptible_sleep_on(&s->midi.iwait);
3863                         if (signal_pending(current))
3864                                 return ret ? ret : -ERESTARTSYS;
3865                         continue;
3866                 }
3867                 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
3868                         return ret ? ret : -EFAULT;
3869                 ptr = (ptr + cnt) % MIDIINBUF;
3870                 spin_lock_irqsave(&s->lock, flags);
3871                 s->midi.ird = ptr;
3872                 s->midi.icnt -= cnt;
3873                 spin_unlock_irqrestore(&s->lock, flags);
3874                 count -= cnt;
3875                 buffer += cnt;
3876                 ret += cnt;
3877         }
3878         return ret;
3879 }
3880
3881
3882 static ssize_t cs4281_midi_write(struct file *file, const char __user *buffer,
3883                                  size_t count, loff_t * ppos)
3884 {
3885         struct cs4281_state *s =
3886             (struct cs4281_state *) file->private_data;
3887         ssize_t ret;
3888         unsigned long flags;
3889         unsigned ptr;
3890         int cnt;
3891
3892         VALIDATE_STATE(s);
3893         if (ppos != &file->f_pos)
3894                 return -ESPIPE;
3895         if (!access_ok(VERIFY_READ, buffer, count))
3896                 return -EFAULT;
3897         ret = 0;
3898         while (count > 0) {
3899                 spin_lock_irqsave(&s->lock, flags);
3900                 ptr = s->midi.owr;
3901                 cnt = MIDIOUTBUF - ptr;
3902                 if (s->midi.ocnt + cnt > MIDIOUTBUF)
3903                         cnt = MIDIOUTBUF - s->midi.ocnt;
3904                 if (cnt <= 0)
3905                         cs4281_handle_midi(s);
3906                 spin_unlock_irqrestore(&s->lock, flags);
3907                 if (cnt > count)
3908                         cnt = count;
3909                 if (cnt <= 0) {
3910                         if (file->f_flags & O_NONBLOCK)
3911                                 return ret ? ret : -EAGAIN;
3912                         interruptible_sleep_on(&s->midi.owait);
3913                         if (signal_pending(current))
3914                                 return ret ? ret : -ERESTARTSYS;
3915                         continue;
3916                 }
3917                 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
3918                         return ret ? ret : -EFAULT;
3919                 ptr = (ptr + cnt) % MIDIOUTBUF;
3920                 spin_lock_irqsave(&s->lock, flags);
3921                 s->midi.owr = ptr;
3922                 s->midi.ocnt += cnt;
3923                 spin_unlock_irqrestore(&s->lock, flags);
3924                 count -= cnt;
3925                 buffer += cnt;
3926                 ret += cnt;
3927                 spin_lock_irqsave(&s->lock, flags);
3928                 cs4281_handle_midi(s);
3929                 spin_unlock_irqrestore(&s->lock, flags);
3930         }
3931         return ret;
3932 }
3933
3934
3935 static unsigned int cs4281_midi_poll(struct file *file,
3936                                      struct poll_table_struct *wait)
3937 {
3938         struct cs4281_state *s =
3939             (struct cs4281_state *) file->private_data;
3940         unsigned long flags;
3941         unsigned int mask = 0;
3942
3943         VALIDATE_STATE(s);
3944         if (file->f_flags & FMODE_WRITE)
3945                 poll_wait(file, &s->midi.owait, wait);
3946         if (file->f_flags & FMODE_READ)
3947                 poll_wait(file, &s->midi.iwait, wait);
3948         spin_lock_irqsave(&s->lock, flags);
3949         if (file->f_flags & FMODE_READ) {
3950                 if (s->midi.icnt > 0)
3951                         mask |= POLLIN | POLLRDNORM;
3952         }
3953         if (file->f_flags & FMODE_WRITE) {
3954                 if (s->midi.ocnt < MIDIOUTBUF)
3955                         mask |= POLLOUT | POLLWRNORM;
3956         }
3957         spin_unlock_irqrestore(&s->lock, flags);
3958         return mask;
3959 }
3960
3961
3962 static int cs4281_midi_open(struct inode *inode, struct file *file)
3963 {
3964         unsigned long flags, temp1;
3965         unsigned int minor = iminor(inode);
3966         struct cs4281_state *s=NULL;
3967         struct list_head *entry;
3968         list_for_each(entry, &cs4281_devs)
3969         {
3970                 s = list_entry(entry, struct cs4281_state, list);
3971
3972                 if (s->dev_midi == minor)
3973                         break;
3974         }
3975
3976         if (entry == &cs4281_devs)
3977                 return -ENODEV;
3978         if (!s)
3979         {
3980                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3981                         "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3982                 return -ENODEV;
3983         }
3984         VALIDATE_STATE(s);
3985         file->private_data = s;
3986         // wait for device to become free
3987         down(&s->open_sem);
3988         while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
3989                 if (file->f_flags & O_NONBLOCK) {
3990                         up(&s->open_sem);
3991                         return -EBUSY;
3992                 }
3993                 up(&s->open_sem);
3994                 interruptible_sleep_on(&s->open_wait);
3995                 if (signal_pending(current))
3996                         return -ERESTARTSYS;
3997                 down(&s->open_sem);
3998         }
3999         spin_lock_irqsave(&s->lock, flags);
4000         if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4001                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4002                 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4003                 writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface.
4004                 writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode.
4005                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4006                 writel(0x0000000f, s->pBA0 + BA0_MIDCR);        // Enable transmit, record, ints.
4007                 temp1 = readl(s->pBA0 + BA0_HIMR);
4008                 writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition.
4009                 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts
4010                 init_timer(&s->midi.timer);
4011                 s->midi.timer.expires = jiffies + 1;
4012                 s->midi.timer.data = (unsigned long) s;
4013                 s->midi.timer.function = cs4281_midi_timer;
4014                 add_timer(&s->midi.timer);
4015         }
4016         if (file->f_mode & FMODE_READ) {
4017                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4018         }
4019         if (file->f_mode & FMODE_WRITE) {
4020                 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4021         }
4022         spin_unlock_irqrestore(&s->lock, flags);
4023         s->open_mode |=
4024             (file->
4025              f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ |
4026                                             FMODE_MIDI_WRITE);
4027         up(&s->open_sem);
4028         return 0;
4029 }
4030
4031
4032 static int cs4281_midi_release(struct inode *inode, struct file *file)
4033 {
4034         struct cs4281_state *s =
4035             (struct cs4281_state *) file->private_data;
4036         DECLARE_WAITQUEUE(wait, current);
4037         unsigned long flags;
4038         unsigned count, tmo;
4039
4040         VALIDATE_STATE(s);
4041
4042         if (file->f_mode & FMODE_WRITE) {
4043                 add_wait_queue(&s->midi.owait, &wait);
4044                 for (;;) {
4045                         set_current_state(TASK_INTERRUPTIBLE);
4046                         spin_lock_irqsave(&s->lock, flags);
4047                         count = s->midi.ocnt;
4048                         spin_unlock_irqrestore(&s->lock, flags);
4049                         if (count <= 0)
4050                                 break;
4051                         if (signal_pending(current))
4052                                 break;
4053                         if (file->f_flags & O_NONBLOCK) {
4054                                 remove_wait_queue(&s->midi.owait, &wait);
4055                                 current->state = TASK_RUNNING;
4056                                 return -EBUSY;
4057                         }
4058                         tmo = (count * HZ) / 3100;
4059                         if (!schedule_timeout(tmo ? : 1) && tmo)
4060                                 printk(KERN_DEBUG
4061                                        "cs4281: midi timed out??\n");
4062                 }
4063                 remove_wait_queue(&s->midi.owait, &wait);
4064                 current->state = TASK_RUNNING;
4065         }
4066         down(&s->open_sem);
4067         s->open_mode &=
4068             (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ |
4069                                                      FMODE_MIDI_WRITE);
4070         spin_lock_irqsave(&s->lock, flags);
4071         if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4072                 writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts.
4073                 del_timer(&s->midi.timer);
4074         }
4075         spin_unlock_irqrestore(&s->lock, flags);
4076         up(&s->open_sem);
4077         wake_up(&s->open_wait);
4078         return 0;
4079 }
4080
4081 // ******************************************************************************************
4082 //   Midi file operations struct.
4083 // ******************************************************************************************
4084 static /*const */ struct file_operations cs4281_midi_fops = {
4085         .owner   = THIS_MODULE,
4086         .llseek  = no_llseek,
4087         .read    = cs4281_midi_read,
4088         .write   = cs4281_midi_write,
4089         .poll    = cs4281_midi_poll,
4090         .open    = cs4281_midi_open,
4091         .release = cs4281_midi_release,
4092 };
4093
4094
4095 // ---------------------------------------------------------------------
4096
4097 // maximum number of devices
4098 #define NR_DEVICE 8             // Only eight devices supported currently.
4099
4100 // ---------------------------------------------------------------------
4101
4102 static struct initvol {
4103         int mixch;
4104         int vol;
4105 } initvol[] __initdata = {
4106
4107         {
4108         SOUND_MIXER_WRITE_VOLUME, 0x4040}, {
4109         SOUND_MIXER_WRITE_PCM, 0x4040}, {
4110         SOUND_MIXER_WRITE_SYNTH, 0x4040}, {
4111         SOUND_MIXER_WRITE_CD, 0x4040}, {
4112         SOUND_MIXER_WRITE_LINE, 0x4040}, {
4113         SOUND_MIXER_WRITE_LINE1, 0x4040}, {
4114         SOUND_MIXER_WRITE_RECLEV, 0x0000}, {
4115         SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {
4116         SOUND_MIXER_WRITE_MIC, 0x0000}
4117 };
4118
4119
4120 #ifndef NOT_CS4281_PM
4121 void __devinit cs4281_BuildFIFO(
4122         struct cs4281_pipeline *p,
4123         struct cs4281_state *s)
4124 {
4125         switch(p->number)
4126         {
4127                 case 0:  /* playback */
4128                 {
4129                         p->u32FCRnAddress  =  BA0_FCR0;
4130                         p->u32FSICnAddress = BA0_FSIC0;
4131                         p->u32FPDRnAddress = BA0_FPDR0;
4132                         break;
4133                 }
4134                 case 1:  /* capture */
4135                 {
4136                         p->u32FCRnAddress  =  BA0_FCR1;
4137                         p->u32FSICnAddress = BA0_FSIC1;
4138                         p->u32FPDRnAddress = BA0_FPDR1;
4139                         break;
4140                 }
4141
4142                 case 2:
4143                 {
4144                         p->u32FCRnAddress  =  BA0_FCR2;
4145                         p->u32FSICnAddress = BA0_FSIC2;
4146                         p->u32FPDRnAddress = BA0_FPDR2;
4147                         break;
4148                 }
4149                 case 3:
4150                 {
4151                         p->u32FCRnAddress  =  BA0_FCR3;
4152                         p->u32FSICnAddress = BA0_FSIC3;
4153                         p->u32FPDRnAddress = BA0_FPDR3;
4154                         break;
4155                 }
4156                 default:
4157                         break;
4158         }
4159         //
4160         // first read the hardware to initialize the member variables
4161         //
4162         p->u32FCRnValue = readl(s->pBA0 + p->u32FCRnAddress);
4163         p->u32FSICnValue = readl(s->pBA0 + p->u32FSICnAddress);
4164         p->u32FPDRnValue = readl(s->pBA0 + p->u32FPDRnAddress);
4165
4166 }
4167
4168 void __devinit cs4281_BuildDMAengine(
4169         struct cs4281_pipeline *p,
4170         struct cs4281_state *s)
4171 {
4172 /*
4173 * initialize all the addresses of this pipeline dma info.
4174 */
4175         switch(p->number)
4176         {
4177                 case 0:  /* playback */
4178                 {
4179                         p->u32DBAnAddress = BA0_DBA0;
4180                         p->u32DCAnAddress = BA0_DCA0;
4181                         p->u32DBCnAddress = BA0_DBC0;
4182                         p->u32DCCnAddress = BA0_DCC0;
4183                         p->u32DMRnAddress = BA0_DMR0;
4184                         p->u32DCRnAddress = BA0_DCR0;
4185                         p->u32HDSRnAddress = BA0_HDSR0;
4186                         break;
4187                 }
4188
4189                 case 1: /* capture */
4190                 {
4191                         p->u32DBAnAddress = BA0_DBA1;
4192                         p->u32DCAnAddress = BA0_DCA1;
4193                         p->u32DBCnAddress = BA0_DBC1;
4194                         p->u32DCCnAddress = BA0_DCC1;
4195                         p->u32DMRnAddress = BA0_DMR1;
4196                         p->u32DCRnAddress = BA0_DCR1;
4197                         p->u32HDSRnAddress = BA0_HDSR1;
4198                         break;
4199                 }
4200
4201                 case 2:
4202                 {
4203                         p->u32DBAnAddress = BA0_DBA2;
4204                         p->u32DCAnAddress = BA0_DCA2;
4205                         p->u32DBCnAddress = BA0_DBC2;
4206                         p->u32DCCnAddress = BA0_DCC2;
4207                         p->u32DMRnAddress = BA0_DMR2;
4208                         p->u32DCRnAddress = BA0_DCR2;
4209                         p->u32HDSRnAddress = BA0_HDSR2;
4210                         break;
4211                 }
4212
4213                 case 3:
4214                 {
4215                         p->u32DBAnAddress = BA0_DBA3;
4216                         p->u32DCAnAddress = BA0_DCA3;
4217                         p->u32DBCnAddress = BA0_DBC3;
4218                         p->u32DCCnAddress = BA0_DCC3;
4219                         p->u32DMRnAddress = BA0_DMR3;
4220                         p->u32DCRnAddress = BA0_DCR3;
4221                         p->u32HDSRnAddress = BA0_HDSR3;
4222                         break;
4223                 }
4224                 default:
4225                         break;
4226         }
4227
4228 //
4229 // Initialize the dma values for this pipeline
4230 //
4231         p->u32DBAnValue = readl(s->pBA0 + p->u32DBAnAddress);
4232         p->u32DBCnValue = readl(s->pBA0 + p->u32DBCnAddress);
4233         p->u32DMRnValue = readl(s->pBA0 + p->u32DMRnAddress);
4234         p->u32DCRnValue = readl(s->pBA0 + p->u32DCRnAddress);
4235
4236 }
4237
4238 void __devinit cs4281_InitPM(struct cs4281_state *s)
4239 {
4240         int i;
4241         struct cs4281_pipeline *p;
4242
4243         for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
4244         {
4245                 p = &s->pl[i];
4246                 p->number = i;
4247                 cs4281_BuildDMAengine(p,s);
4248                 cs4281_BuildFIFO(p,s);
4249         /*
4250         * currently only  2 pipelines are used
4251         * so, only set the valid bit on the playback and capture.
4252         */
4253                 if( (i == CS4281_PLAYBACK_PIPELINE_NUMBER) ||
4254                         (i == CS4281_CAPTURE_PIPELINE_NUMBER))
4255                         p->flags |= CS4281_PIPELINE_VALID;
4256         }
4257         s->pm.u32SSPM_BITS = 0x7e;  /* rev c, use 0x7c for rev a or b */
4258 }
4259 #endif
4260
4261 static int __devinit cs4281_probe(struct pci_dev *pcidev,
4262                                   const struct pci_device_id *pciid)
4263 {
4264 #ifndef NOT_CS4281_PM
4265         struct pm_dev *pmdev;
4266 #endif
4267         struct cs4281_state *s;
4268         dma_addr_t dma_mask;
4269         mm_segment_t fs;
4270         int i, val;
4271         unsigned int temp1, temp2;
4272
4273         CS_DBGOUT(CS_FUNCTION | CS_INIT, 2,
4274                   printk(KERN_INFO "cs4281: probe()+\n"));
4275
4276         if (pci_enable_device(pcidev)) {
4277                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4278                          "cs4281: pci_enable_device() failed\n"));
4279                 return -1;
4280         }
4281         if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM) ||
4282             !(pci_resource_flags(pcidev, 1) & IORESOURCE_MEM)) {
4283                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4284                          "cs4281: probe()- Memory region not assigned\n"));
4285                 return -ENODEV;
4286         }
4287         if (pcidev->irq == 0) {
4288                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4289                          "cs4281: probe() IRQ not assigned\n"));
4290                 return -ENODEV;
4291         }
4292         dma_mask = 0xffffffff;  /* this enables playback and recording */
4293         i = pci_set_dma_mask(pcidev, dma_mask);
4294         if (i) {
4295                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4296                       "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n"));
4297                 return i;
4298         }
4299         if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
4300                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4301                       "cs4281: probe() no memory for state struct.\n"));
4302                 return -1;
4303         }
4304         memset(s, 0, sizeof(struct cs4281_state));
4305         init_waitqueue_head(&s->dma_adc.wait);
4306         init_waitqueue_head(&s->dma_dac.wait);
4307         init_waitqueue_head(&s->open_wait);
4308         init_waitqueue_head(&s->open_wait_adc);
4309         init_waitqueue_head(&s->open_wait_dac);
4310         init_waitqueue_head(&s->midi.iwait);
4311         init_waitqueue_head(&s->midi.owait);
4312         init_MUTEX(&s->open_sem);
4313         init_MUTEX(&s->open_sem_adc);
4314         init_MUTEX(&s->open_sem_dac);
4315         spin_lock_init(&s->lock);
4316         s->pBA0phys = pci_resource_start(pcidev, 0);
4317         s->pBA1phys = pci_resource_start(pcidev, 1);
4318
4319         /* Convert phys to linear. */
4320         s->pBA0 = ioremap_nocache(s->pBA0phys, 4096);
4321         if (!s->pBA0) {
4322                 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4323                          "cs4281: BA0 I/O mapping failed. Skipping part.\n"));
4324                 goto err_free;
4325         }
4326         s->pBA1 = ioremap_nocache(s->pBA1phys, 65536);
4327         if (!s->pBA1) {
4328                 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4329                          "cs4281: BA1 I/O mapping failed. Skipping part.\n"));
4330                 goto err_unmap;
4331         }
4332
4333         temp1 = readl(s->pBA0 + BA0_PCICFG00);
4334         temp2 = readl(s->pBA0 + BA0_PCICFG04);
4335
4336         CS_DBGOUT(CS_INIT, 2,
4337                   printk(KERN_INFO
4338                          "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=%p pBA1=%p \n",
4339                          (unsigned) temp1, (unsigned) temp2, s->pBA0, s->pBA1));
4340         CS_DBGOUT(CS_INIT, 2,
4341                   printk(KERN_INFO
4342                          "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n",
4343                          (unsigned) s->pBA0phys, (unsigned) s->pBA1phys));
4344
4345 #ifndef NOT_CS4281_PM
4346         s->pm.flags = CS4281_PM_IDLE;
4347 #endif
4348         temp1 = cs4281_hw_init(s);
4349         if (temp1) {
4350                 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4351                          "cs4281: cs4281_hw_init() failed. Skipping part.\n"));
4352                 goto err_irq;
4353         }
4354         s->magic = CS4281_MAGIC;
4355         s->pcidev = pcidev;
4356         s->irq = pcidev->irq;
4357         if (request_irq
4358             (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) {
4359                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
4360                           printk(KERN_ERR "cs4281: irq %u in use\n", s->irq));
4361                 goto err_irq;
4362         }
4363         if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) <
4364             0) {
4365                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4366                          "cs4281: probe() register_sound_dsp() failed.\n"));
4367                 goto err_dev1;
4368         }
4369         if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) <
4370             0) {
4371                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4372                          "cs4281: probe() register_sound_mixer() failed.\n"));
4373                 goto err_dev2;
4374         }
4375         if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) {
4376                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4377                          "cs4281: probe() register_sound_midi() failed.\n"));
4378                 goto err_dev3;
4379         }
4380 #ifndef NOT_CS4281_PM
4381         cs4281_InitPM(s);
4382         pmdev = cs_pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev), cs4281_pm_callback);
4383         if (pmdev)
4384         {
4385                 CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO
4386                          "cs4281: probe() pm_register() succeeded (%p).\n", pmdev));
4387                 pmdev->data = s;
4388         }
4389         else
4390         {
4391                 CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO
4392                          "cs4281: probe() pm_register() failed (%p).\n", pmdev));
4393                 s->pm.flags |= CS4281_PM_NOT_REGISTERED;
4394         }
4395 #endif
4396
4397         pci_set_master(pcidev); // enable bus mastering
4398
4399         fs = get_fs();
4400         set_fs(KERNEL_DS);
4401         val = SOUND_MASK_LINE;
4402         mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
4403         for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
4404                 val = initvol[i].vol;
4405                 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
4406         }
4407         val = 1;                // enable mic preamp
4408         mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val);
4409         set_fs(fs);
4410
4411         pci_set_drvdata(pcidev, s);
4412         list_add(&s->list, &cs4281_devs);
4413         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4414                 "cs4281: probe()- device allocated successfully\n"));
4415         return 0;
4416
4417       err_dev3:
4418         unregister_sound_mixer(s->dev_mixer);
4419       err_dev2:
4420         unregister_sound_dsp(s->dev_audio);
4421       err_dev1:
4422         free_irq(s->irq, s);
4423       err_irq:
4424         iounmap(s->pBA1);
4425       err_unmap:
4426         iounmap(s->pBA0);
4427       err_free:
4428         kfree(s);
4429
4430         CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
4431                 "cs4281: probe()- no device allocated\n"));
4432         return -ENODEV;
4433 } // probe_cs4281
4434
4435
4436 // ---------------------------------------------------------------------
4437
4438 static void __devexit cs4281_remove(struct pci_dev *pci_dev)
4439 {
4440         struct cs4281_state *s = pci_get_drvdata(pci_dev);
4441         // stop DMA controller
4442         synchronize_irq(s->irq);
4443         free_irq(s->irq, s);
4444         unregister_sound_dsp(s->dev_audio);
4445         unregister_sound_mixer(s->dev_mixer);
4446         unregister_sound_midi(s->dev_midi);
4447         iounmap(s->pBA1);
4448         iounmap(s->pBA0);
4449         pci_set_drvdata(pci_dev,NULL);
4450         list_del(&s->list);
4451         kfree(s);
4452         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4453                  "cs4281: cs4281_remove()-: remove successful\n"));
4454 }
4455
4456 static struct pci_device_id cs4281_pci_tbl[] = {
4457         {
4458                 .vendor    = PCI_VENDOR_ID_CIRRUS,
4459                 .device    = PCI_DEVICE_ID_CRYSTAL_CS4281,
4460                 .subvendor = PCI_ANY_ID,
4461                 .subdevice = PCI_ANY_ID,
4462         },
4463         { 0, },
4464 };
4465
4466 MODULE_DEVICE_TABLE(pci, cs4281_pci_tbl);
4467
4468 struct pci_driver cs4281_pci_driver = {
4469         .name     = "cs4281",
4470         .id_table = cs4281_pci_tbl,
4471         .probe    = cs4281_probe,
4472         .remove   = __devexit_p(cs4281_remove),
4473         .suspend  = CS4281_SUSPEND_TBL,
4474         .resume   = CS4281_RESUME_TBL,
4475 };
4476
4477 int __init cs4281_init_module(void)
4478 {
4479         int rtn = 0;
4480         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4481                 "cs4281: cs4281_init_module()+ \n"));
4482         printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " "
4483                __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION,
4484                CS4281_ARCH);
4485         rtn = pci_module_init(&cs4281_pci_driver);
4486
4487         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4488                   printk(KERN_INFO "cs4281: cs4281_init_module()- (%d)\n",rtn));
4489         return rtn;
4490 }
4491
4492 void __exit cs4281_cleanup_module(void)
4493 {
4494         pci_unregister_driver(&cs4281_pci_driver);
4495 #ifndef NOT_CS4281_PM
4496         cs_pm_unregister_all(cs4281_pm_callback);
4497 #endif
4498         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4499                   printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n"));
4500 }
4501 // ---------------------------------------------------------------------
4502
4503 MODULE_AUTHOR("gw boynton, audio@crystal.cirrus.com");
4504 MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
4505 MODULE_LICENSE("GPL");
4506
4507 // ---------------------------------------------------------------------
4508
4509 module_init(cs4281_init_module);
4510 module_exit(cs4281_cleanup_module);
4511
4512 #ifndef MODULE
4513 int __init init_cs4281(void)
4514 {
4515         return cs4281_init_module();
4516 }
4517 #endif