sound/oss/emu10k1/hwaccess.c

   1 /*
   2  **********************************************************************
   3  *     hwaccess.c -- Hardware access layer
   4  *     Copyright 1999, 2000 Creative Labs, Inc.
   5  *
   6  **********************************************************************
   7  *
   8  *     Date                 Author          Summary of changes
   9  *     ----                 ------          ------------------
  10  *     October 20, 1999     Bertrand Lee    base code release
  11  *     December 9, 1999     Jon Taylor      rewrote the I/O subsystem
  12  *
  13  **********************************************************************
  14  *
  15  *     This program is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of
  18  *     the License, or (at your option) any later version.
  19  *
  20  *     This program is distributed in the hope that it will be useful,
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  *     You should have received a copy of the GNU General Public
  26  *     License along with this program; if not, write to the Free
  27  *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
  28  *     USA.
  29  *
  30  **********************************************************************
  31  */
  32
  33 #include <asm/io.h>
  34
  35 #include "hwaccess.h"
  36 #include "8010.h"
  37 #include "icardmid.h"
  38
  39 /*************************************************************************
  40 * Function : srToPitch                                                   *
  41 * Input    : sampleRate - sampling rate                                  *
  42 * Return   : pitch value                                                 *
  43 * About    : convert sampling rate to pitch                              *
  44 * Note     : for 8010, sampling rate is at 48kHz, this function should   *
  45 *            be changed.                                                 *
  46 *************************************************************************/
  47 u32 srToPitch(u32 sampleRate)
  48 {
  49         int i;
  50
  51         /* FIXME: These tables should be defined in a headerfile */
  52         static u32 logMagTable[128] = {
  53                 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
  54                 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
  55                 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
  56                 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
  57                 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
  58                 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
  59                 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
  60                 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
  61                 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
  62                 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
  63                 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
  64                 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
  65                 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
  66                 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
  67                 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
  68                 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
  69         };
  70
  71         static char logSlopeTable[128] = {
  72                 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
  73                 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
  74                 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
  75                 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
  76                 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
  77                 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
  78                 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
  79                 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
  80                 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
  81                 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
  82                 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
  83                 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
  84                 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
  85                 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
  86                 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
  87                 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
  88         };
  89
  90         if (sampleRate == 0)
  91                 return 0;       /* Bail out if no leading "1" */
  92
  93         sampleRate *= 11185;    /* Scale 48000 to 0x20002380 */
  94
  95         for (i = 31; i > 0; i--) {
  96                 if (sampleRate & 0x80000000) {  /* Detect leading "1" */
  97                         return (u32) (((s32) (i - 15) << 20) +
  98                                       logMagTable[0x7f & (sampleRate >> 24)] +
  99                                       (0x7f & (sampleRate >> 17)) * logSlopeTable[0x7f & (sampleRate >> 24)]);
 100                 }
 101                 sampleRate = sampleRate << 1;
 102         }
 103
 104         DPF(2, "srToPitch: BUG!\n");
 105         return 0;               /* Should never reach this point */
 106 }
 107
 108 /* Returns an attenuation based upon a cumulative volume value */
 109
 110 /* Algorithm calculates 0x200 - 0x10 log2 (input) */
 111 u8 sumVolumeToAttenuation(u32 value)
 112 {
 113         u16 count = 16;
 114         s16 ans;
 115
 116         if (value == 0)
 117                 return 0xFF;
 118
 119         /* Find first SET bit. This is the integer part of the value */
 120         while ((value & 0x10000) == 0) {
 121                 value <<= 1;
 122                 count--;
 123         }
 124
 125         /* The REST of the data is the fractional part. */
 126         ans = (s16) (0x110 - ((count << 4) + ((value & 0x0FFFFL) >> 12)));
 127         if (ans > 0xFF)
 128                 ans = 0xFF;
 129
 130         return (u8) ans;
 131 }
 132
 133 /*******************************************
 134 * write/read PCI function 0 registers      *
 135 ********************************************/
 136 void emu10k1_writefn0(struct emu10k1_card *card, u32 reg, u32 data)
 137 {
 138         unsigned long flags;
 139
 140         if (reg & 0xff000000) {
 141                 u32 mask;
 142                 u8 size, offset;
 143
 144                 size = (reg >> 24) & 0x3f;
 145                 offset = (reg >> 16) & 0x1f;
 146                 mask = ((1 << size) - 1) << offset;
 147                 data = (data << offset) & mask;
 148                 reg &= 0x7f;
 149
 150                 spin_lock_irqsave(&card->lock, flags);
 151                 data |= inl(card->iobase + reg) & ~mask;
 152                 outl(data, card->iobase + reg);
 153                 spin_unlock_irqrestore(&card->lock, flags);
 154         } else {
 155                 spin_lock_irqsave(&card->lock, flags);
 156                 outl(data, card->iobase + reg);
 157                 spin_unlock_irqrestore(&card->lock, flags);
 158         }
 159
 160         return;
 161 }
 162
 163 void emu10k1_writefn0_2(struct emu10k1_card *card, u32 reg, u32 data, int size)
 164 {
 165         unsigned long flags;
 166
 167         spin_lock_irqsave(&card->lock, flags);
 168
 169         if (size == 32)
 170                 outl(data, card->iobase + (reg & 0x1F));
 171         else if (size == 16)
 172                 outw(data, card->iobase + (reg & 0x1F));
 173         else
 174                 outb(data, card->iobase + (reg & 0x1F));
 175
 176         spin_unlock_irqrestore(&card->lock, flags);
 177
 178         return;
 179 }
 180
 181 u32 emu10k1_readfn0(struct emu10k1_card * card, u32 reg)
 182 {
 183         u32 val;
 184         unsigned long flags;
 185
 186         if (reg & 0xff000000) {
 187                 u32 mask;
 188                 u8 size, offset;
 189
 190                 size = (reg >> 24) & 0x3f;
 191                 offset = (reg >> 16) & 0x1f;
 192                 mask = ((1 << size) - 1) << offset;
 193                 reg &= 0x7f;
 194
 195                 spin_lock_irqsave(&card->lock, flags);
 196                 val = inl(card->iobase + reg);
 197                 spin_unlock_irqrestore(&card->lock, flags);
 198
 199                 return (val & mask) >> offset;
 200         } else {
 201                 spin_lock_irqsave(&card->lock, flags);
 202                 val = inl(card->iobase + reg);
 203                 spin_unlock_irqrestore(&card->lock, flags);
 204                 return val;
 205         }
 206 }
 207
 208 void emu10k1_timer_set(struct emu10k1_card * card, u16 data)
 209 {
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&card->lock, flags);
 213         outw(data & TIMER_RATE_MASK, card->iobase + TIMER);
 214         spin_unlock_irqrestore(&card->lock, flags);
 215 }
 216
 217 /************************************************************************
 218 * write/read Emu10k1 pointer-offset register set, accessed through      *
 219 *  the PTR and DATA registers                                           *
 220 *************************************************************************/
 221 #define A_PTR_ADDRESS_MASK 0x0fff0000
 222 void sblive_writeptr(struct emu10k1_card *card, u32 reg, u32 channel, u32 data)
 223 {
 224         u32 regptr;
 225         unsigned long flags;
 226
 227         regptr = ((reg << 16) & A_PTR_ADDRESS_MASK) | (channel & PTR_CHANNELNUM_MASK);
 228
 229         if (reg & 0xff000000) {
 230                 u32 mask;
 231                 u8 size, offset;
 232
 233                 size = (reg >> 24) & 0x3f;
 234                 offset = (reg >> 16) & 0x1f;
 235                 mask = ((1 << size) - 1) << offset;
 236                 data = (data << offset) & mask;
 237
 238                 spin_lock_irqsave(&card->lock, flags);
 239                 outl(regptr, card->iobase + PTR);
 240                 data |= inl(card->iobase + DATA) & ~mask;
 241                 outl(data, card->iobase + DATA);
 242                 spin_unlock_irqrestore(&card->lock, flags);
 243         } else {
 244                 spin_lock_irqsave(&card->lock, flags);
 245                 outl(regptr, card->iobase + PTR);
 246                 outl(data, card->iobase + DATA);
 247                 spin_unlock_irqrestore(&card->lock, flags);
 248         }
 249 }
 250
 251 /* ... :  data, reg, ... , TAGLIST_END */
 252 void sblive_writeptr_tag(struct emu10k1_card *card, u32 channel, ...)
 253 {
 254         va_list args;
 255
 256         unsigned long flags;
 257         u32 reg;
 258
 259         va_start(args, channel);
 260
 261         spin_lock_irqsave(&card->lock, flags);
 262         while ((reg = va_arg(args, u32)) != TAGLIST_END) {
 263                 u32 data = va_arg(args, u32);
 264                 u32 regptr = (((reg << 16) & A_PTR_ADDRESS_MASK)
 265                               | (channel & PTR_CHANNELNUM_MASK));
 266                 outl(regptr, card->iobase + PTR);
 267                 if (reg & 0xff000000) {
 268                         int size = (reg >> 24) & 0x3f;
 269                         int offset = (reg >> 16) & 0x1f;
 270                         u32 mask = ((1 << size) - 1) << offset;
 271                         data = (data << offset) & mask;
 272
 273                         data |= inl(card->iobase + DATA) & ~mask;
 274                 }
 275                 outl(data, card->iobase + DATA);
 276         }
 277         spin_unlock_irqrestore(&card->lock, flags);
 278
 279         va_end(args);
 280
 281         return;
 282 }
 283
 284 u32 sblive_readptr(struct emu10k1_card * card, u32 reg, u32 channel)
 285 {
 286         u32 regptr, val;
 287         unsigned long flags;
 288
 289         regptr = ((reg << 16) & A_PTR_ADDRESS_MASK) | (channel & PTR_CHANNELNUM_MASK);
 290
 291         if (reg & 0xff000000) {
 292                 u32 mask;
 293                 u8 size, offset;
 294
 295                 size = (reg >> 24) & 0x3f;
 296                 offset = (reg >> 16) & 0x1f;
 297                 mask = ((1 << size) - 1) << offset;
 298
 299                 spin_lock_irqsave(&card->lock, flags);
 300                 outl(regptr, card->iobase + PTR);
 301                 val = inl(card->iobase + DATA);
 302                 spin_unlock_irqrestore(&card->lock, flags);
 303
 304                 return (val & mask) >> offset;
 305         } else {
 306                 spin_lock_irqsave(&card->lock, flags);
 307                 outl(regptr, card->iobase + PTR);
 308                 val = inl(card->iobase + DATA);
 309                 spin_unlock_irqrestore(&card->lock, flags);
 310
 311                 return val;
 312         }
 313 }
 314
 315 void emu10k1_irq_enable(struct emu10k1_card *card, u32 irq_mask)
 316 {
 317         u32 val;
 318         unsigned long flags;
 319
 320         DPF(2,"emu10k1_irq_enable()\n");
 321
 322         spin_lock_irqsave(&card->lock, flags);
 323         val = inl(card->iobase + INTE) | irq_mask;
 324         outl(val, card->iobase + INTE);
 325         spin_unlock_irqrestore(&card->lock, flags);
 326         return;
 327 }
 328
 329 void emu10k1_irq_disable(struct emu10k1_card *card, u32 irq_mask)
 330 {
 331         u32 val;
 332         unsigned long flags;
 333
 334         DPF(2,"emu10k1_irq_disable()\n");
 335
 336         spin_lock_irqsave(&card->lock, flags);
 337         val = inl(card->iobase + INTE) & ~irq_mask;
 338         outl(val, card->iobase + INTE);
 339         spin_unlock_irqrestore(&card->lock, flags);
 340         return;
 341 }
 342
 343 void emu10k1_set_stop_on_loop(struct emu10k1_card *card, u32 voicenum)
 344 {
 345         /* Voice interrupt */
 346         if (voicenum >= 32)
 347                 sblive_writeptr(card, SOLEH | ((0x0100 | (voicenum - 32)) << 16), 0, 1);
 348         else
 349                 sblive_writeptr(card, SOLEL | ((0x0100 | voicenum) << 16), 0, 1);
 350
 351         return;
 352 }
 353
 354 void emu10k1_clear_stop_on_loop(struct emu10k1_card *card, u32 voicenum)
 355 {
 356         /* Voice interrupt */
 357         if (voicenum >= 32)
 358                 sblive_writeptr(card, SOLEH | ((0x0100 | (voicenum - 32)) << 16), 0, 0);
 359         else
 360                 sblive_writeptr(card, SOLEL | ((0x0100 | voicenum) << 16), 0, 0);
 361
 362         return;
 363 }
 364
 365 static void sblive_wcwait(struct emu10k1_card *card, u32 wait)
 366 {
 367         volatile unsigned uCount;
 368         u32 newtime = 0, curtime;
 369
 370         curtime = emu10k1_readfn0(card, WC_SAMPLECOUNTER);
 371         while (wait--) {
 372                 uCount = 0;
 373                 while (uCount++ < TIMEOUT) {
 374                         newtime = emu10k1_readfn0(card, WC_SAMPLECOUNTER);
 375                         if (newtime != curtime)
 376                                 break;
 377                 }
 378
 379                 if (uCount >= TIMEOUT)
 380                         break;
 381
 382                 curtime = newtime;
 383         }
 384 }
 385
 386 u16 emu10k1_ac97_read(struct ac97_codec *codec, u8 reg)
 387 {
 388         struct emu10k1_card *card = codec->private_data;
 389         u16 data;
 390         unsigned long flags;
 391
 392         spin_lock_irqsave(&card->lock, flags);
 393
 394         outb(reg, card->iobase + AC97ADDRESS);
 395         data = inw(card->iobase + AC97DATA);
 396
 397         spin_unlock_irqrestore(&card->lock, flags);
 398
 399         return data;
 400 }
 401
 402 void emu10k1_ac97_write(struct ac97_codec *codec, u8 reg, u16 value)
 403 {
 404         struct emu10k1_card *card = codec->private_data;
 405         unsigned long flags;
 406
 407         spin_lock_irqsave(&card->lock, flags);
 408
 409         outb(reg, card->iobase + AC97ADDRESS);
 410         outw(value, card->iobase + AC97DATA);
 411         outb( AC97_EXTENDED_ID, card->iobase + AC97ADDRESS);
 412         spin_unlock_irqrestore(&card->lock, flags);
 413 }
 414
 415 /*********************************************************
 416 *            MPU access functions                        *
 417 **********************************************************/
 418
 419 int emu10k1_mpu_write_data(struct emu10k1_card *card, u8 data)
 420 {
 421         unsigned long flags;
 422         int ret;
 423
 424         if (card->is_audigy) {
 425                 if ((sblive_readptr(card, A_MUSTAT,0) & MUSTAT_ORDYN) == 0) {
 426                         sblive_writeptr(card, A_MUDATA, 0, data);
 427                         ret = 0;
 428                 } else
 429                         ret = -1;
 430         } else {
 431                 spin_lock_irqsave(&card->lock, flags);
 432
 433                 if ((inb(card->iobase + MUSTAT) & MUSTAT_ORDYN) == 0) {
 434                         outb(data, card->iobase + MUDATA);
 435                         ret = 0;
 436                 } else
 437                         ret = -1;
 438
 439                 spin_unlock_irqrestore(&card->lock, flags);
 440         }
 441
 442         return ret;
 443 }
 444
 445 int emu10k1_mpu_read_data(struct emu10k1_card *card, u8 * data)
 446 {
 447         unsigned long flags;
 448         int ret;
 449
 450         if (card->is_audigy) {
 451                 if ((sblive_readptr(card, A_MUSTAT,0) & MUSTAT_IRDYN) == 0) {
 452                         *data = sblive_readptr(card, A_MUDATA,0);
 453                         ret = 0;
 454                 } else
 455                         ret = -1;
 456         } else {
 457                 spin_lock_irqsave(&card->lock, flags);
 458
 459                 if ((inb(card->iobase + MUSTAT) & MUSTAT_IRDYN) == 0) {
 460                         *data = inb(card->iobase + MUDATA);
 461                         ret = 0;
 462                 } else
 463                         ret = -1;
 464
 465                 spin_unlock_irqrestore(&card->lock, flags);
 466         }
 467
 468         return ret;
 469 }
 470
 471 int emu10k1_mpu_reset(struct emu10k1_card *card)
 472 {
 473         u8 status;
 474         unsigned long flags;
 475
 476         DPF(2, "emu10k1_mpu_reset()\n");
 477         if (card->is_audigy) {
 478                 if (card->mpuacqcount == 0) {
 479                         sblive_writeptr(card, A_MUCMD, 0, MUCMD_RESET);
 480                         sblive_wcwait(card, 8);
 481                         sblive_writeptr(card, A_MUCMD, 0, MUCMD_RESET);
 482                         sblive_wcwait(card, 8);
 483                         sblive_writeptr(card, A_MUCMD, 0, MUCMD_ENTERUARTMODE);
 484                         sblive_wcwait(card, 8);
 485                         status = sblive_readptr(card, A_MUDATA, 0);
 486                         if (status == 0xfe)
 487                                 return 0;
 488                         else
 489                                 return -1;
 490                 }
 491
 492                 return 0;
 493         } else {
 494                 if (card->mpuacqcount == 0) {
 495                         spin_lock_irqsave(&card->lock, flags);
 496                         outb(MUCMD_RESET, card->iobase + MUCMD);
 497                         spin_unlock_irqrestore(&card->lock, flags);
 498
 499                         sblive_wcwait(card, 8);
 500
 501                         spin_lock_irqsave(&card->lock, flags);
 502                         outb(MUCMD_RESET, card->iobase + MUCMD);
 503                         spin_unlock_irqrestore(&card->lock, flags);
 504
 505                         sblive_wcwait(card, 8);
 506
 507                         spin_lock_irqsave(&card->lock, flags);
 508                         outb(MUCMD_ENTERUARTMODE, card->iobase + MUCMD);
 509                         spin_unlock_irqrestore(&card->lock, flags);
 510
 511                         sblive_wcwait(card, 8);
 512
 513                         spin_lock_irqsave(&card->lock, flags);
 514                         status = inb(card->iobase + MUDATA);
 515                         spin_unlock_irqrestore(&card->lock, flags);
 516
 517                         if (status == 0xfe)
 518                                 return 0;
 519                         else
 520                                 return -1;
 521                 }
 522
 523                 return 0;
 524         }
 525 }
 526
 527 int emu10k1_mpu_acquire(struct emu10k1_card *card)
 528 {
 529         /* FIXME: This should be a macro */
 530         ++card->mpuacqcount;
 531
 532         return 0;
 533 }
 534
 535 int emu10k1_mpu_release(struct emu10k1_card *card)
 536 {
 537         /* FIXME: this should be a macro */
 538         --card->mpuacqcount;
 539
 540         return 0;
 541 }